545 lines
21 KiB
C
545 lines
21 KiB
C
/*
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* -------------------------------------------
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* MSP432 DriverLib - v3_40_00_10
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* -------------------------------------------
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*
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* --COPYRIGHT--,BSD,BSD
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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#ifndef __SYSCTL_H__
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#define __SYSCTL_H__
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//*****************************************************************************
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//
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//! \addtogroup sysctl_api
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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#include <msp.h>
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//*****************************************************************************
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//
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// Control specific variables
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//
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//*****************************************************************************
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#define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
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#define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
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#define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
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#define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
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#define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
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#define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
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#define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
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#define SYSCTL_HARD_RESET 1
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#define SYSCTL_SOFT_RESET 0
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#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
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#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
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#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
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#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
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#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
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#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
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#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
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#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
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#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
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#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
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#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
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#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
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#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
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#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
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#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
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#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
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#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
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#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
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#define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
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#define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
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#define SYSCTL_REBOOT_KEY 0x6900
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#define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
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#define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
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#define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
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#define SYSCTL_85_DEGREES_C 4
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#define SYSCTL_30_DEGREES_C 0
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#define TLV_START 0x00201004
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#define TLV_TAG_RESERVED1 1
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#define TLV_TAG_RESERVED2 2
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#define TLV_TAG_CS 3
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#define TLV_TAG_FLASHCTL 4
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#define TLV_TAG_ADC14 5
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#define TLV_TAG_RESERVED6 6
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#define TLV_TAG_RESERVED7 7
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#define TLV_TAG_REF 8
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#define TLV_TAG_RESERVED9 9
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#define TLV_TAG_RESERVED10 10
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#define TLV_TAG_DEVINFO 11
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#define TLV_TAG_DIEREC 12
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#define TLV_TAG_RANDNUM 13
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#define TLV_TAG_RESERVED14 14
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#define TLV_TAG_BSL 15
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#define TLV_TAGEND 0x0BD0E11D
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//*****************************************************************************
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//
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// Structures for TLV definitions
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//
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//*****************************************************************************
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typedef struct
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{
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uint32_t maxProgramPulses;
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uint32_t maxErasePulses;
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} SysCtl_FlashTLV_Info;
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typedef struct
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{
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uint32_t rDCOIR_FCAL_RSEL04;
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uint32_t rDCOIR_FCAL_RSEL5;
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uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
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uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
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uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
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uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
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uint32_t rDCOIR_CONSTK_RSEL04;
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uint32_t rDCOIR_CONSTK_RSEL5;
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uint32_t rDCOER_FCAL_RSEL04;
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uint32_t rDCOER_FCAL_RSEL5;
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uint32_t rDCOER_MAXPOSTUNE_RSEL04;
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uint32_t rDCOER_MAXNEGTUNE_RSEL04;
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uint32_t rDCOER_MAXPOSTUNE_RSEL5;
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uint32_t rDCOER_MAXNEGTUNE_RSEL5;
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uint32_t rDCOER_CONSTK_RSEL04;
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uint32_t rDCOER_CONSTK_RSEL5;
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} SysCtl_CSCalTLV_Info;
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//*****************************************************************************
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//
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// Prototypes for the APIs.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! Gets the size of the SRAM.
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//!
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//! \return The total number of bytes of SRAM.
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//
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//*****************************************************************************
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extern uint_least32_t SysCtl_getSRAMSize(void);
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//*****************************************************************************
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//
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//! Gets the size of the flash.
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//!
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//! \return The total number of bytes of flash.
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//
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//*****************************************************************************
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extern uint_least32_t SysCtl_getFlashSize(void);
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//*****************************************************************************
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//
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//! Reboots the device and causes the device to re-initialize itself.
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//!
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//! \return This function does not return.
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//
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//*****************************************************************************
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extern void SysCtl_rebootDevice(void);
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//*****************************************************************************
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//
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//! The TLV structure uses a tag or base address to identify segments of the
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//! table where information is stored. Some examples of TLV tags are Peripheral
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//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
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//! the value of a tag and the length of the tag.
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//!
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//! \param tag represents the tag for which the information needs to be
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//! retrieved.
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//! Valid values are:
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//! - \b TLV_TAG_RESERVED1
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//! - \b TLV_TAG_RESERVED2
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//! - \b TLV_TAG_CS
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//! - \b TLV_TAG_FLASHCTL
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//! - \b TLV_TAG_ADC14
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//! - \b TLV_TAG_RESERVED6
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//! - \b TLV_TAG_RESERVED7
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//! - \b TLV_TAG_REF
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//! - \b TLV_TAG_RESERVED9
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//! - \b TLV_TAG_RESERVED10
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//! - \b TLV_TAG_DEVINFO
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//! - \b TLV_TAG_DIEREC
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//! - \b TLV_TAG_RANDNUM
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//! - \b TLV_TAG_RESERVED14
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//! \param instance In some cases a specific tag may have more than one
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//! instance. For example there may be multiple instances of timer
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//! calibration data present under a single Timer Cal tag. This variable
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//! specifies the instance for which information is to be retrieved (0,
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//! 1, etc.). When only one instance exists; 0 is passed.
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//! \param length Acts as a return through indirect reference. The function
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//! retrieves the value of the TLV tag length. This value is pointed to
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//! by *length and can be used by the application level once the
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//! function is called. If the specified tag is not found then the
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//! pointer is null 0.
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//! \param data_address acts as a return through indirect reference. Once the
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//! function is called data_address points to the pointer that holds the
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//! value retrieved from the specified TLV tag. If the specified tag is
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//! not found then the pointer is null 0.
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//!
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//! \return None
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//
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//*****************************************************************************
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extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
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uint_fast8_t *length, uint32_t **data_address);
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//*****************************************************************************
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//
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//! Enables a set of banks in the SRAM. This can be used to optimize power
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//! consumption when every SRAM bank isn't needed. It is important to note
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//! that when a higher bank is enabled, all of the SRAM banks below that bank
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//! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7,
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//! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled
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//! (SRAM_BANK0 is reserved and always enabled).
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//!
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//! \param sramBank The SRAM bank tier to enable.
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//! Must be only one of the following values:
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//! - \b SYSCTL_SRAM_BANK1,
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//! - \b SYSCTL_SRAM_BANK2,
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//! - \b SYSCTL_SRAM_BANK3,
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//! - \b SYSCTL_SRAM_BANK4,
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//! - \b SYSCTL_SRAM_BANK5,
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//! - \b SYSCTL_SRAM_BANK6,
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//! - \b SYSCTL_SRAM_BANK7
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//!
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//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
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//!
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//! \return None.
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//
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//*****************************************************************************
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extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
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//*****************************************************************************
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//
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//! Disables a set of banks in the SRAM. This can be used to optimize power
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//! consumption when every SRAM bank isn't needed. It is important to note
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//! that when a higher bank is disabled, all of the SRAM banks above that bank
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//! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5,
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//! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled.
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//!
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//! \param sramBank The SRAM bank tier to disable.
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//! Must be only one of the following values:
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//! - \b SYSCTL_SRAM_BANK1,
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//! - \b SYSCTL_SRAM_BANK2,
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//! - \b SYSCTL_SRAM_BANK3,
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//! - \b SYSCTL_SRAM_BANK4,
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//! - \b SYSCTL_SRAM_BANK5,
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//! - \b SYSCTL_SRAM_BANK6,
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//! - \b SYSCTL_SRAM_BANK7
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//!
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//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
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//!
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//! \return None.
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//
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//*****************************************************************************
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extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
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//*****************************************************************************
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//
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//! Enables retention of the specified SRAM bank register when the device goes
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//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
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//! banks specified with this function will be placed into retention mode. By
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//! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is
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//! disabled. Retention of individual banks can be set without the restrictions
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//! of the enable/disable functions.
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//!
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//! \param sramBank The SRAM banks to enable retention
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//! Can be a bitwise OR of the following values:
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//! - \b SYSCTL_SRAM_BANK1,
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//! - \b SYSCTL_SRAM_BANK2,
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//! - \b SYSCTL_SRAM_BANK3,
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//! - \b SYSCTL_SRAM_BANK4,
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//! - \b SYSCTL_SRAM_BANK5,
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//! - \b SYSCTL_SRAM_BANK6,
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//! - \b SYSCTL_SRAM_BANK7
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//! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
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//!
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//!
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//! \return None.
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//
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//*****************************************************************************
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extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
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//*****************************************************************************
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//
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//! Disables retention of the specified SRAM bank register when the device goes
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//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
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//! banks specified with this function will not be placed into retention mode.
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//! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved)
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//! is disabled. Retention of individual banks can be set without the
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//! restrictions of the enable/disable SRAM bank functions.
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//!
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//! \param sramBank The SRAM banks to disable retention
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//! Can be a bitwise OR of the following values:
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//! - \b SYSCTL_SRAM_BANK1,
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//! - \b SYSCTL_SRAM_BANK2,
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//! - \b SYSCTL_SRAM_BANK3,
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//! - \b SYSCTL_SRAM_BANK4,
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//! - \b SYSCTL_SRAM_BANK5,
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//! - \b SYSCTL_SRAM_BANK6,
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//! - \b SYSCTL_SRAM_BANK7
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//! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
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//!
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//! \return None.
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//
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//
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//*****************************************************************************
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extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
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//*****************************************************************************
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//
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//! Makes it so that the provided peripherals will either halt execution after
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//! a CPU HALT. Parameters in this function can be combined to account for
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//! multiple peripherals. By default, all peripherals keep running after a
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//! CPU HALT.
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//!
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//! \param devices The peripherals to continue running after a CPU HALT
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//! This can be a bitwise OR of the following values:
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//! - \b SYSCTL_PERIPH_DMA,
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//! - \b SYSCTL_PERIPH_WDT,
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//! - \b SYSCTL_PERIPH_ADC,
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//! - \b SYSCTL_PERIPH_EUSCIB3,
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//! - \b SYSCTL_PERIPH_EUSCIB2,
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//! - \b SYSCTL_PERIPH_EUSCIB1
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//! - \b SYSCTL_PERIPH_EUSCIB0,
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//! - \b SYSCTL_PERIPH_EUSCIA3,
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//! - \b SYSCTL_PERIPH_EUSCIA2
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//! - \b SYSCTL_PERIPH_EUSCIA1,
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//! - \b SYSCTL_PERIPH_EUSCIA0,
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//! - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
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//! - \b SYSCTL_PERIPH_TIMER16_3,
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//! - \b SYSCTL_PERIPH_TIMER16_2,
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//! - \b SYSCTL_PERIPH_TIMER16_1,
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//! - \b SYSCTL_PERIPH_TIMER16_0
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//!
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//! \return None.
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//
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//
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//*****************************************************************************
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extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
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//*****************************************************************************
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//
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//! Makes it so that the provided peripherals will either halt execution after
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//! a CPU HALT. Parameters in this function can be combined to account for
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//! multiple peripherals. By default, all peripherals keep running after a
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//! CPU HALT.
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//!
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//! \param devices The peripherals to disable after a CPU HALT
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//!
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//! The \e devices parameter can be a bitwise OR of the following values:
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//! This can be a bitwise OR of the following values:
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//! - \b SYSCTL_PERIPH_DMA,
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//! - \b SYSCTL_PERIPH_WDT,
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//! - \b SYSCTL_PERIPH_ADC,
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//! - \b SYSCTL_PERIPH_EUSCIB3,
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//! - \b SYSCTL_PERIPH_EUSCIB2,
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//! - \b SYSCTL_PERIPH_EUSCIB1
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//! - \b SYSCTL_PERIPH_EUSCIB0,
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//! - \b SYSCTL_PERIPH_EUSCIA3,
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//! - \b SYSCTL_PERIPH_EUSCIA2
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//! - \b SYSCTL_PERIPH_EUSCIA1,
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//! - \b SYSCTL_PERIPH_EUSCIA0,
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//! - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
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//! - \b SYSCTL_PERIPH_TIMER16_3,
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//! - \b SYSCTL_PERIPH_TIMER16_2,
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//! - \b SYSCTL_PERIPH_TIMER16_1,
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//! - \b SYSCTL_PERIPH_TIMER16_0
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//!
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//! \return None.
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//
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//
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//*****************************************************************************
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extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
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//*****************************************************************************
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//
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//! Sets the type of RESET that happens when a watchdog timeout occurs.
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//!
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//! \param resetType The type of reset to set
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//!
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//! The \e resetType parameter must be only one of the following values:
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//! - \b SYSCTL_HARD_RESET,
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//! - \b SYSCTL_SOFT_RESET
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//!
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//! \return None.
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//
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//
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//*****************************************************************************
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extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
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//*****************************************************************************
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//
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//! Sets the type of RESET that happens when a watchdog password violation
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//! occurs.
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//!
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//! \param resetType The type of reset to set
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//!
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//! The \e resetType parameter must be only one of the following values:
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//! - \b SYSCTL_HARD_RESET,
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//! - \b SYSCTL_SOFT_RESET
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//!
|
|
//! \return None.
|
|
//
|
|
//
|
|
//*****************************************************************************
|
|
extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables NMIs for the provided modules. When disabled, a NMI flag will not
|
|
//! occur when a fault condition comes from the corresponding modules.
|
|
//!
|
|
//! \param flags The NMI sources to disable
|
|
//! Can be a bitwise OR of the following parameters:
|
|
//! - \b SYSCTL_NMIPIN_SRC,
|
|
//! - \b SYSCTL_PCM_SRC,
|
|
//! - \b SYSCTL_PSS_SRC,
|
|
//! - \b SYSCTL_CS_SRC
|
|
//!
|
|
//
|
|
//*****************************************************************************
|
|
extern void SysCtl_disableNMISource(uint_fast8_t flags);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables NMIs for the provided modules. When enabled, a NMI flag will
|
|
//! occur when a fault condition comes from the corresponding modules.
|
|
//!
|
|
//! \param flags The NMI sources to enable
|
|
//! Can be a bitwise OR of the following parameters:
|
|
//! - \b SYSCTL_NMIPIN_SRC,
|
|
//! - \b SYSCTL_PCM_SRC,
|
|
//! - \b SYSCTL_PSS_SRC,
|
|
//! - \b SYSCTL_CS_SRC
|
|
//!
|
|
//
|
|
//*****************************************************************************
|
|
extern void SysCtl_enableNMISource(uint_fast8_t flags);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Returns the current sources of NMIs that are enabled
|
|
//!
|
|
//! \return Bitwise OR of NMI flags that are enabled
|
|
//
|
|
//*****************************************************************************
|
|
extern uint_fast8_t SysCtl_getNMISourceStatus(void);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Enables glitch suppression on the reset pin of the device. Refer to the
|
|
//! device data sheet for specific information about glitch suppression
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//
|
|
//*****************************************************************************
|
|
extern void SysCtl_enableGlitchFilter(void);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Disables glitch suppression on the reset pin of the device. Refer to the
|
|
//! device data sheet for specific information about glitch suppression
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//
|
|
//*****************************************************************************
|
|
extern void SysCtl_disableGlitchFilter(void);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Retrieves the calibration constant of the temperature sensor to be used
|
|
//! in temperature calculation.
|
|
//!
|
|
//! \param refVoltage Reference voltage being used.
|
|
//!
|
|
//! The \e refVoltage parameter must be only one of the following values:
|
|
//! - \b SYSCTL_1_2V_REF
|
|
//! - \b SYSCTL_1_45V_REF
|
|
//! - \b SYSCTL_2_5V_REF
|
|
//!
|
|
//! \param temperature is the calibration temperature that the user wants to be
|
|
//! returned.
|
|
//!
|
|
//! The \e temperature parameter must be only one of the following values:
|
|
//! - \b SYSCTL_30_DEGREES_C
|
|
//! - \b SYSCTL_85_DEGREES_C
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//
|
|
//*****************************************************************************
|
|
extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
|
|
uint32_t temperature);
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Mark the end of the C bindings section for C++ compilers.
|
|
//
|
|
//*****************************************************************************
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|
|
|
|
#endif // __SYSCTL_H__
|