408 lines
9.1 KiB
ArmAsm
408 lines
9.1 KiB
ArmAsm
.global port_int_disable
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.global port_int_enable
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.global port_cpsr_save
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.global port_cpsr_restore
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.global port_sched_start
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.global port_context_switch
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.global port_irq_context_switch
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#include "riscv_encoding.h"
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.text
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.align 2
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.type port_int_disable, %function
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port_int_disable:
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csrci mstatus, MSTATUS_MIE
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ret
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.type port_int_enable, %function
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port_int_enable:
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csrsi mstatus, MSTATUS_MIE
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ret
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.type port_cpsr_save, %function
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port_cpsr_save:
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csrrci a0, mstatus, MSTATUS_MIE
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#csrrci a0, mstatus, MSTATUS_MPIE
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ret
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.type port_cpsr_restore, %function
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port_cpsr_restore:
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csrw mstatus, a0
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ret
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#define REGBYTES 4
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#define LOAD lw
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#define STORE sw
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.extern k_curr_task
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.type port_sched_start, %function
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port_sched_start:
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// enable timer interrupt
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li t0, MIE_MTIE
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csrs mie, t0
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t0, (t0) // t0 = &(k_curr_task->sp)
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LOAD sp, (t0) // k_curr_task->sp = sp
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// save sp
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addi t1, sp, 32*REGBYTES
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STORE t1, (t0)
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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.align 2
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.global machine_trap_entry
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machine_trap_entry:
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addi sp, sp, -32*REGBYTES
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STORE x1, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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#if 1
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//li t0, MSTATUS_MPP | MSTATUS_MPIE // acutally MPIE is not need
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csrr t0, mstatus
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STORE t0, 1*REGBYTES(sp)
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csrr t0, mepc // just save information for handler
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STORE t0, 0*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t1, (t0)
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STORE sp, (t1)
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csrr a0, mcause
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mv a1, sp
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bltz a0, irq
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call cpu_trap_entry
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j restore
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irq:
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slli a0, a0, 1
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srli a0, a0, 1
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call cpu_irq_entry
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restore:
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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#else
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// for debug timer interrupt only
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csrr a0, mcause
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slli a0, a0, 1
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srli a0, a0, 1
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call cpu_irq_entry
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#endif
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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.align 2
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.type port_context_switch, %function
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port_context_switch:
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nop
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nop
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addi sp, sp, -32*REGBYTES
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STORE x1, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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li t0, MSTATUS_MPP // force use machine mode
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csrr t1, mstatus
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and t1, t1, MSTATUS_MIE
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beqz t1, save_mstatus
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or t0, t0, MSTATUS_MPIE
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save_mstatus:
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STORE t0, 1*REGBYTES(sp)
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la t0, port_context_switch_return // just save information for handler
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STORE t0, 0*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t1, (t0)
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STORE sp, (t1)
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// k_curr_task = k_next_task
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la t1, k_next_task // t1 = &k_next_task
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LOAD t1, (t1) // t1 = k_next_task
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STORE t1, (t0)
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// load sp from k_next_task.sp
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LOAD sp, (t1)
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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.align 2
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port_context_switch_return:
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ret
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.align 2
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.type port_irq_context_switch, %function
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port_irq_context_switch:
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addi sp, sp, -32*REGBYTES
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STORE x1, 2*REGBYTES(sp)
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x29, 29*REGBYTES(sp)
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STORE x30, 30*REGBYTES(sp)
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STORE x31, 31*REGBYTES(sp)
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li t0, MSTATUS_MPP
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STORE t0, 1*REGBYTES(sp)
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la t0, irq_context_return
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STORE t0, 0*REGBYTES(sp)
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// save sp to k_curr_task.sp
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la t0, k_curr_task // t0 = &k_curr_task
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LOAD t1, (t0)
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STORE sp, (t1)
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// k_curr_task = k_next_task
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la t1, k_next_task // t1 = &k_next_task
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LOAD t1, (t1) // t1 = k_next_task
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STORE t1, (t0)
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// load sp from k_next_task.sp
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LOAD sp, (t1)
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LOAD t0, 1*REGBYTES(sp)
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csrw mstatus, t0
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LOAD t0, 0*REGBYTES(sp)
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csrw mepc, t0
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LOAD x1, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x10, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x29, 29*REGBYTES(sp)
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LOAD x30, 30*REGBYTES(sp)
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LOAD x31, 31*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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irq_context_return:
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ret
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