684 lines
22 KiB
C
684 lines
22 KiB
C
/*
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* FreeModbus Libary: MCF5235 Demo Application
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* Copyright (C) 2006 Christian Walter <wolti@sil.at>
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* Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* File: $Id$
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*/
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#include "mcf5xxx.h"
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#include "mcf523x.h"
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/* Function prototypes */
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void init_main( void );
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static void disable_interrupts( void );
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static void disable_watchdog_timer( void );
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static void disable_cache( void );
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static void init_ipsbar( void );
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static void init_basics( void );
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static void init_clock_config( void );
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static void init_chip_selects( void );
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static void init_bus_config( void );
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static void init_cache( void );
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static void init_eport( void );
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static void init_flexcan( void );
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static void init_power_management( void );
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static void init_dma_timers( void );
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static void init_interrupt_timers( void );
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static void init_watchdog_timers( void );
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static void init_pin_assignments( void );
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static void init_sdram_controller( void );
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static void init_interrupt_controller( void );
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/*********************************************************************
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* init_main - Main entry point for initialisation code *
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**********************************************************************/
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void
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init_main( void )
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{
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/* Initialise base address of peripherals, VBR, etc */
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init_ipsbar( );
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init_basics( );
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init_clock_config( );
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/* Disable interrupts, watchdog timer, cache */
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disable_interrupts( );
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disable_watchdog_timer( );
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disable_cache( );
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/* Initialise individual modules */
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init_chip_selects( );
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init_bus_config( );
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init_cache( );
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init_eport( );
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init_flexcan( );
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init_power_management( );
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init_dma_timers( );
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init_interrupt_timers( );
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init_watchdog_timers( );
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init_pin_assignments( );
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init_sdram_controller( );
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/* Initialise interrupt controller */
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init_interrupt_controller( );
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}
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/*********************************************************************
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* disable_interrupts - Disable all interrupt sources *
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**********************************************************************/
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static void
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disable_interrupts( void )
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{
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vuint8 *p;
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int i;
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/* Set ICR008-ICR063 to 0x0 */
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p = ( vuint8 * ) & MCF_INTC0_ICR8;
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for( i = 8; i <= 63; i++ )
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*p++ = 0x0;
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/* Set ICR108-ICR163 to 0x0 */
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p = ( vuint8 * ) & MCF_INTC1_ICR8;
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for( i = 108; i <= 163; i++ )
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*p++ = 0x0;
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}
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/*********************************************************************
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* disable_watchdog_timer - Disable system watchdog timer *
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**********************************************************************/
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static void
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disable_watchdog_timer( void )
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{
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/* Disable Core Watchdog Timer */
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MCF_SCM_CWCR = 0;
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}
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/*********************************************************************
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* disable_cache - Disable and invalidate cache *
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**********************************************************************/
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static void
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disable_cache( void )
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{
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asm( "move.l #0x01000000,%d0" );
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asm( "movec %d0,%cacr" );
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}
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/*********************************************************************
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* init_basics - Configuration Information & VBR *
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**********************************************************************/
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static void
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init_basics( void )
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{
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extern void ramvec_start;
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extern void romvec_start;
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/* Transfer size not driven on SIZ[1:0] pins during external cycles
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Processor Status (PST) and Debug Data (DDATA) functions disabled
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Bus monitor disabled
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Output pads configured for full strength
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*/
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MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
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/* Exception vector table at $00000000 */
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asm( "move.l %0,%%d0": :"i"( &romvec_start ) );
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asm( "movec %d0,%vbr" );
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}
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/*********************************************************************
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* init_clock_config - Clock Module *
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**********************************************************************/
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static void
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init_clock_config( void )
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{
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/* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
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MFD = 0, RFD = 1
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Bus clock frequency = 25.00 MHz
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Processor clock frequency = 2 x bus clock = 50.00 MHz
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Frequency Modulation disabled
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Loss of clock detection disabled
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Reset/Interrupt on loss of lock disabled
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*/
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MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */
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while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
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;
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MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */
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while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */
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;
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}
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/*********************************************************************
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* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) *
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**********************************************************************/
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static void
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init_ipsbar( void )
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{
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/* Base address of internal peripherals (IPSBAR) = 0x40000000
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Note: Processor powers up with IPS base address = 0x40000000
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Write to IPS base + 0x00000000 to set new value
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*/
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*( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1; /* +1 for Enable */
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}
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/*********************************************************************
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* init_chip_selects - Chip Select Module *
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**********************************************************************/
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static void
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init_chip_selects( void )
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{
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/* Chip Select 0 disabled (CSMR0[V] = 0) */
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MCF_CS_CSAR0 = 0;
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MCF_CS_CSMR0 = 0;
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MCF_CS_CSCR0 = MCF_CS_CSCR_IWS( 0xf ) | MCF_CS_CSCR_AA;
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/* Chip Select 1 disabled (CSMR1[V] = 0) */
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MCF_CS_CSAR1 = 0;
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MCF_CS_CSMR1 = 0;
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MCF_CS_CSCR1 = 0;
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/* Chip Select 2 disabled (CSMR2[V] = 0) */
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MCF_CS_CSAR2 = 0;
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MCF_CS_CSMR2 = 0;
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MCF_CS_CSCR2 = 0;
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/* Chip Select 3 disabled (CSMR3[V] = 0) */
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MCF_CS_CSAR3 = 0;
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MCF_CS_CSMR3 = 0;
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MCF_CS_CSCR3 = 0;
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/* Chip Select 4 disabled (CSMR4[V] = 0) */
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MCF_CS_CSAR4 = 0;
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MCF_CS_CSMR4 = 0;
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MCF_CS_CSCR4 = 0;
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/* Chip Select 5 disabled (CSMR5[V] = 0) */
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MCF_CS_CSAR5 = 0;
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MCF_CS_CSMR5 = 0;
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MCF_CS_CSCR5 = 0;
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/* Chip Select 6 disabled (CSMR6[V] = 0) */
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MCF_CS_CSAR6 = 0;
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MCF_CS_CSMR6 = 0;
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MCF_CS_CSCR6 = 0;
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/* Chip Select 7 disabled (CSMR7[V] = 0) */
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MCF_CS_CSAR7 = 0;
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MCF_CS_CSMR7 = 0;
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MCF_CS_CSCR7 = 0;
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}
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/*********************************************************************
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* init_bus_config - Internal Bus Arbitration *
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**********************************************************************/
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static void
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init_bus_config( void )
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{
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/* Use round robin arbitration scheme
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Assigned priorities (highest first):
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Ethernet
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DMA Controller
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ColdFire Core
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DMA bandwidth control disabled
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Park on last active bus master
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*/
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MCF_SCM_MPARK = MCF_SCM_MPARK_M3_PRTY( 0x3 ) |
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MCF_SCM_MPARK_M2_PRTY( 0x2 ) | MCF_SCM_MPARK_M1_PRTY( 0x1 );
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}
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/*********************************************************************
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* init_cache - Instruction/Data Cache *
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**********************************************************************/
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static void
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init_cache( void )
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{
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/* Instruction/Data cache disabled */
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asm( "move.l #0x00000000, %d0" );
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asm( "movec %d0,%cacr" );
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}
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/*********************************************************************
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* init_eport - Edge Port Module (EPORT) *
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**********************************************************************/
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static void
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init_eport( void )
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{
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/* Pins 1-7 configured as GPIO inputs */
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MCF_EPORT_EPPAR = 0;
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MCF_EPORT_EPDDR = 0;
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MCF_EPORT_EPIER = 0;
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}
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/*********************************************************************
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* init_flexcan - FlexCAN Module *
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**********************************************************************/
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static void
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init_flexcan( void )
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{
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/* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
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MCF_CAN_IMASK0 = 0;
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MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
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MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
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MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
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MCF_CAN_CANCTRL0 = 0;
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MCF_CAN_CANMCR0 = MCF_CAN_CANMCR_MDIS |
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MCF_CAN_CANMCR_FRZ |
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MCF_CAN_CANMCR_HALT |
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MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
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/* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
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MCF_CAN_IMASK1 = 0;
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MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
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MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
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MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
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MCF_CAN_CANCTRL1 = 0;
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MCF_CAN_CANMCR1 = MCF_CAN_CANMCR_MDIS |
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MCF_CAN_CANMCR_FRZ |
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MCF_CAN_CANMCR_HALT |
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MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
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}
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/*********************************************************************
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* init_power_management - Power Management *
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**********************************************************************/
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static void
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init_power_management( void )
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{
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/* On executing STOP instruction, processor enters RUN mode
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Mode is exited when an interrupt of level 1 or higher is received
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*/
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MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
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MCF_CCM_LPCR = 0;
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}
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/*********************************************************************
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* init_sdram_controller - SDRAM Controller *
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**********************************************************************/
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static void
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init_sdram_controller( void )
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{
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/* DRAM type is Synchronous (SDRAM)
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SDRAM refresh timings:
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Number of clocks spent in refresh state = 3
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Refresh count = 511 (Refresh every 327.68 microseconds at 25.0 MHz bus clock)
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*/
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MCF_SDRAMC_DCR = MCF_SDRAMC_DCR_RC( 0x1ff );
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/* Memory block 0 not in use (DMR0[V] = 0) */
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MCF_SDRAMC_DMR0 = MCF_SDRAMC_DMR_BAM_256K;
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MCF_SDRAMC_DACR0 = 0;
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/* Memory block 1 not in use (DMR1[V] = 0) */
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MCF_SDRAMC_DMR1 = MCF_SDRAMC_DMR_BAM_256K;
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MCF_SDRAMC_DACR1 = 0;
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}
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/*********************************************************************
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* init_dma_timers - DMA Timer Modules *
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**********************************************************************/
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static void
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init_dma_timers( void )
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{
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/* DMA Timer 0 disabled (DTMR0[RST] = 0) */
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MCF_TIMER_DTMR0 = 0;
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MCF_TIMER_DTXMR0 = 0;
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MCF_TIMER_DTRR0 = 0xffffffff;
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/* DMA Timer 1 disabled (DTMR1[RST] = 0) */
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MCF_TIMER_DTMR1 = 0;
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MCF_TIMER_DTXMR1 = 0;
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MCF_TIMER_DTRR1 = 0xffffffff;
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/* DMA Timer 2 disabled (DTMR2[RST] = 0) */
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MCF_TIMER_DTMR2 = 0;
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MCF_TIMER_DTXMR2 = 0;
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MCF_TIMER_DTRR2 = 0xffffffff;
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/* DMA Timer 3 disabled (DTMR3[RST] = 0) */
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MCF_TIMER_DTMR3 = 0;
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MCF_TIMER_DTXMR3 = 0;
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MCF_TIMER_DTRR3 = 0xffffffff;
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}
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/**********************************************************************
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* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules *
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***********************************************************************/
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static void
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init_interrupt_timers( void )
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{
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/* PIT0 disabled (PCSR0[EN]=0) */
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MCF_PIT_PCSR0 = 0;
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/* PIT1 disabled (PCSR1[EN]=0) */
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MCF_PIT_PCSR1 = 0;
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/* PIT2 disabled (PCSR2[EN]=0) */
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MCF_PIT_PCSR2 = 0;
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/* PIT3 disabled (PCSR3[EN]=0) */
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MCF_PIT_PCSR3 = 0;
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}
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/*********************************************************************
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* init_watchdog_timers - Watchdog Timer Modules *
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**********************************************************************/
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static void
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init_watchdog_timers( void )
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{
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/* Watchdog Timer disabled (WCR[EN]=0)
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NOTE: WCR and WMR cannot be written again until after the
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processor is reset.
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*/
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MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
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MCF_WTM_WMR = 0xffff;
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/* Core Watchdog Timer disabled (CWCR[CWE]=0) */
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MCF_SCM_CWCR = 0;
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}
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/*********************************************************************
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* init_interrupt_controller - Interrupt Controller *
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**********************************************************************/
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static void
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init_interrupt_controller( void )
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{
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/* Configured interrupt sources in order of priority...
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Level 7: External interrupt /IRQ7, (initially masked)
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Level 6: External interrupt /IRQ6, (initially masked)
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Level 5: External interrupt /IRQ5, (initially masked)
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Level 4: External interrupt /IRQ4, (initially masked)
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Level 3: External interrupt /IRQ3, (initially masked)
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Level 2: External interrupt /IRQ2, (initially masked)
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Level 1: External interrupt /IRQ1, (initially masked)
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*/
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MCF_INTC0_ICR1 = 0;
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MCF_INTC0_ICR2 = 0;
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MCF_INTC0_ICR3 = 0;
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MCF_INTC0_ICR4 = 0;
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MCF_INTC0_ICR5 = 0;
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MCF_INTC0_ICR6 = 0;
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MCF_INTC0_ICR7 = 0;
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MCF_INTC0_ICR8 = 0;
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MCF_INTC0_ICR9 = 0;
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MCF_INTC0_ICR10 = 0;
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MCF_INTC0_ICR11 = 0;
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MCF_INTC0_ICR12 = 0;
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MCF_INTC0_ICR13 = 0;
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MCF_INTC0_ICR14 = 0;
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MCF_INTC0_ICR15 = 0;
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MCF_INTC0_ICR17 = 0;
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MCF_INTC0_ICR18 = 0;
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MCF_INTC0_ICR19 = 0;
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MCF_INTC0_ICR20 = 0;
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MCF_INTC0_ICR21 = 0;
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MCF_INTC0_ICR22 = 0;
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MCF_INTC0_ICR23 = 0;
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MCF_INTC0_ICR24 = 0;
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MCF_INTC0_ICR25 = 0;
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MCF_INTC0_ICR26 = 0;
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MCF_INTC0_ICR27 = 0;
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MCF_INTC0_ICR28 = 0;
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MCF_INTC0_ICR29 = 0;
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MCF_INTC0_ICR30 = 0;
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MCF_INTC0_ICR31 = 0;
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MCF_INTC0_ICR32 = 0;
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MCF_INTC0_ICR33 = 0;
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MCF_INTC0_ICR34 = 0;
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MCF_INTC0_ICR35 = 0;
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MCF_INTC0_ICR36 = 0;
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MCF_INTC0_ICR37 = 0;
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MCF_INTC0_ICR38 = 0;
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MCF_INTC0_ICR39 = 0;
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MCF_INTC0_ICR40 = 0;
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MCF_INTC0_ICR41 = 0;
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MCF_INTC0_ICR42 = 0;
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MCF_INTC0_ICR43 = 0;
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MCF_INTC0_ICR44 = 0;
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MCF_INTC0_ICR45 = 0;
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MCF_INTC0_ICR46 = 0;
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MCF_INTC0_ICR47 = 0;
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MCF_INTC0_ICR48 = 0;
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MCF_INTC0_ICR49 = 0;
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MCF_INTC0_ICR50 = 0;
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MCF_INTC0_ICR51 = 0;
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MCF_INTC0_ICR52 = 0;
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MCF_INTC0_ICR53 = 0;
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MCF_INTC0_ICR54 = 0;
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MCF_INTC0_ICR55 = 0;
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MCF_INTC0_ICR56 = 0;
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MCF_INTC0_ICR57 = 0;
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MCF_INTC0_ICR58 = 0;
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MCF_INTC0_ICR59 = 0;
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MCF_INTC0_ICR60 = 0;
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MCF_INTC1_ICR8 = 0;
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MCF_INTC1_ICR9 = 0;
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MCF_INTC1_ICR10 = 0;
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MCF_INTC1_ICR11 = 0;
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MCF_INTC1_ICR12 = 0;
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MCF_INTC1_ICR13 = 0;
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MCF_INTC1_ICR14 = 0;
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MCF_INTC1_ICR15 = 0;
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MCF_INTC1_ICR16 = 0;
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MCF_INTC1_ICR17 = 0;
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MCF_INTC1_ICR18 = 0;
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MCF_INTC1_ICR19 = 0;
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MCF_INTC1_ICR20 = 0;
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MCF_INTC1_ICR21 = 0;
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MCF_INTC1_ICR22 = 0;
|
|
MCF_INTC1_ICR23 = 0;
|
|
MCF_INTC1_ICR24 = 0;
|
|
MCF_INTC1_ICR25 = 0;
|
|
MCF_INTC1_ICR27 = 0;
|
|
MCF_INTC1_ICR28 = 0;
|
|
MCF_INTC1_ICR29 = 0;
|
|
MCF_INTC1_ICR30 = 0;
|
|
MCF_INTC1_ICR31 = 0;
|
|
MCF_INTC1_ICR32 = 0;
|
|
MCF_INTC1_ICR33 = 0;
|
|
MCF_INTC1_ICR34 = 0;
|
|
MCF_INTC1_ICR35 = 0;
|
|
MCF_INTC1_ICR36 = 0;
|
|
MCF_INTC1_ICR37 = 0;
|
|
MCF_INTC1_ICR38 = 0;
|
|
MCF_INTC1_ICR39 = 0;
|
|
MCF_INTC1_ICR40 = 0;
|
|
MCF_INTC1_ICR41 = 0;
|
|
MCF_INTC1_ICR42 = 0;
|
|
MCF_INTC1_ICR59 = 0;
|
|
MCF_INTC0_IMRH = 0xffffffff;
|
|
MCF_INTC0_IMRL = MCF_INTC0_IMRL_INT_MASK31 |
|
|
MCF_INTC0_IMRL_INT_MASK30 |
|
|
MCF_INTC0_IMRL_INT_MASK29 |
|
|
MCF_INTC0_IMRL_INT_MASK28 |
|
|
MCF_INTC0_IMRL_INT_MASK27 |
|
|
MCF_INTC0_IMRL_INT_MASK26 |
|
|
MCF_INTC0_IMRL_INT_MASK25 |
|
|
MCF_INTC0_IMRL_INT_MASK24 |
|
|
MCF_INTC0_IMRL_INT_MASK23 |
|
|
MCF_INTC0_IMRL_INT_MASK22 |
|
|
MCF_INTC0_IMRL_INT_MASK21 |
|
|
MCF_INTC0_IMRL_INT_MASK20 |
|
|
MCF_INTC0_IMRL_INT_MASK19 |
|
|
MCF_INTC0_IMRL_INT_MASK18 |
|
|
MCF_INTC0_IMRL_INT_MASK17 |
|
|
MCF_INTC0_IMRL_INT_MASK16 |
|
|
MCF_INTC0_IMRL_INT_MASK15 |
|
|
MCF_INTC0_IMRL_INT_MASK14 |
|
|
MCF_INTC0_IMRL_INT_MASK13 |
|
|
MCF_INTC0_IMRL_INT_MASK12 |
|
|
MCF_INTC0_IMRL_INT_MASK11 |
|
|
MCF_INTC0_IMRL_INT_MASK10 |
|
|
MCF_INTC0_IMRL_INT_MASK9 |
|
|
MCF_INTC0_IMRL_INT_MASK8 |
|
|
MCF_INTC0_IMRL_INT_MASK7 |
|
|
MCF_INTC0_IMRL_INT_MASK6 |
|
|
MCF_INTC0_IMRL_INT_MASK5 |
|
|
MCF_INTC0_IMRL_INT_MASK4 |
|
|
MCF_INTC0_IMRL_INT_MASK3 |
|
|
MCF_INTC0_IMRL_INT_MASK2 | MCF_INTC0_IMRL_INT_MASK1;
|
|
MCF_INTC1_IMRH = 0xffffffff;
|
|
MCF_INTC1_IMRL = MCF_INTC1_IMRL_INT_MASK31 |
|
|
MCF_INTC1_IMRL_INT_MASK30 |
|
|
MCF_INTC1_IMRL_INT_MASK29 |
|
|
MCF_INTC1_IMRL_INT_MASK28 |
|
|
MCF_INTC1_IMRL_INT_MASK27 |
|
|
MCF_INTC1_IMRL_INT_MASK26 |
|
|
MCF_INTC1_IMRL_INT_MASK25 |
|
|
MCF_INTC1_IMRL_INT_MASK24 |
|
|
MCF_INTC1_IMRL_INT_MASK23 |
|
|
MCF_INTC1_IMRL_INT_MASK22 |
|
|
MCF_INTC1_IMRL_INT_MASK21 |
|
|
MCF_INTC1_IMRL_INT_MASK20 |
|
|
MCF_INTC1_IMRL_INT_MASK19 |
|
|
MCF_INTC1_IMRL_INT_MASK18 |
|
|
MCF_INTC1_IMRL_INT_MASK17 |
|
|
MCF_INTC1_IMRL_INT_MASK16 |
|
|
MCF_INTC1_IMRL_INT_MASK15 |
|
|
MCF_INTC1_IMRL_INT_MASK14 |
|
|
MCF_INTC1_IMRL_INT_MASK13 |
|
|
MCF_INTC1_IMRL_INT_MASK12 |
|
|
MCF_INTC1_IMRL_INT_MASK11 |
|
|
MCF_INTC1_IMRL_INT_MASK10 |
|
|
MCF_INTC1_IMRL_INT_MASK9 |
|
|
MCF_INTC1_IMRL_INT_MASK8 |
|
|
MCF_INTC1_IMRL_INT_MASK7 |
|
|
MCF_INTC1_IMRL_INT_MASK6 |
|
|
MCF_INTC1_IMRL_INT_MASK5 |
|
|
MCF_INTC1_IMRL_INT_MASK4 |
|
|
MCF_INTC1_IMRL_INT_MASK3 |
|
|
MCF_INTC1_IMRL_INT_MASK2 | MCF_INTC1_IMRL_INT_MASK1;
|
|
}
|
|
|
|
/*********************************************************************
|
|
* init_pin_assignments - Pin Assignment and General Purpose I/O *
|
|
**********************************************************************/
|
|
static void
|
|
init_pin_assignments( void )
|
|
{
|
|
/* Pin assignments for port ADDR
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_APDDR = 0;
|
|
MCF_GPIO_PAR_AD = 0;
|
|
|
|
/* Pin assignments for ports DATAH and DATAL
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_DATAH = 0;
|
|
MCF_GPIO_PDDR_DATAL = 0;
|
|
|
|
/* Pin assignments for port BUSCTL
|
|
Pin /OE : External bus output enable, /OE
|
|
Pin /TA : External bus transfer acknowledge, /TA
|
|
Pin /TEA : External bus transfer error acknowledge, /TEA
|
|
Pin R/W : External bus read/write indication, R/W
|
|
Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
|
|
Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
|
|
Pin /TS : External bus transfer start, /TS
|
|
Pin /TIP : External bus transfer in progess, /TIP
|
|
*/
|
|
MCF_GPIO_PDDR_BUSCTL = 0;
|
|
MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_TA |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_RWB |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
|
|
MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
|
|
|
|
/* Pin assignments for port BS
|
|
Pin /BS3 : External byte strobe /BS3
|
|
Pin /BS2 : External byte strobe /BS2
|
|
Pin /BS1 : External byte strobe /BS1
|
|
Pin /BS0 : External byte strobe /BS0
|
|
*/
|
|
MCF_GPIO_PDDR_BS = 0;
|
|
MCF_GPIO_PAR_BS = MCF_GPIO_PAR_BS_PAR_BS3 |
|
|
MCF_GPIO_PAR_BS_PAR_BS2 |
|
|
MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
|
|
|
|
/* Pin assignments for port CS
|
|
Pin /CS7 : Chip select /CS7
|
|
Pin /CS6 : Chip select /CS6
|
|
Pin /CS5 : Chip select /CS5
|
|
Pin /CS4 : Chip select /CS4
|
|
Pin /CS3 : Chip select /CS3
|
|
Pin /CS2 : Chip select /CS2
|
|
Pin /CS1 : Chip select /CS1
|
|
*/
|
|
MCF_GPIO_PDDR_CS = 0;
|
|
MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS7 |
|
|
MCF_GPIO_PAR_CS_PAR_CS6 |
|
|
MCF_GPIO_PAR_CS_PAR_CS5 |
|
|
MCF_GPIO_PAR_CS_PAR_CS4 |
|
|
MCF_GPIO_PAR_CS_PAR_CS3 |
|
|
MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
|
|
|
|
/* Pin assignments for port SDRAM
|
|
Pin /SD_WE : SDRAM controller /SD_WE
|
|
Pin /SD_SCAS : SDRAM controller /SD_SCAS
|
|
Pin /SD_SRAS : SDRAM controller /SD_SRAS
|
|
Pin /SD_SCKE : SDRAM controller /SD_SCKE
|
|
Pin /SD_CS1 : SDRAM controller /SD_CS1
|
|
Pin /SD_CS0 : SDRAM controller /SD_CS0
|
|
*/
|
|
MCF_GPIO_PDDR_SDRAM = 0;
|
|
MCF_GPIO_PAR_SDRAM = MCF_GPIO_PAR_SDRAM_PAR_SDWE |
|
|
MCF_GPIO_PAR_SDRAM_PAR_SCAS |
|
|
MCF_GPIO_PAR_SDRAM_PAR_SRAS |
|
|
MCF_GPIO_PAR_SDRAM_PAR_SCKE |
|
|
MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
|
|
|
|
/* Pin assignments for port FECI2C
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_FECI2C = 0;
|
|
MCF_GPIO_PAR_FECI2C = 0;
|
|
|
|
/* Pin assignments for port UARTL
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_UARTL = 0;
|
|
MCF_GPIO_PAR_UART = 0;
|
|
|
|
/* Pin assignments for port UARTH
|
|
Pin U2TXD : GPIO input
|
|
Pin U2RXD : GPIO input
|
|
Pin /IRQ2 : Interrupt request /IRQ2 or GPIO
|
|
*/
|
|
MCF_GPIO_PDDR_UARTH = 0;
|
|
|
|
/* Pin assignments for port QSPI
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_QSPI = 0;
|
|
MCF_GPIO_PAR_QSPI = 0;
|
|
|
|
/* Pin assignments for port TIMER
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_TIMER = 0;
|
|
MCF_GPIO_PAR_TIMER = 0;
|
|
|
|
/* Pin assignments for port ETPU
|
|
Pins are all GPIO inputs
|
|
*/
|
|
MCF_GPIO_PDDR_ETPU = 0;
|
|
MCF_GPIO_PAR_ETPU = 0;
|
|
}
|