442 lines
13 KiB
C
442 lines
13 KiB
C
/**
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******************************************************************************
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* File Name : ETH.c
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* Description : This file provides code for the configuration
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* of the ETH instances.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "bsp_eth.h"
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#include "main.h"
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#include "tos_k.h"
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#include "lwip/opt.h"
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#include "lwip/timeouts.h"
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#include "netif/ethernet.h"
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#include "netif/etharp.h"
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#include "lwip/ethip6.h"
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#include "ethernetif.h"
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#include <string.h>
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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ETH_HandleTypeDef heth;
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k_sem_t s_xSemaphore;
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/* Private variables ---------------------------------------------------------*/
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#if defined ( __ICCARM__ ) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB] __ALIGN_END;/* Ethernet Rx MA Descriptor */
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#if defined ( __ICCARM__ ) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB] __ALIGN_END;/* Ethernet Tx DMA Descriptor */
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#if defined ( __ICCARM__ ) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __ALIGN_END; /* Ethernet Receive Buffer */
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#if defined ( __ICCARM__ ) /*!< IAR Compiler */
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#pragma data_alignment=4
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#endif
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__ALIGN_BEGIN uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __ALIGN_END; /* Ethernet Transmit Buffer */
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/* Private functions ---------------------------------------------------------*/
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void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
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{
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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if(ethHandle->Instance==ETH)
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{
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/* USER CODE BEGIN ETH_MspInit 0 */
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/* USER CODE END ETH_MspInit 0 */
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/* Enable Peripheral clock */
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__HAL_RCC_ETH_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/**ETH GPIO Configuration
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PC1 ------> ETH_MDC
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PA1 ------> ETH_REF_CLK
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PA2 ------> ETH_MDIO
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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PB13 ------> ETH_TXD1
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PG11 ------> ETH_TX_EN
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PG13 ------> ETH_TXD0
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*/
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GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_TXD1_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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/* Peripheral interrupt init */
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HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(ETH_IRQn);
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/* USER CODE BEGIN ETH_MspInit 1 */
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/* USER CODE END ETH_MspInit 1 */
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}
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}
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void HAL_ETH_MspDeInit(ETH_HandleTypeDef* ethHandle)
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{
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if(ethHandle->Instance==ETH)
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{
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/* USER CODE BEGIN ETH_MspDeInit 0 */
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/* USER CODE END ETH_MspDeInit 0 */
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/* Peripheral clock disable */
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__HAL_RCC_ETH_CLK_DISABLE();
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/**ETH GPIO Configuration
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PC1 ------> ETH_MDC
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PA1 ------> ETH_REF_CLK
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PA2 ------> ETH_MDIO
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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PB13 ------> ETH_TXD1
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PG11 ------> ETH_TX_EN
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PG13 ------> ETH_TXD0
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*/
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HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
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HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
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HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
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HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
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/* Peripheral interrupt Deinit*/
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HAL_NVIC_DisableIRQ(ETH_IRQn);
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/* USER CODE BEGIN ETH_MspDeInit 1 */
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/* USER CODE END ETH_MspDeInit 1 */
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}
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}
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/**
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* @brief Ethernet Rx Transfer completed callback
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* @param heth: ETH handle
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* @retval None
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*/
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void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
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{
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HAL_GPIO_TogglePin(LD1_GPIO_Port,LD1_Pin);
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tos_sem_post(&s_xSemaphore);
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}
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void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
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{
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printf("eth err\n");
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}
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static void eth_thread(void *arg)
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{
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while (1)
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{
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sys_arch_sem_wait(&s_xSemaphore, (u32_t)TOS_TIME_FOREVER);
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ethernetif_input(arg);
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}
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}
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static int lan8742a_init(struct netif *netif)
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{
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uint32_t regvalue = 0;
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HAL_StatusTypeDef hal_eth_init_status;
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/* Init ETH */
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uint8_t MACAddr[6] ;
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heth.Instance = ETH;
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heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
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MACAddr[0] = 0x00;
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MACAddr[1] = 0x80;
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MACAddr[2] = 0xE1;
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MACAddr[3] = 0x00;
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MACAddr[4] = 0x00;
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MACAddr[5] = 0x00;
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heth.Init.MACAddr = &MACAddr[0];
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heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
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heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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hal_eth_init_status = HAL_ETH_Init(&heth);
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if (hal_eth_init_status == HAL_OK)
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{
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/* Set netif link flag */
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netif->flags |= NETIF_FLAG_LINK_UP;
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}
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/* Initialize Tx Descriptors list: Chain Mode */
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HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
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/* Initialize Rx Descriptors list: Chain Mode */
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HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
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#if LWIP_ARP || LWIP_ETHERNET
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/* set MAC hardware address length */
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netif->hwaddr_len = ETH_HWADDR_LEN;
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/* set MAC hardware address */
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netif->hwaddr[0] = heth.Init.MACAddr[0];
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netif->hwaddr[1] = heth.Init.MACAddr[1];
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netif->hwaddr[2] = heth.Init.MACAddr[2];
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netif->hwaddr[3] = heth.Init.MACAddr[3];
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netif->hwaddr[4] = heth.Init.MACAddr[4];
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netif->hwaddr[5] = heth.Init.MACAddr[5];
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/* maximum transfer unit */
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netif->mtu = 1500;
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/* Accept broadcast address and ARP traffic */
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/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
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#if LWIP_ARP
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netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
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#else
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netif->flags |= NETIF_FLAG_BROADCAST;
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#endif /* LWIP_ARP */
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if (ERR_OK != sys_sem_new(&s_xSemaphore, 1))
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{
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return -1;
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}
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#define NETIF_IN_TASK_STACK_SIZE (1024)
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#define NETIF_IN_TASK_PRIORITY (3)
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/* create the task that handles the ETH_MAC */
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sys_thread_new((char *)"Eth_if", eth_thread, netif, NETIF_IN_TASK_STACK_SIZE, NETIF_IN_TASK_PRIORITY);
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/* Enable MAC and DMA transmission and reception */
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(void)HAL_ETH_Start(&heth);
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/* Read Register Configuration */
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HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR, ®value);
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regvalue |= (PHY_ISFR_INT4);
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/* Enable Interrupt on change of link status */
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HAL_ETH_WritePHYRegister(&heth, PHY_ISFR , regvalue );
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/* Read Register Configuration */
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HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , ®value);
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#endif /* LWIP_ARP || LWIP_ETHERNET */
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return 0;
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}
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static int lan8742a_write(struct netif *netif, struct pbuf *p)
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{
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err_t errval;
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struct pbuf *q;
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uint8_t *buffer = (uint8_t *)(heth.TxDesc->Buffer1Addr);
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__IO ETH_DMADescTypeDef *DmaTxDesc;
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uint32_t framelength = 0;
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uint32_t bufferoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t payloadoffset = 0;
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DmaTxDesc = heth.TxDesc;
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bufferoffset = 0;
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/* copy frame from pbufs to driver buffers */
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for(q = p; q != NULL; q = q->next)
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{
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/* Is this buffer available? If not, goto error */
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if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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errval = ERR_USE;
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goto error;
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}
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/* Get bytes in current lwIP buffer */
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of data to copy is bigger than Tx buffer size*/
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while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
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{
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/* Copy data to Tx buffer*/
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memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
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/* Point to next descriptor */
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DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
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/* Check if the buffer is available */
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if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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errval = ERR_USE;
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goto error;
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}
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buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
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framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy the remaining bytes */
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memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
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bufferoffset = bufferoffset + byteslefttocopy;
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framelength = framelength + byteslefttocopy;
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}
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/* Prepare transmit descriptors to give to DMA */
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HAL_ETH_TransmitFrame(&heth, framelength);
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errval = ERR_OK;
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error:
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/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
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if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
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{
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/* Clear TUS ETHERNET DMA flag */
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heth.Instance->DMASR = ETH_DMASR_TUS;
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/* Resume DMA transmission*/
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heth.Instance->DMATPDR = 0;
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}
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return errval;
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}
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static struct pbuf * lan8742a_read(struct netif *netif)
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{
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struct pbuf *p = NULL;
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struct pbuf *q = NULL;
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uint16_t len = 0;
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uint8_t *buffer;
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__IO ETH_DMADescTypeDef *dmarxdesc;
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uint32_t bufferoffset = 0;
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uint32_t payloadoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t i=0;
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/* get received frame */
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if (HAL_ETH_GetReceivedFrame_IT(&heth) != HAL_OK)
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return NULL;
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = heth.RxFrameInfos.length;
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buffer = (uint8_t *)heth.RxFrameInfos.buffer;
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if (len > 0)
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{
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/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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}
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if (p != NULL)
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{
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dmarxdesc = heth.RxFrameInfos.FSRxDesc;
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bufferoffset = 0;
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for(q = p; q != NULL; q = q->next)
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{
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
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while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
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{
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/* Copy data to pbuf */
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memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
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/* Point to next descriptor */
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dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
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buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy remaining data in pbuf */
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memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
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}
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}
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/* Release descriptors to DMA */
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/* Point to first descriptor */
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dmarxdesc = heth.RxFrameInfos.FSRxDesc;
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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for (i=0; i< heth.RxFrameInfos.SegCount; i++)
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{
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dmarxdesc->Status |= ETH_DMARXDESC_OWN;
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dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
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}
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/* Clear Segment_Count */
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heth.RxFrameInfos.SegCount =0;
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/* When Rx Buffer unavailable flag is set: clear it and resume reception */
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if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
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{
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/* Clear RBUS ETHERNET DMA flag */
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heth.Instance->DMASR = ETH_DMASR_RBUS;
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/* Resume DMA reception */
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heth.Instance->DMARPDR = 0;
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}
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return p;
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}
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ethernetif_drv_t lan8742a_drv =
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{
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.init = lan8742a_init,
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.write = lan8742a_write,
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.read = lan8742a_read
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};
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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