384 lines
7.5 KiB
C
384 lines
7.5 KiB
C
/*
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* nrf24l01.c
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*
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* Created on: Mar 27, 2020
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* Author: ace
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*/
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#include "main.h"
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#include "nrf24l01.h"
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#include "tos_k.h"
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int nrf_init(SPI_HandleTypeDef* spi, GPIO_TypeDef* csn_gpio_port, uint16_t csn_pin, GPIO_TypeDef* ce_gpio_port, uint16_t ce_pin) {
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return nrf_hal_init(spi, csn_gpio_port, csn_pin, ce_gpio_port, ce_pin);
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}
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void nrf_flush_rx() {
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nrf_hal_write_cmd(CMD_FLUSH_RX);
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}
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void nrf_flush_tx() {
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nrf_hal_write_cmd(CMD_FLUSH_TX);
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}
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void nrf_delay(uint32_t delay) {
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tos_task_delay(delay);
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}
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int nrf_powerup() {
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return nrf_hal_set_reg_bit(REG_CONFIG, PWR_UP);
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}
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int nrf_powerdown() {
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return nrf_hal_clear_reg_bit(REG_CONFIG, PWR_UP);
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}
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void nrf_enable_rx_irq() {
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nrf_hal_clear_reg_bit(REG_CONFIG, MASK_RX_DR);
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}
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void nrf_disable_rx_irq() {
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nrf_hal_set_reg_bit(REG_CONFIG, MASK_RX_DR);
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}
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void nrf_enable_tx_irq() {
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nrf_hal_clear_reg_bit(REG_CONFIG, MASK_TX_DS);
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}
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void nrf_disable_tx_irq() {
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nrf_hal_set_reg_bit(REG_CONFIG, MASK_TX_DS);
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}
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void nrf_enable_max_rt_irq() {
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nrf_hal_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
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}
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void nrf_disable_max_rt_irq() {
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nrf_hal_clear_reg_bit(REG_CONFIG, MASK_MAX_RT);
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}
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void nrf_set_rf_channel(uint8_t channel) {
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channel &= 0x7F;
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nrf_hal_write_reg_byte(REG_RF_CH, channel);
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}
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int nrf_set_rxaddr(uint8_t pipe, uint8_t *addr, uint8_t addrlen) {
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if(addrlen >= 6 || pipe >= 6) {
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return -1;
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}
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if(pipe >= 2) {
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addrlen = 1;
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}
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uint8_t reg = REG_RX_ADDR_P0 + pipe;
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return nrf_hal_write_reg(reg, addr, addrlen);
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}
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int nrf_set_txaddr(uint8_t *addr, uint8_t addrlen) {
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if(addrlen >= 6) {
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return -1;
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}
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return nrf_hal_write_reg(REG_TX_ADDR, addr, addrlen);
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}
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int nrf_enable_rxaddr(uint8_t pipe) {
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if(pipe >= 6) {
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return -1;
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}
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nrf_hal_write_reg_byte(REG_EN_RXADDR, pipe);
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return 0;
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}
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void nrf_reset_registers() {
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nrf_hal_write_reg_byte(REG_CONFIG, _BV(EN_CRC));
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nrf_hal_write_reg_byte(REG_EN_AA, _BV(ENAA_P0) | _BV(ENAA_P1) | _BV(ENAA_P2) | _BV(ENAA_P3) | _BV(ENAA_P4) | _BV(ENAA_P5));
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nrf_hal_write_reg_byte(REG_EN_RXADDR, _BV(ERX_P0) | _BV(ERX_P1));
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nrf_hal_write_reg_byte(REG_SETUP_AW, _VV(AW_5BYTES, AW));
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nrf_hal_write_reg_byte(REG_SETUP_RETR, _VV(ARD_250us, ARD) | _VV(ARC_3, ARC));
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nrf_hal_write_reg_byte(REG_RF_CH, 0b00000010);
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nrf_hal_write_reg_byte(REG_RF_SETUP, _BV(RF_DR_HIGH) | _VV(RF_PWR_0dBm, RF_PWR));
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uint8_t status = 0;
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nrf_hal_read_reg_byte(REG_STATUS, &status);
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if(status & _BV(RX_DR)) {
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nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
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}
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if(status & _BV(TX_DS)) {
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nrf_hal_set_reg_bit(REG_STATUS, _BV(TX_DS));
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}
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if(status & _BV(MAX_RT)) {
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nrf_hal_set_reg_bit(REG_STATUS, _BV(MAX_RT));
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}
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nrf_hal_write_reg_byte(REG_RX_PW_P0, 0);
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nrf_hal_write_reg_byte(REG_RX_PW_P1, 0);
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nrf_hal_write_reg_byte(REG_RX_PW_P2, 0);
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nrf_hal_write_reg_byte(REG_RX_PW_P3, 0);
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nrf_hal_write_reg_byte(REG_RX_PW_P4, 0);
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nrf_hal_write_reg_byte(REG_RX_PW_P5, 0);
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nrf_hal_write_reg_byte(REG_DYNPD, 0);
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nrf_hal_write_reg_byte(REG_FEATURE, 0);
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uint8_t addrp0[] = {0xE7, 0xE7, 0xE7, 0xE7, 0xE7};
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uint8_t addrp1[] = {0xC2, 0xC2, 0xC2, 0xC2, 0xC2};
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nrf_hal_write_reg(REG_TX_ADDR, addrp0, 5);
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nrf_hal_write_reg(REG_RX_ADDR_P0, addrp0, 5);
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nrf_hal_write_reg(REG_RX_ADDR_P1, addrp1, 5);
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nrf_hal_write_reg_byte(REG_RX_ADDR_P2, 0xC3);
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nrf_hal_write_reg_byte(REG_RX_ADDR_P3, 0xC4);
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nrf_hal_write_reg_byte(REG_RX_ADDR_P4, 0xC5);
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nrf_hal_write_reg_byte(REG_RX_ADDR_P5, 0xC6);
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nrf_flush_rx();
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nrf_flush_tx();
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}
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void nrf_set_standby_mode() {
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nrf_hal_ce(0);
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nrf_powerdown();
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nrf_reset_registers();
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nrf_delay(10);
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nrf_powerup();
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nrf_delay(10); // 10m > 1.5~2ms
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}
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void nrf_set_receive_mode() {
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nrf_hal_set_reg_bit(REG_CONFIG, PRIM_RX);
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nrf_hal_ce(1);
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nrf_delay(1); // 1ms > 120~130us
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}
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void nrf_set_send_mode() {
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nrf_hal_clear_reg_bit(REG_CONFIG, PRIM_RX);
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nrf_hal_ce(1);
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nrf_delay(1); // 1ms > 120~130us
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}
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void nrf_enable_autoack(uint8_t pipe) {
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if(pipe >= 6) {
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return ;
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}
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nrf_hal_set_reg_bit(REG_EN_AA, pipe);
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}
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void nrf_disable_autoack(uint8_t pipe) {
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if(pipe >= 6) {
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return ;
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}
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nrf_hal_clear_reg_bit(REG_EN_AA, pipe);
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}
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void nrf_set_datarate(uint8_t dr) {
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if(NRF_1Mbps == dr) {
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dr = 0;
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} else if(NRF_2Mbps == dr) {
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nrf_hal_write_reg_byte(REG_RF_SETUP, 0b00001110);
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nrf_hal_write_reg_byte(REG_SETUP_RETR, 0b00010011);
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} else {
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}
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}
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int nrf_enable_dynamic_payload(uint8_t pipe) {
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if(pipe >= 6) {
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return -1;
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}
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uint8_t feature = 0;
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uint8_t dynpd = 0;
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nrf_hal_read_reg_byte(REG_FEATURE, &feature);
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nrf_hal_read_reg_byte(REG_DYNPD, &dynpd);
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feature |= _BV(EN_DPL);
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dynpd |= _BV(pipe);
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nrf_hal_write_reg_byte(REG_DYNPD, dynpd);
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nrf_hal_write_reg_byte(REG_FEATURE, feature);
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return 0;
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}
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int nrf_read_payload(uint8_t *buf, uint8_t *len) {
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nrf_hal_cmd_read_byte(CMD_R_RX_PL_WID, len);
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nrf_hal_cmd_read(CMD_R_RX_PAYLOAD, buf, *len);
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return 0;
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}
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int nrf_write_payload(uint8_t *buf, uint8_t len) {
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return nrf_hal_cmd_write(CMD_W_TX_PAYLOAD_NOACK, buf, len);
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}
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void print_addr(uint8_t pipe) {
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uint8_t addr[5];
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nrf_hal_read_reg(REG_RX_ADDR_P0+pipe, addr, 5);
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printf("pipe %u addr: ", pipe);
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for(int i=0; i<5; i++) {
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printf("%u ", addr[i]);
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}
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printf("\n");
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}
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uint8_t nrf_received_data = 0;
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uint8_t nrf_hal_test_rx() {
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uint8_t data = 0;
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extern SPI_HandleTypeDef hspi1;
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nrf_init(&hspi1, CSN_GPIO_Port, CSN_Pin, CE_GPIO_Port, CE_Pin);
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nrf_delay(200);
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nrf_hal_csn(1);
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nrf_hal_ce(0);
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nrf_delay(200);
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nrf_set_standby_mode();
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nrf_set_receive_mode();
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nrf_disable_rx_irq();
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nrf_set_rf_channel(64);
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nrf_set_datarate(NRF_2Mbps);
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uint8_t rxaddr[] = { 1, 2, 3, 4, 1 };
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uint8_t txaddr[] = { 1, 2, 3, 4, 2 };
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nrf_set_rxaddr(0, rxaddr, 5);
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nrf_set_txaddr(txaddr, 5);
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nrf_enable_dynamic_payload(0);
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nrf_enable_dynamic_payload(1);
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nrf_enable_rxaddr(0);
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nrf_enable_rxaddr(1);
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print_addr(0);
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print_addr(1);
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print_addr(2);
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nrf_flush_rx();
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while(1) {
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uint8_t buf[32];
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uint8_t len = 0;
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uint8_t status = 0;
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nrf_hal_read_reg_byte(REG_STATUS, &status);
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nrf_read_payload(buf, &len);
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if(status & _BV(RX_DR)) {
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nrf_hal_set_reg_bit(REG_STATUS, _BV(RX_DR));
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nrf_flush_rx();
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if(len > 0) {
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uint8_t pipe = status;
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pipe >>= 1;
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pipe &= 0x07;
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printf("received %u bytes from pipe %u: ", len, pipe);
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if(pipe >= 6) {
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printf("\n");
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continue;
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}
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for(int i=0; i<len; i++) {
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printf("%x ", buf[i]);
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}
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nrf_received_data = 1;
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printf("\n");
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}
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} else {
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printf("nodata %x\n", status);
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nrf_delay(100);
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}
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}
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return data;
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}
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uint8_t nrf_hal_test_tx() {
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uint8_t data = 0;
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extern SPI_HandleTypeDef hspi1;
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nrf_init(&hspi1, CSN_GPIO_Port, CSN_Pin, CE_GPIO_Port, CE_Pin);
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nrf_delay(200);
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nrf_hal_csn(1);
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nrf_hal_ce(0);
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nrf_delay(200);
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nrf_set_standby_mode();
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nrf_set_send_mode();
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nrf_set_rf_channel(100);
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nrf_set_datarate(NRF_2Mbps);
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nrf_enable_dynamic_payload(0);
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uint8_t txaddr[] = { 1, 2, 3, 4, 0 };
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nrf_set_txaddr(txaddr, 5);
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nrf_flush_rx();
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nrf_flush_tx();
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uint32_t cnt = 0;
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while(1) {
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nrf_flush_rx();
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nrf_flush_tx();
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uint8_t buf[] = {0x0A, 0x0C, 0x0E, cnt++ };
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nrf_write_payload(buf, sizeof(buf));
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while(1) {
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uint8_t status = 0;
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nrf_hal_read_reg_byte(REG_STATUS, &status);
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printf("status %x\n", status);
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if(status & _BV(MAX_RT)) {
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printf("send error....\n");
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nrf_hal_set_reg_bit(REG_STATUS, _BV(MAX_RT));
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nrf_flush_tx();
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break;
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}else if(status & _BV(TX_DS)) {
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printf("sended....\n");
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nrf_hal_set_reg_bit(REG_STATUS, _BV(TX_DS));
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break;
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} else {
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printf("sending....\n");
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}
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}
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nrf_delay(100);
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}
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return data;
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}
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uint8_t nrf_hal_test() {
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//return nrf_hal_test_rx();
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return nrf_hal_test_tx();
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}
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