410 lines
12 KiB
C
410 lines
12 KiB
C
/*
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* -------------------------------------------
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* MSP432 DriverLib - v3_40_00_10
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* -------------------------------------------
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*
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* --COPYRIGHT--,BSD,BSD
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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/* Standard Includes */
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#include <stdint.h>
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#include <stdbool.h>
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/* DriverLib Includes */
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#include <sysctl_a.h>
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#include <debug.h>
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void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
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uint_fast8_t *length, uint32_t **data_address)
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{
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/* TLV Structure Start Address */
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uint32_t *TLV_address = (uint32_t *) TLV_START;
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if(*TLV_address == 0xFFFFFFFF)
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{
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*length = 0;
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// Return 0 for TAG not found
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*data_address = 0;
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return;
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}
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while (((*TLV_address != tag)) // check for tag and instance
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&& (*TLV_address != TLV_TAGEND)) // do range check first
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{
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if (*TLV_address == tag)
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{
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if (instance == 0)
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{
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break;
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}
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/* Repeat until requested instance is reached */
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instance--;
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}
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TLV_address += (*(TLV_address + 1)) + 2;
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}
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/* Check if Tag match happened... */
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if (*TLV_address == tag)
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{
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/* Return length = Address + 1 */
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*length = (*(TLV_address + 1)) * 4;
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/* Return address of first data/value info = Address + 2 */
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*data_address = (uint32_t *) (TLV_address + 2);
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}
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// If there was no tag match and the end of TLV structure was reached..
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else
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{
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// Return 0 for TAG not found
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*length = 0;
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// Return 0 for TAG not found
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*data_address = 0;
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}
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}
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uint_least32_t SysCtl_A_getSRAMSize(void)
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{
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return SYSCTL_A->SRAM_SIZE;
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}
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uint_least32_t SysCtl_A_getFlashSize(void)
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{
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return SYSCTL_A->MAINFLASH_SIZE;
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}
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uint_least32_t SysCtl_A_getInfoFlashSize(void)
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{
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return SYSCTL_A->INFOFLASH_SIZE;
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}
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void SysCtl_A_disableNMISource(uint_fast8_t flags)
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{
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SYSCTL_A->NMI_CTLSTAT &= ~(flags);
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}
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void SysCtl_A_enableNMISource(uint_fast8_t flags)
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{
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SYSCTL_A->NMI_CTLSTAT |= flags;
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}
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uint_fast8_t SysCtl_A_getNMISourceStatus(void)
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{
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return SYSCTL_A->NMI_CTLSTAT;
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}
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void SysCtl_A_rebootDevice(void)
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{
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SYSCTL_A->REBOOT_CTL = (SYSCTL_A_REBOOT_CTL_REBOOT | SYSCTL_A_REBOOT_KEY);
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}
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void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices)
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{
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SYSCTL_A->PERIHALT_CTL &= ~devices;
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}
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void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices)
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{
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SYSCTL_A->PERIHALT_CTL |= devices;
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}
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void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType)
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{
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if (resetType)
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SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_TIMEOUT;
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else
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SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_TIMEOUT;
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}
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void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType)
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{
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if (resetType)
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SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_VIOLATION;
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else
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SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_VIOLATION;
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}
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void SysCtl_A_enableGlitchFilter(void)
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{
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SYSCTL_A->DIO_GLTFLT_CTL |= SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN;
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}
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void SysCtl_A_disableGlitchFilter(void)
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{
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SYSCTL_A->DIO_GLTFLT_CTL &= ~SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN;
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}
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uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage,
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uint32_t temperature)
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{
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return HWREG16(TLV_BASE + refVoltage + temperature);
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}
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bool SysCtl_A_enableSRAM(uint32_t addr)
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{
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uint32_t bankSize, bankBit;
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/* If SRAM is busy, return false */
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if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY))
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return false;
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/* Grabbing the bank size */
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bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS;
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bankBit = (addr - SRAM_BASE) / bankSize;
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if (bankBit < 32)
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{
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SYSCTL_A->SRAM_BANKEN_CTL0 |= (1 << bankBit);
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} else if (bankBit < 64)
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{
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SYSCTL_A->SRAM_BANKEN_CTL1 |= (1 << (bankBit - 32));
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} else if (bankBit < 96)
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{
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SYSCTL_A->SRAM_BANKEN_CTL2 |= (1 << (bankBit - 64));
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} else
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{
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SYSCTL_A->SRAM_BANKEN_CTL3 |= (1 << (bankBit - 96));
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}
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return true;
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}
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bool SysCtl_A_disableSRAM(uint32_t addr)
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{
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uint32_t bankSize, bankBit;
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/* If SRAM is busy, return false */
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if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY))
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return false;
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/* Grabbing the bank size */
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bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS;
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bankBit = (addr - SRAM_BASE) / bankSize;
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if (bankBit < 32)
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{
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SYSCTL_A->SRAM_BANKEN_CTL0 &= ~(0xFFFFFFFF << bankBit);
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} else if (bankBit < 64)
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{
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SYSCTL_A->SRAM_BANKEN_CTL1 &= ~(0xFFFFFFFF << (bankBit - 32));
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} else if (bankBit < 96)
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{
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SYSCTL_A->SRAM_BANKEN_CTL2 &= ~(0xFFFFFFFF << (bankBit - 64));
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} else
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{
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SYSCTL_A->SRAM_BANKEN_CTL3 &= ~(0xFFFFFFFF << (bankBit - 96));
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}
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return true;
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}
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bool SysCtl_A_enableSRAMRetention(uint32_t startAddr,
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uint32_t endAddr)
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{
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uint32_t blockSize, blockBitStart, blockBitEnd;
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if (startAddr > endAddr)
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return false;
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/* If SRAM is busy, return false */
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if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY))
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return false;
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/* Getting how big each bank is and how many blocks we have per bank */
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blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS;
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blockBitStart = (startAddr - SRAM_BASE) / blockSize;
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blockBitEnd = (endAddr - SRAM_BASE) / blockSize;
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if (blockBitStart < 32)
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{
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if (blockBitEnd < 32)
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{
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SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF >> (31 - blockBitEnd))
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& (0xFFFFFFFF << blockBitStart);
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return true;
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} else if (blockBitEnd < 64)
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{
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SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
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SYSCTL_A->SRAM_BLKRET_CTL1 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 32)));
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} else if (blockBitEnd < 96)
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{
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SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
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SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF;
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SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 64)));
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
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SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF;
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SYSCTL_A->SRAM_BLKRET_CTL2 = 0xFFFFFFFF;
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SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 96)));
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}
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} else if (blockBitStart < 64)
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{
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if (blockBitEnd < 64)
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{
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SYSCTL_A->SRAM_BLKRET_CTL1 |= ((0xFFFFFFFF
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>> (31 - (blockBitEnd - 32)))
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& (0xFFFFFFFF << (blockBitStart - 32)));
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return true;
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}
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SYSCTL_A->SRAM_BLKRET_CTL1 = (0xFFFFFFFF << (blockBitStart - 32));
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if (blockBitEnd < 96)
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 64)));
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 |= 0xFFFFFFFF;
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SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 96)));
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}
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} else if (blockBitStart < 96)
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{
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if (blockBitEnd < 96)
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 64)))
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& (0xFFFFFFFF << (blockBitStart - 64));
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return true;
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF << (blockBitStart - 64));
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SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
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>> (31 - (blockBitEnd - 96)));
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}
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF >> (31 - (blockBitEnd - 96)))
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& (0xFFFFFFFF << (blockBitStart - 96));
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}
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return true;
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}
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bool SysCtl_A_disableSRAMRetention(uint32_t startAddr,
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uint32_t endAddr)
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{
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uint32_t blockSize, blockBitStart, blockBitEnd;
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if (startAddr > endAddr)
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return false;
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/* If SRAM is busy, return false */
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if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY))
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return false;
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/* Getting how big each bank is and how many blocks we have per bank */
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blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS;
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blockBitStart = (startAddr - SRAM_BASE) / blockSize;
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blockBitEnd = (endAddr - SRAM_BASE) / blockSize;
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if (blockBitStart < 32)
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{
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if (blockBitEnd < 32)
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{
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SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF >> (31 - blockBitEnd))
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& (0xFFFFFFFF << blockBitStart));
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return true;
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}
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SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF << blockBitStart));
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if (blockBitEnd < 64)
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{
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SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF
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>> (31 - (blockBitEnd - 32))));
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} else if (blockBitEnd < 96)
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{
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SYSCTL_A->SRAM_BLKRET_CTL1 = 0;
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SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF
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>> (31 - (blockBitEnd - 64)));
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL1 = 0;
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SYSCTL_A->SRAM_BLKRET_CTL2 = 0;
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SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
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>> (31 - (blockBitEnd - 96)));
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}
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} else if (blockBitStart < 64)
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{
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if (blockBitEnd < 64)
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{
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SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF
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>> (31 - (blockBitEnd - 32)))
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& (0xFFFFFFFF << (blockBitStart - 32)));
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return true;
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}
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SYSCTL_A->SRAM_BLKRET_CTL1 &= ~(0xFFFFFFFF << (blockBitStart - 32));
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if (blockBitEnd < 96)
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF
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>> (31 - (blockBitEnd - 64)));
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 = 0;
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SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
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>> (31 - (blockBitEnd - 96)));
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}
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} else if (blockBitStart < 96)
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{
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if (blockBitEnd < 96)
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 &= ~((0xFFFFFFFF
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>> (31 - (blockBitEnd - 64)))
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& (0xFFFFFFFF << (blockBitStart - 64)));
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF << (blockBitStart - 64));
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SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
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>> (31 - (blockBitEnd - 96)));
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}
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} else
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{
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SYSCTL_A->SRAM_BLKRET_CTL3 &= ~((0xFFFFFFFF >> (31 - (blockBitEnd - 96)))
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& (0xFFFFFFFF << (blockBitStart - 96)));
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}
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return true;
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}
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