397 lines
14 KiB
C
397 lines
14 KiB
C
/*
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* -------------------------------------------
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* MSP432 DriverLib - v3_40_00_10
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* -------------------------------------------
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*
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* --COPYRIGHT--,BSD,BSD
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* Copyright (c) 2016, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* --/COPYRIGHT--*/
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#include <uart.h>
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#include <interrupt.h>
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#include <debug.h>
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#include <eusci.h>
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bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
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{
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bool retVal = true;
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ASSERT(
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(EUSCI_A_UART_MODE == config->uartMode)
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|| (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
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== config->uartMode)
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|| (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
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== config->uartMode)
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|| (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
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== config->uartMode));
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ASSERT(
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(EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
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|| (EUSCI_A_UART_CLOCKSOURCE_SMCLK
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== config->selectClockSource));
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ASSERT(
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(EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
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|| (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
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ASSERT(
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(EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
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|| (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
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ASSERT(
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(EUSCI_A_UART_NO_PARITY == config->parity)
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|| (EUSCI_A_UART_ODD_PARITY == config->parity)
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|| (EUSCI_A_UART_EVEN_PARITY == config->parity));
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/* Disable the USCI Module */
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
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/* Clock source select */
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EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
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(EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
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| config->selectClockSource;
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/* MSB, LSB select */
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if (config->msborLsbFirst)
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
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else
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
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/* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
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if (config->numberofStopBits)
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
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else
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
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/* Parity */
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switch (config->parity)
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{
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case EUSCI_A_UART_NO_PARITY:
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
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break;
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case EUSCI_A_UART_ODD_PARITY:
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
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break;
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case EUSCI_A_UART_EVEN_PARITY:
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
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break;
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}
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/* BaudRate Control Register */
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EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
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EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
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+ (config->firstModReg << 4) + config->overSampling);
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/* Asynchronous mode & 8 bit character select & clear mode */
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EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
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(EUSCI_A_CMSIS(moduleInstance)->CTLW0
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& ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
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| EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
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return retVal;
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}
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void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
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{
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/* If interrupts are not used, poll for flags */
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if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
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while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
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;
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EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
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}
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uint8_t UART_receiveData(uint32_t moduleInstance)
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{
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/* If interrupts are not used, poll for flags */
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if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_RXIE_OFS))
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while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
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;
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return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
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}
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void UART_enableModule(uint32_t moduleInstance)
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{
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/* Reset the UCSWRST bit to enable the USCI Module */
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
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}
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void UART_disableModule(uint32_t moduleInstance)
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{
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/* Set the UCSWRST bit to disable the USCI Module */
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
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}
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uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
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{
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ASSERT(
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0x00 != mask
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&& (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
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+ EUSCI_A_UART_OVERRUN_ERROR
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+ EUSCI_A_UART_PARITY_ERROR
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+ EUSCI_A_UART_BREAK_DETECT
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+ EUSCI_A_UART_RECEIVE_ERROR
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+ EUSCI_A_UART_ADDRESS_RECEIVED
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+ EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
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return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
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}
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void UART_setDormant(uint32_t moduleInstance)
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{
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
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}
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void UART_resetDormant(uint32_t moduleInstance)
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{
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
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}
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void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
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{
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/* Set UCTXADDR bit */
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
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/* Place next byte to be sent into the transmit buffer */
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EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
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}
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void UART_transmitBreak(uint32_t moduleInstance)
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{
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/* Set UCTXADDR bit */
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BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
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/* If current mode is automatic baud-rate detection */
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if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
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== (EUSCI_A_CMSIS(moduleInstance)->CTLW0
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& EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
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EUSCI_A_CMSIS(moduleInstance)->TXBUF =
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EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
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else
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EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
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/* If interrupts are not used, poll for flags */
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if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
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while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
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;
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}
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uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
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{
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return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
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}
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uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
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{
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return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
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}
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void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
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{
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ASSERT(
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(EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
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|| (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
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|| (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
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|| (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
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EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
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(EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
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| deglitchTime;
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}
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void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
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{
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uint_fast8_t locMask;
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ASSERT(
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!(mask
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& ~(EUSCI_A_UART_RECEIVE_INTERRUPT
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| EUSCI_A_UART_TRANSMIT_INTERRUPT
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| EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
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| EUSCI_A_UART_BREAKCHAR_INTERRUPT
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| EUSCI_A_UART_STARTBIT_INTERRUPT
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| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
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locMask = (mask
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& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
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| EUSCI_A_UART_STARTBIT_INTERRUPT
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| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
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EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
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locMask = (mask
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& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
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| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
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EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
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}
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void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
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{
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uint_fast8_t locMask;
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ASSERT(
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!(mask
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& ~(EUSCI_A_UART_RECEIVE_INTERRUPT
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| EUSCI_A_UART_TRANSMIT_INTERRUPT
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| EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
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| EUSCI_A_UART_BREAKCHAR_INTERRUPT
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| EUSCI_A_UART_STARTBIT_INTERRUPT
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| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
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locMask = (mask
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& (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
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| EUSCI_A_UART_STARTBIT_INTERRUPT
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| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
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EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
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locMask = (mask
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& (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
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| EUSCI_A_UART_BREAKCHAR_INTERRUPT));
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EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
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}
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uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
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{
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ASSERT(
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!(mask
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& ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
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| EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
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| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
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| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
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return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
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}
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uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
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{
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uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
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EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
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uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
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if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
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{
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intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
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}
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if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
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{
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intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
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}
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intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
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if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
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{
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intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
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}
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if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
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{
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intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
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}
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return intStatus;
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}
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void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
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{
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ASSERT(
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!(mask
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& ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
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| EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
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| EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
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| EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
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//Clear the UART interrupt source.
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EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
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}
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void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
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{
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switch (moduleInstance)
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{
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case EUSCI_A0_BASE:
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Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
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Interrupt_enableInterrupt(INT_EUSCIA0);
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break;
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case EUSCI_A1_BASE:
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Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
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Interrupt_enableInterrupt(INT_EUSCIA1);
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break;
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#ifdef EUSCI_A2_BASE
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case EUSCI_A2_BASE:
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Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
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Interrupt_enableInterrupt(INT_EUSCIA2);
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break;
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#endif
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#ifdef EUSCI_A3_BASE
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case EUSCI_A3_BASE:
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Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
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Interrupt_enableInterrupt(INT_EUSCIA3);
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break;
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#endif
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default:
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ASSERT(false);
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}
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}
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void UART_unregisterInterrupt(uint32_t moduleInstance)
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{
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switch (moduleInstance)
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{
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case EUSCI_A0_BASE:
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Interrupt_disableInterrupt(INT_EUSCIA0);
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Interrupt_unregisterInterrupt(INT_EUSCIA0);
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break;
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case EUSCI_A1_BASE:
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Interrupt_disableInterrupt(INT_EUSCIA1);
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Interrupt_unregisterInterrupt(INT_EUSCIA1);
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break;
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#ifdef EUSCI_A2_BASE
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case EUSCI_A2_BASE:
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Interrupt_disableInterrupt(INT_EUSCIA2);
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Interrupt_unregisterInterrupt(INT_EUSCIA2);
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break;
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#endif
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#ifdef EUSCI_A3_BASE
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case EUSCI_A3_BASE:
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Interrupt_disableInterrupt(INT_EUSCIA3);
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Interrupt_unregisterInterrupt(INT_EUSCIA3);
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break;
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#endif
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default:
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ASSERT(false);
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}
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}
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