stm32f10x_i2c.h 28 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f10x_i2c.h
  4. * @author MCD Application Team
  5. * @version V3.6.2
  6. * @date 17-September-2021
  7. * @brief This file contains all the functions prototypes for the I2C firmware
  8. * library.
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * Copyright (c) 2012 STMicroelectronics.
  13. * All rights reserved.
  14. *
  15. * This software is licensed under terms that can be found in the LICENSE file
  16. * in the root directory of this software component.
  17. * If no LICENSE file comes with this software, it is provided AS-IS.
  18. *
  19. ******************************************************************************
  20. */
  21. /* Define to prevent recursive inclusion -------------------------------------*/
  22. #ifndef __STM32F10x_I2C_H
  23. #define __STM32F10x_I2C_H
  24. #ifdef __cplusplus
  25. extern "C" {
  26. #endif
  27. /* Includes ------------------------------------------------------------------*/
  28. #include "stm32f10x.h"
  29. /** @addtogroup STM32F10x_StdPeriph_Driver
  30. * @{
  31. */
  32. /** @addtogroup I2C
  33. * @{
  34. */
  35. /** @defgroup I2C_Exported_Types
  36. * @{
  37. */
  38. /**
  39. * @brief I2C Init structure definition
  40. */
  41. typedef struct
  42. {
  43. uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
  44. This parameter must be set to a value lower than 400kHz */
  45. uint16_t I2C_Mode; /*!< Specifies the I2C mode.
  46. This parameter can be a value of @ref I2C_mode */
  47. uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
  48. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
  49. uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
  50. This parameter can be a 7-bit or 10-bit address. */
  51. uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
  52. This parameter can be a value of @ref I2C_acknowledgement */
  53. uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
  54. This parameter can be a value of @ref I2C_acknowledged_address */
  55. }I2C_InitTypeDef;
  56. /**
  57. * @}
  58. */
  59. /** @defgroup I2C_Exported_Constants
  60. * @{
  61. */
  62. #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
  63. ((PERIPH) == I2C2))
  64. /** @defgroup I2C_mode
  65. * @{
  66. */
  67. #define I2C_Mode_I2C ((uint16_t)0x0000)
  68. #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
  69. #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
  70. #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
  71. ((MODE) == I2C_Mode_SMBusDevice) || \
  72. ((MODE) == I2C_Mode_SMBusHost))
  73. /**
  74. * @}
  75. */
  76. /** @defgroup I2C_duty_cycle_in_fast_mode
  77. * @{
  78. */
  79. #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
  80. #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
  81. #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
  82. ((CYCLE) == I2C_DutyCycle_2))
  83. /**
  84. * @}
  85. */
  86. /** @defgroup I2C_acknowledgement
  87. * @{
  88. */
  89. #define I2C_Ack_Enable ((uint16_t)0x0400)
  90. #define I2C_Ack_Disable ((uint16_t)0x0000)
  91. #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
  92. ((STATE) == I2C_Ack_Disable))
  93. /**
  94. * @}
  95. */
  96. /** @defgroup I2C_transfer_direction
  97. * @{
  98. */
  99. #define I2C_Direction_Transmitter ((uint8_t)0x00)
  100. #define I2C_Direction_Receiver ((uint8_t)0x01)
  101. #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
  102. ((DIRECTION) == I2C_Direction_Receiver))
  103. /**
  104. * @}
  105. */
  106. /** @defgroup I2C_acknowledged_address
  107. * @{
  108. */
  109. #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
  110. #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
  111. #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
  112. ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
  113. /**
  114. * @}
  115. */
  116. /** @defgroup I2C_registers
  117. * @{
  118. */
  119. #define I2C_Register_CR1 ((uint8_t)0x00)
  120. #define I2C_Register_CR2 ((uint8_t)0x04)
  121. #define I2C_Register_OAR1 ((uint8_t)0x08)
  122. #define I2C_Register_OAR2 ((uint8_t)0x0C)
  123. #define I2C_Register_DR ((uint8_t)0x10)
  124. #define I2C_Register_SR1 ((uint8_t)0x14)
  125. #define I2C_Register_SR2 ((uint8_t)0x18)
  126. #define I2C_Register_CCR ((uint8_t)0x1C)
  127. #define I2C_Register_TRISE ((uint8_t)0x20)
  128. #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
  129. ((REGISTER) == I2C_Register_CR2) || \
  130. ((REGISTER) == I2C_Register_OAR1) || \
  131. ((REGISTER) == I2C_Register_OAR2) || \
  132. ((REGISTER) == I2C_Register_DR) || \
  133. ((REGISTER) == I2C_Register_SR1) || \
  134. ((REGISTER) == I2C_Register_SR2) || \
  135. ((REGISTER) == I2C_Register_CCR) || \
  136. ((REGISTER) == I2C_Register_TRISE))
  137. /**
  138. * @}
  139. */
  140. /** @defgroup I2C_SMBus_alert_pin_level
  141. * @{
  142. */
  143. #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
  144. #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
  145. #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
  146. ((ALERT) == I2C_SMBusAlert_High))
  147. /**
  148. * @}
  149. */
  150. /** @defgroup I2C_PEC_position
  151. * @{
  152. */
  153. #define I2C_PECPosition_Next ((uint16_t)0x0800)
  154. #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
  155. #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
  156. ((POSITION) == I2C_PECPosition_Current))
  157. /**
  158. * @}
  159. */
  160. /** @defgroup I2C_NCAK_position
  161. * @{
  162. */
  163. #define I2C_NACKPosition_Next ((uint16_t)0x0800)
  164. #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
  165. #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
  166. ((POSITION) == I2C_NACKPosition_Current))
  167. /**
  168. * @}
  169. */
  170. /** @defgroup I2C_interrupts_definition
  171. * @{
  172. */
  173. #define I2C_IT_BUF ((uint16_t)0x0400)
  174. #define I2C_IT_EVT ((uint16_t)0x0200)
  175. #define I2C_IT_ERR ((uint16_t)0x0100)
  176. #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
  177. /**
  178. * @}
  179. */
  180. /** @defgroup I2C_interrupts_definition
  181. * @{
  182. */
  183. #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
  184. #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
  185. #define I2C_IT_PECERR ((uint32_t)0x01001000)
  186. #define I2C_IT_OVR ((uint32_t)0x01000800)
  187. #define I2C_IT_AF ((uint32_t)0x01000400)
  188. #define I2C_IT_ARLO ((uint32_t)0x01000200)
  189. #define I2C_IT_BERR ((uint32_t)0x01000100)
  190. #define I2C_IT_TXE ((uint32_t)0x06000080)
  191. #define I2C_IT_RXNE ((uint32_t)0x06000040)
  192. #define I2C_IT_STOPF ((uint32_t)0x02000010)
  193. #define I2C_IT_ADD10 ((uint32_t)0x02000008)
  194. #define I2C_IT_BTF ((uint32_t)0x02000004)
  195. #define I2C_IT_ADDR ((uint32_t)0x02000002)
  196. #define I2C_IT_SB ((uint32_t)0x02000001)
  197. #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
  198. #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
  199. ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
  200. ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
  201. ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
  202. ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
  203. ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
  204. ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
  205. /**
  206. * @}
  207. */
  208. /** @defgroup I2C_flags_definition
  209. * @{
  210. */
  211. /**
  212. * @brief SR2 register flags
  213. */
  214. #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
  215. #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
  216. #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
  217. #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
  218. #define I2C_FLAG_TRA ((uint32_t)0x00040000)
  219. #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
  220. #define I2C_FLAG_MSL ((uint32_t)0x00010000)
  221. /**
  222. * @brief SR1 register flags
  223. */
  224. #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
  225. #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
  226. #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
  227. #define I2C_FLAG_OVR ((uint32_t)0x10000800)
  228. #define I2C_FLAG_AF ((uint32_t)0x10000400)
  229. #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
  230. #define I2C_FLAG_BERR ((uint32_t)0x10000100)
  231. #define I2C_FLAG_TXE ((uint32_t)0x10000080)
  232. #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
  233. #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
  234. #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
  235. #define I2C_FLAG_BTF ((uint32_t)0x10000004)
  236. #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
  237. #define I2C_FLAG_SB ((uint32_t)0x10000001)
  238. #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
  239. #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
  240. ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
  241. ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
  242. ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
  243. ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
  244. ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
  245. ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
  246. ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
  247. ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
  248. ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
  249. ((FLAG) == I2C_FLAG_SB))
  250. /**
  251. * @}
  252. */
  253. /** @defgroup I2C_Events
  254. * @{
  255. */
  256. /*========================================
  257. I2C Master Events (Events grouped in order of communication)
  258. ==========================================*/
  259. /**
  260. * @brief Communication start
  261. *
  262. * After sending the START condition (I2C_GenerateSTART() function) the master
  263. * has to wait for this event. It means that the Start condition has been correctly
  264. * released on the I2C bus (the bus is free, no other devices is communicating).
  265. *
  266. */
  267. /* --EV5 */
  268. #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
  269. /**
  270. * @brief Address Acknowledge
  271. *
  272. * After checking on EV5 (start condition correctly released on the bus), the
  273. * master sends the address of the slave(s) with which it will communicate
  274. * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
  275. * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
  276. * his address. If an acknowledge is sent on the bus, one of the following events will
  277. * be set:
  278. *
  279. * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
  280. * event is set.
  281. *
  282. * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
  283. * is set
  284. *
  285. * 3) In case of 10-Bit addressing mode, the master (just after generating the START
  286. * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
  287. * function). Then master should wait on EV9. It means that the 10-bit addressing
  288. * header has been correctly sent on the bus. Then master should send the second part of
  289. * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
  290. * should wait for event EV6.
  291. *
  292. */
  293. /* --EV6 */
  294. #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
  295. #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
  296. /* --EV9 */
  297. #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
  298. /**
  299. * @brief Communication events
  300. *
  301. * If a communication is established (START condition generated and slave address
  302. * acknowledged) then the master has to check on one of the following events for
  303. * communication procedures:
  304. *
  305. * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
  306. * the data received from the slave (I2C_ReceiveData() function).
  307. *
  308. * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
  309. * function) then to wait on event EV8 or EV8_2.
  310. * These two events are similar:
  311. * - EV8 means that the data has been written in the data register and is
  312. * being shifted out.
  313. * - EV8_2 means that the data has been physically shifted out and output
  314. * on the bus.
  315. * In most cases, using EV8 is sufficient for the application.
  316. * Using EV8_2 leads to a slower communication but ensure more reliable test.
  317. * EV8_2 is also more suitable than EV8 for testing on the last data transmission
  318. * (before Stop condition generation).
  319. *
  320. * @note In case the user software does not guarantee that this event EV7 is
  321. * managed before the current byte end of transfer, then user may check on EV7
  322. * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
  323. * In this case the communication may be slower.
  324. *
  325. */
  326. /* Master RECEIVER mode -----------------------------*/
  327. /* --EV7 */
  328. #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
  329. /* Master TRANSMITTER mode --------------------------*/
  330. /* --EV8 */
  331. #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
  332. /* --EV8_2 */
  333. #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
  334. /*========================================
  335. I2C Slave Events (Events grouped in order of communication)
  336. ==========================================*/
  337. /**
  338. * @brief Communication start events
  339. *
  340. * Wait on one of these events at the start of the communication. It means that
  341. * the I2C peripheral detected a Start condition on the bus (generated by master
  342. * device) followed by the peripheral address. The peripheral generates an ACK
  343. * condition on the bus (if the acknowledge feature is enabled through function
  344. * I2C_AcknowledgeConfig()) and the events listed above are set :
  345. *
  346. * 1) In normal case (only one address managed by the slave), when the address
  347. * sent by the master matches the own address of the peripheral (configured by
  348. * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
  349. * (where XXX could be TRANSMITTER or RECEIVER).
  350. *
  351. * 2) In case the address sent by the master matches the second address of the
  352. * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
  353. * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
  354. * (where XXX could be TRANSMITTER or RECEIVER) are set.
  355. *
  356. * 3) In case the address sent by the master is General Call (address 0x00) and
  357. * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
  358. * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
  359. *
  360. */
  361. /* --EV1 (all the events below are variants of EV1) */
  362. /* 1) Case of One Single Address managed by the slave */
  363. #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
  364. #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
  365. /* 2) Case of Dual address managed by the slave */
  366. #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
  367. #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
  368. /* 3) Case of General Call enabled for the slave */
  369. #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
  370. /**
  371. * @brief Communication events
  372. *
  373. * Wait on one of these events when EV1 has already been checked and:
  374. *
  375. * - Slave RECEIVER mode:
  376. * - EV2: When the application is expecting a data byte to be received.
  377. * - EV4: When the application is expecting the end of the communication: master
  378. * sends a stop condition and data transmission is stopped.
  379. *
  380. * - Slave Transmitter mode:
  381. * - EV3: When a byte has been transmitted by the slave and the application is expecting
  382. * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
  383. * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
  384. * used when the user software doesn't guarantee the EV3 is managed before the
  385. * current byte end of transfer.
  386. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
  387. * shall end (before sending the STOP condition). In this case slave has to stop sending
  388. * data bytes and expect a Stop condition on the bus.
  389. *
  390. * @note In case the user software does not guarantee that the event EV2 is
  391. * managed before the current byte end of transfer, then user may check on EV2
  392. * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
  393. * In this case the communication may be slower.
  394. *
  395. */
  396. /* Slave RECEIVER mode --------------------------*/
  397. /* --EV2 */
  398. #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
  399. /* --EV4 */
  400. #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
  401. /* Slave TRANSMITTER mode -----------------------*/
  402. /* --EV3 */
  403. #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
  404. #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
  405. /* --EV3_2 */
  406. #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
  407. /*=========================== End of Events Description ==========================================*/
  408. #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
  409. ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
  410. ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
  411. ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
  412. ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
  413. ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
  414. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
  415. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
  416. ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
  417. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
  418. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
  419. ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
  420. ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
  421. ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
  422. ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
  423. ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
  424. ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
  425. ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
  426. ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
  427. ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
  428. /**
  429. * @}
  430. */
  431. /** @defgroup I2C_own_address1
  432. * @{
  433. */
  434. #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
  435. /**
  436. * @}
  437. */
  438. /** @defgroup I2C_clock_speed
  439. * @{
  440. */
  441. #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
  442. /**
  443. * @}
  444. */
  445. /**
  446. * @}
  447. */
  448. /** @defgroup I2C_Exported_Macros
  449. * @{
  450. */
  451. /**
  452. * @}
  453. */
  454. /** @defgroup I2C_Exported_Functions
  455. * @{
  456. */
  457. void I2C_DeInit(I2C_TypeDef* I2Cx);
  458. void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
  459. void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
  460. void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  461. void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  462. void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  463. void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
  464. void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
  465. void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
  466. void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
  467. void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  468. void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  469. void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
  470. void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
  471. uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
  472. void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
  473. uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
  474. void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  475. void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
  476. void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
  477. void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
  478. void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
  479. void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
  480. uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
  481. void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  482. void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
  483. void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
  484. /**
  485. * @brief
  486. ****************************************************************************************
  487. *
  488. * I2C State Monitoring Functions
  489. *
  490. ****************************************************************************************
  491. * This I2C driver provides three different ways for I2C state monitoring
  492. * depending on the application requirements and constraints:
  493. *
  494. *
  495. * 1) Basic state monitoring:
  496. * Using I2C_CheckEvent() function:
  497. * It compares the status registers (SR1 and SR2) content to a given event
  498. * (can be the combination of one or more flags).
  499. * It returns SUCCESS if the current status includes the given flags
  500. * and returns ERROR if one or more flags are missing in the current status.
  501. * - When to use:
  502. * - This function is suitable for most applications as well as for startup
  503. * activity since the events are fully described in the product reference manual
  504. * (RM0008).
  505. * - It is also suitable for users who need to define their own events.
  506. * - Limitations:
  507. * - If an error occurs (ie. error flags are set besides to the monitored flags),
  508. * the I2C_CheckEvent() function may return SUCCESS despite the communication
  509. * hold or corrupted real state.
  510. * In this case, it is advised to use error interrupts to monitor the error
  511. * events and handle them in the interrupt IRQ handler.
  512. *
  513. * @note
  514. * For error management, it is advised to use the following functions:
  515. * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  516. * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
  517. * Where x is the peripheral instance (I2C1, I2C2 ...)
  518. * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
  519. * in order to determine which error occurred.
  520. * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
  521. * and/or I2C_GenerateStop() in order to clear the error flag and source,
  522. * and return to correct communication status.
  523. *
  524. *
  525. * 2) Advanced state monitoring:
  526. * Using the function I2C_GetLastEvent() which returns the image of both status
  527. * registers in a single word (uint32_t) (Status Register 2 value is shifted left
  528. * by 16 bits and concatenated to Status Register 1).
  529. * - When to use:
  530. * - This function is suitable for the same applications above but it allows to
  531. * overcome the limitations of I2C_GetFlagStatus() function (see below).
  532. * The returned value could be compared to events already defined in the
  533. * library (stm32f10x_i2c.h) or to custom values defined by user.
  534. * - This function is suitable when multiple flags are monitored at the same time.
  535. * - At the opposite of I2C_CheckEvent() function, this function allows user to
  536. * choose when an event is accepted (when all events flags are set and no
  537. * other flags are set or just when the needed flags are set like
  538. * I2C_CheckEvent() function).
  539. * - Limitations:
  540. * - User may need to define his own events.
  541. * - Same remark concerning the error management is applicable for this
  542. * function if user decides to check only regular communication flags (and
  543. * ignores error flags).
  544. *
  545. *
  546. * 3) Flag-based state monitoring:
  547. * Using the function I2C_GetFlagStatus() which simply returns the status of
  548. * one single flag (ie. I2C_FLAG_RXNE ...).
  549. * - When to use:
  550. * - This function could be used for specific applications or in debug phase.
  551. * - It is suitable when only one flag checking is needed (most I2C events
  552. * are monitored through multiple flags).
  553. * - Limitations:
  554. * - When calling this function, the Status register is accessed. Some flags are
  555. * cleared when the status register is accessed. So checking the status
  556. * of one Flag, may clear other ones.
  557. * - Function may need to be called twice or more in order to monitor one
  558. * single event.
  559. *
  560. */
  561. /**
  562. *
  563. * 1) Basic state monitoring
  564. *******************************************************************************
  565. */
  566. ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
  567. /**
  568. *
  569. * 2) Advanced state monitoring
  570. *******************************************************************************
  571. */
  572. uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
  573. /**
  574. *
  575. * 3) Flag-based state monitoring
  576. *******************************************************************************
  577. */
  578. FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
  579. /**
  580. *
  581. *******************************************************************************
  582. */
  583. void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
  584. ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
  585. void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
  586. #ifdef __cplusplus
  587. }
  588. #endif
  589. #endif /*__STM32F10x_I2C_H */
  590. /**
  591. * @}
  592. */
  593. /**
  594. * @}
  595. */
  596. /**
  597. * @}
  598. */