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divide bumblebee and spike irq trap entry code

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This commit is contained in:
acevest
2019-10-05 15:48:45 +08:00
parent 08170b3490
commit 2d419440f3
9 changed files with 392 additions and 121 deletions
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167
arch/risc-v/bumblebee/gcc/riscv_port_s.S Normal file
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@@ -0,0 +1,167 @@
#include "port.h"
.global irq_entry
.global trap_entry
.extern k_curr_task
.extern k_next_task
.extern k_task_irq_switch_flag
.align 2
irq_entry:
addi sp, sp, -32*REGBYTES
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
csrr t0, mepc
sw t0, 0*REGBYTES(sp)
csrr t0, mstatus
sw t0, 1*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
csrr a0, mcause
mv a1, sp
slli a0, a0, 16
srli a0, a0, 16
call cpu_irq_entry
la t0, k_task_irq_switch_flag
lw t1, (t0)
beqz t1, irq_restore
sw zero,(t0)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
// switch task
// k_curr_task = k_next_task
la t1, k_next_task // t1 = &k_next_task
lw t1, (t1) // t1 = k_next_task
sw t1, (t0)
// load new task sp
lw sp, (t1)
irq_restore:
// restore context
lw t0, 0*REGBYTES(sp)
csrw mepc, t0
lw t0, 1*REGBYTES(sp)
csrw mstatus, t0
lw x1, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
lw x16, 16*REGBYTES(sp)
lw x17, 17*REGBYTES(sp)
lw x18, 18*REGBYTES(sp)
lw x19, 19*REGBYTES(sp)
lw x20, 20*REGBYTES(sp)
lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
lw x23, 23*REGBYTES(sp)
lw x24, 24*REGBYTES(sp)
lw x25, 25*REGBYTES(sp)
lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
lw x28, 28*REGBYTES(sp)
lw x29, 29*REGBYTES(sp)
lw x30, 30*REGBYTES(sp)
lw x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
.align 2
trap_entry:
addi sp, sp, -32*REGBYTES
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
csrr t0, mepc
sw t0, 0*REGBYTES(sp)
csrr t0, mstatus
sw t0, 1*REGBYTES(sp)
call cpu_trap_entry
1:
j 1b

7
arch/risc-v/rv32i/gcc/port.h
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@@ -18,6 +18,8 @@
#ifndef _PORT_H_ #ifndef _PORT_H_
#define _PORT_H_ #define _PORT_H_
#ifndef __ASSEMBLER__
__PORT__ void port_int_disable(void); __PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void); __PORT__ void port_int_enable(void);
@@ -69,4 +71,9 @@ __PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void); __PORT__ void port_fault_diagnosis(void);
#endif #endif
#endif /* __ASSEMBLER__ */
#define REGBYTES 4
#endif /* _PORT_H_ */ #endif /* _PORT_H_ */

194
arch/risc-v/rv32i/gcc/port_s.S
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@@ -65,42 +65,23 @@ port_systick_pending_reset:
csrc mip, t0 csrc mip, t0
ret ret
.align 2
.type port_sched_start, %function
port_sched_start:
// enable timer interrupt
li t0, MIE_MTIE
csrs mie, t0
.macro SAVE_CONTEXT // load sp from k_curr_task->sp
addi sp, sp, -32*REGBYTES la t0, k_curr_task // t0 = &k_curr_task
sw x1, 2*REGBYTES(sp) lw t0, (t0) // t0 = &(k_curr_task->sp)
sw x3, 3*REGBYTES(sp) lw sp, (t0) // sp = k_curr_task->sp
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
.endm
.macro RESTORE_CONTEXT // save sp to stack
addi t1, sp, 32*REGBYTES
sw t1, (t0)
// restore context
lw t0, 0*REGBYTES(sp) lw t0, 0*REGBYTES(sp)
csrw mepc, t0 csrw mepc, t0
@@ -139,25 +120,6 @@ port_systick_pending_reset:
lw x31, 31*REGBYTES(sp) lw x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES addi sp, sp, 32*REGBYTES
.endm
.align 2
.type port_sched_start, %function
port_sched_start:
// enable timer interrupt
li t0, MIE_MTIE
csrs mie, t0
// load sp from k_curr_task->sp
la t0, k_curr_task // t0 = &k_curr_task
lw t0, (t0) // t0 = &(k_curr_task->sp)
lw sp, (t0) // sp = k_curr_task->sp
// save sp to stack
addi t1, sp, 32*REGBYTES
sw t1, (t0)
RESTORE_CONTEXT
mret mret
@@ -165,7 +127,38 @@ port_sched_start:
.align 2 .align 2
.type port_context_switch, %function .type port_context_switch, %function
port_context_switch: port_context_switch:
SAVE_CONTEXT addi sp, sp, -32*REGBYTES
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
sw ra, 0*REGBYTES(sp) sw ra, 0*REGBYTES(sp)
@@ -188,59 +181,44 @@ port_context_switch:
// load new task sp // load new task sp
lw sp, (t1) lw sp, (t1)
RESTORE_CONTEXT // restore context
lw t0, 0*REGBYTES(sp)
mret csrw mepc, t0
.align 2 lw t0, 1*REGBYTES(sp)
.global trap_entry csrw mstatus, t0
.global irq_entry
trap_entry: lw x1, 2*REGBYTES(sp)
irq_entry: lw x3, 3*REGBYTES(sp)
SAVE_CONTEXT lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
csrr t0, mepc lw x6, 6*REGBYTES(sp)
sw t0, 0*REGBYTES(sp) lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
csrr t0, mstatus lw x9, 9*REGBYTES(sp)
sw t0, 1*REGBYTES(sp) lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
// save sp to k_curr_task.sp lw x12, 12*REGBYTES(sp)
la t0, k_curr_task // t0 = &k_curr_task lw x13, 13*REGBYTES(sp)
lw t1, (t0) lw x14, 14*REGBYTES(sp)
sw sp, (t1) lw x15, 15*REGBYTES(sp)
lw x16, 16*REGBYTES(sp)
csrr a0, mcause lw x17, 17*REGBYTES(sp)
mv a1, sp lw x18, 18*REGBYTES(sp)
bltz a0, irq lw x19, 19*REGBYTES(sp)
call cpu_trap_entry lw x20, 20*REGBYTES(sp)
j irq_restore lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
irq: lw x23, 23*REGBYTES(sp)
slli a0, a0, 16 lw x24, 24*REGBYTES(sp)
srli a0, a0, 16 lw x25, 25*REGBYTES(sp)
call cpu_irq_entry lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
la t0, k_task_irq_switch_flag lw x28, 28*REGBYTES(sp)
lw t1, (t0) lw x29, 29*REGBYTES(sp)
beqz t1, irq_restore lw x30, 30*REGBYTES(sp)
sw zero,(t0) lw x31, 31*REGBYTES(sp)
// save sp to k_curr_task.sp addi sp, sp, 32*REGBYTES
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
// switch task
// k_curr_task = k_next_task
la t1, k_next_task // t1 = &k_next_task
lw t1, (t1) // t1 = k_next_task
sw t1, (t0)
// load new task sp
lw sp, (t1)
irq_restore:
RESTORE_CONTEXT
mret mret

120
arch/risc-v/spike/gcc/riscv_port_s.S Normal file
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@@ -0,0 +1,120 @@
.equ REGBYTES, 4
.align 2
.global rv32_trap_entry
rv32_trap_entry:
addi sp, sp, -32*REGBYTES
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
csrr t0, mepc
sw t0, 0*REGBYTES(sp)
csrr t0, mstatus
sw t0, 1*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
csrr a0, mcause
mv a1, sp
bltz a0, handle_irq
call cpu_trap_entry
j irq_restore
handle_irq:
slli a0, a0, 16
srli a0, a0, 16
call cpu_irq_entry
la t0, k_task_irq_switch_flag
lw t1, (t0)
beqz t1, irq_restore
sw zero,(t0)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
// switch task
// k_curr_task = k_next_task
la t1, k_next_task // t1 = &k_next_task
lw t1, (t1) // t1 = k_next_task
sw t1, (t0)
// load new task sp
lw sp, (t1)
irq_restore:
// restore context
lw t0, 0*REGBYTES(sp)
csrw mepc, t0
lw t0, 1*REGBYTES(sp)
csrw mstatus, t0
lw x1, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
lw x16, 16*REGBYTES(sp)
lw x17, 17*REGBYTES(sp)
lw x18, 18*REGBYTES(sp)
lw x19, 19*REGBYTES(sp)
lw x20, 20*REGBYTES(sp)
lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
lw x23, 23*REGBYTES(sp)
lw x24, 24*REGBYTES(sp)
lw x25, 25*REGBYTES(sp)
lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
lw x28, 28*REGBYTES(sp)
lw x29, 29*REGBYTES(sp)
lw x30, 30*REGBYTES(sp)
lw x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret

2
board/GD32VF103C_START/eclipse/hello_world/.cproject
View File

@@ -105,6 +105,8 @@
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/GD32VF103_Firmware_Library/RISCV/drivers}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/GD32VF103_Firmware_Library/RISCV/drivers}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/rv32i}&quot;"/>
</option> </option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.asmlisting.842125273" name="Generate assembler listing (-Wa,-adhlns=&quot;$@.lst&quot;)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.asmlisting" useByScannerDiscovery="false" value="true" valueType="boolean"/> <option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.asmlisting.842125273" name="Generate assembler listing (-Wa,-adhlns=&quot;$@.lst&quot;)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.asmlisting" useByScannerDiscovery="false" value="true" valueType="boolean"/>

2
board/GD32VF103C_START/eclipse/hello_world/main.c
View File

@@ -27,7 +27,7 @@ void task2(void *pdata)
share++; share++;
for(int i=0; i<5; i++) { for(int i=0; i<5; i++) {
printf("hello world from %s cnt: %08x\n", __func__, task_cnt2--); printf("hello world from %s cnt: %08x\n", __func__, task_cnt2--);
tos_task_delay(10); tos_task_delay(50);
} }
tos_sem_post(&sem); tos_sem_post(&sem);
} }

1
board/QEMU_Spike/GCC/demo/Makefile
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@@ -54,6 +54,7 @@ ASM_SOURCES =
ASM_SOURCES_S = \ ASM_SOURCES_S = \
$(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \ $(TOP_DIR)/arch/risc-v/rv32i/gcc/port_s.S \
$(TOP_DIR)/arch/risc-v/spike/gcc/riscv_port_s.S \
start.S start.S

9
board/QEMU_Spike/GCC/demo/start.S
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@@ -1,15 +1,12 @@
// See LICENSE for license details. .align 2
#include "riscv_encoding.h"
.section .text.entry .section .text.entry
.globl _start .globl _start
.type _start,@function .type _start,@function
_start: _start:
csrc mstatus, MSTATUS_MIE csrc mstatus, 0x00000008
csrw mie, 0 csrw mie, 0
la t0, trap_entry la t0, rv32_trap_entry
csrw mtvec, t0 csrw mtvec, t0
la sp, _stack_top la sp, _stack_top

9
board/QEMU_Spike/eclipse/demo/start.S
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@@ -1,15 +1,14 @@
// See LICENSE for license details. .extern rv32_trap_entry
#include "riscv_encoding.h"
.align 2
.section .text.entry .section .text.entry
.globl _start .globl _start
.type _start,@function .type _start,@function
_start: _start:
csrc mstatus, MSTATUS_MIE csrc mstatus, 0x00000008
csrw mie, 0 csrw mie, 0
la t0, trap_entry la t0, rv32_trap_entry
csrw mtvec, t0 csrw mtvec, t0
la sp, _stack_top la sp, _stack_top