PowLu/TencentOS-tiny
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

update GD32VF103_Firmware_Library to 1.0.1

Browse Source
This commit is contained in:
acevest
2019-09-26 22:38:54 +08:00
parent b1436e7431
commit 67e5155475
44 changed files with 333 additions and 315 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_adc.h
\brief definitions for the ADC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_bkp.h
\brief definitions for the BKP
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_can.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_can.h
\brief definitions for the CAN
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h
View File

@@ -3,7 +3,7 @@
\brief definitions for the CRC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_dac.h
\brief definitions for the DAC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_dbg.h
\brief definitions for the DBG
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_dma.h
\brief definitions for the DMA
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_eclic.h
\brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller)
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_exmc.h
\brief definitions for the EXMC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_exti.h
\brief definitions for the EXTI
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

85
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h
View File

@@ -2,7 +2,8 @@
\file gd32vf103_fmc.h
\brief definitions for the FMC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-09-18, V1.0.1, firmware for GD32VF103
*/
/*
@@ -43,11 +44,11 @@ OF SUCH DAMAGE.
/* registers definitions */
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
@@ -63,31 +64,31 @@ OF SUCH DAMAGE.
/* FMC_WS */
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
/* FMC_KEY0 */
#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
/* FMC_KEY */
#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */
/* FMC_OBKEY */
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
/* FMC_STAT0 */
#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
/* FMC_STAT */
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
#define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag bit */
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */
/* FMC_CTL0 */
#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
/* FMC_CTL */
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
#define FMC_CTL_PER BIT(1) /*!< main flash page erase command bit */
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase command bit */
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
#define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock bit */
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
/* FMC_ADDR0 */
/* FMC_ADDR */
#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */
/* FMC_OBSTAT */
@@ -117,8 +118,8 @@ OF SUCH DAMAGE.
#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
/* configuration register */
#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
#define FMC_STAT_REG_OFFSET 0x0CU /*!< status register offset */
#define FMC_CTL_REG_OFFSET 0x10U /*!< control register offset */
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
/* fmc state */
@@ -134,26 +135,26 @@ typedef enum
/* FMC interrupt enable */
typedef enum
{
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
}fmc_int_enum;
/* FMC flags */
typedef enum
{
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */
FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */
FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 0U), /*!< FMC busy flag */
FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 2U), /*!< FMC operation error flag bit */
FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */
FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
}fmc_flag_enum;
/* FMC interrupt flags */
typedef enum
{
FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */
FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */
FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */
FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */
FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */
FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */
}fmc_interrupt_flag_enum;
/* unlock key */
@@ -273,21 +274,21 @@ void ob_unlock(void);
void ob_lock(void);
/* erase the FMC option byte */
fmc_state_enum ob_erase(void);
/* enable write protect */
/* enable write protection */
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
/* configure the option byte security protection */
/* configure security protection */
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
/* write the FMC option byte */
/* program the FMC user option byte */
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
/* program option bytes data */
/* program the FMC data option byte */
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
/* get the FMC option byte user */
/* get OB_USER in register FMC_OBSTAT */
uint8_t ob_user_get(void);
/* get OB_DATA in register FMC_OBSTAT */
uint16_t ob_data_get(void);
/* get the FMC option byte write protection */
uint32_t ob_write_protection_get(void);
/* get FMC option byte security protection code value */
/* get FMC option byte security protection state */
FlagStatus ob_spc_get(void);
/* FMC interrupts and flags management functions */

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_fwdgt.h
\brief definitions for the FWDGT
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

9
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_i2c.h
\brief definitions for the I2C
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.1, firmware for GD32VF103
*/
/*
@@ -51,7 +51,7 @@ OF SUCH DAMAGE.
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */
#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */
#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */
/* bits definitions */
/* I2Cx_CTL0 */
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
@@ -124,6 +124,9 @@ OF SUCH DAMAGE.
/* I2Cx_RT */
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
/* I2Cx_FMPCFG */
#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */
/* constants definitions */
/* define the I2C bit position and its register index offset */
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
@@ -285,8 +288,6 @@ void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
/* master sends slave address */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection);
/* configure I2C saddress1 */
void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr);
/* enable dual-address mode */
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
/* disable dual-address mode */

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_pmu.h
\brief definitions for the PMU
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

232
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_rcu.h
\brief definitions for the RCU
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
@@ -259,146 +259,146 @@ OF SUCH DAMAGE.
/* peripheral clock enable */
typedef enum {
/* AHB peripherals */
RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */
RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */
RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */
/* APB1 peripherals */
RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */
RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */
RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */
RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */
RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */
RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */
RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */
RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */
RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */
RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */
RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */
RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */
RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */
RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */
RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */
RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */
RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */
RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */
RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */
RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */
RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */
/* APB2 peripherals */
RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */
RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */
RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */
RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */
RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */
RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */
RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */
RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */
RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */
RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */
RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */
/* AHB peripherals */
RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */
RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */
RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */
RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */
RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */
/* APB1 peripherals */
RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */
RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */
RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */
RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */
RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */
RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */
RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */
RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */
RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */
RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */
RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */
RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */
RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */
RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */
RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */
RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */
RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */
RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */
RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */
RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */
RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */
/* APB2 peripherals */
RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */
RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */
RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */
RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */
RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */
RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */
RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */
RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */
RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */
RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */
RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */
} rcu_periph_enum;
/* peripheral clock enable when sleep mode*/
typedef enum {
/* AHB peripherals */
RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */
RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */
} rcu_periph_sleep_enum;
/* peripherals reset */
typedef enum {
/* AHB peripherals */
RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
/* APB1 peripherals */
RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */
RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */
RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */
RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */
RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */
RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */
RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */
RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */
RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */
RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */
RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */
RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */
RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */
RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */
RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */
RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */
RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */
RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */
RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */
RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */
/* APB2 peripherals */
RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */
RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */
RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */
RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */
RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */
RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */
RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */
RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */
RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */
RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */
RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */
/* AHB peripherals */
RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */
/* APB1 peripherals */
RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */
RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */
RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */
RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */
RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */
RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */
RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */
RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */
RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */
RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */
RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */
RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */
RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */
RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */
RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */
RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */
RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */
RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */
RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */
RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */
/* APB2 peripherals */
RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */
RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */
RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */
RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */
RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */
RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */
RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */
RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */
RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */
RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */
RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */
} rcu_periph_reset_enum;
/* clock stabilization and peripheral reset flags */
typedef enum {
/* clock stabilization flags */
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */
RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */
RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */
RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */
RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */
/* reset source flags */
RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */
RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */
RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */
RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */
RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */
/* clock stabilization flags */
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */
RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */
RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */
RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */
RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */
RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */
/* reset source flags */
RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */
RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */
RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */
RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */
RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */
} rcu_flag_enum;
/* clock stabilization and ckm interrupt flags */
typedef enum {
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */
RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */
RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */
RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */
RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */
RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */
RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */
RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */
RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */
RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */
RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */
RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */
} rcu_int_flag_enum;
/* clock stabilization and stuck interrupt flags clear */
typedef enum {
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */
RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */
RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */
RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */
RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */
RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */
RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */
RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */
RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */
RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */
} rcu_int_flag_clear_enum;
/* clock stabilization interrupt enable or disable */
typedef enum {
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */
RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */
RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */
RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */
RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */
RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */
RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */
RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */
RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */
RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */
} rcu_int_enum;
/* oscillator types */

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_rtc.h
\brief definitions for the RTC
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_spi.h
\brief definitions for the SPI
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_timer.h
\brief definitions for the TIMER
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.1, firmware for GD32VF103
*/
/*

15
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h
View File

@@ -2,7 +2,8 @@
\file gd32vf103_usart.h
\brief definitions for the USART
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-09-18, V1.0.1, firmware for GD32VF103
*/
/*
@@ -137,12 +138,12 @@ OF SUCH DAMAGE.
typedef enum
{
/* flags in STAT register */
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
@@ -364,11 +365,11 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
/* interrupt functions */
/* enable USART interrupt */
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag);
void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt);
/* disable USART interrupt */
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag);
void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt);
/* get USART interrupt and flag status */
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
/* clear interrupt flag in STAT register */
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag);
#endif /* GD32VF103_USART_H */

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103_wwdgt.h
\brief definitions for the WWDGT
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_adc.c
\brief ADC driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_bkp.c
\brief BKP driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_can.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_can.c
\brief CAN driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_crc.c
\brief CRC driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_dac.c
\brief DAC driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_dbg.c
\brief DBG driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_dma.c
\brief DMA driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

25
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_eclic.c
\brief ECLIC(Enhancement Core-Local Interrupt Controller) driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.1, firmware for GD32VF103
*/
/*
@@ -44,7 +44,8 @@ OF SUCH DAMAGE.
\param[out] none
\retval none
*/
void eclic_global_interrupt_enable(void){
void eclic_global_interrupt_enable(void)
{
/* set machine interrupt enable bit */
set_csr(mstatus, MSTATUS_MIE);
}
@@ -55,7 +56,8 @@ void eclic_global_interrupt_enable(void){
\param[out] none
\retval none
*/
void eclic_global_interrupt_disable(void){
void eclic_global_interrupt_disable(void)
{
/* clear machine interrupt enable bit */
clear_csr(mstatus, MSTATUS_MIE);
}
@@ -71,7 +73,8 @@ void eclic_global_interrupt_disable(void){
\param[out] none
\retval none
*/
void eclic_priority_group_set(uint32_t prigroup) {
void eclic_priority_group_set(uint32_t prigroup)
{
eclic_set_nlbits(prigroup);
}
@@ -83,9 +86,10 @@ void eclic_priority_group_set(uint32_t prigroup) {
\param[out] none
\retval none
*/
void eclic_irq_enable(uint32_t source, uint8_t lvl_abs, uint8_t priority) {
void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority)
{
eclic_enable_interrupt(source);
eclic_set_irq_lvl_abs(source, lvl_abs);
eclic_set_irq_lvl_abs(source, level);
eclic_set_irq_priority(source, priority);
}
@@ -95,7 +99,8 @@ void eclic_irq_enable(uint32_t source, uint8_t lvl_abs, uint8_t priority) {
\param[out] none
\retval none
*/
void eclic_irq_disable(uint32_t source) {
void eclic_irq_disable(uint32_t source)
{
eclic_disable_interrupt(source);
}
@@ -105,7 +110,8 @@ void eclic_irq_disable(uint32_t source) {
\param[out] none
\retval none
*/
void eclic_system_reset(void) {
void eclic_system_reset(void)
{
REG32(REG_DBGMCU2EN) = 0x4b5a6978;
REG32(REG_DBGMCU2) = 0x1;
}
@@ -116,6 +122,7 @@ void eclic_system_reset(void) {
\param[out] none
\retval none
*/
void eclic_send_event(void) {
void eclic_send_event(void)
{
set_csr(0x812, 0x1);
}

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_exmc.c
\brief EXMC driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_exti.c
\brief EXTI driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

106
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c
View File

@@ -2,7 +2,8 @@
\file gd32vf103_fmc.c
\brief FMC driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-09-18, V1.0.1, firmware for GD32VF103
*/
/*
@@ -35,7 +36,7 @@ OF SUCH DAMAGE.
#include "gd32vf103_fmc.h"
/*!
\brief set the wait state counter value
\brief set the FMC wait state counter
\param[in] wscnt<6E><74>wait state counter value
\arg WS_WSCNT_0: FMC 0 wait state
\arg WS_WSCNT_1: FMC 1 wait state
@@ -61,10 +62,10 @@ void fmc_wscnt_set(uint32_t wscnt)
*/
void fmc_unlock(void)
{
if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
if((RESET != (FMC_CTL & FMC_CTL_LK))){
/* write the FMC unlock key */
FMC_KEY0 = UNLOCK_KEY0;
FMC_KEY0 = UNLOCK_KEY1;
FMC_KEY = UNLOCK_KEY0;
FMC_KEY = UNLOCK_KEY1;
}
}
@@ -77,7 +78,7 @@ void fmc_unlock(void)
void fmc_lock(void)
{
/* set the LK bit */
FMC_CTL0 |= FMC_CTL0_LK;
FMC_CTL |= FMC_CTL_LK;
}
@@ -93,13 +94,13 @@ fmc_state_enum fmc_page_erase(uint32_t page_address)
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* if the last operation is completed, start page erase */
if (FMC_READY == fmc_state) {
FMC_CTL0 |= FMC_CTL0_PER;
FMC_ADDR0 = page_address;
FMC_CTL0 |= FMC_CTL0_START;
FMC_CTL |= FMC_CTL_PER;
FMC_ADDR = page_address;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the PER bit */
FMC_CTL0 &= ~FMC_CTL0_PER;
FMC_CTL &= ~FMC_CTL_PER;
}
/* return the FMC state */
return fmc_state;
@@ -118,12 +119,12 @@ fmc_state_enum fmc_mass_erase(void)
if(FMC_READY == fmc_state){
/* start whole chip erase */
FMC_CTL0 |= FMC_CTL0_MER;
FMC_CTL0 |= FMC_CTL0_START;
FMC_CTL |= FMC_CTL_MER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the MER bit */
FMC_CTL0 &= ~FMC_CTL0_MER;
FMC_CTL &= ~FMC_CTL_MER;
}
/* return the FMC state */
return fmc_state;
@@ -143,12 +144,12 @@ fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
if(FMC_READY == fmc_state){
/* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG;
FMC_CTL |= FMC_CTL_PG;
REG32(address) = data;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the PG bit */
FMC_CTL0 &= ~FMC_CTL0_PG;
FMC_CTL &= ~FMC_CTL_PG;
}
/* return the FMC state */
return fmc_state;
@@ -167,12 +168,12 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
if(FMC_READY == fmc_state){
/* set the PG bit to start program */
FMC_CTL0 |= FMC_CTL0_PG;
FMC_CTL |= FMC_CTL_PG;
REG16(address) = data;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the PG bit */
FMC_CTL0 &= ~FMC_CTL0_PG;
FMC_CTL &= ~FMC_CTL_PG;
}
/* return the FMC state */
return fmc_state;
@@ -186,14 +187,14 @@ fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
*/
void ob_unlock(void)
{
if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
/* write the FMC key */
FMC_OBKEY = UNLOCK_KEY0;
FMC_OBKEY = UNLOCK_KEY1;
}
/* wait until OBWEN bit is set by hardware */
while (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) {
while (RESET == (FMC_CTL & FMC_CTL_OBWEN)){
}
}
@@ -206,12 +207,12 @@ void ob_unlock(void)
void ob_lock(void)
{
/* reset the OBWEN bit */
FMC_CTL0 &= ~FMC_CTL0_OBWEN;
FMC_CTL &= ~FMC_CTL_OBWEN;
}
/*!
\brief erase the FMC option byte
unlock the FMC_CTL0 and option byte before calling this function
unlock the FMC_CTL and option byte before calling this function
\param[in] none
\param[out] none
\retval state of FMC, refer to fmc_state_enum
@@ -230,29 +231,29 @@ fmc_state_enum ob_erase(void)
if(FMC_READY == fmc_state){
/* start erase the option byte */
FMC_CTL0 |= FMC_CTL0_OBER;
FMC_CTL0 |= FMC_CTL0_START;
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER;
FMC_CTL &= ~FMC_CTL_OBER;
/* set the OBPG bit */
FMC_CTL0 |= FMC_CTL0_OBPG;
FMC_CTL |= FMC_CTL_OBPG;
/* no security protection */
OB_SPC = (uint16_t) temp_spc;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
FMC_CTL &= ~FMC_CTL_OBPG;
}
}else{
if(FMC_TOERR != fmc_state){
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
FMC_CTL &= ~FMC_CTL_OBPG;
}
}
}
@@ -266,7 +267,7 @@ fmc_state_enum ob_erase(void)
you want to protect the corresponding pages. meanwhile, sector
macro could used to set specific sector write protected.
one or more parameters can be selected which are shown as below:
\arg OB_WPx(x = 0..31): write protect specify sector
\arg OB_WP_x(x = 0..31): write protect specify sector
\arg OB_WP_ALL: write protect all sector
\param[out] none
\retval state of FMC, refer to fmc_state_enum
@@ -286,7 +287,7 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
if(FMC_READY == fmc_state){
/* set the OBPG bit*/
FMC_CTL0 |= FMC_CTL0_OBPG;
FMC_CTL |= FMC_CTL_OBPG;
if(0xFFU != temp_wp0){
OB_WP0 = temp_wp0;
@@ -314,7 +315,7 @@ fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
}
if(FMC_TOERR != fmc_state){
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
FMC_CTL &= ~FMC_CTL_OBPG;
}
}
/* return the FMC state */
@@ -335,18 +336,18 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
FMC_CTL0 |= FMC_CTL0_OBER;
FMC_CTL0 |= FMC_CTL0_START;
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER;
FMC_CTL &= ~FMC_CTL_OBER;
/* start the option byte program */
FMC_CTL0 |= FMC_CTL0_OBPG;
FMC_CTL |= FMC_CTL_OBPG;
OB_SPC = (uint16_t) ob_spc;
@@ -355,12 +356,12 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
if (FMC_TOERR != fmc_state) {
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
FMC_CTL &= ~FMC_CTL_OBPG;
}
}else{
if (FMC_TOERR != fmc_state) {
/* reset the OBER bit */
FMC_CTL0 &= ~FMC_CTL0_OBER;
FMC_CTL &= ~FMC_CTL_OBER;
}
}
}
@@ -372,12 +373,12 @@ fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
\brief program the FMC user option byte
\param[in] ob_fwdgt: option byte watchdog value
\arg OB_FWDGT_SW: software free watchdog
\arg OB_FWDGT_HW: hardware free watchdog
\arg OB_FWDGT_HW: hardware free watchdog
\param[in] ob_deepsleep: option byte deepsleep reset value
\arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
\arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
\param[in] ob_stdby:option byte standby reset value
\arg OB_STDBY_NRST: no reset when entering standby mode
\arg OB_STDBY_NRST: no reset when entering standby mode
\arg OB_STDBY_RST: generate a reset instead of entering standby mode
\param[in] ob_boot: specifies the option byte boot bank value
\arg OB_BOOT_B0: boot from bank0
@@ -394,7 +395,7 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_
if(FMC_READY == fmc_state){
/* set the OBPG bit*/
FMC_CTL0 |= FMC_CTL0_OBPG;
FMC_CTL |= FMC_CTL_OBPG;
temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
OB_USER = (uint16_t) temp;
@@ -404,7 +405,7 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_
if(FMC_TOERR != fmc_state){
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
FMC_CTL &= ~FMC_CTL_OBPG;
}
}
/* return the FMC state */
@@ -412,18 +413,19 @@ fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_
}
/*!
\brief program option bytes data
\brief program the FMC data option byte
\param[in] address: the option bytes address to be programmed
\param[in] data: the byte to be programmed
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
{
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* set the OBPG bit */
FMC_CTL0 |= FMC_CTL0_OBPG;
FMC_CTL |= FMC_CTL_OBPG;
REG16(address) = data;
/* wait for the FMC ready */
@@ -431,7 +433,7 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
if(FMC_TOERR != fmc_state){
/* reset the OBPG bit */
FMC_CTL0 &= ~FMC_CTL0_OBPG;
FMC_CTL &= ~FMC_CTL_OBPG;
}
}
/* return the FMC state */
@@ -439,7 +441,7 @@ fmc_state_enum ob_data_program(uint32_t address, uint8_t data) {
}
/*!
\brief get the FMC user option byte
\brief get OB_USER in register FMC_OBSTAT
\param[in] none
\param[out] none
\retval the FMC user option byte values
@@ -474,7 +476,7 @@ uint32_t ob_write_protection_get(void)
}
/*!
\brief get the FMC option byte security protection
\brief get FMC option byte security protection state
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
@@ -527,7 +529,7 @@ void fmc_interrupt_disable(uint32_t interrupt)
\arg FMC_FLAG_PGERR: FMC operation error flag bit
\arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit
\arg FMC_FLAG_END: FMC end of operation flag bit
\arg FMC_FLAG_OBERR: FMC option bytes read error flag bit
\arg FMC_FLAG_OBERR: FMC option byte read error flag bit
\param[out] none
\retval FlagStatus: SET or RESET
*/
@@ -570,11 +572,11 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
FlagStatus ret1 = RESET;
FlagStatus ret2 = RESET;
if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
if(FMC_STAT_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
/* get the staus of interrupt flag */
ret1 = (FlagStatus) (FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
/* get the staus of interrupt enale bit */
ret2 = (FlagStatus) (FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
ret2 = (FlagStatus) (FMC_CTL & BIT(FMC_BIT_POS1(flag)));
}
if(ret1 && ret2){
@@ -609,13 +611,13 @@ fmc_state_enum fmc_state_get(void)
{
fmc_state_enum fmc_state = FMC_READY;
if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
if((uint32_t) 0x00U != (FMC_STAT & FMC_STAT_BUSY)){
fmc_state = FMC_BUSY;
}else{
if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
if((uint32_t) 0x00U != (FMC_STAT & FMC_STAT_WPERR)){
fmc_state = FMC_WPERR;
}else{
if((uint32_t) 0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
if((uint32_t) 0x00U != (FMC_STAT & (FMC_STAT_PGERR))){
fmc_state = FMC_PGERR;
}
}

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_fwdgt.c
\brief FWDGT driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_gpio.c
\brief GPIO driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

58
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c
View File

@@ -2,7 +2,8 @@
\file gd32vf103_i2c.c
\brief I2C driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-09-18, V1.0.1, firmware for GD32VF103
*/
/*
@@ -35,7 +36,7 @@ OF SUCH DAMAGE.
#include "gd32vf103_i2c.h"
/* I2C register bit mask */
#define I2CCLK_MAX ((uint32_t)0x00000048U) /*!< i2cclk maximum value */
#define I2CCLK_MAX ((uint32_t)0x00000036U) /*!< i2cclk maximum value */
#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */
#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */
@@ -72,18 +73,19 @@ void i2c_deinit(uint32_t i2c_periph)
\brief configure I2C clock
\param[in] i2c_periph: I2Cx(x=0,1)
\param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz)
\param[in] dutycyc: duty cycle in fast mode
and fast mode plus (up to 1MHz)
\param[in] dutycyc: duty cycle in fast mode or fast mode plus
only one parameter can be selected which is shown as below:
\arg I2C_DTCY_2: T_low/T_high=2
\arg I2C_DTCY_16_9: T_low/T_high=16/9
\arg I2C_DTCY_2: T_low/T_high=2
\arg I2C_DTCY_16_9: T_low/T_high=16/9
\param[out] none
\retval none
*/
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
{
uint32_t pclk1, clkc, freq, risetime;
uint32_t temp;
pclk1 = rcu_clock_freq_get(CK_APB1);
/* I2C peripheral clock frequency */
freq = (uint32_t) (pclk1 / 1000000U);
@@ -93,9 +95,9 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
temp = I2C_CTL1(i2c_periph);
temp &= ~I2C_CTL1_I2CCLK;
temp |= freq;
I2C_CTL1(i2c_periph) = temp;
if (100000U >= clkspeed) {
/* the maximum SCL rise time is 1000ns in standard mode */
risetime = (uint32_t) ((pclk1 / 1000000U) + 1U);
@@ -106,7 +108,7 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
} else {
I2C_RT(i2c_periph) = risetime;
}
clkc = (uint32_t) (pclk1 / (clkspeed * 2U));
clkc = (uint32_t) (pclk1 / (clkspeed * 2U));
if (clkc < 0x04U) {
/* the CLKC in standard mode minmum value is 4 */
clkc = 0x04U;
@@ -115,9 +117,8 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
} else if (400000U >= clkspeed) {
/* the maximum SCL rise time is 300ns in fast mode */
I2C_RT(i2c_periph) = (uint32_t) (((freq * (uint32_t) 300U)
/ (uint32_t) 1000U) + (uint32_t) 1U);
if (I2C_DTCY_2 == dutycyc) {
I2C_RT(i2c_periph) = (uint32_t) (((freq * (uint32_t) 300U)/(uint32_t)1000U)+(uint32_t)1U);
if (I2C_DTCY_2 == dutycyc){
/* I2C duty cycle is 2 */
clkc = (uint32_t) (pclk1 / (clkspeed * 3U));
I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
@@ -128,11 +129,27 @@ void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc)
}
if (0U == (clkc & I2C_CKCFG_CLKC)) {
/* the CLKC in fast mode minmum value is 1 */
clkc |= 0x0001U;
clkc |= 0x0001U;
}
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
I2C_CKCFG(i2c_periph) |= clkc;
} else {
/* fast mode plus, the maximum SCL rise time is 120ns */
I2C_RT (i2c_periph) = (uint32_t) (((freq * (uint32_t) 120U) / (uint32_t) 1000U)+(uint32_t) 1U);
if (I2C_DTCY_2 == dutycyc) {
/* I2C duty cycle is 2 */
clkc = (uint32_t) (pclk1 / (clkspeed * 3U));
I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY;
} else {
/* I2C duty cycle is 16/9 */
clkc = (uint32_t) (pclk1 / (clkspeed * 25U));
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY;
}
/* enable fast mode */
I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST;
I2C_CKCFG(i2c_periph) |= clkc;
/* enable I2C fast mode plus */
I2C_FMPCFG(i2c_periph) |= I2C_FMPCFG_FMPEN;
}
}
@@ -246,19 +263,6 @@ void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirec
I2C_DATA(i2c_periph) = addr;
}
/*!
\brief configure I2C saddress1
\param[in] i2c_periph: I2Cx(x=0,1)
\param[in] addr: I2C address
\param[out] none
\retval none
*/
void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr)
{
/* configure saddress1 */
I2C_SADDR1(i2c_periph) = (0xFE & addr);
}
/*!
\brief enable dual-address mode
\param[in] i2c_periph: I2Cx(x=0,1)

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_pmu.c
\brief PMU driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_rcu.c
\brief RCU driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_rtc.c
\brief RTC driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_spi.c
\brief SPI driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

15
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_timer.c
\brief TIMER driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.1, firmware for GD32VF103
*/
/*
@@ -40,7 +40,7 @@ OF SUCH DAMAGE.
/*!
\brief deinit a timer
\param[in] timer_periph: TIMERx(x=0..13)
\param[in] timer_periph: TIMERx(x=0..6)
\param[out] none
\retval none
*/
@@ -166,7 +166,7 @@ void timer_enable(uint32_t timer_periph)
/*!
\brief disable a timer
\param[in] timer_periph: TIMERx(x=0..13)
\param[in] timer_periph: TIMERx(x=0..6)
\param[out] none
\retval none
*/
@@ -384,6 +384,7 @@ void timer_update_source_config(uint32_t timer_periph, uint32_t update)
}
}
/*!
\brief enable the TIMER DMA
\param[in] timer_periph: TIMERx(x=0..6)
@@ -979,7 +980,7 @@ void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, u
\param[in] channel:
only one parameter can be selected which is shown as below:
\arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
\arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..41))
\arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
\arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
\arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
\param[in] occlear: channel output clear function
@@ -1900,7 +1901,7 @@ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
\arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
\arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
\arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0)
\arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0)
\arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..4)
\arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
\param[out] none
\retval none
@@ -1921,7 +1922,7 @@ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
\arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
\arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
\arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
\arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0)
\arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4)
\arg TIMER_FLAG_BRK: break flag, TIMERx(x=0)
\arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
\arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
@@ -1950,7 +1951,7 @@ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
\arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
\arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
\arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
\arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0)
\arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..4)
\arg TIMER_FLAG_BRK: break flag, TIMERx(x=0)
\arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
\arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)

31
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c
View File

@@ -2,7 +2,8 @@
\file gd32vf103_usart.c
\brief USART driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
\version 2019-09-18, V1.0.1, firmware for GD32VF103
*/
/*
@@ -631,12 +632,12 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd)
\param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
\param[in] flag: USART flags, refer to usart_flag_enum
only one parameter can be selected which is shown as below:
\arg USART_FLAG_CTSF: CTS change flag
\arg USART_FLAG_LBDF: LIN break detected flag
\arg USART_FLAG_CTS: CTS change flag
\arg USART_FLAG_LBD: LIN break detected flag
\arg USART_FLAG_TBE: transmit data buffer empty
\arg USART_FLAG_TC: transmission complete
\arg USART_FLAG_RBNE: read data buffer not empty
\arg USART_FLAG_IDLEF: IDLE frame detected flag
\arg USART_FLAG_IDLE: IDLE frame detected flag
\arg USART_FLAG_ORERR: overrun error
\arg USART_FLAG_NERR: noise error flag
\arg USART_FLAG_FERR: frame error flag
@@ -658,8 +659,8 @@ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag)
\param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
\param[in] flag: USART flags, refer to usart_flag_enum
only one parameter can be selected which is shown as below:
\arg USART_FLAG_CTSF: CTS change flag
\arg USART_FLAG_LBDF: LIN break detected flag
\arg USART_FLAG_CTS: CTS change flag
\arg USART_FLAG_LBD: LIN break detected flag
\arg USART_FLAG_TC: transmission complete
\arg USART_FLAG_RBNE: read data buffer not empty
\param[out] none
@@ -673,7 +674,7 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
/*!
\brief enable USART interrupt
\param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
\param[in] int_flag
\param[in] interrupt
only one parameter can be selected which is shown as below:
\arg USART_INT_PERR: parity error interrupt
\arg USART_INT_TBE: transmitter buffer empty interrupt
@@ -686,15 +687,15 @@ void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag)
\param[out] none
\retval none
*/
void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt)
{
USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag));
USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt));
}
/*!
\brief disable USART interrupt
\param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
\param[in] int_flag
\param[in] interrupt
only one parameter can be selected which is shown as below:
\arg USART_INT_PERR: parity error interrupt
\arg USART_INT_TBE: transmitter buffer empty interrupt
@@ -707,9 +708,9 @@ void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag)
\param[out] none
\retval none
*/
void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag)
void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt)
{
USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag));
USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt));
}
/*!
@@ -749,7 +750,7 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
/*!
\brief clear USART interrupt flag in STAT register
\param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4)
\param[in] flag: USART interrupt flag
\param[in] int_flag: USART interrupt flag
only one parameter can be selected which is shown as below:
\arg USART_INT_FLAG_CTS: CTS change flag
\arg USART_INT_FLAG_LBD: LIN break detected flag
@@ -758,7 +759,7 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag)
\param[out] none
\retval none
*/
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag)
void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag)
{
USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag));
USART_REG_VAL2(usart_periph, int_flag) &= ~BIT(USART_BIT_POS2(int_flag));
}

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c
View File

@@ -2,7 +2,7 @@
\file gd32vf103_wwdgt.c
\brief WWDGT driver
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

4
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/gd32vf103.h
View File

@@ -2,7 +2,7 @@
\file gd32vf103.h
\brief general definitions for GD32VF103
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*
@@ -59,7 +59,7 @@ OF SUCH DAMAGE.
#ifdef GD32VF103R_START
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
#define HXTAL_VALUE_8M HXTAL_VALUE
#elif defined(GD32VF103V_EVAL) || defined(GD32VF103C_START)
#elif defined(GD32VF103V_EVAL) || defined(GD32VF103C_START) || defined(GD32VF103T_START)
#define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
#define HXTAL_VALUE_25M HXTAL_VALUE
#else

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/system_gd32vf103.c
View File

@@ -3,7 +3,7 @@
\brief RISC-V Device Peripheral Access Layer Source File for
GD32VF103 Device Series
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*

2
platform/vendor_bsp/gd/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/system_gd32vf103.h
View File

@@ -3,7 +3,7 @@
\brief RISC-V Device Peripheral Access Layer Header File for
GD32VF103 Device Series
\version 2019-6-5, V1.0.0, firmware for GD32VF103
\version 2019-06-05, V1.0.0, firmware for GD32VF103
*/
/*