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add gd32E507 iar project for tos

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add gd32E507  iar project for tos
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supowang
2020-12-23 20:26:18 +08:00
parent 707c8c7e1f
commit 6c16fcc953
206 changed files with 85761 additions and 0 deletions
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165
board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/gd32e507z_eval.h Normal file
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/*!
\file gd32e507z_eval.h
\brief definitions for GD32E507Z_EVAL's leds, keys and COM ports hardware resources
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E507Z_EVAL_H
#define GD32E507Z_EVAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "gd32e50x.h"
/* exported types */
typedef enum
{
LED1 = 0,
LED2 = 1,
LED3 = 2,
LED4 = 3
} led_typedef_enum;
typedef enum
{
KEY_A = 0,
KEY_B = 1,
KEY_C = 2,
KEY_D = 3,
KEY_CET = 4
} key_typedef_enum;
typedef enum
{
KEY_MODE_GPIO = 0,
KEY_MODE_EXTI = 1
} keymode_typedef_enum;
/* eval board low layer led */
#define LEDn 4U
#define LED1_PIN GPIO_PIN_10
#define LED1_GPIO_PORT GPIOG
#define LED1_GPIO_CLK RCU_GPIOG
#define LED2_PIN GPIO_PIN_11
#define LED2_GPIO_PORT GPIOG
#define LED2_GPIO_CLK RCU_GPIOG
#define LED3_PIN GPIO_PIN_12
#define LED3_GPIO_PORT GPIOG
#define LED3_GPIO_CLK RCU_GPIOG
#define LED4_PIN GPIO_PIN_13
#define LED4_GPIO_PORT GPIOG
#define LED4_GPIO_CLK RCU_GPIOG
#define COMn 1U
#define EVAL_COM0 USART0
#define EVAL_COM0_CLK RCU_USART0
#define EVAL_COM0_TX_PIN GPIO_PIN_9
#define EVAL_COM0_RX_PIN GPIO_PIN_10
#define EVAL_COM0_GPIO_PORT GPIOA
#define EVAL_COM0_GPIO_CLK RCU_GPIOA
#define KEYn 5U
/* wakeup push-button */
#define KEY_A_PIN GPIO_PIN_0
#define KEY_A_GPIO_PORT GPIOA
#define KEY_A_GPIO_CLK RCU_GPIOA
#define KEY_A_EXTI_LINE EXTI_0
#define KEY_A_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA
#define KEY_A_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0
#define KEY_A_EXTI_IRQn EXTI0_IRQn
/* tamper push-button */
#define KEY_B_PIN GPIO_PIN_13
#define KEY_B_GPIO_PORT GPIOC
#define KEY_B_GPIO_CLK RCU_GPIOC
#define KEY_B_EXTI_LINE EXTI_13
#define KEY_B_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC
#define KEY_B_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_13
#define KEY_B_EXTI_IRQn EXTI10_15_IRQn
/* user push-button */
#define KEY_C_PIN GPIO_PIN_13
#define KEY_C_GPIO_PORT GPIOF
#define KEY_C_GPIO_CLK RCU_GPIOF
#define KEY_C_EXTI_LINE EXTI_13
#define KEY_C_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOF
#define KEY_C_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_13
#define KEY_C_EXTI_IRQn EXTI10_15_IRQn
/* extension push-button */
#define KEY_D_PIN GPIO_PIN_14
#define KEY_D_GPIO_PORT GPIOF
#define KEY_D_GPIO_CLK RCU_GPIOF
#define KEY_D_EXTI_LINE EXTI_14
#define KEY_D_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOF
#define KEY_D_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_14
#define KEY_D_EXTI_IRQn EXTI10_15_IRQn
/* extension push-button */
#define KEY_CET_PIN GPIO_PIN_15
#define KEY_CET_GPIO_PORT GPIOF
#define KEY_CET_GPIO_CLK RCU_GPIOF
#define KEY_CET_EXTI_LINE EXTI_15
#define KEY_CET_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOF
#define KEY_CET_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_15
#define KEY_CET_EXTI_IRQn EXTI10_15_IRQn
/* function declarations */
/* configure led GPIO */
void gd_eval_led_init(led_typedef_enum lednum);
/* turn on selected led */
void gd_eval_led_on(led_typedef_enum lednum);
/* turn off selected led */
void gd_eval_led_off(led_typedef_enum lednum);
/* toggle the selected led */
void gd_eval_led_toggle(led_typedef_enum lednum);
/* configure key */
void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode);
/* return the selected key state */
uint8_t gd_eval_key_state_get(key_typedef_enum key);
/* configure COM port */
void gd_eval_com_init(uint32_t com);
#ifdef __cplusplus
}
#endif
#endif /* GD32E507Z_EVAL_H */

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board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/gd32e507z_lcd_eval.h Normal file
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/*!
\file gd32e507z_lcd_eval.h
\brief LCD driver header file
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E507Z_LCD_EVAL_H
#define GD32E507Z_LCD_EVAL_H
#include "gd32e50x.h"
#define BANK0_LCD_D ((uint32_t)0x65000000) /*!< LCD data address */
#define BANK0_LCD_C ((uint32_t)0x64000000) /*!< LCD register address */
/* LCD registers */
#define R0 0x00
#define R1 0x01
#define R2 0x02
#define R3 0x03
#define R4 0x04
#define R5 0x05
#define R6 0x06
#define R7 0x07
#define R8 0x08
#define R9 0x09
#define R10 0x0A
#define R11 0x0B
#define R12 0x0C
#define R13 0x0D
#define R14 0x0E
#define R15 0x0F
#define R16 0x10
#define R17 0x11
#define R18 0x12
#define R19 0x13
#define R20 0x14
#define R21 0x15
#define R22 0x16
#define R23 0x17
#define R24 0x18
#define R25 0x19
#define R26 0x1A
#define R27 0x1B
#define R28 0x1C
#define R29 0x1D
#define R30 0x1E
#define R31 0x1F
#define R32 0x20
#define R33 0x21
#define R34 0x22
#define R35 0x23
#define R36 0x24
#define R37 0x25
#define R40 0x28
#define R41 0x29
#define R43 0x2B
#define R45 0x2D
#define R48 0x30
#define R49 0x31
#define R50 0x32
#define R51 0x33
#define R52 0x34
#define R53 0x35
#define R54 0x36
#define R55 0x37
#define R56 0x38
#define R57 0x39
#define R58 0x3A
#define R59 0x3B
#define R60 0x3C
#define R61 0x3D
#define R62 0x3E
#define R63 0x3F
#define R64 0x40
#define R65 0x41
#define R66 0x42
#define R67 0x43
#define R68 0x44
#define R69 0x45
#define R70 0x46
#define R71 0x47
#define R72 0x48
#define R73 0x49
#define R74 0x4A
#define R75 0x4B
#define R76 0x4C
#define R77 0x4D
#define R78 0x4E
#define R79 0x4F
#define R80 0x50
#define R81 0x51
#define R82 0x52
#define R83 0x53
#define R96 0x60
#define R97 0x61
#define R106 0x6A
#define R118 0x76
#define R128 0x80
#define R129 0x81
#define R130 0x82
#define R131 0x83
#define R132 0x84
#define R133 0x85
#define R134 0x86
#define R135 0x87
#define R136 0x88
#define R137 0x89
#define R139 0x8B
#define R140 0x8C
#define R141 0x8D
#define R143 0x8F
#define R144 0x90
#define R145 0x91
#define R146 0x92
#define R147 0x93
#define R148 0x94
#define R149 0x95
#define R150 0x96
#define R151 0x97
#define R152 0x98
#define R153 0x99
#define R154 0x9A
#define R157 0x9D
#define R192 0xC0
#define R193 0xC1
#define R229 0xE5
/* LCD color */
#define LCD_COLOR_WHITE 0xFFFF
#define LCD_COLOR_BLACK 0x0000
#define LCD_COLOR_GREY 0xF7DE
#define LCD_COLOR_BLUE 0x001F
#define LCD_COLOR_BLUE2 0x051F
#define LCD_COLOR_RED 0xF800
#define LCD_COLOR_MAGENTA 0xF81F
#define LCD_COLOR_GREEN 0x07E0
#define LCD_COLOR_CYAN 0x7FFF
#define LCD_COLOR_YELLOW 0xFFE0
/* definitions of LCD lines */
#define LCD_LINE_0 0
#define LCD_LINE_1 24
#define LCD_LINE_2 48
#define LCD_LINE_3 72
#define LCD_LINE_4 96
#define LCD_LINE_5 120
#define LCD_LINE_6 144
#define LCD_LINE_7 168
#define LCD_LINE_8 192
#define LCD_LINE_9 216
#define CHAR_FONT_8_16 ((uint16_t)0x0000U) /*!< the font of char is 8X16 */
#define CHAR_FONT_16_24 ((uint16_t)0x0001U) /*!< the font of char is 16X24 */
#define CHAR_DIRECTION_HORIZONTAL ((uint16_t)0x0000U) /*!< character display direction is horizontal */
#define CHAR_DIRECTION_VERTICAL ((uint16_t)0x0001U) /*!< character display direction is vertical */
#define LCD_PIXEL_WIDTH ((uint16_t)320)
#define LCD_PIXEL_HEIGHT ((uint16_t)240)
/* char format struct definitions */
typedef struct
{
uint16_t font; /*!< the type of font */
uint16_t direction; /*!< the direction of char */
uint16_t char_color; /*!< the color of char */
uint16_t bk_color; /*!< the color of backgroud */
}char_format_struct;
/* lcd peripheral initialize */
void exmc_lcd_init(void);
/* initialize the LCD */
void lcd_init(void);
/* write data to the selected LCD register */
void lcd_register_write(uint16_t register_id,uint16_t value);
/* read the value of LCD register */
uint16_t lcd_register_read(uint8_t register_id);
/* write command to LCD register */
void lcd_command_write (uint16_t value);
/* prepare to write to the LCD GRAM */
void lcd_gram_write_prepare(void);
/* write RGB code to the LCD GRAM register */
void lcd_gram_write(uint16_t rgb_code);
/* read data from GRAM */
uint16_t lcd_gram_read(void);
/* set the cursor of LCD */
void lcd_cursor_set(uint16_t x,uint16_t y);
/* clear the LCD screen to the specified color */
void lcd_clear(uint16_t Color);
/* set the point according to the specified position and color */
void lcd_point_set(uint16_t x,uint16_t y,uint16_t point);
/* get the point according to the specified position */
uint16_t lcd_point_get(uint16_t x,uint16_t y);
/* set window area */
void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y);
/* draw a horizontal line on LCD screen */
void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width);
/* draw a vertical line on LCD screen */
void lcd_vline_draw(uint16_t start_x,uint16_t end_x,uint16_t y,uint16_t color,uint16_t width);
/* draw a rectangle according to the specified position and color */
void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point);
/* fill the specified color to a rectangle */
void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color);
/* draw a picture on LCD screen according to the specified position */
void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic);
/* display a char on LCD screen according to the specified position */
void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format);
#endif /* GD32E507Z_LCD_EVAL_H */

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board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/gd32e50x_it.h Normal file
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/*!
\file gd32e50x_it.h
\brief the header file of the ISR
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_IT_H
#define GD32E50X_IT_H
#include "gd32e50x.h"
/* function declarations */
/* this function handles NMI exception */
void NMI_Handler(void);
/* this function handles HardFault exception */
void HardFault_Handler(void);
/* this function handles MemManage exception */
void MemManage_Handler(void);
/* this function handles BusFault exception */
void BusFault_Handler(void);
/* this function handles UsageFault exception */
void UsageFault_Handler(void);
/* this function handles SVC exception */
void SVC_Handler(void);
/* this function handles DebugMon exception */
void DebugMon_Handler(void);
/* this function handles PendSV exception */
void PendSV_Handler(void);
/* this function handles SysTick exception */
void SysTick_Handler(void);
#endif /* GD32E50X_IT_H */

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board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/gd32e50x_libopt.h Normal file
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/*!
\file gd32e50x_libopt.h
\brief library optional for gd32e50x
\version 2020-03-10, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_LIBOPT_H
#define GD32E50X_LIBOPT_H
#ifndef GD32EPRT
#include "gd32e50x_adc.h"
#include "gd32e50x_bkp.h"
#include "gd32e50x_crc.h"
#include "gd32e50x_ctc.h"
#include "gd32e50x_dac.h"
#include "gd32e50x_dbg.h"
#include "gd32e50x_dma.h"
#include "gd32e50x_exmc.h"
#include "gd32e50x_exti.h"
#include "gd32e50x_fmc.h"
#include "gd32e50x_fwdgt.h"
#include "gd32e50x_gpio.h"
#include "gd32e50x_shrtimer.h"
#include "gd32e50x_i2c.h"
#include "gd32e50x_misc.h"
#include "gd32e50x_pmu.h"
#include "gd32e50x_rcu.h"
#include "gd32e50x_rtc.h"
#include "gd32e50x_spi.h"
#include "gd32e50x_timer.h"
#include "gd32e50x_usart.h"
#include "gd32e50x_wwdgt.h"
#include "gd32e50x_sqpi.h"
#ifdef GD32E50X_CL
#include "gd32e50x_enet.h"
#include "gd32e50x_tmu.h"
#include "gd32e50x_cmp.h"
#else /* GD32E50X_CL */
#include "gd32e50x_sdio.h"
#endif /* GD32E50X_CL */
#else /* GD32EPRT */
#include "gd32e50x_adc.h"
#include "gd32e50x_bkp.h"
#include "gd32e50x_crc.h"
#include "gd32e50x_ctc.h"
#include "gd32e50x_dac.h"
#include "gd32e50x_dbg.h"
#include "gd32e50x_dma.h"
#include "gd32e50x_enet.h"
#include "gd32e50x_exmc.h"
#include "gd32e50x_exti.h"
#include "gd32e50x_fmc.h"
#include "gd32e50x_fwdgt.h"
#include "gd32e50x_gpio.h"
#include "gd32e50x_i2c.h"
#include "gd32e50x_misc.h"
#include "gd32e50x_pmu.h"
#include "gd32e50x_rcu.h"
#include "gd32e50x_rtc.h"
#include "gd32e50x_spi.h"
#include "gd32e50x_timer.h"
#include "gd32e50x_usart.h"
#include "gd32e50x_wwdgt.h"
#include "gd32e50x_sqpi.h"
#endif /* GD32EPRT */
#endif /* GD32E50X_LIBOPT_H */

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board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/lcd_font.h Normal file
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#include "gd32e50x.h"
// 8x16 ASCII
unsigned char const ascii_8x16[1536] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00,
0x00,0x66,0x66,0x66,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x6C,0x6C,0xFE,0x6C,0x6C,0x6C,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00,
0x18,0x18,0x7C,0xC6,0xC2,0xC0,0x7C,0x06,0x86,0xC6,0x7C,0x18,0x18,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0xC2,0xC6,0x0C,0x18,0x30,0x60,0xC6,0x86,0x00,0x00,0x00,0x00,
0x00,0x00,0x38,0x6C,0x6C,0x38,0x76,0xDC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00,
0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x0C,0x18,0x30,0x30,0x30,0x30,0x30,0x30,0x18,0x0C,0x00,0x00,0x00,0x00,
0x00,0x00,0x30,0x18,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x18,0x30,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x7E,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x02,0x06,0x0C,0x18,0x30,0x60,0xC0,0x80,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0xC6,0xCE,0xD6,0xD6,0xE6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x18,0x38,0x78,0x18,0x18,0x18,0x18,0x18,0x18,0x7E,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0x06,0x0C,0x18,0x30,0x60,0xC0,0xC6,0xFE,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0x06,0x06,0x3C,0x06,0x06,0x06,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x0C,0x1C,0x3C,0x6C,0xCC,0xFE,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00,
0x00,0x00,0xFE,0xC0,0xC0,0xC0,0xFC,0x0E,0x06,0x06,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x38,0x60,0xC0,0xC0,0xFC,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0xFE,0xC6,0x06,0x06,0x0C,0x18,0x30,0x30,0x30,0x30,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0xC6,0xC6,0x7C,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0xC6,0xC6,0x7E,0x06,0x06,0x06,0x0C,0x78,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x30,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0xC6,0x0C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x7C,0xC6,0xC6,0xDE,0xDE,0xDE,0xDC,0xC0,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00,
0x00,0x00,0xFC,0x66,0x66,0x66,0x7C,0x66,0x66,0x66,0x66,0xFC,0x00,0x00,0x00,0x00,
0x00,0x00,0x3C,0x66,0xC2,0xC0,0xC0,0xC0,0xC0,0xC2,0x66,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0xF8,0x6C,0x66,0x66,0x66,0x66,0x66,0x66,0x6C,0xF8,0x00,0x00,0x00,0x00,
0x00,0x00,0xFE,0x66,0x62,0x68,0x78,0x68,0x60,0x62,0x66,0xFE,0x00,0x00,0x00,0x00,
0x00,0x00,0xFE,0x66,0x62,0x68,0x78,0x68,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00,
0x00,0x00,0x3C,0x66,0xC2,0xC0,0xC0,0xDE,0xC6,0xC6,0x66,0x3A,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xFE,0xC6,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00,
0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0x1E,0x0C,0x0C,0x0C,0x0C,0x0C,0xCC,0xCC,0xCC,0x78,0x00,0x00,0x00,0x00,
0x00,0x00,0xE6,0x66,0x6C,0x6C,0x78,0x78,0x6C,0x66,0x66,0xE6,0x00,0x00,0x00,0x00,
0x00,0x00,0xF0,0x60,0x60,0x60,0x60,0x60,0x60,0x62,0x66,0xFE,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xEE,0xFE,0xFE,0xD6,0xC6,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xE6,0xF6,0xFE,0xDE,0xCE,0xC6,0xC6,0xC6,0xC6,0x00,0x00,0x00,0x00,
0x00,0x00,0x38,0x6C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x6C,0x38,0x00,0x00,0x00,0x00,
0x00,0x00,0xFC,0x66,0x66,0x66,0x7C,0x60,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xD6,0xDE,0x7C,0x0C,0x0E,0x00,0x00,
0x00,0x00,0xFC,0x66,0x66,0x66,0x7C,0x6C,0x66,0x66,0x66,0xE6,0x00,0x00,0x00,0x00,
0x00,0x00,0x7C,0xC6,0xC6,0x60,0x38,0x0C,0x06,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x7E,0x7E,0x5A,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x6C,0x38,0x10,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xD6,0xD6,0xFE,0x6C,0x6C,0x00,0x00,0x00,0x00,
0x00,0x00,0xC6,0xC6,0x6C,0x6C,0x38,0x38,0x6C,0x6C,0xC6,0xC6,0x00,0x00,0x00,0x00,
0x00,0x00,0x66,0x66,0x66,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0xFE,0xC6,0x86,0x0C,0x18,0x30,0x60,0xC2,0xC6,0xFE,0x00,0x00,0x00,0x00,
0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x06,0x02,0x00,0x00,0x00,0x00,
0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00,
0x10,0x38,0x6C,0xC6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,
0x30,0x30,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x78,0x0C,0x7C,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00,
0x00,0x00,0xE0,0x60,0x60,0x78,0x6C,0x66,0x66,0x66,0x66,0xDC,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0xC0,0xC0,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x1C,0x0C,0x0C,0x3C,0x6C,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0xFE,0xC0,0xC0,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x38,0x6C,0x64,0x60,0xF0,0x60,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x76,0xCC,0xCC,0xCC,0xCC,0xCC,0x7C,0x0C,0xCC,0x78,0x00,
0x00,0x00,0xE0,0x60,0x60,0x6C,0x76,0x66,0x66,0x66,0x66,0xE6,0x00,0x00,0x00,0x00,
0x00,0x00,0x18,0x18,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,
0x00,0x00,0xE0,0x60,0x60,0x66,0x6C,0x78,0x78,0x6C,0x66,0xE6,0x00,0x00,0x00,0x00,
0x00,0x00,0x38,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xEC,0xFE,0xD6,0xD6,0xD6,0xD6,0xD6,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xDC,0x66,0x66,0x66,0x66,0x66,0x66,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC6,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xDC,0x66,0x66,0x66,0x66,0x66,0x7C,0x60,0x60,0xF0,0x00,
0x00,0x00,0x00,0x00,0x00,0x76,0xCC,0xCC,0xCC,0xCC,0xCC,0x7C,0x0C,0x0C,0x1E,0x00,
0x00,0x00,0x00,0x00,0x00,0xDC,0x76,0x62,0x60,0x60,0x60,0xF0,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x7C,0xC6,0x60,0x38,0x0C,0xC6,0x7C,0x00,0x00,0x00,0x00,
0x00,0x00,0x10,0x30,0x30,0xFC,0x30,0x30,0x30,0x30,0x36,0x1C,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0x76,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xC6,0xC6,0xC6,0xD6,0xD6,0xFE,0x6C,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xC6,0x6C,0x38,0x38,0x38,0x6C,0xC6,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x7E,0x06,0x0C,0xF8,0x00,
0x00,0x00,0x00,0x00,0x00,0xFE,0xCC,0x18,0x30,0x60,0xC6,0xFE,0x00,0x00,0x00,0x00,
0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00,
0x00,0x00,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00,0x00,
0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00,
0x00,0x00,0x76,0xDC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x10,0x38,0x6C,0xC6,0xC6,0xC6,0xFE,0x00,0x00,0x00,0x00,0x00
};
/* ASCII Table: each character is 16 column (16dots large)
and 24 raw (24 dots high) */
const uint16_t ASCII_Table_16x24[] =
{
/**
* @brief Space ' '
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '!'
*/
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '"'
*/
0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '#'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
/**
* @brief '$'
*/
0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
/**
* @brief '%'
*/
0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
/**
* @brief '&'
*/
0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '''
*/
0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '('
*/
0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
/**
* @brief ')'
*/
0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
/**
* @brief '*'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '+'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief ','
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
/**
* @brief '-'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '.'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '/'
*/
0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '0'
*/
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '1'
*/
0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '2'
*/
0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '3'
*/
0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '4'
*/
0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '5'
*/
0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '6'
*/
0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '7'
*/
0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '8'
*/
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '9'
*/
0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief ':'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief ';'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
/**
* @brief '<'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '='
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '>'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '?'
*/
0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '@'
*/
0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'A'
*/
0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'B'
*/
0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'C'
*/
0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'D'
*/
0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'E'
*/
0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'F'
*/
0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'G'
*/
0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'H'
*/
0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'I'
*/
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'J'
*/
0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'K'
*/
0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'L'
*/
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'M'
*/
0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'N'
*/
0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'O'
*/
0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'P'
*/
0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'Q'
*/
0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'R'
*/
0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'S'
*/
0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'T'
*/
0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'U'
*/
0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'V'
*/
0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'W'
*/
0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'X'
*/
0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'Y'
*/
0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'Z'
*/
0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '['
*/
0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
/**
* @brief '\'
*/
0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief ']'
*/
0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
/**
* @brief '^'
*/
0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '_'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '''
*/
0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'a'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'b'
*/
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'c'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'd'
*/
0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'e'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'f'
*/
0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'g'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
/**
* @brief 'h'
*/
0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'i'
*/
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'j'
*/
0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
/**
* @brief 'k'
*/
0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'l'
*/
0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'm'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'n'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'o'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'p'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
/**
* @brief 'q'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
/**
* @brief 'r'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 's'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 't'
*/
0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'u'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'v'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'w'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'x'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief 'y'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
/**
* @brief 'z'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
/**
* @brief '{'
*/
0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
/**
* @brief '|'
*/
0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
/**
* @brief '}'
*/
0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
/**
* @brief '~'
*/
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
};

20
board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/main.h Normal file
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/*!
\file main.h
\brief the header file of main
*/
/*
Copyright (C) 2016 GigaDevice
2016-08-15, V1.0.0, firmware for GD32F4xx
*/
#ifndef __MAIN_H
#define __MAIN_H
/* led spark function */
void led_spark(void);
#endif /* __MAIN_H */

48
board/GigaDevice_GD32E507Z_EVAL/BSP/Inc/systick.h Normal file
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/*!
\file systick.h
\brief the header file of systick
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef SYS_TICK_H
#define SYS_TICK_H
#include <stdint.h>
/* configure systick */
void systick_config(void);
/* delay a time in milliseconds */
void delay_1ms(uint32_t count);
/* delay decrement */
void delay_decrement(void);
#endif /* SYS_TICK_H */

240
board/GigaDevice_GD32E507Z_EVAL/BSP/Src/gd32e507z_eval.c Normal file
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/*!
\file gd32e507z_eval.c
\brief firmware functions to manage leds, keys, COM ports
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e507z_eval.h"
/* private variables */
static uint32_t GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT,
LED3_GPIO_PORT, LED4_GPIO_PORT};
static uint32_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN, LED4_PIN};
static rcu_periph_enum COM_CLK[COMn] = {EVAL_COM0_CLK};
static uint32_t COM_TX_PIN[COMn] = {EVAL_COM0_TX_PIN};
static uint32_t COM_RX_PIN[COMn] = {EVAL_COM0_RX_PIN};
static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM0_GPIO_PORT};
static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM0_GPIO_CLK};
static rcu_periph_enum GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK,
LED3_GPIO_CLK, LED4_GPIO_CLK};
static uint32_t KEY_PORT[KEYn] = {KEY_A_GPIO_PORT,
KEY_B_GPIO_PORT,
KEY_C_GPIO_PORT,
KEY_D_GPIO_PORT,
KEY_CET_GPIO_PORT};
static uint32_t KEY_PIN[KEYn] = {KEY_A_PIN,
KEY_B_PIN,
KEY_C_PIN,
KEY_D_PIN,
KEY_CET_PIN};
static rcu_periph_enum KEY_CLK[KEYn] = {KEY_A_GPIO_CLK,
KEY_B_GPIO_CLK,
KEY_C_GPIO_CLK,
KEY_D_GPIO_CLK,
KEY_CET_GPIO_CLK};
static exti_line_enum KEY_EXTI_LINE[KEYn] = {KEY_A_EXTI_LINE,
KEY_B_EXTI_LINE,
KEY_C_EXTI_LINE,
KEY_D_EXTI_LINE,
KEY_CET_EXTI_LINE};
static uint8_t KEY_PORT_SOURCE[KEYn] = {KEY_A_EXTI_PORT_SOURCE,
KEY_B_EXTI_PORT_SOURCE,
KEY_C_EXTI_PORT_SOURCE,
KEY_D_EXTI_PORT_SOURCE,
KEY_CET_EXTI_PORT_SOURCE};
static uint8_t KEY_PIN_SOURCE[KEYn] = {KEY_A_EXTI_PIN_SOURCE,
KEY_B_EXTI_PIN_SOURCE,
KEY_C_EXTI_PIN_SOURCE,
KEY_D_EXTI_PIN_SOURCE,
KEY_CET_EXTI_PIN_SOURCE};
static uint8_t KEY_IRQn[KEYn] = {KEY_A_EXTI_IRQn,
KEY_B_EXTI_IRQn,
KEY_C_EXTI_IRQn,
KEY_D_EXTI_IRQn,
KEY_CET_EXTI_IRQn};
/*!
\brief configure led GPIO
\param[in] lednum: specify the led to be configured
\arg LED1
\arg LED2
\arg LED3
\arg LED4
\param[out] none
\retval none
*/
void gd_eval_led_init (led_typedef_enum lednum)
{
/* enable the led clock */
rcu_periph_clock_enable(GPIO_CLK[lednum]);
/* configure led GPIO port */
gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,GPIO_PIN[lednum]);
GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
}
/*!
\brief turn on selected led
\param[in] lednum: specify the led to be turned on
\arg LED1
\arg LED2
\arg LED3
\arg LED4
\param[out] none
\retval none
*/
void gd_eval_led_on(led_typedef_enum lednum)
{
GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
}
/*!
\brief turn off selected led
\param[in] lednum: specify the led to be turned off
\arg LED1
\arg LED2
\arg LED3
\arg LED4
\param[out] none
\retval none
*/
void gd_eval_led_off(led_typedef_enum lednum)
{
GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
}
/*!
\brief toggle selected led
\param[in] lednum: specify the led to be toggled
\arg LED1
\arg LED2
\arg LED3
\arg LED4
\param[out] none
\retval none
*/
void gd_eval_led_toggle(led_typedef_enum lednum)
{
gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum],
(bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum])));
}
/*!
\brief configure key
\param[in] key_num: specify the key to be configured
\arg KEY_A: wakeup key
\arg KEY_B: tamper key
\arg KEY_C: user key
\arg KEY_D: extension key
\arg KEY_CET: extension key
\param[in] key_mode: specify button mode
\arg KEY_MODE_GPIO: key will be used as simple IO
\arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt
\param[out] none
\retval none
*/
void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode)
{
/* enable the key clock */
rcu_periph_clock_enable(KEY_CLK[key_num]);
rcu_periph_clock_enable(RCU_AF);
/* configure button pin as input */
gpio_init(KEY_PORT[key_num], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[key_num]);
if (key_mode == KEY_MODE_EXTI) {
/* enable and set key EXTI interrupt to the lowest priority */
nvic_irq_enable(KEY_IRQn[key_num], 2U, 0U);
/* connect key EXTI line to key GPIO pin */
gpio_exti_source_select(KEY_PORT_SOURCE[key_num], KEY_PIN_SOURCE[key_num]);
/* configure key EXTI line */
exti_init(KEY_EXTI_LINE[key_num], EXTI_INTERRUPT, EXTI_TRIG_FALLING);
exti_interrupt_flag_clear(KEY_EXTI_LINE[key_num]);
}
}
/*!
\brief return the selected key state
\param[in] key: specify the key to be checked
\arg KEY_A: wakeup key
\arg KEY_B: tamper key
\arg KEY_C: user key
\arg KEY_D: extension key
\arg KEY_CET: extension key
\param[out] none
\retval the key's GPIO pin value
*/
uint8_t gd_eval_key_state_get(key_typedef_enum key)
{
return gpio_input_bit_get(KEY_PORT[key], KEY_PIN[key]);
}
/*!
\brief configure COM port
\param[in] com: COM on the board
\arg EVAL_COM0: COM0 on the board
\param[out] none
\retval none
*/
void gd_eval_com_init(uint32_t com)
{
uint32_t com_id = 0U;
if(EVAL_COM0 == com){
com_id = 0U;
}else{
while(1);
}
/* enable GPIO clock */
rcu_periph_clock_enable(COM_GPIO_CLK[com_id]);
/* enable USART clock */
rcu_periph_clock_enable(COM_CLK[com_id]);
/* connect port to USARTx_Tx */
gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, COM_TX_PIN[com_id]);
/* connect port to USARTx_Rx */
gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, COM_RX_PIN[com_id]);
/* USART configure */
usart_deinit(com);
usart_baudrate_set(com, 115200U);
usart_receive_config(com, USART_RECEIVE_ENABLE);
usart_transmit_config(com, USART_TRANSMIT_ENABLE);
usart_enable(com);
}

631
board/GigaDevice_GD32E507Z_EVAL/BSP/Src/gd32e507z_lcd_eval.c Normal file
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/*!
\file gd32e507c_lcd_eval.c
\brief LCD driver functions
\version 2020-06-30, V1.0.1, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x.h"
#include "gd32e507z_lcd_eval.h"
#include "lcd_font.h"
#define LCD_ILI9320 0x9320
#define LCD_ILI9325 0x9325
#define ABS(X) ((X) > 0 ? (X) : -(X))
uint16_t device_code;
/*!
\brief lcd peripheral initialize
\param[in] none
\param[out] none
\retval none
*/
void exmc_lcd_init(void)
{
exmc_norsram_parameter_struct lcd_init_struct;
exmc_norsram_timing_parameter_struct lcd_timing_init_struct;
/* EXMC clock enable */
rcu_periph_clock_enable(RCU_EXMC);
/* GPIO clock enable */
rcu_periph_clock_enable(RCU_GPIOD);
rcu_periph_clock_enable(RCU_GPIOE);
rcu_periph_clock_enable(RCU_GPIOG);
/* configure EXMC_D[0~15]*/
/* PD14(EXMC_D0), PD15(EXMC_D1),PD0(EXMC_D2), PD1(EXMC_D3), PD8(EXMC_D13), PD9(EXMC_D14), PD10(EXMC_D15) */
gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
/* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9),
PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */
gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
/* configure PE2(EXMC_A23) */
gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
/* configure PD4(NOE) and PD5(NWE) */
gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5);
/* configure PG9(EXMC NE1) */
gpio_init(GPIOG, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
lcd_timing_init_struct.asyn_access_mode = EXMC_ACCESS_MODE_A;
lcd_timing_init_struct.syn_data_latency = EXMC_DATALAT_2_CLK;
lcd_timing_init_struct.syn_clk_division = EXMC_SYN_CLOCK_RATIO_DISABLE;
lcd_timing_init_struct.bus_latency = 2;
lcd_timing_init_struct.asyn_data_setuptime = 18;
lcd_timing_init_struct.asyn_address_holdtime = 3;
lcd_timing_init_struct.asyn_address_setuptime = 8;
lcd_init_struct.norsram_region = EXMC_BANK0_NORSRAM_REGION1;
lcd_init_struct.write_mode = EXMC_ASYN_WRITE;
lcd_init_struct.extended_mode = DISABLE;
lcd_init_struct.asyn_wait = DISABLE;
lcd_init_struct.nwait_signal = DISABLE;
lcd_init_struct.memory_write = ENABLE;
lcd_init_struct.nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
lcd_init_struct.wrap_burst_mode = DISABLE;
lcd_init_struct.nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
lcd_init_struct.burst_mode = DISABLE;
lcd_init_struct.databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
lcd_init_struct.memory_type = EXMC_MEMORY_TYPE_SRAM;
lcd_init_struct.address_data_mux = DISABLE;
lcd_init_struct.read_write_timing = &lcd_timing_init_struct;
lcd_init_struct.write_timing = &lcd_timing_init_struct;
exmc_norsram_init(&lcd_init_struct);
exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION1);
}
/*!
\brief write data to the selected LCD register
\param[in] register_id: the selected register id
\param[in] value: the register value to be written
\param[out] none
\retval none
*/
void lcd_register_write(uint16_t register_id,uint16_t value)
{
*(__IO uint16_t *) (BANK0_LCD_C)= register_id;
*(__IO uint16_t *) (BANK0_LCD_D)= value;
}
/*!
\brief read the value of LCD register
\param[in] register_id: the register id
\param[out] none
\retval the register value
*/
uint16_t lcd_register_read(uint8_t register_id)
{
uint16_t data;
*(__IO uint16_t *) (BANK0_LCD_C)= register_id;
data = *(__IO uint16_t *) (BANK0_LCD_D);
return data;
}
/*!
\brief write command to LCD register
\param[in] value: the register value to be written
\param[out] none
\retval none
*/
void lcd_command_write(uint16_t value)
{
/* write 16-bit index, then write reg */
*(__IO uint16_t *) (BANK0_LCD_C) = value;
}
/*!
\brief prepare to write to the LCD GRAM register(R22h)
\param[in] none
\param[out] none
\retval none
*/
void lcd_gram_write_prepare(void)
{
*(__IO uint16_t *) (BANK0_LCD_C) = 0x0022;
}
/*!
\brief write RGB code to the LCD GRAM register
\param[in] rgb_code: the pixel color in RGB mode (5-6-5)
\param[out] none
\retval none
*/
void lcd_gram_write(uint16_t rgb_code)
{
/* write 16-bit GRAM register */
*(__IO uint16_t *) (BANK0_LCD_D) = rgb_code;
}
/*!
\brief read data from GRAM
\param[in] none
\param[out] none
\retval GRAM value
*/
uint16_t lcd_gram_read(void)
{
uint16_t data;
/* write GRAM register (R22h) */
*(__IO uint16_t *) (BANK0_LCD_C) = 0x0022;
/* dummy read (invalid data) */
data = *(__IO uint16_t *) (BANK0_LCD_D);
data = *(__IO uint16_t *) (BANK0_LCD_D);
return data;
}
/*!
\brief initialize the LCD
\param[in] none
\param[out] none
\retval none
*/
void lcd_init(void)
{
__IO uint16_t i;
/* read the LCD controller device code */
device_code = lcd_register_read(0x0000);
if(0x8989 == device_code){ // SSD1289
lcd_register_write(0x0000,0x0001);
lcd_register_write(0x0003,0xA8A4);
lcd_register_write(0x000C,0x0000);
lcd_register_write(0x000D,0x080C);
lcd_register_write(0x000E,0x2B00);
lcd_register_write(0x001E,0x00B0);
lcd_register_write(0x0001,0x2B3F);
lcd_register_write(0x0002,0x0600);
lcd_register_write(0x0010,0x0000);
lcd_register_write(0x0011,0x6070);
lcd_register_write(0x0005,0x0000);
lcd_register_write(0x0006,0x0000);
lcd_register_write(0x0016,0xEF1C);
lcd_register_write(0x0017,0x0003);
lcd_register_write(0x0007,0x0233);
lcd_register_write(0x000B,0x0000);
lcd_register_write(0x000F,0x0000);
lcd_register_write(0x0041,0x0000);
lcd_register_write(0x0042,0x0000);
lcd_register_write(0x0048,0x0000);
lcd_register_write(0x0049,0x013F);
lcd_register_write(0x004A,0x0000);
lcd_register_write(0x004B,0x0000);
lcd_register_write(0x0044,0xEF00);
lcd_register_write(0x0045,0x0000);
lcd_register_write(0x0046,0x013F);
lcd_register_write(0x0030,0x0707);
lcd_register_write(0x0031,0x0204);
lcd_register_write(0x0032,0x0204);
lcd_register_write(0x0033,0x0502);
lcd_register_write(0x0034,0x0507);
lcd_register_write(0x0035,0x0204);
lcd_register_write(0x0036,0x0204);
lcd_register_write(0x0037,0x0502);
lcd_register_write(0x003A,0x0302);
lcd_register_write(0x003B,0x0302);
lcd_register_write(0x0023,0x0000);
lcd_register_write(0x0024,0x0000);
lcd_register_write(0x0025,0x8000);
lcd_register_write(0x004e,0);
lcd_register_write(0x004f,0);
}else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320
lcd_register_write(0x01,0x0100); //driver output control
lcd_register_write(0x02,0x0700); //lcd driver waveform control
lcd_register_write(0x03,0x1020); //entry mode set
lcd_register_write(0x04,0x0000); //resizing control
lcd_register_write(0x08,0x0202); //display control 2
lcd_register_write(0x09,0x0000); //display control 3
lcd_register_write(0x0a,0x0000); //frame cycle control
lcd_register_write(0x0c,(1<<0)); //extern display interface control 1
lcd_register_write(0x0d,0x0000); //frame maker position
lcd_register_write(0x0f,0x0000); //extern display interface control 2
for(i=50000;i>0;i--);
lcd_register_write(0x07,0x0101); //display control
for(i=50000;i>0;i--);
lcd_register_write(0x10,(1<<12)|(0<<8)|(1<<7)|(1<<6)|(0<<4)); //power control 1
lcd_register_write(0x11,0x0007); //power control 2
lcd_register_write(0x12,(1<<8)|(1<<4)|(0<<0)); //power control 3
lcd_register_write(0x13,0x0b00); //power control 4
lcd_register_write(0x29,0x0000); //power control 7
lcd_register_write(0x2b,(1<<14)|(1<<4));
lcd_register_write(0x50,0); //set x start
lcd_register_write(0x51,239); //set x end
lcd_register_write(0x52,0); //set y start
lcd_register_write(0x53,319); //set y end
lcd_register_write(0x60,0x2700); //driver output control
lcd_register_write(0x61,0x0001); //driver output control
lcd_register_write(0x6a,0x0000); //vertical srcoll control
lcd_register_write(0x80,0x0000); //display position? partial display 1
lcd_register_write(0x81,0x0000); //ram address start? partial display 1
lcd_register_write(0x82,0x0000); //ram address end-partial display 1
lcd_register_write(0x83,0x0000); //display position? partial display 2
lcd_register_write(0x84,0x0000); //ram address start? partial display 2
lcd_register_write(0x85,0x0000); //ram address end? partial display 2
lcd_register_write(0x90,(0<<7)|(16<<0)); //frame cycle control
lcd_register_write(0x92,0x0000); //panel interface control 2
lcd_register_write(0x93,0x0001); //panel interface control 3
lcd_register_write(0x95,0x0110); //frame cycle control
lcd_register_write(0x97,(0<<8));
lcd_register_write(0x98,0x0000); //frame cycle control
for(i=50000;i>0;i--);
lcd_register_write(0x07,0x0173);
for(i=50000;i>0;i--);
}else{
return;
}
for(i=50000;i>0;i--);
}
/*!
\brief set the cursor of LCD
\param[in] x: the row-coordinate
\param[in] y: the column-coordinate
\param[out] none
\retval none
*/
void lcd_cursor_set(uint16_t x,uint16_t y)
{
if(0x8989 == device_code){ // SSD1289
lcd_register_write(0x004e, x);
lcd_register_write(0x004f, y);
}else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320
lcd_register_write(0x20, x);
lcd_register_write(0x21, y);
}
}
/*!
\brief clear the LCD screen to the specified color
\param[in] color: specified screen color
\param[out] none
\retval none
*/
void lcd_clear(uint16_t color)
{
uint32_t index=0;
if(0x8989 == device_code){ // SSD1289
lcd_cursor_set(0,0);
/* prepare to write GRAM */
lcd_gram_write_prepare();
for(index=0; index<LCD_PIXEL_WIDTH*LCD_PIXEL_HEIGHT; index++){
*(__IO uint16_t *) (BANK0_LCD_D) = color;
}
}else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320
lcd_register_write(0x20, 0);
lcd_register_write(0x21, 0);
lcd_command_write(0x22);
for(index=0; index<LCD_PIXEL_WIDTH*LCD_PIXEL_HEIGHT; index++){
*(__IO uint16_t *) (BANK0_LCD_D) = color;
}
}
}
/*!
\brief set the point according to the specified position and color
\param[in] x: the row-coordinate
\param[in] y: the column-coordinate
\param[in] point: specified color of the point
\param[out] none
\retval none
*/
void lcd_point_set(uint16_t x,uint16_t y,uint16_t point)
{
if ((x > LCD_PIXEL_HEIGHT)||(y > LCD_PIXEL_WIDTH)){
return;
}
if(0x8989 == device_code){ // SSD1289
lcd_cursor_set(x,y);
lcd_gram_write_prepare();
lcd_gram_write(point);
}else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320
lcd_register_write(0x20, x);
lcd_register_write(0x21, y);
lcd_register_write(0x22, point);
}
}
/*!
\brief get point GRAM according to the specified position
\param[in] x: the row-coordinate
\param[in] y: the column-coordinate
\param[out] none
\retval GRAM value of point
*/
uint16_t lcd_point_get(uint16_t x,uint16_t y)
{
uint16_t data;
if ((x > LCD_PIXEL_HEIGHT)||(y > LCD_PIXEL_WIDTH)){
return 0;
}
lcd_cursor_set(x,y);
data = lcd_gram_read();
return data;
}
/*!
\brief set window area
\param[in] start_x: the start position of row-coordinate
\param[in] start_y: the start position of column-coordinate
\param[in] end_x: the end position of row-coordinate
\param[in] end_y: the end position of column-coordinate
\param[out] none
\retval none
*/
void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y)
{
if(0x8989 == device_code){ // SSD1289
lcd_register_write(0x0044, start_x + (end_x<<8));
lcd_register_write(0x0045, start_y);
lcd_register_write(0x0046, end_y);
lcd_cursor_set(start_x, start_y);
lcd_gram_write_prepare();
}else if((0x9320 == device_code) || (0x9300 == device_code)){ //ILI9320
lcd_register_write(0x0050, start_x);
lcd_register_write(0x0052, start_y);
lcd_register_write(0x0051, end_x);
lcd_register_write(0x0053, end_y);
lcd_cursor_set(start_x, start_y);
lcd_gram_write_prepare();
}
}
/*!
\brief draw a horizontal line on LCD screen
\param[in] x: the row-coordinate
\param[in] start_y: the start column-coordinate
\param[in] end_y: the end column-coordinate
\param[in] color: specified color of the point
\param[in] width: line width
\param[out] none
\retval none
*/
void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width)
{
uint16_t i, y;
for (i = 0; i < width; i++) {
uint16_t sx = x + i;
for (y = start_y; y < end_y; y++) {
lcd_point_set(sx, y, color);
}
}
}
/*!
\brief draw a vertical line on LCD screen
\param[in] start_x: the start column-coordinate
\param[in] end_x: the end column-coordinate
\param[in] y: the row-coordinate
\param[in] color: specified color of the point
\param[in] width: line width
\param[out] none
\retval none
*/
void lcd_vline_draw(uint16_t start_x,uint16_t end_x,uint16_t y,uint16_t color,uint16_t width)
{
uint16_t i, x;
for (i = 0; i < width; i++) {
uint16_t sy = y + i;
for (x = start_x; x < end_x; x++) {
lcd_point_set(x, sy, color);
}
}
}
/*!
\brief draw a rectangle according to the specified position and color
\param[in] start_x: the start position of row-coordinate
\param[in] start_y: the start position of column-coordinate
\param[in] end_x: the end position of row-coordinate
\param[in] end_y: the end position of column-coordinate
\param[in] point: specified color of the point
\param[out] none
\retval none
*/
void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point)
{
uint16_t x,y;
x=start_x;
y=start_y;
/* draw four lines */
for(x=start_x;x<end_x;x++){
/* draw a point */
lcd_point_set(x,y,point);
}
for(y=start_y;y<end_y;y++){
lcd_point_set(x,y,point);
}
for(x=end_x;x>start_x;x--){
lcd_point_set(x,y,point);
}
for(y=end_y;y>start_y;y--){
lcd_point_set(x,y,point);
}
}
/*!
\brief fill the specified color to a rectangle
\param[in] start_x: the start position of row-coordinate
\param[in] start_y: the start position of column-coordinate
\param[in] end_x: the end position of row-coordinate
\param[in] end_y: the end position of column-coordinate
\param[in] color: specified color
\param[out] none
\retval none
*/
void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color)
{
uint16_t x, y;
x = start_x;
y = start_y;
for (x = start_x; x < end_x; x++) {
for (y = start_y; y < end_y; y++) {
lcd_point_set(x, y, color);
}
}
}
/*!
\brief draw a picture on LCD screen according to the specified position
\param[in] start_x: the start position of row-coordinate
\param[in] start_y: the start position of column-coordinate
\param[in] end_x: the end position of row-coordinate
\param[in] end_y: the end position of column-coordinate
\param[in] pic: the picture pointer
\param[out] none
\retval none
*/
void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic)
{
uint32_t i, total;
uint16_t *picturepointer = pic;
uint16_t x,y;
x = start_x;
y = start_y;
total = (end_x - start_x + 1) * (end_y - start_y + 1);
for(i = 0; i < total; i ++){
/* set point according to the specified position and color */
lcd_point_set(x,y,*picturepointer++);
x++;
if(x > end_x){
y++;
x = start_x;
}
}
}
/*!
\brief display a char on LCD screen according to the specified position
\param[in] x: the start position of row-coordinate
\param[in] y: the start position of column-coordinate
\param[in] c: the char
\param[in] char_color: the color of char
\param[in] c_format: the structure of char format
font: CHAR_FONT_8_16 or CHAR_FONT_16_24
direction: CHAR_DIRECTION_HORIZONTAL or CHAR_DIRECTION_VERTICAL
char_color: the color of char
bk_color: the color of background
\param[out] none
\retval none
*/
void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format)
{
uint16_t i = 0, j = 0;
uint8_t temp_char = 0;
uint16_t temp_char_16 = 0;
if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */
for (i = 0; i < 16; i++) {
temp_char = ascii_8x16[((c - 0x20) * 16) + i];
if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){
for (j = 0; j < 8; j++) {
if (((temp_char >> (7 - j)) & 0x01) == 0x01) {
/* set point of char */
lcd_point_set(x - i, y + j, c_format.char_color);
} else {
/* set point of background */
lcd_point_set(x - i, y + j, c_format.bk_color);
}
}
}else{
for (j = 0; j < 8; j++) {
if (((temp_char >> (7 - j)) & 0x01) == 0x01) {
/* set point of char */
lcd_point_set(x + j, y + i, c_format.char_color);
} else {
/* set point of background */
lcd_point_set(x + j, y + i, c_format.bk_color);
}
}
}
}
}else if(CHAR_FONT_16_24 == c_format.font){ /* 16x24 ASCII */
for (i = 0; i < 24; i++) {
temp_char_16 = ASCII_Table_16x24[((c - 0x20) * 24) + i];
if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){
for (j = 0; j < 16; j++) {
if (((temp_char_16 >> j) & 0x01) == 0x01) {
/* set point of char */
lcd_point_set(x - i, y + j, c_format.char_color);
} else {
/* set point of background */
lcd_point_set(x - i, y + j, c_format.bk_color);
}
}
}else{
for (j = 0; j < 16; j++) {
if (((temp_char_16 >> j) & 0x01) == 0x01) {
/* set point of char */
lcd_point_set(x + j, y + i, c_format.char_color);
} else {
/* set point of background */
lcd_point_set(x + j, y + i, c_format.bk_color);
}
}
}
}
}
}

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/*!
\file gd32e50x_it.c
\brief interrupt service routines
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_it.h"
#include "systick.h"
#include "tos_k.h"
/*!
\brief this function handles NMI exception
\param[in] none
\param[out] none
\retval none
*/
void NMI_Handler(void)
{
}
/*!
\brief this function handles HardFault exception
\param[in] none
\param[out] none
\retval none
*/
void HardFault_Handler(void)
{
/* if Hard Fault exception occurs, go to infinite loop */
while (1){
}
}
/*!
\brief this function handles MemManage exception
\param[in] none
\param[out] none
\retval none
*/
void MemManage_Handler(void)
{
/* if Memory Manage exception occurs, go to infinite loop */
while (1){
}
}
/*!
\brief this function handles BusFault exception
\param[in] none
\param[out] none
\retval none
*/
void BusFault_Handler(void)
{
/* if Bus Fault exception occurs, go to infinite loop */
while (1){
}
}
/*!
\brief this function handles UsageFault exception
\param[in] none
\param[out] none
\retval none
*/
void UsageFault_Handler(void)
{
/* if Usage Fault exception occurs, go to infinite loop */
while (1){
}
}
/*!
\brief this function handles SVC exception
\param[in] none
\param[out] none
\retval none
*/
void SVC_Handler(void)
{
}
/*!
\brief this function handles DebugMon exception
\param[in] none
\param[out] none
\retval none
*/
void DebugMon_Handler(void)
{
}
/*!
\brief this function handles PendSV exception
\param[in] none
\param[out] none
\retval none
*/
//void PendSV_Handler(void)
//{
//}
/*!
\brief this function handles SysTick exception
\param[in] none
\param[out] none
\retval none
*/
void SysTick_Handler(void)
{
if(tos_knl_is_running())
{
tos_knl_irq_enter();
tos_tick_handler();
tos_knl_irq_leave();
}
delay_decrement();
}

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#include "gd32e50x.h"
#include "gd32e507z_eval.h"
#include "systick.h"
#include <stdio.h>
#include "cmsis_os.h"
#define TASK1_STK_SIZE 512
void task1(void *arg);
osThreadDef(task1, osPriorityNormal, 2, TASK1_STK_SIZE);
#define TASK2_STK_SIZE 512
void task2(void *arg);
osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
void board_init(void)
{
/* initialize the leds */
gd_eval_led_init(LED1);
gd_eval_led_init(LED2);
gd_eval_led_init(LED3);
gd_eval_led_init(LED4);
/* close all of leds */
gd_eval_led_off(LED1);
gd_eval_led_off(LED2);
gd_eval_led_off(LED3);
gd_eval_led_off(LED4);
/* configure systick */
systick_config();
/* configure EVAL_COM0 */
gd_eval_com_init(EVAL_COM0);
}
void task1(void *arg)
{
while (1) {
gd_eval_led_toggle(LED1);
gd_eval_led_toggle(LED2);
printf("++++++++This is task1!\r\n");
osDelay(2000);
}
}
void task2(void *arg)
{
while (1) {
gd_eval_led_toggle(LED3);
gd_eval_led_toggle(LED4);
printf("---------This is task2!\r\n");
osDelay(1000);
}
}
int main(void)
{
board_init();
printf("Welcome to TencentOS Tiny!\r\n");
osKernelInitialize();
osThreadCreate(osThread(task1), NULL); // Create task1
osThreadCreate(osThread(task2), NULL); // Create task2
osKernelStart();
}
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
usart_data_transmit(EVAL_COM0, (uint8_t)ch);
while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
return ch;
}

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/*!
\file systick.c
\brief the systick configuration file
\version 2020-06-30, V1.0.0, demo for GD32E50x
\version 2020-08-26, V1.1.0, demo for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x.h"
#include "systick.h"
static __IO uint32_t delay;
/*!
\brief configure systick
\param[in] none
\param[out] none
\retval none
*/
void systick_config(void)
{
/* setup systick timer for 1000Hz interrupts */
if (SysTick_Config(SystemCoreClock / 1000U)){
/* capture error */
while (1){
}
}
/* configure the systick handler priority */
NVIC_SetPriority(SysTick_IRQn, 0x00U);
}
/*!
\brief delay a time in milliseconds
\param[in] count: count in milliseconds
\param[out] none
\retval none
*/
void delay_1ms(uint32_t count)
{
delay = count;
while(0U != delay){
}
}
/*!
\brief delay decrement
\param[in] none
\param[out] none
\retval none
*/
void delay_decrement(void)
{
if (0U != delay){
delay--;
}
}

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\GD32E507Z_EVAL.ewp</path>
</project>
<batchBuild/>
</workspace>

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#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "gd32e50x.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 0u
#define TOS_CFG_OBJECT_VERIFY_EN 1u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 1u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x100
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
#define TOS_CFG_MAIL_QUEUE_EN 1u
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u
#define TOS_CFG_TIMER_EN 0u
#define TOS_CFG_PWR_MGR_EN 0u
#define TOS_CFG_TICKLESS_EN 0u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#define TOS_CFG_TIMER_AS_PROC 1u
#endif

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/*!
\file gd32e50x.h
\brief general definitions for GD32E50x
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_H
#define GD32E50X_H
#ifdef __cplusplus
extern "C" {
#endif
/* define GD32E50X */
#if !defined (GD32EPRT) && !defined (GD32E50X_HD) && !defined (GD32E50X_XD) && !defined (GD32E50X_CL)
#error "Please select chip type in project configuration"
/* #define GD32EPRT */
/* #define GD32E50X_HD */
/* #define GD32E50X_XD */
/* #define GD32E50X_CL */
#endif /* define GD32E50X */
#if !defined (GD32E50X)
#error "Please select the target GD32E50x device used in your application (in gd32e50x.h file)"
#endif /* undefine GD32E50X tip */
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined HXTAL_VALUE
#ifdef GD32E50X_CL
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
#else
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
#endif /* HXTAL_VALUE */
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined (HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
#if !defined (IRC8M_VALUE)
#define IRC8M_VALUE ((uint32_t)8000000)
#endif /* internal 8MHz RC oscillator value */
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
#if !defined (IRC8M_STARTUP_TIMEOUT)
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 8MHz RC oscillator startup timeout */
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
#if !defined (IRC48M_VALUE)
#define IRC48M_VALUE ((uint32_t)48000000)
#endif /* internal 48MHz RC oscillator value */
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
#if !defined (IRC40K_VALUE)
#define IRC40K_VALUE ((uint32_t)40000)
#endif /* internal 40KHz RC oscillator value */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined (LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* GD32E50x firmware library version number V1.0 */
#define __GD32E50X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __GD32E50X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __GD32E50X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __GD32E50X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __GD32E50X_STDPERIPH_VERSION ((__GD32E50X_STDPERIPH_VERSION_MAIN << 24)\
|(__GD32E50X_STDPERIPH_VERSION_SUB1 << 16)\
|(__GD32E50X_STDPERIPH_VERSION_SUB2 << 8)\
|(__GD32E50X_STDPERIPH_VERSION_RC))
/* configuration of the Cortex-M33 processor and core peripherals */
#define __CM33_REV 0x0003U /*!< Core revision r0p3 */
#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
#define __MPU_PRESENT 1U /*!< MPU is present */
#define __VTOR_PRESENT 1U /*!< VTOR is present */
#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#define __DSP_PRESENT 1 /*!< DSP present */
/* define interrupt number */
typedef enum IRQn
{
/* Cortex-M33 processor exceptions numbers */
NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */
HardFault_IRQn = -13, /*!< hard-fault interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M33 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M33 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M33 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M33 sv call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M33 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M33 pend sv interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M33 system tick interrupt */
/* interrupt numbers */
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
FMC_IRQn = 4, /*!< FMC interrupt */
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupt */
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupt */
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupt */
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupt */
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupt */
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
#ifdef GD32EPRT
USBD_HP_IRQn = 19, /*!< USBD High Priority interrupts */
USBD_LP_IRQn = 20, /*!< USBD Low Priority interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt */
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupt */
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupt */
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt */
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
ENET_IRQn = 61, /*!< ENET global interrupt */
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
USART5_IRQn = 84, /*!< USART5 interrupt */
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
#endif /* GD32EPRT */
#ifdef GD32E50X_HD
USBD_HP_IRQn = 19, /*!< USBD High Priority interrupts */
USBD_LP_IRQn = 20, /*!< USBD Low Priority interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt */
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupt */
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupt */
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt */
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
SDIO_IRQn = 49, /*!< SDIO global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */
SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */
SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */
SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */
SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */
SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */
SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
USART5_IRQn = 84, /*!< USART5 interrupt */
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
#endif /* GD32E50X_HD */
#ifdef GD32E50X_XD
USBD_HP_IRQn = 19, /*!< USBD High Priority */
USBD_LP_IRQn = 20, /*!< USBD Low Priority */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
SDIO_IRQn = 49, /*!< SDIO global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */
SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */
SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */
SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */
SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */
SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */
SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
USART5_IRQn = 84, /*!< USART5 interrupt */
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
#endif /* GD32E50X_XD */
#ifdef GD32E50X_CL
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
USBHS_WKUP_IRQn = 42, /*!< USBHS wakeup interrupt */
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
ENET_IRQn = 61, /*!< ENET global interrupt */
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
USBHS_IRQn = 67, /*!< USBHS global interrupt */
SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */
SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */
SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */
SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */
SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */
USBHS_EP1_OUT_IRQn = 74, /*!< USBHS end point 1 out interrupt */
USBHS_EP1_IN_IRQn = 75, /*!< USBHS end point 1 in interrupt */
SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */
SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */
I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */
I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */
USART5_IRQn = 84, /*!< USART5 global interrupt */
I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */
USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */
TMU_IRQn = 87, /*!< TMU interrupt */
#endif /* GD32E50X_CL */
} IRQn_Type;
/* includes */
#include "core_cm33.h"
#include "system_gd32e50x.h"
#include <stdint.h>
/* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */
#define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr))
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
#define I2S_add_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S_add base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
/* advanced peripheral bus 2 memory map */
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
#define SHRTIMER_BASE (APB2_BUS_BASE + 0x00007400U) /*!< SHRTIMER base address */
#define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */
/* advanced high performance bus 1 memory map */
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
#define TMU_BASE (AHB1_BUS_BASE + 0x00068000U) /*!< TMU base address */
#define USBHS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
/* advanced high performance bus 3 memory map */
#define EXMC_BASE (AHB3_BUS_BASE + 0x40000000U) /*!< EXMC base address */
/* option byte and debug memory map */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0xE0044000U) /*!< DBG base address */
#define SQPI_BASE ((uint32_t)0xA0001000U) /*!< SQPI base address */
#include "gd32e50x_libopt.h"
#ifdef __cplusplus
}
#endif
#endif /* GD32E50X_H */

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/*!
\file system_gd32e50x.h
\brief CMSIS Cortex-M33 Device Peripheral Access Layer Header File for
GD32E50x Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32E50X_H
#define SYSTEM_GD32E50X_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from CPU registers */
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32E50X_H */

417
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32e50x_cl.s Normal file
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;/*!
; \file startup_gd32e50x_cl.s
; \brief start up file
;
; \version 2020-03-10, V1.0.0, firmware for GD32E50x
; \version 2020-08-26, V1.1.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; /* reset Vector Mapped to at Address 0 */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; /* external interrupts handler */
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBHS_WKUP_IRQHandler ; 58:USBHS Wakeup
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD 0 ; Reserved
DCD EXMC_IRQHandler ; 64:EXMC
DCD 0 ; Reserved
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
DCD ENET_IRQHandler ; 77:Ethernet
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USBHS_IRQHandler ; 83:USBHS
DCD 0 ; Reserved
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
DCD USBHS_EP1_OUT_IRQHandler ; 90:USBHS end point 1 out
DCD USBHS_EP1_IN_IRQHandler ; 91:USBHS end point 1 in
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD TMU_IRQHandler ; 103:TMU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/* reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/* dummy Exception Handlers */
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; /* external interrupts handler */
EXPORT WWDGT_IRQHandler [WEAK]
EXPORT LVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT RCU_CTC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA0_Channel0_IRQHandler [WEAK]
EXPORT DMA0_Channel1_IRQHandler [WEAK]
EXPORT DMA0_Channel2_IRQHandler [WEAK]
EXPORT DMA0_Channel3_IRQHandler [WEAK]
EXPORT DMA0_Channel4_IRQHandler [WEAK]
EXPORT DMA0_Channel5_IRQHandler [WEAK]
EXPORT DMA0_Channel6_IRQHandler [WEAK]
EXPORT ADC0_1_IRQHandler [WEAK]
EXPORT EXTI5_9_IRQHandler [WEAK]
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
EXPORT TIMER0_Channel_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT I2C0_EV_IRQHandler [WEAK]
EXPORT I2C0_ER_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI10_15_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBHS_WKUP_IRQHandler [WEAK]
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
EXPORT TIMER7_Channel_IRQHandler [WEAK]
EXPORT EXMC_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIMER5_DAC_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT DMA1_Channel0_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT ENET_WKUP_IRQHandler [WEAK]
EXPORT USBHS_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ2_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ3_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ4_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ5_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ6_IRQHandler [WEAK]
EXPORT USBHS_EP1_OUT_IRQHandler [WEAK]
EXPORT USBHS_EP1_IN_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ0_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ1_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT USART5_IRQHandler [WEAK]
EXPORT I2C2_WKUP_IRQHandler [WEAK]
EXPORT USART5_WKUP_IRQHandler [WEAK]
EXPORT TMU_IRQHandler [WEAK]
;/* external interrupts handler */
WWDGT_IRQHandler
LVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FMC_IRQHandler
RCU_CTC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA0_Channel0_IRQHandler
DMA0_Channel1_IRQHandler
DMA0_Channel2_IRQHandler
DMA0_Channel3_IRQHandler
DMA0_Channel4_IRQHandler
DMA0_Channel5_IRQHandler
DMA0_Channel6_IRQHandler
ADC0_1_IRQHandler
EXTI5_9_IRQHandler
TIMER0_BRK_TIMER8_IRQHandler
TIMER0_UP_TIMER9_IRQHandler
TIMER0_TRG_CMT_TIMER10_IRQHandler
TIMER0_Channel_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
I2C0_EV_IRQHandler
I2C0_ER_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI0_IRQHandler
SPI1_I2S1ADD_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI10_15_IRQHandler
RTC_Alarm_IRQHandler
USBHS_WKUP_IRQHandler
TIMER7_BRK_TIMER11_IRQHandler
TIMER7_UP_TIMER12_IRQHandler
TIMER7_TRG_CMT_TIMER13_IRQHandler
TIMER7_Channel_IRQHandler
EXMC_IRQHandler
TIMER4_IRQHandler
SPI2_I2S2ADD_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
TIMER5_DAC_IRQHandler
TIMER6_IRQHandler
DMA1_Channel0_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
ENET_IRQHandler
ENET_WKUP_IRQHandler
USBHS_IRQHandler
SHRTIMER_IRQ2_IRQHandler
SHRTIMER_IRQ3_IRQHandler
SHRTIMER_IRQ4_IRQHandler
SHRTIMER_IRQ5_IRQHandler
SHRTIMER_IRQ6_IRQHandler
USBHS_EP1_OUT_IRQHandler
USBHS_EP1_IN_IRQHandler
SHRTIMER_IRQ0_IRQHandler
SHRTIMER_IRQ1_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
USART5_IRQHandler
I2C2_WKUP_IRQHandler
USART5_WKUP_IRQHandler
TMU_IRQHandler
B .
ENDP
ALIGN
; user Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

411
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32e50x_hd.s Normal file
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;/*!
; \file startup_gd32e50x_hd.s
; \brief start up file
;
; \version 2020-03-10, V1.0.0, firmware for GD32E50x
; \version 2020-08-26, V1.1.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; /* reset Vector Mapped to at Address 0 */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; /* external interrupts handler */
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD USBD_HP_IRQHandler ; 35:USBD HP
DCD USBD_LP_IRQHandler ; 36:USBD LP
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD ADC2_IRQHandler ; 63:ADC2
DCD EXMC_IRQHandler ; 64:EXMC
DCD SDIO_IRQHandler ; 65:SDIO
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/* reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/* dummy Exception Handlers */
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; /* external interrupts handler */
EXPORT WWDGT_IRQHandler [WEAK]
EXPORT LVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT RCU_CTC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA0_Channel0_IRQHandler [WEAK]
EXPORT DMA0_Channel1_IRQHandler [WEAK]
EXPORT DMA0_Channel2_IRQHandler [WEAK]
EXPORT DMA0_Channel3_IRQHandler [WEAK]
EXPORT DMA0_Channel4_IRQHandler [WEAK]
EXPORT DMA0_Channel5_IRQHandler [WEAK]
EXPORT DMA0_Channel6_IRQHandler [WEAK]
EXPORT ADC0_1_IRQHandler [WEAK]
EXPORT USBD_HP_IRQHandler [WEAK]
EXPORT USBD_LP_IRQHandler [WEAK]
EXPORT EXTI5_9_IRQHandler [WEAK]
EXPORT TIMER0_BRK_IRQHandler [WEAK]
EXPORT TIMER0_UP_IRQHandler [WEAK]
EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
EXPORT TIMER0_Channel_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT I2C0_EV_IRQHandler [WEAK]
EXPORT I2C0_ER_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI10_15_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBD_WKUP_IRQHandler [WEAK]
EXPORT TIMER7_BRK_IRQHandler [WEAK]
EXPORT TIMER7_UP_IRQHandler [WEAK]
EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
EXPORT TIMER7_Channel_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT EXMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIMER5_DAC_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT DMA1_Channel0_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ2_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ3_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ4_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ5_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ6_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ0_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ1_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT USART5_IRQHandler [WEAK]
EXPORT I2C2_WKUP_IRQHandler [WEAK]
EXPORT USART5_WKUP_IRQHandler [WEAK]
;/* external interrupts handler */
WWDGT_IRQHandler
LVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FMC_IRQHandler
RCU_CTC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA0_Channel0_IRQHandler
DMA0_Channel1_IRQHandler
DMA0_Channel2_IRQHandler
DMA0_Channel3_IRQHandler
DMA0_Channel4_IRQHandler
DMA0_Channel5_IRQHandler
DMA0_Channel6_IRQHandler
ADC0_1_IRQHandler
USBD_HP_IRQHandler
USBD_LP_IRQHandler
EXTI5_9_IRQHandler
TIMER0_BRK_IRQHandler
TIMER0_UP_IRQHandler
TIMER0_TRG_CMT_IRQHandler
TIMER0_Channel_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
I2C0_EV_IRQHandler
I2C0_ER_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI0_IRQHandler
SPI1_I2S1ADD_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI10_15_IRQHandler
RTC_Alarm_IRQHandler
USBD_WKUP_IRQHandler
TIMER7_BRK_IRQHandler
TIMER7_UP_IRQHandler
TIMER7_TRG_CMT_IRQHandler
TIMER7_Channel_IRQHandler
ADC2_IRQHandler
EXMC_IRQHandler
SDIO_IRQHandler
TIMER4_IRQHandler
SPI2_I2S2ADD_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
TIMER5_DAC_IRQHandler
TIMER6_IRQHandler
DMA1_Channel0_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_4_IRQHandler
SHRTIMER_IRQ2_IRQHandler
SHRTIMER_IRQ3_IRQHandler
SHRTIMER_IRQ4_IRQHandler
SHRTIMER_IRQ5_IRQHandler
SHRTIMER_IRQ6_IRQHandler
SHRTIMER_IRQ0_IRQHandler
SHRTIMER_IRQ1_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
USART5_IRQHandler
I2C2_WKUP_IRQHandler
USART5_WKUP_IRQHandler
B .
ENDP
ALIGN
; user Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

411
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32e50x_xd.s Normal file
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@@ -0,0 +1,411 @@
;/*!
; \file startup_gd32e50x_xd.s
; \brief start up file
;
; \version 2020-03-10, V1.0.0, firmware for GD32E50x
; \version 2020-08-26, V1.1.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; /* reset Vector Mapped to at Address 0 */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; /* external interrupts handler */
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD USBD_HP_IRQHandler ; 35:USBD HP
DCD USBD_LP_IRQHandler ; 36:USBD LP
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD ADC2_IRQHandler ; 63:ADC2
DCD EXMC_IRQHandler ; 64:EXMC
DCD SDIO_IRQHandler ; 65:SDIO
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
DCD 0 ; ReservedER
DCD 0 ; Reserved
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/* reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/* dummy Exception Handlers */
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; /* external interrupts handler */
EXPORT WWDGT_IRQHandler [WEAK]
EXPORT LVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT RCU_CTC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA0_Channel0_IRQHandler [WEAK]
EXPORT DMA0_Channel1_IRQHandler [WEAK]
EXPORT DMA0_Channel2_IRQHandler [WEAK]
EXPORT DMA0_Channel3_IRQHandler [WEAK]
EXPORT DMA0_Channel4_IRQHandler [WEAK]
EXPORT DMA0_Channel5_IRQHandler [WEAK]
EXPORT DMA0_Channel6_IRQHandler [WEAK]
EXPORT ADC0_1_IRQHandler [WEAK]
EXPORT USBD_HP_IRQHandler [WEAK]
EXPORT USBD_LP_IRQHandler [WEAK]
EXPORT EXTI5_9_IRQHandler [WEAK]
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
EXPORT TIMER0_Channel_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT I2C0_EV_IRQHandler [WEAK]
EXPORT I2C0_ER_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI10_15_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBD_WKUP_IRQHandler [WEAK]
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
EXPORT TIMER7_Channel_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT EXMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIMER5_DAC_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT DMA1_Channel0_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ2_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ3_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ4_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ5_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ6_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ0_IRQHandler [WEAK]
EXPORT SHRTIMER_IRQ1_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT USART5_IRQHandler [WEAK]
EXPORT I2C2_WKUP_IRQHandler [WEAK]
EXPORT USART5_WKUP_IRQHandler [WEAK]
;/* external interrupts handler */
WWDGT_IRQHandler
LVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FMC_IRQHandler
RCU_CTC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA0_Channel0_IRQHandler
DMA0_Channel1_IRQHandler
DMA0_Channel2_IRQHandler
DMA0_Channel3_IRQHandler
DMA0_Channel4_IRQHandler
DMA0_Channel5_IRQHandler
DMA0_Channel6_IRQHandler
ADC0_1_IRQHandler
USBD_HP_IRQHandler
USBD_LP_IRQHandler
EXTI5_9_IRQHandler
TIMER0_BRK_TIMER8_IRQHandler
TIMER0_UP_TIMER9_IRQHandler
TIMER0_TRG_CMT_TIMER10_IRQHandler
TIMER0_Channel_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
I2C0_EV_IRQHandler
I2C0_ER_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI0_IRQHandler
SPI1_I2S1ADD_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI10_15_IRQHandler
RTC_Alarm_IRQHandler
USBD_WKUP_IRQHandler
TIMER7_BRK_TIMER11_IRQHandler
TIMER7_UP_TIMER12_IRQHandler
TIMER7_TRG_CMT_TIMER13_IRQHandler
TIMER7_Channel_IRQHandler
ADC2_IRQHandler
EXMC_IRQHandler
SDIO_IRQHandler
TIMER4_IRQHandler
SPI2_I2S2ADD_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
TIMER5_DAC_IRQHandler
TIMER6_IRQHandler
DMA1_Channel0_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_4_IRQHandler
SHRTIMER_IRQ2_IRQHandler
SHRTIMER_IRQ3_IRQHandler
SHRTIMER_IRQ4_IRQHandler
SHRTIMER_IRQ5_IRQHandler
SHRTIMER_IRQ6_IRQHandler
SHRTIMER_IRQ0_IRQHandler
SHRTIMER_IRQ1_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
USART5_IRQHandler
I2C2_WKUP_IRQHandler
USART5_WKUP_IRQHandler
B .
ENDP
ALIGN
; user Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

398
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32eprt.s Normal file
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@@ -0,0 +1,398 @@
;/*!
; \file startup_gd32eprt.s
; \brief start up file
;
; \version 2020-08-26, V1.0.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; /* reset Vector Mapped to at Address 0 */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; /* external interrupts handler */
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD USBD_HP_IRQHandler ; 35:USBD HP
DCD USBD_LP_IRQHandler ; 36:USBD LP
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD ADC2_IRQHandler ; 63:ADC2
DCD EXMC_IRQHandler ; 64:EXMC
DCD 0 ; Reserved
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
DCD 0 ; Reserved
DCD ENET_IRQHandler ; 77:Ethernet
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/* reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/* dummy Exception Handlers */
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; /* external interrupts handler */
EXPORT WWDGT_IRQHandler [WEAK]
EXPORT LVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT RCU_CTC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA0_Channel0_IRQHandler [WEAK]
EXPORT DMA0_Channel1_IRQHandler [WEAK]
EXPORT DMA0_Channel2_IRQHandler [WEAK]
EXPORT DMA0_Channel3_IRQHandler [WEAK]
EXPORT DMA0_Channel4_IRQHandler [WEAK]
EXPORT DMA0_Channel5_IRQHandler [WEAK]
EXPORT DMA0_Channel6_IRQHandler [WEAK]
EXPORT ADC0_1_IRQHandler [WEAK]
EXPORT USBD_HP_IRQHandler [WEAK]
EXPORT USBD_LP_IRQHandler [WEAK]
EXPORT EXTI5_9_IRQHandler [WEAK]
EXPORT TIMER0_BRK_IRQHandler [WEAK]
EXPORT TIMER0_UP_IRQHandler [WEAK]
EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
EXPORT TIMER0_Channel_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT I2C0_EV_IRQHandler [WEAK]
EXPORT I2C0_ER_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_I2S1ADD_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI10_15_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBD_WKUP_IRQHandler [WEAK]
EXPORT TIMER7_BRK_IRQHandler [WEAK]
EXPORT TIMER7_UP_IRQHandler [WEAK]
EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
EXPORT TIMER7_Channel_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT EXMC_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT SPI2_I2S2ADD_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT TIMER5_DAC_IRQHandler [WEAK]
EXPORT TIMER6_IRQHandler [WEAK]
EXPORT DMA1_Channel0_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT ENET_WKUP_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT USART5_IRQHandler [WEAK]
EXPORT I2C2_WKUP_IRQHandler [WEAK]
EXPORT USART5_WKUP_IRQHandler [WEAK]
;/* external interrupts handler */
WWDGT_IRQHandler
LVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FMC_IRQHandler
RCU_CTC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA0_Channel0_IRQHandler
DMA0_Channel1_IRQHandler
DMA0_Channel2_IRQHandler
DMA0_Channel3_IRQHandler
DMA0_Channel4_IRQHandler
DMA0_Channel5_IRQHandler
DMA0_Channel6_IRQHandler
ADC0_1_IRQHandler
USBD_HP_IRQHandler
USBD_LP_IRQHandler
EXTI5_9_IRQHandler
TIMER0_BRK_IRQHandler
TIMER0_UP_IRQHandler
TIMER0_TRG_CMT_IRQHandler
TIMER0_Channel_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
I2C0_EV_IRQHandler
I2C0_ER_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI0_IRQHandler
SPI1_I2S1ADD_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI10_15_IRQHandler
RTC_Alarm_IRQHandler
USBD_WKUP_IRQHandler
TIMER7_BRK_IRQHandler
TIMER7_UP_IRQHandler
TIMER7_TRG_CMT_IRQHandler
TIMER7_Channel_IRQHandler
ADC2_IRQHandler
EXMC_IRQHandler
TIMER4_IRQHandler
SPI2_I2S2ADD_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
TIMER5_DAC_IRQHandler
TIMER6_IRQHandler
DMA1_Channel0_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_4_IRQHandler
ENET_IRQHandler
ENET_WKUP_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
USART5_IRQHandler
I2C2_WKUP_IRQHandler
USART5_WKUP_IRQHandler
B .
ENDP
ALIGN
; user Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

582
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32e50x_cl.s Normal file
View File

@@ -0,0 +1,582 @@
;/*!
; \file startup_gd32e50x_cl.s
; \brief start up file
;
; \version 2020-03-10, V1.0.0, firmware for GD32E50x
; \version 2020-08-26, V1.1.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; top of stack
DCD Reset_Handler ; Vector Number 1,Reset Handler
DCD NMI_Handler ; Vector Number 2,NMI Handler
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; Vector Number 11,SVCall Handler
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
; External Interrupts
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBHS_WKUP_IRQHandler ; 58:USBHS Wakeup
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD 0 ; Reserved
DCD EXMC_IRQHandler ; 64:EXMC
DCD 0 ; Reserved
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
DCD ENET_IRQHandler ; 77:Ethernet
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USBHS_IRQHandler ; 83:USBHS
DCD 0 ; Reserved
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
DCD USBHS_EP1_OUT_IRQHandler ; 90:USBHS end point 1 out
DCD USBHS_EP1_IN_IRQHandler ; 91:USBHS end point 1 in
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD TMU_IRQHandler ; 103:TMU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDGT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDGT_IRQHandler
B WWDGT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK RCU_CTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCU_CTC_IRQHandler
B RCU_CTC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI1_IRQHandler
PUBWEAK DMA0_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel0_IRQHandler
B DMA0_Channel0_IRQHandler
PUBWEAK DMA0_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel1_IRQHandler
B DMA0_Channel1_IRQHandler
PUBWEAK DMA0_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel2_IRQHandler
B DMA0_Channel2_IRQHandler
PUBWEAK DMA0_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel3_IRQHandler
B DMA0_Channel3_IRQHandler
PUBWEAK DMA0_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel4_IRQHandler
B DMA0_Channel4_IRQHandler
PUBWEAK DMA0_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel5_IRQHandler
B DMA0_Channel5_IRQHandler
PUBWEAK DMA0_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel6_IRQHandler
B DMA0_Channel6_IRQHandler
PUBWEAK ADC0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC0_1_IRQHandler
B ADC0_1_IRQHandler
PUBWEAK EXTI5_9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI5_9_IRQHandler
B EXTI5_9_IRQHandler
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_BRK_TIMER8_IRQHandler
B TIMER0_BRK_TIMER8_IRQHandler
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_UP_TIMER9_IRQHandler
B TIMER0_UP_TIMER9_IRQHandler
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_TRG_CMT_TIMER10_IRQHandler
B TIMER0_TRG_CMT_TIMER10_IRQHandler
PUBWEAK TIMER0_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_Channel_IRQHandler
B TIMER0_Channel_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK I2C0_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_EV_IRQHandler
B I2C0_EV_IRQHandler
PUBWEAK I2C0_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_ER_IRQHandler
B I2C0_ER_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_I2S1ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_I2S1ADD_IRQHandler
B SPI1_I2S1ADD_IRQHandler
PUBWEAK USART0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART0_IRQHandler
B USART0_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI10_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI10_15_IRQHandler
B EXTI10_15_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBHS_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBHS_WKUP_IRQHandler
B USBHS_WKUP_IRQHandler
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_BRK_TIMER11_IRQHandler
B TIMER7_BRK_TIMER11_IRQHandler
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_UP_TIMER12_IRQHandler
B TIMER7_UP_TIMER12_IRQHandler
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_TRG_CMT_TIMER13_IRQHandler
B TIMER7_TRG_CMT_TIMER13_IRQHandler
PUBWEAK TIMER7_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_Channel_IRQHandler
B TIMER7_Channel_IRQHandler
PUBWEAK EXMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXMC_IRQHandler
B EXMC_IRQHandler
PUBWEAK TIMER4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER4_IRQHandler
B TIMER4_IRQHandler
PUBWEAK SPI2_I2S2ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_I2S2ADD_IRQHandler
B SPI2_I2S2ADD_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK TIMER5_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER5_DAC_IRQHandler
B TIMER5_DAC_IRQHandler
PUBWEAK TIMER6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER6_IRQHandler
B TIMER6_IRQHandler
PUBWEAK DMA1_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel0_IRQHandler
B DMA1_Channel0_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK ENET_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ENET_IRQHandler
B ENET_IRQHandler
PUBWEAK ENET_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ENET_WKUP_IRQHandler
B ENET_WKUP_IRQHandler
PUBWEAK USBHS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBHS_IRQHandler
B USBHS_IRQHandler
PUBWEAK SHRTIMER_IRQ2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ2_IRQHandler
B SHRTIMER_IRQ2_IRQHandler
PUBWEAK SHRTIMER_IRQ3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ3_IRQHandler
B SHRTIMER_IRQ3_IRQHandler
PUBWEAK SHRTIMER_IRQ4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ4_IRQHandler
B SHRTIMER_IRQ4_IRQHandler
PUBWEAK SHRTIMER_IRQ5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ5_IRQHandler
B SHRTIMER_IRQ5_IRQHandler
PUBWEAK SHRTIMER_IRQ6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ6_IRQHandler
B SHRTIMER_IRQ6_IRQHandler
PUBWEAK USBHS_EP1_OUT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBHS_EP1_OUT_IRQHandler
B USBHS_EP1_OUT_IRQHandler
PUBWEAK USBHS_EP1_IN_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBHS_EP1_IN_IRQHandler
B USBHS_EP1_IN_IRQHandler
PUBWEAK SHRTIMER_IRQ0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ0_IRQHandler
B SHRTIMER_IRQ0_IRQHandler
PUBWEAK SHRTIMER_IRQ1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ1_IRQHandler
B SHRTIMER_IRQ1_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK USART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_IRQHandler
B USART5_IRQHandler
PUBWEAK I2C2_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_WKUP_IRQHandler
B I2C2_WKUP_IRQHandler
PUBWEAK USART5_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_WKUP_IRQHandler
B USART5_WKUP_IRQHandler
PUBWEAK TMU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TMU_IRQHandler
B TMU_IRQHandler
END

567
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32e50x_hd.s Normal file
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;/*!
; \file startup_gd32e50x_hd.s
; \brief start up file
;
; \version 2020-03-10, V1.0.0, firmware for GD32E50x
; \version 2020-08-26, V1.1.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; top of stack
DCD Reset_Handler ; Vector Number 1,Reset Handler
DCD NMI_Handler ; Vector Number 2,NMI Handler
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; Vector Number 11,SVCall Handler
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
; External Interrupts
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD USBD_HP_IRQHandler ; 35:USBD HP
DCD USBD_LP_IRQHandler ; 36:USBD LP
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD ADC2_IRQHandler ; 63:ADC2
DCD EXMC_IRQHandler ; 64:EXMC
DCD SDIO_IRQHandler ; 65:SDIO
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD 0 ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDGT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDGT_IRQHandler
B WWDGT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK RCU_CTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCU_CTC_IRQHandler
B RCU_CTC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI1_IRQHandler
PUBWEAK DMA0_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel0_IRQHandler
B DMA0_Channel0_IRQHandler
PUBWEAK DMA0_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel1_IRQHandler
B DMA0_Channel1_IRQHandler
PUBWEAK DMA0_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel2_IRQHandler
B DMA0_Channel2_IRQHandler
PUBWEAK DMA0_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel3_IRQHandler
B DMA0_Channel3_IRQHandler
PUBWEAK DMA0_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel4_IRQHandler
B DMA0_Channel4_IRQHandler
PUBWEAK DMA0_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel5_IRQHandler
B DMA0_Channel5_IRQHandler
PUBWEAK DMA0_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel6_IRQHandler
B DMA0_Channel6_IRQHandler
PUBWEAK ADC0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC0_1_IRQHandler
B ADC0_1_IRQHandler
PUBWEAK USBD_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_HP_IRQHandler
B USBD_HP_IRQHandler
PUBWEAK USBD_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_LP_IRQHandler
B USBD_LP_IRQHandler
PUBWEAK EXTI5_9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI5_9_IRQHandler
B EXTI5_9_IRQHandler
PUBWEAK TIMER0_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_BRK_IRQHandler
B TIMER0_BRK_IRQHandler
PUBWEAK TIMER0_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_UP_IRQHandler
B TIMER0_UP_IRQHandler
PUBWEAK TIMER0_TRG_CMT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_TRG_CMT_IRQHandler
B TIMER0_TRG_CMT_IRQHandler
PUBWEAK TIMER0_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_Channel_IRQHandler
B TIMER0_Channel_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK I2C0_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_EV_IRQHandler
B I2C0_EV_IRQHandler
PUBWEAK I2C0_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_ER_IRQHandler
B I2C0_ER_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_I2S1ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_I2S1ADD_IRQHandler
B SPI1_I2S1ADD_IRQHandler
PUBWEAK USART0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART0_IRQHandler
B USART0_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI10_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI10_15_IRQHandler
B EXTI10_15_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBD_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_WKUP_IRQHandler
B USBD_WKUP_IRQHandler
PUBWEAK TIMER7_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_BRK_IRQHandler
B TIMER7_BRK_IRQHandler
PUBWEAK TIMER7_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_UP_IRQHandler
B TIMER7_UP_IRQHandler
PUBWEAK TIMER7_TRG_CMT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_TRG_CMT_IRQHandler
B TIMER7_TRG_CMT_IRQHandler
PUBWEAK TIMER7_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_Channel_IRQHandler
B TIMER7_Channel_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK EXMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXMC_IRQHandler
B EXMC_IRQHandler
PUBWEAK TIMER4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER4_IRQHandler
B TIMER4_IRQHandler
PUBWEAK SPI2_I2S2ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_I2S2ADD_IRQHandler
B SPI2_I2S2ADD_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK TIMER5_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER5_DAC_IRQHandler
B TIMER5_DAC_IRQHandler
PUBWEAK TIMER6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER6_IRQHandler
B TIMER6_IRQHandler
PUBWEAK DMA1_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel0_IRQHandler
B DMA1_Channel0_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_4_IRQHandler
B DMA1_Channel3_4_IRQHandler
PUBWEAK SHRTIMER_IRQ2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ2_IRQHandler
B SHRTIMER_IRQ2_IRQHandler
PUBWEAK SHRTIMER_IRQ3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ3_IRQHandler
B SHRTIMER_IRQ3_IRQHandler
PUBWEAK SHRTIMER_IRQ4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ4_IRQHandler
B SHRTIMER_IRQ4_IRQHandler
PUBWEAK SHRTIMER_IRQ5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ5_IRQHandler
B SHRTIMER_IRQ5_IRQHandler
PUBWEAK SHRTIMER_IRQ6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ6_IRQHandler
B SHRTIMER_IRQ6_IRQHandler
PUBWEAK SHRTIMER_IRQ0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ0_IRQHandler
B SHRTIMER_IRQ0_IRQHandler
PUBWEAK SHRTIMER_IRQ1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ1_IRQHandler
B SHRTIMER_IRQ1_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK USART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_IRQHandler
B USART5_IRQHandler
PUBWEAK I2C2_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_WKUP_IRQHandler
B I2C2_WKUP_IRQHandler
PUBWEAK USART5_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_WKUP_IRQHandler
B USART5_WKUP_IRQHandler
END

567
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32e50x_xd.s Normal file
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;/*!
; \file startup_gd32e50x_xd.s
; \brief start up file
;
; \version 2020-03-10, V1.0.0, firmware for GD32E50x
; \version 2020-08-26, V1.1.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; top of stack
DCD Reset_Handler ; Vector Number 1,Reset Handler
DCD NMI_Handler ; Vector Number 2,NMI Handler
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; Vector Number 11,SVCall Handler
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
; External Interrupts
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD USBD_HP_IRQHandler ; 35:USBD HP
DCD USBD_LP_IRQHandler ; 36:USBD LP
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD ADC2_IRQHandler ; 63:ADC2
DCD EXMC_IRQHandler ; 64:EXMC
DCD SDIO_IRQHandler ; 65:SDIO
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ2_IRQHandler ; 85:SHRTIMER IRQ2
DCD SHRTIMER_IRQ3_IRQHandler ; 86:SHRTIMER IRQ3
DCD SHRTIMER_IRQ4_IRQHandler ; 87:SHRTIMER IRQ4
DCD SHRTIMER_IRQ5_IRQHandler ; 88:SHRTIMER IRQ5
DCD SHRTIMER_IRQ6_IRQHandler ; 89:SHRTIMER IRQ6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SHRTIMER_IRQ0_IRQHandler ; 92:SHRTIMER IRQ0
DCD SHRTIMER_IRQ1_IRQHandler ; 93:SHRTIMER IRQ1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD 0 ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDGT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDGT_IRQHandler
B WWDGT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK RCU_CTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCU_CTC_IRQHandler
B RCU_CTC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI1_IRQHandler
PUBWEAK DMA0_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel0_IRQHandler
B DMA0_Channel0_IRQHandler
PUBWEAK DMA0_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel1_IRQHandler
B DMA0_Channel1_IRQHandler
PUBWEAK DMA0_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel2_IRQHandler
B DMA0_Channel2_IRQHandler
PUBWEAK DMA0_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel3_IRQHandler
B DMA0_Channel3_IRQHandler
PUBWEAK DMA0_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel4_IRQHandler
B DMA0_Channel4_IRQHandler
PUBWEAK DMA0_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel5_IRQHandler
B DMA0_Channel5_IRQHandler
PUBWEAK DMA0_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel6_IRQHandler
B DMA0_Channel6_IRQHandler
PUBWEAK ADC0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC0_1_IRQHandler
B ADC0_1_IRQHandler
PUBWEAK USBD_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_HP_IRQHandler
B USBD_HP_IRQHandler
PUBWEAK USBD_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_LP_IRQHandler
B USBD_LP_IRQHandler
PUBWEAK EXTI5_9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI5_9_IRQHandler
B EXTI5_9_IRQHandler
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_BRK_TIMER8_IRQHandler
B TIMER0_BRK_TIMER8_IRQHandler
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_UP_TIMER9_IRQHandler
B TIMER0_UP_TIMER9_IRQHandler
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_TRG_CMT_TIMER10_IRQHandler
B TIMER0_TRG_CMT_TIMER10_IRQHandler
PUBWEAK TIMER0_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_Channel_IRQHandler
B TIMER0_Channel_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK I2C0_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_EV_IRQHandler
B I2C0_EV_IRQHandler
PUBWEAK I2C0_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_ER_IRQHandler
B I2C0_ER_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_I2S1ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_I2S1ADD_IRQHandler
B SPI1_I2S1ADD_IRQHandler
PUBWEAK USART0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART0_IRQHandler
B USART0_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI10_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI10_15_IRQHandler
B EXTI10_15_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBD_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_WKUP_IRQHandler
B USBD_WKUP_IRQHandler
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_BRK_TIMER11_IRQHandler
B TIMER7_BRK_TIMER11_IRQHandler
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_UP_TIMER12_IRQHandler
B TIMER7_UP_TIMER12_IRQHandler
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_TRG_CMT_TIMER13_IRQHandler
B TIMER7_TRG_CMT_TIMER13_IRQHandler
PUBWEAK TIMER7_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_Channel_IRQHandler
B TIMER7_Channel_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK EXMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXMC_IRQHandler
B EXMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIMER4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER4_IRQHandler
B TIMER4_IRQHandler
PUBWEAK SPI2_I2S2ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_I2S2ADD_IRQHandler
B SPI2_I2S2ADD_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK TIMER5_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER5_DAC_IRQHandler
B TIMER5_DAC_IRQHandler
PUBWEAK TIMER6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER6_IRQHandler
B TIMER6_IRQHandler
PUBWEAK DMA1_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel0_IRQHandler
B DMA1_Channel0_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_4_IRQHandler
B DMA1_Channel3_4_IRQHandler
PUBWEAK SHRTIMER_IRQ2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ2_IRQHandler
B SHRTIMER_IRQ2_IRQHandler
PUBWEAK SHRTIMER_IRQ3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ3_IRQHandler
B SHRTIMER_IRQ3_IRQHandler
PUBWEAK SHRTIMER_IRQ4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ4_IRQHandler
B SHRTIMER_IRQ4_IRQHandler
PUBWEAK SHRTIMER_IRQ5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ5_IRQHandler
B SHRTIMER_IRQ5_IRQHandler
PUBWEAK SHRTIMER_IRQ6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ6_IRQHandler
B SHRTIMER_IRQ6_IRQHandler
PUBWEAK SHRTIMER_IRQ0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ0_IRQHandler
B SHRTIMER_IRQ0_IRQHandler
PUBWEAK SHRTIMER_IRQ1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SHRTIMER_IRQ1_IRQHandler
B SHRTIMER_IRQ1_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK USART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_IRQHandler
B USART5_IRQHandler
PUBWEAK I2C2_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_WKUP_IRQHandler
B I2C2_WKUP_IRQHandler
PUBWEAK USART5_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_WKUP_IRQHandler
B USART5_WKUP_IRQHandler
END

536
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32eprt.s Normal file
View File

@@ -0,0 +1,536 @@
;/*!
; \file startup_gd32eprt.s
; \brief start up file
;
; \version 2020-08-26, V1.0.0, firmware for GD32E50x
;*/
;
;/*
; Copyright (c) 2020, GigaDevice Semiconductor Inc.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; top of stack
DCD Reset_Handler ; Vector Number 1,Reset Handler
DCD NMI_Handler ; Vector Number 2,NMI Handler
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; Vector Number 11,SVCall Handler
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
; External Interrupts
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect
DCD RTC_IRQHandler ; 19:RTC through EXTI Line
DCD FMC_IRQHandler ; 20:FMC
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
DCD USBD_HP_IRQHandler ; 35:USBD HP
DCD USBD_LP_IRQHandler ; 36:USBD LP
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
DCD TIMER1_IRQHandler ; 44:TIMER1
DCD TIMER2_IRQHandler ; 45:TIMER2
DCD TIMER3_IRQHandler ; 46:TIMER3
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
DCD SPI0_IRQHandler ; 51:SPI0
DCD SPI1_I2S1ADD_IRQHandler ; 52:SPI1 or I2S1ADD
DCD USART0_IRQHandler ; 53:USART0
DCD USART1_IRQHandler ; 54:USART1
DCD USART2_IRQHandler ; 55:USART2
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup
DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break
DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update
DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
DCD ADC2_IRQHandler ; 63:ADC2
DCD EXMC_IRQHandler ; 64:EXMC
DCD 0 ; Reserved
DCD TIMER4_IRQHandler ; 66:TIMER4
DCD SPI2_I2S2ADD_IRQHandler ; 67:SPI2 or I2S2ADD
DCD UART3_IRQHandler ; 68:UART3
DCD UART4_IRQHandler ; 69:UART4
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 or DAC
DCD TIMER6_IRQHandler ; 71:TIMER6
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
DCD 0 ; Reserved
DCD ENET_IRQHandler ; 77:Ethernet
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C2_EV_IRQHandler ; 98:I2C2 Event
DCD I2C2_ER_IRQHandler ; 99:I2C2 Error
DCD USART5_IRQHandler ; 100:USART5
DCD I2C2_WKUP_IRQHandler ; 101:I2C2 Wakeup
DCD USART5_WKUP_IRQHandler ; 102:USART5 Wakeup
DCD 0 ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDGT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDGT_IRQHandler
B WWDGT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK RCU_CTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCU_CTC_IRQHandler
B RCU_CTC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI1_IRQHandler
PUBWEAK DMA0_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel0_IRQHandler
B DMA0_Channel0_IRQHandler
PUBWEAK DMA0_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel1_IRQHandler
B DMA0_Channel1_IRQHandler
PUBWEAK DMA0_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel2_IRQHandler
B DMA0_Channel2_IRQHandler
PUBWEAK DMA0_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel3_IRQHandler
B DMA0_Channel3_IRQHandler
PUBWEAK DMA0_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel4_IRQHandler
B DMA0_Channel4_IRQHandler
PUBWEAK DMA0_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel5_IRQHandler
B DMA0_Channel5_IRQHandler
PUBWEAK DMA0_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA0_Channel6_IRQHandler
B DMA0_Channel6_IRQHandler
PUBWEAK ADC0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC0_1_IRQHandler
B ADC0_1_IRQHandler
PUBWEAK USBD_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_HP_IRQHandler
B USBD_HP_IRQHandler
PUBWEAK USBD_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_LP_IRQHandler
B USBD_LP_IRQHandler
PUBWEAK EXTI5_9_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI5_9_IRQHandler
B EXTI5_9_IRQHandler
PUBWEAK TIMER0_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_BRK_IRQHandler
B TIMER0_BRK_IRQHandler
PUBWEAK TIMER0_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_UP_IRQHandler
B TIMER0_UP_IRQHandler
PUBWEAK TIMER0_TRG_CMT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_TRG_CMT_IRQHandler
B TIMER0_TRG_CMT_IRQHandler
PUBWEAK TIMER0_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_Channel_IRQHandler
B TIMER0_Channel_IRQHandler
PUBWEAK TIMER1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER1_IRQHandler
B TIMER1_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER3_IRQHandler
B TIMER3_IRQHandler
PUBWEAK I2C0_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_EV_IRQHandler
B I2C0_EV_IRQHandler
PUBWEAK I2C0_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_ER_IRQHandler
B I2C0_ER_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_I2S1ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_I2S1ADD_IRQHandler
B SPI1_I2S1ADD_IRQHandler
PUBWEAK USART0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART0_IRQHandler
B USART0_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI10_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI10_15_IRQHandler
B EXTI10_15_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBD_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBD_WKUP_IRQHandler
B USBD_WKUP_IRQHandler
PUBWEAK TIMER7_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_BRK_IRQHandler
B TIMER7_BRK_IRQHandler
PUBWEAK TIMER7_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_UP_IRQHandler
B TIMER7_UP_IRQHandler
PUBWEAK TIMER7_TRG_CMT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_TRG_CMT_IRQHandler
B TIMER7_TRG_CMT_IRQHandler
PUBWEAK TIMER7_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER7_Channel_IRQHandler
B TIMER7_Channel_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK EXMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXMC_IRQHandler
B EXMC_IRQHandler
PUBWEAK TIMER4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER4_IRQHandler
B TIMER4_IRQHandler
PUBWEAK SPI2_I2S2ADD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_I2S2ADD_IRQHandler
B SPI2_I2S2ADD_IRQHandler
PUBWEAK UART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART3_IRQHandler
B UART3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK TIMER5_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER5_DAC_IRQHandler
B TIMER5_DAC_IRQHandler
PUBWEAK TIMER6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER6_IRQHandler
B TIMER6_IRQHandler
PUBWEAK DMA1_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel0_IRQHandler
B DMA1_Channel0_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_4_IRQHandler
B DMA1_Channel3_4_IRQHandler
PUBWEAK ENET_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ENET_IRQHandler
B ENET_IRQHandler
PUBWEAK ENET_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ENET_WKUP_IRQHandler
B ENET_WKUP_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK USART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_IRQHandler
B USART5_IRQHandler
PUBWEAK I2C2_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_WKUP_IRQHandler
B I2C2_WKUP_IRQHandler
PUBWEAK USART5_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART5_WKUP_IRQHandler
B USART5_WKUP_IRQHandler
END

967
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/system_gd32e50x.c Normal file
View File

@@ -0,0 +1,967 @@
/*!
\file system_gd32e50x.c
\brief CMSIS Cortex-M33 Device Peripheral Access Layer Source File for
GD32E50x Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#include "gd32e50x.h"
/* system frequency define */
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
/* select a system clock by uncommenting the following line */
/* use IRC8M */
//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M)
//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000)
//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_168M_PLL_IRC8M (uint32_t)(168000000)
//#define __SYSTEM_CLOCK_180M_PLL_IRC8M (uint32_t)(180000000)
/* use HXTAL(EPRT/HD/XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */
//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
//#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000)
//#define __SYSTEM_CLOCK_168M_PLL_HXTAL (uint32_t)(168000000)
#define __SYSTEM_CLOCK_180M_PLL_HXTAL (uint32_t)(180000000)
#define SEL_IRC8M 0x00
#define SEL_HXTAL 0x01
#define SEL_PLL 0x02
#define RCU_MODIFY {volatile uint32_t i; \
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
for(i=0;i<20000;i++);}
/* set the system clock frequency and declare the system clock configuration function */
#ifdef __SYSTEM_CLOCK_IRC8M
uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M;
static void system_clock_8m_irc8m(void);
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
static void system_clock_72m_irc8m(void);
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M;
static void system_clock_120m_irc8m(void);
#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC8M)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC8M;
static void system_clock_168m_irc8m(void);
#elif defined (__SYSTEM_CLOCK_180M_PLL_IRC8M)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_180M_PLL_IRC8M;
static void system_clock_180m_irc8m(void);
#elif defined (__SYSTEM_CLOCK_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
static void system_clock_hxtal(void);
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
static void system_clock_72m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL;
static void system_clock_120m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_168M_PLL_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_HXTAL;
static void system_clock_168m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_180M_PLL_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_180M_PLL_HXTAL;
static void system_clock_180m_hxtal(void);
#endif /* __SYSTEM_CLOCK_IRC8M */
/* configure the system clock */
static void system_clock_config(void);
/*!
\brief setup the micro-controller system, initialize the system
\param[in] none
\param[out] none
\retval none
*/
void SystemInit (void)
{
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* reset the RCU clock configuration to the default reset state */
/* Set IRC8MEN bit */
RCU_CTL |= RCU_CTL_IRC8MEN;
RCU_MODIFY
/* Reset CFG0 and CFG1 registers */
RCU_CFG0 = 0x00000000U;
RCU_CFG1 = 0x00000000U;
#if (defined(GD32EPRT) || defined(GD32E50X_HD) || defined(GD32E50X_XD))
/* reset HXTALEN, CKMEN and PLLEN bits */
RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
/* disable all interrupts */
RCU_INT = 0x009f0000U;
#elif defined(GD32E50X_CL)
/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
/* disable all interrupts */
RCU_INT = 0x00ff0000U;
#endif /* GD32F50X_EPRT and GD32F50X_HD and GD32F50X_XD */
/* reset HXTALBPS bit */
RCU_CTL &= ~(RCU_CTL_HXTALBPS);
/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
system_clock_config();
#ifdef VECT_TAB_SRAM
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
#else
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
#endif
}
/*!
\brief configure the system clock
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_config(void)
{
#ifdef __SYSTEM_CLOCK_IRC8M
system_clock_8m_irc8m();
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
system_clock_72m_irc8m();
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
system_clock_120m_irc8m();
#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC8M)
system_clock_168m_irc8m();
#elif defined (__SYSTEM_CLOCK_180M_PLL_IRC8M)
system_clock_180m_irc8m();
#elif defined (__SYSTEM_CLOCK_HXTAL)
system_clock_hxtal();
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
system_clock_72m_hxtal();
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
system_clock_120m_hxtal();
#elif defined (__SYSTEM_CLOCK_168M_PLL_HXTAL)
system_clock_168m_hxtal();
#elif defined (__SYSTEM_CLOCK_180M_PLL_HXTAL)
system_clock_180m_hxtal();
#endif /* __SYSTEM_CLOCK_IRC8M */
}
#ifdef __SYSTEM_CLOCK_IRC8M
/*!
\brief configure the system clock to 8M by IRC8M
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_8m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
}
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
while(1){
}
}
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* select IRC8M as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
/* wait until IRC8M is selected as system clock */
while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
}
}
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
/*!
\brief configure the system clock to 72M by PLL which selects IRC8M as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_72m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
}
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(1);
/* LDO output voltage high mode */
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* IRC8M is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL18;
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 120 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
/*!
\brief configure the system clock to 120M by PLL which selects IRC8M as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_120m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(3);
/* LDO output voltage high mode */
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* IRC8M is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL30;
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 120 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC8M)
/*!
\brief configure the system clock to 168M by PLL which selects IRC8M as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_168m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(4);
/* LDO output voltage high mode */
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* IRC8M is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* CK_PLL = (CK_IRC8M/2) * 42 = 168 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL42;
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 120 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_180M_PLL_IRC8M)
/*!
\brief configure the system clock to 180M by PLL which selects IRC8M as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_180m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC8M */
RCU_CTL |= RCU_CTL_IRC8MEN;
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(4);
/* LDO output voltage high mode */
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* IRC8M is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* CK_PLL = (CK_IRC8M/2) * 45 = 180 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL45;
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 120 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_HXTAL)
/*!
\brief configure the system clock to HXTAL
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
}
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* select HXTAL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
/* wait until HXTAL is selected as system clock */
while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
}
}
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
/*!
\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_72m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(1);
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
#if (defined(GD32EPRT) || defined(GD32E50X_HD) || defined(GD32E50X_XD))
/* select HXTAL/2 as clock source */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
/* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL18;
#elif defined(GD32E50X_CL)
/* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18);
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
}
#endif /* GD32F50X_EPRT and GD32F50X_HD and GD32F50X_XD */
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 180 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
/*!
\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_120m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(3);
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
#if (defined(GD32EPRT) || defined(GD32E50X_HD) || defined(GD32E50X_XD))
/* select HXTAL/2 as clock source */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
/* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL30;
#elif defined(GD32E50X_CL)
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
}
#endif /* GD32F50X_EPRT and GD32F50X_HD and GD32F50X_XD */
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 180 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_168M_PLL_HXTAL)
/*!
\brief configure the system clock to 108M by PLL which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_168m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(4);
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
#if (defined(GD32EPRT) || defined(GD32E50X_HD) || defined(GD32E50X_XD))
/* select HXTAL/2 as clock source */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
/* CK_PLL = (CK_HXTAL/2) * 42 = 168 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL42;
#elif defined(GD32E50X_CL)
/* CK_PLL = (CK_PREDIV0) * 42 = 168 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL42);
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
}
#endif /* GD32F50X_EPRT and GD32F50X_HD and GD32F50X_XD */
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 180 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_180M_PLL_HXTAL)
/*!
\brief configure the system clock to 180M by PLL which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_180m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
while(1){
}
}
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT(4);
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
#if (defined(GD32EPRT) || defined(GD32E50X_HD) || defined(GD32E50X_XD))
/* select HXTAL/2 as clock source */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
/* CK_PLL = (CK_HXTAL/2) * 45 = 180 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= RCU_PLL_MUL45;
#elif defined(GD32E50X_CL)
/* CK_PLL = (CK_PREDIV0) * 45 = 180 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL45);
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
}
#endif /* GD32F50X_EPRT and GD32F50X_HD and GD32F50X_XD */
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
}
/* enable the high-drive to extend the clock frequency to 180 MHz */
PMU_CTL0 |= PMU_CTL0_HDEN;
while(0U == (PMU_CS0 & PMU_CS0_HDRF)){
}
/* select the high-drive mode */
PMU_CTL0 |= PMU_CTL0_HDS;
while(0U == (PMU_CS0 & PMU_CS0_HDSRF)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#endif /* __SYSTEM_CLOCK_IRC8M */
/*!
\brief update the SystemCoreClock with current core clock retrieved from CPU registers
\param[in] none
\param[out] none
\retval none
*/
void SystemCoreClockUpdate (void)
{
uint32_t sws = 0U;
uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
/* exponent of AHB clock divider */
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws){
/* IRC8M is selected as CK_SYS */
case SEL_IRC8M:
SystemCoreClock = IRC8M_VALUE;
break;
/* HXTAL is selected as CK_SYS */
case SEL_HXTAL:
SystemCoreClock = HXTAL_VALUE;
break;
/* PLL is selected as CK_SYS */
case SEL_PLL:
/* get the value of PLLMF[3:0] */
pllmf = GET_BITS(RCU_CFG0, 18, 21);
pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
/* high 16 bits */
if(1U == pllmf4){
pllmf += 17U;
}else if(15U == pllmf){
pllmf = 16U;
}else{
pllmf += 2U;
}
/* PLL clock source selection, HXTAL or IRC8M/2 */
pllsel = GET_BITS(RCU_CFG0, 16, 16);
if(0U != pllsel){
prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
}else{
SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
}
break;
/* IRC8M is selected as CK_SYS */
default:
SystemCoreClock = IRC8M_VALUE;
break;
}
/* calculate AHB clock frequency */
idx = GET_BITS(RCU_CFG0, 4, 7);
clk_exp = ahb_exp[idx];
SystemCoreClock >>= clk_exp;
}

869
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/cmsis_armcc.h Normal file
View File

@@ -0,0 +1,869 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.5
* @date 14. December 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

940
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/cmsis_iccarm.h Normal file
View File

@@ -0,0 +1,940 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.8
* @date 04. September 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/cmsis_version.h Normal file
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@@ -0,0 +1,39 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/CMSIS/core_cm33.h Normal file
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532
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_adc.h Normal file
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/*!
\file gd32e50x_adc.h
\brief definitions for the ADC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_ADC_H
#define GD32E50X_ADC_H
#include "gd32e50x.h"
/* ADC definitions */
#define ADC0 ADC_BASE
#define ADC1 (ADC_BASE + 0x00000400U)
#if (defined(GD32E50X_HD) || defined(GD32E50X_XD))
#define ADC2 (ADC_BASE + 0x00001800U)
#endif
/* registers definitions */
#define ADC_STAT(adcx) REG32((adcx) + 0x00000000U) /*!< ADC status register */
#define ADC_CTL0(adcx) REG32((adcx) + 0x00000004U) /*!< ADC control register 0 */
#define ADC_CTL1(adcx) REG32((adcx) + 0x00000008U) /*!< ADC control register 1 */
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0000000CU) /*!< ADC sampling time register 0 */
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x00000010U) /*!< ADC sampling time register 1 */
#define ADC_IOFF0(adcx) REG32((adcx) + 0x00000014U) /*!< ADC inserted channel data offset register 0 */
#define ADC_IOFF1(adcx) REG32((adcx) + 0x00000018U) /*!< ADC inserted channel data offset register 1 */
#define ADC_IOFF2(adcx) REG32((adcx) + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */
#define ADC_IOFF3(adcx) REG32((adcx) + 0x00000020U) /*!< ADC inserted channel data offset register 3 */
#define ADC_WDHT0(adcx) REG32((adcx) + 0x00000024U) /*!< ADC watchdog high threshold register 0 */
#define ADC_WDLT0(adcx) REG32((adcx) + 0x00000028U) /*!< ADC watchdog low threshold register 0 */
#define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence register 0 */
#define ADC_RSQ1(adcx) REG32((adcx) + 0x00000030U) /*!< ADC regular sequence register 1 */
#define ADC_RSQ2(adcx) REG32((adcx) + 0x00000034U) /*!< ADC regular sequence register 2 */
#define ADC_ISQ(adcx) REG32((adcx) + 0x00000038U) /*!< ADC inserted sequence register */
#define ADC_IDATA0(adcx) REG32((adcx) + 0x0000003CU) /*!< ADC inserted data register 0 */
#define ADC_IDATA1(adcx) REG32((adcx) + 0x00000040U) /*!< ADC inserted data register 1 */
#define ADC_IDATA2(adcx) REG32((adcx) + 0x00000044U) /*!< ADC inserted data register 2 */
#define ADC_IDATA3(adcx) REG32((adcx) + 0x00000048U) /*!< ADC inserted data register 3 */
#define ADC_RDATA(adcx) REG32((adcx) + 0x0000004CU) /*!< ADC regular data register */
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x00000080U) /*!< ADC oversampling control register */
#define ADC_WD1SR(adcx) REG32((adcx) + 0x000000A0U) /*!< ADC watchdog 1 channel selection register */
#define ADC_WD2SR(adcx) REG32((adcx) + 0x000000A4U) /*!< ADC watchdog 2 channel selection register */
#define ADC_WDT1(adcx) REG32((adcx) + 0x000000A8U) /*!< ADC watchdog threshold register 1 */
#define ADC_WDT2(adcx) REG32((adcx) + 0x000000ACU) /*!< ADC watchdog threshold register 2 */
#define ADC_DIFCTL(adcx) REG32((adcx) + 0x000000B0U) /*!< ADC differential mode control register */
/* bits definitions */
/* ADC_STAT */
#define ADC_STAT_WDE0 BIT(0) /*!< analog watchdog 0 event flag */
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
#define ADC_STAT_WDE1 BIT(30) /*!< analog watchdog 1 event flag */
#define ADC_STAT_WDE2 BIT(31) /*!< analog watchdog 2 event flag */
/* ADC_CTL0 */
#define ADC_CTL0_WD0CHSEL BITS(0, 4) /*!< analog watchdog 0 channel select bits */
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
#define ADC_CTL0_WDE0IE BIT(6) /*!< analog watchdog 0 interrupt enable */
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
#define ADC_CTL0_WD0SC BIT(9) /*!< when in scan mode, analog watchdog 0 is effective on a single channel */
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
#define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */
#define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */
#define ADC_CTL0_IWD0EN BIT(22) /*!< analog watchdog 0 enable on inserted channels */
#define ADC_CTL0_RWD0EN BIT(23) /*!< analog watchdog 0 enable on regular channels */
#define ADC_CTL0_WDE1IE BIT(30) /*!< analog watchdog 1 interrupt enable */
#define ADC_CTL0_WDE2IE BIT(31) /*!< analog watchdog 2 interrupt enable */
/* ADC_CTL1 */
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
#define ADC_CTL1_CLBNUM BITS(4, 6) /*!< ADC calibration times */
#define ADC_CTL1_DMA BIT(8) /*!< DMA request enable */
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
#define ADC_CTL1_ETSIC (BIT(30) | BITS(12, 14)) /*!< external trigger select for inserted channel */
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
#define ADC_CTL1_ETSRC (BIT(31) | BITS(17, 19)) /*!< external trigger select for regular channel */
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
#define ADC_CTL1_ETSIC4 BIT(30) /*!< bit 4 of ETSIC */
#define ADC_CTL1_ETSRC4 BIT(31) /*!< bit 4 of ETSRC */
/* ADC_SAMPTx x=0..1 */
#define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n(n=0..17) sample time selection */
/* ADC_IOFFx x=0..3 */
#define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */
/* ADC_WDHT */
#define ADC_WDHT0_WDHT0 BITS(0, 11) /*!< analog watchdog 0 high threshold */
/* ADC_WDLT */
#define ADC_WDLT0_WDLT0 BITS(0, 11) /*!< analog watchdog 0 low threshold */
/* ADC_RSQx x=0..2 */
#define ADC_RSQX_RSQN BITS(0, 4) /*!< n conversion in regular sequence */
#define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */
/* ADC_ISQ */
#define ADC_ISQ_ISQN BITS(0, 4) /*!< n conversion in regular sequence */
#define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */
/* ADC_IDATAx x=0..3 */
#define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted channel x conversion data */
/* ADC_RDATA */
#define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */
#define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */
/* ADC_OVSAMPCTL */
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
#define ADC_OVSAMPCTL_OVSR BITS(2, 4) /*!< oversampling ratio */
#define ADC_OVSAMPCTL_OVSS BITS(5, 8) /*!< oversampling shift */
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
#define ADC_OVSAMPCTL_DRES BITS(12, 13) /*!< ADC resolution */
/* ADC_WD1SR */
#define ADC_WD1SR_AWD1CS BITS(0, 17) /*!< analog watchdog 1 channel selection */
/* ADC_WD2SR */
#define ADC_WD2SR_AWD2CS BITS(0, 17) /*!< analog watchdog 2 channel selection */
/* ADC_WDT1 */
#define ADC_WDT1_WDLT1 BITS(0, 7) /*!< analog watchdog 1 low threshold */
#define ADC_WDT1_WDHT1 BITS(16, 23) /*!< analog watchdog 1 high threshold */
/* ADC_WDT2 */
#define ADC_WDT2_WDLT2 BITS(0, 7) /*!< analog watchdog 2 low threshold */
#define ADC_WDT2_WDHT2 BITS(16, 23) /*!< analog watchdog 2 high threshold */
/* ADC_DIFCTL */
#define ADC_DIFCTL_DIFCTL BITS(0, 17) /*!< Differential mode for channel 17..0 */
/* constants definitions */
/* ADC flag definitions */
#define ADC_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event flag */
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
#define ADC_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event flag */
#define ADC_FLAG_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event flag */
/* ADC_CTL0 register value */
#define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
/* ADC special function definitions */
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
/* ADC synchronization mode */
#define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
/* ADC calibration times */
#define CTL1_CLBNUM(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4)) /*!< write value to ADC_CTL1_CLBNUM bit field */
#define ADC_CALIBRATION_NUM1 CTL1_CLBNUM(0) /*!< ADC calibration 1 time */
#define ADC_CALIBRATION_NUM2 CTL1_CLBNUM(1) /*!< ADC calibration 2 times */
#define ADC_CALIBRATION_NUM4 CTL1_CLBNUM(2) /*!< ADC calibration 4 times */
#define ADC_CALIBRATION_NUM8 CTL1_CLBNUM(3) /*!< ADC calibration 8 times */
#define ADC_CALIBRATION_NUM16 CTL1_CLBNUM(4) /*!< ADC calibration 16 times */
#define ADC_CALIBRATION_NUM32 CTL1_CLBNUM(5) /*!< ADC calibration 32 times */
/* ADC data alignment */
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
/* ADC external trigger select for regular channel */
#define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */
#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */
#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
#if !defined (GD32EPRT)
#define ADC0_1_EXTTRIG_REGULAR_SHRTIMER_ADCTRG0 (ADC_CTL1_ETSRC4 | CTL1_ETSRC(0)) /*!< SHRTIMER_ADCTRG0 output select */
#define ADC0_1_EXTTRIG_REGULAR_SHRTIMER_ADCTRG2 (ADC_CTL1_ETSRC4 | CTL1_ETSRC(1)) /*!< SHRTIMER_ADCTRG2 output select */
#endif /* defined (GD32E50X_HD) && defined (GD32E50X_XD) && defined (GD32E50X_CL) */
#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */
#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */
#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */
#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */
#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */
#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */
/* ADC external trigger select for inserted channel */
#define CTL1_ETSIC(regval) (BITS(12, 14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */
#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */
#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
#if !defined (GD32EPRT)
#define ADC0_1_EXTTRIG_INSERTED_SHRTIMER_ADCTRG1 (ADC_CTL1_ETSIC4 | CTL1_ETSIC(0)) /*!< SHRTIMER_ADCTRG1 output select */
#define ADC0_1_EXTTRIG_INSERTED_SHRTIMER_ADCTRG3 (ADC_CTL1_ETSIC4 | CTL1_ETSIC(1)) /*!< SHRTIMER_ADCTRG3 output select */
#endif /* defined (GD32E50X_HD) && defined (GD32E50X_XD) && defined (GD32E50X_CL) */
#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */
#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */
#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */
#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */
#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */
/* ADC_SAMPTX register value */
#define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
/* ADC data offset for inserted channel x */
#define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0))
/* ADC analog watchdog 0 high threshold */
#define WDHT0_WDHT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0))
/* ADC analog watchdog 0 low threshold */
#define WDLT0_WDLT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0))
/* ADC analog watchdog 1 high threshold */
#define WDT1_WDHT1(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16))
/* ADC analog watchdog 1 low threshold */
#define WDT1_WDLT1(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0))
/* ADC analog watchdog 2 high threshold */
#define WDT2_WDHT2(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16))
/* ADC analog watchdog 2 low threshold */
#define WDT2_WDLT2(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0))
/* ADC regular channel group length */
#define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20))
/* ADC inserted channel group length */
#define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20))
/* adc_ovsampctl register value */
/* ADC resolution */
#define OVSAMPCTL_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */
#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */
#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */
#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */
#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */
/* oversampling shift */
#define OVSAMPCTL_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
/* oversampling ratio */
#define OVSAMPCTL_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
/* triggered oversampling */
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
/* ADC channel group definitions */
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
/* ADC inserted channel definitions */
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */
/* ADC channel definitions */
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
/* analog watchdog 1/2 channel selection for channel n(n=0..17) */
#define ADC_AWD1_2_SELECTION_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 analog watchdog 1/2 selection */
#define ADC_AWD1_2_SELECTION_CHANNEL_ALL ((uint32_t)0x0003FFFFU) /*!< all ADC channels analog watchdog 1/2 selection */
/* Differential mode for channel n(n=0..17) */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 differential mode */
#define ADC_DIFFERENTIAL_MODE_CHANNEL_ALL ((uint32_t)0x00007FFFU) /*!< all ADC channelx(x=0..14) differential mode */
/* ADC interrupt */
#define ADC_INT_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt */
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
#define ADC_INT_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt */
#define ADC_INT_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event interrupt */
/* ADC interrupt flag */
#define ADC_INT_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt flag */
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
#define ADC_INT_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt flag */
#define ADC_INT_FLAG_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event interrupt flag */
/* function declarations */
/* ADC deinitialization and initialization functions */
/* reset ADC */
void adc_deinit(uint32_t adc_periph);
/* enable ADC interface */
void adc_enable(uint32_t adc_periph);
/* disable ADC interface */
void adc_disable(uint32_t adc_periph);
/* ADC calibration and DMA functions */
/* ADC calibration and reset calibration */
void adc_calibration_enable(uint32_t adc_periph);
/* configure ADC calibration number */
void adc_calibration_number(uint32_t adc_periph, uint32_t clb_num);
/* enable DMA request */
void adc_dma_mode_enable(uint32_t adc_periph);
/* disable DMA request */
void adc_dma_mode_disable(uint32_t adc_periph);
/* configure ADC temperature sensor and vrefint channel */
/* enable the temperature sensor and vrefint channel */
void adc_tempsensor_vrefint_enable(void);
/* disable the temperature sensor and vrefint channel */
void adc_tempsensor_vrefint_disable(void);
/* ADC special function functions */
/* configure ADC discontinuous mode */
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length);
/* configure the ADC0 mode */
void adc_mode_config(uint32_t mode);
/* configure ADC special function */
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue);
/* ADC channel configuration functions */
/* configure ADC data alignment */
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment);
/* configure the length of regular channel group or inserted channel group */
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length);
/* configure ADC regular channel */
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
/* configure ADC inserted channel */
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
/* configure ADC inserted channel offset */
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
/* configure differential mode for channel */
void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue);
/* ADC external trigger functions */
/* configure ADC external trigger */
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
/* configure ADC external trigger source */
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
/* enable ADC software trigger */
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group);
/* ADC data read functions */
/* read ADC regular group data register */
uint16_t adc_regular_data_read(uint32_t adc_periph);
/* read ADC inserted group data register */
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
/* read the last ADC0 and ADC1 conversion result data in sync mode */
uint32_t adc_sync_mode_convert_value_read(void);
/* ADC analog watchdog functions */
/* configure ADC analog watchdog 0 single channel */
void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
/* configure ADC analog watchdog 0 group channel */
void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
/* disable ADC analog watchdog 0 */
void adc_watchdog0_disable(uint32_t adc_periph);
/* configure ADC analog watchdog 1 channel */
void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue);
/* configure ADC analog watchdog 2 channel */
void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue);
/* disable ADC analog watchdog 1 */
void adc_watchdog1_disable(uint32_t adc_periph);
/* disable ADC analog watchdog 2 */
void adc_watchdog2_disable(uint32_t adc_periph);
/* configure ADC analog watchdog 0 threshold */
void adc_watchdog0_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
/* configure ADC analog watchdog 1 threshold */
void adc_watchdog1_threshold_config(uint32_t adc_periph , uint8_t low_threshold , uint8_t high_threshold);
/* configure ADC analog watchdog 2 threshold */
void adc_watchdog2_threshold_config(uint32_t adc_periph , uint8_t low_threshold , uint8_t high_threshold);
/* ADC resolution and oversample functions */
/* configure ADC resolution */
void adc_resolution_config(uint32_t adc_periph , uint32_t resolution);
/* configure ADC oversample mode */
void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio);
/* enable ADC oversample mode */
void adc_oversample_mode_enable(uint32_t adc_periph);
/* disable ADC oversample mode */
void adc_oversample_mode_disable(uint32_t adc_periph);
/* flag and interrupt functions */
/* get the ADC flag */
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t flag);
/* clear the ADC flag */
void adc_flag_clear(uint32_t adc_periph , uint32_t flag);
/* enable ADC interrupt */
void adc_interrupt_enable(uint32_t adc_periph , uint32_t interrupt);
/* disable ADC interrupt */
void adc_interrupt_disable(uint32_t adc_periph , uint32_t interrupt);
/* get the ADC interrupt */
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t int_flag);
/* clear the ADC flag */
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t int_flag);
#endif /* GD32E50X_ADC_H */

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/*!
\file gd32e50x_bkp.h
\brief definitions for the BKP
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_BKP_H
#define GD32E50X_BKP_H
#include "gd32e50x.h"
/* BKP definitions */
#define BKP BKP_BASE /*!< BKP base address */
/* registers definitions */
#define BKP_DATA0 REG16((BKP) + 0x0004U) /*!< BKP data register 0 */
#define BKP_DATA1 REG16((BKP) + 0x0008U) /*!< BKP data register 1 */
#define BKP_DATA2 REG16((BKP) + 0x000CU) /*!< BKP data register 2 */
#define BKP_DATA3 REG16((BKP) + 0x0010U) /*!< BKP data register 3 */
#define BKP_DATA4 REG16((BKP) + 0x0014U) /*!< BKP data register 4 */
#define BKP_DATA5 REG16((BKP) + 0x0018U) /*!< BKP data register 5 */
#define BKP_DATA6 REG16((BKP) + 0x001CU) /*!< BKP data register 6 */
#define BKP_DATA7 REG16((BKP) + 0x0020U) /*!< BKP data register 7 */
#define BKP_DATA8 REG16((BKP) + 0x0024U) /*!< BKP data register 8 */
#define BKP_DATA9 REG16((BKP) + 0x0028U) /*!< BKP data register 9 */
#define BKP_DATA10 REG16((BKP) + 0x0040U) /*!< BKP data register 10 */
#define BKP_DATA11 REG16((BKP) + 0x0044U) /*!< BKP data register 11 */
#define BKP_DATA12 REG16((BKP) + 0x0048U) /*!< BKP data register 12 */
#define BKP_DATA13 REG16((BKP) + 0x004CU) /*!< BKP data register 13 */
#define BKP_DATA14 REG16((BKP) + 0x0050U) /*!< BKP data register 14 */
#define BKP_DATA15 REG16((BKP) + 0x0054U) /*!< BKP data register 15 */
#define BKP_DATA16 REG16((BKP) + 0x0058U) /*!< BKP data register 16 */
#define BKP_DATA17 REG16((BKP) + 0x005CU) /*!< BKP data register 17 */
#define BKP_DATA18 REG16((BKP) + 0x0060U) /*!< BKP data register 18 */
#define BKP_DATA19 REG16((BKP) + 0x0064U) /*!< BKP data register 19 */
#define BKP_DATA20 REG16((BKP) + 0x0068U) /*!< BKP data register 20 */
#define BKP_DATA21 REG16((BKP) + 0x006CU) /*!< BKP data register 21 */
#define BKP_DATA22 REG16((BKP) + 0x0070U) /*!< BKP data register 22 */
#define BKP_DATA23 REG16((BKP) + 0x0074U) /*!< BKP data register 23 */
#define BKP_DATA24 REG16((BKP) + 0x0078U) /*!< BKP data register 24 */
#define BKP_DATA25 REG16((BKP) + 0x007CU) /*!< BKP data register 25 */
#define BKP_DATA26 REG16((BKP) + 0x0080U) /*!< BKP data register 26 */
#define BKP_DATA27 REG16((BKP) + 0x0084U) /*!< BKP data register 27 */
#define BKP_DATA28 REG16((BKP) + 0x0088U) /*!< BKP data register 28 */
#define BKP_DATA29 REG16((BKP) + 0x008CU) /*!< BKP data register 29 */
#define BKP_DATA30 REG16((BKP) + 0x0090U) /*!< BKP data register 30 */
#define BKP_DATA31 REG16((BKP) + 0x0094U) /*!< BKP data register 31 */
#define BKP_DATA32 REG16((BKP) + 0x0098U) /*!< BKP data register 32 */
#define BKP_DATA33 REG16((BKP) + 0x009CU) /*!< BKP data register 33 */
#define BKP_DATA34 REG16((BKP) + 0x00A0U) /*!< BKP data register 34 */
#define BKP_DATA35 REG16((BKP) + 0x00A4U) /*!< BKP data register 35 */
#define BKP_DATA36 REG16((BKP) + 0x00A8U) /*!< BKP data register 36 */
#define BKP_DATA37 REG16((BKP) + 0x00ACU) /*!< BKP data register 37 */
#define BKP_DATA38 REG16((BKP) + 0x00B0U) /*!< BKP data register 38 */
#define BKP_DATA39 REG16((BKP) + 0x00B4U) /*!< BKP data register 39 */
#define BKP_DATA40 REG16((BKP) + 0x00B8U) /*!< BKP data register 40 */
#define BKP_DATA41 REG16((BKP) + 0x00BCU) /*!< BKP data register 41 */
#define BKP_OCTL REG16((BKP) + 0x002CU) /*!< RTC signal output control register */
#define BKP_TPCTL REG16((BKP) + 0x0030U) /*!< tamper pin control register */
#define BKP_TPCS REG16((BKP) + 0x0034U) /*!< tamper control and status register */
/* bits definitions */
/* BKP_DATA */
#define BKP_DATA BITS(0,15) /*!< backup data */
/* BKP_OCTL */
#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */
#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */
#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */
/* BKP_TPCTL */
#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */
#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */
/* BKP_TPCS */
#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */
#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */
#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */
#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */
#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */
/* constants definitions */
/* BKP register */
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U)
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
/* get data of BKP data register */
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
/* RTC clock calibration value */
#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
/* RTC output selection */
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */
#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */
/* RTC clock output selection */
#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */
#define RTC_CLOCK_DIV_1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */
/* RTC clock calibration direction */
#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */
#define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */
/* tamper pin active level */
#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */
#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */
/* tamper flag */
#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */
/* tamper interrupt flag */
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
/* BKP data register number */
typedef enum
{
BKP_DATA_0 = 1, /*!< BKP data register 0 */
BKP_DATA_1, /*!< BKP data register 1 */
BKP_DATA_2, /*!< BKP data register 2 */
BKP_DATA_3, /*!< BKP data register 3 */
BKP_DATA_4, /*!< BKP data register 4 */
BKP_DATA_5, /*!< BKP data register 5 */
BKP_DATA_6, /*!< BKP data register 6 */
BKP_DATA_7, /*!< BKP data register 7 */
BKP_DATA_8, /*!< BKP data register 8 */
BKP_DATA_9, /*!< BKP data register 9 */
BKP_DATA_10, /*!< BKP data register 10 */
BKP_DATA_11, /*!< BKP data register 11 */
BKP_DATA_12, /*!< BKP data register 12 */
BKP_DATA_13, /*!< BKP data register 13 */
BKP_DATA_14, /*!< BKP data register 14 */
BKP_DATA_15, /*!< BKP data register 15 */
BKP_DATA_16, /*!< BKP data register 16 */
BKP_DATA_17, /*!< BKP data register 17 */
BKP_DATA_18, /*!< BKP data register 18 */
BKP_DATA_19, /*!< BKP data register 19 */
BKP_DATA_20, /*!< BKP data register 20 */
BKP_DATA_21, /*!< BKP data register 21 */
BKP_DATA_22, /*!< BKP data register 22 */
BKP_DATA_23, /*!< BKP data register 23 */
BKP_DATA_24, /*!< BKP data register 24 */
BKP_DATA_25, /*!< BKP data register 25 */
BKP_DATA_26, /*!< BKP data register 26 */
BKP_DATA_27, /*!< BKP data register 27 */
BKP_DATA_28, /*!< BKP data register 28 */
BKP_DATA_29, /*!< BKP data register 29 */
BKP_DATA_30, /*!< BKP data register 30 */
BKP_DATA_31, /*!< BKP data register 31 */
BKP_DATA_32, /*!< BKP data register 32 */
BKP_DATA_33, /*!< BKP data register 33 */
BKP_DATA_34, /*!< BKP data register 34 */
BKP_DATA_35, /*!< BKP data register 35 */
BKP_DATA_36, /*!< BKP data register 36 */
BKP_DATA_37, /*!< BKP data register 37 */
BKP_DATA_38, /*!< BKP data register 38 */
BKP_DATA_39, /*!< BKP data register 39 */
BKP_DATA_40, /*!< BKP data register 40 */
BKP_DATA_41, /*!< BKP data register 41 */
}bkp_data_register_enum;
/* function declarations */
/* reset BKP registers */
void bkp_deinit(void);
/* write BKP data register */
void bkp_write_data(bkp_data_register_enum register_number, uint16_t data);
/* read BKP data register */
uint16_t bkp_read_data(bkp_data_register_enum register_number);
/* RTC related functions */
/* enable RTC clock calibration output */
void bkp_rtc_calibration_output_enable(void);
/* disable RTC clock calibration output */
void bkp_rtc_calibration_output_disable(void);
/* enable RTC alarm or second signal output */
void bkp_rtc_signal_output_enable(void);
/* disable RTC alarm or second signal output */
void bkp_rtc_signal_output_disable(void);
/* select RTC output */
void bkp_rtc_output_select(uint16_t outputsel);
/* select RTC clock output */
void bkp_rtc_clock_output_select(uint16_t clocksel);
/* RTC clock calibration direction */
void bkp_rtc_clock_calibration_direction(uint16_t direction);
/* set RTC clock calibration value */
void bkp_rtc_calibration_value_set(uint8_t value);
/* tamper pin related functions */
/* enable tamper pin detection */
void bkp_tamper_detection_enable(void);
/* disable tamper pin detection */
void bkp_tamper_detection_disable(void);
/* set tamper pin active level */
void bkp_tamper_active_level_set(uint16_t level);
/* enable tamper pin interrupt */
void bkp_tamper_interrupt_enable(void);
/* disable tamper pin interrupt */
void bkp_tamper_interrupt_disable(void);
/* flag functions */
/* get BKP flag state */
FlagStatus bkp_flag_get(uint16_t flag);
/* clear BKP flag state */
void bkp_flag_clear(uint16_t flag);
/* get BKP interrupt flag state */
FlagStatus bkp_interrupt_flag_get(uint16_t flag);
/* clear BKP interrupt flag state */
void bkp_interrupt_flag_clear(uint16_t flag);
#endif /* GD32E50X_BKP_H */

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/*!
\file gd32e50x_cmp.h
\brief definitions for the CMP
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_CMP_H
#define GD32E50X_CMP_H
#include "gd32e50x.h"
/* CMP definitions */
#define CMP CMP_BASE /*!< CMP base address */
/* registers definitions */
#define CMP_CS(CMPx) REG32((CMP) + 0x00000020U + (CMPx) * 0x00000008U)
/* CMPx_CS bits definitions */
#define CMP_CS_CMPEN BIT(0) /*!< CMPx enable */
#define CMP_CS_CMPMSEL BITS(4,6) /*!< CMPx_IM input selection */
#define CMP_CS_CMPOSEL BITS(10,13) /*!< CMPx output selection */
#define CMP_CS_CMPPL BIT(15) /*!< polarity of CMPx output */
#define CMP_CS_CMPBLK BITS(18,20) /*!< CMPx output blanking source */
#define CMP_CS_CMPMSEL_3 BIT(22) /*!< bit3 of CMPx_CS_CMP1MSEL */
#define CMP_CS_CMPO BIT(30) /*!< CMPx output */
#define CMP_CS_CMPLK BIT(31) /*!< CMPx lock */
/* CMP1_CS bits definitions */
#define CMP1_CS_CMP1EN BIT(0) /*!< CMP1 enable */
#define CMP1_CS_CMP1MSEL BITS(4,6) /*!< CMP1_IM input selection */
#define CMP1_CS_CMP1OSEL BITS(10,13) /*!< CMP1 output selection */
#define CMP1_CS_CMP1PL BIT(15) /*!< polarity of CMP1 output */
#define CMP1_CS_CMP1BLK BITS(18,20) /*!< CMP1 output blanking source */
#define CMP1_CS_CMP1MSEL_3 BIT(22) /*!< bit3 of CMP1_CS_CMP1MSEL */
#define CMP1_CS_CMP1O BIT(30) /*!< CMP1 output */
#define CMP1_CS_CMP1LK BIT(31) /*!< CMP1 lock */
/* CMP3_CS bits definitions */
#define CMP3_CS_CMP3EN BIT(0) /*!< CMP3 enable */
#define CMP3_CS_CMP3MSEL BITS(4,6) /*!< CMP3_IM input selection */
#define CMP3_CS_CMP3OSEL BITS(10,13) /*!< CMP3 output selection */
#define CMP3_CS_CMP3PL BIT(15) /*!< polarity of CMP3 output */
#define CMP3_CS_CMP3BLK BITS(18,20) /*!< CMP3 output blanking source */
#define CMP3_CS_CMP3MSEL_3 BIT(22) /*!< bit3 of CMP3_CS_CMP3MSEL */
#define CMP3_CS_CMP3O BIT(30) /*!< CMP3 output */
#define CMP3_CS_CMP3LK BIT(31) /*!< CMP3 lock */
/* CMP5_CS bits definitions */
#define CMP5_CS_CMP5EN BIT(0) /*!< CMP5 enable */
#define CMP5_CS_CMP5MSEL BITS(4,6) /*!< CMP5_IM input selection */
#define CMP5_CS_CMP5OSEL BITS(10,13) /*!< CMP5 output selection */
#define CMP5_CS_CMP5PL BIT(15) /*!< polarity of CMP5 output */
#define CMP5_CS_CMP5BLK BITS(18,20) /*!< CMP5 output blanking source */
#define CMP5_CS_CMP5MSEL_3 BIT(22) /*!< bit3 of CMP5_CS_CMP5MSEL */
#define CMP5_CS_CMP5O BIT(30) /*!< CMP5 output */
#define CMP5_CS_CMP5LK BIT(31) /*!< CMP5 lock */
/* consts definitions */
/* CMP units */
typedef enum
{
CMP1, /*!< Cmoparator 1 */
CMP3, /*!< Cmoparator 3 */
CMP5 /*!< Cmoparator 5 */
}cmp_enum;
/* inverting input */
typedef enum
{
CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */
CMP_1_2VREFINT, /*!< VREFINT /2 input */
CMP_3_4VREFINT, /*!< VREFINT *3/4 input */
CMP_VREFINT, /*!< VREFINT input */
CMP_PA4, /*!< PA4 input */
CMP_PA5, /*!< PA5 input */
CMP_PA2, /*!< PA2 input */
CMP_PB_2_15 /*!< PB2 or PB15 input */
}inverting_input_enum;
/* output */
typedef enum
{
CMP_OUTPUT_NONE = 0x0U, /*!< output no selection */
CMP_OUTPUT_TIMER0_BKIN = 0x1U, /*!< TIMER 0 break input */
CMP_OUTPUT_TIMER2IC2_TIMER1IC1= 0x6U, /*!< TIMER 2 channel2 or TIMER 1 channel1 input */
CMP_OUTPUT_TIMER0IC0 = 0x7U, /*!< TIMER 0 channel0 input */
CMP_OUTPUT_TIMER1IC3 = 0x08U, /*!< TIMER 1 channel3 input */
CMP_OUTPUT_TIMER2IC0 = 0xAU, /*!< TIMER 2 channel0 input*/
}cmp_output_enum;
typedef enum
{
CMP_OUTPUTBLANK_NONE = 0x0U, /*!< output no blanking */
CMP_OUTPUTBLANK_TIMER2_IC3 = 0x1U, /*!< select TIMER2_CH3 as blanking source */
CMP_OUTPUTBLANK_TIMER1IC2 = 0x2U, /*!< select TIMER1_CH2 as blanking source */
CMP_OUTPUTBLANK_TIMER2IC2_TIMER1IC3 = 0x3U, /*!< select TIMER2_CH2 or TIMER1_CH3 as blanking source */
}cmp_outputblank_enum;
/* comparator inverting input */
#define CS_CMPMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
#define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
#define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
#define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
#define CS_CMPMSEL_VREFINT CS_CMPMSEL(3) /*!< CMP inverting input Vrefint */
#define CS_CMPMSEL_PA4 CS_CMPMSEL(4) /*!< CMP inverting input PA4 */
#define CS_CMPMSEL_PA5 CS_CMPMSEL(5) /*!< CMP inverting input PA5 */
#define CS_CMPMSEL_PA2 CS_CMPMSEL(6) /*!< CMP inverting input PA2 */
#define CS_CMPMSEL_PB_2_15 CS_CMPMSEL(7) /*!< CMP inverting input PB2 or PB15 */
/* CMP output */
#define CS_CMPOSEL(regval) (BITS(10,13) & ((uint32_t)(regval) << 10))
#define CS_CMPOSEL_OUTPUT_NONE CS_CMPOSEL(0) /*!< CMP output none */
#define CS_CMPOSEL_OUTPUT_TIMER0_BKIN CS_CMPOSEL(1) /*!< CMP output TIMER 0 break input */
#define CS_CMPOSEL_OUTPUT_TIMER2IC2_TIMER1IC1 CS_CMPOSEL(6) /*!< TIMER 2 channel 2 or TIMER 1 channel 1 input capture */
#define CS_CMPOSEL_OUTPUT_TIMER0IC0 CS_CMPOSEL(7) /*!< CMP output TIMER 0 channle 1 input capture */
#define CS_CMPOSEL_OUTPUT_TIMER1IC3 CS_CMPOSEL(8) /*!< CMP output TIMER 1 channle 3 input capture */
#define CS_CMPOSEL_OUTPUT_TIMER2IC0 CS_CMPOSEL(10) /*!< CMP output TIMER 2 channle 0 input capture */
/* output polarity of comparator */
#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */
#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */
/* CMP output blanking source */
#define CS_CMPMBLK(regval) (BITS(18,20) & ((uint32_t)(regval) << 18))
#define CS_CMPMBLK_OUTPUTBLANK_NONE CS_CMPMBLK(0) /*!< output no blanking */
#define CS_CMPMBLK_OUTPUTBLANK_TIMER2_IC3 CS_CMPMBLK(1) /*!< select TIMER2_CH3 as blanking source */
#define CS_CMPMBLK_OUTPUTBLANK_TIMER1IC2 CS_CMPMBLK(2) /*!< select TIMER1_CH2 as blanking source */
#define CS_CMPMBLK_OUTPUTBLANK_TIMER2IC2_TIMER1IC3 CS_CMPMBLK(3) /*!< select TIMER2_CH2 or TIMER1_CH3 as blanking source */
/* CMP output level */
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */
/* function declarations */
/* initialization functions */
/* CMP deinit */
void cmp_deinit(void);
/* CMP input init */
void cmp_input_init(cmp_enum cmp_periph,inverting_input_enum inverting_input);
/* CMP output init */
void cmp_output_init(cmp_enum cmp_periph,cmp_output_enum output_slection, uint32_t output_polarity);
/* CMP output blank init */
void cmp_outputblank_init(cmp_enum cmp_periph,cmp_outputblank_enum output_blank);
/* enable CMP */
void cmp_enable(cmp_enum cmp_periph);
/* disable CMP */
void cmp_disable(cmp_enum cmp_periph);
/* lock the CMP */
void cmp_lock_enable(cmp_enum cmp_periph);
/* get output level */
uint32_t cmp_output_level_get(cmp_enum cmp_periph);
#endif /* GD32E50X_CMP_H */

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/*!
\file gd32e50x_crc.h
\brief definitions for the CRC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_CRC_H
#define GD32E50X_CRC_H
#include "gd32e50x.h"
/* CRC definitions */
#define CRC CRC_BASE /*!< CRC base address */
/* registers definitions */
#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0, 31) /*!< CRC data */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset */
#define CRC_CTL_PS BITS(3, 4) /*!< size of polynomial */
#define CRC_CTL_REV_I BITS(5, 6) /*!< input data reverse */
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse */
/* CRC_IDATA */
#define CRC_IDATA_IDATA BITS(0, 31) /*!< CRC initialization data */
/* CRC_POLY */
#define CRC_POLY_POLY BITS(0, 31) /*!< CRC polynomial value */
/* constants definitions */
/* size of polynomial function */
#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
/* input data reverse function */
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
/* input data format */
#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
/* function declarations */
/* deinitialize CRC calculation unit */
void crc_deinit(void);
/* reset data register to the value of initializaiton data register */
void crc_data_register_reset(void);
/* enable the reverse operation of output data */
void crc_reverse_output_data_enable(void);
/* disable the reverse operation of output data */
void crc_reverse_output_data_disable(void);
/* configure the CRC input data function */
void crc_input_data_reverse_config(uint32_t data_reverse);
/* read the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* write the initializaiton data register */
void crc_init_data_register_write(uint32_t init_data);
/* configure the CRC size of polynomial function */
void crc_polynomial_size_set(uint32_t poly_size);
/* configure the CRC polynomial value function */
void crc_polynomial_set(uint32_t poly);
/* CRC calculate single data */
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
/* CRC calculate a data array */
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
#endif /* GD32E50X_CRC_H */

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/*!
\file gd32e50x_ctc.h
\brief definitions for the CTC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_CTC_H
#define GD32E50X_CTC_H
#include "gd32e50x.h"
/* CTC definitions */
#define CTC CTC_BASE
/* registers definitions */
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
/* bits definitions */
/* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
/* CTC_CTL1 */
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
/* CTC_STAT */
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
/* CTC_INTC */
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
/* constants definitions */
/* hardware automatically trim mode definitions */
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
/* reference signal source polarity definitions */
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
/* reference signal source selection definitions */
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
#define CTC_REFSOURCE_USB_SOF CTL1_REFSEL(2) /*!< USBD_SOF or USBHS_SOF is selected */
/* reference signal source prescaler definitions */
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
/* CTC interrupt enable definitions */
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
/* CTC interrupt source definitions */
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
/* CTC flag definitions */
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
/* function declarations */
/* reset ctc clock trim controller */
void ctc_deinit(void);
/* enable CTC trim counter */
void ctc_counter_enable(void);
/* disable CTC trim counter */
void ctc_counter_disable(void);
/* configure the IRC48M trim value */
void ctc_irc48m_trim_value_config(uint8_t trim_value);
/* generate software reference source sync pulse */
void ctc_software_refsource_pulse_generate(void);
/* configure hardware automatically trim mode */
void ctc_hardware_trim_mode_config(uint32_t hardmode);
/* configure reference signal source polarity */
void ctc_refsource_polarity_config(uint32_t polarity);
/* select reference signal source */
void ctc_refsource_signal_select(uint32_t refs);
/* configure reference signal source prescaler */
void ctc_refsource_prescaler_config(uint32_t prescaler);
/* configure clock trim base limit value */
void ctc_clock_limit_value_config(uint8_t limit_value);
/* configure CTC counter reload value */
void ctc_counter_reload_value_config(uint16_t reload_value);
/* read CTC counter capture value when reference sync pulse occurred */
uint16_t ctc_counter_capture_value_read(void);
/* read CTC trim counter direction when reference sync pulse occurred */
FlagStatus ctc_counter_direction_read(void);
/* read CTC counter reload value */
uint16_t ctc_counter_reload_value_read(void);
/* read the IRC48M trim value */
uint8_t ctc_irc48m_trim_value_read(void);
/* interrupt & flag functions */
/* get CTC flag */
FlagStatus ctc_flag_get(uint32_t flag);
/* clear CTC flag */
void ctc_flag_clear(uint32_t flag);
/* enable the CTC interrupt */
void ctc_interrupt_enable(uint32_t interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t int_flag);
#endif /* GD32E50X_CTC_H */

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/*!
\file gd32e50x_dac.h
\brief definitions for the DAC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_DAC_H
#define GD32E50X_DAC_H
#include "gd32e50x.h"
/* DAC definitions */
#define DAC DAC_BASE
/* registers definitions */
#define DAC_CTL0 REG32(DAC + 0x00000000U) /*!< DAC control register 0 */
#define DAC_SWT REG32(DAC + 0x00000004U) /*!< DAC software trigger register */
#define OUT0_R12DH REG32(DAC + 0x00000008U) /*!< DAC_OUT0 12-bit right-aligned data holding register */
#define OUT0_L12DH REG32(DAC + 0x0000000CU) /*!< DAC_OUT0 12-bit left-aligned data holding register */
#define OUT0_R8DH REG32(DAC + 0x00000010U) /*!< DAC_OUT0 8-bit right-aligned data holding register */
#define OUT1_R12DH REG32(DAC + 0x00000014U) /*!< DAC_OUT1 12-bit right-aligned data holding register */
#define OUT1_L12DH REG32(DAC + 0x00000018U) /*!< DAC_OUT1 12-bit left-aligned data holding register */
#define OUT1_R8DH REG32(DAC + 0x0000001CU) /*!< DAC_OUT1 8-bit right-aligned data holding register */
#define DACC_R12DH REG32(DAC + 0x00000020U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
#define DACC_L12DH REG32(DAC + 0x00000024U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
#define DACC_R8DH REG32(DAC + 0x00000028U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
#define OUT0_DO REG32(DAC + 0x0000002CU) /*!< DAC_OUT0 data output register */
#define OUT1_DO REG32(DAC + 0x00000030U) /*!< DAC_OUT1 data output register */
#define DAC_STAT0 REG32(DAC + 0x00000034U) /*!< DAC status register 0 */
#define DAC_CTL1 REG32(DAC + 0x00000080U) /*!< DAC control register 1 */
#define DAC_STAT1 REG32(DAC + 0x00000084U) /*!< DAC status register 1 */
/* bits definitions */
/* DAC_CTL0 */
#define DAC_CTL0_DEN0 BIT(0) /*!< DAC_OUT0 enable/disable bit */
#define DAC_CTL0_DBOFF0 BIT(1) /*!< DAC_OUT0 output buffer turn on/turn off bit */
#define DAC_CTL0_DTEN0 BIT(2) /*!< DAC_OUT0 trigger enable/disable bit */
#define DAC_CTL0_DTSEL0 BITS(3, 5) /*!< DAC_OUT0 trigger source selection enable/disable bits */
#define DAC_CTL0_DWM0 BITS(6, 7) /*!< DAC_OUT0 noise wave mode */
#define DAC_CTL0_DWBW0 BITS(8, 11) /*!< DAC_OUT0 noise wave bit width */
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DAC_OUT0 DMA enable/disable bit */
#define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DAC_OUT0 DMA underrun interrupt enable/disable bit */
#define DAC_CTL0_DTSEL0_3 BIT(14) /*!< DAC_OUT0 trigger selection bit[3], refer to DTSEL1[2:0] */
#define DAC_CTL0_DEN1 BIT(16) /*!< DAC_OUT1 enable/disable bit */
#define DAC_CTL0_DBOFF1 BIT(17) /*!< DAC_OUT1 output buffer turn on/turn off bit */
#define DAC_CTL0_DTEN1 BIT(18) /*!< DAC_OUT1 trigger enable/disable bit */
#define DAC_CTL0_DTSEL1 BITS(19, 21) /*!< DAC_OUT1 trigger source selection enable/disable bits */
#define DAC_CTL0_DWM1 BITS(22, 23) /*!< DAC_OUT1 noise wave mode */
#define DAC_CTL0_DWBW1 BITS(24, 27) /*!< DAC_OUT1 noise wave bit width */
#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DAC_OUT1 DMA enable/disable bit */
#define DAC_CTL0_DDUDRIE1 BIT(29) /*!< DAC_OUT1 DMA underrun interrupt enable/disable bit */
#define DAC_CTL0_DTSEL1_3 BIT(30) /*!< DAC_OUT1 trigger selection bit[3], refer to DTSEL1[2:0] */
/* DAC_SWT */
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC_OUT0 software trigger bit, cleared by hardware */
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC_OUT1 software trigger bit, cleared by hardware */
/* OUT0_R12DH */
#define OUT0_R12DH_OUT0_DH BITS(0, 11) /*!< DAC_OUT0 12-bit right-aligned data bits */
/* OUT0_L12DH */
#define OUT0_L12DH_OUT0_DH BITS(4, 15) /*!< DAC_OUT0 12-bit left-aligned data bits */
/* OUT0_R8DH */
#define OUT0_R8DH_OUT0_DH BITS(0, 7) /*!< DAC_OUT0 8-bit right-aligned data bits */
/* OUT1_R12DH */
#define OUT1_R12DH_OUT1_DH BITS(0, 11) /*!< DAC_OUT1 12-bit right-aligned data bits */
/* OUT1_L12DH */
#define OUT1_L12DH_OUT1_DH BITS(4, 15) /*!< DAC_OUT1 12-bit left-aligned data bits */
/* OUT1_R8DH */
#define OUT1_R8DH_OUT1_DH BITS(0, 7) /*!< DAC_OUT1 8-bit right-aligned data bits */
/* DACC_R12DH */
#define DACC_R12DH_OUT0_DH BITS(0, 11) /*!< DAC concurrent mode DAC_OUT0 12-bit right-aligned data bits */
#define DACC_R12DH_OUT1_DH BITS(16, 27) /*!< DAC concurrent mode DAC_OUT1 12-bit right-aligned data bits */
/* DACC_L12DH */
#define DACC_L12DH_OUT0_DH BITS(4, 15) /*!< DAC concurrent mode DAC_OUT0 12-bit left-aligned data bits */
#define DACC_L12DH_OUT1_DH BITS(20, 31) /*!< DAC concurrent mode DAC_OUT1 12-bit left-aligned data bits */
/* DACC_R8DH */
#define DACC_R8DH_OUT0_DH BITS(0, 7) /*!< DAC concurrent mode DAC_OUT0 8-bit right-aligned data bits */
#define DACC_R8DH_OUT1_DH BITS(8, 15) /*!< DAC concurrent mode DAC_OUT1 8-bit right-aligned data bits */
/* OUT0_DO */
#define OUT0_DO_OUT0_DO BITS(0, 11) /*!< DAC_OUT0 12-bit output data bits */
/* OUT1_DO */
#define OUT1_DO_OUT1_DO BITS(0, 11) /*!< DAC_OUT1 12-bit output data bits */
/* DAC_STAT0 */
#define DAC_STAT0_DDUDR0 BIT(13) /*!< DAC_OUT0 DMA underrun flag */
#define DAC_STAT0_DDUDR1 BIT(29) /*!< DAC_OUT1 DMA underrun flag */
/* DAC_CTL1 */
#define DAC_CTL1_FIFOEN0 BIT(0) /*!< DAC_OUT0 data FIFO enable */
#define DAC_CTL1_FIFOOVRIE0 BIT(1) /*!< DAC_OUT0 FIFO overflow interrupt enable */
#define DAC_CTL1_FIFOUDRIE0 BIT(2) /*!< DAC_OUT0 FIFO underflow interrupt enable */
#define DAC_CTL1_FIFOEN1 BIT(16) /*!< DAC_OUT1 data FIFO enable */
#define DAC_CTL1_FIFOOVRIE1 BIT(17) /*!< DAC_OUT1 FIFO overflow interrupt enable */
#define DAC_CTL1_FIFOUDRIE1 BIT(18) /*!< DAC_OUT1 FIFO underflow interrupt enable */
/* DAC_STAT1 */
#define DAC_STAT1_FF0 BIT(0) /*!< DAC_OUT0 FIFO full flag */
#define DAC_STAT1_FE0 BIT(1) /*!< DAC_OUT0 FIFO empty flag */
#define DAC_STAT1_FIFOOVR0 BIT(2) /*!< DAC_OUT0 FIFO overflow flag */
#define DAC_STAT1_FIFOUDR0 BIT(3) /*!< DAC_OUT0 FIFO underflow flag */
#define DAC_STAT1_FIFONUM0 BITS(4, 6) /*!< number of data in the DAC_OUT0 FIFO */
#define DAC_STAT1_FF1 BIT(16) /*!< DAC_OUT0 FIFO full flag */
#define DAC_STAT1_FE1 BIT(17) /*!< DAC_OUT0 FIFO empty flag */
#define DAC_STAT1_FIFOOVR1 BIT(18) /*!< DAC_OUT0 FIFO overflow flag */
#define DAC_STAT1_FIFOUDR1 BIT(19) /*!< DAC_OUT0 FIFO underflow flag */
#define DAC_STAT1_FIFONUM1 BITS(20, 22) /*!< number of data in the DAC_OUT0 FIFO */
/* constants definitions */
/* DAC trigger source */
#define CTL0_DTSEL(regval) (BITS(3, 5) & ((uint32_t)(regval) << 3))
#define DAC_TRIGGER_T5_TRGO CTL0_DTSEL(0) /*!< TIMER5 TRGO */
#if (defined(GD32E50X_HD) || defined(GD32E50X_XD))
#define DAC_TRIGGER_T7_TRGO CTL0_DTSEL(1) /*!< TIMER7 TRGO(for GD32E50X_HD and GD32E50X_XD devices, except for 48 pin chips) */
#elif defined(GD32E50X_CL)
#define DAC_TRIGGER_T2_TRGO CTL0_DTSEL(1) /*!< TIMER2 TRGO(for GD32E50X_CL devices ) */
#endif /* GD32E50X_HD and GD32E50X_XD */
#define DAC_TRIGGER_T6_TRGO CTL0_DTSEL(2) /*!< TIMER6 TRGO */
#define DAC_TRIGGER_T4_TRGO CTL0_DTSEL(3) /*!< TIMER4 TRGO */
#define DAC_TRIGGER_T1_TRGO CTL0_DTSEL(4) /*!< TIMER1 TRGO */
#define DAC_TRIGGER_T3_TRGO CTL0_DTSEL(5) /*!< TIMER3 TRGO */
#define DAC_TRIGGER_EXTI_9 CTL0_DTSEL(6) /*!< EXTI interrupt line9 event */
#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(7) /*!< software trigger */
#if !defined (GD32EPRT)
#define DAC_TRIGGER_SHRTIMER_DACTRIG0 (DAC_CTL0_DTSEL0_3 | CTL0_DTSEL(0)) /*!< SHRTIMER_DACTRIG0 trigger */
#define DAC_TRIGGER_SHRTIMER_DACTRIG1 (DAC_CTL0_DTSEL0_3 | CTL0_DTSEL(1)) /*!< SHRTIMER_DACTRIG1 trigger */
#define DAC_TRIGGER_SHRTIMER_DACTRIG2 (DAC_CTL0_DTSEL0_3 | CTL0_DTSEL(2)) /*!< SHRTIMER_DACTRIG2 trigger */
#endif /* defined (GD32E50X_HD) && defined (GD32E50X_XD) && defined (GD32E50X_CL) */
/* DAC noise wave mode */
#define CTL0_DWM(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6))
#define DAC_WAVE_DISABLE CTL0_DWM(0) /*!< wave disable */
#define DAC_WAVE_MODE_LFSR CTL0_DWM(1) /*!< LFSR noise mode */
#define DAC_WAVE_MODE_TRIANGLE CTL0_DWM(2) /*!< triangle noise mode */
/* DAC noise wave bit width */
#define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8))
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
/* unmask LFSR bits in DAC LFSR noise mode */
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
/* DAC data alignment */
#define DATA_ALIGN(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0))
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */
/* triangle amplitude in DAC triangle noise mode */
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
/* DAC output channel definitions */
#define DAC_OUT_0 ((uint8_t)0x00U) /*!< DAC_OUT0 */
#define DAC_OUT_1 ((uint8_t)0x01U) /*!< DAC_OUT1 */
/* DAC interrupt */
#define DAC_INT_DDUDRIE0 DAC_CTL0_DDUDRIE0 /*!< DAC_OUT0 DMA underrun interrupt enable */
#define DAC_INT_FIFOOVRIE0 DAC_CTL1_FIFOOVRIE0 /*!< DAC_OUT0 FIFO overflow interrupt enable */
#define DAC_INT_FIFOUDRIE0 DAC_CTL1_FIFOUDRIE0 /*!< DAC_OUT0 FIFO underflow interrupt enable */
#define DAC_INT_DDUDRIE1 DAC_CTL0_DDUDRIE1 /*!< DAC_OUT1 DMA underrun interrupt enable */
#define DAC_INT_FIFOOVRIE1 DAC_CTL1_FIFOOVRIE1 /*!< DAC_OUT1 FIFO overflow interrupt enable */
#define DAC_INT_FIFOUDRIE1 DAC_CTL1_FIFOUDRIE1 /*!< DAC_OUT1 FIFO underflow interrupt enable */
/* DAC interrupt flag */
#define DAC_INT_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DAC_OUT0 DMA underrun interrupt flag */
#define DAC_INT_FLAG_FIFOOVR0 DAC_STAT1_FIFOOVR0 /*!< DAC_OUT0 FIFO overflow interrupt flag */
#define DAC_INT_FLAG_FIFOUDR0 DAC_STAT1_FIFOUDR0 /*!< DAC_OUT0 FIFO underflow interrupt flag */
#define DAC_INT_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DAC_OUT1 DMA underrun interrupt flag */
#define DAC_INT_FLAG_FIFOOVR1 DAC_STAT1_FIFOOVR1 /*!< DAC_OUT1 FIFO overflow interrupt flag */
#define DAC_INT_FLAG_FIFOUDR1 DAC_STAT1_FIFOUDR1 /*!< DAC_OUT1 FIFO underflow interrupt flag */
/* DAC flag */
#define DAC_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DAC_OUT0 DMA underrun flag */
#define DAC_FLAG_FF0 DAC_STAT1_FF0 /*!< DAC_OUT0 FIFO full flag */
#define DAC_FLAG_FE0 DAC_STAT1_FE0 /*!< DAC_OUT0 FIFO empty flag */
#define DAC_FLAG_FIFOOVR0 DAC_STAT1_FIFOOVR0 /*!< DAC_OUT0 FIFO overflow flag */
#define DAC_FLAG_FIFOUDR0 DAC_STAT1_FIFOUDR0 /*!< DAC_OUT0 FIFO underflow flag */
#define DAC_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DAC_OUT1 DMA underrun flag */
#define DAC_FLAG_FF1 DAC_STAT1_FF1 /*!< DAC_OUT1 FIFO full flag */
#define DAC_FLAG_FE1 DAC_STAT1_FE1 /*!< DAC_OUT1 FIFO empty flag */
#define DAC_FLAG_FIFOOVR1 DAC_STAT1_FIFOOVR1 /*!< DAC_OUT1 FIFO overflow flag */
#define DAC_FLAG_FIFOUDR1 DAC_STAT1_FIFOUDR1 /*!< DAC_OUT1 FIFO underflow flag */
/* function declarations */
/* initialization functions */
/* deinitialize DAC */
void dac_deinit(void);
/* enable DAC */
void dac_enable(uint8_t dac_out);
/* disable DAC */
void dac_disable(uint8_t dac_out);
/* enable DAC DMA */
void dac_dma_enable(uint8_t dac_out);
/* disable DAC DMA */
void dac_dma_disable(uint8_t dac_out);
/* enable DAC output buffer */
void dac_output_buffer_enable(uint8_t dac_out);
/* disable DAC output buffer */
void dac_output_buffer_disable(uint8_t dac_out);
/* get DAC output value */
uint16_t dac_output_value_get(uint8_t dac_out);
/* set DAC data holding register value */
void dac_data_set(uint8_t dac_out, uint32_t dac_align, uint16_t data);
/* enable DAC output FIFO */
void dac_output_fifo_enable(uint8_t dac_out);
/* disable DAC output FIFO */
void dac_output_fifo_disable(uint8_t dac_out);
/* get DAC output FIFO number */
uint16_t dac_output_fifo_number_get(uint8_t dac_out);
/* DAC trigger configuration */
/* enable DAC trigger */
void dac_trigger_enable(uint8_t dac_out);
/* disable DAC trigger */
void dac_trigger_disable(uint8_t dac_out);
/* configure DAC trigger source */
void dac_trigger_source_config(uint8_t dac_out, uint32_t triggersource);
/* enable DAC software trigger */
void dac_software_trigger_enable(uint8_t dac_out);
/* disable DAC software trigger */
void dac_software_trigger_disable(uint8_t dac_out);
/* DAC wave mode configuration */
/* configure DAC wave mode */
void dac_wave_mode_config(uint8_t dac_out, uint32_t wave_mode);
/* configure DAC wave bit width */
void dac_wave_bit_width_config(uint8_t dac_out, uint32_t bit_width);
/* configure DAC LFSR noise mode */
void dac_lfsr_noise_config(uint8_t dac_out, uint32_t unmask_bits);
/* configure DAC triangle noise mode */
void dac_triangle_noise_config(uint8_t dac_out, uint32_t amplitude);
/* DAC concurrent mode configuration */
/* enable DAC concurrent mode */
void dac_concurrent_enable(void);
/* disable DAC concurrent mode */
void dac_concurrent_disable(void);
/* enable DAC concurrent software trigger */
void dac_concurrent_software_trigger_enable(void);
/* disable DAC concurrent software trigger */
void dac_concurrent_software_trigger_disable(void);
/* enable DAC concurrent buffer function */
void dac_concurrent_output_buffer_enable(void);
/* disable DAC concurrent buffer function */
void dac_concurrent_output_buffer_disable(void);
/* set DAC concurrent mode data holding register value */
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
/* interrupt and flag functions */
/* get DAC flag */
FlagStatus dac_flag_get(uint8_t dac_out, uint32_t flag);
/* clear DAC flag */
void dac_flag_clear(uint8_t dac_out, uint32_t flag);
/* enable DAC interrupt */
void dac_interrupt_enable(uint8_t dac_out, uint32_t interrupt);
/* disable DAC interrupt */
void dac_interrupt_disable(uint8_t dac_out, uint32_t interrupt);
/* get DAC interrupt flag */
FlagStatus dac_interrupt_flag_get(uint8_t dac_out, uint32_t int_flag);
/* clear DAC interrupt flag */
void dac_interrupt_flag_clear(uint8_t dac_out, uint32_t int_flag);
#endif /* GD32E50X_DAC_H */

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/*!
\file gd32e50x_dbg.h
\brief definitions for the DBG
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_DBG_H
#define GD32E50X_DBG_H
#include "gd32e50x.h"
/* DBG definitions */
#define DBG DBG_BASE /*!< DBG base address */
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */
#define DBG_CTL REG32(DBG + 0x00000004U) /*!< DBG control register */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code */
/* DBG_CTL */
#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< hold FWDGT counter when core is halted */
#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< hold WWDGT counter when core is halted */
#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus timeout when core is halted */
#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus timeout when core is halted */
#define DBG_CTL_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */
#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
#define DBG_CTL_I2C2_HOLD BIT(22) /*!< hold I2C2 smbus timeout when core is halted */
#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */
#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */
#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */
#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */
#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */
#if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32E50X_CL))
#define DBG_CTL_SHRTIMER_HOLD BIT(31) /*!< hold SHRTIMER counter when core is halted */
#endif /* GD32E50X_HD and GD32E50X_XD and GD32E50X_CL */
/* constants definitions */
#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */
/* define the peripheral debug hold bit position and its register index offset */
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
/* register index */
#define DBG_IDX_CTL ((uint32_t)0x00000004U)
typedef enum
{
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 8U), /*!< hold FWDGT counter when core is halted */
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 9U), /*!< hold WWDGT counter when core is halted */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 10U), /*!< hold TIMER0 counter when core is halted */
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 11U), /*!< hold TIMER1 counter when core is halted */
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 12U), /*!< hold TIMER2 counter when core is halted */
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 13U), /*!< hold TIMER3 counter when core is halted */
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 15U), /*!< hold I2C0 smbus timeout when core is halted */
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 16U), /*!< hold I2C1 smbus timeout when core is halted */
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 17U), /*!< hold TIMER7 counter when core is halted */
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 18U), /*!< hold TIMER4 counter when core is halted */
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 19U), /*!< hold TIMER5 counter when core is halted */
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 20U), /*!< hold TIMER6 counter when core is halted */
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 22U), /*!< hold I2C2 smbus timeout when core is halted */
DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 25U), /*!< hold TIMER11 counter when core is halted */
DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 26U), /*!< hold TIMER12 counter when core is halted */
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 27U), /*!< hold TIMER13 counter when core is halted */
DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 28U), /*!< hold TIMER8 counter when core is halted */
DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 29U), /*!< hold TIMER9 counter when core is halted */
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 30U), /*!< hold TIMER10 counter when core is halted */
#if (defined(GD32E50X_HD) || defined(GD32E50X_XD) || defined(GD32E50X_CL))
DBG_SHRTIMER_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL, 31U), /*!< hold SHRTIMER counter when core is halted */
#endif /* GD32E50X_HD and GD32E50X_XD and GD32E50X_CL */
}dbg_periph_enum;
#define CTL_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6))
#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
/* function declarations */
/* deinitialize the DBG */
void dbg_deinit(void);
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/* enable low power behavior when the MCU is in debug mode */
void dbg_low_power_enable(uint32_t dbg_low_power);
/* disable low power behavior when the MCU is in debug mode */
void dbg_low_power_disable(uint32_t dbg_low_power);
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
/* enable trace pin assignment */
void dbg_trace_pin_enable(void);
/* disable trace pin assignment */
void dbg_trace_pin_disable(void);
/* set trace pin mode */
void dbg_trace_pin_mode_set(uint32_t trace_mode);
#endif /* GD32E50X_DBG_H */

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/*!
\file gd32e50x_dma.h
\brief definitions for the DMA
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_DMA_H
#define GD32E50X_DMA_H
#include "gd32e50x.h"
/* DMA definitions */
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */
/* registers definitions */
#define DMA_INTF(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register */
#define DMA_INTC(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag clear register */
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000008U) /*!< DMA channel 0 control register */
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA channel 0 counter register */
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 peripheral base address register */
#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 memory base address register */
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 1 control register */
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 1 counter register */
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 1 peripheral base address register */
#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 memory base address register */
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 2 control register */
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 2 counter register */
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 2 peripheral base address register */
#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 2 memory base address register */
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 3 control register */
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 3 counter register */
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */
#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 3 memory base address register */
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 4 control register */
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 4 counter register */
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 4 peripheral base address register */
#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 4 memory base address register */
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 5 control register */
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 5 counter register */
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 5 peripheral base address register */
#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 5 memory base address register */
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 6 control register */
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 6 counter register */
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 6 peripheral base address register */
#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 6 memory base address register */
/* bits definitions */
/* DMA_INTF */
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
/* DMA_INTC */
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
/* DMA_CHxCTL, x=0..6 */
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
/* DMA_CHxCNT,x=0..6 */
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
/* DMA_CHxPADDR,x=0..6 */
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
/* DMA_CHxMADDR,x=0..6 */
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
/* constants definitions */
/* DMA channel select */
typedef enum
{
DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */
DMA_CH3, /*!< DMA Channel3 */
DMA_CH4, /*!< DMA Channel4 */
DMA_CH5, /*!< DMA Channel5 */
DMA_CH6 /*!< DMA Channel6 */
} dma_channel_enum;
/* DMA initialize struct */
typedef struct
{
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */
uint32_t memory_width; /*!< transfer data size of memory */
uint32_t number; /*!< channel transfer number */
uint32_t priority; /*!< channel priority level */
uint8_t periph_inc; /*!< peripheral increasing mode */
uint8_t memory_inc; /*!< memory increasing mode */
uint8_t direction; /*!< channel data transfer direction */
} dma_parameter_struct;
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
/* DMA_register address */
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x00000008U) + 0x00000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0000000CU) + 0x00000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x00000010U) + 0x00000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x00000014U) + 0x00000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
/* DMA reset value */
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
/* DMA_INTF register */
/* interrupt flag bits */
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
/* flag bits */
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
/* DMA_CHxCTL register */
/* interrupt enable bits */
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
/* transfer direction */
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
/* peripheral increasing mode */
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
/* memory increasing mode */
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
/* transfer data size of peripheral */
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */
/* transfer data size of memory */
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */
/* channel priority level */
#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
/* memory to memory mode */
#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U)
#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U)
/* DMA_CHxCNT register */
/* transfer counter */
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
/* function declarations */
/* DMA deinitialization and initialization functions */
/* deinitialize DMA a channel registers */
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
/* initialize the parameters of DMA struct with the default values */
void dma_struct_para_init(dma_parameter_struct* init_struct);
/* initialize DMA channel */
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct);
/* enable DMA circulation mode */
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable DMA circulation mode */
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable memory to memory mode */
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable memory to memory mode */
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable DMA channel */
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable DMA channel */
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* DMA configuration functions */
/* set DMA peripheral base address */
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
/* set DMA memory base address */
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
/* set the number of remaining data to be transferred by the DMA */
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
/* get the number of remaining data to be transferred by the DMA */
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
/* configure priority level of DMA channel */
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
/* configure transfer data size of memory */
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
/* configure transfer data size of peripheral */
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
/* enable next address increasement algorithm of memory */
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable next address increasement algorithm of memory */
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* enable next address increasement algorithm of peripheral */
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
/* disable next address increasement algorithm of peripheral */
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
/* configure the direction of data transfer on the channel */
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
/* flag and interrupt functions */
/* check DMA flag is set or not */
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* clear a DMA channel flag */
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* enable DMA interrupt */
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
/* disable DMA interrupt */
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
/* check DMA flag and interrupt enable bit is set or not */
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
/* clear a DMA channel flag */
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
#endif /* GD32E50X_DMA_H */

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/*!
\file gd32e50x_exmc.h
\brief definitions for the EXMC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_EXMC_H
#define GD32E50X_EXMC_H
#include "gd32e50x.h"
/* EXMC definitions */
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
/* registers definitions */
/* NOR/PSRAM */
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register0 */
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register0 */
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register0 */
#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register1 */
#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register1 */
#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register1 */
#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register2 */
#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register2 */
#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register2 */
#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register3 */
#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register3 */
#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register3 */
/* NAND/PC card */
#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register1 */
#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register1 */
#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register1 */
#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register1 */
#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register1 */
#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register2 */
#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register2 */
#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register2 */
#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register2 */
#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register2 */
#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register3 */
#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register3 */
#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register3 */
#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register3 */
#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */
/* bits definitions */
/* EXMC_SNCTLx,x=0..3 */
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */
/* EXMC_SNTCFGx,x=0..3 */
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
/* EXMC_SNWTCFGx,x=0..3 */
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */
#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
/* EXMC_NPCTLx,x=1..3 */
#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
/* EXMC_NPINTENx,x=1..3 */
#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
/* EXMC_NPCTCFGx,x=1..3 */
#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
/* EXMC_NPATCFGx,x=1..3 */
#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
/* EXMC_PIOTCFG3 */
#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
/* EXMC_NECCx,x=1,2 */
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
/* constants definitions */
/* EXMC NOR/SRAM timing initialize struct */
typedef struct
{
uint32_t asyn_access_mode; /*!< asynchronous access mode */
uint32_t syn_data_latency; /*!< configure the data latency, synchronous access mode valid */
uint32_t syn_clk_division; /*!< configure the clock divide ratio, synchronous access mode valid */
uint32_t bus_latency; /*!< configure the bus latency */
uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */
uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */
uint32_t asyn_address_setuptime; /*!< configure the data setup time, asynchronous access mode valid */
}exmc_norsram_timing_parameter_struct;
/* EXMC NOR/SRAM initialize struct */
typedef struct
{
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
uint32_t extended_mode; /*!< enable or disable the extended mode */
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
uint32_t memory_write; /*!< enable or disable the write operation */
uint32_t nwait_config; /*!< NWAIT signal configuration, only work in synchronous mode */
uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
uint32_t burst_mode; /*!< enable or disable the burst mode */
uint32_t databus_width; /*!< specifies the databus width of external memory */
uint32_t memory_type; /*!< specifies the type of external memory */
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing
parameters for read if the extended mode is used */
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */
}exmc_norsram_parameter_struct;
/* EXMC NAND/PC card timing initialize struct */
typedef struct
{
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
uint32_t waittime; /*!< configure the minimum wait time */
uint32_t setuptime; /*!< configure the address setup time */
}exmc_nand_pccard_timing_parameter_struct;
/* EXMC NAND initialize struct */
typedef struct
{
uint32_t nand_bank; /*!< select the bank of NAND */
uint32_t ecc_size; /*!< the page size for the ECC calculation */
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
uint32_t databus_width; /*!< the NAND flash databus width */
uint32_t wait_feature; /*!< enable or disable the wait feature */
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
}exmc_nand_parameter_struct;
/* EXMC PC card initialize struct */
typedef struct
{
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
uint32_t wait_feature; /*!< enable or disable the wait feature */
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
}exmc_pccard_parameter_struct;
/* EXMC_register address */
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */
#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */
#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */
#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */
#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC registers, bank = 1,2 */
/* CRAM page size */
#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
/* NOR bank memory data bus width */
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */
/* NOR bank memory type */
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
/* asynchronous access mode */
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
/* data latency for NOR flash */
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */
/* synchronous clock divide ratio */
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
/* ECC size */
#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */
#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */
#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */
#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */
#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */
#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */
/* ALE to RE delay */
#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
/* CLE to RE delay */
#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
/* NAND bank memory data bus width */
#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */
#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */
/* EXMC NOR/SRAM bank region definition */
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
/* EXMC NOR/SRAM write mode */
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */
/* EXMC NWAIT signal configuration */
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */
/* EXMC NWAIT signal polarity configuration */
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */
/* EXMC NAND/PC card bank definition */
#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */
#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */
/* EXMC flag bits */
#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
/* EXMC interrupt flag bits */
#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and corresponding flag */
#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and corresponding flag */
#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and corresponding flag */
/* function declarations */
/* NOR/SRAM */
/* deinitialize EXMC NOR/SRAM region */
void exmc_norsram_deinit(uint32_t exmc_norsram_region);
/* initialize exmc_norsram_parameter_struct with the default values */
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
/* initialize EXMC NOR/SRAM region */
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
/* enable EXMC NOR/SRAM region */
void exmc_norsram_enable(uint32_t exmc_norsram_region);
/* disable EXMC NOR/SRAM region */
void exmc_norsram_disable(uint32_t exmc_norsram_region);
/* configure CRAM page size */
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
/* NAND */
/* deinitialize EXMC NAND bank */
void exmc_nand_deinit(uint32_t exmc_nand_bank);
/* initialize exmc_norsram_parameter_struct with the default values */
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
/* initialize EXMC NAND bank */
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
/* enable EXMC NAND bank */
void exmc_nand_enable(uint32_t exmc_nand_bank);
/* disable EXMC NAND bank */
void exmc_nand_disable(uint32_t exmc_nand_bank);
/* enable or disable the EXMC NAND ECC function */
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue);
/* get the EXMC ECC value */
uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
/* PC card */
/* deinitialize EXMC PC card bank */
void exmc_pccard_deinit(void);
/* initialize exmc_pccard_parameter_struct parameter with the default values */
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
/* initialize EXMC PC card bank */
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
/* enable EXMC PC card bank */
void exmc_pccard_enable(void);
/* disable EXMC PC card bank */
void exmc_pccard_disable(void);
/* interrupt & flag functions */
/* enable EXMC interrupt */
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt);
/* disable EXMC interrupt */
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt);
/* get EXMC flag status */
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag);
/* clear EXMC flag status */
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag);
/* get EXMC interrupt flag */
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt);
/* clear EXMC interrupt flag */
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt);
#endif /* GD32E50X_EXMC_H */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_exti.h Normal file
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/*!
\file gd32e50x_exti.h
\brief definitions for the EXTI
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_EXTI_H
#define GD32E50X_EXTI_H
#include "gd32e50x.h"
/* EXTI definitions */
#define EXTI EXTI_BASE
/* registers definitions */
#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */
#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */
#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */
#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling trigger enable register */
#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */
#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */
/* bits definitions */
/* EXTI_INTEN */
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
/* EXTI_EVEN */
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
/* EXTI_RTEN */
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
/* EXTI_FTEN */
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
/* EXTI_SWIEV */
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
/* EXTI_PD */
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
/* constants definitions */
/* EXTI line number */
typedef enum
{
EXTI_0 = BIT(0), /*!< EXTI line 0 */
EXTI_1 = BIT(1), /*!< EXTI line 1 */
EXTI_2 = BIT(2), /*!< EXTI line 2 */
EXTI_3 = BIT(3), /*!< EXTI line 3 */
EXTI_4 = BIT(4), /*!< EXTI line 4 */
EXTI_5 = BIT(5), /*!< EXTI line 5 */
EXTI_6 = BIT(6), /*!< EXTI line 6 */
EXTI_7 = BIT(7), /*!< EXTI line 7 */
EXTI_8 = BIT(8), /*!< EXTI line 8 */
EXTI_9 = BIT(9), /*!< EXTI line 9 */
EXTI_10 = BIT(10), /*!< EXTI line 10 */
EXTI_11 = BIT(11), /*!< EXTI line 11 */
EXTI_12 = BIT(12), /*!< EXTI line 12 */
EXTI_13 = BIT(13), /*!< EXTI line 13 */
EXTI_14 = BIT(14), /*!< EXTI line 14 */
EXTI_15 = BIT(15), /*!< EXTI line 15 */
EXTI_16 = BIT(16), /*!< EXTI line 16 */
EXTI_17 = BIT(17), /*!< EXTI line 17 */
EXTI_18 = BIT(18), /*!< EXTI line 18 */
EXTI_19 = BIT(19), /*!< EXTI line 19 */
EXTI_20 = BIT(20), /*!< EXTI line 20 */
EXTI_21 = BIT(21), /*!< EXTI line 21 */
}exti_line_enum;
/* external interrupt and event */
typedef enum
{
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
EXTI_EVENT /*!< EXTI event mode */
}exti_mode_enum;
/* interrupt trigger mode */
typedef enum
{
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
}exti_trig_type_enum;
/* function declarations */
/* deinitialize the EXTI */
void exti_deinit(void);
/* initialize the EXTI */
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
/* enable the interrupts from EXTI line x */
void exti_interrupt_enable(exti_line_enum linex);
/* disable the interrupts from EXTI line x */
void exti_interrupt_disable(exti_line_enum linex);
/* enable the events from EXTI line x */
void exti_event_enable(exti_line_enum linex);
/* disable the events from EXTI line x */
void exti_event_disable(exti_line_enum linex);
/* enable the EXTI software interrupt event */
void exti_software_interrupt_enable(exti_line_enum linex);
/* disable the EXTI software interrupt event */
void exti_software_interrupt_disable(exti_line_enum linex);
/* get EXTI line x pending flag */
FlagStatus exti_flag_get(exti_line_enum linex);
/* clear EXTI line x pending flag */
void exti_flag_clear(exti_line_enum linex);
/* get EXTI line x flag when the interrupt flag is set */
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
/* clear EXTI line x pending flag */
void exti_interrupt_flag_clear(exti_line_enum linex);
#endif /* GD32E50X_EXTI_H */

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/*!
\file gd32e50x_fmc.h
\brief definitions for the FMC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_FMC_H
#define GD32E50X_FMC_H
#include "gd32e50x.h"
/* FMC and option bytes definition */
#define FMC FMC_BASE /*!< FMC base address */
#define OB OB_BASE /*!< option bytes base address */
/* registers definitions */
#define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */
#define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key register */
#define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */
#define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */
#define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */
#define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */
#define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC erase/program protection register */
#define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC product ID register */
#define OP_BYTE(x) REG32(OB + ((uint32_t)((uint32_t)0x04U * (x)))) /*!< option bytes value */
#define OB_SPC_USER REG32(OB + 0x00000000U) /*!< option bytes security protection value and user value */
#define OB_DATA REG32(OB + 0x00000004U) /*!< option bytes data value */
#define OB_WP0 REG32(OB + 0x00000008U) /*!< option bytes write protection value 0 */
#define OB_WP1 REG32(OB + 0x0000000CU) /*!< option bytes write protection value 1 */
/* bits definitions */
/* FMC_WS */
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */
#define FMC_WS_ICEN BIT(9) /*!< IBUS cache enable */
#define FMC_WS_DCEN BIT(10) /*!< DBUS cache enable */
#define FMC_WS_ICRST BIT(11) /*!< IBUS cache reset */
#define FMC_WS_DCRST BIT(12) /*!< DBUS cache reset */
/* FMC_KEY */
#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key */
/* FMC_OBKEY */
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key */
/* FMC_STAT */
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag */
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag */
#define FMC_STAT_PGAERR BIT(3) /*!< flash program alignment error flag */
#define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag */
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag */
/* FMC_CTL */
#define FMC_CTL_PG BIT(0) /*!< main flash program command */
#define FMC_CTL_PER BIT(1) /*!< main flash page erase command */
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase command */
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command */
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command */
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC */
#define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock */
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable */
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable */
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable */
/* FMC_ADDR */
#define FMC_ADDR_ADDR BITS(0,31) /*!< address of flash to be erased/programmed */
/* FMC_OBSTAT */
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error */
#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset */
/* FMC_WP */
#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
/* FMC_PID */
#define FMC_PID_PID BITS(0,31) /*!< product ID */
/* constants definitions */
/* fmc state */
typedef enum
{
FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */
FMC_PGAERR, /*!< program alignment error */
FMC_WPERR, /*!< erase/program protection error */
FMC_TOERR, /*!< timeout error */
FMC_OB_HSPC, /*!< high security protection */
}fmc_state_enum;
/* unlock key */
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
/* FMC wait state added */
#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
#define FMC_WAIT_STATE_0 WS_WSCNT(0) /*!< 0 wait state added */
#define FMC_WAIT_STATE_1 WS_WSCNT(1) /*!< 1 wait state added */
#define FMC_WAIT_STATE_2 WS_WSCNT(2) /*!< 2 wait state added */
#define FMC_WAIT_STATE_3 WS_WSCNT(3) /*!< 3 wait state added */
#define FMC_WAIT_STATE_4 WS_WSCNT(4) /*!< 4 wait state added */
/* read protection configuration */
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection */
#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */
/* option bytes software/hardware free watch dog timer */
#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
/* option bytes reset or not entering deep sleep mode */
#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
/* option bytes reset or not entering standby mode */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering standby mode */
/* option bytes write protection */
#define OB_WP_NONE ((uint32_t)0x00000000U) /*!< disable all erase/program protection */
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 ~ 63 */
#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
/* FMC interrupt enable */
#define FMC_INT_ERR FMC_CTL_ERRIE /*!< FMC error interrupt enable */
#define FMC_INT_END FMC_CTL_ENDIE /*!< FMC end of operation interrupt enable */
/* FMC flags */
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC operation error flag */
#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag */
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of operation flag */
/* FMC interrupt flags */
#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC operation error interrupt flag */
#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error interrupt flag */
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */
#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of operation interrupt flag */
/* FMC timeout */
#define FMC_TIMEOUT_COUNT ((uint32_t)0x00100000U) /*!< FMC timeout count value */
/* function declarations */
/* FMC main memory programming functions */
/* unlock the main FMC operation */
void fmc_unlock(void);
/* lock the main FMC operation */
void fmc_lock(void);
/* set the wait state */
void fmc_wscnt_set(uint32_t wscnt);
/* enable pre-fetch */
void fmc_prefetch_enable(void);
/* disable pre-fetch */
void fmc_prefetch_disable(void);
/* enable IBUS cache */
void fmc_ibus_enable(void);
/* disable IBUS cache */
void fmc_ibus_disable(void);
/* reset IBUS cache */
void fmc_ibus_reset(void);
/* enable DBUS cache */
void fmc_dbus_enable(void);
/* disable DBUS cache */
void fmc_dbus_disable(void);
/* reset DBUS cache */
void fmc_dbus_reset(void);
/* FMC erase page */
fmc_state_enum fmc_page_erase(uint32_t page_address);
/* FMC erase whole chip */
fmc_state_enum fmc_mass_erase(void);
/* FMC program a word at the corresponding address */
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
/* FMC option bytes programming functions */
/* unlock the option bytes operation */
void ob_unlock(void);
/* lock the option bytes operation */
void ob_lock(void);
/* erase the option bytes */
fmc_state_enum ob_erase(void);
/* enable write protection */
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
/* configure the option bytes security protection */
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
/* program option bytes USER */
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby);
/* program option bytes DATA */
fmc_state_enum ob_data_program(uint16_t ob_data);
/* get the value of option bytes USER */
uint8_t ob_user_get(void);
/* get the value of option bytes DATA */
uint16_t ob_data_get(void);
/* get the value of option bytes write protection */
uint32_t ob_write_protection_get(void);
/* get option bytes security protection state */
FlagStatus ob_security_protection_flag_get(void);
/* FMC interrupts and flags management functions */
/* get FMC flag status */
FlagStatus fmc_flag_get(uint32_t flag);
/* clear the FMC flag */
void fmc_flag_clear(uint32_t flag);
/* enable FMC interrupt */
void fmc_interrupt_enable(uint32_t interrupt);
/* disable FMC interrupt */
void fmc_interrupt_disable(uint32_t interrupt);
/* get FMC interrupt flag */
FlagStatus fmc_interrupt_flag_get(uint32_t flag);
/* clear FMC interrupt flag */
void fmc_interrupt_flag_clear(uint32_t flag);
#endif /* GD32E50X_FMC_H */

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/*!
\file gd32e50x_fwdgt.h
\brief definitions for the FWDGT
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_FWDGT_H
#define GD32E50X_FWDGT_H
#include "gd32e50x.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
/* constants definitions */
/* psc register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
/* function declarations */
/* enable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_enable(void);
/* disable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_disable(void);
/* start the free watchdog timer counter */
void fwdgt_enable(void);
/* configure the FWDGT counter prescaler value */
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
/* configure the FWDGT counter reload value */
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32E50X_FWDGT_H */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Include/gd32e50x_gpio.h Normal file
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/*!
\file gd32e50x_gpio.h
\brief definitions for the GPIO
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_GPIO_H
#define GD32E50X_GPIO_H
#include "gd32e50x.h"
/* GPIOx(x=A,B,C,D,E,F,G) definitions */
#define GPIOA (GPIO_BASE + 0x00000000U) /*!< GPIOA bsae address */
#define GPIOB (GPIO_BASE + 0x00000400U) /*!< GPIOB bsae address */
#define GPIOC (GPIO_BASE + 0x00000800U) /*!< GPIOC bsae address */
#define GPIOD (GPIO_BASE + 0x00000C00U) /*!< GPIOD bsae address */
#define GPIOE (GPIO_BASE + 0x00001000U) /*!< GPIOE bsae address */
#define GPIOF (GPIO_BASE + 0x00001400U) /*!< GPIOF bsae address */
#define GPIOG (GPIO_BASE + 0x00001800U) /*!< GPIOG bsae address */
/* AFIO definitions */
#define AFIO AFIO_BASE /*!< AFIO bsae address */
/* registers definitions */
/* GPIO registers definitions */
#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register 0 */
#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port control register 1 */
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port input status register */
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port output control register */
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port bit operation register */
#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO bit clear register */
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port configuration lock register */
#define GPIOx_SPD(gpiox) REG32((gpiox) + 0x0000003CU) /*!< GPIO port bit speed register */
/* AFIO registers definitions */
#define AFIO_EC REG32(AFIO + 0x00000000U) /*!< AFIO event control register */
#define AFIO_PCF0 REG32(AFIO + 0x00000004U) /*!< AFIO port configuration register 0 */
#define AFIO_EXTISS0 REG32(AFIO + 0x00000008U) /*!< AFIO port EXTI sources selection register 0 */
#define AFIO_EXTISS1 REG32(AFIO + 0x0000000CU) /*!< AFIO port EXTI sources selection register 1 */
#define AFIO_EXTISS2 REG32(AFIO + 0x00000010U) /*!< AFIO port EXTI sources selection register 2 */
#define AFIO_EXTISS3 REG32(AFIO + 0x00000014U) /*!< AFIO port EXTI sources selection register 3 */
#define AFIO_PCF1 REG32(AFIO + 0x0000001CU) /*!< AFIO port configuration register 1 */
#define AFIO_CPSCTL REG32(AFIO + 0x00000020U) /*!< IO compensation control register */
#define AFIO_PCFA REG32(AFIO + 0x0000003CU) /*!< AFIO port configuration register A */
#define AFIO_PCFB REG32(AFIO + 0x00000040U) /*!< AFIO port configuration register B */
#define AFIO_PCFC REG32(AFIO + 0x00000044U) /*!< AFIO port configuration register C */
#define AFIO_PCFD REG32(AFIO + 0x00000048U) /*!< AFIO port configuration register D */
#define AFIO_PCFE REG32(AFIO + 0x0000004CU) /*!< AFIO port configuration register E */
#define AFIO_PCFG REG32(AFIO + 0x00000054U) /*!< AFIO port configuration register G */
/* bits definitions */
/* GPIO_CTL0 */
#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */
#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */
#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */
#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */
#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */
#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */
#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */
#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */
#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */
#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */
#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */
#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */
#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */
#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */
#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */
#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */
/* GPIO_CTL1 */
#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */
#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */
#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */
#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */
#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */
#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */
#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */
#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */
#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */
#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */
#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */
#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */
#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */
#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */
#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */
#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
/* GPIO_ISTAT */
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
/* GPIO_OCTL */
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
/* GPIO_BOP */
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
/* GPIO_BC */
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
/* GPIO_LOCK */
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
/* GPIO_SPD */
#define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */
#define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */
/* AFIO_EC */
#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */
#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */
#define AFIO_EC_EOE BIT(7) /*!< event output enable */
/* AFIO_PCF0 */
#ifdef GD32E50X_CL
/* memory map and bit definitions for GD32E50X_CL devices */
#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */
#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */
#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */
#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */
#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */
#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */
#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */
#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */
#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */
#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */
#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */
#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */
#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */
#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */
#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */
#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */
#else
/* memory map and bit definitions for GD32E50X_HD devices and GD32E50X_XD devices */
#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */
#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */
#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */
#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */
#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */
#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */
#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */
#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */
#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */
#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */
#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */
#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */
#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */
#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */
#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */
#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */
#endif /* GD32E50X_CL */
/* AFIO_EXTISS0 */
#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */
#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */
#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */
#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */
/* AFIO_EXTISS1 */
#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */
#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */
#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */
#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */
/* AFIO_EXTISS2 */
#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */
#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */
#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */
#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */
/* AFIO_EXTISS3 */
#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */
#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */
#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */
#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */
/* AFIO_PCF1 */
#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */
#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */
#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */
#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */
#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */
#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */
#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */
/* AFIO_CPSCTL */
#define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */
#define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */
/* AFIO_PCFA */
#define AFIO_PCFA_PA2_AFCFG BIT(4) /*!< PA2 AF function configuration bit */
#define AFIO_PCFA_PA3_AFCFG BIT(6) /*!< PA3 AF function configuration bit */
#define AFIO_PCFA_PA5_AFCFG BIT(10) /*!< PA5 AF function configuration bit */
#define AFIO_PCFA_PA8_AFCFG BITS(16, 17) /*!< PA8 AF function configuration bits */
#define AFIO_PCFA_PA9_AFCFG BITS(18, 19) /*!< PA9 AF function configuration bits */
#define AFIO_PCFA_PA10_AFCFG BITS(20, 21) /*!< PA10 AF function configuration bits */
#define AFIO_PCFA_PA11_AFCFG BITS(22, 23) /*!< PA11 AF function configuration bits */
#define AFIO_PCFA_PA12_AFCFG BITS(24, 25) /*!< PA12 AF function configuration bits */
#define AFIO_PCFA_PA15_AFCFG BIT(30) /*!< PA15 AF function configuration bit */
/* AFIO_PCFB */
#define AFIO_PCFB_PB0_AFCFG BIT(0) /*!< PB0 AF function configuration bit */
#define AFIO_PCFB_PB1_AFCFG BITS(2, 3) /*!< PB1 AF function configuration bits */
#define AFIO_PCFB_PB2_AFCFG BITS(4, 5) /*!< PB2 AF function configuration bits */
#define AFIO_PCFB_PB3_AFCFG BIT(6) /*!< PB3 AF function configuration bit */
#define AFIO_PCFB_PB4_AFCFG BITS(8, 9) /*!< PB4 AF function configuration bits */
#define AFIO_PCFB_PB5_AFCFG BITS(10, 11) /*!< PB5 AF function configuration bits */
#define AFIO_PCFB_PB6_AFCFG BIT(12) /*!< PB6 AF function configuration bit */
#define AFIO_PCFB_PB7_AFCFG BIT(14) /*!< PB7 AF function configuration bit */
#define AFIO_PCFB_PB8_AFCFG BITS(16, 17) /*!< PB8 AF function configuration bits */
#define AFIO_PCFB_PB9_AFCFG BITS(18, 19) /*!< PB9 AF function configuration bits */
#define AFIO_PCFB_PB10_AFCFG BITS(20, 21) /*!< PB10 AF function configuration bits */
#define AFIO_PCFB_PB11_AFCFG BITS(22, 23) /*!< PB11 AF function configuration bits */
#define AFIO_PCFB_PB12_AFCFG BITS(24, 25) /*!< PB12 AF function configuration bits */
#define AFIO_PCFB_PB13_AFCFG BITS(26, 27) /*!< PB13 AF function configuration bits */
#define AFIO_PCFB_PB14_AFCFG BITS(28, 29) /*!< PB14 AF function configuration bits */
#define AFIO_PCFB_PB15_AFCFG BIT(30) /*!< PB15 AF function configuration bits */
/* AFIO_PCFC */
#define AFIO_PCFC_PC0_AFCFG BIT(0) /*!< PC0 AF function configuration bit */
#define AFIO_PCFC_PC2_AFCFG BITS(4, 5) /*!< PC2 AF function configuration bits */
#define AFIO_PCFC_PC3_AFCFG BIT(6) /*!< PC3 AF function configuration bit */
#define AFIO_PCFC_PC6_AFCFG BITS(12, 13) /*!< PC6 AF function configuration bits */
#define AFIO_PCFC_PC7_AFCFG BITS(14, 15) /*!< PC7 AF function configuration bits */
#define AFIO_PCFC_PC8_AFCFG BITS(16, 17) /*!< PC8 AF function configuration bits */
#define AFIO_PCFC_PC9_AFCFG BITS(18, 19) /*!< PC9 AF function configuration bits */
#define AFIO_PCFC_PC10_AFCFG BIT(20) /*!< PC10 AF function configuration bit */
#define AFIO_PCFC_PC11_AFCFG BITS(22, 23) /*!< PC11 AF function configuration bits */
#define AFIO_PCFC_PC12_AFCFG BIT(24) /*!< PC12 AF function configuration bit */
/* AFIO_PCFD */
#define AFIO_PCFD_PD4_AFCFG BIT(8) /*!< PD4 AF function configuration bit */
#define AFIO_PCFD_PD5_AFCFG BIT(10) /*!< PD5 AF function configuration bit */
/* AFIO_PCFE */
#define AFIO_PCFE_PE0_AFCFG BITS(0, 1) /*!< PE0 AF function configuration bits */
#define AFIO_PCFE_PE1_AFCFG BITS(2, 3) /*!< PE1 AF function configuration bits */
#define AFIO_PCFE_PE8_AFCFG BIT(16) /*!< PE8 AF function configuration bit */
#define AFIO_PCFE_PE9_AFCFG BIT(18) /*!< PE9 AF function configuration bit */
#define AFIO_PCFE_PE10_AFCFG BIT(20) /*!< PE10 AF function configuration bit */
#define AFIO_PCFE_PE11_AFCFG BIT(22) /*!< PE11 AF function configuration bit */
#define AFIO_PCFE_PE12_AFCFG BIT(24) /*!< PE12 AF function configuration bit */
#define AFIO_PCFE_PE13_AFCFG BIT(26) /*!< PE13 AF function configuration bit */
/* AFIO_PCFG */
#define AFIO_PCFG_PG6_AFCFG BIT(12) /*!< PG6 AF function configuration bit */
#define AFIO_PCFG_PG7_AFCFG BITS(14, 15) /*!< PG7 AF function configuration bits */
#define AFIO_PCFG_PG9_AFCFG BIT(18) /*!< PG9 AF function configuration bit */
#define AFIO_PCFG_PG10_AFCFG BIT(20) /*!< PG10 AF function configuration bit */
#define AFIO_PCFG_PG11_AFCFG BIT(22) /*!< PG11 AF function configuration bit */
#define AFIO_PCFG_PG12_AFCFG BIT(24) /*!< PG12 AF function configuration bit */
#define AFIO_PCFG_PG13_AFCFG BIT(26) /*!< PG13 AF function configuration bit */
#define AFIO_PCFG_PG14_AFCFG BIT(28) /*!< PG14 AF function configuration bit */
/* constants definitions */
typedef FlagStatus bit_status;
/* GPIO mode values set */
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n))))
#define GPIO_MODE_MASK(n) (0xFU << (4U * (n)))
/* GPIO mode definitions */
#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */
#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */
#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */
#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */
#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */
#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */
#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */
#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */
/* GPIO output max speed value */
#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */
#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */
#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */
#define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */
/* GPIO event output port definitions */
#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */
#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */
#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */
#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */
#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */
/* GPIO output port source definitions */
#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */
#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */
#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */
#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */
#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */
#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */
#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */
/* GPIO event output pin definitions */
#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */
#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */
#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */
#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */
#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */
#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */
#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */
#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */
#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */
#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */
#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */
#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */
#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */
#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */
#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */
#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */
/* GPIO output pin source definitions */
#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */
#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */
#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */
#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */
#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */
#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */
#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */
#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */
#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */
#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */
#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */
#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */
#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */
#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */
#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */
#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */
/* GPIO pin definitions */
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
/* AFIO remap mask */
#define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */
#define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */
#define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */
#define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */
#define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */
#define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */
/* GPIO remap definitions */
#define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */
#define GPIO_I2C0_REMAP AFIO_PCF0_I2C0_REMAP /*!< I2C0 remapping */
#define GPIO_USART0_REMAP AFIO_PCF0_USART0_REMAP /*!< USART0 remapping */
#define GPIO_USART1_REMAP AFIO_PCF0_USART1_REMAP /*!< USART1 remapping */
#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(1)) /*!< USART2 partial remapping */
#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(3)) /*!< USART2 full remapping */
#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(1)) /*!< TIMER0 partial remapping */
#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(3)) /*!< TIMER0 full remapping */
#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(1)) /*!< TIMER1 partial remapping */
#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(2)) /*!< TIMER1 partial remapping */
#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(3)) /*!< TIMER1 full remapping */
#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(2)) /*!< TIMER2 partial remapping */
#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(3)) /*!< TIMER2 full remapping */
#define GPIO_TIMER3_REMAP AFIO_PCF0_TIMER3_REMAP /*!< TIMER3 remapping */
#define GPIO_PD01_REMAP AFIO_PCF0_PD01_REMAP /*!< PD01 remapping */
#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER4CH3_IREMAP >> 16)) /*!< TIMER4 channel3 internal remapping */
#if (defined(GD32E50X_HD) || defined(GD32E50X_XD))
#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGINS_REMAP >> 16)) /*!< ADC0 external trigger inserted conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */
#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGREG_REMAP >> 16)) /*!< ADC0 external trigger regular conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */
#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGINS_REMAP >> 16)) /*!< ADC1 external trigger inserted conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */
#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGREG_REMAP >> 16)) /*!< ADC1 external trigger regular conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices) */
#endif /* GD32E50X_HD||GD32E50X_XD */
#ifdef GD32E50X_CL
#define GPIO_ENET_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ENET_REMAP >> 16)) /*!< ENET remapping(only for GD32E50X_CL devices) */
#endif /* GD32E50X_CL */
#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(1) >> 16)) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */
#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(2) >> 16)) /*!< JTAG-DP disabled and SW-DP enabled */
#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(4) >> 16)) /*!< JTAG-DP disabled and SW-DP disabled */
#define GPIO_SPI2_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_SPI2_REMAP >> 16)) /*!< SPI2 remapping*/
#ifdef GD32E50X_CL
#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER1ITR0_REMAP >> 16)) /*!< TIMER1 internal trigger 0 remapping(only for GD32E50X_CL devices) */
#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_PTP_PPS_REMAP >> 16)) /*!< ethernet PTP PPS remapping(only for GD32E50X_CL devices) */
#endif /* GD32E50X_CL */
#define GPIO_TIMER8_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER8_REMAP) /*!< TIMER8 remapping */
#define GPIO_TIMER9_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER9_REMAP) /*!< TIMER9 remapping */
#define GPIO_TIMER10_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER10_REMAP) /*!< TIMER10 remapping */
#define GPIO_TIMER12_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER12_REMAP) /*!< TIMER12 remapping */
#define GPIO_TIMER13_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER13_REMAP) /*!< TIMER13 remapping */
#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_EXMC_NADV) /*!< EXMC_NADV connect/disconnect */
#define GPIO_CTC_REMAP0 ((uint32_t)0x801B0000U | PCF1_CTC_REMAP(1)) /*!< CTC remapping(PD15) */
#define GPIO_CTC_REMAP1 ((uint32_t)0x801B0000U | PCF1_CTC_REMAP(2)) /*!< CTC remapping(PF0) */
/* AFIO_PCFA AFCFG mask */
#define PCFA_PA8_AFCFG(regval) (BITS(16, 17) & ((uint32_t)(regval) << 16)) /*!< PA8 AFCFG */
#define PCFA_PA9_AFCFG(regval) (BITS(18, 19) & ((uint32_t)(regval) << 18)) /*!< PA9 AFCFG */
#define PCFA_PA10_AFCFG(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< PA10 AFCFG */
#define PCFA_PA11_AFCFG(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) /*!< PA11 AFCFG */
#define PCFA_PA12_AFCFG(regval) (BITS(24, 25) & ((uint32_t)(regval) << 24)) /*!< PA12 AFCFG */
/* AFIO_PCFB AFCFG mask */
#define PCFB_PB1_AFCFG(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2)) /*!< PB1 AFCFG */
#define PCFB_PB2_AFCFG(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4)) /*!< PB2 AFCFG */
#define PCFB_PB4_AFCFG(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8)) /*!< PB4 AFCFG */
#define PCFB_PB5_AFCFG(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10)) /*!< PB5 AFCFG */
#define PCFB_PB8_AFCFG(regval) (BITS(16, 17) & ((uint32_t)(regval) << 16)) /*!< PB8 AFCFG */
#define PCFB_PB9_AFCFG(regval) (BITS(18, 19) & ((uint32_t)(regval) << 18)) /*!< PB9 AFCFG */
#define PCFB_PB10_AFCFG(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< PB10 AFCFG */
#define PCFB_PB11_AFCFG(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) /*!< PB11 AFCFG */
#define PCFB_PB12_AFCFG(regval) (BITS(24, 25) & ((uint32_t)(regval) << 24)) /*!< PB12 AFCFG */
#define PCFB_PB13_AFCFG(regval) (BITS(26, 27) & ((uint32_t)(regval) << 26)) /*!< PB13 AFCFG */
#define PCFB_PB14_AFCFG(regval) (BITS(28, 29) & ((uint32_t)(regval) << 28)) /*!< PB14 AFCFG */
/* AFIO_PCFC AFCFG mask */
#define PCFC_PC2_AFCFG(regval) (BITS(4, 5) & ((uint32_t)(regval) << 4)) /*!< PC2 AFCFG */
#define PCFC_PC6_AFCFG(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< PC6 AFCFG */
#define PCFC_PC7_AFCFG(regval) (BITS(14, 15) & ((uint32_t)(regval) << 14)) /*!< PC7 AFCFG */
#define PCFC_PC8_AFCFG(regval) (BITS(16, 17) & ((uint32_t)(regval) << 16)) /*!< PC8 AFCFG */
#define PCFC_PC9_AFCFG(regval) (BITS(18, 19) & ((uint32_t)(regval) << 18)) /*!< PC9 AFCFG */
#define PCFC_PC11_AFCFG(regval) (BITS(22, 23) & ((uint32_t)(regval) << 22)) /*!< PC11 AFCFG */
/* AFIO_PCFE AFCFG mask */
#define PCFE_PE0_AFCFG(regval) (BITS(0, 1) & ((uint32_t)(regval))) /*!< PE0 AFCFG */
#define PCFE_PE1_AFCFG(regval) (BITS(2, 3) & ((uint32_t)(regval) << 2)) /*!< PE1 AFCFG */
/* AFIO_PCFG AFCFG mask */
#define PCFG_PG7_AFCFG(regval) (BITS(14, 15) & ((uint32_t)(regval) << 14)) /*!< PG7 AFCFG */
/* GPIOA AF function definitions */
#define AFIO_PA2_CMP1_CFG AFIO_PCFA_PA2_AFCFG /*!< configure PA2 alternate function to CMP1 */
#define AFIO_PA3_USBHS_CFG AFIO_PCFA_PA3_AFCFG /*!< configure PA3 alternate function to USBHS */
#define AFIO_PA5_USBHS_CFG AFIO_PCFA_PA5_AFCFG /*!< configure PA5 alternate function to USBHS */
#define AFIO_PA8_I2C2_CFG ((uint32_t)0x00300000U | (PCFA_PA8_AFCFG(1) >> 16)) /*!< configure PA8 alternate function to I2C2 */
#define AFIO_PA8_SHRTIMER_CFG ((uint32_t)0x00300000U | (PCFA_PA8_AFCFG(2) >> 16)) /*!< configure PA8 alternate function to SHRTIMER */
#define AFIO_PA9_I2C2_CFG ((uint32_t)0x00320000U | (PCFA_PA9_AFCFG(2) >> 16)) /*!< configure PA9 alternate function to I2C2 */
#define AFIO_PA9_SHRTIMER_CFG ((uint32_t)0x00320000U | (PCFA_PA9_AFCFG(3) >> 16)) /*!< configure PA9 alternate function to SHRTIMER */
#define AFIO_PA10_CMP5_CFG ((uint32_t)0x00340000U | (PCFA_PA10_AFCFG(2) >> 16)) /*!< configure PA10 alternate function to CMP5 */
#define AFIO_PA10_SHRTIMER_CFG ((uint32_t)0x00340000U | (PCFA_PA10_AFCFG(3) >> 16)) /*!< configure PA10 alternate function to SHRTIMER */
#define AFIO_PA11_USART5_CFG ((uint32_t)0x00360000U | (PCFA_PA11_AFCFG(1) >> 16)) /*!< configure PA11 alternate function to USART5 */
#define AFIO_PA11_SHRTIMER_CFG ((uint32_t)0x00360000U | (PCFA_PA11_AFCFG(2) >> 16)) /*!< configure PA11 alternate function to SHRTIMER */
#define AFIO_PA12_CMP1_CFG ((uint32_t)0x00380000U | (PCFA_PA12_AFCFG(1) >> 16)) /*!< configure PA12 alternate function to CMP1 */
#define AFIO_PA12_USART5_CFG ((uint32_t)0x00380000U | (PCFA_PA12_AFCFG(2) >> 16)) /*!< configure PA12 alternate function to USART5 */
#define AFIO_PA12_SHRTIMER_CFG ((uint32_t)0x00380000U | (PCFA_PA12_AFCFG(3) >> 16)) /*!< configure PA12 alternate function to SHRTIMER */
#define AFIO_PA15_SHRTIMER_CFG ((uint32_t)0x00200000U | AFIO_PCFA_PA15_AFCFG >> 16) /*!< configure PA15 alternate function to SHRTIMER */
/* GPIOB AF function definitions */
#define AFIO_PB0_USBHS_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB0_AFCFG) /*!< configure PB0 alternate function to USBHS */
#define AFIO_PB1_CMP3_CFG ((uint32_t)0x01120000U | PCFB_PB1_AFCFG(1)) /*!< configure PB1 alternate function to CMP3 */
#define AFIO_PB1_USBHS_CFG ((uint32_t)0x01120000U | PCFB_PB1_AFCFG(2)) /*!< configure PB1 alternate function to USBHS */
#define AFIO_PB1_SHRTIMER_CFG ((uint32_t)0x01120000U | PCFB_PB1_AFCFG(3)) /*!< configure PB1 alternate function to SHRTIMER */
#define AFIO_PB2_USBHS_CFG ((uint32_t)0x01140000U | PCFB_PB2_AFCFG(2)) /*!< configure PB2 alternate function to USBHS */
#define AFIO_PB2_SHRTIMER_CFG ((uint32_t)0x01140000U | PCFB_PB2_AFCFG(1)) /*!< configure PB2 alternate function to SHRTIMER */
#define AFIO_PB3_SHRTIMER_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB3_AFCFG) /*!< configure PB3 alternate function to SHRTIMER */
#define AFIO_PB4_I2S2_CFG ((uint32_t)0x01180000U | PCFB_PB4_AFCFG(1)) /*!< configure PB4 alternate function to I2S2 */
#define AFIO_PB4_I2C2_CFG ((uint32_t)0x01180000U | PCFB_PB4_AFCFG(2)) /*!< configure PB4 alternate function to I2C2 */
#define AFIO_PB4_SHRTIMER_CFG ((uint32_t)0x01180000U | PCFB_PB4_AFCFG(3)) /*!< configure PB4 alternate function to SHRTIMER */
#define AFIO_PB5_I2C2_CFG ((uint32_t)0x011A0000U | PCFB_PB5_AFCFG(1)) /*!< configure PB5 alternate function to I2C2 */
#define AFIO_PB5_USBHS_CFG ((uint32_t)0x011A0000U | PCFB_PB5_AFCFG(2)) /*!< configure PB5 alternate function to USBHS */
#define AFIO_PB5_SHRTIMER_CFG ((uint32_t)0x011A0000U | PCFB_PB5_AFCFG(3)) /*!< configure PB5 alternate function to SHRTIMER */
#define AFIO_PB6_SHRTIMER_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB6_AFCFG) /*!< configure PB6 alternate function to SHRTIMER */
#define AFIO_PB7_SHRTIMER_CFG ((uint32_t)0x01000000U | AFIO_PCFB_PB7_AFCFG) /*!< configure PB7 alternate function to SHRTIMER */
#define AFIO_PB8_I2C2_CFG ((uint32_t)0x01300000U | (PCFB_PB8_AFCFG(1) >> 16)) /*!< configure PB8 alternate function to I2C2 */
#define AFIO_PB8_SHRTIMER_CFG ((uint32_t)0x01300000U | (PCFB_PB8_AFCFG(2) >> 16)) /*!< configure PB8 alternate function to SHRTIMER */
#define AFIO_PB9_CMP1_CFG ((uint32_t)0x01320000U | (PCFB_PB9_AFCFG(1) >> 16)) /*!< configure PB9 alternate function to CMP1 */
#define AFIO_PB9_SHRTIMER_CFG ((uint32_t)0x01320000U | (PCFB_PB9_AFCFG(2) >> 16)) /*!< configure PB9 alternate function to SHRTIMER */
#define AFIO_PB10_USBHS_CFG ((uint32_t)0x01340000U | (PCFB_PB10_AFCFG(2) >> 16)) /*!< configure PB10 alternate function to USBHS */
#define AFIO_PB10_SHRTIMER_CFG ((uint32_t)0x01340000U | (PCFB_PB10_AFCFG(3) >> 16)) /*!< configure PB10 alternate function to SHRTIMER */
#define AFIO_PB11_USBHS_CFG ((uint32_t)0x01360000U | (PCFB_PB11_AFCFG(2) >> 16)) /*!< configure PB11 alternate function to USBHS */
#define AFIO_PB11_SHRTIMER_CFG ((uint32_t)0x01360000U | (PCFB_PB11_AFCFG(3) >> 16)) /*!< configure PB11 alternate function to SHRTIMER */
#define AFIO_PB12_USBHS_CFG ((uint32_t)0x01380000U | (PCFB_PB12_AFCFG(2) >> 16)) /*!< configure PB12 alternate function to USBHS */
#define AFIO_PB12_SHRTIMER_CFG ((uint32_t)0x01380000U | (PCFB_PB12_AFCFG(1) >> 16)) /*!< configure PB12 alternate function to SHRTIMER */
#define AFIO_PB13_USBHS_CFG ((uint32_t)0x013A0000U | (PCFB_PB13_AFCFG(2) >> 16)) /*!< configure PB13 alternate function to USBHS */
#define AFIO_PB13_SHRTIMER_CFG ((uint32_t)0x013A0000U | (PCFB_PB13_AFCFG(1) >> 16)) /*!< configure PB13 alternate function to SHRTIMER */
#define AFIO_PB14_I2S1_CFG ((uint32_t)0x013C0000U | (PCFB_PB14_AFCFG(1) >> 16)) /*!< configure PB14 alternate function to I2S1 */
#define AFIO_PB14_SHRTIMER_CFG ((uint32_t)0x013C0000U | (PCFB_PB14_AFCFG(2) >> 16)) /*!< configure PB14 alternate function to SHRTIMER */
#define AFIO_PB15_SHRTIMER_CFG ((uint32_t)0x01200000U | (AFIO_PCFB_PB15_AFCFG >> 16)) /*!< configure PB15 alternate function to SHRTIMER */
/* GPIOC AF function definitions */
#define AFIO_PC0_USBHS_CFG ((uint32_t)0x02000000U | AFIO_PCFC_PC0_AFCFG) /*!< configure PC0 alternate function to USBHS */
#define AFIO_PC2_I2S1_CFG ((uint32_t)0x02140000U | PCFC_PC2_AFCFG(1)) /*!< configure PC2 alternate function to I2S1 */
#define AFIO_PC2_USBHS_CFG ((uint32_t)0x02140000U | PCFC_PC2_AFCFG(2)) /*!< configure PC2 alternate function to USBHS */
#define AFIO_PC3_USBHS_CFG ((uint32_t)0x02000000U | AFIO_PCFC_PC3_AFCFG) /*!< configure PC3 alternate function to USBHS */
#define AFIO_PC6_CMP5_CFG ((uint32_t)0x021C0000U | PCFC_PC6_AFCFG(1)) /*!< configure PC6 alternate function to CMP5 */
#define AFIO_PC6_USART5_CFG ((uint32_t)0x021C0000U | PCFC_PC6_AFCFG(2)) /*!< configure PC6 alternate function to USART5 */
#define AFIO_PC6_SHRTIMER_CFG ((uint32_t)0x021C0000U | PCFC_PC6_AFCFG(3)) /*!< configure PC6 alternate function to SHRTIMER */
#define AFIO_PC7_USART5_CFG ((uint32_t)0x021E0000U | PCFC_PC7_AFCFG(2)) /*!< configure PC7 alternate function to USART5 */
#define AFIO_PC7_SHRTIMER_CFG ((uint32_t)0x021E0000U | PCFC_PC7_AFCFG(1)) /*!< configure PC7 alternate function to SHRTIMER */
#define AFIO_PC8_USART5_CFG ((uint32_t)0x02300000U | (PCFC_PC8_AFCFG(2) >> 16)) /*!< configure PC8 alternate function to USART5 */
#define AFIO_PC8_SHRTIMER_CFG ((uint32_t)0x02300000U | (PCFC_PC8_AFCFG(1) >> 16)) /*!< configure PC8 alternate function to SHRTIMER */
#define AFIO_PC9_I2C2_CFG ((uint32_t)0x02320000U | (PCFC_PC9_AFCFG(2) >> 16)) /*!< configure PC9 alternate function to I2C2 */
#define AFIO_PC9_SHRTIMER_CFG ((uint32_t)0x02320000U | (PCFC_PC9_AFCFG(1) >> 16)) /*!< configure PC9 alternate function to SHRTIMER */
#define AFIO_PC10_I2C2_CFG ((uint32_t)0x02200000U | (AFIO_PCFC_PC10_AFCFG >> 16)) /*!< configure PC10 alternate function to I2C2 */
#define AFIO_PC11_I2S2_CFG ((uint32_t)0x02360000U | (PCFC_PC11_AFCFG(2) >> 16)) /*!< configure PC11 alternate function to I2S2 */
#define AFIO_PC11_SHRTIMER_CFG ((uint32_t)0x02360000U | (PCFC_PC11_AFCFG(1) >> 16)) /*!< configure PC11 alternate function to SHRTIMER */
#define AFIO_PC12_SHRTIMER_CFG ((uint32_t)0x02200000U | (AFIO_PCFC_PC12_AFCFG >> 16)) /*!< configure PC12 alternate function to SHRTIMER */
/* GPIOD AF function definitions */
#define AFIO_PD4_SHRTIMER_CFG ((uint32_t)0x03000000U | AFIO_PCFD_PD4_AFCFG) /*!< configure PD4 alternate function to SHRTIMER */
#define AFIO_PD5_SHRTIMER_CFG ((uint32_t)0x03000000U | AFIO_PCFD_PD5_AFCFG) /*!< configure PD5 alternate function to SHRTIMER */
/* GPIOE AF function definitions */
#define AFIO_PE0_SHRTIMER_CFG ((uint32_t)0x04100000U | PCFE_PE0_AFCFG(2)) /*!< configure PE0 alternate function to SHRTIMER */
#define AFIO_PE1_SHRTIMER_CFG ((uint32_t)0x04120000U | PCFE_PE1_AFCFG(2)) /*!< configure PE1 alternate function to SHRTIMER */
#define AFIO_PE8_CMP1_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE8_AFCFG >> 16)) /*!< configure PE8 alternate function to CMP1 */
#define AFIO_PE9_CMP3_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE9_AFCFG >> 16)) /*!< configure PE9 alternate function to CMP3 */
#define AFIO_PE10_CMP5_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE10_AFCFG >> 16)) /*!< configure PE10 alternate function to CMP5 */
#define AFIO_PE11_CMP5_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE11_AFCFG >> 16)) /*!< configure PE11 alternate function to CMP5 */
#define AFIO_PE12_CMP3_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE12_AFCFG >> 16)) /*!< configure PE12 alternate function to CMP3 */
#define AFIO_PE13_CMP1_CFG ((uint32_t)0x04200000U | (AFIO_PCFE_PE13_AFCFG >> 16)) /*!< configure PE13 alternate function to CMP1 */
/* GPIOG AF function definitions */
#define AFIO_PG6_SHRTIMER_CFG ((uint32_t)0x06000000U | AFIO_PCFG_PG6_AFCFG) /*!< configure PG6 alternate function to SHRTIMER_CFG */
#define AFIO_PG7_USART5_CFG ((uint32_t)0x061E0000U | PCFG_PG7_AFCFG(1)) /*!< configure PG7 alternate function to USART5 */
#define AFIO_PG7_SHRTIMER_CFG ((uint32_t)0x061E0000U | PCFG_PG7_AFCFG(2)) /*!< configure PG7 alternate function to SHRTIMER */
#define AFIO_PG9_USART5_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG9_AFCFG >> 16)) /*!< configure PG9 alternate function to USART5 */
#define AFIO_PG10_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG10_AFCFG >> 16)) /*!< configure PG10 alternate function to SHRTIMER */
#define AFIO_PG11_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG11_AFCFG >> 16)) /*!< configure PG11 alternate function to SHRTIMER */
#define AFIO_PG12_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG12_AFCFG >> 16)) /*!< configure PG12 alternate function to SHRTIMER */
#define AFIO_PG13_SHRTIMER_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG13_AFCFG >> 16)) /*!< configure PG13 alternate function to SHRTIMER */
#define AFIO_PG14_USART5_CFG ((uint32_t)0x06200000U | (AFIO_PCFG_PG14_AFCFG >> 16)) /*!< configure PG14 alternate function to USART5 */
#ifdef GD32E50X_CL
/* ethernet MII or RMII PHY selection */
#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */
#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */
#endif /* GD32E50X_CL */
/* I/O compensation cell enable/disable */
#define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */
#define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */
/* function declarations */
/* reset GPIO port */
void gpio_deinit(uint32_t gpio_periph);
/* reset alternate function I/O(AFIO) */
void gpio_afio_deinit(void);
/* GPIO parameter initialization */
void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin);
/* set GPIO pin bit */
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
/* reset GPIO pin bit */
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
/* write data to the specified GPIO pin */
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
/* write data to the specified GPIO port */
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
/* get GPIO pin input status */
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
/* get GPIO port input status */
uint16_t gpio_input_port_get(uint32_t gpio_periph);
/* get GPIO pin output status */
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
/* get GPIO port output status */
uint16_t gpio_output_port_get(uint32_t gpio_periph);
/* configure GPIO pin remap */
void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue);
/* configure AFIO port alternate function */
void gpio_afio_port_config(uint32_t afio_function, ControlStatus newvalue);
#ifdef GD32E50X_CL
/* select ethernet MII or RMII PHY */
void gpio_ethernet_phy_select(uint32_t enet_sel);
#endif /* GD32E50X_CL */
/* select GPIO pin exti sources */
void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin);
/* configure GPIO pin event output */
void gpio_event_output_config(uint8_t output_port, uint8_t output_pin);
/* enable GPIO pin event output */
void gpio_event_output_enable(void);
/* disable GPIO pin event output */
void gpio_event_output_disable(void);
/* lock GPIO pin bit */
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
/* configure the I/O compensation cell */
void gpio_compensation_config(uint32_t compensation);
/* check the I/O compensation cell is ready or not */
FlagStatus gpio_compensation_flag_get(void);
#endif /* GD32E50X_GPIO_H */

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/*!
\file gd32e50x_i2c.h
\brief definitions for the I2C
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_I2C_H
#define GD32E50X_I2C_H
#include "gd32e50x.h"
/* I2Cx(x=0,1,2) definitions */
#define I2C0 I2C_BASE /*!< I2C0 base address */
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
#define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */
/* registers definitions */
/* registers of I2Cx(x=0,1) */
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */
#define I2C_CTL2(i2cx) REG32((i2cx) + 0x00000090U) /*!< control register 2 */
#define I2C_CS(i2cx) REG32((i2cx) + 0x00000094U) /*!< control and status register */
#define I2C_STATC(i2cx) REG32((i2cx) + 0x00000098U) /*!< status clear register */
/* registers of I2Cx(x=2) */
#define I2C2_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
#define I2C2_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
#define I2C2_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/
#define I2C2_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1*/
#define I2C2_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */
#define I2C2_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */
#define I2C2_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */
#define I2C2_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear register */
#define I2C2_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */
#define I2C2_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data register */
#define I2C2_TDATA(i2cx) REG32((i2cx) + 0x00000028U) /*!< I2C transmit data register */
/* bits definitions */
/* bits definitions of I2Cx(x=0,1) */
/* I2Cx_CTL0 */
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
#define I2C_CTL0_START BIT(8) /*!< start generation */
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
/* I2Cx_CTL1 */
#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
/* I2Cx_SADDR0 */
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
/* I2Cx_SADDR1 */
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
/* I2Cx_DATA */
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
/* I2Cx_STAT0 */
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
/* I2Cx_STAT1 */
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
/* I2Cx_CKCFG */
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
/* I2Cx_RT */
#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
/* I2Cx_SAMCS */
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
/* I2Cx_CTL2 */
#define I2C_CTL2_FMPEN BIT(0) /*!< fast mode plus enable */
#define I2C_CTL2_SETM BIT(1) /*!< start early termination mode */
#define I2C_CTL2_TOEN BIT(4) /*!< timeout calculation disable */
#define I2C_CTL2_RADD BIT(8) /*!< record received slave address to the transfer buffer register */
#define I2C_CTL2_ADDM BITS(9,15) /*!< address bit compare select */
/* I2Cx_CS */
#define I2C_CS_STLO BIT(0) /*!< start lost occurred */
#define I2C_CS_STPSEND BIT(1) /*!< stop condition sent */
#define I2C_CS_STLOIE BIT(8) /*!< start lost interrupt enable */
#define I2C_CS_STPSENDIE BIT(9) /*!< stop condition sent interrupt enable */
/* I2Cx_STATC */
#define I2C_STATC_SBSENDC BIT(0) /*!< clear SBSEND bit */
#define I2C_STATC_ADDSENDC BIT(1) /*!< clear ADDSEND bit */
#define I2C_STATC_BTCC BIT(2) /*!< clear BTC bit */
#define I2C_STATC_ADD10SENDC BIT(3) /*!< clear ADD10SEND bit */
#define I2C_STATC_STOPFC BIT(4) /*!< clear STPDET bit */
#define I2C_STATC_SRCEN BIT(15) /*!< Status register clear enable */
/* bits definitions of I2Cx(x=2) */
/* I2Cx_CTL0 */
#define I2C2_CTL0_I2CEN BIT(0) /*!< I2C peripheral enable */
#define I2C2_CTL0_TIE BIT(1) /*!< transmit interrupt enable */
#define I2C2_CTL0_RBNEIE BIT(2) /*!< receive interrupt enable */
#define I2C2_CTL0_ADDMIE BIT(3) /*!< address match interrupt enable in slave mode */
#define I2C2_CTL0_NACKIE BIT(4) /*!< not acknowledge received interrupt enable */
#define I2C2_CTL0_STPDETIE BIT(5) /*!< stop detection interrupt enable */
#define I2C2_CTL0_TCIE BIT(6) /*!< transfer complete interrupt enable */
#define I2C2_CTL0_ERRIE BIT(7) /*!< error interrupt enable */
#define I2C2_CTL0_DNF BITS(8,11) /*!< digital noise filter */
#define I2C2_CTL0_ANOFF BIT(12) /*!< analog noise filter */
#define I2C2_CTL0_DENT BIT(14) /*!< DMA enable for transmission */
#define I2C2_CTL0_DENR BIT(15) /*!< DMA enable for reception */
#define I2C2_CTL0_SBCTL BIT(16) /*!< slave byte control */
#define I2C2_CTL0_SS BIT(17) /*!< whether to stretch SCL low when data is not ready in slave mode */
#define I2C2_CTL0_WUEN BIT(18) /*!< wakeup from Deep-sleep mode enable */
#define I2C2_CTL0_GCEN BIT(19) /*!< whether or not to response to a General Call (0x00) */
#define I2C2_CTL0_SMBHAEN BIT(20) /*!< SMBus host address enable */
#define I2C2_CTL0_SMBDAEN BIT(21) /*!< SMBus device default address enable */
#define I2C2_CTL0_SMBALTEN BIT(22) /*!< SMBus alert enable */
#define I2C2_CTL0_PECEN BIT(23) /*!< PEC calculation switch */
/* I2Cx_CTL1 */
#define I2C2_CTL1_SADDRESS BITS(0,9) /*!< received slave address */
#define I2C2_CTL1_TRDIR BIT(10) /*!< transfer direction in master mode */
#define I2C2_CTL1_ADD10EN BIT(11) /*!< 10-bit addressing mode enable in master mode */
#define I2C2_CTL1_HEAD10R BIT(12) /*!< 10-bit address header executes read direction only in master receive mode */
#define I2C2_CTL1_START BIT(13) /*!< generate a START condition on I2C bus */
#define I2C2_CTL1_STOP BIT(14) /*!< generate a STOP condition on I2C bus */
#define I2C2_CTL1_NACKEN BIT(15) /*!< generate NACK in slave mode */
#define I2C2_CTL1_BYTENUM BITS(16,23) /*!< number of bytes to be transferred */
#define I2C2_CTL1_RELOAD BIT(24) /*!< reload mode enable */
#define I2C2_CTL1_AUTOEND BIT(25) /*!< automatic end mode in master mode */
#define I2C2_CTL1_PECTRANS BIT(26) /*!< PEC transfer */
/* I2Cx_SADDR0 */
#define I2C2_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
#define I2C2_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
#define I2C2_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
#define I2C2_SADDR0_ADDFORMAT BIT(10) /*!< address mode for the I2C slave */
#define I2C2_SADDR0_ADDRESSEN BIT(15) /*!< I2C address enable */
/* I2Cx_SADDR1 */
#define I2C2_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave */
#define I2C2_SADDR1_ADDMSK2 BITS(8,10) /*!< ADDRESS2[7:1] mask */
#define I2C2_SADDR1_ADDRESS2EN BIT(15) /*!< second I2C address enable */
/* I2Cx_TIMING */
#define I2C2_TIMING_SCLL BITS(0,7) /*!< SCL low period */
#define I2C2_TIMING_SCLH BITS(8,15) /*!< SCL high period */
#define I2C2_TIMING_SDADELY BITS(16,19) /*!< data hold time */
#define I2C2_TIMING_SCLDELY BITS(20,23) /*!< data setup time */
#define I2C2_TIMING_PSC BITS(28,31) /*!< timing prescaler */
/* I2Cx_TIMEOUT */
#define I2C2_TIMEOUT_BUSTOA BITS(0,11) /*!< bus timeout A */
#define I2C2_TIMEOUT_TOIDLE BIT(12) /*!< idle clock timeout detection */
#define I2C2_TIMEOUT_TOEN BIT(15) /*!< clock timeout detection enable */
#define I2C2_TIMEOUT_BUSTOB BITS(16,27) /*!< bus timeout B */
#define I2C2_TIMEOUT_EXTOEN BIT(31) /*!< extended clock timeout detection enable */
/* I2Cx_STAT */
#define I2C2_STAT_TBE BIT(0) /*!< I2C_TDATA is empty during transmitting */
#define I2C2_STAT_TI BIT(1) /*!< transmit interrupt */
#define I2C2_STAT_RBNE BIT(2) /*!< I2C_RDATA is not empty during receiving */
#define I2C2_STAT_ADDSEND BIT(3) /*!< address received matches in slave mode */
#define I2C2_STAT_NACK BIT(4) /*!< not acknowledge flag */
#define I2C2_STAT_STPDET BIT(5) /*!< STOP condition detected in slave mode */
#define I2C2_STAT_TC BIT(6) /*!< transfer complete in master mode */
#define I2C2_STAT_TCR BIT(7) /*!< transfer complete reload */
#define I2C2_STAT_BERR BIT(8) /*!< bus error */
#define I2C2_STAT_LOSTARB BIT(9) /*!< arbitration lost */
#define I2C2_STAT_OUERR BIT(10) /*!< overrun/underrun error in slave mode */
#define I2C2_STAT_PECERR BIT(11) /*!< PEC error */
#define I2C2_STAT_TIMEOUT BIT(12) /*!< timeout flag */
#define I2C2_STAT_SMBALT BIT(13) /*!< SMBus Alert */
#define I2C2_STAT_I2CBSY BIT(15) /*!< busy flag */
#define I2C2_STAT_TR BIT(16) /*!< whether the I2C is a transmitter or a receiver in slave mode */
#define I2C2_STAT_READDR BITS(17,23) /*!< received match address in slave mode */
/* I2Cx_STATC */
#define I2C2_STATC_ADDSENDC BIT(3) /*!< ADDSEND flag clear */
#define I2C2_STATC_NACKC BIT(4) /*!< not acknowledge flag clear */
#define I2C2_STATC_STPDETC BIT(5) /*!< STPDET flag clear */
#define I2C2_STATC_BERRC BIT(8) /*!< bus error flag clear */
#define I2C2_STATC_LOSTARBC BIT(9) /*!< arbitration Lost flag clear */
#define I2C2_STATC_OUERRC BIT(10) /*!< overrun/underrun flag clear */
#define I2C2_STATC_PECERRC BIT(11) /*!< PEC error flag clear */
#define I2C2_STATC_TIMEOUTC BIT(12) /*!< TIMEOUT flag clear */
#define I2C2_STATC_SMBALTC BIT(13) /*!< SMBus Alert flag clear */
/* I2Cx_PEC */
#define I2C2_PEC_PECV BITS(0,7) /*!< Packet Error Checking Value that calculated by hardware when PEC is enabled */
/* I2Cx_RDATA */
#define I2C2_RDATA_RDATA BITS(0,7) /*!< receive data value */
/* I2Cx_TDATA */
#define I2C2_TDATA_TDATA BITS(0,7) /*!< transmit data value */
/* constants definitions */
/* define the I2C bit position and its register index offset */
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
/* register offset */
/* register offset of I2Cx(x=0,1) */
#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */
#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */
#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */
#define I2C_CTL2_REG_OFFSET ((uint32_t)0x00000090U) /*!< CTL2 register offset */
#define I2C_CS_REG_OFFSET ((uint32_t)0x00000094U) /*!< control and status register offset */
#define I2C_STATC_REG_OFFSET ((uint32_t)0x00000098U) /*!< status clear register offset */
/* register offset of I2Cx(x=2) */
#define I2C2_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */
#define I2C2_STAT_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT register offset */
/* I2C flag definitions */
/* I2C flag definitions of I2Cx(x=0,1) */
typedef enum
{
/* flags in STAT0 register */
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
/* flags in STAT1 register */
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
/* flags in SAMCS register */
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U), /*!< rxframe rise flag */
/* flags in control and status register */
I2C_FLAG_STLO = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 0U), /*!< start lost flag */
I2C_FLAG_STPSEND = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 1U) /*!< stop condition sent flag */
}i2c_flag_enum;
/* I2C flag definitions of I2Cx(x=2) */
#define I2C2_FLAG_TBE I2C2_STAT_TBE /*!< I2C_TDATA is empty during transmitting */
#define I2C2_FLAG_TI I2C2_STAT_TI /*!< transmit interrupt */
#define I2C2_FLAG_RBNE I2C2_STAT_RBNE /*!< I2C_RDATA is not empty during receiving */
#define I2C2_FLAG_ADDSEND I2C2_STAT_ADDSEND /*!< address received matches in slave mode */
#define I2C2_FLAG_NACK I2C2_STAT_NACK /*!< not acknowledge flag */
#define I2C2_FLAG_STPDET I2C2_STAT_STPDET /*!< STOP condition detected in slave mode */
#define I2C2_FLAG_TC I2C2_STAT_TC /*!< transfer complete in master mode */
#define I2C2_FLAG_TCR I2C2_STAT_TCR /*!< transfer complete reload */
#define I2C2_FLAG_BERR I2C2_STAT_BERR /*!< bus error */
#define I2C2_FLAG_LOSTARB I2C2_STAT_LOSTARB /*!< arbitration lost */
#define I2C2_FLAG_OUERR I2C2_STAT_OUERR /*!< overrun/underrun error in slave mode */
#define I2C2_FLAG_PECERR I2C2_STAT_PECERR /*!< PEC error */
#define I2C2_FLAG_TIMEOUT I2C2_STAT_TIMEOUT /*!< timeout flag */
#define I2C2_FLAG_SMBALT I2C2_STAT_SMBALT /*!< SMBus Alert */
#define I2C2_FLAG_I2CBSY I2C2_STAT_I2CBSY /*!< busy flag */
#define I2C2_FLAG_TR I2C2_STAT_TR /*!< whether the I2C is a transmitter or a receiver in slave mode */
/* I2C interrupt flags */
/* I2C interrupt flags of I2Cx(x=0,1) */
typedef enum
{
/* interrupt flags in CTL1 register */
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
/* interrupt flags in SAMCS register */
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U), /*!< rxframe rise interrupt flag */
/* interrupt flags in control and status register */
I2C_INT_FLAG_STLO = I2C_REGIDX_BIT2(I2C_CS_REG_OFFSET, 8U, I2C_CS_REG_OFFSET, 0U), /*!< start lost interrupt flag */
I2C_INT_FLAG_STPSEND = I2C_REGIDX_BIT2(I2C_CS_REG_OFFSET, 9U, I2C_CS_REG_OFFSET, 1U) /*!< stop condition sent interrupt flag */
}i2c_interrupt_flag_enum;
/* I2C interrupt flags of I2Cx(x=2) */
typedef enum
{
I2C2_INT_FLAG_TI = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 1U, I2C2_STAT_REG_OFFSET, 1U), /*!< transmit interrupt flag */
I2C2_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 2U, I2C2_STAT_REG_OFFSET, 2U), /*!< I2C_RDATA is not empty during receiving interrupt flag */
I2C2_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 3U, I2C2_STAT_REG_OFFSET, 3U), /*!< address received matches in slave mode interrupt flag */
I2C2_INT_FLAG_NACK = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 4U, I2C2_STAT_REG_OFFSET, 4U), /*!< not acknowledge interrupt flag */
I2C2_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 5U, I2C2_STAT_REG_OFFSET, 5U), /*!< stop condition detected in slave mode interrupt flag */
I2C2_INT_FLAG_TC = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 6U, I2C2_STAT_REG_OFFSET, 6U), /*!< transfer complete in master mode interrupt flag */
I2C2_INT_FLAG_TCR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 6U, I2C2_STAT_REG_OFFSET, 7U), /*!< transfer complete reload interrupt flag */
I2C2_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 8U), /*!< bus error interrupt flag */
I2C2_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 9U), /*!< arbitration lost interrupt flag */
I2C2_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 10U), /*!< overrun/underrun error in slave mode interrupt flag */
I2C2_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 11U), /*!< PEC error interrupt flag */
I2C2_INT_FLAG_TIMEOUT = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 12U), /*!< timeout interrupt flag */
I2C2_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 13U), /*!< SMBus Alert interrupt flag */
}i2c2_interrupt_flag_enum;
/* I2C interrupt enable or disable */
/* I2C interrupt enable or disable of I2Cx(x=0,1) */
typedef enum
{
/* interrupt in CTL1 register */
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
/* interrupt in SAMCS register */
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U), /*!< rxframe rise interrupt enable */
/* interrupt in control and status register */
I2C_INT_STLO = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 8U), /*!< start lost interrupt enable */
I2C_INT_STPSEND = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 9U) /*!< stop condition sent interrupt enable */
}i2c_interrupt_enum;
/* I2C interrupt enable or disable of I2Cx(x=2) */
#define I2C2_INT_ERR I2C2_CTL0_ERRIE /*!< error interrupt enable */
#define I2C2_INT_TC I2C2_CTL0_TCIE /*!< transfer complete interrupt enable */
#define I2C2_INT_STPDET I2C2_CTL0_STPDETIE /*!< stop detection interrupt enable */
#define I2C2_INT_NACK I2C2_CTL0_NACKIE /*!< not acknowledge received interrupt enable */
#define I2C2_INT_ADDM I2C2_CTL0_ADDMIE /*!< address match interrupt enable */
#define I2C2_INT_RBNE I2C2_CTL0_RBNEIE /*!< receive interrupt enable */
#define I2C2_INT_TI I2C2_CTL0_TIE /*!< transmit interrupt enable */
/* I2C status register bit clear */
#define CLEAR_STPDET I2C_STATC_STOPFC /*!< clear STPDET bit in I2C_STAT0 */
#define CLEAR_ADD10SEND I2C_STATC_ADD10SENDC /*!< clear ADD10SEND bit in I2C_STAT0 */
#define CLEAR_BTC I2C_STATC_BTCC /*!< clear BTC bit in I2C_STAT0 */
#define CLEAR_ADDSEND I2C_STATC_ADDSENDC /*!< clear ADDSEND bit in I2C_STAT0 */
#define CLEAR_SBSEND I2C_STATC_SBSENDC /*!< clear SBSEND bit in I2C_STAT0 */
/* I2C start early termination mode */
#define STANDARD_I2C_PROTOCOL_MODE ((uint32_t)0x00000000U) /*!< do as the standard i2c protocol */
#define ARBITRATION_LOST_MODE I2C_CTL2_SETM /*!< do the same thing as arbitration lost */
/* SMBus/I2C mode switch and SMBus type selection */
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
/* SMBus/I2C mode switch and SMBus type selection */
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
/* I2C transfer direction */
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
/* whether or not to send an ACK */
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
/* I2C POAP position*/
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
/* software reset I2C */
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
/* I2C DMA mode configure */
/* DMA mode switch */
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
/* flag indicating DMA last transfer */
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
/* I2C PEC configure */
/* PEC enable */
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
/* PEC transfer */
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
/* I2C SMBus configure */
/* issue or not alert through SMBA pin */
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
/* ARP protocol in SMBus switch */
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
/* fast mode plus enable */
#define I2C_FAST_MODE_PLUS_ENABLE I2C_CTL2_FMPEN /*!< fast mode plus enable */
#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */
/* I2C duty cycle in fast mode or fast mode plus */
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */
/* address mode for the I2C slave */
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
/* I2C DMA constants definitions */
#define I2C2_DMA_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C transmit data use DMA */
#define I2C2_DMA_RECEIVE ((uint32_t)0x00000001U) /*!< I2C receive data use DMA */
/* I2C transfer direction in master mode */
#define I2C2_MASTER_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C master transmit */
#define I2C2_MASTER_RECEIVE I2C2_CTL1_TRDIR /*!< I2C master receive */
/* address mode for the I2C slave */
#define I2C2_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
#define I2C2_ADDFORMAT_10BITS I2C2_SADDR0_ADDFORMAT /*!< address:10 bits */
/* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */
#define ADDRESS_BIT1_COMPARE ((uint32_t)0x00000200U) /*!< address bit1 needs compare */
#define ADDRESS_BIT2_COMPARE ((uint32_t)0x00000400U) /*!< address bit2 needs compare */
#define ADDRESS_BIT3_COMPARE ((uint32_t)0x00000800U) /*!< address bit3 needs compare */
#define ADDRESS_BIT4_COMPARE ((uint32_t)0x00001000U) /*!< address bit4 needs compare */
#define ADDRESS_BIT5_COMPARE ((uint32_t)0x00002000U) /*!< address bit5 needs compare */
#define ADDRESS_BIT6_COMPARE ((uint32_t)0x00004000U) /*!< address bit6 needs compare */
#define ADDRESS_BIT7_COMPARE ((uint32_t)0x00008000U) /*!< address bit7 needs compare */
/* the length of filter spikes */
#define FILTER_DISABLE ((uint32_t)0x00000000U) /*!< digital filter is disabled */
#define FILTER_LENGTH_1 ((uint32_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK */
#define FILTER_LENGTH_2 ((uint32_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK */
#define FILTER_LENGTH_3 ((uint32_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK */
#define FILTER_LENGTH_4 ((uint32_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK */
#define FILTER_LENGTH_5 ((uint32_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK */
#define FILTER_LENGTH_6 ((uint32_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK */
#define FILTER_LENGTH_7 ((uint32_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK */
#define FILTER_LENGTH_8 ((uint32_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK */
#define FILTER_LENGTH_9 ((uint32_t)0x00000009U) /*!< digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK */
#define FILTER_LENGTH_10 ((uint32_t)0x0000000AU) /*!< digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK */
#define FILTER_LENGTH_11 ((uint32_t)0x0000000BU) /*!< digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK */
#define FILTER_LENGTH_12 ((uint32_t)0x0000000CU) /*!< digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK */
#define FILTER_LENGTH_13 ((uint32_t)0x0000000DU) /*!< digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK */
#define FILTER_LENGTH_14 ((uint32_t)0x0000000EU) /*!< digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK */
#define FILTER_LENGTH_15 ((uint32_t)0x0000000FU) /*!< digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK */
/* defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don<6F><6E>t care) */
#define ADDRESS2_NO_MASK ((uint32_t)0x00000000U) /*!< no mask, all the bits must be compared */
#define ADDRESS2_MASK_BIT1 ((uint32_t)0x00000001U) /*!< ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared */
#define ADDRESS2_MASK_BIT1_2 ((uint32_t)0x00000002U) /*!< ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared */
#define ADDRESS2_MASK_BIT1_3 ((uint32_t)0x00000003U) /*!< ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared */
#define ADDRESS2_MASK_BIT1_4 ((uint32_t)0x00000004U) /*!< ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared */
#define ADDRESS2_MASK_BIT1_5 ((uint32_t)0x00000005U) /*!< ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared */
#define ADDRESS2_MASK_BIT1_6 ((uint32_t)0x00000006U) /*!< ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared */
#define ADDRESS2_MASK_ALL ((uint32_t)0x00000007U) /*!< all the ADDRESS2[7:1] bits are masked */
/* idle clock timeout detection */
#define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */
#define BUSTOA_DETECT_IDLE I2C2_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */
/* function declarations */
/* functions of I2C0~2 */
/* reset I2C */
void i2c_deinit(uint32_t i2c_periph);
/* enable I2C */
void i2c_enable(uint32_t i2c_periph);
/* disable I2C */
void i2c_disable(uint32_t i2c_periph);
/* generate a START condition on I2C bus */
void i2c_start_on_bus(uint32_t i2c_periph);
/* generate a STOP condition on I2C bus */
void i2c_stop_on_bus(uint32_t i2c_periph);
/* enable the response to a general call */
void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph);
/* disable the response to a general call */
void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph);
/* enable to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_enable(uint32_t i2c_periph);
/* disable to stretch SCL low when data is not ready in slave mode */
void i2c_stretch_scl_low_disable(uint32_t i2c_periph);
/* I2C transmit data function */
void i2c_data_transmit(uint32_t i2c_periph, uint32_t data);
/* I2C receive data function */
uint32_t i2c_data_receive(uint32_t i2c_periph);
/* I2C transfers PEC value */
void i2c_pec_transfer(uint32_t i2c_periph);
/* enable I2C PEC calculation */
void i2c_pec_enable(uint32_t i2c_periph);
/* disable I2C PEC calculation */
void i2c_pec_disable(uint32_t i2c_periph);
/* get packet error checking value */
uint32_t i2c_pec_value_get(uint32_t i2c_periph);
/* functions of I2C0, I2C1 */
/* configure I2C clock */
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
/* configure I2C address */
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
/* SMBus type selection */
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
/* whether or not to send an ACK */
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
/* configure I2C POAP position */
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
/* master sends slave address */
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
/* enable dual-address mode */
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
/* disable dual-address mode */
void i2c_dualaddr_disable(uint32_t i2c_periph);
/* enable I2C DMA mode */
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
/* configure whether next DMA EOT is DMA last transfer or not */
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
/* software reset I2C */
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
/* I2C issue alert through SMBA pin */
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
/* I2C ARP protocol in SMBus switch */
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
/* enable SAM_V interface */
void i2c_sam_enable(uint32_t i2c_periph);
/* disable SAM_V interface */
void i2c_sam_disable(uint32_t i2c_periph);
/* enable SAM_V interface timeout detect */
void i2c_sam_timeout_enable(uint32_t i2c_periph);
/* disable SAM_V interface timeout detect */
void i2c_sam_timeout_disable(uint32_t i2c_periph);
/* configure I2C start early termination mode */
void i2c_start_early_termination_mode_config(uint32_t i2c_periph, uint32_t mode);
/* enable i2c timeout calculation */
void i2c_timeout_calculation_enable(uint32_t i2c_periph);
/* disable i2c timeout calculation */
void i2c_timeout_calculation_disable(uint32_t i2c_periph);
/* enable i2c record the received slave address to the transfer buffer register */
void i2c_record_received_slave_address_enable(uint32_t i2c_periph);
/* disable i2c record the received slave address to the transfer buffer register */
void i2c_record_received_slave_address_disable(uint32_t i2c_periph);
/* define which bits of ADDRESS[7:1] need to compare with the incoming address byte */
void i2c_address_bit_compare_config(uint32_t i2c_periph, uint16_t compare_bits);
/* enable i2c status register clear */
void i2c_status_clear_enable(uint32_t i2c_periph);
/* disable i2c status register clear */
void i2c_status_clear_disable(uint32_t i2c_periph);
/* clear I2C status in I2C_STAT0 register */
void i2c_status_bit_clear(uint32_t i2c_periph, uint32_t clear_bit);
/* check I2C flag is set or not */
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
/* clear I2C flag */
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
/* enable I2C interrupt */
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
/* disable I2C interrupt */
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
/* check I2C interrupt flag */
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
/* clear I2C interrupt flag */
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
/* functions of I2C2 */
/* configure the timing parameters */
void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely);
/* configure digital noise filter */
void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length);
/* enable analog noise filter */
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
/* disable analog noise filter */
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
/* enable wakeup from Deep-sleep mode */
void i2c_wakeup_from_deepsleep_enable(uint32_t i2c_periph);
/* disable wakeup from Deep-sleep mode */
void i2c_wakeup_from_deepsleep_disable(uint32_t i2c_periph);
/* configure the SCL high and low period of clock in master mode */
void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll);
/* configure i2c slave address and transfer direction in master mode */
void i2c2_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction);
/* 10-bit address header executes read direction only in master receive mode */
void i2c_address10_header_enable(uint32_t i2c_periph);
/* 10-bit address header executes complete sequence in master receive mode */
void i2c_address10_header_disable(uint32_t i2c_periph);
/* enable 10-bit addressing mode in master mode */
void i2c_address10_enable(uint32_t i2c_periph);
/* disable 10-bit addressing mode in master mode */
void i2c_address10_disable(uint32_t i2c_periph);
/* enable I2C automatic end mode in master mode */
void i2c_automatic_end_enable(uint32_t i2c_periph);
/* disable I2C automatic end mode in master mode */
void i2c_automatic_end_disable(uint32_t i2c_periph);
/* configure i2c slave address */
void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format);
/* disable i2c address in slave mode */
void i2c_address_disable(uint32_t i2c_periph);
/* configure i2c second slave address */
void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask);
/* disable i2c second address in slave mode */
void i2c_second_address_disable(uint32_t i2c_periph);
/* get received match address in slave mode */
uint32_t i2c_recevied_address_get(uint32_t i2c_periph);
/* enable slave byte control */
void i2c_slave_byte_control_enable(uint32_t i2c_periph);
/* disable slave byte control */
void i2c_slave_byte_control_disable(uint32_t i2c_periph);
/* generate a NACK in slave mode */
void i2c_nack_enable(uint32_t i2c_periph);
/* generate an ACK in slave mode */
void i2c_nack_disable(uint32_t i2c_periph);
/* enable I2C reload mode */
void i2c_reload_enable(uint32_t i2c_periph);
/* disable I2C reload mode */
void i2c_reload_disable(uint32_t i2c_periph);
/* configure number of bytes to be transferred */
void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number);
/* enable I2C DMA for transmission or reception */
void i2c2_dma_enable(uint32_t i2c_periph, uint8_t dma);
/* disable I2C DMA for transmission or reception */
void i2c2_dma_disable(uint32_t i2c_periph, uint8_t dma);
/* enable SMBus Alert */
void i2c_smbus_alert_enable(uint32_t i2c_periph);
/* disable SMBus Alert */
void i2c_smbus_alert_disable(uint32_t i2c_periph);
/* enable SMBus device default address */
void i2c_smbus_default_addr_enable(uint32_t i2c_periph);
/* disable SMBus device default address */
void i2c_smbus_default_addr_disable(uint32_t i2c_periph);
/* enable SMBus Host address */
void i2c_smbus_host_addr_enable(uint32_t i2c_periph);
/* disable SMBus Host address */
void i2c_smbus_host_addr_disable(uint32_t i2c_periph);
/* enable extended clock timeout detection */
void i2c_extented_clock_timeout_enable(uint32_t i2c_periph);
/* disable extended clock timeout detection */
void i2c_extented_clock_timeout_disable(uint32_t i2c_periph);
/* enable clock timeout detection */
void i2c_clock_timeout_enable(uint32_t i2c_periph);
/* disable clock timeout detection */
void i2c_clock_timeout_disable(uint32_t i2c_periph);
/* configure bus timeout B */
void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout);
/* configure bus timeout A */
void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout);
/* configure idle clock timeout detection */
void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout);
/* get I2C flag status */
FlagStatus i2c2_flag_get(uint32_t i2c_periph, uint32_t flag);
/* clear I2C flag status */
void i2c2_flag_clear(uint32_t i2c_periph, uint32_t flag);
/* enable I2C interrupt */
void i2c2_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt);
/* disable I2C interrupt */
void i2c2_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt);
/* get I2C interrupt flag status */
FlagStatus i2c2_interrupt_flag_get(uint32_t i2c_periph, i2c2_interrupt_flag_enum int_flag);
/* clear I2C interrupt flag status */
void i2c2_interrupt_flag_clear(uint32_t i2c_periph, i2c2_interrupt_flag_enum int_flag);
#endif /* GD32E50X_I2C_H */

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/*!
\file gd32e50x_misc.h
\brief definitions for the MISC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_MISC_H
#define GD32E50X_MISC_H
#include "gd32e50x.h"
/* constants definitions */
/* set the RAM and FLASH base address */
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
/* set the NVIC vector table offset mask */
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/* priority group - define the pre-emption priority and the subpriority */
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
/* choose the method to enter or exit the lowpower mode */
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
/* choose the systick clock source */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
/* function declarations */
/* set the priority group */
void nvic_priority_group_set(uint32_t nvic_prigroup);
/* enable NVIC request */
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
/* disable NVIC request */
void nvic_irq_disable(uint8_t nvic_irq);
/* initiates a system reset request to reset the MCU */
void nvic_system_reset(void);
/* set the NVIC vector table base address */
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
/* set the state of the low power mode */
void system_lowpower_set(uint8_t lowpower_mode);
/* reset the state of the low power mode */
void system_lowpower_reset(uint8_t lowpower_mode);
/* set the systick clock source */
void systick_clksource_set(uint32_t systick_clksource);
#endif /* GD32E50X_MISC_H */

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/*!
\file gd32e50x_pmu.h
\brief definitions for the PMU
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_PMU_H
#define GD32E50X_PMU_H
#include "gd32e50x.h"
/* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */
/* registers definitions */
#define PMU_CTL0 REG32((PMU) + 0x00000000U) /*!< PMU control register 0 */
#define PMU_CS0 REG32((PMU) + 0x00000004U) /*!< PMU control and status register 0 */
#define PMU_CTL1 REG32((PMU) + 0x00000008U) /*!< PMU control register 1 */
#define PMU_CS1 REG32((PMU) + 0x0000000CU) /*!< PMU control and status register 1 */
/* bits definitions */
/* PMU_CTL0 */
#define PMU_CTL0_LDOLP BIT(0) /*!< LDO low power mode */
#define PMU_CTL0_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL0_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL0_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL0_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL0_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL0_BKPWEN BIT(8) /*!< backup domain write enable */
#define PMU_CTL0_LDLP BIT(10) /*!< low-driver mode when use low power LDO */
#define PMU_CTL0_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */
#define PMU_CTL0_HDEN BIT(16) /*!< high-driver mode enable */
#define PMU_CTL0_HDS BIT(17) /*!< high-driver mode switch */
#define PMU_CTL0_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep/deep-sleep 1/deep-sleep 2 mode */
/* PMU_CS0 */
#define PMU_CS0_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS0_STBF BIT(1) /*!< standby flag */
#define PMU_CS0_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS0_WUPEN6 BIT(7) /*!< wakeup pin 6 enable */
#define PMU_CS0_WUPEN0 BIT(8) /*!< wakeup pin 0 enable */
#define PMU_CS0_WUPEN1 BIT(9) /*!< wakeup pin 1 enable */
#define PMU_CS0_WUPEN2 BIT(10) /*!< wakeup pin 2 enable */
#define PMU_CS0_WUPEN3 BIT(11) /*!< wakeup pin 3 enable */
#define PMU_CS0_WUPEN4 BIT(12) /*!< wakeup pin 4 enable */
#define PMU_CS0_WUPEN5 BIT(13) /*!< wakeup pin 5 enable */
#define PMU_CS0_WUPEN7 BIT(15) /*!< wakeup pin 7 enable */
#define PMU_CS0_HDRF BIT(16) /*!< high-driver ready flag */
#define PMU_CS0_HDSRF BIT(17) /*!< high-driver switch ready flag */
#define PMU_CS0_LDRF BITS(18,19) /*!< Low-driver mode ready flag */
/* PMU_CTL1 */
#define PMU_CTL1_DPMOD1 BIT(0) /*!< deep-sleep 1 mode enable */
#define PMU_CTL1_DPMOD2 BIT(1) /*!< deep-sleep 2 mode enable */
/* PMU_CS1 */
#define PMU_CS1_DPF1 BIT(0) /*!< deep-sleep 1 mode status flag */
#define PMU_CS1_DPF2 BIT(1) /*!< deep-sleep 2 mode status flag */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL0_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
#define PMU_LVDT_0 CTL0_LVDT(0) /*!< voltage threshold is 2.1V */
#define PMU_LVDT_1 CTL0_LVDT(1) /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2 CTL0_LVDT(2) /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3 CTL0_LVDT(3) /*!< voltage threshold is 2.6V */
#define PMU_LVDT_4 CTL0_LVDT(4) /*!< voltage threshold is 2.7V */
#define PMU_LVDT_5 CTL0_LVDT(5) /*!< voltage threshold is 2.9V */
#define PMU_LVDT_6 CTL0_LVDT(6) /*!< voltage threshold is 3.0V */
#define PMU_LVDT_7 CTL0_LVDT(7) /*!< voltage threshold is 3.1V */
/* PMU high-driver mode switch */
#define CTL0_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
#define PMU_HIGHDR_SWITCH_NONE CTL0_HDS(0) /*!< no high-driver mode switch */
#define PMU_HIGHDR_SWITCH_EN CTL0_HDS(1) /*!< high-driver mode switch */
/* PMU low-driver mode when use low power LDO */
#define CTL0_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
#define PMU_NORMALDR_LOWPWR CTL0_LDLP(0) /*!< normal driver when use low power LDO */
#define PMU_LOWDR_LOWPWR CTL0_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
/* PMU low-driver mode when use normal power LDO */
#define CTL0_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11))
#define PMU_NORMALDR_NORMALPWR CTL0_LDNP(0) /*!< normal driver when use normal power LDO */
#define PMU_LOWDR_NORMALPWR CTL0_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
/* PMU low power mode ready flag definitions */
#define CS0_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
#define PMU_LDRF_NORMAL CS0_LDRF(0) /*!< normal driver in deep-sleep/deep-sleep 1/deep-sleep 2 mode */
#define PMU_LDRF_LOWDRIVER CS0_LDRF(3) /*!< low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */
/* PMU flag definitions */
#define PMU_FLAG_WAKEUP PMU_CS0_WUF /*!< wakeup flag status */
#define PMU_FLAG_STANDBY PMU_CS0_STBF /*!< standby flag status */
#define PMU_FLAG_LVD PMU_CS0_LVDF /*!< lvd flag status */
#define PMU_FLAG_HDRF PMU_CS0_HDRF /*!< high-driver ready flag */
#define PMU_FLAG_HDSRF PMU_CS0_HDSRF /*!< high-driver switch ready flag */
#define PMU_FLAG_LDRF PMU_CS0_LDRF /*!< low-driver mode ready flag */
#define PMU_FLAG_DEEPSLEEP_1 (BIT(31) | PMU_CS1_DPF1) /*!< deep-sleep 1 mode status flag */
#define PMU_FLAG_DEEPSLEEP_2 (BIT(31) | PMU_CS1_DPF2) /*!< deep-sleep 2 mode status flag */
/* PMU ldo definitions */
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */
#define PMU_LDO_LOWPOWER PMU_CTL0_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
/* PMU WKUP pin definitions */
#define PMU_WAKEUP_PIN0 PMU_CS0_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
#define PMU_WAKEUP_PIN1 PMU_CS0_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
#define PMU_WAKEUP_PIN2 PMU_CS0_WUPEN2 /*!< WKUP Pin 2 (PE6) enable */
#define PMU_WAKEUP_PIN3 PMU_CS0_WUPEN3 /*!< WKUP Pin 3 (PA2) enable */
#define PMU_WAKEUP_PIN4 PMU_CS0_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */
#define PMU_WAKEUP_PIN5 PMU_CS0_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
#define PMU_WAKEUP_PIN6 PMU_CS0_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
#define PMU_WAKEUP_PIN7 PMU_CS0_WUPEN7 /*!< WKUP Pin 7 (PF8) enable */
/* PMU flag reset definitions */
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
#define PMU_FLAG_RESET_DEEPSLEEP_1 ((uint8_t)0x02U) /*!< deep-sleep 1 mode status flag reset */
#define PMU_FLAG_RESET_DEEPSLEEP_2 ((uint8_t)0x03U) /*!< deep-sleep 2 mode status flag reset */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
/* function declarations */
/* reset PMU registers */
void pmu_deinit(void);
/* LVD functions */
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t lvdt_n);
/* disable PMU LVD */
void pmu_lvd_disable(void);
/* functions of low-driver mode and high-driver mode */
/* enable high-driver mode */
void pmu_highdriver_mode_enable(void);
/* disable high-driver mode */
void pmu_highdriver_mode_disable(void);
/* switch high-driver mode */
void pmu_highdriver_switch_select(uint32_t highdr_switch);
/* enable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */
void pmu_lowdriver_mode_enable(void);
/* disable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode */
void pmu_lowdriver_mode_disable(void);
/* in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use low power LDO */
void pmu_lowpower_driver_config(uint32_t mode);
/* in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use normal power LDO */
void pmu_normalpower_driver_config(uint32_t mode);
/* set PMU mode */
/* PMU work at sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* PMU work at deepsleep mode */
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
/* PMU work at deepsleep mode 1 */
void pmu_to_deepsleepmode_1(uint32_t ldo,uint8_t deepsleepmode1cmd);
/* PMU work at deepsleep mode 2 */
void pmu_to_deepsleepmode_2(uint32_t ldo,uint8_t deepsleepmode2cmd);
/* PMU work at standby mode */
void pmu_to_standbymode(uint8_t standbymodecmd);
/* enable PMU wakeup pin */
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
/* disable PMU wakeup pin */
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
/* backup related functions */
/* enable backup domain write */
void pmu_backup_write_enable(void);
/* disable backup domain write */
void pmu_backup_write_disable(void);
/* flag functions */
/* clear flag bit */
void pmu_flag_clear(uint32_t flag_reset);
/* get flag state */
FlagStatus pmu_flag_get(uint32_t flag);
#endif /* GD32E50X_PMU_H */

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/*!
\file gd32e50x_rtc.h
\brief definitions for the RTC
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_RTC_H
#define GD32E50X_RTC_H
#include "gd32e50x.h"
/* RTC definitions */
#define RTC RTC_BASE
/* registers definitions */
#define RTC_INTEN REG32(RTC + 0x00000000U) /*!< interrupt enable register */
#define RTC_CTL REG32(RTC + 0x00000004U) /*!< control register */
#define RTC_PSCH REG32(RTC + 0x00000008U) /*!< prescaler high register */
#define RTC_PSCL REG32(RTC + 0x0000000CU) /*!< prescaler low register */
#define RTC_DIVH REG32(RTC + 0x00000010U) /*!< divider high register */
#define RTC_DIVL REG32(RTC + 0x00000014U) /*!< divider low register */
#define RTC_CNTH REG32(RTC + 0x00000018U) /*!< counter high register */
#define RTC_CNTL REG32(RTC + 0x0000001CU) /*!< counter low register */
#define RTC_ALRMH REG32(RTC + 0x00000020U) /*!< alarm high register */
#define RTC_ALRML REG32(RTC + 0x00000024U) /*!< alarm low register */
/* bits definitions */
/* RTC_INTEN */
#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */
#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */
#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */
/* RTC_CTL */
#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */
#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */
#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */
#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */
#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */
#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */
/* RTC_PSC */
#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */
#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */
/* RTC_DIV */
#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */
#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */
/* RTC_CNT */
#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */
#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */
/* RTC_ALRM */
#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */
#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */
/* constants definitions */
#define RTC_HIGH_VALUE ((uint32_t)0x000F0000U) /*!< RTC high value */
#define RTC_LOW_VALUE ((uint32_t)0x0000FFFFU) /*!< RTC low value */
/* RTC interrupt enable or disable definitions */
#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */
#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */
#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */
/* RTC flag definitions */
#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */
#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */
#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */
#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */
#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */
/* function declarations */
/* enter RTC configuration mode */
void rtc_configuration_mode_enter(void);
/* exit RTC configuration mode */
void rtc_configuration_mode_exit(void);
/* wait RTC last write operation finished flag set */
void rtc_lwoff_wait(void);
/* wait RTC registers synchronized flag set */
void rtc_register_sync_wait(void);
/* get RTC counter value */
uint32_t rtc_counter_get(void);
/* set RTC counter value */
void rtc_counter_set(uint32_t cnt);
/* set RTC prescaler value */
void rtc_prescaler_set(uint32_t psc);
/* set RTC alarm value */
void rtc_alarm_config(uint32_t alarm);
/* get RTC divider value */
uint32_t rtc_divider_get(void);
/* enable RTC interrupt */
void rtc_interrupt_enable(uint32_t interrupt);
/* disable RTC interrupt */
void rtc_interrupt_disable(uint32_t interrupt);
/* get RTC flag status */
FlagStatus rtc_flag_get(uint32_t flag);
/* clear RTC flag status */
void rtc_flag_clear(uint32_t flag);
#endif /* GD32E50X_RTC_H */

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/*!
\file gd32e50x_sdio.h
\brief definitions for the SDIO
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_SDIO_H
#define GD32E50X_SDIO_H
#include "gd32e50x.h"
/* SDIO definitions */
#define SDIO SDIO_BASE
/* registers definitions */
#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */
#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */
#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */
#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */
#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */
#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */
#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */
#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */
#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */
#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */
#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */
#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */
#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */
#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */
#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */
#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */
#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */
#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */
/* bits definitions */
/* SDIO_PWRCTL */
#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
/* SDIO_CLKCTL */
#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */
#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */
#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */
#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */
#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */
#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */
#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */
/* SDIO_CMDAGMT */
#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
/* SDIO_CMDCTL */
#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */
#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */
#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */
#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */
#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */
#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */
#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */
#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */
/* SDIO_DATATO */
#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
/* SDIO_DATALEN */
#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
/* SDIO_DATACTL */
#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */
#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */
#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */
#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */
#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */
#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */
/* SDIO_STAT */
#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */
#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */
#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */
#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */
#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */
#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */
#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */
#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */
/* SDIO_INTC */
#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */
#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */
/* SDIO_INTEN */
#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */
#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */
#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */
#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */
#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */
#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */
#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */
#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */
#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */
/* SDIO_FIFO */
#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */
/* constants definitions */
/* SDIO flags */
#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */
#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */
#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */
#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */
#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */
#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */
#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */
/* SDIO interrupt enable or disable */
#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */
#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */
#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */
#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
/* SDIO interrupt flags */
#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */
#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */
#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */
#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */
#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */
#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */
#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */
#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */
#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */
#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */
#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */
#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */
#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */
#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */
#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */
#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */
#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */
#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */
#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */
#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */
#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */
#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */
#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */
#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */
/* SDIO power control */
#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
/* SDIO card bus mode control */
#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
/* SDIO_CLK clock edge selection */
#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
/* clock bypass enable or disable */
#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */
#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */
/* SDIO_CLK clock dynamic switch on/off for power saving */
#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */
#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
/* SDIO command response type */
#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
/* command state machine wait type */
#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */
#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */
#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */
#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */
#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */
/* SDIO data block size */
#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
/* SDIO data transfer mode */
#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */
#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */
/* SDIO data transfer direction */
#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */
#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
/* SDIO read wait type */
#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */
#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
/* function declarations */
/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */
/* deinitialize the SDIO */
void sdio_deinit(void);
/* configure the SDIO clock */
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
/* enable hardware clock control */
void sdio_hardware_clock_enable(void);
/* disable hardware clock control */
void sdio_hardware_clock_disable(void);
/* set different SDIO card bus mode */
void sdio_bus_mode_set(uint32_t bus_mode);
/* set the SDIO power state */
void sdio_power_state_set(uint32_t power_state);
/* get the SDIO power state */
uint32_t sdio_power_state_get(void);
/* enable SDIO_CLK clock output */
void sdio_clock_enable(void);
/* disable SDIO_CLK clock output */
void sdio_clock_disable(void);
/* configure the command index, argument, response type, wait type and CSM to send command functions */
/* configure the command and response */
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
/* set the command state machine wait type */
void sdio_wait_type_set(uint32_t wait_type);
/* enable the CSM(command state machine) */
void sdio_csm_enable(void);
/* disable the CSM(command state machine) */
void sdio_csm_disable(void);
/* get the last response command index */
uint8_t sdio_command_index_get(void);
/* get the response for the last received command */
uint32_t sdio_response_get(uint32_t responsex);
/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */
/* configure the data timeout, data length and data block size */
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
/* configure the data transfer mode and direction */
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
/* enable the DSM(data state machine) for data transfer */
void sdio_dsm_enable(void);
/* disable the DSM(data state machine) */
void sdio_dsm_disable(void);
/* write data(one word) to the transmit FIFO */
void sdio_data_write(uint32_t data);
/* read data(one word) from the receive FIFO */
uint32_t sdio_data_read(void);
/* get the number of remaining data bytes to be transferred to card */
uint32_t sdio_data_counter_get(void);
/* get the number of words remaining to be written or read from FIFO */
uint32_t sdio_fifo_counter_get(void);
/* enable the DMA request for SDIO */
void sdio_dma_enable(void);
/* disable the DMA request for SDIO */
void sdio_dma_disable(void);
/* flag and interrupt functions */
/* get the flags state of SDIO */
FlagStatus sdio_flag_get(uint32_t flag);
/* clear the pending flags of SDIO */
void sdio_flag_clear(uint32_t flag);
/* enable the SDIO interrupt */
void sdio_interrupt_enable(uint32_t int_flag);
/* disable the SDIO interrupt */
void sdio_interrupt_disable(uint32_t int_flag);
/* get the interrupt flags state of SDIO */
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
/* clear the interrupt pending flags of SDIO */
void sdio_interrupt_flag_clear(uint32_t int_flag);
/* SD I/O card functions */
/* enable the read wait mode(SD I/O only) */
void sdio_readwait_enable(void);
/* disable the read wait mode(SD I/O only) */
void sdio_readwait_disable(void);
/* enable the function that stop the read wait process(SD I/O only) */
void sdio_stop_readwait_enable(void);
/* disable the function that stop the read wait process(SD I/O only) */
void sdio_stop_readwait_disable(void);
/* set the read wait type(SD I/O only) */
void sdio_readwait_type_set(uint32_t readwait_type);
/* enable the SD I/O mode specific operation(SD I/O only) */
void sdio_operation_enable(void);
/* disable the SD I/O mode specific operation(SD I/O only) */
void sdio_operation_disable(void);
/* enable the SD I/O suspend operation(SD I/O only) */
void sdio_suspend_enable(void);
/* disable the SD I/O suspend operation(SD I/O only) */
void sdio_suspend_disable(void);
/* CE-ATA functions */
/* enable the CE-ATA command(CE-ATA only) */
void sdio_ceata_command_enable(void);
/* disable the CE-ATA command(CE-ATA only) */
void sdio_ceata_command_disable(void);
/* enable the CE-ATA interrupt(CE-ATA only) */
void sdio_ceata_interrupt_enable(void);
/* disable the CE-ATA interrupt(CE-ATA only) */
void sdio_ceata_interrupt_disable(void);
/* enable the CE-ATA command completion signal(CE-ATA only) */
void sdio_ceata_command_completion_enable(void);
/* disable the CE-ATA command completion signal(CE-ATA only) */
void sdio_ceata_command_completion_disable(void);
#endif /* GD32E50X_SDIO_H */

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/*!
\file gd32e50x_spi.h
\brief definitions for the SPI
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_SPI_H
#define GD32E50X_SPI_H
#include "gd32e50x.h"
/* SPIx(x=0,1,2) definitions */
#define SPI0 (SPI_BASE + 0x0000F800U)
#define SPI1 SPI_BASE
#define SPI2 (SPI_BASE + 0x00000400U)
/* I2Sx_ADD(x=1,2) definitions */
#define I2S1_ADD I2S_ADD_BASE
#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U)
/* SPI registers definitions */
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only SPI0) */
/* I2S_ADD registers definitions */
#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */
#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/
#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */
#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */
#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */
#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */
#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */
#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */
#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */
/* bits definitions */
/* SPI_CTL0 */
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
#define SPI_CTL0_RO BIT(10) /*!< receive only */
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
/* SPI_CTL1 */
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
/* SPI_STAT */
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
/* SPI_DATA */
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
/* SPI_CRCPOLY */
#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */
/* SPI_RCRC */
#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */
/* SPI_TCRC */
#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */
/* SPI_I2SCTL */
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
/* SPI_I2SPSC */
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
/* SPI_QCTL(only for SPI0) */
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
/* constants definitions */
/* SPI and I2S parameter struct definitions */
typedef struct
{
uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */
uint32_t frame_size; /*!< SPI frame size */
uint32_t nss; /*!< SPI NSS control by handware or software */
uint32_t endian; /*!< SPI big endian or little endian */
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
uint32_t prescale; /*!< SPI prescale factor */
}spi_parameter_struct;
/* SPI mode definitions */
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
/* SPI bidirectional transfer direction */
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
/* SPI transmit type */
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
/* SPI frame size */
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
/* SPI NSS control mode */
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
/* SPI transmit way */
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
/* SPI clock phase and polarity */
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
/* SPI clock prescale factor */
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
/* I2S audio sample rate */
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
/* I2S frame format */
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
/* I2S master clock output */
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
/* I2S operation mode */
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
/* I2S standard */
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
/* I2S clock polarity */
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
/* SPI DMA constants definitions */
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
/* SPI CRC constants definitions */
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
/* SPI/I2S interrupt enable/disable constants definitions */
#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */
#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */
#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */
/* SPI/I2S interrupt flag constants definitions */
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
/* SPI/I2S flag definitions */
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
/* function declarations */
/* SPI/I2S deinitialization and initialization functions */
/* reset SPI and I2S */
void spi_i2s_deinit(uint32_t spi_periph);
/* initialize the parameters of SPI struct with the default values */
void spi_struct_para_init(spi_parameter_struct* spi_struct);
/* initialize SPI parameter */
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
/* enable SPI */
void spi_enable(uint32_t spi_periph);
/* disable SPI */
void spi_disable(uint32_t spi_periph);
/* initialize I2S parameter */
void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl);
/* configure I2S prescaler */
void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout);
/* enable I2S */
void i2s_enable(uint32_t spi_periph);
/* disable I2S */
void i2s_disable(uint32_t spi_periph);
/* NSS functions */
/* enable SPI NSS output */
void spi_nss_output_enable(uint32_t spi_periph);
/* disable SPI NSS output */
void spi_nss_output_disable(uint32_t spi_periph);
/* SPI NSS pin high level in software mode */
void spi_nss_internal_high(uint32_t spi_periph);
/* SPI NSS pin low level in software mode */
void spi_nss_internal_low(uint32_t spi_periph);
/* SPI DMA functions */
/* enable SPI DMA */
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
/* disable SPI DMA */
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
/* SPI/I2S transfer configure functions */
/* configure SPI/I2S data frame format */
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
/* SPI transmit data */
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
/* SPI receive data */
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
/* configure SPI bidirectional transfer direction */
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
/* SPI CRC functions */
/* set SPI CRC polynomial */
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
/* get SPI CRC polynomial */
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
/* turn on SPI CRC function */
void spi_crc_on(uint32_t spi_periph);
/* turn off SPI CRC function */
void spi_crc_off(uint32_t spi_periph);
/* SPI next data is CRC value */
void spi_crc_next(uint32_t spi_periph);
/* get SPI CRC send value or receive value */
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
/* SPI TI mode functions */
/* enable SPI TI mode */
void spi_ti_mode_enable(uint32_t spi_periph);
/* disable SPI TI mode */
void spi_ti_mode_disable(uint32_t spi_periph);
/* SPI NSS pulse mode functions */
/* enable SPI NSS pulse mode */
void spi_nssp_mode_enable(uint32_t spi_periph);
/* disable SPI NSS pulse mode */
void spi_nssp_mode_disable(uint32_t spi_periph);
/* configure i2s full duplex mode */
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat);
/* quad wire SPI functions */
/* enable quad wire SPI */
void qspi_enable(uint32_t spi_periph);
/* disable quad wire SPI */
void qspi_disable(uint32_t spi_periph);
/* enable quad wire SPI write */
void qspi_write_enable(uint32_t spi_periph);
/* enable quad wire SPI read */
void qspi_read_enable(uint32_t spi_periph);
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
void qspi_io23_output_enable(uint32_t spi_periph);
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
void qspi_io23_output_disable(uint32_t spi_periph);
/* flag and interrupt functions */
/* enable SPI and I2S interrupt */
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
/* disable SPI and I2S interrupt */
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
/* get SPI and I2S interrupt status */
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
/* get SPI and I2S flag status */
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
/* clear SPI CRC error flag status */
void spi_crc_error_clear(uint32_t spi_periph);
#endif /* GD32E50X_SPI_H */

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/*!
\file gd32e50x_sqpi.h
\brief definitions for the SQPI
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_SQPI_H
#define GD32E50X_SQPI_H
#include "gd32e50x.h"
/* SQPI definitions */
#define SQPI SQPI_BASE
/* SQPI registers definitions */
#define SQPI_INIT REG32((SQPI) + 0x00000000U) /*!< SQPI initial register*/
#define SQPI_RCMD REG32((SQPI) + 0x00000004U) /*!< SQPI read command register */
#define SQPI_WCMD REG32((SQPI) + 0x00000008U) /*!< SQPI write command register */
#define SQPI_IDL REG32((SQPI) + 0x0000000CU) /*!< SQPI ID low register */
#define SQPI_IDH REG32((SQPI) + 0x00000010U) /*!< SQPI ID high register */
/* bits definitions */
/* SQPI_INIT */
#define SQPI_INIT_CMDBIT BITS(16,17) /*!< bit number of SQPI controller command phase */
#define SQPI_INIT_CLKDIV BITS(18,23) /*!< clock divider for SQPI output clock */
#define SQPI_INIT_ADDRBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase*/
#define SQPI_INIT_IDLEN BITS(29,30) /*!< external memory ID length */
#define SQPI_INIT_PL BIT(31) /*!< SQPI read data sample polarity */
/* SQPI_RCMD */
#define SQPI_RCMD_RCMD BITS(0,15) /*!< SQPI read command for AHB read transfer */
#define SQPI_RCMD_RWAITCYCLE BITS(16,19) /*!< read command waitcycle number */
#define SQPI_RCMD_RMODE BITS(20,22) /*!< read command mode */
#define SQPI_RCMD_RID BIT(31) /*!< send read ID command */
/* SQPI_WCMD */
#define SQPI_WCMD_WCMD BITS(0,15) /*!< SQPI write command for AHB write transfer */
#define SQPI_WCMD_WWAITCYCLE BITS(16,19) /*!< write command waitcycle number */
#define SQPI_WCMD_WMODE BITS(20,22) /*!< write command mode */
#define SQPI_WCMD_SCMD BIT(31) /*!< send special command */
/* SQPI_IDL */
#define SQPI_IDL_IDL BITS(0,31) /*!< ID low register */
/* SQPI_IDH */
#define SQPI_IDH_IDH BITS(0,31) /*!< ID high register */
/* constants definitions */
/* SQPI parameter struct definitions */
typedef struct
{
uint32_t polarity; /*!< SQPI sample polarity*/
uint32_t id_length; /*!< external memory ID length */
uint32_t addr_bit; /*!< bit number of SPI PSRAM address phase */
uint32_t clk_div; /*!< clock divider for SQPI output clock */
uint32_t cmd_bit; /*!< bit number of SQPI controller command phase */
}sqpi_parameter_struct;
/* SQPI sample shift */
#define SQPI_SAMPLE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< SQPI read data at rising edge */
#define SQPI_SAMPLE_POLARITY_FALLING (SQPI_INIT_PL) /*!< SQPI read data at falling edge */
/* SQPI ID length */
#define INIT_IDLEN(regval) (BITS(29,30) & ((uint32_t)(regval) << 29))
#define SQPI_ID_LENGTH_64_BITS INIT_IDLEN(0) /*!< 64 bits ID */
#define SQPI_ID_LENGTH_32_BITS INIT_IDLEN(1) /*!< 32 bits ID */
#define SQPI_ID_LENGTH_16_BITS INIT_IDLEN(2) /*!< 16 bits ID */
#define SQPI_ID_LENGTH_8_BITS INIT_IDLEN(3) /*!< 8 bits ID */
/* SQPI command bits */
#define INIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
#define SQPI_CMDBIT_4_BITS INIT_CMDBIT(0) /*!< 4 bits command */
#define SQPI_CMDBIT_8_BITS INIT_CMDBIT(1) /*!< 8 bits command */
#define SQPI_CMDBIT_16_BITS INIT_CMDBIT(2) /*!< 16 bits command */
/* SQPI mode */
#define SQPI_MODE(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
#define SQPI_MODE_SSQ SQPI_MODE(0) /*!< SQPI SSQ mode */
#define SQPI_MODE_SSS SQPI_MODE(1) /*!< SQPI SSS mode */
#define SQPI_MODE_SQQ SQPI_MODE(2) /*!< SQPI SQQ mode */
#define SQPI_MODE_QQQ SQPI_MODE(3) /*!< SQPI QQQ mode */
#define SQPI_MODE_SSD SQPI_MODE(4) /*!< SQPI SSD mode */
#define SQPI_MODE_SDD SQPI_MODE(5) /*!< SQPI SDD mode */
/* function declarations */
/* SQPI deinitialization and initialization functions */
/* reset SQPI */
void sqpi_deinit(void);
/* initialize the parameters of SQPI struct with the default values */
void sqpi_struct_para_init(sqpi_parameter_struct* sqpi_struct);
/* initialize SQPI parameter */
void sqpi_init(sqpi_parameter_struct *sqpi_struct);
/* send SQPI read ID command */
void sqpi_read_id_command(void);
/* send SQPI special command */
void sqpi_special_command(void);
/* configure SQPI read command */
void sqpi_read_command_config(uint32_t rmode, uint32_t rwaitcycle, uint32_t rcmd);
/* configure SQPI write command */
void sqpi_write_command_config(uint32_t wmode, uint32_t wwaitcycle, uint32_t wcmd);
/* SQPI receive low ID */
uint32_t sqpi_low_id_receive(void);
/* SQPI receive high ID*/
uint32_t sqpi_high_id_receive(void);
#endif /* GD32E50X_SQPI_H */

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/*!
\file gd32e50x_timer.h
\brief definitions for the TIMER
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_TIMER_H
#define GD32E50X_TIMER_H
#include "gd32e50x.h"
/* TIMERx(x=0..13) definitions */
#define TIMER0 (TIMER_BASE + 0x00012C00U)
#define TIMER1 (TIMER_BASE + 0x00000000U)
#define TIMER2 (TIMER_BASE + 0x00000400U)
#define TIMER3 (TIMER_BASE + 0x00000800U)
#define TIMER4 (TIMER_BASE + 0x00000C00U)
#define TIMER5 (TIMER_BASE + 0x00001000U)
#define TIMER6 (TIMER_BASE + 0x00001400U)
#define TIMER7 (TIMER_BASE + 0x00013400U)
#define TIMER8 (TIMER_BASE + 0x00014C00U)
#define TIMER9 (TIMER_BASE + 0x00015000U)
#define TIMER10 (TIMER_BASE + 0x00015400U)
#define TIMER11 (TIMER_BASE + 0x00001800U)
#define TIMER12 (TIMER_BASE + 0x00001C00U)
#define TIMER13 (TIMER_BASE + 0x00002000U)
/* registers definitions */
#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */
#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */
#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */
#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */
#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */
#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */
#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */
#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */
#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */
#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */
#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */
#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */
#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */
#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */
#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */
#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */
#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */
#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */
#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */
#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */
/* bits definitions */
/* TIMER_CTL0 */
#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */
#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */
#define TIMER_CTL0_UPS BIT(2) /*!< update source */
#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */
#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */
/* TIMER_CTL1 */
#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */
#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */
#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */
#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */
#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */
#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */
#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */
#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */
#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */
#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */
/* TIMER_SMCFG */
#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */
#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */
#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */
#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */
#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */
/* TIMER_DMAINTEN */
#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */
#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */
#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */
#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */
#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */
#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */
#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */
#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */
#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */
#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */
#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */
#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */
#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */
#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */
#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */
/* TIMER_INTF */
#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */
#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */
#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */
#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */
#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */
#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */
#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */
#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */
#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */
#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */
#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */
#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */
/* TIMER_SWEVG */
#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */
#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */
#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */
#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */
#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */
#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */
#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */
#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */
/* TIMER_CHCTL0 */
/* output compare mode */
#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */
#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */
#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */
#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */
#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */
#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */
#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */
#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */
#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */
#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */
/* input capture mode */
#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */
#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */
#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */
#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */
/* TIMER_CHCTL1 */
/* output compare mode */
#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */
#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */
#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */
#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */
#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */
#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */
#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */
#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */
#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */
#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */
/* input capture mode */
#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */
#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */
#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */
#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */
/* TIMER_CHCTL2 */
#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */
#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */
#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */
#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */
#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */
#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */
#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */
#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */
#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */
#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */
#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */
#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */
#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */
#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */
#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */
/* TIMER_CNT */
#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */
#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1) timer counter */
/* TIMER_PSC */
#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */
/* TIMER_CAR */
#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */
#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1) counter auto reload value */
/* TIMER_CREP */
#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */
/* TIMER_CH0CV */
#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */
#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 0 */
/* TIMER_CH1CV */
#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */
#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 1 */
/* TIMER_CH2CV */
#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */
#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 2 */
/* TIMER_CH3CV */
#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */
#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 3 */
/* TIMER_CCHP */
#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */
#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */
#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */
#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */
#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */
#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */
#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */
#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */
/* TIMER_DMACFG */
#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */
#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */
/* TIMER_DMATB */
#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */
/* TIMER_CFG */
#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */
#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */
/* constants definitions */
/* TIMER init parameter struct definitions */
typedef struct
{
uint16_t prescaler; /*!< prescaler value */
uint16_t alignedmode; /*!< aligned mode */
uint16_t counterdirection; /*!< counter direction */
uint32_t period; /*!< period value */
uint16_t clockdivision; /*!< clock division value */
uint8_t repetitioncounter; /*!< the counter repetition value */
}timer_parameter_struct;
/* break parameter struct definitions */
typedef struct
{
uint16_t runoffstate; /*!< run mode off-state */
uint16_t ideloffstate; /*!< idle mode off-state */
uint16_t deadtime; /*!< dead time */
uint16_t breakpolarity; /*!< break polarity */
uint16_t outputautostate; /*!< output automatic enable */
uint16_t protectmode; /*!< complementary register protect control */
uint16_t breakstate; /*!< break enable */
}timer_break_parameter_struct;
/* channel output parameter struct definitions */
typedef struct
{
uint16_t outputstate; /*!< channel output state */
uint16_t outputnstate; /*!< channel complementary output state */
uint16_t ocpolarity; /*!< channel output polarity */
uint16_t ocnpolarity; /*!< channel complementary output polarity */
uint16_t ocidlestate; /*!< idle state of channel output */
uint16_t ocnidlestate; /*!< idle state of channel complementary output */
}timer_oc_parameter_struct;
/* channel input parameter struct definitions */
typedef struct
{
uint16_t icpolarity; /*!< channel input polarity */
uint16_t icselection; /*!< channel input mode selection */
uint16_t icprescaler; /*!< channel input capture prescaler */
uint16_t icfilter; /*!< channel input capture filter control */
}timer_ic_parameter_struct;
/* TIMER interrupt enable or disable */
#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */
#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */
#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */
#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */
#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */
#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */
#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */
#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */
/* TIMER flag */
#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */
#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */
#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */
#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */
#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */
#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */
#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */
#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */
#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */
#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */
#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */
#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */
/* TIMER interrupt flag */
#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */
#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */
#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */
#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */
#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */
#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */
#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */
#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
/* TIMER DMA source enable */
#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */
#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */
#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */
#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */
#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */
/* channel DMA request source selection */
#define TIMER_DMAREQUEST_UPDATEEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when update event occurs */
#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000001U) /*!< DMA request of channel y is sent when channel y event occurs */
/* DMA access base address */
#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */
#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */
#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */
#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */
#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */
#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */
#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */
#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */
#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */
#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */
#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */
#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */
#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */
#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */
#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */
#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */
#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */
#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */
#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */
#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */
/* DMA access burst length */
#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */
#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */
#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */
#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */
#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */
#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */
#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */
#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */
#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */
#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */
#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */
#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */
#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */
#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */
#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */
#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */
#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */
#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */
/* TIMER software event generation source */
#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */
#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */
#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */
#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */
#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */
#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */
#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */
#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */
/* center-aligned mode selection */
#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */
#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */
#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */
#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */
/* TIMER prescaler reload mode */
#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */
#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */
/* count direction */
#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */
#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */
/* specify division ratio between TIMER clock and dead-time and sampling clock */
#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */
#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */
#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
/* single pulse mode */
#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */
#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */
/* update source */
#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */
#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
/* run mode off-state configure */
#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */
/* idle mode off-state configure */
#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */
/* break input polarity */
#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */
#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */
/* output automatic enable */
#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */
#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */
/* complementary register protect control */
#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */
#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */
#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */
#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */
/* break input enable */
#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */
#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */
/* TIMER channel n(n=0,1,2,3) */
#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */
#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */
#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */
#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */
/* channel enable state */
#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */
#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */
/* channel complementary output enable state */
#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */
#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */
/* channel output polarity */
#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */
#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */
/* channel complementary output polarity */
#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */
#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */
/* idle state of channel output */
#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */
#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */
/* idle state of channel complementary output */
#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */
#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */
/* channel output compare mode */
#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */
#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */
#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */
#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */
#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */
#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */
#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */
#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/
/* channel output compare shadow enable */
#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */
#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */
/* channel output compare fast enable */
#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */
#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */
/* channel output compare clear enable */
#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */
#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */
/* channel control shadow register update control */
#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */
#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
/* channel input capture polarity */
#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */
#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */
#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */
/* TIMER input capture selection */
#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */
#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */
#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */
/* channel input capture prescaler */
#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */
#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */
#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */
#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */
/* trigger selection */
#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */
#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */
#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */
#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */
#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */
#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */
#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */
#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */
/* master mode control */
#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */
#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */
#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */
#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */
#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */
#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */
#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */
/* slave mode control */
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */
#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */
#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */
/* master slave mode selection */
#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */
#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */
/* external trigger prescaler */
#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */
#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */
#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */
#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */
/* external trigger polarity */
#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */
#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */
/* channel 0 trigger input selection */
#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */
#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */
/* TIMERx(x=0,1,2,13,14,15,16) write cc register selection */
#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */
#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */
/* the output value selection */
#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */
#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */
/* function declarations */
/* TIMER timebase */
/* deinit a TIMER */
void timer_deinit(uint32_t timer_periph);
/* initialize TIMER init parameter struct */
void timer_struct_para_init(timer_parameter_struct* initpara);
/* initialize TIMER counter */
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
/* enable a TIMER */
void timer_enable(uint32_t timer_periph);
/* disable a TIMER */
void timer_disable(uint32_t timer_periph);
/* enable the auto reload shadow function */
void timer_auto_reload_shadow_enable(uint32_t timer_periph);
/* disable the auto reload shadow function */
void timer_auto_reload_shadow_disable(uint32_t timer_periph);
/* enable the update event */
void timer_update_event_enable(uint32_t timer_periph);
/* disable the update event */
void timer_update_event_disable(uint32_t timer_periph);
/* set TIMER counter alignment mode */
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
/* set TIMER counter up direction */
void timer_counter_up_direction(uint32_t timer_periph);
/* set TIMER counter down direction */
void timer_counter_down_direction(uint32_t timer_periph);
/* configure TIMER prescaler */
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload);
/* configure TIMER repetition register value */
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
/* configure TIMER autoreload register value */
void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload);
/* configure TIMER counter register value */
void timer_counter_value_config(uint32_t timer_periph , uint32_t counter);
/* read TIMER counter value */
uint32_t timer_counter_read(uint32_t timer_periph);
/* read TIMER prescaler value */
uint16_t timer_prescaler_read(uint32_t timer_periph);
/* configure TIMER single pulse mode */
void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
/* configure TIMER update source */
void timer_update_source_config(uint32_t timer_periph, uint32_t update);
/* TIMER DMA and event */
/* enable the TIMER DMA */
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
/* disable the TIMER DMA */
void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
/* channel DMA request source selection */
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request);
/* configure the TIMER DMA transfer */
void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
/* software generate events */
void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
/* TIMER channel complementary protection */
/* initialize TIMER break parameter struct */
void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
/* configure TIMER break function */
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
/* enable TIMER break function */
void timer_break_enable(uint32_t timer_periph);
/* disable TIMER break function */
void timer_break_disable(uint32_t timer_periph);
/* enable TIMER output automatic function */
void timer_automatic_output_enable(uint32_t timer_periph);
/* disable TIMER output automatic function */
void timer_automatic_output_disable(uint32_t timer_periph);
/* enable or disable TIMER primary output function */
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
/* enable or disable channel capture/compare control shadow register */
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
/* configure TIMER channel control shadow register update control */
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl);
/* TIMER channel output */
/* initialize TIMER channel output parameter struct */
void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
/* configure TIMER channel output function */
void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
/* configure TIMER channel output compare mode */
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
/* configure TIMER channel output pulse value */
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
/* configure TIMER channel output shadow function */
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
/* configure TIMER channel output fast function */
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
/* configure TIMER channel output clear function */
void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
/* configure TIMER channel output polarity */
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
/* configure TIMER channel complementary output polarity */
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
/* configure TIMER channel enable state */
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
/* configure TIMER channel complementary output enable state */
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
/* TIMER channel input */
/* initialize TIMER channel input parameter struct */
void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
/* configure TIMER input capture parameter */
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
/* configure TIMER channel input capture prescaler value */
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
/* read TIMER channel capture compare register value */
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
/* configure TIMER input pwm capture function */
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
/* configure TIMER hall sensor mode */
void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
/* TIMER master and slave mode */
/* select TIMER input trigger source */
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
/* select TIMER master mode output trigger source */
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
/* select TIMER slave mode */
void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
/* configure TIMER master slave mode */
void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
/* configure TIMER external trigger input */
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
/* configure TIMER quadrature decoder mode */
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
/* configure TIMER internal clock mode */
void timer_internal_clock_config(uint32_t timer_periph);
/* configure TIMER the internal trigger as external clock input */
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
/* configure TIMER the external trigger as external clock input */
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter);
/* configure TIMER the external clock mode 0 */
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
/* configure TIMER the external clock mode 1 */
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
/* disable TIMER the external clock mode 1 */
void timer_external_clock_mode1_disable(uint32_t timer_periph);
/* TIMER configure */
/* configure TIMER write CHxVAL register selection */
void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel);
/* configure TIMER output value selection */
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
/* TIMER interrupt and flag*/
/* get TIMER flags */
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
/* clear TIMER flags */
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
/* enable the TIMER interrupt */
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
/* disable the TIMER interrupt */
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
/* get timer interrupt flag */
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag);
/* clear TIMER interrupt flag */
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag);
#endif /* GD32E50X_TIMER_H */

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/*!
\file gd32e50x_tmu.h
\brief definitions for the TMU
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_TMU_H
#define GD32E50X_TMU_H
#include "gd32e50x.h"
/* TMU definitions */
#define TMU TMU_BASE
/* registers definitions */
#define TMU_IDATA0 REG32((TMU) + 0x00000000U) /*!< input data0 register */
#define TMU_IDATA1 REG32((TMU) + 0x00000004U) /*!< input data1 register */
#define TMU_CTL REG32((TMU) + 0x00000008U) /*!< control register */
#define TMU_DATA0 REG32((TMU) + 0x0000000CU) /*!< data0 register */
#define TMU_DATA1 REG32((TMU) + 0x00000010U) /*!< data1 register */
#define TMU_STAT REG32((TMU) + 0x00000014U) /*!< status register */
/* bits definitions */
/* TMU_IDATA0 */
#define TMU_IDATA0_IDATA0 BITS(0,31) /*!< the value of input data0 register */
/* TMU_IDATA1 */
#define TMU_IDATA1_IDATA1 BITS(0,31) /*!< the value of input data1 register */
/* TMU_CTL */
#define TMU_CTL_TMUEN BIT(0) /*!< start TMU calculation */
#define TMU_CTL_MODE BITS(1,4) /*!< the mode of TMU */
#define TMU_CTL_CFIE BIT(5) /*!< enable calculation finishes interrupt */
#define TMU_CTL_CFIF BIT(6) /*!< the flag of calculation finishes interrupt */
/* TMU_DATA0 */
#define TMU_DATA0_DATA0 BITS(0,31) /*!< the value of data0 register */
/* TMU_DATA0 */
#define TMU_DATA1_DATA1 BITS(0,31) /*!< the value of data1 register */
/* TMU_STAT */
#define TMU_STAT_OVRF BIT(0) /*!< the status of overflow */
#define TMU_STAT_UDRF BIT(1) /*!< the status of underflow */
/* constants definitions */
/* TMU mode definitions */
#define TMU_MODE(regval) (BITS(1,4) & ((uint32_t)(regval) << 1))
#define TMU_MODE0 TMU_MODE(0) /*!< the mode0 of TMU */
#define TMU_MODE1 TMU_MODE(1) /*!< the mode1 of TMU */
#define TMU_MODE2 TMU_MODE(2) /*!< the mode2 of TMU */
#define TMU_MODE3 TMU_MODE(3) /*!< the mode3 of TMU */
#define TMU_MODE4 TMU_MODE(4) /*!< the mode4 of TMU */
#define TMU_MODE5 TMU_MODE(5) /*!< the mode5 of TMU */
#define TMU_MODE6 TMU_MODE(6) /*!< the mode6 of TMU */
#define TMU_MODE7 TMU_MODE(7) /*!< the mode7 of TMU */
#define TMU_MODE8 TMU_MODE(8) /*!< the mode8 of TMU */
/* TMU interrupt flag definitions */
#define TMU_INT_FLAG_CFIF TMU_CTL_CFIF /*!< the interrupt flag of calculation finished */
/* TMU flag definitions */
#define TMU_FLAG_OVRF TMU_STAT_OVRF /*!< the flag of TMU overflow */
#define TMU_FLAG_UDRF TMU_STAT_UDRF /*!< the flag of TMU underflow */
/* function declarations */
/* TMU deinitialization and initialization functions */
/* reset the TMU */
void tmu_deinit(void);
/* enable the TMU */
void tmu_enable(void);
/* configure the TMU calculation */
/* configure the TMU mode */
void tmu_mode_set(uint32_t modex);
/* write the data to TMU input data0 regisetr */
void tmu_idata0_write(uint32_t idata0);
/* write the data to TMU input data1 regisetr */
void tmu_idata1_write(uint32_t idata1);
/* read the data from TMU data0 regisetr */
uint32_t tmu_data0_read(void);
/* read the data from TMU data1 regisetr */
uint32_t tmu_data1_read(void);
/* flag and interrupt functions */
/* enable TTMU interrupt */
void tmu_interrupt_enable(void);
/* disable TTMU interrupt */
void tmu_interrupt_disable(void);
/* check teh TMU status flag */
FlagStatus tmu_flag_get(uint32_t flag);
/* check teh TMU interrupt flag */
FlagStatus tmu_interrupt_flag_get(uint32_t int_flag);
#endif /* GD32E50X_TMU_H */

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/*!
\file gd32e50x_usart.h
\brief definitions for the USART
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_USART_H
#define GD32E50X_USART_H
#include "gd32e50x.h"
/* USARTx(x=0,1,2,5)/UARTx(x=3,4) definitions */
#define USART1 USART_BASE /*!< USART1 base address */
#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */
#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */
#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */
#define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */
#define USART5 (USART_BASE+0x00012C00U) /*!< USART5 base address */
/* USART registers definitions */
/* USARTx(x=0,1,2)/UARTx(x=3,4)registers definitions */
#define USART_STAT0(usartx) REG32((usartx) + 0x000000000U) /*!< USART status register 0 */
#define USART_DATA(usartx) REG32((usartx) + 0x000000004U) /*!< USART data register */
#define USART_BAUD(usartx) REG32((usartx) + 0x000000008U) /*!< USART baud rate register */
#define USART_CTL0(usartx) REG32((usartx) + 0x00000000CU) /*!< USART control register 0 */
#define USART_CTL1(usartx) REG32((usartx) + 0x000000010U) /*!< USART control register 1 */
#define USART_CTL2(usartx) REG32((usartx) + 0x000000014U) /*!< USART control register 2 */
#define USART_GP(usartx) REG32((usartx) + 0x000000018U) /*!< USART guard time and prescaler register */
#define USART_CTL3(usartx) REG32((usartx) + 0x000000080U) /*!< USART control register 3 */
#define USART_RT(usartx) REG32((usartx) + 0x000000084U) /*!< USART receiver timeout register */
#define USART_STAT1(usartx) REG32((usartx) + 0x000000088U) /*!< USART status register 1 */
#define USART_GDCTL(usartx) REG32((usartx) + 0x0000000D0U) /*!< USART GD control register */
/* USART5 registers definitions */
#define USART5_CTL0(usartx) REG32((usartx) + 0x000000000U) /*!< USART5 control register 0 */
#define USART5_CTL1(usartx) REG32((usartx) + 0x000000004U) /*!< USART5 control register 1 */
#define USART5_CTL2(usartx) REG32((usartx) + 0x000000008U) /*!< USART5 control register 2 */
#define USART5_BAUD(usartx) REG32((usartx) + 0x00000000CU) /*!< USART5 baud rate register */
#define USART5_GP(usartx) REG32((usartx) + 0x000000010U) /*!< USART5 guard time and prescaler register */
#define USART5_RT(usartx) REG32((usartx) + 0x000000014U) /*!< USART5 receiver timeout register */
#define USART5_CMD(usartx) REG32((usartx) + 0x000000018U) /*!< USART5 command register */
#define USART5_STAT(usartx) REG32((usartx) + 0x00000001CU) /*!< USART5 status register */
#define USART5_INTC(usartx) REG32((usartx) + 0x000000020U) /*!< USART5 interrupt status clear register */
#define USART5_RDATA(usartx) REG32((usartx) + 0x000000024U) /*!< USART5 receive data register */
#define USART5_TDATA(usartx) REG32((usartx) + 0x000000028U) /*!< USART5 transmit data register */
#define USART5_CHC(usartx) REG32((usartx) + 0x0000000C0U) /*!< USART5 coherence control register */
#define USART5_RFCS(usartx) REG32((usartx) + 0x0000000D0U) /*!< USART5 receive FIFO control and status register */
/* USART bits definitions */
/* USARTx(x=0,1,2)/UARTx(x=3,4) bits definitions */
/* USARTx_STAT0 */
#define USART_STAT0_PERR BIT(0) /*!< parity error flag */
#define USART_STAT0_FERR BIT(1) /*!< frame error flag */
#define USART_STAT0_NERR BIT(2) /*!< noise error flag */
#define USART_STAT0_ORERR BIT(3) /*!< overrun error */
#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */
#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */
#define USART_STAT0_TC BIT(6) /*!< transmission complete */
#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */
#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */
#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */
/* USARTx_DATA */
#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */
/* USARTx_BAUD */
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */
/* USARTx_CTL0 */
#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
#define USART_CTL0_REN BIT(2) /*!< receiver enable */
#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */
#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
#define USART_CTL0_PM BIT(9) /*!< parity mode */
#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
#define USART_CTL0_WL BIT(12) /*!< word length */
#define USART_CTL0_UEN BIT(13) /*!< USART enable */
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
/* USARTx_CTL1 */
#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */
#define USART_CTL1_CLEN BIT(8) /*!< CK length */
#define USART_CTL1_CPH BIT(9) /*!< CK phase */
#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */
#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
/* USARTx_CTL2 */
#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */
#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */
#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */
#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */
/* USARTx_GP */
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
/* USARTx_CTL3 */
#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */
#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */
#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */
#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */
#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */
#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */
#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */
#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */
/* USARTx_RT */
#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
#define USART_RT_BL BITS(24,31) /*!< block length */
/* USARTx_STAT1 */
#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */
#define USART_STAT1_EBF BIT(12) /*!< end of block flag */
#define USART_STAT1_BSY BIT(16) /*!< busy flag */
/* USARTx_GDCR */
#define USART_GDCTL_CDEN BIT(1) /*!< collision detection enable */
#define USART_GDCTL_CD BIT(8) /*!< collision detected status */
#define USART_GDCTL_CDIE BIT(16) /*!< collision detected interrupt enable */
/* USART5 bits definitions */
/* USART5_CTL0 */
#define USART5_CTL0_UEN BIT(0) /*!< USART5 enable */
#define USART5_CTL0_UESM BIT(1) /*!< USART5 enable in Deep-sleep mode */
#define USART5_CTL0_REN BIT(2) /*!< receiver enable */
#define USART5_CTL0_TEN BIT(3) /*!< transmitter enable */
#define USART5_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
#define USART5_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
#define USART5_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
#define USART5_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */
#define USART5_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
#define USART5_CTL0_PM BIT(9) /*!< parity mode */
#define USART5_CTL0_PCEN BIT(10) /*!< parity check function enable */
#define USART5_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
#define USART5_CTL0_WL BIT(12) /*!< word length */
#define USART5_CTL0_MEN BIT(13) /*!< mute mode enable */
#define USART5_CTL0_AMIE BIT(14) /*!< ADDR match interrupt enable */
#define USART5_CTL0_OVSMOD BIT(15) /*!< oversample mode */
#define USART5_CTL0_DED BITS(16,20) /*!< driver enable de-assertion time */
#define USART5_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */
#define USART5_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */
#define USART5_CTL0_EBIE BIT(27) /*!< End of Block interrupt enable */
/* USART5_CTL1 */
#define USART5_CTL1_ADDM BIT(4) /*!< address detection mode */
#define USART5_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
#define USART5_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */
#define USART5_CTL1_CLEN BIT(8) /*!< last bit clock pulse */
#define USART5_CTL1_CPH BIT(9) /*!< clock phase */
#define USART5_CTL1_CPL BIT(10) /*!< clock polarity */
#define USART5_CTL1_CKEN BIT(11) /*!< ck pin enable */
#define USART5_CTL1_STB BITS(12,13) /*!< stop bits length */
#define USART5_CTL1_LMEN BIT(14) /*!< LIN mode enable */
#define USART5_CTL1_STRP BIT(15) /*!< swap TX/RX pins */
#define USART5_CTL1_RINV BIT(16) /*!< RX pin level inversion */
#define USART5_CTL1_TINV BIT(17) /*!< TX pin level inversion */
#define USART5_CTL1_DINV BIT(18) /*!< data bit level inversion */
#define USART5_CTL1_MSBF BIT(19) /*!< most significant bit first */
#define USART5_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */
#define USART5_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */
#define USART5_CTL1_RTEN BIT(23) /*!< receiver timeout enable */
#define USART5_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */
/* USART5_CTL2 */
#define USART5_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */
#define USART5_CTL2_IREN BIT(1) /*!< IrDA mode enable */
#define USART5_CTL2_IRLP BIT(2) /*!< IrDA low-power */
#define USART5_CTL2_HDEN BIT(3) /*!< half-duplex enable */
#define USART5_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
#define USART5_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
#define USART5_CTL2_DENR BIT(6) /*!< DMA enable for reception */
#define USART5_CTL2_DENT BIT(7) /*!< DMA enable for transmission */
#define USART5_CTL2_RTSEN BIT(8) /*!< RTS enable */
#define USART5_CTL2_CTSEN BIT(9) /*!< CTS enable */
#define USART5_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
#define USART5_CTL2_OSB BIT(11) /*!< one sample bit mode */
#define USART5_CTL2_OVRD BIT(12) /*!< overrun disable */
#define USART5_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */
#define USART5_CTL2_DEM BIT(14) /*!< driver enable mode */
#define USART5_CTL2_DEP BIT(15) /*!< driver enable polarity mode */
#define USART5_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */
#define USART5_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */
#define USART5_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */
/* USART5_BAUD */
#define USART5_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */
#define USART5_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */
/* USART5_GP */
#define USART5_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
#define USART5_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
/* USART5_RT */
#define USART5_RT_RT BITS(0,23) /*!< receiver timeout threshold */
#define USART5_RT_BL BITS(24,31) /*!< block length */
/* USART5_CMD */
#define USART5_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */
#define USART5_CMD_SBKCMD BIT(1) /*!< send break command */
#define USART5_CMD_MMCMD BIT(2) /*!< mute mode command */
#define USART5_CMD_RXFCMD BIT(3) /*!< receive data flush command */
#define USART5_CMD_TXFCMD BIT(4) /*!< transmit data flush request */
/* USART5_STAT */
#define USART5_STAT_PERR BIT(0) /*!< parity error flag */
#define USART5_STAT_FERR BIT(1) /*!< frame error flag */
#define USART5_STAT_NERR BIT(2) /*!< noise error flag */
#define USART5_STAT_ORERR BIT(3) /*!< overrun error */
#define USART5_STAT_IDLEF BIT(4) /*!< idle line detected flag */
#define USART5_STAT_RBNE BIT(5) /*!< read data buffer not empty */
#define USART5_STAT_TC BIT(6) /*!< transmission completed */
#define USART5_STAT_TBE BIT(7) /*!< transmit data register empty */
#define USART5_STAT_LBDF BIT(8) /*!< LIN break detected flag */
#define USART5_STAT_CTSF BIT(9) /*!< CTS change flag */
#define USART5_STAT_CTS BIT(10) /*!< CTS level */
#define USART5_STAT_RTF BIT(11) /*!< receiver timeout flag */
#define USART5_STAT_EBF BIT(12) /*!< end of block flag */
#define USART5_STAT_ABDE BIT(14) /*!< auto baudrate detection error */
#define USART5_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */
#define USART5_STAT_BSY BIT(16) /*!< busy flag */
#define USART5_STAT_AMF BIT(17) /*!< address match flag */
#define USART5_STAT_SBF BIT(18) /*!< send break flag */
#define USART5_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */
#define USART5_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */
#define USART5_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */
#define USART5_STAT_REA BIT(22) /*!< receive enable acknowledge flag */
/* USART5_INTC */
#define USART5_INTC_PEC BIT(0) /*!< parity error clear */
#define USART5_INTC_FEC BIT(1) /*!< frame error flag clear */
#define USART5_INTC_NEC BIT(2) /*!< noise detected clear */
#define USART5_INTC_OREC BIT(3) /*!< overrun error clear */
#define USART5_INTC_IDLEC BIT(4) /*!< idle line detected clear */
#define USART5_INTC_TCC BIT(6) /*!< transmission complete clear */
#define USART5_INTC_LBDC BIT(8) /*!< LIN break detected clear */
#define USART5_INTC_CTSC BIT(9) /*!< CTS change clear */
#define USART5_INTC_RTC BIT(11) /*!< receiver timeout clear */
#define USART5_INTC_EBC BIT(12) /*!< end of timeout clear */
#define USART5_INTC_AMC BIT(17) /*!< address match clear */
#define USART5_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */
/* USART5_RDATA */
#define USART5_RDATA_RDATA BITS(0,8) /*!< receive data value */
/* USART5_TDATA */
#define USART5_TDATA_TDATA BITS(0,8) /*!< transmit data value */
/* USART5_CHC */
#define USART5_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */
#define USART5_CHC_EPERR BIT(8) /*!< early parity error flag */
/* USART5_RFCS */
#define USART5_RFCS_ELNACK BIT(0) /*!< early NACK */
#define USART5_RFCS_RFEN BIT(8) /*!< receive FIFO enable */
#define USART5_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */
#define USART5_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */
#define USART5_RFCS_RFF BIT(11) /*!< receive FIFO full flag */
#define USART5_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */
#define USART5_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */
/* USARTx(x=0,1,2,5)/UARTx(x=3,4) constants definitions */
/* define the USART bit position and its register index offset */
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
/* USART register offset */
/* USARTx(x=0,1,2)/UARTx(x=3,4) register offset */
#define USART_STAT0_REG_OFFSET 0x00000000U /*!< STAT0 register offset */
#define USART_STAT1_REG_OFFSET 0x00000088U /*!< STAT1 register offset */
#define USART_CTL0_REG_OFFSET 0x0000000CU /*!< CTL0 register offset */
#define USART_CTL1_REG_OFFSET 0x00000010U /*!< CTL1 register offset */
#define USART_CTL2_REG_OFFSET 0x00000014U /*!< CTL2 register offset */
#define USART_CTL3_REG_OFFSET 0x00000080U /*!< CTL3 register offset */
#define USART_GDCTL_REG_OFFSET 0x000000D0U /*!< GDCTL register offset */
/* USART5 register offset */
#define USART5_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */
#define USART5_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */
#define USART5_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */
#define USART5_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */
#define USART5_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */
#define USART5_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */
/* USART flag definitions */
/* USARTx(x=0,1,2)/UARTx(x=3,4) flags */
typedef enum
{
/* flags in STAT0 register */
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */
USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error flag*/
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */
/* flags in STAT1 register */
USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */
USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */
USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */
/* flags in GDCTL register */
USART_FLAG_CD = USART_REGIDX_BIT(USART_GDCTL_REG_OFFSET, 8U), /*!< collision detected flag */
}usart_flag_enum;
/* USART5 flags */
typedef enum
{
/* flags in STAT register */
USART5_FLAG_REA = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */
USART5_FLAG_TEA = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */
USART5_FLAG_WU = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */
USART5_FLAG_RWU = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */
USART5_FLAG_SB = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 18U), /*!< send break flag */
USART5_FLAG_AM = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */
USART5_FLAG_BSY = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 16U), /*!< busy flag */
USART5_FLAG_ABD = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */
USART5_FLAG_ABDE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */
USART5_FLAG_EB = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 12U), /*!< end of block flag */
USART5_FLAG_RT = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */
USART5_FLAG_CTS = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 10U), /*!< CTS level */
USART5_FLAG_CTSF = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
USART5_FLAG_LBD = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
USART5_FLAG_TBE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
USART5_FLAG_TC = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 6U), /*!< transmission complete */
USART5_FLAG_RBNE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
USART5_FLAG_IDLE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */
USART5_FLAG_ORERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 3U), /*!< overrun error */
USART5_FLAG_NERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 2U), /*!< noise error flag */
USART5_FLAG_FERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 1U), /*!< frame error flag */
USART5_FLAG_PERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 0U), /*!< parity error flag */
/* flags in CHC register */
USART5_FLAG_EPERR = USART_REGIDX_BIT(USART5_CHC_REG_OFFSET, 8U), /*!< early parity error flag */
/* flags in RFCS register */
USART5_FLAG_RFFINT = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */
USART5_FLAG_RFF = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */
USART5_FLAG_RFE = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */
}usart5_flag_enum;
/* USART interrupt flags */
/* USARTx(x=0,1,2)/UARTx(x=3,4) interrupt flags */
typedef enum
{
/* interrupt flags in CTL0 register */
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
/* interrupt flags in CTL1 register */
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
/* interrupt flags in CTL2 register */
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
/* interrupt flags in CTL3 register */
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */
USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */
/* interrupt flags in GDCTL register */
USART_INT_FLAG_CD = USART_REGIDX_BIT2(USART_GDCTL_REG_OFFSET, 16U, USART_GDCTL_REG_OFFSET, 8U), /*!< collision detected interrupt and flag */
}usart_interrupt_flag_enum;
/* USART5 interrupt flags */
typedef enum
{
/* interrupt flags in CTL0 register */
USART5_INT_FLAG_EB = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 27U, USART5_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */
USART5_INT_FLAG_RT = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 26U, USART5_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */
USART5_INT_FLAG_AM = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 14U, USART5_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */
USART5_INT_FLAG_PERR = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 8U, USART5_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
USART5_INT_FLAG_TBE = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 7U, USART5_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
USART5_INT_FLAG_TC = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 6U, USART5_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
USART5_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 5U, USART5_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
USART5_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 5U, USART5_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
USART5_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 4U, USART5_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
/* interrupt flags in CTL1 register */
USART5_INT_FLAG_LBD = USART_REGIDX_BIT2(USART5_CTL1_REG_OFFSET, 6U, USART5_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
/* interrupt flags in CTL2 register */
USART5_INT_FLAG_WU = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 22U, USART5_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */
USART5_INT_FLAG_CTS = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 10U, USART5_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
USART5_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 0U, USART5_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
USART5_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 0U, USART5_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error flag */
USART5_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 0U, USART5_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
/* interrupt flags in RFCS register */
USART5_INT_FLAG_RFF = USART_REGIDX_BIT2(USART5_RFCS_REG_OFFSET, 9U, USART5_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */
}usart5_interrupt_flag_enum;
/* USART interrupt enable or disable */
/* USARTx(x=0,1,2)/UARTx(x=3,4) interrupt enable or disable */
typedef enum
{
/* interrupt in CTL0 register */
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
/* interrupt in CTL1 register */
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
/* interrupt in CTL2 register */
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
/* interrupt in CTL3 register */
USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */
USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */
/* interrupt in GDCTL register */
USART_INT_CD = USART_REGIDX_BIT(USART_GDCTL_REG_OFFSET, 16U), /*!< collision detected interrupt */
}usart_interrupt_enum;
/* USART5 interrupt enable or disable */
typedef enum
{
/* interrupt in CTL0 register */
USART5_INT_EB = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */
USART5_INT_RT = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */
USART5_INT_AM = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */
USART5_INT_PERR = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
USART5_INT_TBE = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
USART5_INT_TC = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
USART5_INT_RBNE = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
USART5_INT_IDLE = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
/* interrupt in CTL1 register */
USART5_INT_LBD = USART_REGIDX_BIT(USART5_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
/* interrupt in CTL2 register */
USART5_INT_WU = USART_REGIDX_BIT(USART5_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */
USART5_INT_CTS = USART_REGIDX_BIT(USART5_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
USART5_INT_ERR = USART_REGIDX_BIT(USART5_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
/* interrupt in RFCS register */
USART5_INT_RFF = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */
}usart5_interrupt_enum;
/* USART invert configure */
/* USARTx(x=0,1,2)/UARTx(x=3,4) invert configure */
typedef enum
{
/* data bit level inversion */
USART_DINV_ENABLE, /*!< data bit level inversion */
USART_DINV_DISABLE, /*!< data bit level not inversion */
/* TX pin level inversion */
USART_TXPIN_ENABLE, /*!< TX pin level inversion */
USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
/* RX pin level inversion */
USART_RXPIN_ENABLE, /*!< RX pin level inversion */
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
}usart_invert_enum;
/* USART5 invert configure */
typedef enum
{
/* data bit level inversion */
USART5_DINV_ENABLE, /*!< data bit level inversion */
USART5_DINV_DISABLE, /*!< data bit level not inversion */
/* TX pin level inversion */
USART5_TXPIN_ENABLE, /*!< TX pin level inversion */
USART5_TXPIN_DISABLE, /*!< TX pin level not inversion */
/* RX pin level inversion */
USART5_RXPIN_ENABLE, /*!< RX pin level inversion */
USART5_RXPIN_DISABLE, /*!< RX pin level not inversion */
/* swap TX/RX pins */
USART5_SWAP_ENABLE, /*!< swap TX/RX pins */
USART5_SWAP_DISABLE, /*!< not swap TX/RX pins */
}usart5_invert_enum;
/* USART bits configure */
/* USARTx(x=1,2,5)/UARTx(X=3,4) bits configure*/
/* USART receiver configure */
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
/* USART transmitter configure */
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
/* USART parity bits definitions */
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
/* USART wakeup method in mute mode */
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */
#define USART_WM_ADDR CTL0_WM(1) /*!< address mask */
/* USART word length definitions */
#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
/* USART oversampling mode definitions */
#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */
#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */
/* USART LIN break frame length */
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */
/* USART CK length */
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
/* USART clock phase */
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
/* USART clock polarity */
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
/* USART stop bits definitions */
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
/* USART IrDA low-power enable */
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
/* USART DMA request for receive configure */
#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */
#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */
/* USART DMA request for transmission configure */
#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */
#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */
/* USART RTS configure */
#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */
#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */
/* USART CTS configure */
#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */
#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */
/* USART one sample bit method configure */
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */
#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */
/* USARTx(x=0,1,2)/UARTx(x=3,4) bits configure*/
/* USART data is transmitted/received with the LSB/MSB first */
#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11))
#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */
#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */
/* USART collision detection enable */
#define GDCR_CDEN(regval) (BIT(1) & ((uint32_t)(regval) << 1))
#define USART_CDEN_ENABLE GDCR_CDEN(1) /*!< collision detection enable */
#define USART_CDEN_DISABLE GDCR_CDEN(0) /*!< collision detection disable */
/* USART collision detected interrupt enable */
#define GDCR_CDIE(regval) (BIT(16) & ((uint32_t)(regval) << 16))
#define USART_CDIE_ENABLE GDCR_CDIE(1) /*!< collision detected interrupt ensable */
#define USART_CDIE_DISABLE GDCR_CDIE(0) /*!< collision detected interrupt disable */
/* USART5 bits configure */
/* USART5 address detection mode */
#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4))
#define USART5_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */
#define USART5_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */
/* USART5 data is transmitted/received with the LSB/MSB first */
#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
#define USART5_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */
#define USART5_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */
/* USART5 auto baud rate detection mode bits definitions */
#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
#define USART5_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */
#define USART5_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */
/* USART5 driver enable polarity mode */
#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
#define USART5_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */
#define USART5_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */
/* USART5 wakeup mode from deep-sleep mode */
#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
#define USART5_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */
#define USART5_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */
#define USART5_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */
/* USART5 hardware flow control coherence mode */
#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0))
#define USART5_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */
#define USART5_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */
/* USARTx(x=0,1,2,5)/UARTx(x=3,4) function declarations */
/* initialization functions */
/* reset USART */
void usart_deinit(uint32_t usart_periph);
/* configure usart baud rate value */
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
/* configure usart parity function */
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
/* configure usart word length */
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
/* configure usart stop bit length */
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
/* enable usart */
void usart_enable(uint32_t usart_periph);
/* disable usart */
void usart_disable(uint32_t usart_periph);
/* configure USART transmitter */
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
/* configure USART receiver */
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
/* normal mode communication */
/* configure the USART oversample mode */
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
/* configure sample bit method */
void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm);
/* enable receiver timeout */
void usart_receiver_timeout_enable(uint32_t usart_periph);
/* disable receiver timeout */
void usart_receiver_timeout_disable(uint32_t usart_periph);
/* configure receiver timeout threshold */
void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
/* USART transmit data function */
void usart_data_transmit(uint32_t usart_periph, uint32_t data);
/* USART receive data function */
uint16_t usart_data_receive(uint32_t usart_periph);
/* multi-processor communication */
/* enable mute mode */
void usart_mute_mode_enable(uint32_t usart_periph);
/* disable mute mode */
void usart_mute_mode_disable(uint32_t usart_periph);
/* configure wakeup method in mute mode */
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
/* LIN mode communication */
/* enable LIN mode */
void usart_lin_mode_enable(uint32_t usart_periph);
/* disable LIN mode */
void usart_lin_mode_disable(uint32_t usart_periph);
/* LIN break detection length */
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
/* half-duplex communication */
/* enable half-duplex mode */
void usart_halfduplex_enable(uint32_t usart_periph);
/* disable half-duplex mode */
void usart_halfduplex_disable(uint32_t usart_periph);
/* synchronous communication */
/* enable CK pin in synchronous mode */
void usart_synchronous_clock_enable(uint32_t usart_periph);
/* disable CK pin in synchronous mode */
void usart_synchronous_clock_disable(uint32_t usart_periph);
/* configure usart synchronous mode parameters */
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
/* smartcard communication */
/* configure guard time value in smartcard mode */
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
/* enable smartcard mode */
void usart_smartcard_mode_enable(uint32_t usart_periph);
/* disable smartcard mode */
void usart_smartcard_mode_disable(uint32_t usart_periph);
/* enable NACK in smartcard mode */
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
/* disable NACK in smartcard mode */
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
/* configure smartcard auto-retry number */
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
/* configure block length */
void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
/* IrDA communication */
/* enable IrDA mode */
void usart_irda_mode_enable(uint32_t usart_periph);
/* disable IrDA mode */
void usart_irda_mode_disable(uint32_t usart_periph);
/* configure the peripheral clock prescaler */
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
/* configure IrDA low-power */
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
/* hardware flow communication */
/* configure hardware flow control RTS */
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
/* configure hardware flow control CTS */
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
/* DMA communication */
/* configure USART DMA for reception */
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
/* configure USART DMA for transmission */
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
/* USARTx(x=0,1,2)/UARTx(x=3,4) function declarations */
/* normal mode communication */
/* data is transmitted/received with the LSB/MSB first */
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
/* configure USART inverted */
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
/* multi-processor communication */
/* configure address of the USART */
void usart_address_config(uint32_t usart_periph, uint8_t addr);
/* LIN mode communication */
/* send break frame */
void usart_send_break(uint32_t usart_periph);
/* collision detected control */
/* enable collision detected interrupt */
void usart_collision_detected_interrupt_enable(uint32_t usart_periph);
/* disable collision detected interrupt */
void usart_collision_detected_interrupt_disable(uint32_t usart_periph);
/* enable collision detection */
void usart_collision_detection_enable(uint32_t usart_periph);
/* disable collision detection */
void usart_collision_detection_disable(uint32_t usart_periph);
/* flag & interrupt functions */
/* get flag in STAT0/STAT1 register */
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
/* clear flag in STAT0/STAT1 register */
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
/* enable USART interrupt */
void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
/* disable USART interrupt */
void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
/* get USART interrupt and flag status */
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
/* clear interrupt flag in STAT0/STAT1 register */
void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
/* USART5 function declarations */
/* normal mode communication */
/* data is transmitted/received with the LSB/MSB first */
void usart5_data_first_config(uint32_t usart_periph, uint32_t msbf);
/* configure USART5 inverted */
void usart5_invert_config(uint32_t usart_periph, usart5_invert_enum invertpara);
/* enable the USART5 overrun function */
void usart5_overrun_enable(uint32_t usart_periph);
/* disable the USART5 overrun function */
void usart5_overrun_disable(uint32_t usart_periph);
/* auto baud rate detection */
/* enable auto baud rate detection */
void usart5_autobaud_detection_enable(uint32_t usart_periph);
/* disable auto baud rate detection */
void usart5_autobaud_detection_disable(uint32_t usart_periph);
/* configure auto baud rate detection mode */
void usart5_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod);
/* multi-processor communication */
/* configure address of the USART5 */
void usart5_address_config(uint32_t usart_periph, uint8_t addr);
/* configure address detection mode */
void usart5_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
/* smartcard communication */
/* enable early NACK in smartcard mode */
void usart5_smartcard_mode_early_nack_enable(uint32_t usart_periph);
/* disable early NACK in smartcard mode */
void usart5_smartcard_mode_early_nack_disable(uint32_t usart_periph);
/* coherence control */
/* configure hardware flow control coherence mode */
void usart5_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm);
/* enable RS485 driver */
void usart5_rs485_driver_enable(uint32_t usart_periph);
/* disable RS485 driver */
void usart5_rs485_driver_disable(uint32_t usart_periph);
/* configure driver enable assertion time */
void usart5_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
/* configure driver enable de-assertion time */
void usart5_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
/* configure driver enable polarity mode */
void usart5_depolarity_config(uint32_t usart_periph, uint32_t dep);
/* DMA communication */
/* enable DMA on reception error */
void usart5_reception_error_dma_enable(uint32_t usart_periph);
/* disable DMA on reception error */
void usart5_reception_error_dma_disable(uint32_t usart_periph);
/* enable USART to wakeup the mcu from deep-sleep mode */
void usart5_wakeup_enable(uint32_t usart_periph);
/* disable USART to wakeup the mcu from deep-sleep mode */
void usart5_wakeup_disable(uint32_t usart_periph);
/* configure the USART wakeup mode from deep-sleep mode */
void usart5_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
/* USART5 receive FIFO */
/* enable receive FIFO */
void usart5_receive_fifo_enable(uint32_t usart_periph);
/* disable receive FIFO */
void usart5_receive_fifo_disable(uint32_t usart_periph);
/* read receive FIFO counter number */
uint8_t usart5_receive_fifo_counter_number(uint32_t usart_periph);
/* flag & interrupt functions */
/* get flag in STAT/RFCS register */
FlagStatus usart5_flag_get(uint32_t usart_periph, usart5_flag_enum flag);
/* clear USART status */
void usart5_flag_clear(uint32_t usart_periph, usart5_flag_enum flag);
/* enable USART interrupt */
void usart5_interrupt_enable(uint32_t usart_periph, usart5_interrupt_enum interrupt);
/* disable USART interrupt */
void usart5_interrupt_disable(uint32_t usart_periph, usart5_interrupt_enum interrupt);
/* enable USART command */
void usart5_command_enable(uint32_t usart_periph, uint32_t cmdtype);
/* get USART interrupt and flag status */
FlagStatus usart5_interrupt_flag_get(uint32_t usart_periph, usart5_interrupt_flag_enum int_flag);
/* clear USART interrupt flag */
void usart5_interrupt_flag_clear(uint32_t usart_periph, usart5_interrupt_flag_enum int_flag);
#endif /* GD32E50X_USART_H */

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/*!
\file gd32e50x_wwdgt.h
\brief definitions for the WWDGT
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_WWDGT_H
#define GD32E50X_WWDGT_H
#include "gd32e50x.h"
/* WWDGT definitions */
#define WWDGT WWDGT_BASE
/* registers definitions */
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
/* bits definitions */
/* WWDGT_CTL */
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
/* WWDGT_CFG */
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
/* WWDGT_STAT */
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
/* constants definitions */
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
/* function declarations */
/* reset the WWDGT configuration */
void wwdgt_deinit(void);
/* start the WWDGT counter */
void wwdgt_enable(void);
/* configure the WWDGT counter value */
void wwdgt_counter_update(uint16_t counter_value);
/* configure counter value, window value, and prescaler divider value */
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
/* enable early wakeup interrupt of WWDGT */
void wwdgt_interrupt_enable(void);
/* check early wakeup interrupt state of WWDGT */
FlagStatus wwdgt_flag_get(void);
/* clear early wakeup interrupt state of WWDGT */
void wwdgt_flag_clear(void);
#endif /* GD32E50X_WWDGT_H */

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/*!
\file gd32e50x_bkp.c
\brief BKP driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_bkp.h"
#define TAMPER_FLAG_SHIFT ((uint8_t)0x08U)
/*!
\brief reset BKP registers
\param[in] none
\param[out] none
\retval none
*/
void bkp_deinit(void)
{
/* reset BKP domain register */
rcu_bkp_reset_enable();
rcu_bkp_reset_disable();
}
/*!
\brief write BKP data register
\param[in] register_number: refer to bkp_data_register_enum
only one parameter can be selected which is shown as below:
\arg BKP_DATA_x(x = 0..41): BKP data register number x
\param[in] data: the data to be write in BKP data register
\param[out] none
\retval none
*/
void bkp_write_data(bkp_data_register_enum register_number, uint16_t data)
{
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
BKP_DATA10_41(register_number-1U) = data;
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
BKP_DATA0_9(register_number-1U) = data;
}else{
/* illegal parameters */
}
}
/*!
\brief read BKP data register
\param[in] register_number: refer to bkp_data_register_enum
only one parameter can be selected which is shown as below:
\arg BKP_DATA_x(x = 0..41): BKP data register number x
\param[out] none
\retval data of BKP data register
*/
uint16_t bkp_read_data(bkp_data_register_enum register_number)
{
uint16_t data = 0U;
/* get the data from the BKP data register */
if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
data = BKP_DATA10_41(register_number-1U);
}else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
data = BKP_DATA0_9(register_number-1U);
}else{
/* illegal parameters */
}
return data;
}
/*!
\brief enable RTC clock calibration output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_calibration_output_enable(void)
{
BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
}
/*!
\brief disable RTC clock calibration output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_calibration_output_disable(void)
{
BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
}
/*!
\brief enable RTC alarm or second signal output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_signal_output_enable(void)
{
BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
}
/*!
\brief disable RTC alarm or second signal output
\param[in] none
\param[out] none
\retval none
*/
void bkp_rtc_signal_output_disable(void)
{
BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
}
/*!
\brief select RTC output
\param[in] outputsel: RTC output selection
only one parameter can be selected which is shown as below:
\arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
\arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
\param[out] none
\retval none
*/
void bkp_rtc_output_select(uint16_t outputsel)
{
uint16_t ctl = 0U;
ctl = BKP_OCTL;
ctl &= (uint16_t)~BKP_OCTL_ROSEL;
ctl |= outputsel;
BKP_OCTL = ctl;
}
/*!
\brief select RTC clock output
\param[in] clocksel: RTC clock output selection
only one parameter can be selected which is shown as below:
\arg RTC_CLOCK_DIV_64: RTC clock div 64
\arg RTC_CLOCK_DIV_1: RTC clock
\param[out] none
\retval none
*/
void bkp_rtc_clock_output_select(uint16_t clocksel)
{
uint16_t ctl = 0U;
ctl = BKP_OCTL;
ctl &= (uint16_t)~BKP_OCTL_CCOSEL;
ctl |= clocksel;
BKP_OCTL = ctl;
}
/*!
\brief RTC clock calibration direction
\param[in] direction: RTC clock calibration direction
only one parameter can be selected which is shown as below:
\arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down
\arg RTC_CLOCK_SPEED_UP: RTC clock speed up
\param[out] none
\retval none
*/
void bkp_rtc_clock_calibration_direction(uint16_t direction)
{
uint16_t ctl = 0U;
ctl = BKP_OCTL;
ctl &= (uint16_t)~BKP_OCTL_CALDIR;
ctl |= direction;
BKP_OCTL = ctl;
}
/*!
\brief set RTC clock calibration value
\param[in] value: RTC clock calibration value
only one parameter can be selected which is shown as below:
\arg 0x00 - 0x7F
\param[out] none
\retval none
*/
void bkp_rtc_calibration_value_set(uint8_t value)
{
uint16_t ctl;
ctl = BKP_OCTL;
ctl &= (uint16_t)OCTL_RCCV(0);
ctl |= (uint16_t)OCTL_RCCV(value);
BKP_OCTL = ctl;
}
/*!
\brief enable tamper pin detection
\param[in] none
\param[out] none
\retval none
*/
void bkp_tamper_detection_enable(void)
{
BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN;
}
/*!
\brief disable tamper pin detection
\param[in] none
\param[out] none
\retval none
*/
void bkp_tamper_detection_disable(void)
{
BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN;
}
/*!
\brief set tamper pin active level
\param[in] level: tamper active level
only one parameter can be selected which is shown as below:
\arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
\arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
\param[out] none
\retval none
*/
void bkp_tamper_active_level_set(uint16_t level)
{
uint16_t ctl = 0U;
ctl = BKP_TPCTL;
ctl &= (uint16_t)~BKP_TPCTL_TPAL;
ctl |= level;
BKP_TPCTL = ctl;
}
/*!
\brief enable tamper pin interrupt
\param[in] none
\param[out] none
\retval none
*/
void bkp_tamper_interrupt_enable(void)
{
BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE;
}
/*!
\brief disable tamper pin interrupt
\param[in] none
\param[out] none
\retval none
*/
void bkp_tamper_interrupt_disable(void)
{
BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE;
}
/*!
\brief get bkp flag state
\param[in] flag:
\arg BKP_FLAG_TAMPER: tamper event flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus bkp_flag_get(uint16_t flag)
{
if(RESET != (BKP_TPCS & flag)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear BKP flag state
\param[in] flag:
\arg BKP_FLAG_TAMPER: tamper event flag
\param[out] none
\retval none
*/
void bkp_flag_clear(uint16_t flag)
{
BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
}
/*!
\brief get BKP interrupt flag state
\param[in] flag
\arg BKP_INT_FLAG_TAMPER: tamper interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus bkp_interrupt_flag_get(uint16_t flag)
{
if(RESET != (BKP_TPCS & flag)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear BKP interrupt flag state
\param[in] flag:
\arg BKP_INT_FLAG_TAMPER: tamper interrupt flag
\param[out] none
\retval none
*/
void bkp_interrupt_flag_clear(uint16_t flag)
{
BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT);
}

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/*!
\file gd32e50x_cmp.c
\brief CMP driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_cmp.h"
#ifdef GD32E50X_CL
/*!
\brief deinitialize comparator
\param[in] none
\param[out] none
\retval none
*/
void cmp_deinit(void)
{
rcu_periph_reset_enable(RCU_CMPRST);
rcu_periph_reset_disable(RCU_CMPRST);
}
/*!
\brief initialize comparator input
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[in] inverting_input: CMP inverting input select
only one parameter can be selected which is shown as below:
\arg CMP_1_4VREFINT: VREFINT *1/4 input
\arg CMP_1_2VREFINT: VREFINT *1/2 input
\arg CMP_3_4VREFINT: VREFINT *3/4 input
\arg CMP_VREFINT: VREFINT input
\arg CMP_PA4: PA4 input
\arg CMP_PA5: PA5 input
\arg CMP_PA2: PA2 input(only CMP1)
\arg CMP_PB_2_15: PB2 input(only CMP1),PB15 input(only CMP3)
\param[out] none
\retval none
*/
void cmp_input_init(cmp_enum cmp_periph,inverting_input_enum inverting_input)
{
/* initialize comparator mode */
CMP_CS(cmp_periph) |= CS_CMPMSEL(inverting_input);
}
/*!
\brief initialize comparator output
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[in] output_slection: CMP output select
only one parameter can be selected which is shown as below:
\arg CMP_OUTPUT_NONE: output no selection
\arg CMP_OUTPUT_TIMER0_BKIN: TIMER0 break input(CMP1,CMP3,CMP5)
\arg CMP_OUTPUT_TIMER2IC2_TIMER1IC1: TIMER2 channel2 input capture(CMP3),TIMER1 channel1 input capture(CMP5)
\arg CMP_OUTPUT_TIMER0IC0: TIMER0 channel0 input capture(CMP1)
\arg CMP_OUTPUT_TIMER1IC3: TIMER1 channel3 input capture(CMP1)
\arg CMP_OUTPUT_TIMER2IC0: TIMER2 channel0 input capture(CMP1)
\param[in] output_polarity: CMP output polarity select
only one parameter can be selected which is shown as below:
\arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted
\arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted
\param[out] none
\retval none
*/
void cmp_output_init(cmp_enum cmp_periph,cmp_output_enum output_slection, uint32_t output_polarity)
{
/* initialize comparator output */
CMP_CS(cmp_periph) |= CS_CMPOSEL(output_slection);
/* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
CMP_CS(cmp_periph) |= CMP_CS_CMPPL;
}else{
CMP_CS(cmp_periph) &= ~CMP_CS_CMPPL;
}
}
/*!
\brief initialize CMP output blanking
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[in] output_blank: CMP output blank select
only one parameter can be selected which is shown as below:
\arg CMP_OUTPUTBLANK_NONE: no blanking
\arg CMP_OUTPUTBLANK_TIMER2_IC3: select TIMER2_CH3 as blanking source(CMP3)
\arg CMP_OUTPUTBLANK_TIMER1IC2: select TIMER1_CH2 as blanking source(CMP1)
\arg CMP_OUTPUTBLANK_TIMER2IC2_TIMER1IC3: Select TIMER2_CH2 as blanking source(CMP1), select TIMER1_CH3 as blanking source(CMP5)
\param[out] none
\retval none
*/
void cmp_outputblank_init(cmp_enum cmp_periph,cmp_outputblank_enum output_blank)
{
CMP_CS(cmp_periph) |= CS_CMPMBLK(output_blank);
}
/*!
\brief enable comparator
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[out] none
\retval none
*/
void cmp_enable(cmp_enum cmp_periph)
{
CMP_CS(cmp_periph) |= CMP_CS_CMPEN;
}
/*!
\brief disable comparator
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[out] none
\retval none
*/
void cmp_disable(cmp_enum cmp_periph)
{
CMP_CS(cmp_periph) &= ~CMP_CS_CMPEN;
}
/*!
\brief lock the comparator
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[out] none
\retval none
*/
void cmp_lock_enable(cmp_enum cmp_periph)
{
CMP_CS(cmp_periph) |= CMP_CS_CMPLK;
}
/*!
\brief get output level
\param[in] cmp_periph: CMPx(x=1,3,5)
\param[out] none
\retval the output level
*/
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
{
if(CMP_CS(cmp_periph) & CMP_CS_CMPO){
return CMP_OUTPUTLEVEL_HIGH;
}else{
return CMP_OUTPUTLEVEL_LOW;
}
}
#endif /* GD32E50x_CL */

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/*!
\file gd32e50x_crc.c
\brief CRC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_crc.h"
/*!
\brief deinitialize CRC calculation unit
\param[in] none
\param[out] none
\retval none
*/
void crc_deinit(void)
{
CRC_IDATA = (uint32_t)0xFFFFFFFFU;
CRC_DATA = (uint32_t)0xFFFFFFFFU;
CRC_FDATA = (uint32_t)0x00000000U;
CRC_POLY = (uint32_t)0x04C11DB7U;
CRC_CTL = CRC_CTL_RST;
}
/*!
\brief reset data register to the value of initializaiton data register
\param[in] none
\param[out] none
\retval none
*/
void crc_data_register_reset(void)
{
CRC_CTL |= (uint32_t)CRC_CTL_RST;
}
/*!
\brief enable the reverse operation of output data
\param[in] none
\param[out] none
\retval none
*/
void crc_reverse_output_data_enable(void)
{
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
}
/*!
\brief disable the reverse operation of output data
\param[in] none
\param[out] none
\retval none
*/
void crc_reverse_output_data_disable(void)
{
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
}
/*!
\brief configure the CRC input data function
\param[in] data_reverse: specify input data reverse function
only one parameter can be selected which is shown as below:
\arg CRC_INPUT_DATA_NOT: input data is not reversed
\arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
\arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
\arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
\param[out] none
\retval none
*/
void crc_input_data_reverse_config(uint32_t data_reverse)
{
CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
CRC_CTL |= (uint32_t)data_reverse;
}
/*!
\brief read the data register
\param[in] none
\param[out] none
\retval 32-bit value of the data register
*/
uint32_t crc_data_register_read(void)
{
uint32_t data;
data = CRC_DATA;
return (data);
}
/*!
\brief read the free data register
\param[in] none
\param[out] none
\retval 8-bit value of the free data register
*/
uint8_t crc_free_data_register_read(void)
{
uint8_t fdata;
fdata = (uint8_t)CRC_FDATA;
return (fdata);
}
/*!
\brief write the free data register
\param[in] free_data: specify 8-bit data
\param[out] none
\retval none
*/
void crc_free_data_register_write(uint8_t free_data)
{
CRC_FDATA = (uint32_t)free_data;
}
/*!
\brief write the initializaiton data register
\param[in] init_data: specify 32-bit data
\param[out] none
\retval none
*/
void crc_init_data_register_write(uint32_t init_data)
{
CRC_IDATA = (uint32_t)init_data;
}
/*!
\brief configure the CRC size of polynomial function
\param[in] poly_size: size of polynomial
only one parameter can be selected which is shown as below:
\arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
\arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
\arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
\arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
\param[out] none
\retval none
*/
void crc_polynomial_size_set(uint32_t poly_size)
{
CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
CRC_CTL |= (uint32_t)poly_size;
}
/*!
\brief configure the CRC polynomial value function
\param[in] poly: configurable polynomial value
\param[out] none
\retval none
*/
void crc_polynomial_set(uint32_t poly)
{
CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
CRC_POLY = poly;
}
/*!
\brief CRC calculate single data
\param[in] sdata: specify input data data
\param[in] data_format: input data format
only one parameter can be selected which is shown as below:
\arg INPUT_FORMAT_WORD: input data in word format
\arg INPUT_FORMAT_HALFWORD: input data in half-word format
\arg INPUT_FORMAT_BYTE: input data in byte format
\param[out] none
\retval CRC calculate value
*/
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format)
{
if(INPUT_FORMAT_WORD == data_format){
REG32(CRC) = sdata;
}else if(INPUT_FORMAT_HALFWORD == data_format){
REG16(CRC) = (uint16_t)sdata;
}else{
REG8(CRC) = (uint8_t)sdata;
}
return(CRC_DATA);
}
/*!
\brief CRC calculate a data array
\param[in] array: pointer to the input data array
\param[in] size: size of the array
\param[in] data_format: input data format
only one parameter can be selected which is shown as below:
\arg INPUT_FORMAT_WORD: input data in word format
\arg INPUT_FORMAT_HALFWORD: input data in half-word format
\arg INPUT_FORMAT_BYTE: input data in byte format
\param[out] none
\retval CRC calculate value
*/
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format)
{
uint8_t *data8;
uint16_t *data16;
uint32_t *data32;
uint32_t index;
if(INPUT_FORMAT_WORD == data_format){
data32 = (uint32_t *)array;
for(index = 0U; index < size; index++){
REG32(CRC) = data32[index];
}
}else if(INPUT_FORMAT_HALFWORD == data_format){
data16 = (uint16_t *)array;
for(index = 0U; index < size; index++){
REG16(CRC) = data16[index];
}
}else{
data8 = (uint8_t *)array;
for(index = 0U; index < size; index++){
REG8(CRC) = data8[index];
}
}
return (CRC_DATA);
}

392
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/*!
\file gd32e50x_ctc.c
\brief CTC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_ctc.h"
#define CTC_FLAG_MASK ((uint32_t)0x00000700U)
/* CTC register bit offset */
#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U)
#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U)
#define CTC_REFCAP_OFFSET ((uint32_t)16U)
#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U)
/*!
\brief reset CTC clock trim controller
\param[in] none
\param[out] none
\retval none
*/
void ctc_deinit(void)
{
/* reset CTC */
rcu_periph_reset_enable(RCU_CTCRST);
rcu_periph_reset_disable(RCU_CTCRST);
}
/*!
\brief enable CTC trim counter
\param[in] none
\param[out] none
\retval none
*/
void ctc_counter_enable(void)
{
CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
}
/*!
\brief disable CTC trim counter
\param[in] none
\param[out] none
\retval none
*/
void ctc_counter_disable(void)
{
CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
}
/*!
\brief configure the IRC48M trim value
\param[in] ctc_trim_value: 8-bit IRC48M trim value
\arg 0x00 - 0x3F
\param[out] none
\retval none
*/
void ctc_irc48m_trim_value_config(uint8_t trim_value)
{
/* clear TRIMVALUE bits */
CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
/* set TRIMVALUE bits */
CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET);
}
/*!
\brief generate software reference source sync pulse
\param[in] none
\param[out] none
\retval none
*/
void ctc_software_refsource_pulse_generate(void)
{
CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
}
/*!
\brief configure hardware automatically trim mode
\param[in] hardmode:
only one parameter can be selected which is shown as below:
\arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable
\arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable
\param[out] none
\retval none
*/
void ctc_hardware_trim_mode_config(uint32_t hardmode)
{
CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
CTC_CTL0 |= (uint32_t)hardmode;
}
/*!
\brief configure reference signal source polarity
\param[in] polarity:
only one parameter can be selected which is shown as below:
\arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge
\arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge
\param[out] none
\retval none
*/
void ctc_refsource_polarity_config(uint32_t polarity)
{
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
CTC_CTL1 |= (uint32_t)polarity;
}
/*!
\brief select reference signal source
\param[in] refs:
only one parameter can be selected which is shown as below:
\arg CTC_REFSOURCE_GPIO: GPIO is selected
\arg CTC_REFSOURCE_LXTAL: LXTAL is selected
\arg CTC_REFSOURCE_USB_SOF: USBD_SOF or USBHS_SOF is selected
\param[out] none
\retval none
*/
void ctc_refsource_signal_select(uint32_t refs)
{
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
CTC_CTL1 |= (uint32_t)refs;
}
/*!
\brief configure reference signal source prescaler
\param[in] prescaler:
only one parameter can be selected which is shown as below:
\arg CTC_REFSOURCE_PSC_OFF: reference signal not divided
\arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2
\arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4
\arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8
\arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16
\arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32
\arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64
\arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128
\param[out] none
\retval none
*/
void ctc_refsource_prescaler_config(uint32_t prescaler)
{
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
CTC_CTL1 |= (uint32_t)prescaler;
}
/*!
\brief configure clock trim base limit value
\param[in] limit_value: 8-bit clock trim base limit value
\arg 0x00 - 0xFF
\param[out] none
\retval none
*/
void ctc_clock_limit_value_config(uint8_t limit_value)
{
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET);
}
/*!
\brief configure CTC counter reload value
\param[in] reload_value: 16-bit CTC counter reload value
\arg 0x0000 - 0xFFFF
\param[out] none
\retval none
*/
void ctc_counter_reload_value_config(uint16_t reload_value)
{
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
CTC_CTL1 |= (uint32_t)reload_value;
}
/*!
\brief read CTC counter capture value when reference sync pulse occurred
\param[in] none
\param[out] none
\retval the 16-bit CTC counter capture value
*/
uint16_t ctc_counter_capture_value_read(void)
{
uint16_t capture_value = 0U;
capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> CTC_REFCAP_OFFSET);
return (capture_value);
}
/*!
\brief read CTC trim counter direction when reference sync pulse occurred
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
\arg SET: CTC trim counter direction is down-counting
\arg RESET: CTC trim counter direction is up-counting
*/
FlagStatus ctc_counter_direction_read(void)
{
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
return SET;
}else{
return RESET;
}
}
/*!
\brief read CTC counter reload value
\param[in] none
\param[out] none
\retval the 16-bit CTC counter reload value
*/
uint16_t ctc_counter_reload_value_read(void)
{
uint16_t reload_value = 0U;
reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
return (reload_value);
}
/*!
\brief read the IRC48M trim value
\param[in] none
\param[out] none
\retval the 8-bit IRC48M trim value
*/
uint8_t ctc_irc48m_trim_value_read(void)
{
uint8_t trim_value = 0U;
trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET);
return (trim_value);
}
/*!
\brief get CTC flag
\param[in] flag: the CTC flag
only one parameter can be selected which is shown as below:
\arg CTC_FLAG_CKOK: clock trim OK flag
\arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_EREF: expect reference flag
\arg CTC_FLAG_CKERR: clock trim error bit
\arg CTC_FLAG_REFMISS: reference sync pulse miss
\arg CTC_FLAG_TRIMERR: trim value error bit
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus ctc_flag_get(uint32_t flag)
{
if(RESET != (CTC_STAT & flag)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear CTC flag
\param[in] flag: the CTC flag
only one parameter can be selected which is shown as below:
\arg CTC_FLAG_CKOK: clock trim OK flag
\arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_EREF: expect reference flag
\arg CTC_FLAG_CKERR: clock trim error bit
\arg CTC_FLAG_REFMISS: reference sync pulse miss
\arg CTC_FLAG_TRIMERR: trim value error bit
\param[out] none
\retval none
*/
void ctc_flag_clear(uint32_t flag)
{
if(RESET != (flag & CTC_FLAG_MASK)){
CTC_INTC |= CTC_INTC_ERRIC;
}else{
CTC_INTC |= flag;
}
}
/*!
\brief enable the CTC interrupt
\param[in] interrupt: CTC interrupt enable
one or more parameters can be selected which are shown as below:
\arg CTC_INT_CKOK: clock trim OK interrupt enable
\arg CTC_INT_CKWARN: clock trim warning interrupt enable
\arg CTC_INT_ERR: error interrupt enable
\arg CTC_INT_EREF: expect reference interrupt enable
\param[out] none
\retval none
*/
void ctc_interrupt_enable(uint32_t interrupt)
{
CTC_CTL0 |= (uint32_t)interrupt;
}
/*!
\brief disable the CTC interrupt
\param[in] interrupt: CTC interrupt enable source
one or more parameters can be selected which are shown as below:
\arg CTC_INT_CKOK: clock trim OK interrupt enable
\arg CTC_INT_CKWARN: clock trim warning interrupt enable
\arg CTC_INT_ERR: error interrupt enable
\arg CTC_INT_EREF: expect reference interrupt enable
\param[out] none
\retval none
*/
void ctc_interrupt_disable(uint32_t interrupt)
{
CTC_CTL0 &= (uint32_t)(~interrupt);
}
/*!
\brief get CTC interrupt flag
\param[in] int_flag: the CTC interrupt flag
only one parameter can be selected which is shown as below:
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt
\arg CTC_INT_FLAG_ERR: error interrupt
\arg CTC_INT_FLAG_EREF: expect reference interrupt
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
{
uint32_t interrupt_flag = 0U, intenable = 0U;
/* check whether the interrupt is enabled */
if(RESET != (int_flag & CTC_FLAG_MASK)){
intenable = CTC_CTL0 & CTC_CTL0_ERRIE;
}else{
intenable = CTC_CTL0 & int_flag;
}
/* get interrupt flag status */
interrupt_flag = CTC_STAT & int_flag;
if(interrupt_flag && intenable){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear CTC interrupt flag
\param[in] int_flag: the CTC interrupt flag
only one parameter can be selected which is shown as below:
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt
\arg CTC_INT_FLAG_ERR: error interrupt
\arg CTC_INT_FLAG_EREF: expect reference interrupt
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt
\param[out] none
\retval none
*/
void ctc_interrupt_flag_clear(uint32_t int_flag)
{
if(RESET != (int_flag & CTC_FLAG_MASK)){
CTC_INTC |= CTC_INTC_ERRIC;
}else{
CTC_INTC |= int_flag;
}
}

833
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/*!
\file gd32e50x_dac.c
\brief DAC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_dac.h"
/* DAC register bit offset */
#define OUT1_REG_OFFSET ((uint32_t)0x00000010U)
#define DH_12BIT_OFFSET ((uint32_t)0x00000010U)
#define DH_8BIT_OFFSET ((uint32_t)0x00000008U)
/*!
\brief deinitialize DAC
\param[in] none
\param[out] none
\retval none
*/
void dac_deinit(void)
{
rcu_periph_reset_enable(RCU_DACRST);
rcu_periph_reset_disable(RCU_DACRST);
}
/*!
\brief enable DAC
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_enable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 |= DAC_CTL0_DEN0;
}else{
DAC_CTL0 |= DAC_CTL0_DEN1;
}
}
/*!
\brief disable DAC
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_disable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 &= ~DAC_CTL0_DEN0;
}else{
DAC_CTL0 &= ~DAC_CTL0_DEN1;
}
}
/*!
\brief enable DAC DMA function
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_dma_enable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 |= DAC_CTL0_DDMAEN0;
}else{
DAC_CTL0 |= DAC_CTL0_DDMAEN1;
}
}
/*!
\brief disable DAC DMA function
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_dma_disable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 &= ~DAC_CTL0_DDMAEN0;
}else{
DAC_CTL0 &= ~DAC_CTL0_DDMAEN1;
}
}
/*!
\brief enable DAC output buffer
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_output_buffer_enable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 &= ~DAC_CTL0_DBOFF0;
}else{
DAC_CTL0 &= ~DAC_CTL0_DBOFF1;
}
}
/*!
\brief disable DAC output buffer
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_output_buffer_disable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 |= DAC_CTL0_DBOFF0;
}else{
DAC_CTL0 |= DAC_CTL0_DBOFF1;
}
}
/*!
\brief get DAC output value
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval DAC output data: 0~4095
*/
uint16_t dac_output_value_get(uint8_t dac_out)
{
uint16_t data = 0U;
if(DAC_OUT_0 == dac_out){
/* store the DAC_OUT0 output value */
data = (uint16_t)OUT0_DO;
}else{
/* store the DAC_OUT1 output value */
data = (uint16_t)OUT1_DO;
}
return data;
}
/*!
\brief set DAC data holding register value
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] dac_align: DAC data alignment mode
only one parameter can be selected which is shown as below:
\arg DAC_ALIGN_12B_R: 12-bit right-aligned data
\arg DAC_ALIGN_12B_L: 12-bit left-aligned data
\arg DAC_ALIGN_8B_R: 8-bit right-aligned data
\param[in] data: data to be loaded, 0~4095
\param[out] none
\retval none
*/
void dac_data_set(uint8_t dac_out, uint32_t dac_align, uint16_t data)
{
/* DAC_OUT0 data alignment */
if(DAC_OUT_0 == dac_out){
switch(dac_align){
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
OUT0_R12DH = data;
break;
/* 12-bit left-aligned data */
case DAC_ALIGN_12B_L:
OUT0_L12DH = data;
break;
/* 8-bit right-aligned data */
case DAC_ALIGN_8B_R:
OUT0_R8DH = data;
break;
default:
break;
}
}else{
/* DAC_OUT1 data alignment */
switch(dac_align){
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
OUT1_R12DH = data;
break;
/* 12-bit left-aligned data */
case DAC_ALIGN_12B_L:
OUT1_L12DH = data;
break;
/* 8-bit right-aligned data */
case DAC_ALIGN_8B_R:
OUT1_R8DH = data;
break;
default:
break;
}
}
}
/*!
\brief enable DAC output FIFO
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_output_fifo_enable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL1 |= DAC_CTL1_FIFOEN0;
}else{
DAC_CTL1 |= DAC_CTL1_FIFOEN1;
}
}
/*!
\brief disable DAC output FIFO
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_output_fifo_disable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL1 &= ~DAC_CTL1_FIFOEN0;
}else{
DAC_CTL1 &= ~DAC_CTL1_FIFOEN1;
}
}
/*!
\brief get DAC output FIFO number
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval DAC output FIFO number: 0~4
*/
uint16_t dac_output_fifo_number_get(uint8_t dac_out)
{
uint16_t number = 0U;
if(DAC_OUT_0 == dac_out){
/* get the DAC_OUT0 output FIFO number */
number = (uint16_t)((uint16_t)DAC_STAT1 >> 4U);
}else{
/* get the DAC_OUT1 output FIFO number */
number = (uint16_t)(DAC_STAT1 >> 20U);
}
return number;
}
/*!
\brief enable DAC trigger
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_trigger_enable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 |= DAC_CTL0_DTEN0;
}else{
DAC_CTL0 |= DAC_CTL0_DTEN1;
}
}
/*!
\brief disable DAC trigger
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_trigger_disable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_CTL0 &= ~DAC_CTL0_DTEN0;
}else{
DAC_CTL0 &= ~DAC_CTL0_DTEN1;
}
}
/*!
\brief configure DAC trigger source
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] triggersource: external triggers of DAC
only one parameter can be selected which is shown as below:
\arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
\arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32E50X_HD and GD32E50X_XD devices)
\arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32E50X_CL devices)
\arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
\arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
\arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
\arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
\arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
\arg DAC_TRIGGER_SOFTWARE: software trigger
\arg DAC_TRIGGER_SHRTIMER_DACTRIG0: SHRTIMER_DACTRIG0 trigger(for GD32E50X_HD, GD32E50X_XD and GD32E50X_CL devices)
\arg DAC_TRIGGER_SHRTIMER_DACTRIG1: SHRTIMER_DACTRIG1 trigger(for GD32E50X_HD, GD32E50X_XD and GD32E50X_CL devices)
\arg DAC_TRIGGER_SHRTIMER_DACTRIG2: SHRTIMER_DACTRIG2 trigger(for GD32E50X_HD, GD32E50X_XD and GD32E50X_CL devices)
\param[out] none
\retval none
*/
void dac_trigger_source_config(uint8_t dac_out,uint32_t triggersource)
{
if(DAC_OUT_0 == dac_out){
/* configure DAC_OUT0 trigger source */
DAC_CTL0 &= (uint32_t)(~(DAC_CTL0_DTSEL0 | DAC_CTL0_DTSEL0_3));
DAC_CTL0 |= triggersource;
}else{
/* configure DAC_OUT1 trigger source */
DAC_CTL0 &= (uint32_t)(~(DAC_CTL0_DTSEL1 | DAC_CTL0_DTSEL1_3));
DAC_CTL0 |= (triggersource << OUT1_REG_OFFSET);
}
}
/*!
\brief enable DAC software trigger
\param[in] dac_out: DAC_OUT_x(x=0,1)
\retval none
*/
void dac_software_trigger_enable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_SWT |= DAC_SWT_SWTR0;
}else{
DAC_SWT |= DAC_SWT_SWTR1;
}
}
/*!
\brief disable DAC software trigger
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[out] none
\retval none
*/
void dac_software_trigger_disable(uint8_t dac_out)
{
if(DAC_OUT_0 == dac_out){
DAC_SWT &= ~DAC_SWT_SWTR0;
}else{
DAC_SWT &= ~DAC_SWT_SWTR1;
}
}
/*!
\brief configure DAC wave mode
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] wave_mode: DAC wave mode
only one parameter can be selected which is shown as below:
\arg DAC_WAVE_DISABLE: wave mode disable
\arg DAC_WAVE_MODE_LFSR: LFSR noise mode
\arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
\param[out] none
\retval none
*/
void dac_wave_mode_config(uint8_t dac_out, uint32_t wave_mode)
{
if(DAC_OUT_0 == dac_out){
/* configure DAC_OUT0 wave mode */
DAC_CTL0 &= ~DAC_CTL0_DWM0;
DAC_CTL0 |= wave_mode;
}else{
/* configure DAC_OUT1 wave mode */
DAC_CTL0 &= ~DAC_CTL0_DWM1;
DAC_CTL0 |= (wave_mode << OUT1_REG_OFFSET);
}
}
/*!
\brief configure DAC wave bit width
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] bit_width: DAC noise wave bit width
only one parameter can be selected which is shown as below:
\arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
\arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
\arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
\arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
\arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
\arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
\arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
\arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
\arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
\arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
\arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
\arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
\param[out] none
\retval none
*/
void dac_wave_bit_width_config(uint8_t dac_out, uint32_t bit_width)
{
if(DAC_OUT_0 == dac_out){
/* configure DAC_OUT0 wave bit width */
DAC_CTL0 &= ~DAC_CTL0_DWBW0;
DAC_CTL0 |= bit_width;
}else{
/* configure DAC_OUT1 wave bit width */
DAC_CTL0 &= ~DAC_CTL0_DWBW1;
DAC_CTL0 |= (bit_width << OUT1_REG_OFFSET);
}
}
/*!
\brief configure DAC LFSR noise mode
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] unmask_bits: LFSR noise unmask bits
only one parameter can be selected which is shown as below:
\arg DAC_LFSR_BIT0: unmask the LFSR bit0
\arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
\arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
\arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
\arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
\arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
\arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
\arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
\arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
\arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
\arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
\arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
\param[out] none
\retval none
*/
void dac_lfsr_noise_config(uint8_t dac_out, uint32_t unmask_bits)
{
if(DAC_OUT_0 == dac_out){
/* configure DAC_OUT0 LFSR noise mode */
DAC_CTL0 &= ~DAC_CTL0_DWBW0;
DAC_CTL0 |= unmask_bits;
}else{
/* configure DAC_OUT1 LFSR noise mode */
DAC_CTL0 &= ~DAC_CTL0_DWBW1;
DAC_CTL0 |= (unmask_bits << OUT1_REG_OFFSET);
}
}
/*!
\brief configure DAC triangle noise mode
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] amplitude: the amplitude of the triangle
only one parameter can be selected which is shown as below:
\arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
\arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
\arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
\arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
\arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
\arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
\arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
\arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
\arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
\arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
\arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
\arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
\param[out] none
\retval none
*/
void dac_triangle_noise_config(uint8_t dac_out, uint32_t amplitude)
{
if(DAC_OUT_0 == dac_out){
/* configure DAC_OUT0 triangle noise mode */
DAC_CTL0 &= ~DAC_CTL0_DWBW0;
DAC_CTL0 |= amplitude;
}else{
/* configure DAC_OUT1 triangle noise mode */
DAC_CTL0 &= ~DAC_CTL0_DWBW1;
DAC_CTL0 |= (amplitude << OUT1_REG_OFFSET);
}
}
/*!
\brief enable DAC concurrent mode
\param[in] none
\param[out] none
\retval none
*/
void dac_concurrent_enable(void)
{
uint32_t ctl = 0U;
ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
DAC_CTL0 |= (uint32_t)(ctl);
}
/*!
\brief disable DAC concurrent mode
\param[in] none
\param[out] none
\retval none
*/
void dac_concurrent_disable(void)
{
uint32_t ctl = 0U;
ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
DAC_CTL0 &= (uint32_t)(~ctl);
}
/*!
\brief enable DAC concurrent software trigger
\param[in] none
\param[out] none
\retval none
*/
void dac_concurrent_software_trigger_enable(void)
{
uint32_t swt = 0U;
swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
DAC_SWT |= (uint32_t)(swt);
}
/*!
\brief disable DAC concurrent software trigger
\param[in] none
\param[out] none
\retval none
*/
void dac_concurrent_software_trigger_disable(void)
{
uint32_t swt = 0U;
swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
DAC_SWT &= (uint32_t)(~swt);
}
/*!
\brief enable DAC concurrent buffer
\param[in] none
\param[out] none
\retval none
*/
void dac_concurrent_output_buffer_enable(void)
{
uint32_t ctl = 0U;
ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
DAC_CTL0 &= (uint32_t)(~ctl);
}
/*!
\brief disable DAC concurrent buffer
\param[in] none
\param[out] none
\retval none
*/
void dac_concurrent_output_buffer_disable(void)
{
uint32_t ctl = 0U;
ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
DAC_CTL0 |= (uint32_t)(ctl);
}
/*!
\brief set DAC concurrent mode data holding register value
\param[in] dac_align: DAC data alignment mode
only one parameter can be selected which is shown as below:
\arg DAC_ALIGN_12B_R: 12-bit right-aligned data
\arg DAC_ALIGN_12B_L: 12-bit left-aligned data
\arg DAC_ALIGN_8B_R: 8-bit right-aligned data
\param[in] data0: data to be loaded, 0~4095
\param[in] data1: data to be loaded, 0~4095
\param[out] none
\retval none
*/
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
{
uint32_t data = 0U;
switch(dac_align){
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
DACC_R12DH = (uint32_t)data;
break;
/* 12-bit left-aligned data */
case DAC_ALIGN_12B_L:
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
DACC_L12DH = (uint32_t)data;
break;
/* 8-bit right-aligned data */
case DAC_ALIGN_8B_R:
data = (uint32_t)(((uint32_t)data1 << DH_8BIT_OFFSET) | data0);
DACC_R8DH = (uint32_t)data;
break;
default:
break;
}
}
/*!
\brief get DAC flag
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] dac_flag: DAC flag
only one parameter can be selected which is shown as below:
\arg DAC_FLAG_DDUDR0: DAC_OUT0 DMA underrun flag
\arg DAC_FLAG_FF0: DAC_OUT0 FIFO full flag
\arg DAC_FLAG_FE0: DAC_OUT0 FIFO empty flag
\arg DAC_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow flag
\arg DAC_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow flag
\arg DAC_FLAG_DDUDR1: DAC_OUT1 DMA underrun flag
\arg DAC_FLAG_FF1: DAC_OUT1 FIFO full flag
\arg DAC_FLAG_FE1: DAC_OUT1 FIFO empty flag
\arg DAC_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow flag
\arg DAC_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dac_flag_get(uint8_t dac_out, uint32_t flag)
{
if(DAC_OUT_0 == dac_out){
/* check DAC_OUT0 flag */
if(DAC_FLAG_DDUDR0 == flag){
if(RESET != (DAC_STAT0 & DAC_STAT0_DDUDR0)){
return SET;
}else{
return RESET;
}
}else{
if(RESET != (DAC_STAT1 & flag)){
return SET;
}else{
return RESET;
}
}
}else{
/* check DAC_OUT1 flag */
if(DAC_FLAG_DDUDR1 == flag){
if(RESET != (DAC_STAT0 & DAC_STAT0_DDUDR1)){
return SET;
}else{
return RESET;
}
}else{
if(RESET != (DAC_STAT1 & flag)){
return SET;
}else{
return RESET;
}
}
}
}
/*!
\brief clear DAC flag
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] flag: DAC flag
only one parameter can be selected which is shown as below:
\arg DAC_FLAG_DDUDR0: DAC_OUT0 DMA underrun flag
\arg DAC_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow flag
\arg DAC_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow flag
\arg DAC_FLAG_DDUDR1: DAC_OUT1 DMA underrun flag
\arg DAC_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow flag
\arg DAC_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow flag
\param[out] none
\retval none
*/
void dac_flag_clear(uint8_t dac_out, uint32_t flag)
{
if(DAC_OUT_0 == dac_out){
/* clear DAC_OUT0 flag */
if(DAC_FLAG_DDUDR0 == flag){
DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR0;
}else{
DAC_STAT1 |= (uint32_t)flag;
}
}else{
/* clear DAC_OUT1 flag */
if(DAC_FLAG_DDUDR1 == flag){
DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR1;
}else{
DAC_STAT1 |= (uint32_t)flag;
}
}
}
/*!
\brief enable DAC interrupt
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] interrupt: the DAC interrupt
only one parameter can be selected which is shown as below:
\arg DAC_INT_DDUDRIE0: DAC_OUT0 DMA underrun interrupt enable
\arg DAC_INT_FIFOOVRIE0: DAC_OUT0 FIFO overflow interrupt enable
\arg DAC_INT_FIFOUDRIE0: DAC_OUT0 FIFO underflow interrupt enable
\arg DAC_INT_DDUDRIE1: DAC_OUT1 DMA underrun interrupt enable
\arg DAC_INT_FIFOOVRIE1: DAC_OUT1 FIFO overflow interrupt enable
\arg DAC_INT_FIFOUDRIE1: DAC_OUT1 FIFO underflow interrupt enable
\param[out] none
\retval none
*/
void dac_interrupt_enable(uint8_t dac_out, uint32_t interrupt)
{
if(DAC_OUT_0 == dac_out){
/* enable DAC_OUT0 interrupt */
if(DAC_INT_DDUDRIE0 == interrupt){
DAC_CTL0 |= (uint32_t)DAC_CTL0_DDUDRIE0;
}else{
DAC_CTL1 |= (uint32_t)interrupt;
}
}else{
/* enable DAC_OUT1 interrupt */
if(DAC_INT_DDUDRIE1 == interrupt){
DAC_CTL0 |= (uint32_t)DAC_CTL0_DDUDRIE1;
}else{
DAC_CTL1 |= (uint32_t)interrupt;
}
}
}
/*!
\brief disable DAC interrupt
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] interrupt: the DAC interrupt
only one parameter can be selected which is shown as below:
\arg DAC_INT_DDUDRIE0: DAC_OUT0 DMA underrun interrupt disable
\arg DAC_INT_FIFOOVRIE0: DAC_OUT0 FIFO overflow interrupt disable
\arg DAC_INT_FIFOUDRIE0: DAC_OUT0 FIFO underflow interrupt disable
\arg DAC_INT_DDUDRIE1: DAC_OUT1 DMA underrun interrupt disable
\arg DAC_INT_FIFOOVRIE1: DAC_OUT1 FIFO overflow interrupt disable
\arg DAC_INT_FIFOUDRIE1: DAC_OUT1 FIFO underflow interrupt disable
\param[out] none
\retval none
*/
void dac_interrupt_disable(uint8_t dac_out, uint32_t interrupt)
{
if(DAC_OUT_0 == dac_out){
/* disable DAC_OUT0 interrupt */
if(DAC_INT_DDUDRIE0 == interrupt){
DAC_CTL0 &= (uint32_t)(~DAC_CTL0_DDUDRIE0);
}else{
DAC_CTL1 &= (uint32_t)(~interrupt);
}
}else{
/* disable DAC_OUT1 interrupt */
if(DAC_INT_DDUDRIE1 == interrupt){
DAC_CTL0 &= (uint32_t)(~DAC_CTL0_DDUDRIE1);
}else{
DAC_CTL1 &= (uint32_t)(~interrupt);
}
}
}
/*!
\brief get DAC interrupt flag
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] int_flag: DAC interrupt flag
only one parameter can be selected which is shown as below:
\arg DAC_INT_FLAG_DDUDR0: DAC_OUT0 DMA underrun interrupt flag
\arg DAC_INT_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow interrupt flag
\arg DAC_INT_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow interrupt flag
\arg DAC_INT_FLAG_DDUDR1: DAC_OUT1 DMA underrun interrupt flag
\arg DAC_INT_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow interrupt flag
\arg DAC_INT_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow interrupt flag
\param[out] none
\retval the state of DAC interrupt flag(SET or RESET)
*/
FlagStatus dac_interrupt_flag_get(uint8_t dac_out, uint32_t int_flag)
{
uint32_t reg1 = 0U, reg2 = 0U;
/* check DAC_OUT0 flag */
if(DAC_OUT_0 == dac_out){
/* check DAC_OUT0 interrupt flag */
if(DAC_INT_FLAG_DDUDR0 == int_flag){
reg1 = DAC_STAT0 & DAC_STAT0_DDUDR0;
reg2 = DAC_CTL0 & DAC_CTL0_DDUDRIE0;
}else if(DAC_INT_FLAG_FIFOOVR0 == int_flag){
reg1 = DAC_STAT1 & DAC_STAT1_FIFOOVR0;
reg2 = DAC_CTL1 & DAC_CTL1_FIFOOVRIE0;
}else{
reg1 = DAC_STAT1 & DAC_FLAG_FIFOUDR0;
reg2 = DAC_CTL1 & DAC_INT_FIFOUDRIE0;
}
}else{
/* check DAC_OUT1 interrupt flag */
if(DAC_INT_FLAG_DDUDR1 == int_flag){
reg1 = DAC_STAT0 & DAC_STAT0_DDUDR1;
reg2 = DAC_CTL0 & DAC_CTL0_DDUDRIE1;
}else if(DAC_INT_FLAG_FIFOOVR1 == int_flag){
reg1 = DAC_STAT1 & DAC_STAT1_FIFOOVR1;
reg2 = DAC_CTL1 & DAC_CTL1_FIFOOVRIE1;
}else{
reg1 = DAC_STAT1 & DAC_FLAG_FIFOUDR1;
reg2 = DAC_CTL1 & DAC_INT_FIFOUDRIE1;
}
}
/*get DAC interrupt flag status */
if((RESET != reg1) && (RESET != reg2)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear DAC interrupt flag
\param[in] dac_out: DAC_OUT_x(x=0,1)
\param[in] int_flag: DAC interrupt flag
only one parameter can be selected which is shown as below:
\arg DAC_INT_FLAG_DDUDR0: DAC_OUT0 DMA underrun interrupt flag
\arg DAC_INT_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow interrupt flag
\arg DAC_INT_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow interrupt flag
\arg DAC_INT_FLAG_DDUDR1: DAC_OUT1 DMA underrun interrupt flag
\arg DAC_INT_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow interrupt flag
\arg DAC_INT_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow interrupt flag
\param[out] none
\retval none
*/
void dac_interrupt_flag_clear(uint8_t dac_out, uint32_t int_flag)
{
if(DAC_OUT_0 == dac_out){
/* clear DAC_OUT0 interrupt flag */
if(DAC_INT_FLAG_DDUDR0 == int_flag){
DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR0;
}else{
DAC_STAT1 |= (uint32_t)int_flag;
}
}else{
/* clear DAC_OUT1 interrupt flag */
if(DAC_INT_FLAG_DDUDR1 == int_flag){
DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR1;
}else{
DAC_STAT1 |= (uint32_t)int_flag;
}
}
}

163
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_dbg.c Normal file
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@@ -0,0 +1,163 @@
/*!
\file gd32e50x_dbg.c
\brief DBG driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_dbg.h"
#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */
/*!
\brief deinitialize the DBG
\param[in] none
\param[out] none
\retval none
*/
void dbg_deinit(void)
{
DBG_CTL = DBG_RESET_VAL;
}
/*!
\brief read DBG_ID code register
\param[in] none
\param[out] none
\retval DBG_ID code
*/
uint32_t dbg_id_get(void)
{
return DBG_ID;
}
/*!
\brief enable low power behavior when the mcu is in debug mode
\param[in] dbg_low_power:
one or more parameters can be selected which are shown as below:
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
\param[out] none
\retval none
*/
void dbg_low_power_enable(uint32_t dbg_low_power)
{
DBG_CTL |= dbg_low_power;
}
/*!
\brief disable low power behavior when the mcu is in debug mode
\param[in] dbg_low_power:
one or more parameters can be selected which are shown as below:
\arg DBG_LOW_POWER_SLEEP: do not keep debugger connection during sleep mode
\arg DBG_LOW_POWER_DEEPSLEEP: do not keep debugger connection during deepsleep mode
\arg DBG_LOW_POWER_STANDBY: do not keep debugger connection during standby mode
\param[out] none
\retval none
*/
void dbg_low_power_disable(uint32_t dbg_low_power)
{
DBG_CTL &= ~dbg_low_power;
}
/*!
\brief enable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum
only one parameter can be selected which is shown as below:
\arg DBG_FWDGT_HOLD : hold FWDGT counter when core is halted
\arg DBG_WWDGT_HOLD : hold WWDGT counter when core is halted
\arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus timeout when core is halted
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted
\arg DBG_SHRTIMER_HOLD : hold SHRTIMER counter when core is halted, except for GD32EPRT series
\param[out] none
\retval none
*/
void dbg_periph_enable(dbg_periph_enum dbg_periph)
{
DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
}
/*!
\brief disable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum
only one parameter can be selected which is shown as below:
\arg DBG_FWDGT_HOLD : hold FWDGT counter when core is halted
\arg DBG_WWDGT_HOLD : hold WWDGT counter when core is halted
\arg DBG_I2Cx_HOLD (x=0,1,2): hold I2Cx smbus timeout when core is halted
\arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted
\arg DBG_SHRTIMER_HOLD : hold SHRTIMER counter when core is halted, except for GD32EPRT series
\param[out] none
\retval none
*/
void dbg_periph_disable(dbg_periph_enum dbg_periph)
{
DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
}
/*!
\brief enable trace pin assignment
\param[in] none
\param[out] none
\retval none
*/
void dbg_trace_pin_enable(void)
{
DBG_CTL |= DBG_CTL_TRACE_IOEN;
}
/*!
\brief disable trace pin assignment
\param[in] none
\param[out] none
\retval none
*/
void dbg_trace_pin_disable(void)
{
DBG_CTL &= ~DBG_CTL_TRACE_IOEN;
}
/*!
\brief set trace pin mode
\param[in] trace_mode:
only one parameter can be selected which is shown as below:
\arg TRACE_MODE_ASYNC: trace pin used for async mode
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
\param[out] none
\retval none
*/
void dbg_trace_pin_mode_set(uint32_t trace_mode)
{
DBG_CTL &= ~DBG_CTL_TRACE_MODE;
DBG_CTL |= trace_mode;
}

753
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_dma.c Normal file
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@@ -0,0 +1,753 @@
/*!
\file gd32e50x_dma.c
\brief DMA driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_dma.h"
#include <stdlib.h>
#define DMA_WRONG_HANDLE while(1){}
/* check whether peripheral matches channels or not */
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx);
/*!
\brief deinitialize DMA a channel registers
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is deinitialized
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* disable DMA a channel */
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
/* reset DMA channel registers */
DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
}
/*!
\brief initialize the parameters of DMA struct with the default values
\param[in] init_struct: the initialization data needed to initialize DMA channel
\param[out] none
\retval none
*/
void dma_struct_para_init(dma_parameter_struct* init_struct)
{
if(NULL == init_struct){
DMA_WRONG_HANDLE
}
/* set the DMA struct with the default values */
init_struct->periph_addr = 0U;
init_struct->periph_width = 0U;
init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE;
init_struct->memory_addr = 0U;
init_struct->memory_width = 0U;
init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE;
init_struct->number = 0U;
init_struct->direction = DMA_PERIPHERAL_TO_MEMORY;
init_struct->priority = DMA_PRIORITY_LOW;
}
/*!
\brief initialize DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel is initialized
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] init_struct: the data needed to initialize DMA channel
periph_addr: peripheral base address
periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT
periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE
memory_addr: memory base address
memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT
memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE
direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL
number: the number of remaining data to be transferred by the DMA
priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH
\param[out] none
\retval none
*/
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct)
{
uint32_t ctl;
if(NULL == init_struct){
DMA_WRONG_HANDLE
}
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* configure peripheral base address */
DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
/* configure memory base address */
DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr;
/* configure the number of remaining data to be transferred */
DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
/* configure peripheral transfer width,memory transfer width and priority */
ctl = DMA_CHCTL(dma_periph, channelx);
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}else{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure the direction of data transfer */
if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief enable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
}
/*!
\brief disable DMA circulation mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
/*!
\brief enable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
}
/*!
\brief disable memory to memory mode
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
}
/*!
\brief enable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
}
/*!
\brief disable DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
}
/*!
\brief set DMA peripheral base address
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set peripheral base address
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] address: peripheral base address
\param[out] none
\retval none
*/
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHPADDR(dma_periph, channelx) = address;
}
/*!
\brief set DMA memory base address
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set memory base address
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] address: memory base address
\param[out] none
\retval none
*/
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHMADDR(dma_periph, channelx) = address;
}
/*!
\brief set the number of remaining data to be transferred by the DMA
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set number
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] number: the number of remaining data to be transferred by the DMA, 0x00000000-0x0000FFFF
\param[out] none
\retval none
*/
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
}
/*!
\brief get the number of remaining data to be transferred by the DMA
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to set number
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval uint32_t: the number of remaining data to be transferred by the DMA, 0x00000000-0x0000FFFF
*/
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
return (uint32_t)DMA_CHCNT(dma_periph, channelx);
}
/*!
\brief configure priority level of DMA channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] priority: priority Level of this channel
only one parameter can be selected which is shown as below:
\arg DMA_PRIORITY_LOW: low priority
\arg DMA_PRIORITY_MEDIUM: medium priority
\arg DMA_PRIORITY_HIGH: high priority
\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
\param[out] none
\retval none
*/
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PRIO;
ctl |= priority;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief configure transfer data size of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] mwidth: transfer data width of memory
only one parameter can be selected which is shown as below:
\arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
\arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
\arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
\param[out] none
\retval none
*/
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_MWIDTH;
ctl |= mwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief configure transfer data size of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] pwidth: transfer data width of peripheral
only one parameter can be selected which is shown as below:
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
\param[out] none
\retval none
*/
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
{
uint32_t ctl;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
/* acquire DMA_CHxCTL register */
ctl = DMA_CHCTL(dma_periph, channelx);
/* assign regiser */
ctl &= ~DMA_CHXCTL_PWIDTH;
ctl |= pwidth;
DMA_CHCTL(dma_periph, channelx) = ctl;
}
/*!
\brief enable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
}
/*!
\brief disable next address increasement algorithm of memory
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/*!
\brief enable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
}
/*!
\brief disable next address increasement algorithm of peripheral
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[out] none
\retval none
*/
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
}
/*!
\brief configure the direction of data transfer on the channel
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] direction: specify the direction of data transfer
only one parameter can be selected which is shown as below:
\arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
\arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
\param[out] none
\retval none
*/
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
if(DMA_PERIPHERAL_TO_MEMORY == direction){
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
}else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
}
}
/*!
\brief check DMA flag is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_FLAG_G: global interrupt flag of channel
\arg DMA_FLAG_FTF: full transfer finish flag of channel
\arg DMA_FLAG_HTF: half transfer finish flag of channel
\arg DMA_FLAG_ERR: error flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
FlagStatus reval;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){
reval = SET;
}else{
reval = RESET;
}
return reval;
}
/*!
\brief clear a DMA channel flag
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to clear flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_FLAG_G: global interrupt flag of channel
\arg DMA_FLAG_FTF: full transfer finish flag of channel
\arg DMA_FLAG_HTF: half transfer finish flag of channel
\arg DMA_FLAG_ERR: error flag of channel
\param[out] none
\retval none
*/
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
/*!
\brief enable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to enbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) |= source;
}
/*!
\brief disable DMA interrupt
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] source: specify which interrupt to disbale
one or more parameters can be selected which are shown as below
\arg DMA_INT_FTF: channel full transfer finish interrupt
\arg DMA_INT_HTF: channel half transfer finish interrupt
\arg DMA_INT_ERR: channel error interrupt
\param[out] none
\retval none
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_CHCTL(dma_periph, channelx) &= ~source;
}
/*!
\brief check DMA flag and interrupt enable bit is set or not
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to get flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
switch(flag){
case DMA_INT_FLAG_FTF:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
break;
case DMA_INT_FLAG_HTF:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
break;
case DMA_INT_FLAG_ERR:
interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx);
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
break;
default:
DMA_WRONG_HANDLE
}
if(interrupt_flag && interrupt_enable){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear a DMA channel flag
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel to clear flag
only one parameter can be selected which is shown as below:
\arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4)
\param[in] flag: specify get which flag
only one parameter can be selected which is shown as below:
\arg DMA_INT_FLAG_G: global interrupt flag of channel
\arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel
\arg DMA_INT_FLAG_ERR: error interrupt flag of channel
\param[out] none
\retval none
*/
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){
DMA_WRONG_HANDLE
}
DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
}
/*!
\brief check whether peripheral and channels match
\param[in] dma_periph: DMAx(x=0,1)
\arg DMAx(x=0,1)
\param[in] channelx: specify which DMA channel
only one parameter can be selected which is shown as below:
\arg DMA_CHx(x=0..6)
\param[out] none
\retval none
*/
static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx)
{
ErrStatus val = SUCCESS;
if(DMA1 == dma_periph){
/* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */
if(channelx > DMA_CH4){
val = ERROR;
}
}
return val;
}

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/*!
\file gd32e50x_exmc.c
\brief EXMC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_exmc.h"
/* EXMC bank0 register reset value */
#define BANK0_SNCTL_REGION0_RESET ((uint32_t)0x000030DBU)
#define BANK0_SNCTL_REGION1_2_3_RESET ((uint32_t)0x000030D2U)
#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU)
/* EXMC bank1/2 register reset mask */
#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U)
#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000042U)
#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
/* EXMC bank3 register reset mask */
#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U)
#define BANK3_NPINTEN_RESET ((uint32_t)0x00000043U)
#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU)
#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU)
/* EXMC register bit offset */
#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U)
#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U)
#define SNCTL_WREN_OFFSET ((uint32_t)12U)
#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U)
#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
#define SNTCFG_DSET_OFFSET ((uint32_t)8U)
#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U)
#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U)
#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U)
#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U)
#define NPCTL_ECCEN_OFFSET ((uint32_t)6U)
#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U)
#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U)
#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U)
#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U)
#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U)
#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U)
#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U)
#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U)
#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U)
#define INTEN_INTS_OFFSET ((uint32_t)3U)
/*!
\brief deinitialize EXMC NOR/SRAM region
\param[in] exmc_norsram_region: select the region of bank0
only one parameter can be selected which is shown as below:
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
\param[out] none
\retval none
*/
void exmc_norsram_deinit(uint32_t exmc_norsram_region)
{
/* reset the registers */
if(EXMC_BANK0_NORSRAM_REGION0 == exmc_norsram_region){
EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET;
}else{
EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET;
}
EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET;
EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET;
}
/*!
\brief initialize exmc_norsram_parameter_struct with the default values
\param[in] none
\param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer
\retval none
*/
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
{
/* configure the structure with default values */
exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0;
exmc_norsram_init_struct->address_data_mux = ENABLE;
exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM;
exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B;
exmc_norsram_init_struct->burst_mode = DISABLE;
exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
exmc_norsram_init_struct->wrap_burst_mode = DISABLE;
exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
exmc_norsram_init_struct->memory_write = ENABLE;
exmc_norsram_init_struct->nwait_signal = ENABLE;
exmc_norsram_init_struct->extended_mode = DISABLE;
exmc_norsram_init_struct->asyn_wait = DISABLE;
exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE;
/* read/write timing configure */
exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK;
exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
/* write timing configure, when extended mode is used */
exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
exmc_norsram_init_struct->write_timing->bus_latency = 0xFU;
exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
}
/*!
\brief initialize EXMC NOR/SRAM region
\param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3
write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE
extended_mode: ENABLE or DISABLE
asyn_wait: ENABLE or DISABLE
nwait_signal: ENABLE or DISABLE
memory_write: ENABLE or DISABLE
nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING
wrap_burst_mode: ENABLE or DISABLE
nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
burst_mode: ENABLE or DISABLE
databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
address_data_mux: ENABLE or DISABLE
read_write_timing: struct exmc_norsram_timing_parameter_struct set the time
asyn_access_mode: EXMC_ACCESS_MODE_A,EXMC_ACCESS_MODE_B,EXMC_ACCESS_MODE_C,EXMC_ACCESS_MODE_D
syn_data_latency: EXMC_DATALAT_n_CLK,(n=2,..,17)
syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_n_CLK,(n=2,..,16)
bus_latency: 1,..,16
asyn_data_setuptime: 2,..,256
asyn_address_holdtime: 2,..,16
asyn_address_setuptime: 1,..,16
write_timing: struct exmc_norsram_timing_parameter_struct set the time
asyn_access_mode: EXMC_ACCESS_MODE_A,EXMC_ACCESS_MODE_B,EXMC_ACCESS_MODE_C,EXMC_ACCESS_MODE_D
syn_data_latency: EXMC_DATALAT_n_CLK,(n=2,..,17)
syn_clk_division: EXMC_SYN_CLOCK_RATIO_DISABLE, EXMC_SYN_CLOCK_RATIO_n_CLK,(n=2,..,16)
bus_latency: 1,..,16
asyn_data_setuptime: 2,..,256
asyn_address_holdtime: 2,..,16
asyn_address_setuptime: 1,..,16
\param[out] none
\retval none
*/
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
{
uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U;
/* get the register value */
snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region);
/* clear relative bits */
snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG |
EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT |
EXMC_SNCTL_SYNCWR ));
snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
exmc_norsram_init_struct->memory_type |
exmc_norsram_init_struct->databus_width |
(exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
exmc_norsram_init_struct->nwait_polarity |
(exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
exmc_norsram_init_struct->nwait_config |
(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
(exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
exmc_norsram_init_struct->write_mode;
sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )|
exmc_norsram_init_struct->read_write_timing->syn_clk_division |
exmc_norsram_init_struct->read_write_timing->syn_data_latency |
exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
/* nor flash access enable */
if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
snctl |= (uint32_t)EXMC_SNCTL_NREN;
}
/* extended mode configure */
if(ENABLE == exmc_norsram_init_struct->extended_mode){
snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET ) |
(((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD )|
(((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & EXMC_SNWTCFG_WDSET )|
(((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_SNWTCFG_WBUSLAT ) |
exmc_norsram_init_struct->write_timing->asyn_access_mode;
}else{
snwtcfg = BANK0_SNWTCFG_RESET;
}
/* configure the registers */
EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl;
EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg;
EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg;
}
/*!
\brief enable EXMC NOR/PSRAM bank region
\param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
\param[out] none
\retval none
*/
void exmc_norsram_enable(uint32_t exmc_norsram_region)
{
EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN;
}
/*!
\brief disable EXMC NOR/PSRAM bank region
\param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
\param[out] none
\retval none
*/
void exmc_norsram_disable(uint32_t exmc_norsram_region)
{
EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
}
/*!
\brief configure CRAM page size
\param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3)
\param[in] page_size: CRAM page size
only one parameter can be selected which is shown as below:
\arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access
\arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes
\arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes
\arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes
\arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes
\param[out] none
\retval none
*/
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size)
{
/* reset the bits */
EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS;
/* set the CPS bits */
EXMC_SNCTL(exmc_norsram_region) |= page_size;
}
/*!
\brief deinitialize EXMC NAND bank
\param[in] exmc_nand_bank: select the bank of NAND
only one parameter can be selected which is shown as below:
\arg EXMC_BANKx_NAND(x=1..2)
\param[out] none
\retval none
*/
void exmc_nand_deinit(uint32_t exmc_nand_bank)
{
/* EXMC_BANK1_NAND or EXMC_BANK2_NAND */
EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET;
EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET;
EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET;
EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET;
}
/*!
\brief initialize exmc_norsram_parameter_struct with the default values
\param[in] none
\param[out] the initialized struct exmc_norsram_parameter_struct pointer
\retval none
*/
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
{
/* configure the structure with default values */
exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND;
exmc_nand_init_struct->wait_feature = DISABLE;
exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B;
exmc_nand_init_struct->ecc_logic = DISABLE;
exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES;
exmc_nand_init_struct->ctr_latency = 0x0U;
exmc_nand_init_struct->atr_latency = 0x0U;
exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU;
exmc_nand_init_struct->common_space_timing->waittime = 0xFCU;
exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU;
exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU;
exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU;
exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU;
exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU;
exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
}
/*!
\brief initialize EXMC NAND bank
\param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter
nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND
ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096
atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16
ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16
ecc_logic: ENABLE or DISABLE
databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B
wait_feature: ENABLE or DISABLE
common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
databus_hiztime: 1,..,255
holdtime: 1,..,254
waittime: 2,..,255
setuptime: 1,..,255
attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
databus_hiztime: 1,..,255
holdtime: 1,..,254
waittime: 2,..,255
setuptime: 1,..,255
\param[out] none
\retval none
*/
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct)
{
uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U;
npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)|
EXMC_NPCTL_NDTP |
exmc_nand_init_struct->databus_width |
(exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)|
exmc_nand_init_struct->ecc_size |
exmc_nand_init_struct->ctr_latency |
exmc_nand_init_struct->atr_latency;
npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) |
(((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
(((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
(((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) |
(((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
/* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */
EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl;
EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg;
EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg;
}
/*!
\brief enable NAND bank
\param[in] exmc_nand_bank: specifie the NAND bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANKx_NAND(x=1,2)
\param[out] none
\retval none
*/
void exmc_nand_enable(uint32_t exmc_nand_bank)
{
EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN;
}
/*!
\brief disable NAND bank
\param[in] exmc_nand_bank: specifie the NAND bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANKx_NAND(x=1,2)
\param[out] none
\retval none
*/
void exmc_nand_disable(uint32_t exmc_nand_bank)
{
EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_NDBKEN);
}
/*!
\brief enable or disable the EXMC NAND ECC function
\param[in] exmc_nand_bank: specifie the NAND bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANKx_NAND(x=1,2)
\param[in] newvalue: ENABLE or DISABLE
\param[out] none
\retval none
*/
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue)
{
if (ENABLE == newvalue){
/* enable the selected NAND bank ECC function */
EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN;
}else{
/* disable the selected NAND bank ECC function */
EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_ECCEN);
}
}
/*!
\brief get the EXMC ECC value
\param[in] exmc_nand_bank: specifie the NAND bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANKx_NAND(x=1,2)
\param[out] none
\retval the error correction code(ECC) value
*/
uint32_t exmc_ecc_get(uint32_t exmc_nand_bank)
{
return (EXMC_NECC(exmc_nand_bank));
}
/*!
\brief deinitialize EXMC PC card bank
\param[in] none
\param[out] none
\retval none
*/
void exmc_pccard_deinit(void)
{
/* EXMC_BANK3_PCCARD */
EXMC_NPCTL3 = BANK3_NPCTL_RESET;
EXMC_NPINTEN3 = BANK3_NPINTEN_RESET;
EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET;
EXMC_NPATCFG3 = BANK3_NPATCFG_RESET;
EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET;
}
/*!
\brief initialize exmc_pccard_parameter_struct parameter with the default values
\param[in] none
\param[out] the initialized struct exmc_pccard_parameter_struct pointer
\retval none
*/
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
{
/* configure the structure with default values */
exmc_pccard_init_struct->wait_feature = DISABLE;
exmc_pccard_init_struct->ctr_latency = 0x0U;
exmc_pccard_init_struct->atr_latency = 0x0U;
exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU;
exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU;
exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU;
exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU;
exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU;
exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU;
exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU;
exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU;
exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU;
exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU;
exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU;
exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU;
}
/*!
\brief initialize EXMC PC card bank
\param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter
atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16
ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16
wait_feature: ENABLE or DISABLE
common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
databus_hiztime: 1,..,255
holdtime: 1,..,254
waittime: 2,..,255
setuptime: 1,..,255
attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time
databus_hiztime: 1,..,255
holdtime: 1,..,254
waittime: 2,..,255
setuptime: 1,..,255
io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time
databus_hiztime: 0,..,255
holdtime: 1,..,255
waittime: 2,..,256
setuptime: 1,..,256
\param[out] none
\retval none
*/
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct)
{
/* configure the EXMC bank3 PC card control register */
EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) |
EXMC_NAND_DATABUS_WIDTH_16B |
exmc_pccard_init_struct->ctr_latency |
exmc_pccard_init_struct->atr_latency ;
/* configure the EXMC bank3 PC card common space timing configuration register */
EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) |
(((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) |
((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) |
(((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ );
/* configure the EXMC bank3 PC card attribute space timing configuration register */
EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) |
(((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) |
((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )|
(((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ );
/* configure the EXMC bank3 PC card io space timing configuration register */
EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) |
(((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) |
((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )|
((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ );
}
/*!
\brief enable PC Card Bank
\param[in] none
\param[out] none
\retval none
*/
void exmc_pccard_enable(void)
{
EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN;
}
/*!
\brief disable PC Card Bank
\param[in] none
\param[out] none
\retval none
*/
void exmc_pccard_disable(void)
{
EXMC_NPCTL3 &= (~EXMC_NPCTL_NDBKEN);
}
/*!
\brief enable EXMC interrupt
\param[in] exmc_bank: specifies the NAND bank,PC card bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK1_NAND: the NAND bank1
\arg EXMC_BANK2_NAND: the NAND bank2
\arg EXMC_BANK3_PCCARD: the PC card bank
\param[in] interrupt: EXMC interrupt flag
only one parameter can be selected which are shown as below:
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and corresponding flag
\param[out] none
\retval none
*/
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt)
{
/* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) |= interrupt;
}
/*!
\brief disable EXMC interrupt
\param[in] exmc_bank: specifies the NAND bank , PC card bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK1_NAND: the NAND bank1
\arg EXMC_BANK2_NAND: the NAND bank2
\arg EXMC_BANK3_PCCARD: the PC card bank
\param[in] interrupt: EXMC interrupt flag
only one parameter can be selected which are shown as below:
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and corresponding flag
\param[out] none
\retval none
*/
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt)
{
/* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) &= (~interrupt);
}
/*!
\brief get EXMC flag status
\param[in] exmc_bank: specifies the NAND bank , PC card bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK1_NAND: the NAND bank1
\arg EXMC_BANK2_NAND: the NAND bank2
\arg EXMC_BANK3_PCCARD: the PC Card bank
\param[in] flag: EXMC status and flag
only one parameter can be selected which are shown as below:
\arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
\arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
\arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
\arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag)
{
uint32_t status = 0x00000000U;
/* NAND bank1,bank2 or PC card bank3 */
status = EXMC_NPINTEN(exmc_bank);
if ((status & flag) != (uint32_t)flag ){
/* flag is reset */
return RESET;
}else{
/* flag is set */
return SET;
}
}
/*!
\brief clear EXMC flag status
\param[in] exmc_bank: specifie the NAND bank , PCCARD bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK1_NAND: the NAND bank1
\arg EXMC_BANK2_NAND: the NAND bank2
\arg EXMC_BANK3_PCCARD: the PC card bank
\param[in] flag: EXMC status and flag
only one parameter can be selected which are shown as below:
\arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status
\arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status
\arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status
\arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag
\param[out] none
\retval none
*/
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag)
{
/* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) &= (~flag);
}
/*!
\brief get EXMC interrupt flag
\param[in] exmc_bank: specifies the NAND bank , PC card bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK1_NAND: the NAND bank1
\arg EXMC_BANK2_NAND: the NAND bank2
\arg EXMC_BANK3_PCCARD: the PC card bank
\param[in] interrupt: EXMC interrupt flag
only one parameter can be selected which are shown as below:
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and corresponding flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt)
{
uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U;
/* NAND bank1,bank2 or PC card bank3 */
status = EXMC_NPINTEN(exmc_bank);
interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET));
interrupt_enable = (status & interrupt);
if ((interrupt_enable) && (interrupt_state)){
/* interrupt flag is set */
return SET;
}else{
/* interrupt flag is reset */
return RESET;
}
}
/*!
\brief clear EXMC interrupt flag
\param[in] exmc_bank: specifies the NAND bank , PC card bank
only one parameter can be selected which is shown as below:
\arg EXMC_BANK1_NAND: the NAND bank1
\arg EXMC_BANK2_NAND: the NAND bank2
\arg EXMC_BANK3_PCCARD: the PC card bank
\param[in] interrupt: EXMC interrupt flag
only one parameter can be selected which are shown as below:
\arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and corresponding flag
\arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and corresponding flag
\param[out] none
\retval none
*/
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt)
{
/* NAND bank1,bank2 or PC card bank3 */
EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET);
}

253
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_exti.c Normal file
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/*!
\file gd32e50x_exti.c
\brief EXTI driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_exti.h"
/*!
\brief deinitialize the EXTI
\param[in] none
\param[out] none
\retval none
*/
void exti_deinit(void)
{
/* reset the value of all the EXTI registers */
EXTI_INTEN = (uint32_t)0x00000000U;
EXTI_EVEN = (uint32_t)0x00000000U;
EXTI_RTEN = (uint32_t)0x00000000U;
EXTI_FTEN = (uint32_t)0x00000000U;
EXTI_SWIEV = (uint32_t)0x00000000U;
}
/*!
\brief initialize the EXTI
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[in] mode: interrupt or event mode, refer to exti_mode_enum
only one parameter can be selected which is shown as below:
\arg EXTI_INTERRUPT: interrupt mode
\arg EXTI_EVENT: event mode
\param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum
only one parameter can be selected which is shown as below:
\arg EXTI_TRIG_RISING: rising edge trigger
\arg EXTI_TRIG_FALLING: falling trigger
\arg EXTI_TRIG_BOTH: rising and falling trigger
\arg EXTI_TRIG_NONE: without rising edge or falling edge trigger
\param[out] none
\retval none
*/
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
{
/* reset the EXTI line x */
EXTI_INTEN &= ~(uint32_t)linex;
EXTI_EVEN &= ~(uint32_t)linex;
EXTI_RTEN &= ~(uint32_t)linex;
EXTI_FTEN &= ~(uint32_t)linex;
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
switch(mode){
case EXTI_INTERRUPT:
EXTI_INTEN |= (uint32_t)linex;
break;
case EXTI_EVENT:
EXTI_EVEN |= (uint32_t)linex;
break;
default:
break;
}
/* set the EXTI trigger type */
switch(trig_type){
case EXTI_TRIG_RISING:
EXTI_RTEN |= (uint32_t)linex;
EXTI_FTEN &= ~(uint32_t)linex;
break;
case EXTI_TRIG_FALLING:
EXTI_RTEN &= ~(uint32_t)linex;
EXTI_FTEN |= (uint32_t)linex;
break;
case EXTI_TRIG_BOTH:
EXTI_RTEN |= (uint32_t)linex;
EXTI_FTEN |= (uint32_t)linex;
break;
case EXTI_TRIG_NONE:
default:
break;
}
}
/*!
\brief enable the interrupts from EXTI line x
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_interrupt_enable(exti_line_enum linex)
{
EXTI_INTEN |= (uint32_t)linex;
}
/*!
\brief disable the interrupt from EXTI line x
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_interrupt_disable(exti_line_enum linex)
{
EXTI_INTEN &= ~(uint32_t)linex;
}
/*!
\brief enable the events from EXTI line x
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_event_enable(exti_line_enum linex)
{
EXTI_EVEN |= (uint32_t)linex;
}
/*!
\brief disable the events from EXTI line x
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_event_disable(exti_line_enum linex)
{
EXTI_EVEN &= ~(uint32_t)linex;
}
/*!
\brief enable EXTI software interrupt event
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_software_interrupt_enable(exti_line_enum linex)
{
EXTI_SWIEV |= (uint32_t)linex;
}
/*!
\brief disable EXTI software interrupt event
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_software_interrupt_disable(exti_line_enum linex)
{
EXTI_SWIEV &= ~(uint32_t)linex;
}
/*!
\brief get EXTI line x pending flag
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval FlagStatus: status of flag (RESET or SET)
*/
FlagStatus exti_flag_get(exti_line_enum linex)
{
if(RESET != (EXTI_PD & (uint32_t)linex)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear EXTI line x pending flag
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_flag_clear(exti_line_enum linex)
{
EXTI_PD = (uint32_t)linex;
}
/*!
\brief get EXTI line x flag when the interrupt flag is set
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval FlagStatus: status of flag (RESET or SET)
*/
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
{
uint32_t flag_left, flag_right;
flag_left = EXTI_PD & (uint32_t)linex;
flag_right = EXTI_INTEN & (uint32_t)linex;
if((RESET != flag_left) && (RESET != flag_right)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear EXTI line x pending flag
\param[in] linex: EXTI line number, refer to exti_line_enum
only one parameter can be selected which is shown as below:
\arg EXTI_x (x=0..21): EXTI line x
\param[out] none
\retval none
*/
void exti_interrupt_flag_clear(exti_line_enum linex)
{
EXTI_PD = (uint32_t)linex;
}

876
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_fmc.c Normal file
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@@ -0,0 +1,876 @@
/*!
\file gd32e50x_fmc.c
\brief FMC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_fmc.h"
/* FMC mask */
#define LOW_8BITS_MASK ((uint32_t)0x000000FFU)
#define HIGH_8BITS_MASK ((uint32_t)0x0000FF00U)
#define LOW_8BITS_MASK1 ((uint32_t)0x00FF0000U)
#define HIGH_8BITS_MASK1 ((uint32_t)0xFF000000U)
#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU)
#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U)
/* USER of option bytes mask */
#define OB_USER_MASK ((uint8_t)0xF8U)
/* default offset */
#define FMC_OBSTAT_USER_OFFSET 2U
#define FMC_OBSTAT_DATA_OFFSET 10U
/* return the FMC state */
static fmc_state_enum fmc_state_get(void);
/* check FMC ready or not */
static fmc_state_enum fmc_ready_wait(uint32_t timeout);
/*!
\brief unlock the main FMC operation
it is better to used in pairs with fmc_lock
\param[in] none
\param[out] none
\retval none
*/
void fmc_unlock(void)
{
if(RESET != (FMC_CTL & FMC_CTL_LK)){
/* write the FMC unlock key */
FMC_KEY = UNLOCK_KEY0;
FMC_KEY = UNLOCK_KEY1;
}
}
/*!
\brief lock the main FMC operation
it is better to used in pairs with fmc_unlock after an operation
\param[in] none
\param[out] none
\retval none
*/
void fmc_lock(void)
{
/* set the LK bit */
FMC_CTL |= FMC_CTL_LK;
}
/*!
\brief set the wait state
\param[in] wscnt: wait state
only one parameter can be selected which is shown as below:
\arg FMC_WAIT_STATE_0: 0 wait state added
\arg FMC_WAIT_STATE_1: 1 wait state added
\arg FMC_WAIT_STATE_2: 2 wait state added
\arg FMC_WAIT_STATE_3: 3 wait state added
\arg FMC_WAIT_STATE_4: 4 wait state added
\param[out] none
\retval none
*/
void fmc_wscnt_set(uint32_t wscnt)
{
uint32_t ws;
ws = FMC_WS;
/* set the wait state counter value */
ws &= ~FMC_WS_WSCNT;
FMC_WS = (ws | wscnt);
}
/*!
\brief enable pre-fetch
\param[in] none
\param[out] none
\retval none
*/
void fmc_prefetch_enable(void)
{
FMC_WS |= FMC_WS_PFEN;
}
/*!
\brief disable pre-fetch
\param[in] none
\param[out] none
\retval none
*/
void fmc_prefetch_disable(void)
{
FMC_WS &= ~FMC_WS_PFEN;
}
/*!
\brief enable IBUS cache
\param[in] none
\param[out] none
\retval none
*/
void fmc_ibus_enable(void)
{
FMC_WS |= FMC_WS_ICEN;
}
/*!
\brief disable IBUS cache
\param[in] none
\param[out] none
\retval none
*/
void fmc_ibus_disable(void)
{
FMC_WS &= ~FMC_WS_ICEN;
}
/*!
\brief reset IBUS cache
\param[in] none
\param[out] none
\retval none
*/
void fmc_ibus_reset(void)
{
FMC_WS |= FMC_WS_ICRST;
}
/*!
\brief enable DBUS cache
\param[in] none
\param[out] none
\retval none
*/
void fmc_dbus_enable(void)
{
FMC_WS |= FMC_WS_DCEN;
}
/*!
\brief disable DBUS cache
\param[in] none
\param[out] none
\retval none
*/
void fmc_dbus_disable(void)
{
FMC_WS &= ~FMC_WS_DCEN;
}
/*!
\brief reset DBUS cache
\param[in] none
\param[out] none
\retval none
*/
void fmc_dbus_reset(void)
{
FMC_WS |= FMC_WS_DCRST;
}
/*!
\brief FMC erase page
\param[in] page_address: target page address
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
*/
fmc_state_enum fmc_page_erase(uint32_t page_address)
{
fmc_state_enum fmc_state;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* start page erase */
FMC_CTL |= FMC_CTL_PER;
FMC_ADDR = page_address;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the PER bit */
FMC_CTL &= ~FMC_CTL_PER;
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief FMC erase whole chip
\param[in] none
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
*/
fmc_state_enum fmc_mass_erase(void)
{
fmc_state_enum fmc_state;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* start chip erase */
FMC_CTL |= FMC_CTL_MER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the MER bit */
FMC_CTL &= ~FMC_CTL_MER;
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief FMC program a word at the corresponding address
\param[in] address: address to program
\param[in] data: word to program
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
*/
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
{
fmc_state_enum fmc_state;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* set the PG bit to start program */
FMC_CTL |= FMC_CTL_PG;
REG32(address) = data;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the PG bit */
FMC_CTL &= ~FMC_CTL_PG;
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief unlock the option bytes operation
it is better to used in pairs with ob_lock
\param[in] none
\param[out] none
\retval none
*/
void ob_unlock(void)
{
if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){
/* write the FMC ob unlock key */
FMC_OBKEY = UNLOCK_KEY0;
FMC_OBKEY = UNLOCK_KEY1;
}
}
/*!
\brief lock the option bytes operation
it is better to used in pairs with ob_unlock after an operation
\param[in] none
\param[out] none
\retval none
*/
void ob_lock(void)
{
/* reset the OBWEN bit */
FMC_CTL &= ~FMC_CTL_OBWEN;
}
/*!
\brief erase the option bytes
programmer must ensure FMC & option bytes are both unlocked before calling this function
\param[in] none
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
\arg FMC_OB_HSPC: high security protection
*/
fmc_state_enum ob_erase(void)
{
uint32_t temp_spc;
fmc_state_enum fmc_state;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
temp_spc = OB_SPC_USER;
/* check the option bytes security protection value */
if((RESET != ob_security_protection_flag_get()) && (FMC_HSPC == (temp_spc & LOW_8BITS_MASK))){
fmc_state = FMC_OB_HSPC;
}
if(FMC_READY == fmc_state){
/* start erase the option bytes */
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit and enable the option bytes programming */
FMC_CTL &= ~FMC_CTL_OBER;
/* set the OBPG bit */
FMC_CTL |= FMC_CTL_OBPG;
/* restore the last get option bytes security protection code */
OB_SPC_USER = (temp_spc & LOW_8BITS_MASK) | LOW_8BITS_MASK1;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
/* reset the OBPG bit */
FMC_CTL &= ~FMC_CTL_OBPG;
}else{
/* reset the OBER bit */
FMC_CTL &= ~FMC_CTL_OBER;
}
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief enable write protection
programmer must ensure FMC & option bytes are both unlocked before calling this function
\param[in] ob_wp: specify sector to be write protected
only one parameter can be selected which are shown as below:
\arg OB_WP_NONE: disable all write protection
\arg OB_WP_x(x=0..31): write protect specify sector
\arg OB_WP_ALL: write protect all sector
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
\arg FMC_OB_HSPC: high security protection
*/
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
{
uint32_t temp_spc;
uint8_t i;
uint32_t op_byte[4];
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
temp_spc = OB_SPC_USER;
/* check the option bytes security protection value */
if((RESET != ob_security_protection_flag_get()) && (FMC_HSPC == (temp_spc & LOW_8BITS_MASK))){
fmc_state = FMC_OB_HSPC;
}
for(i = 0U; i < 4U; i++){
op_byte[i] = OP_BYTE(i);
}
ob_wp = (uint32_t)(~ob_wp);
op_byte[2] = (ob_wp & LOW_8BITS_MASK) | ((ob_wp & HIGH_8BITS_MASK) << 8);
op_byte[3] = ((ob_wp & LOW_8BITS_MASK1) >> 16) | ((ob_wp & HIGH_8BITS_MASK1) >> 8);
if(FMC_READY == fmc_state){
/* start erase the option byte */
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit and enable the option bytes programming */
FMC_CTL &= ~FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_OBPG;
for(i = 0U; i < 4U; i++){
OP_BYTE(i) = op_byte[i];
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY != fmc_state){
break;
}
}
/* reset the OBPG bit */
FMC_CTL &= ~FMC_CTL_OBPG;
}else{
/* reset the OBER bit */
FMC_CTL &= ~FMC_CTL_OBER;
}
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief configure security protection
programmer must ensure FMC & option bytes are both unlocked before calling this function
\param[in] ob_spc: specify security protection
only one parameter can be selected which is shown as below:
\arg FMC_NSPC: no security protection
\arg FMC_LSPC: low security protection
\arg FMC_HSPC: high security protection
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
\arg FMC_OB_HSPC: high security protection
*/
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
{
uint32_t temp_spc;
uint8_t i;
uint32_t op_byte[4];
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
temp_spc = OB_SPC_USER & LOW_16BITS_MASK;
/* check the option bytes security protection value */
if((RESET != ob_security_protection_flag_get()) && (FMC_HSPC == (temp_spc & LOW_8BITS_MASK))){
fmc_state = FMC_OB_HSPC;
}
for(i = 0U; i < 4U; i++){
op_byte[i] = OP_BYTE(i);
}
op_byte[0] = ((uint32_t)(ob_spc)) | ((op_byte[0] & HIGH_16BITS_MASK));
if(FMC_READY == fmc_state){
/* start erase the option bytes */
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit and enable the option bytes programming */
FMC_CTL &= ~FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_OBPG;
for(i = 0U; i < 4U; i++){
OP_BYTE(i) = op_byte[i];
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY != fmc_state){
break;
}
}
/* reset the OBPG bit */
FMC_CTL &= ~FMC_CTL_OBPG;
}else{
/* reset the OBER bit */
FMC_CTL &= ~FMC_CTL_OBER;
}
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief program option bytes USER
programmer must ensure FMC & option bytes are both unlocked before calling this function
\param[in] ob_fwdgt: option bytes free watchdog value
only one parameter can be selected which is shown as below:
\arg OB_FWDGT_SW: software free watchdog
\arg OB_FWDGT_HW: hardware free watchdog
\param[in] ob_deepsleep: option bytes deepsleep reset value
only one parameter can be selected which is shown as below:
\arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
\arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
\param[in] ob_stdby:option bytes standby reset value
only one parameter can be selected which is shown as below:
\arg OB_STDBY_NRST: no reset when entering standby mode
\arg OB_STDBY_RST: generate a reset instead of entering standby mode
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
\arg FMC_OB_HSPC: high security protection
*/
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby)
{
uint32_t temp_spc;
uint8_t temp;
uint8_t i;
uint32_t op_byte[4];
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
temp_spc = OB_SPC_USER;
/* check the option bytes security protection value */
if((RESET != ob_security_protection_flag_get()) && (FMC_HSPC == (temp_spc & LOW_8BITS_MASK))){
fmc_state = FMC_OB_HSPC;
}
for(i = 0U; i < 4U; i++){
op_byte[i] = OP_BYTE(i);
}
temp = ((uint8_t)((uint8_t)((uint8_t)(ob_fwdgt) | ob_deepsleep) | ob_stdby) | (OB_USER_MASK));
op_byte[0] = ((uint32_t)(temp) << 16U) | ((op_byte[0] & LOW_16BITS_MASK));
if(FMC_READY == fmc_state){
/* start erase the option bytes */
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit and enable the option bytes programming */
FMC_CTL &= ~FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_OBPG;
for(i = 0U; i < 4U; i++){
OP_BYTE(i) = op_byte[i];
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY != fmc_state){
break;
}
}
/* reset the OBPG bit */
FMC_CTL &= ~FMC_CTL_OBPG;
}else{
/* reset the OBER bit */
FMC_CTL &= ~FMC_CTL_OBER;
}
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief program option bytes DATA
\param[in] data: the byte to be programmed
\param[out] none
\retval state of FMC
\arg FMC_READY: the operation has been completed
\arg FMC_PGERR: program error
\arg FMC_PGAERR: program alignment error
\arg FMC_WPERR: erase/program protection error
\arg FMC_TOERR: timeout error
\arg FMC_OB_HSPC: high security protection
*/
fmc_state_enum ob_data_program(uint16_t ob_data)
{
uint32_t temp_spc;
uint8_t i;
uint32_t op_byte[4];
fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
temp_spc = OB_SPC_USER;
/* check the option bytes security protection value */
if((RESET != ob_security_protection_flag_get()) && (FMC_HSPC == (temp_spc & LOW_8BITS_MASK))){
fmc_state = FMC_OB_HSPC;
}
for(i = 0U; i < 4U; i++){
op_byte[i] = OP_BYTE(i);
}
op_byte[1] = (uint32_t)((ob_data & LOW_8BITS_MASK) | ((ob_data & HIGH_8BITS_MASK) << 8));
if(FMC_READY == fmc_state){
/* start erase the option bytes */
FMC_CTL |= FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_START;
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY == fmc_state){
/* reset the OBER bit and enable the option bytes programming */
FMC_CTL &= ~FMC_CTL_OBER;
FMC_CTL |= FMC_CTL_OBPG;
for(i = 0U; i < 4U; i++){
OP_BYTE(i) = op_byte[i];
/* wait for the FMC ready */
fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT);
if(FMC_READY != fmc_state){
break;
}
}
/* reset the OBPG bit */
FMC_CTL &= ~FMC_CTL_OBPG;
}else{
/* reset the OBER bit */
FMC_CTL &= ~FMC_CTL_OBER;
}
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief get the value of option bytes USER
\param[in] none
\param[out] none
\retval the option bytes USER value
*/
uint8_t ob_user_get(void)
{
/* return the FMC user option bytes value */
return (uint8_t)(FMC_OBSTAT >> FMC_OBSTAT_USER_OFFSET);
}
/*!
\brief get the value of option bytes DATA
\param[in] none
\param[out] none
\retval the option bytes DATA value
*/
uint16_t ob_data_get(void)
{
return (uint16_t)(FMC_OBSTAT >> FMC_OBSTAT_DATA_OFFSET);
}
/*!
\brief get the value of option bytes write protection
\param[in] none
\param[out] none
\retval the write protection option bytes value
*/
uint32_t ob_write_protection_get(void)
{
/* return the FMC write protection option bytes value */
return FMC_WP;
}
/*!
\brief get the FMC option bytes security protection state
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus ob_security_protection_flag_get(void)
{
FlagStatus spc_state = RESET;
if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
spc_state = SET;
}else{
spc_state = RESET;
}
return spc_state;
}
/*!
\brief get FMC flag status
\param[in] flag: FMC flag
only one parameter can be selected which is shown as below:
\arg FMC_FLAG_BUSY: FMC busy flag
\arg FMC_FLAG_PGERR: FMC program error flag
\arg FMC_FLAG_PGAERR: FMC program alignment error flag
\arg FMC_FLAG_WPERR: FMC erase/program protection error flag
\arg FMC_FLAG_END: FMC end of operation flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fmc_flag_get(uint32_t flag)
{
FlagStatus status = RESET;
if(FMC_STAT & flag){
status = SET;
}
/* return the state of corresponding FMC flag */
return status;
}
/*!
\brief clear the FMC flag
\param[in] flag: FMC flag
only one parameter can be selected which is shown as below:
\arg FMC_FLAG_PGERR: FMC program error flag
\arg FMC_FLAG_PGAERR: FMC program alignment error flag
\arg FMC_FLAG_WPERR: FMC erase/program protection error flag
\arg FMC_FLAG_END: FMC end of operation flag
\param[out] none
\retval none
*/
void fmc_flag_clear(uint32_t flag)
{
/* clear the flags */
FMC_STAT = flag;
}
/*!
\brief enable FMC interrupt
\param[in] interrupt: the FMC interrupt
only one parameter can be selected which is shown as below:
\arg FMC_INT_END: FMC end of operation interrupt
\arg FMC_INT_ERR: FMC error interrupt
\param[out] none
\retval none
*/
void fmc_interrupt_enable(uint32_t interrupt)
{
FMC_CTL |= interrupt;
}
/*!
\brief disable FMC interrupt
\param[in] interrupt: the FMC interrupt
only one parameter can be selected which is shown as below:
\arg FMC_INT_END: FMC end of operation interrupt
\arg FMC_INT_ERR: FMC error interrupt
\param[out] none
\retval none
*/
void fmc_interrupt_disable(uint32_t interrupt)
{
FMC_CTL &= ~(uint32_t)interrupt;
}
/*!
\brief get FMC interrupt flag
\param[in] flag: FMC interrupt flag
only one parameter can be selected which is shown as below:
\arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag
\arg FMC_INT_FLAG_PGAERR: FMC program alignment error interrupt flag
\arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag
\arg FMC_INT_FLAG_END: FMC end of operation interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fmc_interrupt_flag_get(uint32_t flag)
{
FlagStatus status = RESET;
if(FMC_STAT & flag){
status = SET;
}
/* return the state of corresponding FMC flag */
return status;
}
/*!
\brief clear FMC interrupt flag
\param[in] flag: FMC interrupt flag
one or more parameters can be selected which is shown as below:
\arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag
\arg FMC_INT_FLAG_PGAERR: FMC program alignment error interrupt flag
\arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag
\arg FMC_INT_FLAG_END: FMC end of operation interrupt flag
\param[out] none
\retval none
*/
void fmc_interrupt_flag_clear(uint32_t flag)
{
/* clear the flag */
FMC_STAT = flag;
}
/*!
\brief get the FMC state
\param[in] none
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
static fmc_state_enum fmc_state_get(void)
{
fmc_state_enum fmc_state = FMC_READY;
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){
fmc_state = FMC_BUSY;
}else{
if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){
fmc_state = FMC_WPERR;
}else{
if((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGERR))){
fmc_state = FMC_PGERR;
}else{
if((uint32_t)0x00U != (FMC_STAT & (FMC_STAT_PGAERR))){
fmc_state = FMC_PGAERR;
}
}
}
}
/* return the FMC state */
return fmc_state;
}
/*!
\brief check whether FMC is ready or not
\param[in] timeout: timeout count
\param[out] none
\retval state of FMC, refer to fmc_state_enum
*/
static fmc_state_enum fmc_ready_wait(uint32_t timeout)
{
fmc_state_enum fmc_state = FMC_BUSY;
/* wait for FMC ready */
do{
/* get FMC state */
fmc_state = fmc_state_get();
timeout--;
}while((FMC_BUSY == fmc_state) && (0x00U != timeout));
if(FMC_BUSY == fmc_state){
fmc_state = FMC_TOERR;
}
/* return the FMC state */
return fmc_state;
}

221
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_fwdgt.c Normal file
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/*!
\file gd32e50x_fwdgt.c
\brief FWDGT driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_fwdgt.h"
/* write value to FWDGT_CTL_CMD bit field */
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
/* write value to FWDGT_RLD_RLD bit field */
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
/*!
\brief enable write access to FWDGT_PSC and FWDGT_RLD
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_write_enable(void)
{
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
}
/*!
\brief disable write access to FWDGT_PSC and FWDGT_RLD
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_write_disable(void)
{
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
}
/*!
\brief start the free watchdog timer counter
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_enable(void)
{
FWDGT_CTL = FWDGT_KEY_ENABLE;
}
/*!
\brief configure the FWDGT counter prescaler value
\param[in] prescaler_value: specify prescaler value
only one parameter can be selected which is shown as below:
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
\param[out] none
\retval ErrStatus: ERROR or SUCCESS
*/
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
{
uint32_t timeout = FWDGT_PSC_TIMEOUT;
uint32_t flag_status = RESET;
/* enable write access to FWDGT_PSC */
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
/* wait until the PUD flag to be reset */
do{
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
} while((--timeout > 0U) && (RESET != flag_status));
if(RESET != flag_status){
return ERROR;
}
/* configure FWDGT */
FWDGT_PSC = (uint32_t)prescaler_value;
return SUCCESS;
}
/*!
\brief configure the FWDGT counter reload value
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
\param[out] none
\retval ErrStatus: ERROR or SUCCESS
*/
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
{
uint32_t timeout = FWDGT_RLD_TIMEOUT;
uint32_t flag_status = RESET;
/* enable write access to FWDGT_RLD */
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
/* wait until the RUD flag to be reset */
do{
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
return ERROR;
}
FWDGT_RLD = RLD_RLD(reload_value);
return SUCCESS;
}
/*!
\brief configure counter reload value, and prescaler divider value
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
\param[in] prescaler_div: FWDGT prescaler value
only one parameter can be selected which is shown as below:
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
\param[out] none
\retval ErrStatus: ERROR or SUCCESS
*/
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
{
uint32_t timeout = FWDGT_PSC_TIMEOUT;
uint32_t flag_status = RESET;
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
/* wait until the PUD flag to be reset */
do{
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
return ERROR;
}
/* configure FWDGT */
FWDGT_PSC = (uint32_t)prescaler_div;
timeout = FWDGT_RLD_TIMEOUT;
/* wait until the RUD flag to be reset */
do{
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
}while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
if ((uint32_t)RESET != flag_status){
return ERROR;
}
FWDGT_RLD = RLD_RLD(reload_value);
/* reload the counter */
FWDGT_CTL = FWDGT_KEY_RELOAD;
return SUCCESS;
}
/*!
\brief reload the counter of FWDGT
\param[in] none
\param[out] none
\retval none
*/
void fwdgt_counter_reload(void)
{
FWDGT_CTL = FWDGT_KEY_RELOAD;
}
/*!
\brief get flag state of FWDGT
\param[in] flag: flag to get
only one parameter can be selected which is shown as below:
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus fwdgt_flag_get(uint16_t flag)
{
if(RESET != (FWDGT_STAT & flag)){
return SET;
}
return RESET;
}

693
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/*!
\file gd32e50x_gpio.c
\brief GPIO driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_gpio.h"
#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/
#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */
#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */
#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */
#define PCF_SWJCFG_MASK ((uint32_t)0xF8FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */
#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */
#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */
#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */
#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/
/*!
\brief reset GPIO port
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[out] none
\retval none
*/
void gpio_deinit(uint32_t gpio_periph)
{
switch(gpio_periph){
case GPIOA:
/* reset GPIOA */
rcu_periph_reset_enable(RCU_GPIOARST);
rcu_periph_reset_disable(RCU_GPIOARST);
break;
case GPIOB:
/* reset GPIOB */
rcu_periph_reset_enable(RCU_GPIOBRST);
rcu_periph_reset_disable(RCU_GPIOBRST);
break;
case GPIOC:
/* reset GPIOC */
rcu_periph_reset_enable(RCU_GPIOCRST);
rcu_periph_reset_disable(RCU_GPIOCRST);
break;
case GPIOD:
/* reset GPIOD */
rcu_periph_reset_enable(RCU_GPIODRST);
rcu_periph_reset_disable(RCU_GPIODRST);
break;
case GPIOE:
/* reset GPIOE */
rcu_periph_reset_enable(RCU_GPIOERST);
rcu_periph_reset_disable(RCU_GPIOERST);
break;
case GPIOF:
/* reset GPIOF */
rcu_periph_reset_enable(RCU_GPIOFRST);
rcu_periph_reset_disable(RCU_GPIOFRST);
break;
case GPIOG:
/* reset GPIOG */
rcu_periph_reset_enable(RCU_GPIOGRST);
rcu_periph_reset_disable(RCU_GPIOGRST);
break;
default:
break;
}
}
/*!
\brief reset alternate function I/O(AFIO)
\param[in] none
\param[out] none
\retval none
*/
void gpio_afio_deinit(void)
{
rcu_periph_reset_enable(RCU_AFRST);
rcu_periph_reset_disable(RCU_AFRST);
}
/*!
\brief GPIO parameter initialization
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] mode: gpio pin mode
only one parameter can be selected which is shown as below:
\arg GPIO_MODE_AIN: analog input mode
\arg GPIO_MODE_IN_FLOATING: floating input mode
\arg GPIO_MODE_IPD: pull-down input mode
\arg GPIO_MODE_IPU: pull-up input mode
\arg GPIO_MODE_OUT_OD: GPIO output with open-drain
\arg GPIO_MODE_OUT_PP: GPIO output with push-pull
\arg GPIO_MODE_AF_OD: AFIO output with open-drain
\arg GPIO_MODE_AF_PP: AFIO output with push-pull
\param[in] speed: gpio output max speed value
only one parameter can be selected which is shown as below:
\arg GPIO_OSPEED_10MHZ: output max speed 10MHz
\arg GPIO_OSPEED_2MHZ: output max speed 2MHz
\arg GPIO_OSPEED_50MHZ: output max speed 50MHz
\arg GPIO_OSPEED_MAX: output max speed more than 50MHz
\param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[out] none
\retval none
*/
void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin)
{
uint16_t i;
uint32_t temp_mode = 0U;
uint32_t reg = 0U;
/* GPIO mode configuration */
temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU));
/* GPIO speed configuration */
if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){
/* output mode max speed */
if(GPIO_OSPEED_MAX == (uint32_t)speed){
temp_mode |= (uint32_t)0x03U;
/* set the corresponding SPD bit */
GPIOx_SPD(gpio_periph) |= (uint32_t)pin ;
}else{
/* output mode max speed:10MHz,2MHz,50MHz */
temp_mode |= (uint32_t)speed;
}
}
/* configure the eight low port pins with GPIO_CTL0 */
for(i = 0U;i < 8U;i++){
if((1U << i) & pin){
reg = GPIO_CTL0(gpio_periph);
/* clear the specified pin mode bits */
reg &= ~GPIO_MODE_MASK(i);
/* set the specified pin mode bits */
reg |= GPIO_MODE_SET(i, temp_mode);
/* set IPD or IPU */
if(GPIO_MODE_IPD == mode){
/* reset the corresponding OCTL bit */
GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
}else{
/* set the corresponding OCTL bit */
if(GPIO_MODE_IPU == mode){
GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
}
}
/* set GPIO_CTL0 register */
GPIO_CTL0(gpio_periph) = reg;
}
}
/* configure the eight high port pins with GPIO_CTL1 */
for(i = 8U;i < 16U;i++){
if((1U << i) & pin){
reg = GPIO_CTL1(gpio_periph);
/* clear the specified pin mode bits */
reg &= ~GPIO_MODE_MASK(i - 8U);
/* set the specified pin mode bits */
reg |= GPIO_MODE_SET(i - 8U, temp_mode);
/* set IPD or IPU */
if(GPIO_MODE_IPD == mode){
/* reset the corresponding OCTL bit */
GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
}else{
/* set the corresponding OCTL bit */
if(GPIO_MODE_IPU == mode){
GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
}
}
/* set GPIO_CTL1 register */
GPIO_CTL1(gpio_periph) = reg;
}
}
}
/*!
\brief set GPIO pin bit
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[out] none
\retval none
*/
void gpio_bit_set(uint32_t gpio_periph,uint32_t pin)
{
GPIO_BOP(gpio_periph) = (uint32_t)pin;
}
/*!
\brief reset GPIO pin bit
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[out] none
\retval none
*/
void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin)
{
GPIO_BC(gpio_periph) = (uint32_t)pin;
}
/*!
\brief write data to the specified GPIO pin
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[in] bit_value: SET or RESET
\arg RESET: clear the port pin
\arg SET: set the port pin
\param[out] none
\retval none
*/
void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value)
{
if(RESET != bit_value){
GPIO_BOP(gpio_periph) = (uint32_t)pin;
}else{
GPIO_BC(gpio_periph) = (uint32_t)pin;
}
}
/*!
\brief write data to the specified GPIO port
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] data: specify the value to be written to the port output data register
\param[out] none
\retval none
*/
void gpio_port_write(uint32_t gpio_periph,uint16_t data)
{
GPIO_OCTL(gpio_periph) = (uint32_t)data;
}
/*!
\brief get GPIO pin input status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] pin: GPIO pin
only one parameter can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[out] none
\retval input status of gpio pin: SET or RESET
*/
FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin)
{
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
return SET;
}else{
return RESET;
}
}
/*!
\brief get GPIO port input status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[out] none
\retval input status of gpio all pins
*/
uint16_t gpio_input_port_get(uint32_t gpio_periph)
{
return (uint16_t)(GPIO_ISTAT(gpio_periph));
}
/*!
\brief get GPIO pin output status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] pin: GPIO pin
only one parameter can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[out] none
\retval output status of gpio pin: SET or RESET
*/
FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin)
{
if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
return SET;
}else{
return RESET;
}
}
/*!
\brief get GPIO port output status
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[out] none
\retval output status of gpio all pins
*/
uint16_t gpio_output_port_get(uint32_t gpio_periph)
{
return ((uint16_t)GPIO_OCTL(gpio_periph));
}
/*!
\brief configure GPIO pin remap
\param[in] gpio_remap: select the pin to remap
only one parameter can be selected which are shown as below:
\arg GPIO_SPI0_REMAP: SPI0 remapping
\arg GPIO_I2C0_REMAP: I2C0 remapping
\arg GPIO_USART0_REMAP: USART0 remapping
\arg GPIO_USART1_REMAP: USART1 remapping
\arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping
\arg GPIO_USART2_FULL_REMAP: USART2 full remapping
\arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping
\arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping
\arg GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping
\arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping
\arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping
\arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping
\arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping
\arg GPIO_TIMER3_REMAP: TIMER3 remapping
\arg GPIO_PD01_REMAP: PD01 remapping
\arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping
\arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices)
\arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices)
\arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices)
\arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32E50X_HD devices and GD32E50X_XD devices)
\arg GPIO_ENET_REMAP: ENET remapping(only for GD32E50X_CL devices)
\arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST
\arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled
\arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled
\arg GPIO_SPI2_REMAP: SPI2 remapping
\arg GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32E50X_CL devices)
\arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32E50X_CL devices)
\arg GPIO_TIMER8_REMAP: TIMER8 remapping
\arg GPIO_TIMER9_REMAP: TIMER9 remapping
\arg GPIO_TIMER10_REMAP: TIMER10 remapping
\arg GPIO_TIMER12_REMAP: TIMER12 remapping
\arg GPIO_TIMER13_REMAP: TIMER13 remapping
\arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect
\arg GPIO_CTC_REMAP0: CTC remapping(PD15)
\arg GPIO_CTC_REMAP1: CTC remapping(PF0)
\param[in] newvalue: ENABLE or DISABLE
\param[out] none
\retval none
*/
void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue)
{
uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
if(((uint32_t)0x80000000U) == (remap & 0x80000000U)){
/* get AFIO_PCF1 regiter value */
temp_reg = AFIO_PCF1;
}else{
/* get AFIO_PCF0 regiter value */
temp_reg = AFIO_PCF0;
}
temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U;
remap1 = remap & LSB_16BIT_MASK;
/* judge pin remap type */
if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){
temp_reg &= PCF_SWJCFG_MASK;
AFIO_PCF0 &= PCF_SWJCFG_MASK;
}else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)){
remap2 = ((uint32_t)0x03U) << temp_mask;
temp_reg &= ~remap2;
temp_reg |= ~PCF_SWJCFG_MASK;
}else{
temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U));
temp_reg |= ~PCF_SWJCFG_MASK;
}
/* set pin remap value */
if(DISABLE != newvalue){
temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U));
}
if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){
/* set AFIO_PCF1 regiter value */
AFIO_PCF1 = temp_reg;
}else{
/* set AFIO_PCF0 regiter value */
AFIO_PCF0 = temp_reg;
}
}
/*!
\brief configure AFIO port alternate function
\param[in] afio_function: select the port AFIO function(SHRTIMER not support on GD32E50X_EPRT devices)
only one parameter can be selected which are shown as below:
\arg AFIO_PA2_CMP1_CFG: configure PA2 alternate function to CMP1
\arg AFIO_PA3_USBHS_CFG: configure PA3 alternate function to USBHS
\arg AFIO_PA5_USBHS_CFG: configure PA5 alternate function to USBHS
\arg AFIO_PA8_I2C2_CFG: configure PA8 alternate function to I2C2
\arg AFIO_PA8_SHRTIMER_CFG: configure PA8 alternate function to SHRTIMER
\arg AFIO_PA9_I2C2_CFG: configure PA9 alternate function to I2C2
\arg AFIO_PA9_SHRTIMER_CFG: configure PA9 alternate function to SHRTIMER
\arg AFIO_PA10_CMP5_CFG: configure PA10 alternate function to CMP5
\arg AFIO_PA10_SHRTIMER_CFG: configure PA10 alternate function to SHRTIMER
\arg AFIO_PA11_USART5_CFG: configure PA11 alternate function to USART5
\arg AFIO_PA11_SHRTIMER_CFG: configure PA11 alternate function to SHRTIMER
\arg AFIO_PA12_CMP1_CFG: configure PA12 alternate function to CMP1
\arg AFIO_PA12_USART5_CFG: configure PA12 alternate function to USART5
\arg AFIO_PA12_SHRTIMER_CFG: configure PA12 alternate function to SHRTIMER
\arg AFIO_PA15_SHRTIMER_CFG: configure PA15 alternate function to SHRTIMER
\arg AFIO_PB0_USBHS_CFG: configure PB0 alternate function to USBHS
\arg AFIO_PB1_CMP3_CFG: configure PB1 alternate function to CMP3
\arg AFIO_PB1_USBHS_CFG: configure PB1 alternate function to USBHS
\arg AFIO_PB1_SHRTIMER_CFG: configure PB1 alternate function to SHRTIMER
\arg AFIO_PB2_USBHS_CFG: configure PB2 alternate function to USBHS
\arg AFIO_PB2_SHRTIMER_CFG: configure PB2 alternate function to SHRTIMER
\arg AFIO_PB3_SHRTIMER_CFG: configure PB3 alternate function to SHRTIMER
\arg AFIO_PB4_I2S2_CFG: configure PB4 alternate function to I2S2
\arg AFIO_PB4_I2C2_CFG: configure PB4 alternate function to I2C2
\arg AFIO_PB4_SHRTIMER_CFG: configure PB4 alternate function to SHRTIMER
\arg AFIO_PB5_I2C2_CFG: configure PB5 alternate function to I2C2
\arg AFIO_PB5_USBHS_CFG: configure PB5 alternate function to USBHS
\arg AFIO_PB5_SHRTIMER_CFG: configure PB5 alternate function to SHRTIMER
\arg AFIO_PB6_SHRTIMER_CFG: configure PB6 alternate function to SHRTIMER
\arg AFIO_PB7_SHRTIMER_CFG: configure PB7 alternate function to SHRTIMER
\arg AFIO_PB8_I2C2_CFG: configure PB8 alternate function to I2C2
\arg AFIO_PB8_SHRTIMER_CFG: configure PB8 alternate function to SHRTIMER
\arg AFIO_PB9_CMP1_CFG: configure PB9 alternate function to CMP1
\arg AFIO_PB9_SHRTIMER_CFG: configure PB9 alternate function to SHRTIMER
\arg AFIO_PB10_USBHS_CFG: configure PB10 alternate function to USBHS
\arg AFIO_PB10_SHRTIMER_CFG: configure PB10 alternate function to SHRTIMER
\arg AFIO_PB11_USBHS_CFG: configure PB11 alternate function to USBHS
\arg AFIO_PB11_SHRTIMER_CFG: configure PB11 alternate function to SHRTIMER
\arg AFIO_PB12_USBHS_CFG: configure PB12 alternate function to USBHS
\arg AFIO_PB12_SHRTIMER_CFG: configure PB12 alternate function to SHRTIMER
\arg AFIO_PB13_USBHS_CFG: configure PB13 alternate function to USBHS
\arg AFIO_PB13_SHRTIMER_CFG: configure PB13 alternate function to SHRTIMER
\arg AFIO_PB14_I2S1_CFG: configure PB14 alternate function to I2S1
\arg AFIO_PB14_SHRTIMER_CFG: configure PB14 alternate function to SHRTIMER
\arg AFIO_PB15_SHRTIMER_CFG: configure PB15 alternate function to SHRTIMER
\arg AFIO_PC0_USBHS_CFG: configure PC0 alternate function to USBHS
\arg AFIO_PC2_I2S1_CFG: configure PC2 alternate function to I2S1
\arg AFIO_PC2_USBHS_CFG: configure PC2 alternate function to USBHS
\arg AFIO_PC3_USBHS_CFG: configure PC3 alternate function to USBHS
\arg AFIO_PC6_CMP5_CFG: configure PC6 alternate function to CMP5
\arg AFIO_PC6_USART5_CFG: configure PC6 alternate function to USART5
\arg AFIO_PC6_SHRTIMER_CFG: configure PC6 alternate function to SHRTIMER
\arg AFIO_PC7_USART5_CFG: configure PC7 alternate function to USART5
\arg AFIO_PC7_SHRTIMER_CFG: configure PC7 alternate function to SHRTIMER
\arg AFIO_PC8_USART5_CFG: configure PC8 alternate function to USART5
\arg AFIO_PC8_SHRTIMER_CFG: configure PC8 alternate function to SHRTIMER
\arg AFIO_PC9_I2C2_CFG: configure PC9 alternate function to I2C2
\arg AFIO_PC9_SHRTIMER_CFG: configure PC9 alternate function to SHRTIMER
\arg AFIO_PC10_I2C2_CFG: configure PC10 alternate function to I2C2
\arg AFIO_PC11_I2S2_CFG: configure PC11 alternate function to I2S2
\arg AFIO_PC11_SHRTIMER_CFG: configure PC11 alternate function to SHRTIMER
\arg AFIO_PC12_SHRTIMER_CFG: configure PC12 alternate function to SHRTIMER
\arg AFIO_PD4_SHRTIMER_CFG: configure PD4 alternate function to SHRTIMER
\arg AFIO_PD5_SHRTIMER_CFG: configure PD5 alternate function to SHRTIMER
\arg AFIO_PE0_SHRTIMER_CFG: configure PE0 alternate function to SHRTIMER
\arg AFIO_PE1_SHRTIMER_CFG: configure PE1 alternate function to SHRTIMER
\arg AFIO_PE8_CMP1_CFG: configure PE8 alternate function to CMP1
\arg AFIO_PE9_CMP3_CFG: configure PE9 alternate function to CMP3
\arg AFIO_PE10_CMP5_CFG: configure PE10 alternate function to CMP5
\arg AFIO_PE11_CMP5_CFG: configure PE11 alternate function to CMP5
\arg AFIO_PE12_CMP3_CFG: configure PE12 alternate function to CMP3
\arg AFIO_PE13_CMP1_CFG: configure PE13 alternate function to CMP1
\arg AFIO_PG6_SHRTIMER_CFG: configure PG6 alternate function to SHRTIMER
\arg AFIO_PG7_USART5_CFG: configure PG7 alternate function to USART5
\arg AFIO_PG7_SHRTIMER_CFG: configure PG7 alternate function to SHRTIMER
\arg AFIO_PG9_USART5_CFG: configure PG9 alternate function to USART5
\arg AFIO_PG10_SHRTIMER_CFG: configure PG10 alternate function to SHRTIMER
\arg AFIO_PG11_SHRTIMER_CFG: configure PG11 alternate function to SHRTIMER
\arg AFIO_PG12_SHRTIMER_CFG: configure PG12 alternate function to SHRTIMER
\arg AFIO_PG13_SHRTIMER_CFG: configure PG13 alternate function to SHRTIMER
\arg AFIO_PG14_USART5_CFG: configure PG14 alternate function to USART5
\param[in] newvalue: ENABLE or DISABLE
\param[out] none
\retval none
*/
void gpio_afio_port_config(uint32_t afio_function, ControlStatus newvalue)
{
uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U;
/* get AFIO_PCFx(x=A,B,C,D,E,G) regiter value */
temp_reg = REG32(AFIO+0x0000003CU+((afio_function>>24)<<2));
temp_mask = (afio_function & PCF_POSITION_MASK) >> 0x10U;
remap1 = afio_function & LSB_16BIT_MASK;
/* judge port function select type */
if(afio_function & PCF_LOCATION2_MASK){
remap2 = ((uint32_t)0x03U) << temp_mask;
remap2 = (remap2 << (((afio_function & PCF_LOCATION1_MASK) >> 0x15U)*0x10U));
temp_reg &= ~remap2;
}else{
temp_reg &= ~(remap1 << (((afio_function & PCF_LOCATION1_MASK) >> 0x15U)*0x10U));
}
/* set pin remap value */
if(DISABLE != newvalue){
temp_reg |= (remap1 << (((afio_function & PCF_LOCATION1_MASK) >> 0x15U)*0x10U));
}
/* set AFIO_PCFx(x=A,B,C,D,E,G) regiter value */
REG32(AFIO+0x0000003CU+((afio_function>>24)<<2)) = temp_reg;
}
#ifdef GD32E50X_CL
/*!
\brief select ethernet MII or RMII PHY
\param[in] enet_sel: ethernet MII or RMII PHY selection
\arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY
\arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY
\param[out] none
\retval none
*/
void gpio_ethernet_phy_select(uint32_t enet_sel)
{
/* clear AFIO_PCF0_ENET_PHY_SEL bit */
AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL);
/* select MII or RMII PHY */
AFIO_PCF0 |= (uint32_t)enet_sel;
}
#endif /* GD32E50X_CL */
/*!
\brief select GPIO pin exti sources
\param[in] output_port: gpio event output port
only one parameter can be selected which are shown as below:
\arg GPIO_PORT_SOURCE_GPIOA: output port source A
\arg GPIO_PORT_SOURCE_GPIOB: output port source B
\arg GPIO_PORT_SOURCE_GPIOC: output port source C
\arg GPIO_PORT_SOURCE_GPIOD: output port source D
\arg GPIO_PORT_SOURCE_GPIOE: output port source E
\arg GPIO_PORT_SOURCE_GPIOF: output port source F
\arg GPIO_PORT_SOURCE_GPIOG: output port source G
\param[in] output_pin: GPIO output pin source
only one parameter can be selected which are shown as below:
\arg GPIO_PIN_SOURCE_x(x=0..15)
\param[out] none
\retval none
*/
void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin)
{
uint32_t source = 0U;
source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK));
/* select EXTI sources */
if(GPIO_PIN_SOURCE_4 > output_pin){
/* select EXTI0/EXTI1/EXTI2/EXTI3 */
AFIO_EXTISS0 &= ~source;
AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
}else if(GPIO_PIN_SOURCE_8 > output_pin){
/* select EXTI4/EXTI5/EXTI6/EXTI7 */
AFIO_EXTISS1 &= ~source;
AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
}else if(GPIO_PIN_SOURCE_12 > output_pin){
/* select EXTI8/EXTI9/EXTI10/EXTI11 */
AFIO_EXTISS2 &= ~source;
AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
}else{
/* select EXTI12/EXTI13/EXTI14/EXTI15 */
AFIO_EXTISS3 &= ~source;
AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)));
}
}
/*!
\brief configure GPIO pin event output
\param[in] output_port: gpio event output port
only one parameter can be selected which are shown as below:
\arg GPIO_EVENT_PORT_GPIOA: event output port A
\arg GPIO_EVENT_PORT_GPIOB: event output port B
\arg GPIO_EVENT_PORT_GPIOC: event output port C
\arg GPIO_EVENT_PORT_GPIOD: event output port D
\arg GPIO_EVENT_PORT_GPIOE: event output port E
\param[in] output_pin: GPIO event output pin
only one parameter can be selected which are shown as below:
\arg GPIO_EVENT_PIN_x(x=0..15)
\param[out] none
\retval none
*/
void gpio_event_output_config(uint8_t output_port, uint8_t output_pin)
{
uint32_t reg = 0U;
reg = AFIO_EC;
/* clear AFIO_EC_PORT and AFIO_EC_PIN bits */
reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN));
reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET);
reg |= (uint32_t)output_pin;
AFIO_EC = reg;
}
/*!
\brief enable GPIO pin event output
\param[in] none
\param[out] none
\retval none
*/
void gpio_event_output_enable(void)
{
AFIO_EC |= AFIO_EC_EOE;
}
/*!
\brief disable GPIO pin event output
\param[in] none
\param[out] none
\retval none
*/
void gpio_event_output_disable(void)
{
AFIO_EC &= (uint32_t)(~AFIO_EC_EOE);
}
/*!
\brief lock GPIO pin bit
\param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G)
\param[in] pin: GPIO pin
one or more parameters can be selected which are shown as below:
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
\param[out] none
\retval none
*/
void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin)
{
uint32_t lock = 0x00010000U;
lock |= pin;
/* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
GPIO_LOCK(gpio_periph) = (uint32_t)pin;
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
lock = GPIO_LOCK(gpio_periph);
lock = GPIO_LOCK(gpio_periph);
}
/*!
\brief configure the I/O compensation cell
\param[in] compensation: specifies the I/O compensation cell mode
only one parameter can be selected which are shown as below:
\arg GPIO_COMPENSATION_ENABLE: I/O compensation cell is enabled
\arg GPIO_COMPENSATION_DISABLE: I/O compensation cell is disabled
\param[out] none
\retval none
*/
void gpio_compensation_config(uint32_t compensation)
{
uint32_t reg;
reg = AFIO_CPSCTL;
/* reset the AFIO_CPSCTL_CPS_EN bit and set according to gpio_compensation */
reg &= ~AFIO_CPSCTL_CPS_EN;
AFIO_CPSCTL = (reg | compensation);
}
/*!
\brief check the I/O compensation cell is ready or not
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus gpio_compensation_flag_get(void)
{
if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){
return SET;
}else{
return RESET;
}
}

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/*!
\file gd32e50x_misc.c
\brief MISC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_misc.h"
/*!
\brief set the priority group
\param[in] nvic_prigroup: the NVIC priority group
\arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
\arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
\arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
\arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
\arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
\param[out] none
\retval none
*/
void nvic_priority_group_set(uint32_t nvic_prigroup)
{
/* set the priority group value */
SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
}
/*!
\brief enable NVIC request
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
\param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
\param[in] nvic_irq_sub_priority: the subpriority needed to set
\param[out] none
\retval none
*/
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
uint8_t nvic_irq_sub_priority)
{
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
/* use the priority group value to get the temp_pre and the temp_sub */
if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
temp_pre=0U;
temp_sub=0x4U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
temp_pre=1U;
temp_sub=0x3U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
temp_pre=2U;
temp_sub=0x2U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
temp_pre=3U;
temp_sub=0x1U;
}else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
temp_pre=4U;
temp_sub=0x0U;
}else{
nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
temp_pre=2U;
temp_sub=0x2U;
}
/* get the temp_priority to fill the NVIC->IP register */
temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
temp_priority = temp_priority << 0x04U;
NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
/* enable the selected IRQ */
NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
}
/*!
\brief disable NVIC request
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
\param[out] none
\retval none
*/
void nvic_irq_disable(uint8_t nvic_irq)
{
/* disable the selected IRQ.*/
NVIC_DisableIRQ((IRQn_Type)nvic_irq);
}
/*!
\brief initiates a system reset request to reset the MCU
\param[in] none
\param[out] none
\retval none
*/
void nvic_system_reset(void)
{
NVIC_SystemReset();
}
/*!
\brief set the NVIC vector table base address
\param[in] nvic_vict_tab: the RAM or FLASH base address
\arg NVIC_VECTTAB_RAM: RAM base address
\are NVIC_VECTTAB_FLASH: Flash base address
\param[in] offset: Vector Table offset
\param[out] none
\retval none
*/
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
{
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
}
/*!
\brief set the state of the low power mode
\param[in] lowpower_mode: the low power mode state
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
mode by exiting from ISR
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
by all the enable and disable interrupts
\param[out] none
\retval none
*/
void system_lowpower_set(uint8_t lowpower_mode)
{
SCB->SCR |= (uint32_t)lowpower_mode;
}
/*!
\brief reset the state of the low power mode
\param[in] lowpower_mode: the low power mode state
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
mode by exiting from ISR
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
woke up by the enable interrupts
\param[out] none
\retval none
*/
void system_lowpower_reset(uint8_t lowpower_mode)
{
SCB->SCR &= (~(uint32_t)lowpower_mode);
}
/*!
\brief set the systick clock source
\param[in] systick_clksource: the systick clock source needed to choose
\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
\param[out] none
\retval none
*/
void systick_clksource_set(uint32_t systick_clksource)
{
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
/* set the systick clock source from HCLK */
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}else{
/* set the systick clock source from HCLK/8 */
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
}
}

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/*!
\file gd32e50x_pmu.c
\brief PMU driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_pmu.h"
/*!
\brief reset PMU registers
\param[in] none
\param[out] none
\retval none
*/
void pmu_deinit(void)
{
/* reset PMU */
rcu_periph_reset_enable(RCU_PMURST);
rcu_periph_reset_disable(RCU_PMURST);
}
/*!
\brief select low voltage detector threshold
\param[in] lvdt_n:
only one parameter can be selected which is shown as below:
\arg PMU_LVDT_0: voltage threshold is 2.1V
\arg PMU_LVDT_1: voltage threshold is 2.3V
\arg PMU_LVDT_2: voltage threshold is 2.4V
\arg PMU_LVDT_3: voltage threshold is 2.6V
\arg PMU_LVDT_4: voltage threshold is 2.7V
\arg PMU_LVDT_5: voltage threshold is 2.9V
\arg PMU_LVDT_6: voltage threshold is 3.0V
\arg PMU_LVDT_7: voltage threshold is 3.1V
\param[out] none
\retval none
*/
void pmu_lvd_select(uint32_t lvdt_n)
{
/* disable LVD */
PMU_CTL0 &= ~PMU_CTL0_LVDEN;
/* clear LVDT bits */
PMU_CTL0 &= ~PMU_CTL0_LVDT;
/* set LVDT bits according to lvdt_n */
PMU_CTL0 |= lvdt_n;
/* enable LVD */
PMU_CTL0 |= PMU_CTL0_LVDEN;
}
/*!
\brief disable PMU LVD
\param[in] none
\param[out] none
\retval none
*/
void pmu_lvd_disable(void)
{
/* disable LVD */
PMU_CTL0 &= ~PMU_CTL0_LVDEN;
}
/*!
\brief enable high-driver mode
this bit set by software only when IRC8M or HXTAL used as system clock
\param[in] none
\param[out] none
\retval none
*/
void pmu_highdriver_mode_enable(void)
{
PMU_CTL0 |= PMU_CTL0_HDEN;
}
/*!
\brief disable high-driver mode
\param[in] none
\param[out] none
\retval none
*/
void pmu_highdriver_mode_disable(void)
{
PMU_CTL0 &= ~PMU_CTL0_HDEN;
}
/*!
\brief switch high-driver mode
this bit set by software only when IRC8M or HXTAL used as system clock
\param[in] highdr_switch:
only one parameter can be selected which is shown as below:
\arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
\arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
\param[out] none
\retval none
*/
void pmu_highdriver_switch_select(uint32_t highdr_switch)
{
/* wait for HDRF flag set */
while(SET != pmu_flag_get(PMU_FLAG_HDRF)){
}
PMU_CTL0 &= ~PMU_CTL0_HDS;
PMU_CTL0 |= highdr_switch;
}
/*!
\brief enable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode
\param[in] none
\param[out] none
\retval none
*/
void pmu_lowdriver_mode_enable(void)
{
PMU_CTL0 |= PMU_CTL0_LDEN;
}
/*!
\brief disable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode
\param[in] none
\param[out] none
\retval none
*/
void pmu_lowdriver_mode_disable(void)
{
PMU_CTL0 &= ~PMU_CTL0_LDEN;
}
/*!
\brief in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use low power LDO
\param[in] mode:
only one parameter can be selected which is shown as below:
\arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO
\arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
\param[out] none
\retval none
*/
void pmu_lowpower_driver_config(uint32_t mode)
{
PMU_CTL0 &= ~PMU_CTL0_LDLP;
PMU_CTL0 |= mode;
}
/*!
\brief in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use normal power LDO
\param[in] mode:
only one parameter can be selected which is shown as below:
\arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO
\arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO
\param[out] none
\retval none
*/
void pmu_normalpower_driver_config(uint32_t mode)
{
PMU_CTL0 &= ~PMU_CTL0_LDNP;
PMU_CTL0 |= mode;
}
/*!
\brief PMU work at sleep mode
\param[in] sleepmodecmd:
only one parameter can be selected which is shown as below:
\arg WFI_CMD: use WFI command
\arg WFE_CMD: use WFE command
\param[out] none
\retval none
*/
void pmu_to_sleepmode(uint8_t sleepmodecmd)
{
/* clear sleepdeep bit of Cortex-M33 system control register */
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
/* select WFI or WFE command to enter sleep mode */
if(WFI_CMD == sleepmodecmd){
__WFI();
}else{
__WFE();
}
}
/*!
\brief PMU work at deepsleep mode
\param[in] ldo:
only one parameter can be selected which is shown as below:
\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
\param[in] deepsleepmodecmd:
only one parameter can be selected which is shown as below:
\arg WFI_CMD: use WFI command
\arg WFE_CMD: use WFE command
\param[out] none
\retval none
*/
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
{
static uint32_t reg_snap[ 4 ];
/* clear stbmod and ldolp bits */
PMU_CTL0 &= ~((uint32_t)(PMU_CTL0_STBMOD | PMU_CTL0_LDOLP));
/* clear deep-sleep 1/2 mode enable bits */
PMU_CTL1 &= ~(PMU_CTL1_DPMOD1 | PMU_CTL1_DPMOD2);
/* set ldolp bit according to pmu_ldo */
PMU_CTL0 |= ldo;
/* set sleepdeep bit of Cortex-M33 system control register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
reg_snap[0] = REG32(0xE000E010U);
reg_snap[1] = REG32(0xE000E100U);
reg_snap[2] = REG32(0xE000E104U);
reg_snap[3] = REG32(0xE000E108U);
REG32(0xE000E010U) &= 0x00010004U;
REG32(0xE000E180U) = 0XFF7FF83DU;
REG32(0xE000E184U) = 0XBFFFF8FFU;
REG32(0xE000E188U) = 0xFF9FFFFFU;
/* select WFI or WFE command to enter deepsleep mode */
if(WFI_CMD == deepsleepmodecmd){
__WFI();
}else{
__SEV();
__WFE();
__WFE();
}
REG32(0xE000E010U) = reg_snap[0] ;
REG32(0xE000E100U) = reg_snap[1] ;
REG32(0xE000E104U) = reg_snap[2] ;
REG32(0xE000E108U) = reg_snap[3] ;
/* reset sleepdeep bit of Cortex-M33 system control register */
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
/*!
\brief PMU work at deepsleep mode 1
\param[in] ldo:
only one parameter can be selected which is shown as below:
\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode 1
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode 1
\param[in] deepsleepmode1cmd:
only one parameter can be selected which is shown as below:
\arg WFI_CMD: use WFI command
\arg WFE_CMD: use WFE command
\param[out] none
\retval none
*/
void pmu_to_deepsleepmode_1(uint32_t ldo,uint8_t deepsleepmode1cmd)
{
static uint32_t reg_snap[ 4 ];
/* clear stbmod and ldolp bits */
PMU_CTL0 &= ~((uint32_t)(PMU_CTL0_STBMOD | PMU_CTL0_LDOLP));
/* clear deep-sleep 2 mode enable bit */
PMU_CTL1 &= ~PMU_CTL1_DPMOD2;
/* enable deep-sleep 1 mode */
PMU_CTL1 |= PMU_CTL1_DPMOD1;
/* set ldolp bit according to pmu_ldo */
PMU_CTL0 |= ldo;
/* set sleepdeep bit of Cortex-M33 system control register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
reg_snap[0] = REG32(0xE000E010U);
reg_snap[1] = REG32(0xE000E100U);
reg_snap[2] = REG32(0xE000E104U);
reg_snap[3] = REG32(0xE000E108U);
REG32(0xE000E010U) &= 0x00010004U;
REG32(0xE000E180U) = 0XFF7FF83DU;
REG32(0xE000E184U) = 0XBFFFF8FFU;
REG32(0xE000E188U) = 0xFF9FFFFFU;
/* select WFI or WFE command to enter deepsleep mode 1 */
if(WFI_CMD == deepsleepmode1cmd){
__WFI();
}else{
__SEV();
__WFE();
__WFE();
}
REG32(0xE000E010U) = reg_snap[0] ;
REG32(0xE000E100U) = reg_snap[1] ;
REG32(0xE000E104U) = reg_snap[2] ;
REG32(0xE000E108U) = reg_snap[3] ;
/* reset sleepdeep bit of Cortex-M33 system control register */
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
PMU_CTL1 &= ~PMU_CTL1_DPMOD1;
}
/*!
\brief PMU work at deepsleep mode 2
\param[in] ldo:
only one parameter can be selected which is shown as below:
\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode 2
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode 2
\param[in] deepsleepmode2cmd:
only one parameter can be selected which is shown as below:
\arg WFI_CMD: use WFI command
\arg WFE_CMD: use WFE command
\param[out] none
\retval none
*/
void pmu_to_deepsleepmode_2(uint32_t ldo,uint8_t deepsleepmode2cmd)
{
static uint32_t reg_snap[ 4 ];
/* clear stbmod and ldolp bits */
PMU_CTL0 &= ~((uint32_t)(PMU_CTL0_STBMOD | PMU_CTL0_LDOLP));
/* clear deep-sleep 1 mode enable bit */
PMU_CTL1 &= ~PMU_CTL1_DPMOD1;
/* enable deep-sleep 2 mode */
PMU_CTL1 |= PMU_CTL1_DPMOD2;
/* set ldolp bit according to pmu_ldo */
PMU_CTL0 |= ldo;
/* set sleepdeep bit of Cortex-M33 system control register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
reg_snap[0] = REG32(0xE000E010U);
reg_snap[1] = REG32(0xE000E100U);
reg_snap[2] = REG32(0xE000E104U);
reg_snap[3] = REG32(0xE000E108U);
REG32(0xE000E010U) &= 0x00010004U;
REG32(0xE000E180U) = 0XFF7FF83DU;
REG32(0xE000E184U) = 0XBFFFF8FFU;
REG32(0xE000E188U) = 0xFF9FFFFFU;
/* select WFI or WFE command to enter deepsleep mode 2 */
if(WFI_CMD == deepsleepmode2cmd){
__WFI();
}else{
__SEV();
__WFE();
__WFE();
}
REG32(0xE000E010U) = reg_snap[0] ;
REG32(0xE000E100U) = reg_snap[1] ;
REG32(0xE000E104U) = reg_snap[2] ;
REG32(0xE000E108U) = reg_snap[3] ;
/* reset sleepdeep bit of Cortex-M33 system control register */
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
PMU_CTL1 &= ~PMU_CTL1_DPMOD2;
}
/*!
\brief pmu work at standby mode
\param[in] standbymodecmd:
only one parameter can be selected which is shown as below:
\arg WFI_CMD: use WFI command
\arg WFE_CMD: use WFE command
\param[out] none
\retval none
*/
void pmu_to_standbymode(uint8_t standbymodecmd)
{
/* set sleepdeep bit of Cortex-M33 system control register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* set stbmod bit */
PMU_CTL0 |= PMU_CTL0_STBMOD;
/* reset wakeup flag */
PMU_CTL0 |= PMU_CTL0_WURST;
/* select WFI or WFE command to enter standby mode */
if(WFI_CMD == standbymodecmd){
__WFI();
}else{
__WFE();
}
}
/*!
\brief enable PMU wakeup pin
\param[in] wakeup_pin:
one or more parameters can be selected which are shown as below:
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
\arg PMU_WAKEUP_PIN2: WKUP Pin 2 (PE6)
\arg PMU_WAKEUP_PIN3: WKUP Pin 3 (PA2)
\arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
\arg PMU_WAKEUP_PIN7: WKUP Pin 7 (PF8)
\param[out] none
\retval none
*/
void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
{
PMU_CS0 |= wakeup_pin;
}
/*!
\brief disable PMU wakeup pin
\param[in] wakeup_pin:
one or more parameters can be selected which are shown as below:
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
\arg PMU_WAKEUP_PIN2: WKUP Pin 2 (PE6)
\arg PMU_WAKEUP_PIN3: WKUP Pin 3 (PA2)
\arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
\arg PMU_WAKEUP_PIN7: WKUP Pin 7 (PF8)
\param[out] none
\retval none
*/
void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
{
PMU_CS0 &= ~(wakeup_pin);
}
/*!
\brief enable backup domain write
\param[in] none
\param[out] none
\retval none
*/
void pmu_backup_write_enable(void)
{
PMU_CTL0 |= PMU_CTL0_BKPWEN;
}
/*!
\brief disable backup domain write
\param[in] none
\param[out] none
\retval none
*/
void pmu_backup_write_disable(void)
{
PMU_CTL0 &= ~PMU_CTL0_BKPWEN;
}
/*!
\brief clear flag bit
\param[in] flag_reset:
only one parameter can be selected which is shown as below:
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
\arg PMU_FLAG_RESET_DEEPSLEEP_1: reset deep-sleep 1 mode status flag
\arg PMU_FLAG_RESET_DEEPSLEEP_2: reset deep-sleep 2 mode status flag
\param[out] none
\retval none
*/
void pmu_flag_clear(uint32_t flag_reset)
{
switch(flag_reset){
case PMU_FLAG_RESET_WAKEUP:
/* reset wakeup flag */
PMU_CTL0 |= PMU_CTL0_WURST;
break;
case PMU_FLAG_RESET_STANDBY:
/* reset standby flag */
PMU_CTL0 |= PMU_CTL0_STBRST;
break;
case PMU_FLAG_RESET_DEEPSLEEP_1:
/* reset deep-sleep 1 mode status flag */
PMU_CS1 &= ~PMU_CS1_DPF1;
break;
case PMU_FLAG_RESET_DEEPSLEEP_2:
/* reset deep-sleep 2 mode status flag */
PMU_CS1 &= ~PMU_CS1_DPF2;
break;
default :
break;
}
}
/*!
\brief get flag state
\param[in] flag:
only one parameter can be selected which is shown as below:
\arg PMU_FLAG_WAKEUP: wakeup flag
\arg PMU_FLAG_STANDBY: standby flag
\arg PMU_FLAG_LVD: lvd flag
\arg PMU_FLAG_HDRF: high-driver ready flag
\arg PMU_FLAG_HDSRF: high-driver switch ready flag
\arg PMU_FLAG_LDRF: low-driver mode ready flag
\arg PMU_FLAG_DEEPSLEEP_1: deep-sleep 1 mode status flag
\arg PMU_FLAG_DEEPSLEEP_2: deep-sleep 2 mode status flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus pmu_flag_get(uint32_t flag)
{
FlagStatus ret = RESET;
if(RESET != (flag & BIT(31))){
flag &= ~BIT(31);
if(PMU_CS1 & flag){
ret = SET;
}
}else{
if(PMU_CS0 & flag){
ret = SET;
}
}
return ret;
}

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_rcu.c Normal file
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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_rtc.c Normal file
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/*!
\file gd32e50x_rtc.c
\brief RTC driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_rtc.h"
/* RTC register bit offset */
#define CNTH_16BIT_OFFSET ((uint32_t)0X00000010U)
#define PSCH_16BIT_OFFSET ((uint32_t)0X00000010U)
#define ALARMH_16BIT_OFFSET ((uint32_t)0X00000010U)
/*!
\brief enter RTC configuration mode
\param[in] none
\param[out] none
\retval none
*/
void rtc_configuration_mode_enter(void)
{
RTC_CTL |= RTC_CTL_CMF;
}
/*!
\brief exit RTC configuration mode
\param[in] none
\param[out] none
\retval none
*/
void rtc_configuration_mode_exit(void)
{
RTC_CTL &= ~RTC_CTL_CMF;
}
/*!
\brief wait RTC last write operation finished flag set
\param[in] none
\param[out] none
\retval none
*/
void rtc_lwoff_wait(void)
{
/* loop until LWOFF flag is set */
while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){
}
}
/*!
\brief wait RTC registers synchronized flag set
\param[in] none
\param[out] none
\retval none
*/
void rtc_register_sync_wait(void)
{
/* clear RSYNF flag */
RTC_CTL &= ~RTC_CTL_RSYNF;
/* loop until RSYNF flag is set */
while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){
}
}
/*!
\brief get RTC counter value
\param[in] none
\param[out] none
\retval RTC counter value
*/
uint32_t rtc_counter_get(void)
{
uint32_t temp = 0x0U;
temp = RTC_CNTL;
temp |= (RTC_CNTH << 16);
return temp;
}
/*!
\brief set RTC counter value
\param[in] cnt: RTC counter value(0x00000000~0xFFFFFFFF)
\param[out] none
\retval none
*/
void rtc_counter_set(uint32_t cnt)
{
rtc_configuration_mode_enter();
/* set the RTC counter high bits */
RTC_CNTH = cnt >> CNTH_16BIT_OFFSET;
/* set the RTC counter low bits */
RTC_CNTL = (cnt & RTC_LOW_VALUE);
rtc_configuration_mode_exit();
}
/*!
\brief set RTC prescaler value
\param[in] psc: RTC prescaler value(0x00000000~0x000FFFFF)
\param[out] none
\retval none
*/
void rtc_prescaler_set(uint32_t psc)
{
rtc_configuration_mode_enter();
/* set the RTC prescaler high bits */
RTC_PSCH = (psc & RTC_HIGH_VALUE) >> PSCH_16BIT_OFFSET;
/* set the RTC prescaler low bits */
RTC_PSCL = (psc & RTC_LOW_VALUE);
rtc_configuration_mode_exit();
}
/*!
\brief set RTC alarm value
\param[in] alarm: RTC alarm value(0x00000000~0xFFFFFFFF)
\param[out] none
\retval none
*/
void rtc_alarm_config(uint32_t alarm)
{
rtc_configuration_mode_enter();
/* set the alarm high bits */
RTC_ALRMH = alarm >> ALARMH_16BIT_OFFSET;
/* set the alarm low bits */
RTC_ALRML = (alarm & RTC_LOW_VALUE);
rtc_configuration_mode_exit();
}
/*!
\brief get RTC divider value
\param[in] none
\param[out] none
\retval RTC divider value
*/
uint32_t rtc_divider_get(void)
{
uint32_t temp = 0x00U;
temp = (RTC_DIVH & RTC_DIVH_DIV) << 16;
temp |= RTC_DIVL;
return temp;
}
/*!
\brief enable RTC interrupt
\param[in] interrupt: specify which interrupt to enbale
only one parameter can be selected which is shown as below:
\arg RTC_INT_SECOND: second interrupt
\arg RTC_INT_ALARM: alarm interrupt
\arg RTC_INT_OVERFLOW: overflow interrupt
\param[out] none
\retval none
*/
void rtc_interrupt_enable(uint32_t interrupt)
{
RTC_INTEN |= interrupt;
}
/*!
\brief disable RTC interrupt
\param[in] interrupt: specify which interrupt to disbale
only one parameter can be selected which is shown as below:
\arg RTC_INT_SECOND: second interrupt
\arg RTC_INT_ALARM: alarm interrupt
\arg RTC_INT_OVERFLOW: overflow interrupt
\param[out] none
\retval none
*/
void rtc_interrupt_disable(uint32_t interrupt)
{
RTC_INTEN &= ~interrupt;
}
/*!
\brief get RTC flag status
\param[in] flag: specify which flag status to get
only one parameter can be selected which is shown as below:
\arg RTC_FLAG_SECOND: second interrupt flag
\arg RTC_FLAG_ALARM: alarm interrupt flag
\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
\arg RTC_FLAG_RSYN: registers synchronized flag
\arg RTC_FLAG_LWOF: last write operation finished flag
\param[out] none
\retval SET or RESET
*/
FlagStatus rtc_flag_get(uint32_t flag)
{
if(RESET != (RTC_CTL & flag)){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear RTC flag status
\param[in] flag: specify which flag status to clear
only one parameter can be selected which is shown as below:
\arg RTC_FLAG_SECOND: second interrupt flag
\arg RTC_FLAG_ALARM: alarm interrupt flag
\arg RTC_FLAG_OVERFLOW: overflow interrupt flag
\arg RTC_FLAG_RSYN: registers synchronized flag
\param[out] none
\retval none
*/
void rtc_flag_clear(uint32_t flag)
{
/* clear RTC flag */
RTC_CTL &= ~flag;
}

811
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_sdio.c Normal file
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@@ -0,0 +1,811 @@
/*!
\file gd32e50x_sdio.c
\brief SDIO driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_sdio.h"
#if (defined(GD32E50X_HD) || defined(GD32E50X_XD))
#define DEFAULT_RESET_VALUE 0x00000000U
/*!
\brief deinitialize the SDIO
\param[in] none
\param[out] none
\retval none
*/
void sdio_deinit(void)
{
SDIO_PWRCTL = DEFAULT_RESET_VALUE;
SDIO_CLKCTL = DEFAULT_RESET_VALUE;
SDIO_CMDAGMT = DEFAULT_RESET_VALUE;
SDIO_CMDCTL = DEFAULT_RESET_VALUE;
SDIO_DATATO = DEFAULT_RESET_VALUE;
SDIO_DATALEN = DEFAULT_RESET_VALUE;
SDIO_DATACTL = DEFAULT_RESET_VALUE;
SDIO_INTC = DEFAULT_RESET_VALUE;
SDIO_INTEN = DEFAULT_RESET_VALUE;
}
/*!
\brief configure the SDIO clock
\param[in] clock_edge: SDIO_CLK clock edge
only one parameter can be selected which is shown as below:
\arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK
\arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK
\param[in] clock_bypass: clock bypass
only one parameter can be selected which is shown as below:
\arg SDIO_CLOCKBYPASS_ENABLE: clock bypass
\arg SDIO_CLOCKBYPASS_DISABLE: no bypass
\param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving
only one parameter can be selected which is shown as below:
\arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle
\arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on
\param[in] clock_division: clock division, less than 512
\param[out] none
\retval none
*/
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division)
{
uint32_t clock_config = 0U;
clock_config = SDIO_CLKCTL;
/* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */
clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV);
/* if the clock division is greater or equal to 256, set the DIV[8] */
if(clock_division >= 256U){
clock_config |= SDIO_CLKCTL_DIV8;
clock_division -= 256U;
}
/* configure the SDIO_CLKCTL according to the parameters */
clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division);
SDIO_CLKCTL = clock_config;
}
/*!
\brief enable hardware clock control
\param[in] none
\param[out] none
\retval none
*/
void sdio_hardware_clock_enable(void)
{
SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN;
}
/*!
\brief disable hardware clock control
\param[in] none
\param[out] none
\retval none
*/
void sdio_hardware_clock_disable(void)
{
SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN;
}
/*!
\brief set different SDIO card bus mode
\param[in] bus_mode: SDIO card bus mode
only one parameter can be selected which is shown as below:
\arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode
\arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode
\arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode
\param[out] none
\retval none
*/
void sdio_bus_mode_set(uint32_t bus_mode)
{
/* reset the SDIO card bus mode bits and set according to bus_mode */
SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE;
SDIO_CLKCTL |= bus_mode;
}
/*!
\brief set the SDIO power state
\param[in] power_state: SDIO power state
only one parameter can be selected which is shown as below:
\arg SDIO_POWER_ON: SDIO power on
\arg SDIO_POWER_OFF: SDIO power off
\param[out] none
\retval none
*/
void sdio_power_state_set(uint32_t power_state)
{
SDIO_PWRCTL = power_state;
}
/*!
\brief get the SDIO power state
\param[in] none
\param[out] none
\retval SDIO power state
\arg SDIO_POWER_ON: SDIO power on
\arg SDIO_POWER_OFF: SDIO power off
*/
uint32_t sdio_power_state_get(void)
{
return SDIO_PWRCTL;
}
/*!
\brief enable SDIO_CLK clock output
\param[in] none
\param[out] none
\retval none
*/
void sdio_clock_enable(void)
{
SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN;
}
/*!
\brief disable SDIO_CLK clock output
\param[in] none
\param[out] none
\retval none
*/
void sdio_clock_disable(void)
{
SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN;
}
/*!
\brief configure the command and response
\param[in] cmd_index: command index, refer to the related specifications
\param[in] cmd_argument: command argument, refer to the related specifications
\param[in] response_type: response type
only one parameter can be selected which is shown as below:
\arg SDIO_RESPONSETYPE_NO: no response
\arg SDIO_RESPONSETYPE_SHORT: short response
\arg SDIO_RESPONSETYPE_LONG: long response
\param[out] none
\retval none
*/
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type)
{
uint32_t cmd_config = 0U;
/* reset the command index, command argument and response type */
SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT;
SDIO_CMDAGMT = cmd_argument;
cmd_config = SDIO_CMDCTL;
cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP);
/* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */
cmd_config |= (cmd_index | response_type);
SDIO_CMDCTL = cmd_config;
}
/*!
\brief set the command state machine wait type
\param[in] wait_type: wait type
only one parameter can be selected which is shown as below:
\arg SDIO_WAITTYPE_NO: not wait interrupt
\arg SDIO_WAITTYPE_INTERRUPT: wait interrupt
\arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer
\param[out] none
\retval none
*/
void sdio_wait_type_set(uint32_t wait_type)
{
/* reset INTWAIT and WAITDEND */
SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND);
/* set the wait type according to wait_type */
SDIO_CMDCTL |= wait_type;
}
/*!
\brief enable the CSM(command state machine)
\param[in] none
\param[out] none
\retval none
*/
void sdio_csm_enable(void)
{
SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN;
}
/*!
\brief disable the CSM(command state machine)
\param[in] none
\param[out] none
\retval none
*/
void sdio_csm_disable(void)
{
SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN;
}
/*!
\brief get the last response command index
\param[in] none
\param[out] none
\retval last response command index
*/
uint8_t sdio_command_index_get(void)
{
return (uint8_t)SDIO_RSPCMDIDX;
}
/*!
\brief get the response for the last received command
\param[in] responsex: SDIO response
only one parameter can be selected which is shown as below:
\arg SDIO_RESPONSE0: card response[31:0]/card response[127:96]
\arg SDIO_RESPONSE1: card response[95:64]
\arg SDIO_RESPONSE2: card response[63:32]
\arg SDIO_RESPONSE3: card response[31:1], plus bit 0
\param[out] none
\retval response for the last received command
*/
uint32_t sdio_response_get(uint32_t responsex)
{
uint32_t resp_content = 0U;
switch(responsex){
case SDIO_RESPONSE0:
resp_content = SDIO_RESP0;
break;
case SDIO_RESPONSE1:
resp_content = SDIO_RESP1;
break;
case SDIO_RESPONSE2:
resp_content = SDIO_RESP2;
break;
case SDIO_RESPONSE3:
resp_content = SDIO_RESP3;
break;
default:
break;
}
return resp_content;
}
/*!
\brief configure the data timeout, data length and data block size
\param[in] data_timeout: data timeout period in card bus clock periods
\param[in] data_length: number of data bytes to be transferred
\param[in] data_blocksize: size of data block for block transfer
only one parameter can be selected which is shown as below:
\arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte
\arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes
\arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes
\arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes
\arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes
\arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes
\arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes
\arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes
\arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes
\arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes
\arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes
\arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes
\arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes
\arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes
\arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes
\param[out] none
\retval none
*/
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize)
{
/* reset data timeout, data length and data block size */
SDIO_DATATO &= ~SDIO_DATATO_DATATO;
SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN;
SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ;
/* configure the related parameters of data */
SDIO_DATATO = data_timeout;
SDIO_DATALEN = data_length;
SDIO_DATACTL |= data_blocksize;
}
/*!
\brief configure the data transfer mode and direction
\param[in] transfer_mode: mode of data transfer
only one parameter can be selected which is shown as below:
\arg SDIO_TRANSMODE_BLOCK: block transfer
\arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer
\param[in] transfer_direction: data transfer direction, read or write
only one parameter can be selected which is shown as below:
\arg SDIO_TRANSDIRECTION_TOCARD: write data to card
\arg SDIO_TRANSDIRECTION_TOSDIO: read data from card
\param[out] none
\retval none
*/
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction)
{
uint32_t data_trans = 0U;
/* reset the data transfer mode, transfer direction and set according to the parameters */
data_trans = SDIO_DATACTL;
data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR);
data_trans |= (transfer_mode | transfer_direction);
SDIO_DATACTL = data_trans;
}
/*!
\brief enable the DSM(data state machine) for data transfer
\param[in] none
\param[out] none
\retval none
*/
void sdio_dsm_enable(void)
{
SDIO_DATACTL |= SDIO_DATACTL_DATAEN;
}
/*!
\brief disable the DSM(data state machine)
\param[in] none
\param[out] none
\retval none
*/
void sdio_dsm_disable(void)
{
SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN;
}
/*!
\brief write data(one word) to the transmit FIFO
\param[in] data: 32-bit data write to card
\param[out] none
\retval none
*/
void sdio_data_write(uint32_t data)
{
SDIO_FIFO = data;
}
/*!
\brief read data(one word) from the receive FIFO
\param[in] none
\param[out] none
\retval received data
*/
uint32_t sdio_data_read(void)
{
return SDIO_FIFO;
}
/*!
\brief get the number of remaining data bytes to be transferred to card
\param[in] none
\param[out] none
\retval number of remaining data bytes to be transferred
*/
uint32_t sdio_data_counter_get(void)
{
return SDIO_DATACNT;
}
/*!
\brief get the number of words remaining to be written or read from FIFO
\param[in] none
\param[out] none
\retval remaining number of words
*/
uint32_t sdio_fifo_counter_get(void)
{
return SDIO_FIFOCNT;
}
/*!
\brief enable the DMA request for SDIO
\param[in] none
\param[out] none
\retval none
*/
void sdio_dma_enable(void)
{
SDIO_DATACTL |= SDIO_DATACTL_DMAEN;
}
/*!
\brief disable the DMA request for SDIO
\param[in] none
\param[out] none
\retval none
*/
void sdio_dma_disable(void)
{
SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN;
}
/*!
\brief get the flags state of SDIO
\param[in] flag: flags state of SDIO
one or more parameters can be selected which are shown as below:
\arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
\arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
\arg SDIO_FLAG_CMDTMOUT: command response timeout flag
\arg SDIO_FLAG_DTTMOUT: data timeout flag
\arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
\arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
\arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
\arg SDIO_FLAG_CMDSEND: command sent (no response required) flag
\arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
\arg SDIO_FLAG_STBITE: start bit error in the bus flag
\arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
\arg SDIO_FLAG_CMDRUN: command transmission in progress flag
\arg SDIO_FLAG_TXRUN: data transmission in progress flag
\arg SDIO_FLAG_RXRUN: data reception in progress flag
\arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO
\arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO
\arg SDIO_FLAG_TFF: transmit FIFO is full flag
\arg SDIO_FLAG_RFF: receive FIFO is full flag
\arg SDIO_FLAG_TFE: transmit FIFO is empty flag
\arg SDIO_FLAG_RFE: receive FIFO is empty flag
\arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag
\arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag
\arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
\arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus sdio_flag_get(uint32_t flag)
{
if(RESET != (SDIO_STAT & flag)){
return SET;
}
return RESET;
}
/*!
\brief clear the pending flags of SDIO
\param[in] flag: flags state of SDIO
one or more parameters can be selected which are shown as below:
\arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag
\arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
\arg SDIO_FLAG_CMDTMOUT: command response timeout flag
\arg SDIO_FLAG_DTTMOUT: data timeout flag
\arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag
\arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag
\arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag
\arg SDIO_FLAG_CMDSEND: command sent (no response required) flag
\arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
\arg SDIO_FLAG_STBITE: start bit error in the bus flag
\arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
\arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag
\arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
\param[out] none
\retval none
*/
void sdio_flag_clear(uint32_t flag)
{
SDIO_INTC = flag;
}
/*!
\brief enable the SDIO interrupt
\param[in] int_flag: interrupt flags state of SDIO
one or more parameters can be selected which are shown as below:
\arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
\arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
\arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
\arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
\arg SDIO_INT_TXURE: SDIO TXURE interrupt
\arg SDIO_INT_RXORE: SDIO RXORE interrupt
\arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
\arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
\arg SDIO_INT_DTEND: SDIO DTEND interrupt
\arg SDIO_INT_STBITE: SDIO STBITE interrupt
\arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
\arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
\arg SDIO_INT_TXRUN: SDIO TXRUN interrupt
\arg SDIO_INT_RXRUN: SDIO RXRUN interrupt
\arg SDIO_INT_TFH: SDIO TFH interrupt
\arg SDIO_INT_RFH: SDIO RFH interrupt
\arg SDIO_INT_TFF: SDIO TFF interrupt
\arg SDIO_INT_RFF: SDIO RFF interrupt
\arg SDIO_INT_TFE: SDIO TFE interrupt
\arg SDIO_INT_RFE: SDIO RFE interrupt
\arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
\arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
\arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
\arg SDIO_INT_ATAEND: SDIO ATAEND interrupt
\param[out] none
\retval none
*/
void sdio_interrupt_enable(uint32_t int_flag)
{
SDIO_INTEN |= int_flag;
}
/*!
\brief disable the SDIO interrupt
\param[in] int_flag: interrupt flags state of SDIO
one or more parameters can be selected which are shown as below:
\arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt
\arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt
\arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt
\arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt
\arg SDIO_INT_TXURE: SDIO TXURE interrupt
\arg SDIO_INT_RXORE: SDIO RXORE interrupt
\arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt
\arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt
\arg SDIO_INT_DTEND: SDIO DTEND interrupt
\arg SDIO_INT_STBITE: SDIO STBITE interrupt
\arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt
\arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt
\arg SDIO_INT_TXRUN: SDIO TXRUN interrupt
\arg SDIO_INT_RXRUN: SDIO RXRUN interrupt
\arg SDIO_INT_TFH: SDIO TFH interrupt
\arg SDIO_INT_RFH: SDIO RFH interrupt
\arg SDIO_INT_TFF: SDIO TFF interrupt
\arg SDIO_INT_RFF: SDIO RFF interrupt
\arg SDIO_INT_TFE: SDIO TFE interrupt
\arg SDIO_INT_RFE: SDIO RFE interrupt
\arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt
\arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt
\arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt
\arg SDIO_INT_ATAEND: SDIO ATAEND interrupt
\param[out] none
\retval none
*/
void sdio_interrupt_disable(uint32_t int_flag)
{
SDIO_INTEN &= ~int_flag;
}
/*!
\brief get the interrupt flags state of SDIO
\param[in] int_flag: interrupt flags state of SDIO
one or more parameters can be selected which are shown as below:
\arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag
\arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag
\arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag
\arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag
\arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag
\arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag
\arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag
\arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag
\arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag
\arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag
\arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag
\arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag
\arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag
\arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag
\arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag
\arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag
\arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag
\arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag
\arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag
\arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag
\arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag
\arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag
\arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag
\arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag)
{
if(RESET != (SDIO_STAT & int_flag)){
return SET;
}
return RESET;
}
/*!
\brief clear the interrupt pending flags of SDIO
\param[in] int_flag: interrupt flags state of SDIO
one or more parameters can be selected which are shown as below:
\arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag
\arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag
\arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag
\arg SDIO_INT_FLAG_DTTMOUT: data timeout flag
\arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag
\arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag
\arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag
\arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag
\arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag
\arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag
\arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag
\arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag
\arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag
\param[out] none
\retval none
*/
void sdio_interrupt_flag_clear(uint32_t int_flag)
{
SDIO_INTC = int_flag;
}
/*!
\brief enable the read wait mode(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_readwait_enable(void)
{
SDIO_DATACTL |= SDIO_DATACTL_RWEN;
}
/*!
\brief disable the read wait mode(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_readwait_disable(void)
{
SDIO_DATACTL &= ~SDIO_DATACTL_RWEN;
}
/*!
\brief enable the function that stop the read wait process(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_stop_readwait_enable(void)
{
SDIO_DATACTL |= SDIO_DATACTL_RWSTOP;
}
/*!
\brief disable the function that stop the read wait process(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_stop_readwait_disable(void)
{
SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP;
}
/*!
\brief set the read wait type(SD I/O only)
\param[in] readwait_type: SD I/O read wait type
only one parameter can be selected which is shown as below:
\arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK
\arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2]
\param[out] none
\retval none
*/
void sdio_readwait_type_set(uint32_t readwait_type)
{
if(SDIO_READWAITTYPE_CLK == readwait_type){
SDIO_DATACTL |= SDIO_DATACTL_RWTYPE;
}else{
SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE;
}
}
/*!
\brief enable the SD I/O mode specific operation(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_operation_enable(void)
{
SDIO_DATACTL |= SDIO_DATACTL_IOEN;
}
/*!
\brief disable the SD I/O mode specific operation(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_operation_disable(void)
{
SDIO_DATACTL &= ~SDIO_DATACTL_IOEN;
}
/*!
\brief enable the SD I/O suspend operation(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_suspend_enable(void)
{
SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND;
}
/*!
\brief disable the SD I/O suspend operation(SD I/O only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_suspend_disable(void)
{
SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND;
}
/*!
\brief enable the CE-ATA command(CE-ATA only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_ceata_command_enable(void)
{
SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN;
}
/*!
\brief disable the CE-ATA command(CE-ATA only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_ceata_command_disable(void)
{
SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN;
}
/*!
\brief enable the CE-ATA interrupt(CE-ATA only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_ceata_interrupt_enable(void)
{
SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN;
}
/*!
\brief disable the CE-ATA interrupt(CE-ATA only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_ceata_interrupt_disable(void)
{
SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN;
}
/*!
\brief enable the CE-ATA command completion signal(CE-ATA only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_ceata_command_completion_enable(void)
{
SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC;
}
/*!
\brief disable the CE-ATA command completion signal(CE-ATA only)
\param[in] none
\param[out] none
\retval none
*/
void sdio_ceata_command_completion_disable(void)
{
SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC;
}
#endif

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_shrtimer.c Normal file
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/*!
\file gd32e50x_spi.c
\brief SPI driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_spi.h"
/* SPI/I2S parameter initialization mask */
#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */
#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */
#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x00000480U) /*!< I2S full duples mode configure parameter initialization mask */
/* default value */
#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */
/* I2S clock source selection, multiplication and division mask */
#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /*!< I2S1 clock source selection */
#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /*!< I2S2 clock source selection */
#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /*!< I2S clock multiplication mask */
#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /*!< I2S clock division mask */
/*!
\brief reset SPI and I2S
\param[in] spi_periph: SPIx(x=0,1,2),include I2S1_ADD and I2S2_ADD
\param[out] none
\retval none
*/
void spi_i2s_deinit(uint32_t spi_periph)
{
switch(spi_periph){
case SPI0:
/* reset SPI0 */
rcu_periph_reset_enable(RCU_SPI0RST);
rcu_periph_reset_disable(RCU_SPI0RST);
break;
case SPI1:
/* reset SPI1 , I2S1 and I2S1_ADD */
rcu_periph_reset_enable(RCU_SPI1RST);
rcu_periph_reset_disable(RCU_SPI1RST);
break;
case SPI2:
/* reset SPI2 , I2S2 and I2S2_ADD */
rcu_periph_reset_enable(RCU_SPI2RST);
rcu_periph_reset_disable(RCU_SPI2RST);
break;
default :
break;
}
}
/*!
\brief initialize the parameters of SPI struct with default values
\param[in] none
\param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer
\retval none
*/
void spi_struct_para_init(spi_parameter_struct *spi_struct)
{
/* configure the structure with default value */
spi_struct->device_mode = SPI_SLAVE;
spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
spi_struct->nss = SPI_NSS_HARD;
spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
spi_struct->prescale = SPI_PSC_2;
spi_struct->endian = SPI_ENDIAN_MSB;
}
/*!
\brief initialize SPI parameter
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] spi_struct: SPI parameter initialization stuct members of the structure
and the member values are shown as below:
device_mode: SPI_MASTER, SPI_SLAVE
trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
nss: SPI_NSS_SOFT, SPI_NSS_HARD
endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
\param[out] none
\retval none
*/
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
{
uint32_t reg = 0U;
reg = SPI_CTL0(spi_periph);
reg &= SPI_INIT_MASK;
/* select SPI as master or slave */
reg |= spi_struct->device_mode;
/* select SPI transfer mode */
reg |= spi_struct->trans_mode;
/* select SPI frame size */
reg |= spi_struct->frame_size;
/* select SPI NSS use hardware or software */
reg |= spi_struct->nss;
/* select SPI LSB or MSB */
reg |= spi_struct->endian;
/* select SPI polarity and phase */
reg |= spi_struct->clock_polarity_phase;
/* select SPI prescale to adjust transmit speed */
reg |= spi_struct->prescale;
/* write to SPI_CTL0 register */
SPI_CTL0(spi_periph) = (uint32_t)reg;
SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
}
/*!
\brief enable SPI
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_enable(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
}
/*!
\brief disable SPI
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_disable(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
}
/*!
\brief initialize I2S parameter
\param[in] spi_periph: SPIx(x=1,2)
\param[in] i2s_mode: I2S operation mode
only one parameter can be selected which is shown as below:
\arg I2S_MODE_SLAVETX: I2S slave transmit mode
\arg I2S_MODE_SLAVERX: I2S slave receive mode
\arg I2S_MODE_MASTERTX: I2S master transmit mode
\arg I2S_MODE_MASTERRX: I2S master receive mode
\param[in] i2s_standard: I2S standard
only one parameter can be selected which is shown as below:
\arg I2S_STD_PHILLIPS: I2S phillips standard
\arg I2S_STD_MSB: I2S MSB standard
\arg I2S_STD_LSB: I2S LSB standard
\arg I2S_STD_PCMSHORT: I2S PCM short standard
\arg I2S_STD_PCMLONG: I2S PCM long standard
\param[in] i2s_ckpl: I2S idle state clock polarity
only one parameter can be selected which is shown as below:
\arg I2S_CKPL_LOW: I2S clock polarity low level
\arg I2S_CKPL_HIGH: I2S clock polarity high level
\param[out] none
\retval none
*/
void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl)
{
uint32_t reg= 0U;
reg = SPI_I2SCTL(spi_periph);
reg &= I2S_INIT_MASK;
/* enable I2S mode */
reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
/* select I2S mode */
reg |= (uint32_t)i2s_mode;
/* select I2S standard */
reg |= (uint32_t)i2s_standard;
/* select I2S polarity */
reg |= (uint32_t)i2s_ckpl;
/* write to SPI_I2SCTL register */
SPI_I2SCTL(spi_periph) = (uint32_t)reg;
}
/*!
\brief configure I2S prescaler
\param[in] spi_periph: SPIx(x=1,2)
\param[in] i2s_audiosample: I2S audio sample rate
only one parameter can be selected which is shown as below:
\arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
\arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
\arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
\arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
\arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
\arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
\arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
\arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
\arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
\param[in] i2s_frameformat: I2S data length and channel length
only one parameter can be selected which is shown as below:
\arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
\arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
\arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
\arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
\param[in] i2s_mckout: I2S master clock output
only one parameter can be selected which is shown as below:
\arg I2S_MCKOUT_ENABLE: I2S master clock output enable
\arg I2S_MCKOUT_DISABLE: I2S master clock output disable
\param[out] none
\retval none
*/
void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout)
{
uint32_t i2sdiv = 2U, i2sof = 0U;
uint32_t clks = 0U;
uint32_t i2sclock = 0U;
#ifdef GD32E50X_CL
uint32_t pll2mf_4 = 0U;
#endif /* GD32E50X_CL */
/* deinit SPI_I2SPSC register */
SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
#ifdef GD32E50X_CL
/* get the I2S clock source */
if(((uint32_t)spi_periph) == SPI1){
/* I2S1 clock source selection */
clks = I2S1_CLOCK_SEL;
}else{
/* I2S2 clock source selection */
clks = I2S2_CLOCK_SEL;
}
if(0U != (RCU_CFG1 & clks)){
/* get RCU PLL2 clock multiplication factor */
clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U);
pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4;
if( 0U == pll2mf_4){
if((clks > 5U) && (clks < 15U)){
/* multiplier is between 8 and 16 */
clks += 2U;
}else{
if(15U == clks){
/* multiplier is 20 */
clks = 20U;
}
}
}else{
if(clks < 15U){
/* multiplier is between 18 and 32 */
clks += 18U;
}else{
if(15U == clks){
/* multiplier is 40 */
clks = 40U;
}
}
}
/* get the PREDV1 value */
i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U);
/* calculate i2sclock based on PLL2 and PREDV1 */
i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U);
}else{
/* get system clock */
i2sclock = rcu_clock_freq_get(CK_SYS);
}
#else
/* get system clock */
i2sclock = rcu_clock_freq_get(CK_SYS);
#endif /* GD32E50X_CL */
/* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
if(I2S_MCKOUT_ENABLE == i2s_mckout){
clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample);
}else{
if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){
clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample);
}else{
clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample);
}
}
/* remove the floating point */
clks = (clks + 5U) / 10U;
i2sof = (clks & 0x00000001U);
i2sdiv = ((clks - i2sof) / 2U);
i2sof = (i2sof << 8U);
/* set the default values */
if((i2sdiv < 2U) || (i2sdiv > 255U)){
i2sdiv = 2U;
i2sof = 0U;
}
/* configure SPI_I2SPSC */
SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout);
/* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
/* configure data frame format */
SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat;
}
/*!
\brief enable I2S
\param[in] spi_periph: SPIx(x=1,2)
\param[out] none
\retval none
*/
void i2s_enable(uint32_t spi_periph)
{
SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
}
/*!
\brief disable I2S
\param[in] spi_periph: SPIx(x=1,2)
\param[out] none
\retval none
*/
void i2s_disable(uint32_t spi_periph)
{
SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
}
/*!
\brief enable SPI NSS output
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_nss_output_enable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
}
/*!
\brief disable SPI NSS output
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_nss_output_disable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
}
/*!
\brief SPI NSS pin high level in software mode
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_nss_internal_high(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
}
/*!
\brief SPI NSS pin low level in software mode
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_nss_internal_low(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
}
/*!
\brief enable SPI DMA send or receive
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] dma: SPI DMA mode
only one parameter can be selected which is shown as below:
\arg SPI_DMA_TRANSMIT: SPI transmit data use DMA
\arg SPI_DMA_RECEIVE: SPI receive data use DMA
\param[out] none
\retval none
*/
void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
{
if(SPI_DMA_TRANSMIT == dma){
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
}else{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
}
}
/*!
\brief disable SPI DMA send or receive
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] dma: SPI DMA mode
only one parameter can be selected which is shown as below:
\arg SPI_DMA_TRANSMIT: SPI transmit data use DMA
\arg SPI_DMA_RECEIVE: SPI receive data use DMA
\param[out] none
\retval none
*/
void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
{
if(SPI_DMA_TRANSMIT == dma){
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
}else{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
}
}
/*!
\brief configure SPI/I2S data frame format
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] frame_format: SPI frame size
only one parameter can be selected which is shown as below:
\arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
\arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
\param[out] none
\retval none
*/
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
{
/* clear SPI_CTL0_FF16 bit */
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
/* confige SPI_CTL0_FF16 bit */
SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
}
/*!
\brief SPI transmit data
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] data: 16-bit data
\param[out] none
\retval none
*/
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
{
SPI_DATA(spi_periph) = (uint32_t)data;
}
/*!
\brief SPI receive data
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval 16-bit data
*/
uint16_t spi_i2s_data_receive(uint32_t spi_periph)
{
return ((uint16_t)SPI_DATA(spi_periph));
}
/*!
\brief configure SPI bidirectional transfer direction
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] transfer_direction: SPI transfer direction
only one parameter can be selected which is shown as below:
\arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
\arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
\retval none
*/
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
{
if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
/* set the transmit only mode */
SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
}else{
/* set the receive only mode */
SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
}
}
/*!
\brief set SPI CRC polynomial
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] crc_poly: CRC polynomial value
\param[out] none
\retval none
*/
void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly)
{
/* enable SPI CRC */
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
/* set SPI CRC polynomial */
SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
}
/*!
\brief get SPI CRC polynomial
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval 16-bit CRC polynomial
*/
uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
{
return ((uint16_t)SPI_CRCPOLY(spi_periph));
}
/*!
\brief turn on CRC function
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_crc_on(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
}
/*!
\brief turn off CRC function
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_crc_off(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
}
/*!
\brief SPI next data is CRC value
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_crc_next(uint32_t spi_periph)
{
SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
}
/*!
\brief get SPI CRC send value or receive value
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] crc: SPI crc value
only one parameter can be selected which is shown as below:
\arg SPI_CRC_TX: get transmit crc value
\arg SPI_CRC_RX: get receive crc value
\param[out] none
\retval 16-bit CRC value
*/
uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc)
{
if(SPI_CRC_TX == crc){
return ((uint16_t)(SPI_TCRC(spi_periph)));
}else{
return ((uint16_t)(SPI_RCRC(spi_periph)));
}
}
/*!
\brief enable SPI TI mode
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_ti_mode_enable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
}
/*!
\brief disable SPI TI mode
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_ti_mode_disable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
}
/*!
\brief enable SPI NSS pulse mode
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_nssp_mode_enable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
}
/*!
\brief disable SPI NSS pulse mode
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_nssp_mode_disable(uint32_t spi_periph)
{
SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
}
/*!
\brief configure i2s full duplex mode
\param[in] i2s_add_periph: I2Sx_ADD(x=1,2)
\param[in] i2s_mode:
\arg I2S_MODE_SLAVETX : I2S slave transmit mode
\arg I2S_MODE_SLAVERX : I2S slave receive mode
\arg I2S_MODE_MASTERTX : I2S master transmit mode
\arg I2S_MODE_MASTERRX : I2S master receive mode
\param[in] i2s_standard:
\arg I2S_STD_PHILLIPS : I2S phillips standard
\arg I2S_STD_MSB : I2S MSB standard
\arg I2S_STD_LSB : I2S LSB standard
\arg I2S_STD_PCMSHORT : I2S PCM short standard
\arg I2S_STD_PCMLONG : I2S PCM long standard
\param[in] i2s_ckpl:
\arg I2S_CKPL_LOW : I2S clock polarity low level
\arg I2S_CKPL_HIGH : I2S clock polarity high level
\param[in] i2s_frameformat:
\arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
\arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
\arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
\arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
\param[out] none
\retval none
*/
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard,
uint32_t i2s_ckpl, uint32_t i2s_frameformat)
{
uint32_t reg = 0U, tmp = 0U;
reg = I2S_ADD_I2SCTL(i2s_add_periph);
reg &= I2S_FULL_DUPLEX_MASK;
/* get the mode of the extra I2S module I2Sx_ADD */
if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){
tmp = I2S_MODE_SLAVERX;
}else{
tmp = I2S_MODE_SLAVETX;
}
/* enable I2S mode */
reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
/* select I2S mode */
reg |= (uint32_t)tmp;
/* select I2S standard */
reg |= (uint32_t)i2s_standard;
/* select I2S polarity */
reg |= (uint32_t)i2s_ckpl;
/* configure data frame format */
reg |= (uint32_t)i2s_frameformat;
/* write to SPI_I2SCTL register */
I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg;
}
/*!
\brief enable quad wire SPI
\param[in] spi_periph: SPIx(only x=0)
\param[out] none
\retval none
*/
void qspi_enable(uint32_t spi_periph)
{
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
}
/*!
\brief disable quad wire SPI
\param[in] spi_periph: SPIx(only x=0)
\param[out] none
\retval none
*/
void qspi_disable(uint32_t spi_periph)
{
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
}
/*!
\brief enable quad wire SPI write
\param[in] spi_periph: SPIx(only x=0)
\param[out] none
\retval none
*/
void qspi_write_enable(uint32_t spi_periph)
{
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
}
/*!
\brief enable quad wire SPI read
\param[in] spi_periph: SPIx(only x=0)
\param[out] none
\retval none
*/
void qspi_read_enable(uint32_t spi_periph)
{
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
}
/*!
\brief enable SPI_IO2 and SPI_IO3 pin output
\param[in] spi_periph: SPIx(only x=0)
\param[out] none
\retval none
*/
void qspi_io23_output_enable(uint32_t spi_periph)
{
SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
}
/*!
\brief disable SPI_IO2 and SPI_IO3 pin output
\param[in] spi_periph: SPIx(only x=0)
\param[out] none
\retval none
*/
void qspi_io23_output_disable(uint32_t spi_periph)
{
SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
}
/*!
\brief enable SPI and I2S interrupt
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] interrupt: SPI/I2S interrupt
only one parameter can be selected which is shown as below:
\arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
\arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
\arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
transmission underrun error and format error interrupt
\param[out] none
\retval none
*/
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
{
SPI_CTL1(spi_periph) |= (uint32_t)interrupt;
}
/*!
\brief disable SPI and I2S interrupt
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] interrupt: SPI/I2S interrupt
only one parameter can be selected which is shown as below:
\arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
\arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
\arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
transmission underrun error and format error interrupt
\param[out] none
\retval none
*/
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
{
SPI_CTL1(spi_periph) &= ~(uint32_t)interrupt;
}
/*!
\brief get SPI and I2S interrupt flag status
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] interrupt: SPI/I2S interrupt flag status
only one parameter can be selected which is shown as below:
\arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
\arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
\arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
\arg SPI_INT_FLAG_CONFERR: config error interrupt flag
\arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag
\arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag
\arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
{
uint32_t reg1 = SPI_STAT(spi_periph);
uint32_t reg2 = SPI_CTL1(spi_periph);
switch(interrupt){
/* SPI/I2S transmit buffer empty interrupt */
case SPI_I2S_INT_FLAG_TBE:
reg1 = reg1 & SPI_STAT_TBE;
reg2 = reg2 & SPI_CTL1_TBEIE;
break;
/* SPI/I2S receive buffer not empty interrupt */
case SPI_I2S_INT_FLAG_RBNE:
reg1 = reg1 & SPI_STAT_RBNE;
reg2 = reg2 & SPI_CTL1_RBNEIE;
break;
/* SPI/I2S overrun interrupt */
case SPI_I2S_INT_FLAG_RXORERR:
reg1 = reg1 & SPI_STAT_RXORERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* SPI config error interrupt */
case SPI_INT_FLAG_CONFERR:
reg1 = reg1 & SPI_STAT_CONFERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* SPI CRC error interrupt */
case SPI_INT_FLAG_CRCERR:
reg1 = reg1 & SPI_STAT_CRCERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* I2S underrun error interrupt */
case I2S_INT_FLAG_TXURERR:
reg1 = reg1 & SPI_STAT_TXURERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
/* SPI/I2S format error interrupt */
case SPI_I2S_INT_FLAG_FERR:
reg1 = reg1 & SPI_STAT_FERR;
reg2 = reg2 & SPI_CTL1_ERRIE;
break;
default :
break;
}
/*get SPI/I2S interrupt flag status */
if(reg1 && reg2){
return SET;
}else{
return RESET;
}
}
/*!
\brief get SPI and I2S flag status
\param[in] spi_periph: SPIx(x=0,1,2)
\param[in] flag: SPI/I2S flag status
only one parameter can be selected which is shown as below:
\arg SPI_FLAG_TBE: transmit buffer empty flag
\arg SPI_FLAG_RBNE: receive buffer not empty flag
\arg SPI_FLAG_TRANS: transmit on-going flag
\arg SPI_FLAG_RXORERR: receive overrun error flag
\arg SPI_FLAG_CONFERR: mode config error flag
\arg SPI_FLAG_CRCERR: CRC error flag
\arg SPI_FLAG_FERR: format error flag
\arg I2S_FLAG_TBE: transmit buffer empty flag
\arg I2S_FLAG_RBNE: receive buffer not empty flag
\arg I2S_FLAG_TRANS: transmit on-going flag
\arg I2S_FLAG_RXORERR: overrun error flag
\arg I2S_FLAG_TXURERR: underrun error flag
\arg I2S_FLAG_CH: channel side flag
\arg I2S_FLAG_FERR: format error flag
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
{
if(SPI_STAT(spi_periph) & flag){
return SET;
}else{
return RESET;
}
}
/*!
\brief clear SPI CRC error flag status
\param[in] spi_periph: SPIx(x=0,1,2)
\param[out] none
\retval none
*/
void spi_crc_error_clear(uint32_t spi_periph)
{
SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
}

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/*!
\file gd32e50x_sqpi.c
\brief SQPI driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_sqpi.h"
/*!
\brief reset SQPI
\param[in] none
\param[out] none
\retval none
*/
void sqpi_deinit(void)
{
rcu_periph_reset_enable(RCU_SQPIRST);
rcu_periph_reset_disable(RCU_SQPIRST);
}
/*!
\brief initialize the parameters of SQPI struct with the default values
\param[in] sqpi_struct: SQPI parameter stuct
\param[out] none
\retval none
*/
void sqpi_struct_para_init(sqpi_parameter_struct* sqpi_struct)
{
/* set the SQPI struct with the default values */
sqpi_struct->polarity = SQPI_SAMPLE_POLARITY_RISING;
sqpi_struct->id_length = SQPI_ID_LENGTH_32_BITS;
sqpi_struct->addr_bit = 24U;
sqpi_struct->clk_div = 2U;
sqpi_struct->cmd_bit = SQPI_CMDBIT_8_BITS;
}
/*!
\brief initialize SQPI parameter
\param[in] sqpi_struct: SQPI parameter initialization stuct members of the structure
and the member values are shown as below:
polarity: SQPI_SAMPLE_POLARITY_RISING, SQPI_SAMPLE_POLARITY_FALLING
id_length: SQPI_ID_LENGTH_n_BITS (n=8,16,32,64)
addr_bit: 0x00 - 0x1F
clk_div: 0x01 - 0x3F
cmd_bit: SQPI_CMDBIT_n_BITS (n=4,8,16)
\param[out] none
\retval none
*/
void sqpi_init(sqpi_parameter_struct *sqpi_struct)
{
__IO uint32_t temp = 0U;
temp |= ((sqpi_struct->polarity)|sqpi_struct->id_length|sqpi_struct->cmd_bit);
temp |= ((sqpi_struct->addr_bit << 24U) | sqpi_struct->clk_div << 18U);
SQPI_INIT = temp;
}
/*!
\brief send SQPI read ID command
\param[in] none
\param[out] none
\retval none
*/
void sqpi_read_id_command(void)
{
while((SQPI_RCMD & SQPI_RCMD_RID) != RESET){
}
SQPI_RCMD |= SQPI_RCMD_RID;
while((SQPI_RCMD & SQPI_RCMD_RID) != RESET){
}
}
/*!
\brief send SQPI special command
\param[in] none
\param[out] none
\retval none
*/
void sqpi_special_command(void)
{
while((SQPI_WCMD & SQPI_WCMD_SCMD) != RESET){
}
SQPI_WCMD |= SQPI_WCMD_SCMD;
while((SQPI_WCMD & SQPI_WCMD_SCMD) != RESET){
}
}
/*!
\brief configure SQPI read command
\param[in] rmode: SQPI_MODE_SSQ, SQPI_MODE_SSS, SQPI_MODE_SQQ, SQPI_MODE_QQQ, SQPI_MODE_SSD, SQPI_MODE_SDD
rwaitcycle: 0x00 - 0x1F
rcmd: 0x00 - 0xFF
\param[out] none
\retval none
*/
void sqpi_read_command_config(uint32_t rmode, uint32_t rwaitcycle, uint32_t rcmd)
{
__IO uint32_t temp = 0U;
temp |= (rcmd | (rwaitcycle << 16U) | rmode);
SQPI_RCMD = temp;
}
/*!
\brief configure SQPI write command
\param[in] wmode: SQPI_MODE_SSQ, SQPI_MODE_SSS, SQPI_MODE_SQQ, SQPI_MODE_QQQ, SQPI_MODE_SSD, SQPI_MODE_SDD
wwaitcycle: 0x00 - 0x1F
wcmd: 0x00 - 0xFF
\param[out] none
\retval none
*/
void sqpi_write_command_config(uint32_t wmode, uint32_t wwaitcycle, uint32_t wcmd)
{
__IO uint32_t temp = 0U;
temp |= (wcmd | (wwaitcycle << 16U) | wmode);
SQPI_WCMD = temp;
}
/*!
\brief SQPI receive low ID
\param[in] none
\param[out] none
\retval 32-bit low ID
*/
uint32_t sqpi_low_id_receive(void)
{
__IO uint32_t temp = 0U;
temp = SQPI_IDL;
return temp;
}
/*!
\brief SQPI receive high ID
\param[in] none
\param[out] none
\retval 32-bit high ID
*/
uint32_t sqpi_high_id_receive(void)
{
__IO uint32_t temp = 0U;
temp = SQPI_IDH;
return temp;
}

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/*!
\file gd32e50x_tmu.c
\brief TMU driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_tmu.h"
#ifdef GD32E50X_CL
/*!
\brief reset the TMU
\param[in] none
\param[out] none
\retval none
*/
void tmu_deinit(void)
{
/* reset TMU */
rcu_periph_reset_enable(RCU_TMURST);
rcu_periph_reset_disable(RCU_TMURST);
}
/*!
\brief enable the TMU
\param[in] none
\param[out] none
\retval none
*/
void tmu_enable(void)
{
TMU_CTL |= (uint32_t)TMU_CTL_TMUEN;
}
/*!
\brief configure the TMU mode
\param[in] modex: the operation mode of TMU
\arg TMU_MODE0: the operation mode0
\arg TMU_MODE1: the operation mode1
\arg TMU_MODE2: the operation mode2
\arg TMU_MODE2: the operation mode3
\arg TMU_MODE2: the operation mode4
\arg TMU_MODE1: the operation mode5
\arg TMU_MODE2: the operation mode6
\arg TMU_MODE2: the operation mode7
\arg TMU_MODE2: the operation mode8
\param[out] none
\retval none
*/
void tmu_mode_set(uint32_t modex)
{
TMU_CTL &= (uint32_t)(~ TMU_CTL_MODE);
TMU_CTL |= (uint32_t)modex;
}
/*!
\brief write the data to TMU input data0 regisetr
\param[in] idata0: the value write to input data0
idata0 must meet IEEE 32-Bit Single Precision Floating-Point Format.
\param[out] none
\retval none
*/
void tmu_idata0_write(uint32_t idata0)
{
TMU_IDATA0 &= (uint32_t)(~ TMU_IDATA0_IDATA0);
TMU_IDATA0 = idata0;
}
/*!
\brief write the data to TMU input data1 regisetr
\param[in] idata1: the value write to input data1(idata1 only uesed for MODE6,MODE7,MODE8)
idata1 must meet IEEE 32-Bit Single Precision Floating-Point Format
\param[out] none
\retval none
*/
void tmu_idata1_write(uint32_t idata1)
{
TMU_IDATA1 &= (uint32_t)(~ TMU_IDATA1_IDATA1);
TMU_IDATA1 = idata1;
}
/*!
\brief read the data from TMU data0 regisetr
\param[in] none
\param[out] none
\retval 32-bit value of the data0 register.
the value of data0 register meet IEEE 32-Bit Single Precision Floating-Point Format
*/
uint32_t tmu_data0_read(void)
{
uint32_t data0;
data0 = TMU_DATA0;
return (data0);
}
/*!
\brief read the data from TMU data1 regisetr
\param[in] none
\param[out] none
\retval 32-bit value of the data1 register.
the value of data1 register meet IEEE 32-Bit Single Precision Floating-Point Format
*/
uint32_t tmu_data1_read(void)
{
uint32_t data1;
data1 = TMU_DATA1;
return (data1);
}
/*!
\brief enable TMU interrupt
\param[in] none
\param[out] none
\retval none
*/
void tmu_interrupt_enable(void)
{
TMU_CTL &= (uint32_t)(~ TMU_CTL_CFIE);
TMU_CTL |= (uint32_t)TMU_CTL_CFIE;
}
/*!
\brief disable TMU interrupt
\param[in] none
\param[out] none
\retval none
*/
void tmu_interrupt_disable(void)
{
TMU_CTL &= (uint32_t)(~ TMU_CTL_CFIE);
}
/*!
\brief check the TMU status flag
\param[in] flag: teh TMU status flag
only one parameter can be selected which is shown as below:
\arg TMU_FLAG_OVRF: the flag of TMU overflow
\arg TMU_FLAG_UDRF: the flag of TMU underflow
\param[out] none
\retval none
*/
FlagStatus tmu_flag_get(uint32_t flag)
{
if(TMU_STAT & flag){
return SET;
}else{
return RESET;
}
}
/*!
\brief check teh TMU interrupt flag
\param[in] int_flag: teh TMU interrupt flag
\arg TMU_INT_FLAG_CFIF: the interrupt flag of calculation finished
\param[out] none
\retval none
*/
FlagStatus tmu_interrupt_flag_get(uint32_t int_flag)
{
uint32_t reg = TMU_CTL;
if((reg & int_flag)&&(reg & TMU_CTL_CFIE)){
return SET;
}else{
return RESET;
}
}
#endif /* GD32E50x_CL */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_standard_peripheral/Source/gd32e50x_wwdgt.c Normal file
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/*!
\file gd32e50x_wwdgt.c
\brief WWDGT driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32e50x_wwdgt.h"
/* write value to WWDGT_CTL_CNT bit field */
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
/* write value to WWDGT_CFG_WIN bit field */
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
/*!
\brief reset the WWDGT configuration
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_deinit(void)
{
rcu_periph_reset_enable(RCU_WWDGTRST);
rcu_periph_reset_disable(RCU_WWDGTRST);
}
/*!
\brief start the WWDGT counter
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_enable(void)
{
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
}
/*!
\brief configure the WWDGT value
\param[in] counter_value: 0x00 - 0x7F
\param[out] none
\retval none
*/
void wwdgt_counter_update(uint16_t counter_value)
{
uint32_t reg = 0U;
reg = (WWDGT_CTL & (~WWDGT_CTL_CNT));
reg |= CTL_CNT(counter_value);
WWDGT_CTL = reg;
}
/*!
\brief configure counter value, window value, and prescaler divider value
\param[in] counter: 0x00 - 0x7F
\param[in] window: 0x00 - 0x7F
\param[in] prescaler: wwdgt prescaler value
only one parameter can be selected which is shown as below:
\arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
\arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
\arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
\arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
\param[out] none
\retval none
*/
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
{
uint32_t reg_cfg = 0U, reg_ctl = 0U;
/* clear WIN and PSC bits, clear CNT bit */
reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC)));
reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT));
/* configure WIN and PSC bits, configure CNT bit */
reg_cfg |= CFG_WIN(window);
reg_cfg |= prescaler;
reg_ctl |= CTL_CNT(counter);
WWDGT_CTL = reg_ctl;
WWDGT_CFG = reg_cfg;
}
/*!
\brief enable early wakeup interrupt of WWDGT
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_interrupt_enable(void)
{
WWDGT_CFG |= WWDGT_CFG_EWIE;
}
/*!
\brief check early wakeup interrupt state of WWDGT
\param[in] none
\param[out] none
\retval FlagStatus: SET or RESET
*/
FlagStatus wwdgt_flag_get(void)
{
if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){
return SET;
}
return RESET;
}
/*!
\brief clear early wakeup interrupt state of WWDGT
\param[in] none
\param[out] none
\retval none
*/
void wwdgt_flag_clear(void)
{
WWDGT_STAT &= (~WWDGT_STAT_EWIF);
}

261
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/audio/Include/audio_core.h Normal file
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/*!
\file audio_core.h
\brief the header file of USB audio device class core functions
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __AUDIO_CORE_H
#define __AUDIO_CORE_H
#include "usbd_enum.h"
#define FORMAT_24BIT(x) (uint8_t)(x);(uint8_t)((x) >> 8);(uint8_t)((x) >> 16)
/* audio_freq * data_size (2 bytes) * num_channels (stereo: 2) */
#define DEFAULT_OUT_BIT_RESOLUTION 16U
#define DEFAULT_OUT_CHANNEL_NBR 2U /* mono = 1, stereo = 2 */
#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ_16K * \
(DEFAULT_OUT_BIT_RESOLUTION / 8U) *\
DEFAULT_OUT_CHANNEL_NBR) / 1000U))
/* number of sub-packets in the audio transfer buffer. you can modify this value but always make sure
that it is an even number and higher than 3 */
#define OUT_PACKET_NUM 4U
/* total size of the audio transfer buffer */
#define OUT_BUF_MARGIN 4U
#define TOTAL_OUT_BUF_SIZE ((uint32_t)((AUDIO_OUT_PACKET + OUT_BUF_MARGIN) * OUT_PACKET_NUM))
#define AUDIO_CONFIG_DESC_SET_LEN 109U
#define AUDIO_INTERFACE_DESC_SIZE 9U
#define USB_AUDIO_DESC_SIZ 0x09U
#define AUDIO_STANDARD_EP_DESC_SIZE 0x09U
#define AUDIO_STREAMING_EP_DESC_SIZE 0x07U
/* audio interface class code */
#define USB_CLASS_AUDIO 0x01U
/* audio interface subclass codes */
#define AUDIO_SUBCLASS_CONTROL 0x01U
#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02U
#define AUDIO_SUBCLASS_MIDISTREAMING 0x03U
/* audio interface protocol codes */
#define AUDIO_PROTOCOL_UNDEFINED 0x00U
#define AUDIO_STREAMING_GENERAL 0x01U
#define AUDIO_STREAMING_FORMAT_TYPE 0x02U
/* audio class-specific descriptor types */
#define AUDIO_DESCTYPE_UNDEFINED 0x20U
#define AUDIO_DESCTYPE_DEVICE 0x21U
#define AUDIO_DESCTYPE_CONFIGURATION 0x22U
#define AUDIO_DESCTYPE_STRING 0x23U
#define AUDIO_DESCTYPE_INTERFACE 0x24U
#define AUDIO_DESCTYPE_ENDPOINT 0x25U
/* audio control interface descriptor subtypes */
#define AUDIO_CONTROL_HEADER 0x01U
#define AUDIO_CONTROL_INPUT_TERMINAL 0x02U
#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U
#define AUDIO_CONTROL_MIXER_UNIT 0x04U
#define AUDIO_CONTROL_SELECTOR_UNIT 0x05U
#define AUDIO_CONTROL_FEATURE_UNIT 0x06U
#define AUDIO_CONTROL_PROCESSING_UNIT 0x07U
#define AUDIO_CONTROL_EXTENSION_UNIT 0x08U
#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0CU
#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09U
#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07U
#define AUDIO_CONTROL_MUTE 0x0001U
#define AUDIO_FORMAT_TYPE_I 0x01U
#define AUDIO_FORMAT_TYPE_III 0x03U
#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01U
#define AUDIO_ENDPOINT_GENERAL 0x01U
#define AUDIO_REQ_GET_CUR 0x81U
#define AUDIO_REQ_SET_CUR 0x01U
#define AUDIO_OUT_STREAMING_CTRL 0x02U
#define PACKET_SIZE(freq) (((freq) * 2U) * 2U / 1000U)
#define AUDIO_PACKET_SIZE(frq) (uint8_t)(PACKET_SIZE(frq) & 0xFFU), \
(uint8_t)((PACKET_SIZE(frq) >> 8U) & 0xFFU)
#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq) >> 8U), \
(uint8_t)((frq) >> 16U)
#pragma pack(1)
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< header descriptor subtype */
uint16_t bcdADC; /*!< audio device class specification release number in binary-coded decimal */
uint16_t wTotalLength; /*!< total number of bytes */
uint8_t bInCollection; /*!< the number of the streaming interfaces */
uint8_t baInterfaceNr; /*!< interface number of the streaming interfaces */
} usb_desc_AC_itf;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< AS_GENERAL descriptor subtype */
uint8_t bTerminalLink; /*!< the terminal ID */
uint8_t bDelay; /*!< delay introduced by the data path */
uint16_t wFormatTag; /*!< the audio data format */
} usb_desc_AS_itf;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< INPUT_TERMINAL descriptor subtype. */
uint8_t bTerminalID; /*!< constant uniquely identifying the terminal within the audio function */
uint16_t wTerminalType; /*!< constant characterizing the type of terminal */
uint8_t bAssocTerminal; /*!< ID of the output terminal */
uint8_t bNrChannels; /*!< number of logical output channels */
uint16_t wChannelConfig; /*!< describes the spatial location of the logical channels */
uint8_t iChannelNames; /*!< index of a channel string descriptor */
uint8_t iTerminal; /*!< index of a string descriptor */
} usb_desc_input_terminal;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< OUTPUT_TERMINAL descriptor subtype */
uint8_t bTerminalID; /*!< constant uniquely identifying the terminal within the audio function */
uint16_t wTerminalType; /*!< constant characterizing the type of terminal */
uint8_t bAssocTerminal; /*!< constant, identifying the input terminal to which this output terminal is associated */
uint8_t bSourceID; /*!< ID of the unit or terminal */
uint8_t iTerminal; /*!< index of a string descriptor */
} usb_desc_output_terminal;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */
uint8_t bUnitID; /*!< constant uniquely identifying the unit within the audio function */
uint8_t bSourceID; /*!< ID of the unit or terminal */
uint8_t bControlSize; /*!< size in bytes of an element of the bmaControls() array */
uint8_t bmaControls0; /*!< a bit set to 1 indicates that the mentioned control is supported for master channel 0 */
uint8_t bmaControls1; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 1 */
uint8_t iFeature; /*!< index of a string descriptor */
} usb_desc_mono_feature_unit;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */
uint8_t bUnitID; /*!< constant uniquely identifying the unit within the audio function */
uint8_t bSourceID; /*!< ID of the unit or terminal */
uint8_t bControlSize; /*!< size in bytes of an element of the bmaControls() array */
uint16_t bmaControls0; /*!< a bit set to 1 indicates that the mentioned control is supported for master channel 0 */
uint16_t bmaControls1; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 1 */
uint16_t bmaControls2; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 2 */
uint8_t iFeature; /*!< index of a string descriptor */
} usb_desc_stereo_feature_unit;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< FORMAT_TYPE descriptor subtype */
uint8_t bFormatType; /*!< constant identifying the format type */
uint8_t bNrChannels; /*!< indicates the number of physical channels in the audio data stream */
uint8_t bSubFrameSize; /*!< the number of bytes occupied by one audio subframe */
uint8_t bBitResolution; /*!< the number of effectively used bits from the available bits in an audio subframe */
uint8_t bSamFreqType; /*!< indicates how the sampling frequency can be programmed */
uint8_t bSamFreq[3]; /*!< sampling frequency ns in Hz for this isochronous data endpoint */
} usb_desc_format_type;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bEndpointAddress; /*!< the address of the endpoint */
uint8_t bmAttributes; /*!< transfer type and synchronization type */
uint16_t wMaxPacketSize; /*!< maximum packet size this endpoint is capable of sending or receiving */
uint8_t bInterval; /*!< left to the designer's discretion */
uint8_t bRefresh; /*!< reset to 0 */
uint8_t bSynchAddress; /*!< reset to 0 */
} usb_desc_std_ep;
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bDescriptorSubtype; /*!< EP_GENERAL descriptor subtype */
uint8_t bmAttributes; /*!< transfer type and synchronization type */
uint8_t bLockDelayUnits; /*!< indicates the units used for the wLockDelay field */
uint16_t wLockDelay; /*!< indicates the time it takes this endpoint to reliably lock its internal clock recovery circuitry */
} usb_desc_AS_ep;
#pragma pack()
/* USB configuration descriptor struct */
typedef struct
{
usb_desc_config config;
usb_desc_itf std_itf;
usb_desc_AC_itf ac_itf;
usb_desc_input_terminal in_terminal;
usb_desc_mono_feature_unit feature_unit;
usb_desc_output_terminal out_terminal;
usb_desc_itf std_as_itf_zeroband;
usb_desc_itf std_as_itf_opera;
usb_desc_AS_itf as_itf;
usb_desc_format_type format_typeI;
usb_desc_std_ep std_endpoint;
usb_desc_AS_ep as_endpoint;
} usb_desc_config_set;
typedef struct
{
/* main buffer for audio data out transfers and its relative pointers */
uint8_t isoc_out_buff[TOTAL_OUT_BUF_SIZE * 2U];
uint8_t* isoc_out_wrptr;
uint8_t* isoc_out_rdptr;
/* main buffer for audio control requests transfers and its relative variables */
uint8_t audioctl[64];
uint8_t audioctl_unit;
uint32_t audioctl_len;
uint32_t play_flag;
} usbd_audio_handler;
extern usb_desc audio_desc;
extern usb_class audio_class;
#endif /* __AUDIO_CORE_H */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/audio/Include/audio_out_itf.h Normal file
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/*!
\file audio_out_itf.h
\brief audio OUT (playback) interface header file
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __AUDIO_OUT_ITF_H
#define __AUDIO_OUT_ITF_H
#include "usbd_conf.h"
/* audio commands enumeration */
typedef enum
{
AUDIO_CMD_PLAY = 1U,
AUDIO_CMD_PAUSE,
AUDIO_CMD_STOP,
}audio_cmd_enum;
/* mute commands */
#define AUDIO_MUTE 0x01U
#define AUDIO_UNMUTE 0x00U
/* functions return value */
#define AUDIO_OK 0x00U
#define AUDIO_FAIL 0xFFU
/* audio machine states */
#define AUDIO_STATE_INACTIVE 0x00U
#define AUDIO_STATE_ACTIVE 0x01U
#define AUDIO_STATE_PLAYING 0x02U
#define AUDIO_STATE_PAUSED 0x03U
#define AUDIO_STATE_STOPPED 0x04U
#define AUDIO_STATE_ERROR 0x05U
typedef struct {
uint8_t (*audio_init) (uint32_t audio_freq, uint32_t volume, uint32_t options);
uint8_t (*audio_deinit) (uint32_t options);
uint8_t (*audio_cmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd);
uint8_t (*audio_volume_ctl) (uint8_t vol);
uint8_t (*audio_mute_ctl) (uint8_t cmd);
uint8_t (*audio_periodic_tc) (uint8_t cmd);
uint8_t (*audio_state_get) (void);
} audio_fops_struct;
extern audio_fops_struct audio_out_fops;
#endif /* __AUDIO_OUT_ITF_H */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/audio/Source/audio_core.c Normal file
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/*!
\file audio_core.c
\brief USB audio device class core functions
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "usbd_transc.h"
#include "audio_out_itf.h"
#include "audio_core.h"
#include <string.h>
#define USBD_VID 0x28E9U
#define USBD_PID 0x9574U
static uint8_t usbd_audio_sof (usb_dev *udev);
static uint8_t audio_init (usb_dev *udev, uint8_t config_index);
static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index);
static uint8_t audio_req_handler (usb_dev *udev, usb_req *req);
static uint8_t audio_ctlx_out (usb_dev *udev);
static void audio_data_out (usb_dev *udev, uint8_t ep_num);
usb_class audio_class = {
.init = audio_init,
.deinit = audio_deinit,
.req_process = audio_req_handler,
.ctlx_out = audio_ctlx_out,
.data_out = audio_data_out
};
usbd_int_cb_struct usb_inthandler =
{
usbd_audio_sof,
};
/* note:it should use the c99 standard when compiling the below codes */
/* USB standard device descriptor */
usb_desc_dev audio_dev_desc =
{
.header =
{
.bLength = USB_DEV_DESC_LEN,
.bDescriptorType = USB_DESCTYPE_DEV
},
.bcdUSB = 0x0200U,
.bDeviceClass = 0x00U,
.bDeviceSubClass = 0x00U,
.bDeviceProtocol = 0x00U,
.bMaxPacketSize0 = USBD_EP0_MAX_SIZE,
.idVendor = USBD_VID,
.idProduct = USBD_PID,
.bcdDevice = 0x0100U,
.iManufacturer = STR_IDX_MFC,
.iProduct = STR_IDX_PRODUCT,
.iSerialNumber = STR_IDX_SERIAL,
.bNumberConfigurations = USBD_CFG_MAX_NUM
};
/* USB device configuration descriptor */
usb_desc_config_set audio_config_set =
{
.config =
{
.header =
{
.bLength = sizeof(usb_desc_config),
.bDescriptorType = USB_DESCTYPE_CONFIG
},
.wTotalLength = AUDIO_CONFIG_DESC_SET_LEN,
.bNumInterfaces = 0x02U,
.bConfigurationValue = 0x01U,
.iConfiguration = 0x00U,
.bmAttributes = 0xC0U,
.bMaxPower = 0x32U
},
.std_itf =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x00U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x00U,
.bInterfaceClass = USB_CLASS_AUDIO,
.bInterfaceSubClass = AUDIO_SUBCLASS_CONTROL,
.bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED,
.iInterface = 0x00U
},
.ac_itf =
{
.header =
{
.bLength = sizeof(usb_desc_AC_itf),
.bDescriptorType = AUDIO_DESCTYPE_INTERFACE
},
.bDescriptorSubtype = 0x01U,
.bcdADC = 0x0100U,
.wTotalLength = 0x0027U,
.bInCollection = 0x01U,
.baInterfaceNr = 0x01U
},
.in_terminal =
{
.header =
{
.bLength = sizeof(usb_desc_input_terminal),
.bDescriptorType = AUDIO_DESCTYPE_INTERFACE
},
.bDescriptorSubtype = 0x02U,
.bTerminalID = 0x01U,
.wTerminalType = 0x0101U,
.bAssocTerminal = 0x00U,
.bNrChannels = 0x01U,
.wChannelConfig = 0x0000U,
.iChannelNames = 0x00U,
.iTerminal = 0x00U
},
.feature_unit =
{
.header =
{
.bLength = sizeof(usb_desc_mono_feature_unit),
.bDescriptorType = AUDIO_DESCTYPE_INTERFACE
},
.bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT,
.bUnitID = AUDIO_OUT_STREAMING_CTRL,
.bSourceID = 0x01U,
.bControlSize = 0x01U,
.bmaControls0 = AUDIO_CONTROL_MUTE,
.bmaControls1 = 0x00U,
.iFeature = 0x00U
},
.out_terminal =
{
.header =
{
.bLength = sizeof(usb_desc_output_terminal),
.bDescriptorType = AUDIO_DESCTYPE_INTERFACE
},
.bDescriptorSubtype = AUDIO_CONTROL_OUTPUT_TERMINAL,
.bTerminalID = 0x03U,
.wTerminalType = 0x0301U,
.bAssocTerminal = 0x00U,
.bSourceID = 0x02U,
.iTerminal = 0x00U
},
.std_as_itf_zeroband =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x01U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x00U,
.bInterfaceClass = USB_CLASS_AUDIO,
.bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING,
.bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED,
.iInterface = 0x00U
},
.std_as_itf_opera =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x01U,
.bAlternateSetting = 0x01U,
.bNumEndpoints = 0x01U,
.bInterfaceClass = USB_CLASS_AUDIO,
.bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING,
.bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED,
.iInterface = 0x00U
},
.as_itf =
{
.header =
{
.bLength = sizeof(usb_desc_AS_itf),
.bDescriptorType = AUDIO_DESCTYPE_INTERFACE
},
.bDescriptorSubtype = AUDIO_STREAMING_GENERAL,
.bTerminalLink = 0x01U,
.bDelay = 0x01U,
.wFormatTag = 0x0001U,
},
.format_typeI =
{
.header =
{
.bLength = sizeof(usb_desc_format_type),
.bDescriptorType = AUDIO_DESCTYPE_INTERFACE
},
.bDescriptorSubtype = AUDIO_STREAMING_FORMAT_TYPE,
.bFormatType = AUDIO_FORMAT_TYPE_III,
.bNrChannels = 0x02U,
.bSubFrameSize = 0x02U,
.bBitResolution = 0x10U,
.bSamFreqType = 0x01U,
.bSamFreq[0] = (uint8_t)USBD_AUDIO_FREQ_16K,
.bSamFreq[1] = USBD_AUDIO_FREQ_16K >> 8,
.bSamFreq[2] = USBD_AUDIO_FREQ_16K >> 16
},
.std_endpoint =
{
.header =
{
.bLength = sizeof(usb_desc_std_ep),
.bDescriptorType = USB_DESCTYPE_EP
},
.bEndpointAddress = AUDIO_OUT_EP,
.bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS,
.wMaxPacketSize = PACKET_SIZE(USBD_AUDIO_FREQ_16K),
.bInterval = 0x01U,
.bRefresh = 0x00U,
.bSynchAddress = 0x00U
},
.as_endpoint =
{
.header =
{
.bLength = sizeof(usb_desc_AS_ep),
.bDescriptorType = AUDIO_DESCTYPE_ENDPOINT
},
.bDescriptorSubtype = AUDIO_ENDPOINT_GENERAL,
.bmAttributes = 0x00U,
.bLockDelayUnits = 0x00U,
.wLockDelay = 0x0000U,
}
};
/* USB language ID descriptor */
static usb_desc_LANGID usbd_language_id_desc =
{
.header =
{
.bLength = sizeof(usb_desc_LANGID),
.bDescriptorType = USB_DESCTYPE_STR
},
.wLANGID = ENG_LANGID
};
/* USB manufacture string */
static usb_desc_str manufacturer_string =
{
.header =
{
.bLength = USB_STRING_LEN(10U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'}
};
/* USB product string */
static usb_desc_str product_string =
{
.header =
{
.bLength = USB_STRING_LEN(14U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'A', 'u', 'd', 'i', 'o'}
};
/* USBD serial string */
static usb_desc_str serial_string =
{
.header =
{
.bLength = USB_STRING_LEN(12U),
.bDescriptorType = USB_DESCTYPE_STR,
}
};
/* USB string descriptor */
static uint8_t* usbd_audio_strings[] =
{
[STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc,
[STR_IDX_MFC] = (uint8_t *)&manufacturer_string,
[STR_IDX_PRODUCT] = (uint8_t *)&product_string,
[STR_IDX_SERIAL] = (uint8_t *)&serial_string
};
usb_desc audio_desc = {
.dev_desc = (uint8_t *)&audio_dev_desc,
.config_desc = (uint8_t *)&audio_config_set,
.strings = usbd_audio_strings
};
/*!
\brief initialize the audio device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t audio_init (usb_dev *udev, uint8_t config_index)
{
usb_desc_std_ep std_ep = audio_config_set.std_endpoint;
static usbd_audio_handler audio_handler;
memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler));
usb_desc_ep ep = {
.header = std_ep.header,
.bEndpointAddress = std_ep.bEndpointAddress,
.bmAttributes = std_ep.bmAttributes,
.wMaxPacketSize = std_ep.wMaxPacketSize,
.bInterval = std_ep.bInterval
};
/* initialize RX endpoint */
usbd_ep_init(udev, EP_BUF_DBL, AUDIO_BUF_ADDR, &ep);
usbd_int_fops = &usb_inthandler;
audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff;
audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff;
/* initialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_init(USBD_AUDIO_FREQ_16K, DEFAULT_VOLUME, 0U)) {
return USBD_FAIL;
}
udev->ep_transc[AUDIO_OUT_EP][TRANSC_OUT] = audio_class.data_out;
/* prepare out endpoint to receive audio data */
usbd_ep_recev (udev, AUDIO_OUT_EP, (uint8_t*)audio_handler.isoc_out_buff, (uint16_t)AUDIO_OUT_PACKET);
udev->class_data[USBD_AUDIO_INTERFACE] = (void *)&audio_handler;
return USBD_OK;
}
/*!
\brief de-initialize the audio device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t audio_deinit (usb_dev *udev, uint8_t config_index)
{
/* deinitialize audio endpoints */
usbd_ep_deinit(udev, AUDIO_OUT_EP);
/* deinitialize the audio output hardware layer */
if (USBD_OK != audio_out_fops.audio_deinit(0U)) {
return USBD_FAIL;
}
return USBD_OK;
}
/*!
\brief handle the audio class-specific requests
\param[in] udev: pointer to USB device instance
\param[in] req: device class-specific request
\param[out] none
\retval USB device operation status
*/
static uint8_t audio_req_handler (usb_dev *udev, usb_req *req)
{
uint8_t status = REQ_NOTSUPP;
usbd_audio_handler *audio = (usbd_audio_handler *)udev->class_data[USBD_AUDIO_INTERFACE];
switch (req->bRequest) {
case AUDIO_REQ_GET_CUR:
usb_transc_config(&udev->transc_in[0], audio->audioctl, req->wLength, 0U);
status = REQ_SUPP;
break;
case AUDIO_REQ_SET_CUR:
if (req->wLength) {
usb_transc_config(&udev->transc_out[0], audio->audioctl, req->wLength, 0U);
udev->class_core->req_cmd = AUDIO_REQ_SET_CUR;
audio->audioctl_len = req->wLength;
audio->audioctl_unit = BYTE_HIGH(req->wIndex);
status = REQ_SUPP;
}
break;
default:
break;
}
return status;
}
/*!
\brief handles the audio out data stage
\param[in] udev: pointer to USB device instance
\param[in] ep_num: endpoint number
\param[out] none
\retval USB device operation status
*/
static void audio_data_out (usb_dev *udev, uint8_t ep_num)
{
usbd_audio_handler *audio = (usbd_audio_handler *)udev->class_data[USBD_AUDIO_INTERFACE];
if (AUDIO_OUT_EP == ep_num) {
/* increment the Buffer pointer or roll it back when all buffers are full */
if (audio->isoc_out_wrptr >= (audio->isoc_out_buff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) {
/* all buffers are full: roll back */
audio->isoc_out_wrptr = audio->isoc_out_buff;
} else {
/* increment the buffer pointer */
audio->isoc_out_wrptr += AUDIO_OUT_PACKET;
}
/* prepare out endpoint to receive next audio packet */
usbd_ep_recev (udev, AUDIO_OUT_EP, (uint8_t*)(audio->isoc_out_wrptr), (uint16_t)AUDIO_OUT_PACKET);
/* trigger the start of streaming only when half buffer is full */
if ((0U == audio->play_flag) && (audio->isoc_out_wrptr >= (audio->isoc_out_buff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2U)))) {
/* enable start of streaming */
audio->play_flag = 1U;
}
}
}
/*!
\brief handles audio control request data
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
static uint8_t audio_ctlx_out (usb_dev *udev)
{
usbd_audio_handler *audio = (usbd_audio_handler *)udev->class_data[USBD_AUDIO_INTERFACE];
/* check if an audio_control request has been issued */
if (AUDIO_REQ_SET_CUR == udev->class_core->req_cmd) {
/* in this driver, to simplify code, only SET_CUR request is managed */
/* check for which addressed unit the audio_control request has been issued */
if (AUDIO_OUT_STREAMING_CTRL == audio->audioctl_unit) {
/* in this driver, to simplify code, only one unit is manage */
/* call the audio interface mute function */
audio_out_fops.audio_mute_ctl(audio->audioctl[0]);
/* reset the audioctl_cmd variable to prevent re-entering this function */
udev->class_core->req_cmd = 0U;
audio->audioctl_len = 0U;
}
}
return USBD_OK;
}
/*!
\brief handles the SOF event (data buffer update and synchronization)
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
static uint8_t usbd_audio_sof (usb_dev *udev)
{
usbd_audio_handler *audio = (usbd_audio_handler *)udev->class_data[USBD_AUDIO_INTERFACE];
/* check if there are available data in stream buffer.
in this function, a single variable (play_flag) is used to avoid software delays.
the play operation must be executed as soon as possible after the SOF detection. */
if (audio->play_flag) {
/* start playing received packet */
audio_out_fops.audio_cmd((uint8_t*)(audio->isoc_out_rdptr), /* samples buffer pointer */
AUDIO_OUT_PACKET, /* number of samples in Bytes */
AUDIO_CMD_PLAY); /* command to be processed */
/* increment the Buffer pointer or roll it back when all buffers all full */
if (audio->isoc_out_rdptr >= (audio->isoc_out_buff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) {
/* roll back to the start of buffer */
audio->isoc_out_rdptr = audio->isoc_out_buff;
} else {
/* increment to the next sub-buffer */
audio->isoc_out_rdptr += AUDIO_OUT_PACKET;
}
/* if all available buffers have been consumed, stop playing */
if (audio->isoc_out_rdptr == audio->isoc_out_wrptr) {
/* pause the audio stream */
audio_out_fops.audio_cmd((uint8_t*)(audio->isoc_out_buff), /* samples buffer pointer */
AUDIO_OUT_PACKET, /* number of samples in Bytes */
AUDIO_CMD_PAUSE); /* command to be processed */
/* stop entering play loop */
audio->play_flag = 0U;
/* reset buffer pointers */
audio->isoc_out_rdptr = audio->isoc_out_buff;
audio->isoc_out_wrptr = audio->isoc_out_buff;
}
}
return USBD_OK;
}

243
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/audio/Source/audio_out_itf.c Normal file
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/*!
\file audio_out_itf.c
\brief audio OUT (playback) interface functions
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "audio_core.h"
#include "audio_out_itf.h"
#include "audio_codec.h"
static uint8_t init (uint32_t audio_freq, uint32_t volume, uint32_t options);
static uint8_t deinit (uint32_t options);
static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd);
static uint8_t volume_ctl (uint8_t vol);
static uint8_t mute_ctl (uint8_t cmd);
static uint8_t periodic_tc (uint8_t cmd);
static uint8_t get_state (void);
audio_fops_struct audio_out_fops =
{
init,
deinit,
audio_cmd,
volume_ctl,
mute_ctl,
periodic_tc,
get_state
};
static uint8_t audio_state = AUDIO_STATE_INACTIVE;
/*!
\brief initialize and configures all required resources for audio play function
\param[in] audio_freq: statrt_up audio frequency
\param[in] volume: start_up volume to be set
\param[in] options: specific options passed to low layer function
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t init (uint32_t audio_freq, uint32_t volume, uint32_t options)
{
static uint32_t initialized = 0U;
/* check if the low layer has already been initialized */
if (0U == initialized) {
/* call low layer function */
if (0U != eval_audio_init(OUTPUT_DEVICE_AUTO, volume, audio_freq)) {
audio_state = AUDIO_STATE_ERROR;
return AUDIO_FAIL;
}
/* set the initialization flag to prevent reinitializing the interface again */
initialized = 1U;
}
/* update the audio state machine */
audio_state = AUDIO_STATE_ACTIVE;
return AUDIO_OK;
}
/*!
\brief free all resources used by low layer and stops audio-play function
\param[in] options: specific options passed to low layer function
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t deinit (uint32_t options)
{
/* update the audio state machine */
audio_state = AUDIO_STATE_INACTIVE;
return AUDIO_OK;
}
/*!
\brief play, stop, pause or resume current file
\param[in] pbuf: address from which file should be played
\param[in] size: size of the current buffer/file
\param[in] cmd: command to be executed, can be:
\arg AUDIO_CMD_PLAY
\arg AUDIO_CMD_PAUSE
\arg AUDIO_CMD_RESUME
\arg AUDIO_CMD_STOP
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t audio_cmd (uint8_t* pbuf, uint32_t size, uint8_t cmd)
{
uint8_t status = AUDIO_OK;
/* check the current state */
if ((AUDIO_STATE_INACTIVE == audio_state) || (AUDIO_STATE_ERROR == audio_state)) {
audio_state = AUDIO_STATE_ERROR;
return AUDIO_FAIL;
}
switch (cmd) {
/* process the play command */
case AUDIO_CMD_PLAY:
/* if current state is active or stopped */
if ((AUDIO_STATE_ACTIVE == audio_state) || \
(AUDIO_STATE_STOPPED == audio_state) || \
(AUDIO_STATE_PLAYING == audio_state)) {
audio_mal_play((uint32_t)pbuf, (size / 2U));
audio_state = AUDIO_STATE_PLAYING;
} else if (AUDIO_STATE_PAUSED == audio_state) {
if (eval_audio_pause_resume(AUDIO_RESUME, (uint32_t)pbuf, (size / 2U))) {
audio_state = AUDIO_STATE_ERROR;
status = AUDIO_FAIL;
} else {
audio_state = AUDIO_STATE_PLAYING;
}
} else {
status = AUDIO_FAIL;
}
break;
/* process the stop command */
case AUDIO_CMD_STOP:
if (AUDIO_STATE_PLAYING != audio_state) {
/* unsupported command */
status = AUDIO_FAIL;
} else if (eval_audio_stop(CODEC_PDWN_SW)) {
audio_state = AUDIO_STATE_ERROR;
status = AUDIO_FAIL;
} else {
audio_state = AUDIO_STATE_STOPPED;
}
break;
/* process the pause command */
case AUDIO_CMD_PAUSE:
if (AUDIO_STATE_PLAYING != audio_state) {
/* unsupported command */
status = AUDIO_FAIL;
} else if (eval_audio_pause_resume(AUDIO_PAUSE, (uint32_t)pbuf, (size / 2U))) {
audio_state = AUDIO_STATE_ERROR;
status = AUDIO_FAIL;
} else {
audio_state = AUDIO_STATE_PAUSED;
}
break;
/* unsupported command */
default:
break;
}
return status;
}
/*!
\brief set the volume level
\param[in] vol: volume level to be set in % (from 0% to 100%)
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t volume_ctl (uint8_t vol)
{
/* call low layer volume setting function */
if (eval_audio_volume_ctl(vol)) {
audio_state = AUDIO_STATE_ERROR;
return AUDIO_FAIL;
}
return AUDIO_OK;
}
/*!
\brief mute or unmute the audio current output
\param[in] cmd: can be 0 to unmute, or 1 to mute
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t mute_ctl (uint8_t cmd)
{
/* call low layer mute setting function */
if (eval_audio_mute((uint32_t)cmd)) {
audio_state = AUDIO_STATE_ERROR;
return AUDIO_FAIL;
}
return AUDIO_OK;
}
/*!
\brief periodic transfer control
\param[in] cmd: command
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t periodic_tc (uint8_t cmd)
{
return AUDIO_OK;
}
/*!
\brief return the current state of the audio machine
\param[in] none
\param[out] none
\retval AUDIO_OK if all operations succeed, otherwise, AUDIO_FAIL.
*/
static uint8_t get_state (void)
{
return audio_state;
}

164
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/cdc/Include/cdc_acm_core.h Normal file
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/*!
\file cdc_acm_core.h
\brief the header file of CDC ACM driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __CDC_ACM_CORE_H
#define __CDC_ACM_CORE_H
#include "usbd_enum.h"
/* communications device class code */
#define USB_CLASS_CDC 0x02U
/* CDC subclass code */
#define USB_CDC_SUBCLASS_DLCM 0x01U
#define USB_CDC_SUBCLASS_ACM 0x02U
/* communications interface class control protocol codes */
#define USB_CDC_PROTOCOL_NONE 0x00U
#define USB_CDC_PROTOCOL_AT 0x01U
/* data interface class code */
#define USB_CLASS_DATA 0x0AU
#define USB_DESCTYPE_CDC_ACM 0x21U
#define USB_DESCTYPE_CS_INTERFACE 0x24U
#define USB_CDC_ACM_CONFIG_DESC_SIZE 0x43U
/* class-specific notification codes for PSTN subclasses */
#define USB_CDC_NOTIFY_SERIAL_STATE 0x20U
/* class-specific request codes */
#define SEND_ENCAPSULATED_COMMAND 0x00U
#define GET_ENCAPSULATED_RESPONSE 0x01U
#define SET_COMM_FEATURE 0x02U
#define GET_COMM_FEATURE 0x03U
#define CLEAR_COMM_FEATURE 0x04U
#define SET_LINE_CODING 0x20U
#define GET_LINE_CODING 0x21U
#define SET_CONTROL_LINE_STATE 0x22U
#define SEND_BREAK 0x23U
#define NO_CMD 0xFFU
#pragma pack(1)
/* CDC ACM line coding structure */
typedef struct {
uint32_t dwDTERate; /*!< data terminal rate */
uint8_t bCharFormat; /*!< stop bits */
uint8_t bParityType; /*!< parity */
uint8_t bDataBits; /*!< data bits */
} acm_line;
/* notification structure */
typedef struct {
uint8_t bmRequestType; /*!< type of request */
uint8_t bNotification; /*!< communication interface class notifications */
uint16_t wValue; /*!< value of notification */
uint16_t wIndex; /*!< index of interface */
uint16_t wLength; /*!< length of notification data */
} acm_notification;
/* header function structure */
typedef struct {
usb_desc_header header; /*!< descriptor header, including type and size. */
uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: header function descriptor */
uint16_t bcdCDC; /*!< bcdCDC: low byte of spec release number (CDC1.10) */
} usb_desc_header_func;
/* call management function structure */
typedef struct {
usb_desc_header header; /*!< descriptor header, including type and size. */
uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: call management function descriptor */
uint8_t bmCapabilities; /*!< bmCapabilities: D0 is reset, D1 is ignored */
uint8_t bDataInterface; /*!< bDataInterface: 1 interface used for call management */
} usb_desc_call_managment_func;
/* ACM function structure */
typedef struct {
usb_desc_header header; /*!< descriptor header, including type and size. */
uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: abstract control management descriptor */
uint8_t bmCapabilities; /*!< bmCapabilities: D1 */
} usb_desc_acm_func;
/* union function structure */
typedef struct {
usb_desc_header header; /*!< descriptor header, including type and size. */
uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: union function descriptor */
uint8_t bMasterInterface; /*!< bMasterInterface: communication class interface */
uint8_t bSlaveInterface0; /*!< bSlaveInterface0: data class interface */
} usb_desc_union_func;
#pragma pack()
/* configuration descriptor structure */
typedef struct {
usb_desc_config config;
usb_desc_itf cmd_itf;
usb_desc_header_func cdc_header;
usb_desc_call_managment_func cdc_call_managment;
usb_desc_acm_func cdc_acm;
usb_desc_union_func cdc_union;
usb_desc_ep cdc_cmd_endpoint;
usb_desc_itf cdc_data_interface;
usb_desc_ep cdc_out_endpoint;
usb_desc_ep cdc_in_endpoint;
} usb_cdc_desc_config_set;
#define USB_CDC_RX_LEN 64U
typedef struct {
uint8_t pre_packet_send;
uint8_t packet_sent;
uint8_t packet_receive;
uint8_t data[USB_CDC_RX_LEN];
uint32_t receive_length;
acm_line line_coding;
} usb_cdc_handler;
extern usb_desc cdc_desc;
extern usb_class cdc_class;
/* function declarations */
/* receive CDC ACM data */
void cdc_acm_data_receive(usb_dev *udev);
/* send CDC ACM data */
void cdc_acm_data_send(usb_dev *udev);
/* check CDC ACM is ready for data transfer */
uint8_t cdc_acm_check_ready(usb_dev *udev);
#endif /* __CDC_ACM_CORE_H */

510
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/cdc/Source/cdc_acm_core.c Normal file
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/*!
\file cdc_acm_core.c
\brief CDC ACM driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "usbd_transc.h"
#include "cdc_acm_core.h"
#define USBD_VID 0x28E9U
#define USBD_PID 0x018AU
/* note:it should use the C99 standard when compiling the below codes */
/* USB standard device descriptor */
usb_desc_dev cdc_dev_desc =
{
.header =
{
.bLength = USB_DEV_DESC_LEN,
.bDescriptorType = USB_DESCTYPE_DEV,
},
.bcdUSB = 0x0200U,
.bDeviceClass = USB_CLASS_CDC,
.bDeviceSubClass = 0x00U,
.bDeviceProtocol = 0x00U,
.bMaxPacketSize0 = USBD_EP0_MAX_SIZE,
.idVendor = USBD_VID,
.idProduct = USBD_PID,
.bcdDevice = 0x0100U,
.iManufacturer = STR_IDX_MFC,
.iProduct = STR_IDX_PRODUCT,
.iSerialNumber = STR_IDX_SERIAL,
.bNumberConfigurations = USBD_CFG_MAX_NUM,
};
/* USB device configuration descriptor */
usb_cdc_desc_config_set cdc_config_desc =
{
.config =
{
.header =
{
.bLength = sizeof(usb_desc_config),
.bDescriptorType = USB_DESCTYPE_CONFIG,
},
.wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE,
.bNumInterfaces = 0x02U,
.bConfigurationValue = 0x01U,
.iConfiguration = 0x00U,
.bmAttributes = 0x80U,
.bMaxPower = 0x32U
},
.cmd_itf =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x00U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x01U,
.bInterfaceClass = USB_CLASS_CDC,
.bInterfaceSubClass = USB_CDC_SUBCLASS_ACM,
.bInterfaceProtocol = USB_CDC_PROTOCOL_AT,
.iInterface = 0x00U
},
.cdc_header =
{
.header =
{
.bLength = sizeof(usb_desc_header_func),
.bDescriptorType = USB_DESCTYPE_CS_INTERFACE
},
.bDescriptorSubtype = 0x00U,
.bcdCDC = 0x0110U
},
.cdc_call_managment =
{
.header =
{
.bLength = sizeof(usb_desc_call_managment_func),
.bDescriptorType = USB_DESCTYPE_CS_INTERFACE
},
.bDescriptorSubtype = 0x01U,
.bmCapabilities = 0x00U,
.bDataInterface = 0x01U
},
.cdc_acm =
{
.header =
{
.bLength = sizeof(usb_desc_acm_func),
.bDescriptorType = USB_DESCTYPE_CS_INTERFACE
},
.bDescriptorSubtype = 0x02U,
.bmCapabilities = 0x02U,
},
.cdc_union =
{
.header =
{
.bLength = sizeof(usb_desc_union_func),
.bDescriptorType = USB_DESCTYPE_CS_INTERFACE
},
.bDescriptorSubtype = 0x06U,
.bMasterInterface = 0x00U,
.bSlaveInterface0 = 0x01U,
},
.cdc_cmd_endpoint =
{
.header =
{
.bLength = sizeof(usb_desc_ep),
.bDescriptorType = USB_DESCTYPE_EP,
},
.bEndpointAddress = CDC_CMD_EP,
.bmAttributes = USB_EP_ATTR_INT,
.wMaxPacketSize = CDC_ACM_CMD_PACKET_SIZE,
.bInterval = 0x0AU
},
.cdc_data_interface =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF,
},
.bInterfaceNumber = 0x01U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x02U,
.bInterfaceClass = USB_CLASS_DATA,
.bInterfaceSubClass = 0x00U,
.bInterfaceProtocol = USB_CDC_PROTOCOL_NONE,
.iInterface = 0x00U
},
.cdc_out_endpoint =
{
.header =
{
.bLength = sizeof(usb_desc_ep),
.bDescriptorType = USB_DESCTYPE_EP,
},
.bEndpointAddress = CDC_OUT_EP,
.bmAttributes = USB_EP_ATTR_BULK,
.wMaxPacketSize = CDC_ACM_DATA_PACKET_SIZE,
.bInterval = 0x00U
},
.cdc_in_endpoint =
{
.header =
{
.bLength = sizeof(usb_desc_ep),
.bDescriptorType = USB_DESCTYPE_EP
},
.bEndpointAddress = CDC_IN_EP,
.bmAttributes = USB_EP_ATTR_BULK,
.wMaxPacketSize = CDC_ACM_DATA_PACKET_SIZE,
.bInterval = 0x00U
}
};
/* USB language ID descriptor */
static usb_desc_LANGID usbd_language_id_desc =
{
.header =
{
.bLength = sizeof(usb_desc_LANGID),
.bDescriptorType = USB_DESCTYPE_STR,
},
.wLANGID = ENG_LANGID
};
/* USB manufacture string */
static usb_desc_str manufacturer_string =
{
.header =
{
.bLength = USB_STRING_LEN(10U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'}
};
/* USB product string */
static usb_desc_str product_string =
{
.header =
{
.bLength = USB_STRING_LEN(12U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'D', '3', '2', '-', 'C', 'D', 'C', '_', 'A', 'C', 'M'}
};
/* USBD serial string */
static usb_desc_str serial_string =
{
.header =
{
.bLength = USB_STRING_LEN(12U),
.bDescriptorType = USB_DESCTYPE_STR,
}
};
/* USB string descriptor set */
uint8_t* usbd_cdc_strings[] =
{
[STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc,
[STR_IDX_MFC] = (uint8_t *)&manufacturer_string,
[STR_IDX_PRODUCT] = (uint8_t *)&product_string,
[STR_IDX_SERIAL] = (uint8_t *)&serial_string
};
usb_desc cdc_desc = {
.dev_desc = (uint8_t *)&cdc_dev_desc,
.config_desc = (uint8_t *)&cdc_config_desc,
.strings = usbd_cdc_strings
};
/* local function prototypes ('static') */
static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index);
static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index);
static uint8_t cdc_acm_req_handler (usb_dev *udev, usb_req *req);
static uint8_t cdc_acm_ctlx_out (usb_dev *udev);
static void cdc_acm_data_in (usb_dev *udev, uint8_t ep_num);
static void cdc_acm_data_out (usb_dev *udev, uint8_t ep_num);
usb_class cdc_class = {
.req_cmd = NO_CMD,
.init = cdc_acm_init,
.deinit = cdc_acm_deinit,
.req_process = cdc_acm_req_handler,
.ctlx_out = cdc_acm_ctlx_out,
.data_in = cdc_acm_data_in,
.data_out = cdc_acm_data_out
};
/*!
\brief receive CDC ACM data
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
void cdc_acm_data_receive(usb_dev *udev)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
cdc->packet_receive = 0U;
cdc->pre_packet_send = 0U;
usbd_ep_recev(udev, CDC_OUT_EP, (uint8_t*)(cdc->data), USB_CDC_RX_LEN);
}
/*!
\brief send CDC ACM data
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
void cdc_acm_data_send (usb_dev *udev)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
uint32_t data_len = cdc->receive_length;
if ((0U != data_len) && (1U == cdc->packet_sent)) {
cdc->packet_sent = 0U;
usbd_ep_send(udev, CDC_IN_EP, (uint8_t*)(cdc->data), (uint16_t)data_len);
cdc->receive_length = 0U;
}
}
/*!
\brief check CDC ACM is ready for data transfer
\param[in] udev: pointer to USB device instance
\param[out] none
\retval 0 if CDC is ready, 5 otherwise
*/
uint8_t cdc_acm_check_ready(usb_dev *udev)
{
if (udev->class_data[CDC_COM_INTERFACE] != NULL) {
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
if ((1U == cdc->packet_receive) && (1U == cdc->pre_packet_send)) {
return 0U;
}
}
return 5U;
}
/*!
\brief initialize the CDC ACM device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t cdc_acm_init (usb_dev *udev, uint8_t config_index)
{
static usb_cdc_handler cdc_handler;
/* initialize the data endpoints */
usbd_ep_init(udev, EP_BUF_SNG, BULK_TX_ADDR, &(cdc_config_desc.cdc_in_endpoint));
usbd_ep_init(udev, EP_BUF_SNG, BULK_RX_ADDR, &(cdc_config_desc.cdc_out_endpoint));
/* initialize the command endpoint */
usbd_ep_init(udev, EP_BUF_SNG, INT_TX_ADDR, &(cdc_config_desc.cdc_cmd_endpoint));
udev->ep_transc[EP_ID(CDC_IN_EP)][TRANSC_IN] = cdc_class.data_in;
udev->ep_transc[CDC_OUT_EP][TRANSC_OUT] = cdc_class.data_out;
/* initialize CDC handler structure */
cdc_handler.packet_receive = 0U;
cdc_handler.packet_sent = 1U;
cdc_handler.pre_packet_send = 1U;
cdc_handler.receive_length = 0U;
cdc_handler.line_coding = (acm_line){
.dwDTERate = 115200U,
.bCharFormat = 0U,
.bParityType = 0U,
.bDataBits = 0x08U
};
udev->class_data[CDC_COM_INTERFACE] = (void *)&cdc_handler;
return USBD_OK;
}
/*!
\brief de-initialize the CDC ACM device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t cdc_acm_deinit (usb_dev *udev, uint8_t config_index)
{
/* deinitialize the data endpoints */
usbd_ep_deinit(udev, CDC_IN_EP);
usbd_ep_deinit(udev, CDC_OUT_EP);
/* deinitialize the command endpoint */
usbd_ep_deinit(udev, CDC_CMD_EP);
return USBD_OK;
}
/*!
\brief command data received on control endpoint
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
static uint8_t cdc_acm_ctlx_out (usb_dev *udev)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
if (NO_CMD != udev->class_core->req_cmd) {
cdc->packet_receive = 1U;
cdc->pre_packet_send = 1U;
udev->class_core->req_cmd = NO_CMD;
}
return USBD_OK;
}
/*!
\brief handle CDC ACM data in transaction
\param[in] udev: pointer to USB device instance
\param[in] ep_num: endpoint number
\param[out] none
\retval USB device operation status
*/
static void cdc_acm_data_in (usb_dev *udev, uint8_t ep_num)
{
usb_transc *transc = &udev->transc_in[ep_num];
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
if (transc->xfer_count == transc->max_len) {
usbd_ep_send(udev, EP_ID(ep_num), NULL, 0U);
} else {
cdc->packet_sent = 1U;
cdc->pre_packet_send = 1U;
}
}
/*!
\brief handle CDC ACM data out transaction
\param[in] udev: pointer to USB device instance
\param[in] ep_num: endpoint number
\param[out] none
\retval USB device operation status
*/
static void cdc_acm_data_out (usb_dev *udev, uint8_t ep_num)
{
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
cdc->packet_receive = 1U;
cdc->receive_length = udev->transc_out[ep_num].xfer_count;
}
/*!
\brief handle the CDC ACM class-specific requests
\param[in] udev: pointer to USB device instance
\param[in] req: device class-specific request
\param[out] none
\retval USB device operation status
*/
static uint8_t cdc_acm_req_handler (usb_dev *udev, usb_req *req)
{
uint8_t status = REQ_NOTSUPP, noti_buf[10] = {0U};
usb_cdc_handler *cdc = (usb_cdc_handler *)udev->class_data[CDC_COM_INTERFACE];
acm_notification *notif = (void *)noti_buf;
switch (req->bRequest) {
case SEND_ENCAPSULATED_COMMAND:
break;
case GET_ENCAPSULATED_RESPONSE:
break;
case SET_COMM_FEATURE:
break;
case GET_COMM_FEATURE:
break;
case CLEAR_COMM_FEATURE:
break;
case SET_LINE_CODING:
/* set the value of the current command to be processed */
udev->class_core->req_cmd = req->bRequest;
usb_transc_config(&udev->transc_out[0U], (uint8_t *)&cdc->line_coding, req->wLength, 0U);
status = REQ_SUPP;
break;
case GET_LINE_CODING:
usb_transc_config(&udev->transc_in[0U], (uint8_t *)&cdc->line_coding, 7U, 0U);
status = REQ_SUPP;
break;
case SET_CONTROL_LINE_STATE:
notif->bmRequestType = 0xA1U;
notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE;
notif->wIndex = 0U;
notif->wValue = 0U;
notif->wLength = 2U;
noti_buf[8] = (uint8_t)req->wValue & 3U;
noti_buf[9] = 0U;
status = REQ_SUPP;
break;
case SEND_BREAK:
break;
default:
break;
}
return status;
}

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/dfu/Include/dfu_core.h Normal file
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/*!
\file dfu_core.h
\brief the header file of USB DFU device class core functions
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __DFU_CORE_H
#define __DFU_CORE_H
#include "usbd_enum.h"
/* DFU class code */
#define USB_DFU_CLASS 0xFEU
/* DFU subclass code */
#define USB_DFU_SUBCLASS_UPGRADE 0x01U
/* DFU protocol code */
#define USB_DFU_PROTOCL_RUNTIME 0x01U
#define USB_DFU_PROTOCL_DFU 0x02U
/* manifestation state */
#define MANIFEST_COMPLETE 0x00U
#define MANIFEST_IN_PROGRESS 0x01U
/* DFU attributes code */
#define USB_DFU_CAN_DOWNLOAD 0x01U
#define USB_DFU_CAN_UPLOAD 0x02U
#define USB_DFU_MANIFEST_TOLERANT 0x04U
#define USB_DFU_WILL_DETACH 0x08U
/* special commands with download request */
#define GET_COMMANDS 0x00U
#define SET_ADDRESS_POINTER 0x21U
#define ERASE 0x41U
/* memory operation command */
#define CMD_ERASE 0U
#define CMD_WRITE 1U
#define _BYTE1(x) (uint8_t)((x) & 0xFFU) /*!< addressing cycle 1st byte */
#define _BYTE2(x) (uint8_t)(((x) & 0xFF00U) >> 8U) /*!< addressing cycle 2nd byte */
#define _BYTE3(x) (uint8_t)(((x) & 0xFF0000U) >> 16U) /*!< addressing cycle 3rd byte */
#define SET_POLLING_TIMEOUT(x) do { \
dfu->bwPollTimeout0 = _BYTE1(x);\
dfu->bwPollTimeout1 = _BYTE2(x);\
dfu->bwPollTimeout2 = _BYTE3(x);\
} while(0)
#define FLASH_ERASE_TIMEOUT 60U
#define FLASH_WRITE_TIMEOUT 80U
/* bit detach capable = bit 3 in bmAttributes field */
#define DFU_DETACH_MASK (uint8_t)(0x10U)
#define USB_DFU_CONFIG_DESC_SIZE (18U + (9U * USBD_ITF_MAX_NUM))
#define DFU_DESC_TYPE 0x21U
/* DFU device state enumeration */
typedef enum {
STATE_APP_IDLE = 0x00U,
STATE_APP_DETACH,
STATE_DFU_IDLE,
STATE_DFU_DNLOAD_SYNC,
STATE_DFU_DNBUSY,
STATE_DFU_DNLOAD_IDLE,
STATE_DFU_MANIFEST_SYNC,
STATE_DFU_MANIFEST,
STATE_DFU_MANIFEST_WAIT_RESET,
STATE_DFU_UPLOAD_IDLE,
STATE_DFU_ERROR
} dfu_state;
/* DFU device status enumeration */
typedef enum {
STATUS_OK = 0x00U,
STATUS_ERR_TARGET,
STATUS_ERR_FILE,
STATUS_ERR_WRITE,
STATUS_ERR_ERASE,
STATUS_ERR_CHECK_ERASED,
STATUS_ERR_PROG,
STATUS_ERR_VERIFY,
STATUS_ERR_ADDRESS,
STATUS_ERR_NOTDONE,
STATUS_ERR_FIRMWARE,
STATUS_ERR_VENDOR,
STATUS_ERR_USBR,
STATUS_ERR_POR,
STATUS_ERR_UNKNOWN,
STATUS_ERR_STALLEDPKT
} dfu_status;
/* DFU class-specific requests enumeration */
typedef enum {
DFU_DETACH = 0U,
DFU_DNLOAD,
DFU_UPLOAD,
DFU_GETSTATUS,
DFU_CLRSTATUS,
DFU_GETSTATE,
DFU_ABORT,
DFU_REQ_MAX
} dfu_requests;
#pragma pack(1)
/* USB DFU function descriptor structure */
typedef struct
{
usb_desc_header header; /*!< descriptor header, including type and size */
uint8_t bmAttributes; /*!< DFU attributes */
uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */
uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */
uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU specification release. */
} usb_desc_dfu_func;
#pragma pack()
/* USB configuration descriptor structure */
typedef struct
{
usb_desc_config config;
usb_desc_itf dfu_itf;
usb_desc_dfu_func dfu_func;
} usb_dfu_desc_config_set;
/* USB DFU handler structure */
typedef struct
{
uint8_t bStatus;
uint8_t bwPollTimeout0;
uint8_t bwPollTimeout1;
uint8_t bwPollTimeout2;
uint8_t bState;
uint8_t iString;
uint8_t manifest_state;
uint16_t data_len;
uint16_t block_num;
uint32_t base_addr;
uint8_t buf[TRANSFER_SIZE];
} usbd_dfu_handler;
typedef void (*app_func) (void);
extern usb_desc dfu_desc;
extern usb_class dfu_class;
#endif /* __DFU_CORE_H */

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platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/dfu/Source/dfu_core.c Normal file
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/*!
\file dfu_core.c
\brief USB DFU device class core functions
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "dfu_core.h"
#include "systick.h"
#include <string.h>
#define USBD_VID 0x28E9U
#define USBD_PID 0x0189U
/* local function prototypes ('static') */
static uint8_t dfu_init (usb_dev *udev, uint8_t config_index);
static uint8_t dfu_deinit (usb_dev *udev, uint8_t config_index);
static uint8_t dfu_req_handler (usb_dev *udev, usb_req *req);
static uint8_t dfu_ctlx_in (usb_dev *udev);
/* DFU requests management functions */
static void dfu_detach (usb_dev *udev, usb_req *req);
static void dfu_dnload (usb_dev *udev, usb_req *req);
static void dfu_upload (usb_dev *udev, usb_req *req);
static void dfu_getstatus (usb_dev *udev, usb_req *req);
static void dfu_clrstatus (usb_dev *udev, usb_req *req);
static void dfu_getstate (usb_dev *udev, usb_req *req);
static void dfu_abort (usb_dev *udev, usb_req *req);
static void dfu_mode_leave (usb_dev *udev);
static uint8_t dfu_getstatus_complete (usb_dev *udev);
static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) =
{
[DFU_DETACH] = dfu_detach,
[DFU_DNLOAD] = dfu_dnload,
[DFU_UPLOAD] = dfu_upload,
[DFU_GETSTATUS] = dfu_getstatus,
[DFU_CLRSTATUS] = dfu_clrstatus,
[DFU_GETSTATE] = dfu_getstate,
[DFU_ABORT] = dfu_abort
};
/* note:it should use the c99 standard when compiling the below codes */
/* USB standard device descriptor */
usb_desc_dev dfu_dev_desc =
{
.header =
{
.bLength = USB_DEV_DESC_LEN,
.bDescriptorType = USB_DESCTYPE_DEV
},
.bcdUSB = 0x0200U,
.bDeviceClass = 0x00U,
.bDeviceSubClass = 0x00U,
.bDeviceProtocol = 0x00U,
.bMaxPacketSize0 = USBD_EP0_MAX_SIZE,
.idVendor = USBD_VID,
.idProduct = USBD_PID,
.bcdDevice = 0x0100U,
.iManufacturer = STR_IDX_MFC,
.iProduct = STR_IDX_PRODUCT,
.iSerialNumber = STR_IDX_SERIAL,
.bNumberConfigurations = USBD_CFG_MAX_NUM
};
/* USB device configuration descriptor */
usb_dfu_desc_config_set dfu_config_desc =
{
.config =
{
.header =
{
.bLength = sizeof(usb_desc_config),
.bDescriptorType = USB_DESCTYPE_CONFIG
},
.wTotalLength = USB_DFU_CONFIG_DESC_SIZE,
.bNumInterfaces = 0x01U,
.bConfigurationValue = 0x01U,
.iConfiguration = 0x00U,
.bmAttributes = 0x80U,
.bMaxPower = 0x32U
},
.dfu_itf =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x00U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x00U,
.bInterfaceClass = USB_DFU_CLASS,
.bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE,
.bInterfaceProtocol = USB_DFU_PROTOCL_DFU,
.iInterface = 0x00U
},
.dfu_func =
{
.header =
{
.bLength = sizeof(usb_desc_dfu_func),
.bDescriptorType = DFU_DESC_TYPE
},
.bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_CAN_UPLOAD | USB_DFU_WILL_DETACH,
.wDetachTimeOut = 0x00FFU,
.wTransferSize = TRANSFER_SIZE,
.bcdDFUVersion = 0x011AU,
},
};
/* USB language ID descriptor */
static usb_desc_LANGID usbd_language_id_desc =
{
.header = {
.bLength = sizeof(usb_desc_LANGID),
.bDescriptorType = USB_DESCTYPE_STR
},
.wLANGID = ENG_LANGID
};
/* USB manufacture string */
static usb_desc_str manufacturer_string =
{
.header =
{
.bLength = USB_STRING_LEN(10U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'}
};
/* USB product string */
static usb_desc_str product_string =
{
.header =
{
.bLength = USB_STRING_LEN(12U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'D', 'F', 'U'}
};
/* USB serial string */
static usb_desc_str serial_string =
{
.header =
{
.bLength = USB_STRING_LEN(2U),
.bDescriptorType = USB_DESCTYPE_STR,
}
};
/* USB configure string */
static usb_desc_str config_string =
{
.header =
{
.bLength = USB_STRING_LEN(15U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'D', '3', '2', ' ', 'U', 'S', 'B', ' ', 'C', 'O', 'N', 'F', 'I', 'G'}
};
/* USB interface string */
static usb_desc_str interface_string =
{
.header =
{
.bLength = USB_STRING_LEN(15U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'@', 'I', 'n', 't', 'e', 'r', 'n', 'a', 'l', 'F', 'l', 'a', 's', 'h', ' ', '/', '0', 'x', '0', '8', '0', '0',
'0', '0', '0', '0', '/', '1', '6', '*', '0', '0', '1', 'K', 'a', ',', '4', '8', '*', '0', '0', '1', 'K', 'g'}
};
uint8_t* usbd_dfu_strings[] =
{
[STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc,
[STR_IDX_MFC] = (uint8_t *)&manufacturer_string,
[STR_IDX_PRODUCT] = (uint8_t *)&product_string,
[STR_IDX_SERIAL] = (uint8_t *)&serial_string,
[STR_IDX_CONFIG] = (uint8_t *)&config_string,
[STR_IDX_ITF] = (uint8_t *)&interface_string
};
usb_desc dfu_desc = {
.dev_desc = (uint8_t *)&dfu_dev_desc,
.config_desc = (uint8_t *)&dfu_config_desc,
.strings = usbd_dfu_strings
};
usb_class dfu_class = {
.init = dfu_init,
.deinit = dfu_deinit,
.req_process = dfu_req_handler,
.ctlx_in = dfu_ctlx_in
};
/*!
\brief initialize the USB DFU device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t dfu_init (usb_dev *udev, uint8_t config_index)
{
static usbd_dfu_handler dfu_handler;
/* unlock the internal flash */
fmc_unlock();
systick_config();
memset((void *)&dfu_handler, 0, sizeof(usbd_dfu_handler));
dfu_handler.base_addr = APP_LOADED_ADDR;
dfu_handler.manifest_state = MANIFEST_COMPLETE;
dfu_handler.bState = STATE_DFU_IDLE;
dfu_handler.bStatus = STATUS_OK;
udev->class_data[USBD_DFU_INTERFACE] = (void *)&dfu_handler;
return USBD_OK;
}
/*!
\brief de-initialize the USB DFU device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t dfu_deinit (usb_dev *udev, uint8_t config_index)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
/* restore device default state */
memset(udev->class_data[USBD_DFU_INTERFACE], 0, sizeof(usbd_dfu_handler));
dfu->bState = STATE_DFU_IDLE;
dfu->bStatus = STATUS_OK;
/* lock the internal flash */
fmc_lock();
return USBD_OK;
}
/*!
\brief handle the USB DFU class-specific requests
\param[in] udev: pointer to USB device instance
\param[in] req: device class-specific request
\param[out] none
\retval USB device operation status
*/
static uint8_t dfu_req_handler (usb_dev *udev, usb_req *req)
{
if (req->bRequest < DFU_REQ_MAX) {
dfu_request_process[req->bRequest](udev, req);
} else {
return USBD_FAIL;
}
return USBD_OK;
}
/*!
\brief handle data stage
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
static uint8_t dfu_ctlx_in (usb_dev *udev)
{
dfu_getstatus_complete(udev);
return USBD_OK;
}
/*!
\brief handle data in stage in control endpoint 0
\param[in] udev: pointer to USB device instance
\param[out] none
\retval USB device operation status
*/
static uint8_t dfu_getstatus_complete (usb_dev *udev)
{
uint32_t addr;
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
if (STATE_DFU_DNBUSY == dfu->bState) {
/* decode the special command */
if (0U == dfu->block_num) {
if (1U == dfu->data_len){
if (GET_COMMANDS == dfu->buf[0]) {
/* no operation */
}
} else if (5U == dfu->data_len) {
if (SET_ADDRESS_POINTER == dfu->buf[0]) {
/* set flash operation address */
dfu->base_addr = *(uint32_t *)(dfu->buf + 1U);
} else if (ERASE == dfu->buf[0]) {
dfu->base_addr = *(uint32_t *)(dfu->buf + 1U);
fmc_page_erase(dfu->base_addr);
} else {
/* no operation */
}
} else {
/* no operation */
}
} else if (dfu->block_num > 1U) { /* regular download command */
/* preform the write operation */
uint32_t idx = 0U;
/* decode the required address */
addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr;
if (dfu->data_len & 0x03U) { /* not an aligned data */
for (idx = dfu->data_len; idx < ((dfu->data_len & 0xFFFCU) + 4U); idx++) {
dfu->buf[idx] = 0xFFU;
}
}
/* data received are word multiple */
for (idx = 0U; idx < dfu->data_len; idx += 4U) {
fmc_word_program(addr, *(uint32_t *)(dfu->buf + idx));
addr += 4U;
}
dfu->block_num = 0U;
} else {
/* no operation */
}
dfu->data_len = 0U;
/* update the device state and poll timeout */
dfu->bState = STATE_DFU_DNLOAD_SYNC;
return USBD_OK;
} else if (STATE_DFU_MANIFEST == dfu->bState) { /* manifestation in progress */
/* start leaving DFU mode */
dfu_mode_leave(udev);
} else {
/* no operation */
}
return USBD_OK;
}
/*!
\brief handle the DFU_DETACH request
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none.
*/
static void dfu_detach(usb_dev *udev, usb_req *req)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
switch (dfu->bState) {
case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_SYNC:
case STATE_DFU_DNLOAD_IDLE:
case STATE_DFU_MANIFEST_SYNC:
case STATE_DFU_UPLOAD_IDLE:
dfu->bStatus = STATUS_OK;
dfu->bState = STATE_DFU_IDLE;
dfu->iString = 0U; /* iString */
dfu->block_num = 0U;
dfu->data_len = 0U;
break;
default:
break;
}
/* check the detach capability in the DFU functional descriptor */
if (dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK) {
usbd_disconnect(udev);
usbd_connect(udev);
} else {
/* wait for the period of time specified in detach request */
delay_1ms(4U);
}
}
/*!
\brief handle the DFU_DNLOAD request
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none
*/
static void dfu_dnload(usb_dev *udev, usb_req *req)
{
usb_transc *transc = &udev->transc_out[0];
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
switch (dfu->bState) {
case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_IDLE:
if (req->wLength > 0U) {
/* update the global length and block number */
dfu->block_num = req->wValue;
dfu->data_len = req->wLength;
dfu->bState = STATE_DFU_DNLOAD_SYNC;
transc->xfer_len = dfu->data_len;
transc->xfer_buf = dfu->buf;
transc->xfer_count = 0U;
} else {
dfu->manifest_state = MANIFEST_IN_PROGRESS;
dfu->bState = STATE_DFU_MANIFEST_SYNC;
}
break;
default:
break;
}
}
/*!
\brief handles the DFU UPLOAD request.
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none
*/
static void dfu_upload (usb_dev *udev, usb_req *req)
{
uint8_t *phy_addr = NULL;
uint32_t addr = 0U;
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
if(req->wLength <= 0U) {
dfu->bState = STATE_DFU_IDLE;
return;
}
usb_transc *transc = &udev->transc_in[0];
switch (dfu->bState) {
case STATE_DFU_IDLE:
case STATE_DFU_UPLOAD_IDLE:
/* update the global length and block number */
dfu->block_num = req->wValue;
dfu->data_len = req->wLength;
/* DFU get command */
if (0U == dfu->block_num) {
/* update the state machine */
dfu->bState = (dfu->data_len > 3U) ? STATE_DFU_IDLE : STATE_DFU_UPLOAD_IDLE;
/* store the values of all supported commands */
dfu->buf[0] = GET_COMMANDS;
dfu->buf[1] = SET_ADDRESS_POINTER;
dfu->buf[2] = ERASE;
/* send the status data over EP0 */
transc->xfer_buf = &(dfu->buf[0]);
transc->xfer_len = 3U;
} else if (dfu->block_num > 1U) {
dfu->bState = STATE_DFU_UPLOAD_IDLE;
/* change is accelerated */
addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr;
/* return the physical address where data are stored */
phy_addr = (uint8_t *)(addr);
/* send the status data over EP0 */
transc->xfer_buf = phy_addr;
transc->xfer_len = dfu->data_len;
} else {
dfu->bState = STATUS_ERR_STALLEDPKT;
}
break;
default:
dfu->data_len = 0U;
dfu->block_num = 0U;
break;
}
}
/*!
\brief handle the DFU_GETSTATUS request
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none
*/
static void dfu_getstatus (usb_dev *udev, usb_req *req)
{
usb_transc *transc = &udev->transc_in[0];
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
switch (dfu->bState) {
case STATE_DFU_DNLOAD_SYNC:
if (0U != dfu->data_len) {
dfu->bState = STATE_DFU_DNBUSY;
if (0U == dfu->block_num) {
if (ERASE == dfu->buf[0]) {
SET_POLLING_TIMEOUT(FLASH_ERASE_TIMEOUT);
} else {
SET_POLLING_TIMEOUT(FLASH_WRITE_TIMEOUT);
}
}
} else {
dfu->bState = STATE_DFU_DNLOAD_IDLE;
}
break;
case STATE_DFU_MANIFEST_SYNC:
if (MANIFEST_IN_PROGRESS == dfu->manifest_state) {
dfu->bState = STATE_DFU_MANIFEST;
dfu->bwPollTimeout0 = 1U;
} else if ((MANIFEST_COMPLETE == dfu->manifest_state) && \
(dfu_config_desc.dfu_func.bmAttributes & 0x04U)){
dfu->bState = STATE_DFU_IDLE;
dfu->bwPollTimeout0 = 0U;
} else {
/* no operation */
}
break;
default:
break;
}
/* send the status data of DFU interface to host over EP0 */
transc->xfer_buf = (uint8_t *)&(dfu->bStatus);
transc->xfer_len = 6U;
}
/*!
\brief handle the DFU_CLRSTATUS request
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none
*/
static void dfu_clrstatus (usb_dev *udev, usb_req *req)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
if (STATE_DFU_ERROR == dfu->bState) {
dfu->bStatus = STATUS_OK;
dfu->bState = STATE_DFU_IDLE;
} else {
/* state error */
dfu->bStatus = STATUS_ERR_UNKNOWN;
dfu->bState = STATE_DFU_ERROR;
}
dfu->iString = 0U; /* iString: index = 0 */
}
/*!
\brief handle the DFU_GETSTATE request
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none
*/
static void dfu_getstate (usb_dev *udev, usb_req *req)
{
usb_transc *transc = &udev->transc_in[0];
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
/* send the current state of the DFU interface to host */
transc->xfer_buf = &(dfu->bState);
transc->xfer_len = 1U;
}
/*!
\brief handle the DFU_ABORT request
\param[in] udev: pointer to USB device instance
\param[in] req: DFU class request
\param[out] none
\retval none
*/
static void dfu_abort (usb_dev *udev, usb_req *req)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
switch (dfu->bState){
case STATE_DFU_IDLE:
case STATE_DFU_DNLOAD_SYNC:
case STATE_DFU_DNLOAD_IDLE:
case STATE_DFU_MANIFEST_SYNC:
case STATE_DFU_UPLOAD_IDLE:
dfu->bStatus = STATUS_OK;
dfu->bState = STATE_DFU_IDLE;
dfu->iString = 0U; /* iString: index = 0 */
dfu->block_num = 0U;
dfu->data_len = 0U;
break;
default:
break;
}
}
/*!
\brief leave DFU mode and reset device to jump to user loaded code
\param[in] udev: pointer to USB device instance
\param[out] none
\retval none
*/
static void dfu_mode_leave (usb_dev *udev)
{
usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->class_data[USBD_DFU_INTERFACE];
dfu->manifest_state = MANIFEST_COMPLETE;
if (dfu_config_desc.dfu_func.bmAttributes & 0x04U) {
dfu->bState = STATE_DFU_MANIFEST_SYNC;
} else {
dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET;
/* lock the internal flash */
fmc_lock();
/* generate system reset to allow jumping to the user code */
NVIC_SystemReset();
}
}

68
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/hid/Include/custom_hid_core.h Normal file
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/*!
\file custom_hid_core.h
\brief definitions for HID core
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __CUSTOM_HID_CORE_H
#define __CUSTOM_HID_CORE_H
#include "usbd_enum.h"
#include "usb_hid.h"
#define DESC_LEN_REPORT 96U
#define DESC_LEN_CONFIG 41U
#define MAX_PERIPH_NUM 4U
typedef struct {
uint8_t data[2];
uint8_t reportID;
uint8_t idlestate;
uint8_t protocol;
} custom_hid_handler;
typedef struct {
void (*periph_config[MAX_PERIPH_NUM])(void);
} hid_fop_handler;
extern usb_desc custom_hid_desc;
extern usb_class custom_hid_class;
/* function declarations */
/* register HID interface operation functions */
uint8_t custom_hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop);
/* send custom HID report */
uint8_t custom_hid_report_send (usb_dev *udev, uint8_t *report, uint16_t len);
#endif /* __CUSTOM_HID_CORE_H */

67
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/hid/Include/standard_hid_core.h Normal file
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/*!
\file standard_hid_core.h
\brief definitions for HID core
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __STANDARD_HID_CORE_H
#define __STANDARD_HID_CORE_H
#include "usbd_enum.h"
#include "usb_hid.h"
#define USB_HID_CONFIG_DESC_LEN 0x22U
#define USB_HID_REPORT_DESC_LEN 0x29U
typedef struct {
uint32_t protocol;
uint32_t idle_state;
uint8_t data[HID_IN_PACKET];
__IO uint8_t prev_transfer_complete;
} standard_hid_handler;
typedef struct {
void (*hid_itf_config) (void);
void (*hid_itf_data_process) (usb_dev *udev);
} hid_fop_handler;
extern usb_desc hid_desc;
extern usb_class hid_class;
/* function declarations */
/* register HID interface operation functions */
uint8_t hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop);
/* send HID report */
uint8_t hid_report_send (usb_dev *udev, uint8_t *report, uint16_t len);
#endif /* __STANDARD_HID_CORE_H */

84
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/*!
\file usb_hid.h
\brief definitions for the USB HID class
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef __USB_HID_H
#define __USB_HID_H
#include "usb_ch9_std.h"
#define USB_HID_CLASS 0x03U
#define USB_DESCTYPE_HID 0x21U
#define USB_DESCTYPE_REPORT 0x22U
/* HID subclass code */
#define USB_HID_SUBCLASS_BOOT_ITF 0x01U
/* HID protocol codes */
#define USB_HID_PROTOCOL_KEYBOARD 0x01U
#define USB_HID_PROTOCOL_MOUSE 0x02U
#define GET_REPORT 0x01U
#define GET_IDLE 0x02U
#define GET_PROTOCOL 0x03U
#define SET_REPORT 0x09U
#define SET_IDLE 0x0AU
#define SET_PROTOCOL 0x0BU
#pragma pack(1)
typedef struct
{
usb_desc_header header; /*!< regular descriptor header containing the descriptor's type and length */
uint16_t bcdHID; /*!< BCD encoded version that the HID descriptor and device complies to */
uint8_t bCountryCode; /*!< country code of the localized device, or zero if universal */
uint8_t bNumDescriptors; /*!< total number of HID report descriptors for the interface */
uint8_t bDescriptorType; /*!< type of HID report */
uint16_t wDescriptorLength; /*!< length of the associated HID report descriptor, in bytes */
} usb_desc_hid;
#pragma pack()
typedef struct
{
usb_desc_config config;
usb_desc_itf hid_itf;
usb_desc_hid hid_vendor;
usb_desc_ep hid_epin;
usb_desc_ep hid_epout;
} usb_hid_desc_config_set;
#endif /* __USB_HID_H */

505
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/hid/Source/custom_hid_core.c Normal file
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/*!
\file custom_hid_core.c
\brief custom HID class driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "usbd_transc.h"
#include "custom_hid_core.h"
#include <string.h>
#define USBD_VID 0x28E9U
#define USBD_PID 0x128AU
/* Note:it should use the C99 standard when compiling the below codes */
/* USB standard device descriptor */
usb_desc_dev custom_hid_dev_desc =
{
.header =
{
.bLength = USB_DEV_DESC_LEN,
.bDescriptorType = USB_DESCTYPE_DEV,
},
.bcdUSB = 0x0200U,
.bDeviceClass = 0x00U,
.bDeviceSubClass = 0x00U,
.bDeviceProtocol = 0x00U,
.bMaxPacketSize0 = USBD_EP0_MAX_SIZE,
.idVendor = USBD_VID,
.idProduct = USBD_PID,
.bcdDevice = 0x0100U,
.iManufacturer = STR_IDX_MFC,
.iProduct = STR_IDX_PRODUCT,
.iSerialNumber = STR_IDX_SERIAL,
.bNumberConfigurations = USBD_CFG_MAX_NUM,
};
/* USB device configure descriptor */
usb_hid_desc_config_set custom_hid_config_desc =
{
.config =
{
.header =
{
.bLength = sizeof(usb_desc_config),
.bDescriptorType = USB_DESCTYPE_CONFIG
},
.wTotalLength = DESC_LEN_CONFIG,
.bNumInterfaces = 0x01U,
.bConfigurationValue = 0x01U,
.iConfiguration = 0x00U,
.bmAttributes = 0x80U,
.bMaxPower = 0x32U
},
.hid_itf =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x00U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x02U,
.bInterfaceClass = USB_HID_CLASS,
.bInterfaceSubClass = 0x00U,
.bInterfaceProtocol = 0x00U,
.iInterface = 0x00U
},
.hid_vendor =
{
.header =
{
.bLength = sizeof(usb_desc_hid),
.bDescriptorType = USB_DESCTYPE_HID
},
.bcdHID = 0x0111U,
.bCountryCode = 0x00U,
.bNumDescriptors = 0x01U,
.bDescriptorType = USB_DESCTYPE_REPORT,
.wDescriptorLength = DESC_LEN_REPORT,
},
.hid_epin =
{
.header =
{
.bLength = sizeof(usb_desc_ep),
.bDescriptorType = USB_DESCTYPE_EP
},
.bEndpointAddress = CUSTOMHID_IN_EP,
.bmAttributes = USB_EP_ATTR_INT,
.wMaxPacketSize = CUSTOMHID_IN_PACKET,
.bInterval = 0x20U
},
.hid_epout =
{
.header =
{
.bLength = sizeof(usb_desc_ep),
.bDescriptorType = USB_DESCTYPE_EP
},
.bEndpointAddress = CUSTOMHID_OUT_EP,
.bmAttributes = USB_EP_ATTR_INT,
.wMaxPacketSize = CUSTOMHID_OUT_PACKET,
.bInterval = 0x20U
}
};
/* USB language ID descriptor */
static usb_desc_LANGID usbd_language_id_desc =
{
.header =
{
.bLength = sizeof(usb_desc_LANGID),
.bDescriptorType = USB_DESCTYPE_STR
},
.wLANGID = ENG_LANGID
};
/* USB manufacture string */
static usb_desc_str manufacturer_string =
{
.header =
{
.bLength = USB_STRING_LEN(10U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'}
};
/* USB product string */
static usb_desc_str product_string =
{
.header =
{
.bLength = USB_STRING_LEN(14U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'D', '3', '2', '-', 'C', 'u', 's', 't', 'o', 'm', 'H', 'I', 'D'}
};
/* USB serial string */
static usb_desc_str serial_string =
{
.header =
{
.bLength = USB_STRING_LEN(12U),
.bDescriptorType = USB_DESCTYPE_STR,
}
};
/* USB string descriptor set */
static uint8_t* usbd_hid_strings[] =
{
[STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc,
[STR_IDX_MFC] = (uint8_t *)&manufacturer_string,
[STR_IDX_PRODUCT] = (uint8_t *)&product_string,
[STR_IDX_SERIAL] = (uint8_t *)&serial_string
};
usb_desc custom_hid_desc = {
.dev_desc = (uint8_t *)&custom_hid_dev_desc,
.config_desc = (uint8_t *)&custom_hid_config_desc,
.strings = usbd_hid_strings
};
/* local function prototypes ('static') */
static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index);
static uint8_t custom_hid_deinit (usb_dev *udev, uint8_t config_index);
static uint8_t custom_hid_req_handler (usb_dev *udev, usb_req *req);
static void custom_hid_data_in (usb_dev *udev, uint8_t ep_num);
static void custom_hid_data_out (usb_dev *udev, uint8_t ep_num);
usb_class custom_hid_class = {
.req_cmd = 0xFFU,
.init = custom_hid_init,
.deinit = custom_hid_deinit,
.req_process = custom_hid_req_handler,
.data_in = custom_hid_data_in,
.data_out = custom_hid_data_out
};
const uint8_t customhid_report_descriptor[DESC_LEN_REPORT] =
{
0x06, 0x00, 0xFF, /* USAGE_PAGE (Vendor Defined: 0xFF00) */
0x09, 0x00, /* USAGE (Custom Device) */
0xa1, 0x01, /* COLLECTION (Application) */
/* led 1 */
0x85, 0x11, /* REPORT_ID (0x11) */
0x09, 0x01, /* USAGE (LED 1) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x01, /* REPORT_COUNT (1) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* led 2 */
0x85, 0x12, /* REPORT_ID (0x12) */
0x09, 0x02, /* USAGE (LED 2) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x01, /* REPORT_COUNT (1) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* led 3 */
0x85, 0x13, /* REPORT_ID (0x13) */
0x09, 0x03, /* USAGE (LED 3) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x01, /* REPORT_COUNT (1) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* led 4 */
0x85, 0x14, /* REPORT_ID (0x14) */
0x09, 0x04, /* USAGE (LED 4) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x95, 0x01, /* REPORT_COUNT (1) */
0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
/* wakeup key */
0x85, 0x15, /* REPORT_ID (0x15) */
0x09, 0x05, /* USAGE (Push Button) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x01, /* REPORT_SIZE (1) */
0x81, 0x02, /* INPUT (Data,Var,Abs,Vol) */
0x75, 0x07, /* REPORT_SIZE (7) */
0x81, 0x03, /* INPUT (Cnst,Var,Abs,Vol) */
/* tamper key */
0x85, 0x16, /* REPORT_ID (0x16) */
0x09, 0x06, /* USAGE (Push Button) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x75, 0x01, /* REPORT_SIZE (1) */
0x81, 0x02, /* INPUT (Data,Var,Abs,Vol) */
0x75, 0x07, /* REPORT_SIZE (7) */
0x81, 0x03, /* INPUT (Cnst,Var,Abs,Vol) */
0xc0 /* END_COLLECTION */
};
/*!
\brief register HID interface operation functions
\param[in] udev: pointer to USB device instance
\param[in] hid_fop: HID operation functions structure
\param[out] none
\retval USB device operation status
*/
uint8_t custom_hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop)
{
if (NULL != hid_fop) {
udev->user_data = hid_fop;
return USBD_OK;
}
return USBD_FAIL;
}
/*!
\brief send custom HID report
\param[in] udev: pointer to USB device instance
\param[in] report: pointer to HID report
\param[in] len: data length
\param[out] none
\retval USB device operation status
*/
uint8_t custom_hid_report_send (usb_dev *udev, uint8_t *report, uint16_t len)
{
usbd_ep_send (udev, CUSTOMHID_IN_EP, report, len);
return USBD_OK;
}
/*!
\brief initialize the HID device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t custom_hid_init (usb_dev *udev, uint8_t config_index)
{
static custom_hid_handler hid_handler;
memset((void *)&hid_handler, 0, sizeof(custom_hid_handler));
/* initialize the data endpoints */
usbd_ep_init(udev, EP_BUF_SNG, HID_TX_ADDR, &(custom_hid_config_desc.hid_epin));
usbd_ep_init(udev, EP_BUF_SNG, HID_RX_ADDR, &(custom_hid_config_desc.hid_epout));
usbd_ep_recev (udev, CUSTOMHID_OUT_EP, hid_handler.data, 2U);
udev->ep_transc[EP_ID(CUSTOMHID_IN_EP)][TRANSC_IN] = custom_hid_class.data_in;
udev->ep_transc[EP_ID(CUSTOMHID_OUT_EP)][TRANSC_OUT] = custom_hid_class.data_out;
udev->class_data[CUSTOM_HID_INTERFACE] = (void *)&hid_handler;
if (udev->user_data != NULL) {
for (uint8_t i = 0U; i < MAX_PERIPH_NUM; i++) {
if (((hid_fop_handler *)udev->user_data)->periph_config[i] != NULL) {
((hid_fop_handler *)udev->user_data)->periph_config[i]();
}
}
}
return USBD_OK;
}
/*!
\brief de-initialize the HID device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t custom_hid_deinit (usb_dev *udev, uint8_t config_index)
{
/* deinitialize HID endpoints */
usbd_ep_deinit(udev, CUSTOMHID_IN_EP);
usbd_ep_deinit(udev, CUSTOMHID_OUT_EP);
return USBD_OK;
}
/*!
\brief handle the HID class-specific requests
\param[in] udev: pointer to USB device instance
\param[in] req: device class-specific request
\param[out] none
\retval USB device operation status
*/
static uint8_t custom_hid_req_handler (usb_dev *udev, usb_req *req)
{
uint8_t status = REQ_NOTSUPP;
custom_hid_handler *hid = (custom_hid_handler *)udev->class_data[CUSTOM_HID_INTERFACE];
switch (req->bRequest) {
case USB_GET_DESCRIPTOR:
if (USB_DESCTYPE_REPORT == (req->wValue >> 8)) {
usb_transc_config(&udev->transc_in[0],
(uint8_t *)customhid_report_descriptor,
USB_MIN(DESC_LEN_REPORT, req->wLength),
0U);
status = REQ_SUPP;
}
break;
case GET_REPORT:
if (2U == req->wLength) {
usb_transc_config(&udev->transc_in[0], hid->data, 2U, 0U);
status = REQ_SUPP;
}
break;
case GET_IDLE:
usb_transc_config(&udev->transc_in[0], (uint8_t *)&hid->idlestate, 1U, 0U);
status = REQ_SUPP;
break;
case GET_PROTOCOL:
usb_transc_config(&udev->transc_in[0], (uint8_t *)&hid->protocol, 1U, 0U);
status = REQ_SUPP;
break;
case SET_REPORT:
hid->reportID = (uint8_t)(req->wValue);
usb_transc_config(&udev->transc_out[0], hid->data, req->wLength, 0U);
status = REQ_SUPP;
break;
case SET_IDLE:
hid->idlestate = (uint8_t)(req->wValue >> 8);
status = REQ_SUPP;
break;
case SET_PROTOCOL:
hid->protocol = (uint8_t)(req->wValue);
status = REQ_SUPP;
break;
default:
break;
}
return status;
}
/*!
\brief handle custom HID data in transaction
\param[in] udev: pointer to USB device instance
\param[in] ep_num: endpoint number
\param[out] none
\retval none
*/
static void custom_hid_data_in (usb_dev *udev, uint8_t ep_num)
{
return;
}
/*!
\brief handle custom HID data out transaction
\param[in] udev: pointer to USB device instance
\param[in] ep_num: endpoint number
\param[out] none
\retval none
*/
static void custom_hid_data_out (usb_dev *udev, uint8_t ep_num)
{
custom_hid_handler *hid = (custom_hid_handler *)udev->class_data[CUSTOM_HID_INTERFACE];
if (CUSTOMHID_OUT_EP == ep_num){
switch (hid->data[0]){
case 0x11:
if (RESET != hid->data[1]) {
/* turn on led1 */
gd_eval_led_on(LED1);
} else {
gd_eval_led_off(LED1);
}
break;
case 0x12:
if (RESET != hid->data[1]) {
gd_eval_led_on(LED2);
} else {
gd_eval_led_off(LED2);
}
break;
case 0x13:
if (RESET != hid->data[1]) {
gd_eval_led_on(LED3);
} else {
gd_eval_led_off(LED3);
}
break;
case 0x14:
if (RESET != hid->data[1]) {
gd_eval_led_on(LED4);
} else {
gd_eval_led_off(LED4);
}
break;
default:
/* turn off all LEDs */
gd_eval_led_off(LED1);
gd_eval_led_off(LED2);
gd_eval_led_off(LED3);
gd_eval_led_off(LED4);
break;
}
usbd_ep_recev(udev, CUSTOMHID_IN_EP, hid->data, 2U);
}
}

421
platform/vendor_bsp/gd/GD32E50x_Firmware_Library/GD32E50x_usbd_library/class/device/hid/Source/standard_hid_core.c Normal file
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/*!
\file standard_hid_core.c
\brief HID class driver
\version 2020-03-10, V1.0.0, firmware for GD32E50x
\version 2020-08-26, V1.1.0, firmware for GD32E50x
*/
/*
Copyright (c) 2020, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "usbd_transc.h"
#include "standard_hid_core.h"
#include <string.h>
#define USBD_VID 0x28E9U
#define USBD_PID 0x0380U
/* Note:it should use the C99 standard when compiling the below codes */
/* USB standard device descriptor */
usb_desc_dev hid_dev_desc =
{
.header =
{
.bLength = USB_DEV_DESC_LEN,
.bDescriptorType = USB_DESCTYPE_DEV
},
#ifdef LPM_ENABLED
.bcdUSB = 0x0201U,
#else
.bcdUSB = 0x0200U,
#endif /* LPM_ENABLED */
.bDeviceClass = 0x00U,
.bDeviceSubClass = 0x00U,
.bDeviceProtocol = 0x00U,
.bMaxPacketSize0 = USBD_EP0_MAX_SIZE,
.idVendor = USBD_VID,
.idProduct = USBD_PID,
.bcdDevice = 0x0100U,
.iManufacturer = STR_IDX_MFC,
.iProduct = STR_IDX_PRODUCT,
.iSerialNumber = STR_IDX_SERIAL,
.bNumberConfigurations = USBD_CFG_MAX_NUM
};
#ifdef LPM_ENABLED
/* BOS descriptor */
uint8_t USBD_BOSDesc[USB_BOS_DESC_LEN] =
{
0x05,
USB_DESCTYPE_BOS,
0x0C,
0x00,
0x01, /* 1 device capability descriptor */
/* device capability*/
0x07,
USB_DEVICE_CAPABITY,
0x02,
0x06, /* LPM capability bit set */
0x00,
0x00,
0x00
};
#endif /* LPM_ENABLED */
usb_hid_desc_config_set hid_config_desc =
{
.config =
{
.header =
{
.bLength = sizeof(usb_desc_config),
.bDescriptorType = USB_DESCTYPE_CONFIG
},
.wTotalLength = USB_HID_CONFIG_DESC_LEN,
.bNumInterfaces = 0x01U,
.bConfigurationValue = 0x01U,
.iConfiguration = 0x00U,
.bmAttributes = 0xA0U,
.bMaxPower = 0x32U
},
.hid_itf =
{
.header =
{
.bLength = sizeof(usb_desc_itf),
.bDescriptorType = USB_DESCTYPE_ITF
},
.bInterfaceNumber = 0x00U,
.bAlternateSetting = 0x00U,
.bNumEndpoints = 0x01U,
.bInterfaceClass = USB_HID_CLASS,
.bInterfaceSubClass = USB_HID_SUBCLASS_BOOT_ITF,
.bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD,
.iInterface = 0x00U
},
.hid_vendor =
{
.header =
{
.bLength = sizeof(usb_desc_hid),
.bDescriptorType = USB_DESCTYPE_HID
},
.bcdHID = 0x0111U,
.bCountryCode = 0x00U,
.bNumDescriptors = 0x01U,
.bDescriptorType = USB_DESCTYPE_REPORT,
.wDescriptorLength = USB_HID_REPORT_DESC_LEN,
},
.hid_epin =
{
.header =
{
.bLength = sizeof(usb_desc_ep),
.bDescriptorType = USB_DESCTYPE_EP
},
.bEndpointAddress = HID_IN_EP,
.bmAttributes = USB_EP_ATTR_INT,
.wMaxPacketSize = HID_IN_PACKET,
.bInterval = 0x40U
}
};
/* USB language ID Descriptor */
static usb_desc_LANGID usbd_language_id_desc =
{
.header =
{
.bLength = sizeof(usb_desc_LANGID),
.bDescriptorType = USB_DESCTYPE_STR
},
.wLANGID = ENG_LANGID
};
/* USB manufacture string */
static usb_desc_str manufacturer_string =
{
.header =
{
.bLength = USB_STRING_LEN(10U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'}
};
/* USB product string */
static usb_desc_str product_string =
{
.header =
{
.bLength = USB_STRING_LEN(17U),
.bDescriptorType = USB_DESCTYPE_STR,
},
.unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'}
};
/* USB serial string */
static usb_desc_str serial_string =
{
.header =
{
.bLength = USB_STRING_LEN(12U),
.bDescriptorType = USB_DESCTYPE_STR,
}
};
/* USB string descriptor set */
static uint8_t* usbd_hid_strings[] =
{
[STR_IDX_LANGID] = (uint8_t *)&usbd_language_id_desc,
[STR_IDX_MFC] = (uint8_t *)&manufacturer_string,
[STR_IDX_PRODUCT] = (uint8_t *)&product_string,
[STR_IDX_SERIAL] = (uint8_t *)&serial_string
};
usb_desc hid_desc = {
#ifdef LPM_ENABLED
.bos_desc = (uint8_t *)&USBD_BOSDesc,
#endif /* LPM_ENABLED */
.dev_desc = (uint8_t *)&hid_dev_desc,
.config_desc = (uint8_t *)&hid_config_desc,
.strings = usbd_hid_strings
};
/* local function prototypes ('static') */
static uint8_t hid_init (usb_dev *udev, uint8_t config_index);
static uint8_t hid_deinit (usb_dev *udev, uint8_t config_index);
static uint8_t hid_req_handler (usb_dev *udev, usb_req *req);
static void hid_data_in_handler (usb_dev *udev, uint8_t ep_num);
usb_class hid_class = {
.init = hid_init,
.deinit = hid_deinit,
.req_process = hid_req_handler,
.data_in = hid_data_in_handler
};
const uint8_t hid_report_desc[USB_HID_REPORT_DESC_LEN] =
{
0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */
0x09, 0x06, /* USAGE (Keyboard) */
0xa1, 0x01, /* COLLECTION (Application) */
0x05, 0x07, /* USAGE_PAGE (Keyboard/Keypad) */
0x19, 0xe0, /* USAGE_MINIMUM (Keyboard LeftControl) */
0x29, 0xe7, /* USAGE_MAXIMUM (Keyboard Right GUI) */
0x15, 0x00, /* LOGICAL_MINIMUM (0) */
0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
0x95, 0x08, /* REPORT_COUNT (8) */
0x75, 0x01, /* REPORT_SIZE (1) */
0x81, 0x02, /* INPUT (Data,Var,Abs) */
0x95, 0x01, /* REPORT_COUNT (1) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x81, 0x03, /* INPUT (Cnst,Var,Abs) */
0x95, 0x06, /* REPORT_COUNT (6) */
0x75, 0x08, /* REPORT_SIZE (8) */
0x25, 0xFF, /* LOGICAL_MAXIMUM (255) */
0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */
0x29, 0x65, /* USAGE_MAXIMUM (Keyboard Application) */
0x81, 0x00, /* INPUT (Data,Ary,Abs) */
0xc0 /* END_COLLECTION */
};
/*!
\brief register HID interface operation functions
\param[in] udev: pointer to USB device instance
\param[in] hid_fop: HID operation functions structure
\param[out] none
\retval USB device operation status
*/
uint8_t hid_itfop_register (usb_dev *udev, hid_fop_handler *hid_fop)
{
if (NULL != hid_fop) {
udev->user_data = (void *)hid_fop;
return USBD_OK;
}
return USBD_FAIL;
}
/*!
\brief send HID report
\param[in] udev: pointer to USB device instance
\param[in] report: pointer to HID report
\param[in] len: data length
\param[out] none
\retval USB device operation status
*/
uint8_t hid_report_send (usb_dev *udev, uint8_t *report, uint16_t len)
{
standard_hid_handler *hid = (standard_hid_handler *)udev->class_data[USBD_HID_INTERFACE];
/* check if USB is configured */
hid->prev_transfer_complete = 0U;
usbd_ep_send(udev, HID_IN_EP, report, len);
return USBD_OK;
}
/*!
\brief initialize the HID device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t hid_init (usb_dev *udev, uint8_t config_index)
{
static standard_hid_handler hid_handler;
memset((void *)&hid_handler, 0, sizeof(standard_hid_handler));
/* initialize TX endpoint */
usbd_ep_init(udev, EP_BUF_SNG, INT_TX_ADDR, &(hid_config_desc.hid_epin));
udev->ep_transc[EP_ID(HID_IN_EP)][TRANSC_IN] = hid_class.data_in;
hid_handler.prev_transfer_complete = 1U;
udev->class_data[USBD_HID_INTERFACE] = (void *)&hid_handler;
if (NULL != udev->user_data) {
((hid_fop_handler *)udev->user_data)->hid_itf_config();
}
return USBD_OK;
}
/*!
\brief de-initialize the HID device
\param[in] udev: pointer to USB device instance
\param[in] config_index: configuration index
\param[out] none
\retval USB device operation status
*/
static uint8_t hid_deinit (usb_dev *udev, uint8_t config_index)
{
/* deinitialize HID endpoints */
usbd_ep_deinit (udev, HID_IN_EP);
return USBD_OK;
}
/*!
\brief handle the HID class-specific requests
\param[in] udev: pointer to USB device instance
\param[in] req: device class-specific request
\param[out] none
\retval USB device operation status
*/
static uint8_t hid_req_handler (usb_dev *udev, usb_req *req)
{
uint8_t status = REQ_NOTSUPP;
standard_hid_handler *hid = (standard_hid_handler *)udev->class_data[USBD_HID_INTERFACE];
switch (req->bRequest) {
case GET_REPORT:
/* no use for this driver */
break;
case GET_IDLE:
usb_transc_config(&udev->transc_in[0U], (uint8_t *)&hid->idle_state, 1U, 0U);
status = REQ_SUPP;
break;
case GET_PROTOCOL:
usb_transc_config(&udev->transc_in[0U], (uint8_t *)&hid->protocol, 1U, 0U);
status = REQ_SUPP;
break;
case SET_REPORT:
/* no use for this driver */
break;
case SET_IDLE:
hid->idle_state = (uint8_t)(req->wValue >> 8);
status = REQ_SUPP;
break;
case SET_PROTOCOL:
hid->protocol = (uint8_t)(req->wValue);
status = REQ_SUPP;
break;
case USB_GET_DESCRIPTOR:
if (USB_DESCTYPE_REPORT == (req->wValue >> 8)) {
usb_transc_config(&udev->transc_in[0U],
(uint8_t *)hid_report_desc,
USB_MIN(USB_HID_REPORT_DESC_LEN, req->wLength),
0U);
status = REQ_SUPP;
}
break;
default:
break;
}
return status;
}
/*!
\brief handle data stage in DATA IN transaction
\param[in] udev: pointer to USB device instance
\param[in] ep_num: endpoint identifier
\param[out] none
\retval none
*/
static void hid_data_in_handler (usb_dev *udev, uint8_t ep_num)
{
standard_hid_handler *hid = (standard_hid_handler *)udev->class_data[USBD_HID_INTERFACE];
if (hid->data[2]) {
hid->data[2] = 0x00U;
usbd_ep_send(udev, HID_IN_EP, hid->data, HID_IN_PACKET);
} else {
hid->prev_transfer_complete = 1U;
}
}

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