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add new board RA6M4

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supowang
2021-04-13 11:07:44 +08:00
parent 4468eb8514
commit 8bc0b76112
108 changed files with 191808 additions and 0 deletions
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board/Renesas_ra6m4/20210401_ra6m4_tencent.uvprojx Normal file
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9
board/Renesas_ra6m4/EventRecorderStub.scvd Normal file
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@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="utf-8"?>
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<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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</events>
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13029
board/Renesas_ra6m4/JLinkLog.txt Normal file
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40
board/Renesas_ra6m4/JLinkSettings.ini Normal file
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

36
board/Renesas_ra6m4/R7FA6M4AF3CFB.pincfg Normal file
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<?xml version="1.0" encoding="utf-8"?>
<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
<v1:pinMappingsRef version="2.05" file="" />
<v1:deviceSetting id="renesas.ra6m4_fb" pattern="R7FA6M4****FB">
<v1:packageSetting id="renesas.144lqfp" />
</v1:deviceSetting>
<v1:configSetting configurationId="debug0.mode" altId="debug0.mode.jtag" />
<v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p108" altId="p108.debug0.tms">
<v1:connectionSetting altId="debug0.tms.p108" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tms" altId="debug0.tms.p108">
<v1:connectionSetting altId="p108.debug0.tms" />
</v1:configSetting>
<v1:configSetting configurationId="p109.gpio_mode" altId="p109.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p109" altId="p109.debug0.tdo">
<v1:connectionSetting altId="debug0.tdo.p109" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tdo" altId="debug0.tdo.p109">
<v1:connectionSetting altId="p109.debug0.tdo" />
</v1:configSetting>
<v1:configSetting configurationId="p110.gpio_mode" altId="p110.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p110" altId="p110.debug0.tdi">
<v1:connectionSetting altId="debug0.tdi.p110" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tdi" altId="debug0.tdi.p110">
<v1:connectionSetting altId="p110.debug0.tdi" />
</v1:configSetting>
<v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
<v1:configSetting configurationId="p300" altId="p300.debug0.tck">
<v1:connectionSetting altId="debug0.tck.p300" />
</v1:configSetting>
<v1:configSetting configurationId="debug0.tck" altId="debug0.tck.p300">
<v1:connectionSetting altId="p300.debug0.tck" />
</v1:configSetting>
</v1:pinSettings>

15
board/Renesas_ra6m4/RTE/_Target_1/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: '20210401_ra6m4_tencent'
* Target: 'Target 1'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */

15
board/Renesas_ra6m4/RTE/_TencentOS_Tiny/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: '20210401_ra6m4_tencent'
* Target: 'TencentOS_Tiny'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#endif /* RTE_COMPONENTS_H */

55
board/Renesas_ra6m4/TOS-CONFIG/tos_config.h Normal file
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#ifndef _TOS_CONFIG_H_
#define _TOS_CONFIG_H_
#include "hal_data.h"
#define TOS_CFG_TASK_PRIO_MAX 10u
#define TOS_CFG_ROUND_ROBIN_EN 0u
#define TOS_CFG_OBJECT_VERIFY_EN 1u
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 1u
#define TOS_CFG_EVENT_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#define TOS_CFG_MMHEAP_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x8000
#define TOS_CFG_MUTEX_EN 1u
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
#define TOS_CFG_MAIL_QUEUE_EN 1u
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u
#define TOS_CFG_TIMER_EN 1u
#define TOS_CFG_PWR_MGR_EN 0u
#define TOS_CFG_TICKLESS_EN 0u
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
#define TOS_CFG_TIMER_AS_PROC 1u
#endif

136
board/Renesas_ra6m4/buildinfo.gpdsc Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="header" name="src/Driver_Common.h" path=""/>
<file category="source" name="src/hal_entry.c"/>
<file category="source" name="src/uart_stdout.c"/>
<file category="header" name="src/uart_stdout.h" path=""/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/SVD/RA.svd"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h" path=""/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>

237
board/Renesas_ra6m4/configuration.xml Normal file
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@@ -0,0 +1,237 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="6">
<generalSettings>
<option key="#Board#" value="board.custom"/>
<option key="CPU" value="RA6M4"/>
<option key="#TargetName#" value="R7FA6M4AF3CFB"/>
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
<option key="#DeviceCommand#" value="R7FA6M4AF"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA6M4AF3CFB.pincfg"/>
<option key="#FSPVersion#" value="2.3.0"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration>
<config id="config.bsp.ra6m4.R7FA6M4AF3CFB">
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
</config>
<config id="config.bsp.ra6m4">
<property id="config.bsp.series" value="config.bsp.series.value"/>
</config>
<config id="config.bsp.ra6m4.fsp">
<property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
<property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
<property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
<property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
<property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
<property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
<property id="config.bsp.fsp.tz.bbfsar" value="config.bsp.fsp.tz.bbfsar.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
<property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
<property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
<property id="config.bsp.fsp.BPS.BPS1" value=""/>
<property id="config.bsp.fsp.BPS.BPS2" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS1" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS2" value=""/>
<property id="config.bsp.fsp.dual_bank" value="config.bsp.fsp.dual_bank.disabled"/>
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="20000000"/>
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
</config>
<config id="config.bsp.ra">
<property id="config.bsp.common.main" value="0x400"/>
<property id="config.bsp.common.heap" value="0"/>
<property id="config.bsp.common.vcc" value="3300"/>
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
</config>
</raBspConfiguration>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.hoco"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.200"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.1"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="2.3.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="2.3.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.7.0+fsp.2.3.0">
<description>Arm CMSIS Version 5 - Core (M)</description>
<originalPack>Arm.CMSIS5.5.7.0+fsp.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="2.3.0">
<description>Custom Board Support Files</description>
<originalPack>Renesas.RA_board_custom.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m4" subgroup="device" variant="R7FA6M4AF3CFB" vendor="Renesas" version="2.3.0">
<description>Board support package for R7FA6M4AF3CFB</description>
<originalPack>Renesas.RA_mcu_ra6m4.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m4" subgroup="device" variant="" vendor="Renesas" version="2.3.0">
<description>Board support package for RA6M4</description>
<originalPack>Renesas.RA_mcu_ra6m4.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra6m4" subgroup="fsp" variant="" vendor="Renesas" version="2.3.0">
<description>Board support package for RA6M4 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra6m4.2.3.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="2.3.0">
<description>SCI UART</description>
<originalPack>Renesas.RA.2.3.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
<raIcuConfiguration/>
<raModuleConfiguration>
<module id="module.driver.ioport_on_ioport.0">
<property id="module.driver.ioport.name" value="g_ioport"/>
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
</module>
<module id="module.driver.uart_on_sci_uart.263105129">
<property id="module.driver.uart.name" value="g_uart0"/>
<property id="module.driver.uart.channel" value="0"/>
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
<property id="module.driver.uart.baud" value="115200"/>
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
<property id="module.driver.uart.baudrate_max_err" value="5"/>
<property id="module.driver.uart.ctsrts_en" value="module.driver.uart.ctsrts_en.false"/>
<property id="module.driver.uart.uart_comm_mode" value="module.driver.uart.uart_comm_mode.uart_rs232_mode"/>
<property id="module.driver.uart.pin_control" value="module.driver.uart.pin_control.false"/>
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
<property id="module.driver.uart.callback" value="user_uart_callback"/>
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.uart_on_sci_uart.263105129"/>
</context>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
<config id="config.driver.sci_uart">
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
</config>
</raModuleConfiguration>
<raPinConfiguration>
<pincfg active="true" name="R7FA6M4AF3CFB.pincfg" selected="true" symbol="g_bsp_pin_cfg">
<configSetting altId="debug0.mode.jtag" configurationId="debug0.mode"/>
<configSetting altId="debug0.tck.p300" configurationId="debug0.tck"/>
<configSetting altId="debug0.tdi.p110" configurationId="debug0.tdi"/>
<configSetting altId="debug0.tdo.p109" configurationId="debug0.tdo"/>
<configSetting altId="debug0.tms.p108" configurationId="debug0.tms"/>
<configSetting altId="p100.sci0.rxd" configurationId="p100"/>
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
<configSetting altId="p101.sci0.txd" configurationId="p101"/>
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
<configSetting altId="p108.debug0.tms" configurationId="p108"/>
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
<configSetting altId="p109.debug0.tdo" configurationId="p109"/>
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
<configSetting altId="p110.debug0.tdi" configurationId="p110"/>
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
<configSetting altId="p300.debug0.tck" configurationId="p300"/>
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
<configSetting altId="sci0.mode.asynchronous.a" configurationId="sci0.mode"/>
<configSetting altId="sci0.pairing.a" configurationId="sci0.pairing"/>
<configSetting altId="sci0.rxd.p100" configurationId="sci0.rxd"/>
<configSetting altId="sci0.txd.p101" configurationId="sci0.txd"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

411
board/Renesas_ra6m4/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h Normal file
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@@ -0,0 +1,411 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.0
* @date 03. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.2.1
* @date 26. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
/* CMSIS compiler control DSP macros */
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __ARM_FEATURE_DSP 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __memory_changed()
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.2.0
* @date 28. January 2020
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.8
* @date 21. August 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.1
* @date 12. November 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.1
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.2
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file pmu_armv8.h
* @brief CMSIS PMU API for Armv8.1-M PMU
* @version V1.0.0
* @date 24. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_PMU_ARMV8_H
#define ARM_PMU_ARMV8_H
/**
* \brief PMU Events
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
* */
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
/** \brief PMU Functions */
__STATIC_INLINE void ARM_PMU_Enable(void);
__STATIC_INLINE void ARM_PMU_Disable(void);
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
/**
\brief Set event to count for PMU eventer counter
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
/**
\brief Enable counters
\param [in] mask Counters to enable
\note Enables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
PMU->CNTENSET = mask;
}
/**
\brief Disable counters
\param [in] mask Counters to enable
\note Disables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
PMU->CNTENCLR = mask;
}
/**
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
return PMU->CCNTR;
}
/**
\brief Read event counter
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
return PMU->EVCNTR[num];
}
/**
\brief Read counter overflow status
\return Counter overflow status bits for the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
return PMU->OVSSET;
}
/**
\brief Clear counter overflow status
\param [in] mask Counter overflow status bits to clear
\note Clears overflow status bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
PMU->OVSCLR = mask;
}
/**
\brief Enable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to set
\note Sets overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
PMU->INTENSET = mask;
}
/**
\brief Disable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to clear
\note Clears overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
PMU->INTENCLR = mask;
}
/**
\brief Software increment event counter
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
PMU->SWINC = mask;
}
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_API_H
#define BSP_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* FSP Common Includes. */
#include "../../inc/fsp_common_api.h"
/* Gets MCU configuration information. */
#include "bsp_cfg.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
* We are not modifying these files so we will ignore these warnings temporarily. */
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wsign-conversion"
#endif
/* Vector information for this project. This is generated by the tooling. */
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic pop
#endif
/* BSP Common Includes. */
#include "../../src/bsp/mcu/all/bsp_common.h"
/* BSP MCU Specific Includes. */
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
#include "../../src/bsp/mcu/all/bsp_irq.h"
#include "../../src/bsp/mcu/all/bsp_io.h"
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
#include "../../src/bsp/mcu/all/bsp_clocks.h"
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
#include "../../src/bsp/mcu/all/bsp_security.h"
/* Factory MCU information. */
#include "../../inc/fsp_features.h"
/* BSP Common Includes (Other than bsp_common.h) */
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
* @brief Interface for accessing I/O ports and configuring I/O functionality.
*
* @section IOPORT_API_SUMMARY Summary
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
* Port and pin direction can be changed.
*
* IOPORT Interface description: @ref IOPORT
*
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_API_H
#define R_IOPORT_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define IOPORT_API_VERSION_MAJOR (1U) // DEPRECATED
#define IOPORT_API_VERSION_MINOR (0U) // DEPRECATED
/* Private definition to set enumeration values. */
#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** IO port type used with ports */
typedef uint16_t ioport_size_t; ///< IO port size on this device
/** Superset of all peripheral functions. */
typedef enum e_ioport_peripheral
{
/** Pin will functions as an IO pin */
IOPORT_PERIPHERAL_IO = 0x00,
/** Pin will function as a DEBUG pin */
IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI peripheral pin */
IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI peripheral pin */
IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a SPI peripheral pin */
IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a IIC peripheral pin */
IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a KEY peripheral pin */
IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a clock/comparator/RTC peripheral pin */
IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAC/ADC peripheral pin */
IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a BUS peripheral pin */
IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CTSU peripheral pin */
IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a segment LCD peripheral pin */
IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a DALI peripheral pin */
IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAN peripheral pin */
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a QSPI peripheral pin */
IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SSI peripheral pin */
IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a USB full speed peripheral pin */
IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a USB high speed peripheral pin */
IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SD/MMC peripheral pin */
IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an Ethernet MMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an Ethernet RMMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PDC peripheral pin */
IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a graphics LCD peripheral pin */
IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a debug trace peripheral pin */
IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a OSPI peripheral pin */
IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Marks end of enum - used by parameter checking */
IOPORT_PERIPHERAL_END
} ioport_peripheral_t;
/** Superset of Ethernet channels. */
typedef enum e_ioport_eth_ch
{
IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1
IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
} ioport_ethernet_channel_t;
/** Superset of Ethernet PHY modes. */
typedef enum e_ioport_eth_mode
{
IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII
IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking
} ioport_ethernet_mode_t;
/** Options to configure pin functions */
typedef enum e_ioport_cfg_options
{
IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default)
IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output
IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low
IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high
IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up
IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode
IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output
IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput
IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium
IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed
IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port
IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high
IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge
IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge
IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges
IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin
IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin
IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin
} ioport_cfg_options_t;
/* PFS writing enable/disable. */
typedef enum e_ioport_pwpr
{
IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access
IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access
} ioport_pwpr_t;
/** Pin identifier and pin PFS pin configuration value */
typedef struct st_ioport_pin_cfg
{
uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure
bsp_io_port_pin_t pin; ///< Pin identifier
} ioport_pin_cfg_t;
/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */
typedef struct st_ioport_cfg
{
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
} ioport_cfg_t;
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
* @par Implemented as
* - ioport_instance_ctrl_t
*/
typedef void ioport_ctrl_t;
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
typedef struct st_ioport_api
{
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
* multiple pins.
* @par Implemented as
* - @ref R_IOPORT_Open()
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Close the API.
* @par Implemented as
* - @ref R_IOPORT_Close()
*
* @param[in] p_ctrl Pointer to control structure.
**/
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
/** Configure multiple pins.
* @par Implemented as
* - @ref R_IOPORT_PinsCfg()
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Configure settings for an individual pin.
* @par Implemented as
* - @ref R_IOPORT_PinCfg()
* @param[in] pin Pin to be read.
* @param[in] cfg Configuration options for the pin.
*/
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
/** Read the event input data of the specified pin and return the level.
* @par Implemented as
* - @ref R_IOPORT_PinEventInputRead()
* @param[in] pin Pin to be read.
* @param[in] p_pin_event Pointer to return the event data.
*/
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
/** Write pin event data.
* @par Implemented as
* - @ref R_IOPORT_PinEventOutputWrite()
* @param[in] pin Pin event data is to be written to.
* @param[in] pin_value Level to be written to pin output event.
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
/** Configure the PHY mode of the Ethernet channels.
* @par Implemented as
* - @ref R_IOPORT_EthernetModeCfg()
* @param[in] channel Channel configuration will be set for.
* @param[in] mode PHY mode to set the channel to.
*/
fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
ioport_ethernet_mode_t mode);
/** Read level of a pin.
* @par Implemented as
* - @ref R_IOPORT_PinRead()
* @param[in] pin Pin to be read.
* @param[in] p_pin_value Pointer to return the pin level.
*/
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
/** Write specified level to a pin.
* @par Implemented as
* - @ref R_IOPORT_PinWrite()
* @param[in] pin Pin to be written to.
* @param[in] level State to be written to the pin.
*/
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
/** Set the direction of one or more pins on a port.
* @par Implemented as
* - @ref R_IOPORT_PortDirectionSet()
* @param[in] port Port being configured.
* @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input).
* @param[in] mask Mask controlling which pins on the port are to be configured.
*/
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
ioport_size_t mask);
/** Read captured event data for a port.
* @par Implemented as
* - @ref R_IOPORT_PortEventInputRead()
* @param[in] port Port to be read.
* @param[in] p_event_data Pointer to return the event data.
*/
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
/** Write event output data for a port.
* @par Implemented as
* - @ref R_IOPORT_PortEventOutputWrite()
* @param[in] port Port event data will be written to.
* @param[in] event_data Data to be written as event data to specified port.
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
* being written to port.
*/
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
ioport_size_t mask_value);
/** Read states of pins on the specified port.
* @par Implemented as
* - @ref R_IOPORT_PortRead()
* @param[in] port Port to be read.
* @param[in] p_port_value Pointer to return the port value.
*/
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
/** Write to multiple pins on a port.
* @par Implemented as
* - @ref R_IOPORT_PortWrite()
* @param[in] port Port to be written to.
* @param[in] value Value to be written to the port.
* @param[in] mask Mask controlling which pins on the port are written to.
*/
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
/* DEPRECATED Return the version of the IOPort driver.
* @par Implemented as
* - @ref R_IOPORT_VersionGet()
* @param[out] p_data Memory address to return version information to.
*/
fsp_err_t (* versionGet)(fsp_version_t * p_data);
} ioport_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_ioport_instance
{
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
} ioport_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup TRANSFER_API Transfer Interface
*
* @brief Interface for data transfer functions.
*
* @section TRANSFER_API_SUMMARY Summary
* The transfer interface supports background data transfer (no CPU intervention).
*
* Implemented by:
* - @ref DTC
* - @ref DMAC
*
* @{
**********************************************************************************************************************/
#ifndef R_TRANSFER_API_H
#define R_TRANSFER_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define TRANSFER_API_VERSION_MAJOR (1U) // DEPRECATED
#define TRANSFER_API_VERSION_MINOR (0U) // DEPRECATED
#define TRANSFER_SETTINGS_MODE_BITS (30U)
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
* @par Implemented as
* - dtc_instance_ctrl_t
* - dmac_instance_ctrl_t
*/
typedef void transfer_ctrl_t;
/** Transfer mode describes what will happen when a transfer request occurs. */
typedef enum e_transfer_mode
{
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
* the destination pointer. The transfer length is decremented and the source and address pointers are
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
* will not cause any further transfers. */
TRANSFER_MODE_NORMAL = 0,
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
TRANSFER_MODE_REPEAT = 1,
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
* After each individual transfer, the source and destination pointers are updated according to
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
* further transfers. */
TRANSFER_MODE_BLOCK = 2
} transfer_mode_t;
/** Transfer size specifies the size of each individual transfer.
* Total transfer length = transfer_size_t * transfer_length_t
*/
typedef enum e_transfer_size
{
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
} transfer_size_t;
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
typedef enum e_transfer_addr_mode
{
/** Address pointer remains fixed after each transfer. */
TRANSFER_ADDR_MODE_FIXED = 0,
/** Offset is added to the address pointer after each transfer. */
TRANSFER_ADDR_MODE_OFFSET = 1,
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_INCREMENTED = 2,
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_DECREMENTED = 3
} transfer_addr_mode_t;
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK, the selected pointer
* returns to its original value after each transfer. */
typedef enum e_transfer_repeat_area
{
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK. */
TRANSFER_REPEAT_AREA_DESTINATION = 0,
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK. */
TRANSFER_REPEAT_AREA_SOURCE = 1
} transfer_repeat_area_t;
/** Chain transfer mode options.
* @note Only applies for DTC. */
typedef enum e_transfer_chain_mode
{
/** Chain mode not used. */
TRANSFER_CHAIN_MODE_DISABLED = 0,
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
TRANSFER_CHAIN_MODE_EACH = 2,
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
TRANSFER_CHAIN_MODE_END = 3
} transfer_chain_mode_t;
/** Interrupt options. */
typedef enum e_transfer_irq
{
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
* the interrupt will occur only after subsequent chained transfer(s) are complete.
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
* prevent activation source interrupts until the transfer is complete. */
TRANSFER_IRQ_END = 0,
/** Interrupt occurs after each transfer.
* @note Not available in all HAL drivers. See HAL driver for details. */
TRANSFER_IRQ_EACH = 1
} transfer_irq_t;
/** Driver specific information. */
typedef struct st_transfer_properties
{
uint32_t block_count_max; ///< Maximum number of blocks
uint32_t block_count_remaining; ///< Number of blocks remaining
uint32_t transfer_length_max; ///< Maximum number of transfers
uint32_t transfer_length_remaining; ///< Number of transfers remaining
} transfer_properties_t;
/** This structure specifies the properties of the transfer.
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
* have a unique transfer_info_t.
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
* structure must remain in scope until the transfer it is used for is closed.
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
typedef struct st_transfer_info
{
union
{
struct
{
uint32_t : 16;
uint32_t : 2;
/** Select what happens to destination pointer after each transfer. */
transfer_addr_mode_t dest_addr_mode : 2;
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
transfer_repeat_area_t repeat_area : 1;
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
* transfers. */
transfer_irq_t irq : 1;
/** Select when the chain transfer ends. */
transfer_chain_mode_t chain_mode : 2;
uint32_t : 2;
/** Select what happens to source pointer after each transfer. */
transfer_addr_mode_t src_addr_mode : 2;
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
transfer_size_t size : 2;
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
};
uint32_t transfer_settings_word;
};
void const * volatile p_src; ///< Source pointer
void * volatile p_dest; ///< Destination pointer
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) and
* @ref TRANSFER_MODE_REPEAT (DMAC only), unused in other modes. */
volatile uint16_t num_blocks;
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT,
* see HAL driver for details. */
volatile uint16_t length;
} transfer_info_t;
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
* initialized. */
typedef struct st_transfer_cfg
{
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
* an array of chained transfers that will be completed in order. */
transfer_info_t * p_info;
void const * p_extend; ///< Extension parameter for hardware specific settings.
} transfer_cfg_t;
/** Select whether to start single or repeated transfer with software start. */
typedef enum e_transfer_start_mode
{
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
} transfer_start_mode_t;
/** Transfer functions implemented at the HAL layer will follow this API. */
typedef struct st_transfer_api
{
/** Initial configuration.
* @par Implemented as
* - @ref R_DTC_Open()
* - @ref R_DMAC_Open()
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
* must be set by user.
*/
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
/** Reconfigure the transfer.
* Enable the transfer if p_info is valid.
* @par Implemented as
* - @ref R_DTC_Reconfigure()
* - @ref R_DMAC_Reconfigure()
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_info Pointer to a new transfer info structure.
*/
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
* Enable the transfer if p_src, p_dest, and length are valid.
* @par Implemented as
* - @ref R_DTC_Reset()
* - @ref R_DMAC_Reset()
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
* repeat mode. Not used in repeat mode for DTC.
*/
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint16_t const num_transfers);
/** Enable transfer. Transfers occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source).
* @par Implemented as
* - @ref R_DTC_Enable()
* - @ref R_DMAC_Enable()
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
/** Disable transfer. Transfers do not occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source).
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
* transfer.
* @par Implemented as
* - @ref R_DTC_Disable()
* - @ref R_DMAC_Disable()
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
/** Start transfer in software.
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
* @note Not supported for DTC.
* @par Implemented as
* - @ref R_DMAC_SoftwareStart()
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] mode Select mode from @ref transfer_start_mode_t.
*/
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
* @note Not supported for DTC.
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
* @par Implemented as
* - @ref R_DMAC_SoftwareStop()
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
/** Provides information about this transfer.
* @par Implemented as
* - @ref R_DTC_InfoGet()
* - @ref R_DMAC_InfoGet()
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[out] p_properties Driver specific information.
*/
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
* @par Implemented as
* - @ref R_DTC_Close()
* - @ref R_DMAC_Close()
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
/* DEPRECATED Gets version and stores it in provided pointer p_version.
* @par Implemented as
* - @ref R_DTC_VersionGet()
* - @ref R_DMAC_VersionGet()
* @param[out] p_version Code and API version used.
*/
fsp_err_t (* versionGet)(fsp_version_t * const p_version);
} transfer_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_transfer_instance
{
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
} transfer_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup TRANSFER_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_INTERFACES
* @defgroup UART_API UART Interface
* @brief Interface for UART communications.
*
* @section UART_INTERFACE_SUMMARY Summary
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
* - Full-duplex UART communication
* - Interrupt driven transmit/receive processing
* - Callback function with returned event code
* - Runtime baud-rate change
* - Hardware resource locking during a transaction
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
*
* Implemented by:
* - @ref SCI_UART
*
* @{
**********************************************************************************************************************/
#ifndef R_UART_API_H
#define R_UART_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "r_transfer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define UART_API_VERSION_MAJOR (1U) // DEPRECATED
#define UART_API_VERSION_MINOR (1U) // DEPRECATED
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** UART Event codes */
typedef enum e_sf_event
{
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
} uart_event_t;
/** UART Data bit length definition */
typedef enum e_uart_data_bits
{
UART_DATA_BITS_8, ///< Data bits 8-bit
UART_DATA_BITS_7, ///< Data bits 7-bit
UART_DATA_BITS_9 ///< Data bits 9-bit
} uart_data_bits_t;
/** UART Parity definition */
typedef enum e_uart_parity
{
UART_PARITY_OFF = 0U, ///< No parity
UART_PARITY_EVEN = 2U, ///< Even parity
UART_PARITY_ODD = 3U, ///< Odd parity
} uart_parity_t;
/** UART Stop bits definition */
typedef enum e_uart_stop_bits
{
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
} uart_stop_bits_t;
/** UART transaction definition */
typedef enum e_uart_dir
{
UART_DIR_RX_TX = 3U, ///< Both RX and TX
UART_DIR_RX = 1U, ///< Only RX
UART_DIR_TX = 2U, ///< Only TX
} uart_dir_t;
/** UART driver specific information */
typedef struct st_uart_info
{
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
uint32_t write_bytes_max;
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
uint32_t read_bytes_max;
} uart_info_t;
/** UART Callback parameter definition */
typedef struct st_uart_callback_arg
{
uint32_t channel; ///< Device channel number
uart_event_t event; ///< Event code
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
uint32_t data;
void const * p_context; ///< Context provided to user during callback
} uart_callback_args_t;
/** UART Configuration */
typedef struct st_uart_cfg
{
/* UART generic configuration */
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
uart_parity_t parity; ///< Parity type (none or odd or even)
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
uint8_t rxi_ipl; ///< Receive interrupt priority
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
uint8_t txi_ipl; ///< Transmit interrupt priority
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
uint8_t tei_ipl; ///< Transmit end interrupt priority
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
uint8_t eri_ipl; ///< Error interrupt priority
IRQn_Type eri_irq; ///< Error interrupt IRQ number
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
transfer_instance_t const * p_transfer_rx;
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
transfer_instance_t const * p_transfer_tx;
/* Configuration for UART Event processing */
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
void const * p_context; ///< User defined context passed into callback function
/* Pointer to UART peripheral specific configuration */
void const * p_extend; ///< UART hardware dependent configuration
} uart_cfg_t;
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
* @par Implemented as
* - sci_uart_instance_ctrl_t
*/
typedef void uart_ctrl_t;
/** Shared Interface definition for UART */
typedef struct st_uart_api
{
/** Open UART device.
* @par Implemented as
* - @ref R_SCI_UART_Open()
*
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
* user.
*/
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
* the callback function with event UART_EVENT_RX_CHAR.
* The maximum transfer size is reported by infoGet().
* @par Implemented as
* - @ref R_SCI_UART_Read()
*
* @param[in] p_ctrl Pointer to the UART control block for the channel.
* @param[in] p_dest Destination address to read data from.
* @param[in] bytes Read data length.
*/
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
* the callback called with event UART_EVENT_TX_COMPLETE.
* The maximum transfer size is reported by infoGet().
* @par Implemented as
* - @ref R_SCI_UART_Write()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_src Source address to write data to.
* @param[in] bytes Write data length.
*/
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
/** Change baud rate.
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
* settings have been applied.
*
* @par Implemented as
* - @ref R_SCI_UART_BaudSet()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
*/
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
/** Get the driver specific information.
* @par Implemented as
* - @ref R_SCI_UART_InfoGet()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] baudrate Baud rate in bps.
*/
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
/**
* Abort ongoing transfer.
* @par Implemented as
* - @ref R_SCI_UART_Abort()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] communication_to_abort Type of abort request.
*/
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
/**
* Specify callback function and optional context pointer and working memory pointer.
* @par Implemented as
* - R_SCI_Uart_CallbackSet()
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *),
void const * const p_context, uart_callback_args_t * const p_callback_memory);
/** Close UART device.
* @par Implemented as
* - @ref R_SCI_UART_Close()
*
* @param[in] p_ctrl Pointer to the UART control block.
*/
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
/* DEPRECATED Get version.
* @par Implemented as
* - @ref R_SCI_UART_VersionGet()
*
* @param[in] p_version Pointer to the memory to store the version information.
*/
fsp_err_t (* versionGet)(fsp_version_t * p_version);
} uart_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_uart_instance
{
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
} uart_instance_t;
/** @} (end defgroup UART_API) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_COMMON_API_H
#define FSP_COMMON_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <assert.h>
#include <stdint.h>
/* Includes FSP version macros. */
#include "fsp_version.h"
/*******************************************************************************************************************//**
* @ingroup RENESAS_COMMON
* @defgroup RENESAS_ERROR_CODES Common Error Codes
* All FSP modules share these common error codes.
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
* about using this implementation is that it does not take any extra RAM or ROM. */
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
/** Determine if a C++ compiler is being used.
* If so, ensure that standard C is used to process the API information. */
#if defined(__cplusplus)
#define FSP_CPP_HEADER extern "C" {
#define FSP_CPP_FOOTER }
#else
#define FSP_CPP_HEADER
#define FSP_CPP_FOOTER
#endif
/** FSP Header and Footer definitions */
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
#define FSP_SECURE_ARGUMENT (NULL)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Common error codes */
typedef enum e_fsp_err
{
FSP_SUCCESS = 0,
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
FSP_ERR_ABORTED = 18, ///< An operation was aborted
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
FSP_ERR_TIMEOUT = 20, ///< Timeout error
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
/* Start of RTOS only error codes */
FSP_ERR_INTERNAL = 100, ///< Internal error
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
/* Start of UART specific */
FSP_ERR_FRAMING = 200, ///< Framing error occurs
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
FSP_ERR_PARITY = 202, ///< Parity error occurs
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
/* Start of SPI specific */
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
FSP_ERR_OVERRUN = 304, ///< Overrun error.
/* Start of CGC Specific */
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
/* Start of FLASH Specific */
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
/* Start of JPEG Specific */
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
/* Start of USB specific */
FSP_ERR_USB_FAILED = 1500,
FSP_ERR_USB_BUSY = 1501,
FSP_ERR_USB_SIZE_SHORT = 1502,
FSP_ERR_USB_SIZE_OVER = 1503,
FSP_ERR_USB_NOT_OPEN = 1504,
FSP_ERR_USB_NOT_SUSPEND = 1505,
FSP_ERR_USB_PARAMETER = 1506,
/* Start of Message framework specific */
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
/* Start of 2DG Driver specific */
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
/* Start of ETHER Driver specific */
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
/* Start of ETHER_PHY Driver specific */
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
/* Start of BYTEQ library specific */
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
/* Start of CTSU Driver specific */
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
/* Start of SDMMC specific */
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
/* Start of FX_IO specific */
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
/* Start of CAN specific */
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
/* Start of SF_WIFI Specific */
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
/* Start of SF_BLE specific */
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
/* Start of SF_BLE_ABS specific */
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013,
/* Start of SF_CRYPTO specific */
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
* Refer to sf_cryoto_err.h for Crypto error codes.
*/
} fsp_err_t;
/** Common version structure */
typedef union st_fsp_version
{
/** Version id */
uint32_t version_id;
/** Code version parameters */
struct
{
uint8_t code_version_minor; ///< Code minor version
uint8_t code_version_major; ///< Code major version
uint8_t api_version_minor; ///< API minor version
uint8_t api_version_major; ///< API major version
};
} fsp_version_t;
/** @} */
/***********************************************************************************************************************
* Function prototypes
**********************************************************************************************************************/
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_FEATURES_H
#define FSP_FEATURES_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
/* Different compiler support. */
#include "fsp_common_api.h"
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Available modules. */
typedef enum e_fsp_ip
{
FSP_IP_CFLASH = 0, ///< Code Flash
FSP_IP_DFLASH = 1, ///< Data Flash
FSP_IP_RAM = 2, ///< RAM
FSP_IP_LVD = 3, ///< Low Voltage Detection
FSP_IP_CGC = 3, ///< Clock Generation Circuit
FSP_IP_LPM = 3, ///< Low Power Modes
FSP_IP_FCU = 4, ///< Flash Control Unit
FSP_IP_ICU = 6, ///< Interrupt Control Unit
FSP_IP_DMAC = 7, ///< DMA Controller
FSP_IP_DTC = 8, ///< Data Transfer Controller
FSP_IP_IOPORT = 9, ///< I/O Ports
FSP_IP_PFS = 10, ///< Pin Function Select
FSP_IP_ELC = 11, ///< Event Link Controller
FSP_IP_MPU = 13, ///< Memory Protection Unit
FSP_IP_MSTP = 14, ///< Module Stop
FSP_IP_MMF = 15, ///< Memory Mirror Function
FSP_IP_KEY = 16, ///< Key Interrupt Function
FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit
FSP_IP_DOC = 18, ///< Data Operation Circuit
FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator
FSP_IP_SCI = 20, ///< Serial Communications Interface
FSP_IP_IIC = 21, ///< I2C Bus Interface
FSP_IP_SPI = 22, ///< Serial Peripheral Interface
FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit
FSP_IP_SCE = 24, ///< Secure Cryptographic Engine
FSP_IP_SLCDC = 25, ///< Segment LCD Controller
FSP_IP_AES = 26, ///< Advanced Encryption Standard
FSP_IP_TRNG = 27, ///< True Random Number Generator
FSP_IP_FCACHE = 30, ///< Flash Cache
FSP_IP_SRAM = 31, ///< SRAM
FSP_IP_ADC = 32, ///< A/D Converter
FSP_IP_DAC = 33, ///< 12-Bit D/A Converter
FSP_IP_TSN = 34, ///< Temperature Sensor
FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit
FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator
FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator
FSP_IP_OPAMP = 38, ///< Operational Amplifier
FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter
FSP_IP_RTC = 40, ///< Real Time Clock
FSP_IP_WDT = 41, ///< Watch Dog Timer
FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer
FSP_IP_GPT = 43, ///< General PWM Timer
FSP_IP_POEG = 44, ///< Port Output Enable for GPT
FSP_IP_OPS = 45, ///< Output Phase Switch
FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer
FSP_IP_CAN = 48, ///< Controller Area Network
FSP_IP_IRDA = 49, ///< Infrared Data Association
FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface
FSP_IP_USBFS = 51, ///< USB Full Speed
FSP_IP_SDHI = 52, ///< SD/MMC Host Interface
FSP_IP_SRC = 53, ///< Sampling Rate Converter
FSP_IP_SSI = 54, ///< Serial Sound Interface
FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface
FSP_IP_ETHER = 64, ///< Ethernet MAC Controller
FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller
FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller
FSP_IP_PDC = 66, ///< Parallel Data Capture Unit
FSP_IP_GLCDC = 67, ///< Graphics LCD Controller
FSP_IP_DRW = 68, ///< 2D Drawing Engine
FSP_IP_JPEG = 69, ///< JPEG
FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter
FSP_IP_USBHS = 71, ///< USB High Speed
FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
typedef enum e_fsp_signal
{
FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH
FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH
FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END
FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B
FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A
FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B
FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ
FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ
FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A
FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B
FSP_SIGNAL_AGT_INT, ///< AGT INT
FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR
FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END
FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW
FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR
FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX
FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX
FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX
FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX
FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP
FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST
FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1
FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2
FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD
FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT
FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT
FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT
FSP_SIGNAL_CTSU_END = 0, ///< CTSU END
FSP_SIGNAL_CTSU_READ, ///< CTSU READ
FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE
FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI
FSP_SIGNAL_DALI_CLI, ///< DALI CLI
FSP_SIGNAL_DALI_SDI, ///< DALI SDI
FSP_SIGNAL_DALI_BPI, ///< DALI BPI
FSP_SIGNAL_DALI_FEI, ///< DALI FEI
FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI
FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT
FSP_SIGNAL_DOC_INT = 0, ///< DOC INT
FSP_SIGNAL_DRW_INT = 0, ///< DRW INT
FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE
FSP_SIGNAL_DTC_END, ///< DTC END
FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1
FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS
FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT
FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT
FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL
FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE
FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL
FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE
FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL
FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE
FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL
FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE
FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL
FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE
FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL
FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE
FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR
FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI
FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT
FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1
FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B
FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C
FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D
FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E
FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F
FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW
FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A
FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B
FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE
FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0
FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1
FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2
FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3
FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4
FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5
FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6
FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7
FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8
FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9
FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10
FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11
FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12
FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13
FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14
FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15
FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL
FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI
FSP_SIGNAL_IIC_RXI, ///< IIC RXI
FSP_SIGNAL_IIC_TEI, ///< IIC TEI
FSP_SIGNAL_IIC_TXI, ///< IIC TXI
FSP_SIGNAL_IIC_WUI, ///< IIC WUI
FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1
FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2
FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3
FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4
FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW
FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI
FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI
FSP_SIGNAL_KEY_INT = 0, ///< KEY INT
FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END
FSP_SIGNAL_PDC_INT, ///< PDC INT
FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY
FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT
FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT
FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM
FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD
FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY
FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY
FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY
FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG
FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY
FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0
FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1
FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK
FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY
FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0
FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1
FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4
FSP_SIGNAL_SCI_AM = 0, ///< SCI AM
FSP_SIGNAL_SCI_ERI, ///< SCI ERI
FSP_SIGNAL_SCI_RXI, ///< SCI RXI
FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI
FSP_SIGNAL_SCI_TEI, ///< SCI TEI
FSP_SIGNAL_SCI_TXI, ///< SCI TXI
FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI
FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND
FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND
FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS
FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD
FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ
FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO
FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI
FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE
FSP_SIGNAL_SPI_RXI, ///< SPI RXI
FSP_SIGNAL_SPI_TEI, ///< SPI TEI
FSP_SIGNAL_SPI_TXI, ///< SPI TXI
FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW
FSP_SIGNAL_SSI_INT = 0, ///< SSI INT
FSP_SIGNAL_SSI_RXI, ///< SSI RXI
FSP_SIGNAL_SSI_TXI, ///< SSI TXI
FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI
FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ
FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0
FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1
FSP_SIGNAL_USB_INT, ///< USB INT
FSP_SIGNAL_USB_RESUME, ///< USB RESUME
FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
} fsp_signal_t;
typedef void (* fsp_vector_t)(void);
/** @} (end addtogroup BSP_MCU) */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_VERSION_H
#define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
#define FSP_VERSION_MAJOR (2U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (3U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("2.3.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 2.3.0")
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** FSP Pack version structure */
typedef union st_fsp_pack_version
{
/** Version id */
uint32_t version_id;
/** Code version parameters, little endian order. */
struct
{
uint8_t build; ///< Build version of FSP Pack
uint8_t patch; ///< Patch version of FSP Pack
uint8_t minor; ///< Minor version of FSP Pack
uint8_t major; ///< Major version of FSP Pack
};
} fsp_pack_version_t;
/** @} */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_H
#define R_IOPORT_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "r_ioport_api.h"
#include "r_ioport_cfg.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define IOPORT_CODE_VERSION_MAJOR (1U) // DEPRECATED
#define IOPORT_CODE_VERSION_MINOR (1U) // DEPRECATED
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
typedef struct st_ioport_instance_ctrl
{
uint32_t open;
void const * p_context;
} ioport_instance_ctrl_t;
/* This typedef is here temporarily. See SWFLEX-144 for details. */
/** Superset list of all possible IO port pins. */
typedef enum e_ioport_port_pin_t
{
IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2
IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3
IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4
IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5
IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6
IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7
IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8
IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9
IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10
IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11
IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12
IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13
IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14
IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15
IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2
IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3
IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4
IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5
IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6
IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7
IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8
IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9
IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10
IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11
IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12
IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13
IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14
IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15
IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2
IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3
IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4
IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5
IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6
IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7
IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8
IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9
IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10
IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11
IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12
IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13
IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14
IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15
IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2
IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3
IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4
IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5
IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6
IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7
IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8
IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9
IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10
IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11
IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12
IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13
IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14
IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15
IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2
IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3
IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4
IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5
IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6
IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7
IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8
IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9
IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10
IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11
IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12
IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13
IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14
IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15
IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3
IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4
IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5
IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6
IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7
IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8
IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9
IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10
IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11
IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12
IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13
IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14
IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15
IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2
IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3
IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4
IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5
IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6
IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7
IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8
IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9
IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10
IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11
IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12
IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13
IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14
IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15
IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3
IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4
IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5
IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6
IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7
IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8
IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9
IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10
IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11
IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12
IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13
IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14
IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15
IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3
IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4
IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5
IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6
IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7
IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8
IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9
IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10
IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11
IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12
IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13
IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14
IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15
IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2
IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3
IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4
IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5
IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6
IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7
IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8
IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9
IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10
IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11
IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12
IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13
IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14
IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15
IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2
IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3
IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4
IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5
IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6
IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7
IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8
IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9
IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10
IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11
IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12
IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13
IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14
IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15
IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2
IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3
IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4
IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5
IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6
IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7
IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8
IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9
IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10
IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11
IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12
IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
} ioport_port_pin_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const ioport_api_t g_ioport_on_ioport;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask);
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl,
ioport_ethernet_channel_t channel,
ioport_ethernet_mode_t mode);
fsp_err_t R_IOPORT_VersionGet(fsp_version_t * p_data);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif // R_IOPORT_H

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board/Renesas_ra6m4/ra/fsp/inc/instances/r_sci_uart.h Normal file
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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_SCI_UART_H
#define R_SCI_UART_H
/*******************************************************************************************************************//**
* @addtogroup SCI_UART
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_uart_api.h"
#include "r_sci_uart_cfg.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define SCI_UART_CODE_VERSION_MAJOR (1U) // DEPRECATED
#define SCI_UART_CODE_VERSION_MINOR (2U) // DEPRECATED
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Enumeration for SCI clock source */
typedef enum e_sci_clk_src
{
SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation
SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
} sci_clk_src_t;
/** UART communication mode definition */
typedef enum e_uart_mode
{
UART_MODE_RS232 = 0U, ///< Enables RS232 communication mode
UART_MODE_RS485_HD = 1U, ///< Enables RS485 half duplex communication mode
UART_MODE_RS485_FD = 2U, ///< Enables RS485 full duplex communication mode
} uart_mode_t;
/** UART instance control block. */
typedef struct st_sci_uart_instance_ctrl
{
/* Parameters to control UART peripheral device */
uint8_t fifo_depth; // FIFO depth of the UART channel
uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise
uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise
uint32_t open; // Used to determine if the channel is configured
bsp_io_port_pin_t flow_pin;
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint8_t const * p_tx_src;
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint32_t tx_src_bytes;
/* Destination buffer pointer used for receiving data. */
uint8_t const * p_rx_dest;
/* Size of destination buffer pointer used for receiving data. */
uint32_t rx_dest_bytes;
/* Pointer to the configuration block. */
uart_cfg_t const * p_cfg;
/* Base register for this channel */
R_SCI0_Type * p_reg;
void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
/* Pointer to context to be passed into callback function */
void const * p_context;
} sci_uart_instance_ctrl_t;
/** Receive FIFO trigger configuration. */
typedef enum e_sci_uart_rx_fifo_trigger
{
SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering
SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
} sci_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
typedef enum e_sci_uart_start_bit_detect
{
SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
} sci_uart_start_bit_detect_t;
/** Noise cancellation configuration. */
typedef enum e_sci_uart_noise_cancellation
{
SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation
} sci_uart_noise_cancellation_t;
/** CTS/RTS function of the SSn pin. */
typedef enum e_sci_uart_ctsrts_config
{
SCI_UART_CTSRTS_RTS_OUTPUT = 0x0, ///< Disable CTS function (RTS output function is enabled)
SCI_UART_CTSRTS_CTS_INPUT = 0x1, ///< Enable CTS function
} sci_uart_ctsrts_config_t;
/** Register settings to acheive a desired baud rate and modulation duty. */
typedef struct st_baud_setting_t
{
union
{
uint8_t semr_baudrate_bits;
struct
{
uint8_t : 2;
uint8_t brme : 1; ///< Bit Rate Modulation Enable
uint8_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1
uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select
uint8_t : 1;
uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
uint8_t : 1;
};
};
uint8_t cks : 2; ///< CKS value to get divisor (CKS = N)
uint8_t brr; ///< Bit Rate Register setting
uint8_t mddr; ///< Modulation Duty Register setting
} baud_setting_t;
/** UART on SCI device Configuration */
typedef struct st_sci_uart_extended_cfg
{
sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
sci_uart_start_bit_detect_t rx_edge_start; ///< Start reception on falling edge
sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used.
uart_mode_t uart_mode; ///< UART communication mode selection
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
sci_uart_ctsrts_config_t ctsrts_en; ///< CTS/RTS function of the SSn pin
} sci_uart_extended_cfg_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const uart_api_t g_uart_on_sci;
/** @endcond */
fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl);
fsp_err_t R_SCI_UART_VersionGet(fsp_version_t * p_version);
fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate,
bool bitrate_modulation,
uint32_t baud_rate_error_x_1000,
baud_setting_t * const p_baud_setting);
fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
void ( * p_callback)(uart_callback_args_t *),
void const * const p_context,
uart_callback_args_t * const p_callback_memory);
/*******************************************************************************************************************//**
* @} (end addtogroup SCI_UART)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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board/Renesas_ra6m4/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h Normal file
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#ifndef __BASE_ADDRESSES_H
#define __BASE_ADDRESSES_H
#if 33U == __CORTEX_M // NOLINT(readability-magic-numbers)
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
#define R_MPU_BASE 0x40000000
#define R_TZF_BASE 0x40000E00
#define R_SRAM_BASE 0x40002000
#define R_BUS_BASE 0x40003000
#define R_DMAC0_BASE 0x40005000
#define R_DMAC1_BASE 0x40005040
#define R_DMAC2_BASE 0x40005080
#define R_DMAC3_BASE 0x400050C0
#define R_DMAC4_BASE 0x40005100
#define R_DMAC5_BASE 0x40005140
#define R_DMAC6_BASE 0x40005180
#define R_DMAC7_BASE 0x400051C0
#define R_DMA_BASE 0x40005200
#define R_DTC_BASE 0x40005400
#define R_ICU_BASE 0x40006000
#define R_CACHE_BASE 0x40007000
#define R_CPSCU_BASE 0x40008000
#define R_DBG_BASE 0x4001B000
#define R_FCACHE_BASE 0x4001C000
#define R_SYSC_BASE 0x4001E000
#define R_TSN_CAL_BASE 0x407FB17C
#define R_TSN_CTRL_BASE 0x400F3000
#define R_PFS_BASE 0x40080800
#define R_ELC_BASE 0x40082000
#define R_TC_BASE 0x40083000
#define R_IWDT_BASE 0x40083200
#define R_WDT_BASE 0x40083400
#define R_CAC_BASE 0x40083600
#define R_MSTP_BASE 0x40084004
// #define R_MSTP_BASE 0x40084000
#define R_POEG_BASE 0x4008A000
#define R_USB_FS0_BASE 0x40090000
#define R_USB_HS0_BASE 0x40111000
#define R_SDHI0_BASE 0x40092000
#define R_SSI0_BASE 0x4009D000
#define R_IIC0_BASE 0x4009F000
#define R_IIC0WU_BASE 0x4009F014
#define R_IIC1_BASE 0x4009F100
#define R_OSPI_BASE 0x400A6000
#define R_CAN0_BASE 0x400A8000
#define R_CAN1_BASE 0x400A9000
#define R_CTSU_BASE 0x400D0000
#define R_PSCU_BASE 0x400E0000
#define R_AGT0_BASE 0x400E8000
#define R_AGT1_BASE 0x400E8100
#define R_AGT2_BASE 0x400E8200
#define R_AGT3_BASE 0x400E8300
#define R_AGT4_BASE 0x400E8400
#define R_AGT5_BASE 0x400E8500
#define R_TSN_CTRL_BASE 0x400F3000
#define R_CRC_BASE 0x40108000
#define R_DOC_BASE 0x40109000
#define R_ETHERC_EDMAC_BASE 0x40114000
#define R_ETHERC0_BASE 0x40114100
#define R_SCI0_BASE 0x40118000
#define R_SCI1_BASE 0x40118100
#define R_SCI2_BASE 0x40118200
#define R_SCI3_BASE 0x40118300
#define R_SCI4_BASE 0x40118400
#define R_SCI5_BASE 0x40118500
#define R_SCI6_BASE 0x40118600
#define R_SCI7_BASE 0x40118700
#define R_SCI8_BASE 0x40118800
#define R_SCI9_BASE 0x40118900
#define R_SPI0_BASE 0x4011A000
#define R_SPI1_BASE 0x4011A100
#define R_GPT320_BASE 0x40169000
#define R_GPT321_BASE 0x40169100
#define R_GPT322_BASE 0x40169200
#define R_GPT323_BASE 0x40169300
#define R_GPT164_BASE 0x40169400
#define R_GPT165_BASE 0x40169500
#define R_GPT166_BASE 0x40169600
#define R_GPT167_BASE 0x40169700
#define R_GPT168_BASE 0x40169800
#define R_GPT169_BASE 0x40169900
#define R_GPT_OPS_BASE 0x40169A00
#define R_ADC120_BASE 0x40170000
#define R_ADC121_BASE 0x40170200
#define R_DAC12_BASE 0x40171000
#define R_FLAD_BASE 0x407FC000
#define R_FACI_HP_CMD_BASE 0x407E0000
#define R_FACI_HP_BASE 0x407FE000
#define R_QSPI_BASE 0x64000000
/* Not included in SVD */
#define R_PORT0_BASE 0x40080000
#define R_PORT1_BASE 0x40080020
#define R_PORT2_BASE 0x40080040
#define R_PORT3_BASE 0x40080060
#define R_PORT4_BASE 0x40080080
#define R_PORT5_BASE 0x400800A0
#define R_PORT6_BASE 0x400800C0
#define R_PORT7_BASE 0x400800E0
#define R_PORT8_BASE 0x40080100
#define R_PORT9_BASE 0x40080120
#define R_PORT10_BASE 0x40080140
#define R_PORT11_BASE 0x40080160
#define R_PFS_BASE 0x40080800
#define R_PMISC_BASE 0x40080D00 // does not exist but FSP will not build without this
#define R_GPT_POEG0_BASE 0x4008A000
#define R_GPT_POEG1_BASE 0x4008A100
#define R_GPT_POEG2_BASE 0x4008A200
#define R_GPT_POEG3_BASE 0x4008A300
#define R_RTC_BASE 0x40083000
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
// #define R_MPU ((R_MPU_Type *) R_MPU_BASE)
#define R_TZF ((R_TZF_Type *) R_TZF_BASE)
#define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
#define R_BUS ((R_BUS_Type *) R_BUS_BASE)
#define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
#define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
#define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
#define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
#define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
#define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
#define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
#define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
#define R_DMA ((R_DMA_Type *) R_DMA_BASE)
#define R_DTC ((R_DTC_Type *) R_DTC_BASE)
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
#define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE)
#define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
#define R_DEBUG ((R_DEBUG_Type *) R_DBG_BASE)
#define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
#define R_SYSTEM ((R_SYSTEM_Type *) R_SYSC_BASE)
#define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
#define R_ELC ((R_ELC_Type *) R_ELC_BASE)
#define R_TC ((R_TC_Type *) R_TC_BASE)
#define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
#define R_WDT ((R_WDT_Type *) R_WDT_BASE)
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
#define R_POEG ((R_POEG_Type *) R_POEG_BASE)
#define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
#define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
#define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
#define R_IIC0WU ((R_IIC0WU_Type *) R_IIC0WU_BASE)
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
#define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE)
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
#define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
#define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE)
#define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE)
#define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE)
#define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE)
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
#define R_DOC ((R_DOC_Type *) R_DOC_BASE)
#define R_ETHERC_EDMAC0 ((R_ETHERC_EDMAC0_Type *) R_ETHERC_EDMAC0_BASE)
#define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
#define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
#define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
#define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
#define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
#define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
#define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
#define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
#define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
#define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
#define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
#define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
#define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
#define R_GPT0 ((R_GPT0_Type *) R_GPT320_BASE)
#define R_GPT1 ((R_GPT0_Type *) R_GPT321_BASE)
#define R_GPT2 ((R_GPT0_Type *) R_GPT322_BASE)
#define R_GPT3 ((R_GPT0_Type *) R_GPT323_BASE)
#define R_GPT4 ((R_GPT0_Type *) R_GPT164_BASE)
#define R_GPT5 ((R_GPT0_Type *) R_GPT165_BASE)
#define R_GPT6 ((R_GPT0_Type *) R_GPT166_BASE)
#define R_GPT7 ((R_GPT0_Type *) R_GPT167_BASE)
#define R_GPT8 ((R_GPT0_Type *) R_GPT168_BASE)
#define R_GPT9 ((R_GPT0_Type *) R_GPT169_BASE)
#define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
#define R_ADC0 ((R_ADC0_Type *) R_ADC120_BASE)
#define R_ADC1 ((R_ADC0_Type *) R_ADC121_BASE)
#define R_DAC ((R_DAC_Type *) R_DAC12_BASE)
#define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
#define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
#define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
#define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
/* Not in SVD. */
#define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
#define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
#define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
#define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
#define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
#define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
#define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
#define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
#define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
#define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
#define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
#define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
#define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
#define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
#define R_RTC ((R_RTC_Type *) R_RTC_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
#else
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
#define R_ACMPHS0_BASE 0x40085000
#define R_ACMPHS1_BASE 0x40085100
#define R_ACMPHS2_BASE 0x40085200
#define R_ACMPHS3_BASE 0x40085300
#define R_ACMPHS4_BASE 0x40085400
#define R_ACMPHS5_BASE 0x40085500
#define R_ACMPLP_BASE 0x40085E00
#define R_ADC0_BASE 0x4005C000
#define R_ADC1_BASE 0x4005C200
#define R_AGT0_BASE 0x40084000
#define R_AGT1_BASE 0x40084100
#define R_BUS_BASE 0x40003000
#define R_CAC_BASE 0x40044600
#define R_CAN0_BASE 0x40050000
#define R_CAN1_BASE 0x40051000
#define R_CRC_BASE 0x40074000
#define R_CTSU_BASE 0x40081000
#define R_CTSU2_BASE 0x40082000
#define R_DAC_BASE 0x4005E000
#define R_DAC8_BASE 0x4009E000
#define R_DALI0_BASE 0x4008F000
#define R_DEBUG_BASE 0x4001B000
#define R_DMA_BASE 0x40005200
#define R_DMAC0_BASE 0x40005000
#define R_DMAC1_BASE 0x40005040
#define R_DMAC2_BASE 0x40005080
#define R_DMAC3_BASE 0x400050C0
#define R_DMAC4_BASE 0x40005100
#define R_DMAC5_BASE 0x40005140
#define R_DMAC6_BASE 0x40005180
#define R_DMAC7_BASE 0x400051C0
#define R_DOC_BASE 0x40054100
#define R_DRW_BASE 0x400E4000
#define R_DTC_BASE 0x40005400
#define R_ELC_BASE 0x40041000
#define R_ETHERC0_BASE 0x40064100
#define R_ETHERC_EDMAC_BASE 0x40064000
#define R_ETHERC_EPTPC_BASE 0x40065800
#define R_ETHERC_EPTPC1_BASE 0x40065C00
#define R_ETHERC_EPTPC_CFG_BASE 0x40064500
#define R_ETHERC_EPTPC_COMMON_BASE 0x40065000
#define R_FACI_HP_CMD_BASE 0x407E0000
#define R_FACI_HP_BASE 0x407FE000
#define R_FACI_LP_BASE 0x407EC000
#define R_CTSUTRIM_BASE 0x407EC000
#define R_FCACHE_BASE 0x4001C000
#define R_GLCDC_BASE 0x400E0000
#define R_GPT0_BASE 0x40078000
#define R_GPT1_BASE 0x40078100
#define R_GPT2_BASE 0x40078200
#define R_GPT3_BASE 0x40078300
#define R_GPT4_BASE 0x40078400
#define R_GPT5_BASE 0x40078500
#define R_GPT6_BASE 0x40078600
#define R_GPT7_BASE 0x40078700
#define R_GPT8_BASE 0x40078800
#define R_GPT9_BASE 0x40078900
#define R_GPT10_BASE 0x40078A00
#define R_GPT11_BASE 0x40078B00
#define R_GPT12_BASE 0x40078C00
#define R_GPT13_BASE 0x40078D00
#define R_GPT_ODC_BASE 0x4007B000
#define R_GPT_OPS_BASE 0x40078FF0
#define R_GPT_POEG0_BASE 0x40042000
#define R_GPT_POEG1_BASE 0x40042100
#define R_GPT_POEG2_BASE 0x40042200
#define R_GPT_POEG3_BASE 0x40042300
#define R_ICU_BASE 0x40006000
#define R_IIC0_BASE 0x40053000
#define R_IIC1_BASE 0x40053100
#define R_IIC2_BASE 0x40053200
#define R_IRDA_BASE 0x40070F00
#define R_IWDT_BASE 0x40044400
#define R_JPEG_BASE 0x400E6000
#define R_KINT_BASE 0x40080000
#define R_MMF_BASE 0x40001000
#define R_MPU_MMPU_BASE 0x40000000
#define R_MPU_SMPU_BASE 0x40000C00
#define R_MPU_SPMON_BASE 0x40000D00
#define R_MSTP_BASE 0x40047000
#define R_OPAMP_BASE 0x40086000
#define R_OPAMP2_BASE 0x400867F8
#define R_PDC_BASE 0x40094000
#define R_PORT0_BASE 0x40040000
#define R_PORT1_BASE 0x40040020
#define R_PORT2_BASE 0x40040040
#define R_PORT3_BASE 0x40040060
#define R_PORT4_BASE 0x40040080
#define R_PORT5_BASE 0x400400A0
#define R_PORT6_BASE 0x400400C0
#define R_PORT7_BASE 0x400400E0
#define R_PORT8_BASE 0x40040100
#define R_PORT9_BASE 0x40040120
#define R_PORT10_BASE 0x40040140
#define R_PORT11_BASE 0x40040160
#define R_PFS_BASE 0x40040800
#define R_PMISC_BASE 0x40040D00
#define R_QSPI_BASE 0x64000000
#define R_RTC_BASE 0x40044000
#define R_SCI0_BASE 0x40070000
#define R_SCI1_BASE 0x40070020
#define R_SCI2_BASE 0x40070040
#define R_SCI3_BASE 0x40070060
#define R_SCI4_BASE 0x40070080
#define R_SCI5_BASE 0x400700A0
#define R_SCI6_BASE 0x400700C0
#define R_SCI7_BASE 0x400700E0
#define R_SCI8_BASE 0x40070100
#define R_SCI9_BASE 0x40070120
#define R_SDADC0_BASE 0x4009C000
#define R_SDHI0_BASE 0x40062000
#define R_SDHI1_BASE 0x40062400
#define R_SLCDC_BASE 0x40082000
#define R_SPI0_BASE 0x40072000
#define R_SPI1_BASE 0x40072100
#define R_SRAM_BASE 0x40002000
#define R_SRC_BASE 0x40048000
#define R_SSI0_BASE 0x4004E000
#define R_SSI1_BASE 0x4004E100
#define R_SYSTEM_BASE 0x4001E000
#define R_TSN_BASE 0x407EC000
#define R_TSN_CAL_BASE 0x407FB17C
#define R_TSN_CTRL_BASE 0x4005D000
#define R_USB_FS0_BASE 0x40090000
#define R_USB_HS0_BASE 0x40060000
#define R_WDT_BASE 0x40044200
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
#define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
#define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
#define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
#define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
#define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
#define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE)
#define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE)
#define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
#define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE)
#define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE)
#define R_BUS ((R_BUS_Type *) R_BUS_BASE)
#define R_CAC ((R_CAC_Type *) R_CAC_BASE)
#define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE)
#define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE)
#define R_CRC ((R_CRC_Type *) R_CRC_BASE)
#if (BSP_FEATURE_CTSU_VERSION == 2)
#define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE)
#else
#define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE)
#endif
#define R_DAC ((R_DAC_Type *) R_DAC_BASE)
#define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE)
#define R_DALI0 ((R_DALI0_Type *) R_DALI0_BASE)
#define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE)
#define R_DMA ((R_DMA_Type *) R_DMA_BASE)
#define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
#define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
#define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
#define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
#define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
#define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
#define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
#define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
#define R_DOC ((R_DOC_Type *) R_DOC_BASE)
#define R_DRW ((R_DRW_Type *) R_DRW_BASE)
#define R_DTC ((R_DTC_Type *) R_DTC_BASE)
#define R_ELC ((R_ELC_Type *) R_ELC_BASE)
#define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
#define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
#define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE)
#define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC0_Type *) R_ETHERC_EPTPC1_BASE)
#define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE)
#define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE)
#define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
#define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
#define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE)
#define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE)
#define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
#define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE)
#define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE)
#define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE)
#define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE)
#define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE)
#define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE)
#define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE)
#define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE)
#define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE)
#define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE)
#define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE)
#define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE)
#define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE)
#define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE)
#define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE)
#define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE)
#define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
#define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
#define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
#define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
#define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
#define R_ICU ((R_ICU_Type *) R_ICU_BASE)
#define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
#define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
#define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE)
#define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE)
#define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
#define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE)
#define R_KINT ((R_KINT_Type *) R_KINT_BASE)
#define R_MMF ((R_MMF_Type *) R_MMF_BASE)
#define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
#define R_MPU_SMPU ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
#define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
#define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
#if (BSP_FEATURE_OPAMP_BASE_ADDRESS == 2U)
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP2_BASE)
#else
#define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE)
#endif
#define R_PDC ((R_PDC_Type *) R_PDC_BASE)
#define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
#define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
#define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
#define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
#define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
#define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
#define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
#define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
#define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
#define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
#define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
#define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
#define R_PFS ((R_PFS_Type *) R_PFS_BASE)
#define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
#define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE)
#define R_RTC ((R_RTC_Type *) R_RTC_BASE)
#define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
#define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
#define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
#define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
#define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
#define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
#define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
#define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
#define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
#define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
#define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE)
#define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
#define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE)
#define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE)
#define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
#define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
#define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
#define R_SRC ((R_SRC_Type *) R_SRC_BASE)
#define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
#define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE)
#define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE)
#define R_TSN ((R_TSN_Type *) R_TSN_BASE)
#define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
#define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
#define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
#define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
#define R_WDT ((R_WDT_Type *) R_WDT_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef SYSTEM_RENESAS_ARM_H
#define SYSTEM_RENESAS_ARM_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if BSP_TZ_SECURE_BUILD
#define BSP_TZ_STACK_SEAL_SIZE (8U)
#else
#define BSP_TZ_STACK_SEAL_SIZE (0U)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/* Defines function pointers to be used with vector table. */
typedef void (* exc_ptr_t)(void);
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
void Reset_Handler(void);
void Default_Handler(void);
int32_t main(void);
/*******************************************************************************************************************//**
* MCU starts executing here out of reset. Main stack pointer is set up already.
**********************************************************************************************************************/
void Reset_Handler (void)
{
/* Initialize system using BSP. */
SystemInit();
/* Call user application. */
main();
while (1)
{
/* Infinite Loop. */
}
}
/*******************************************************************************************************************//**
* Default exception handler.
**********************************************************************************************************************/
void Default_Handler (void)
{
/** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption
* or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status
* registers for more information.
*/
BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
}
/* Main stack */
static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_STACK);
/* Heap */
#if (BSP_CFG_HEAP_BYTES > 0)
BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \
BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP);
#endif
/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle
* these exceptions in their code they should define their own function with the same name.
*/
#if defined(__ICCARM__)
#define WEAK_REF_ATTRIBUTE
#pragma weak HardFault_Handler = Default_Handler
#pragma weak MemManage_Handler = Default_Handler
#pragma weak BusFault_Handler = Default_Handler
#pragma weak UsageFault_Handler = Default_Handler
#pragma weak SecureFault_Handler = Default_Handler
#pragma weak SVC_Handler = Default_Handler
#pragma weak DebugMon_Handler = Default_Handler
#pragma weak PendSV_Handler = Default_Handler
#pragma weak SysTick_Handler = Default_Handler
#elif defined(__GNUC__)
#define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler")))
#endif
void NMI_Handler(void); // NMI has many sources and is handled by BSP
void HardFault_Handler(void) WEAK_REF_ATTRIBUTE;
void MemManage_Handler(void) WEAK_REF_ATTRIBUTE;
void BusFault_Handler(void) WEAK_REF_ATTRIBUTE;
void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE;
void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE;
void SVC_Handler(void) WEAK_REF_ATTRIBUTE;
void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE;
void PendSV_Handler(void) WEAK_REF_ATTRIBUTE;
void SysTick_Handler(void) WEAK_REF_ATTRIBUTE;
/* Vector table. */
BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION(
BSP_SECTION_FIXED_VECTORS) =
{
(exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
SecureFault_Handler, /* Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
};
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include <string.h>
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Mask to select CP bits( 0xF00000 ) */
#define CP_MASK (0xFU << 20)
/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U)
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
#if defined(__ICCARM__)
#define BSP_PRV_STACK_LIMIT ((uint32_t) __section_begin(".stack"))
#define BSP_PRV_STACK_TOP ((uint32_t) __section_end(".stack"))
#elif defined(__ARMCC_VERSION)
#define BSP_PRV_STACK_LIMIT ((uint32_t) &Image$$STACK$$ZI$$Base)
#define BSP_PRV_STACK_TOP ((uint32_t) &Image$$STACK$$ZI$$Base + \
(uint32_t) &Image$$STACK$$ZI$$Length)
#elif defined(__GNUC__)
#define BSP_PRV_STACK_LIMIT ((uint32_t) &__StackLimit)
#define BSP_PRV_STACK_TOP ((uint32_t) &__StackTop)
#endif
#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = 0U;
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$BSS$$ZI$$Base;
extern uint32_t Image$$BSS$$ZI$$Length;
extern uint32_t Load$$DATA$$Base;
extern uint32_t Image$$DATA$$Base;
extern uint32_t Image$$DATA$$Length;
extern uint32_t Image$$STACK$$ZI$$Base;
extern uint32_t Image$$STACK$$ZI$$Length;
#elif defined(__GNUC__)
/* Generated by linker. */
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackLimit;
extern uint32_t __StackTop;
#elif defined(__ICCARM__)
#pragma section=".bss"
#pragma section=".data"
#pragma section=".data_init"
#pragma section=".stack"
#endif
/* Initialize static constructors */
#if defined(__ARMCC_VERSION)
extern void (* Image$$INIT_ARRAY$$Base[])(void);
extern void (* Image$$INIT_ARRAY$$Limit[])(void);
#elif defined(__GNUC__)
extern void (* __init_array_start[])(void);
extern void (* __init_array_end[])(void);
#elif defined(__ICCARM__)
extern void __call_ctors(void const *, void const *);
#pragma section = "SHT$$PREINIT_ARRAY" const
#pragma section = "SHT$$INIT_ARRAY" const
#endif
extern void * __Vectors[];
extern void R_BSP_SecurityInit(void);
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#if BSP_FEATURE_BSP_RESET_TRNG
static void bsp_reset_trng_circuit(void);
#endif
#if defined(__ICCARM__)
void R_BSP_WarmStart(bsp_warm_start_event_t event);
#pragma weak R_BSP_WarmStart
#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
#endif
/*******************************************************************************************************************//**
* Initialize the MCU and the runtime environment.
**********************************************************************************************************************/
void SystemInit (void)
{
#if __FPU_USED
/* Enable the FPU only when it is used.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */
/* Set bits 20-23 (CP10 and CP11) to enable FPU. */
SCB->CPACR = (uint32_t) CP_MASK;
#endif
#if BSP_TZ_SECURE_BUILD
/* Seal the main stack for secure projects. Reference:
* https://developer.arm.com/documentation/100720/0300
* https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */
uint32_t * p_main_stack = (uint32_t *) __Vectors[0];
p_main_stack[BSP_CFG_STACK_MAIN_BYTES / sizeof(uint32_t)] = BSP_TZ_STACK_SEAL_VALUE;
#endif
#if !BSP_TZ_NONSECURE_BUILD
/* VTOR is in undefined state out of RESET:
* https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en.
* Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure
* projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if !BSP_TZ_CFG_SKIP_INIT
#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP
/* Unlock VBTCR1 register. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
/* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1
* "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual
* R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot
* be accessed until VBTSR.VBTRVLD is set. */
R_SYSTEM->VBTCR1 = 1U;
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U);
/* Lock VBTCR1 register. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
#endif
#endif
/* Call pre clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_RESET);
#if BSP_TZ_CFG_SKIP_INIT
/* Initialize clock variables to be used with R_BSP_SoftwareDelay. */
bsp_clock_freq_var_init();
#else
/* Configure system clocks. */
bsp_clock_init();
#if BSP_FEATURE_BSP_RESET_TRNG
/* To prevent an undesired current draw, this MCU requires a reset
* of the TRNG circuit after the clocks are initialized */
bsp_reset_trng_circuit();
#endif
#endif
/* Call post clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
#if BSP_FEATURE_BSP_HAS_SP_MON
/* Disable MSP monitoring */
R_MPU_SPMON->SP[0].CTL = 0;
/* Setup NMI interrupt */
R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION;
/* Setup start address */
R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT;
/* Setup end address */
R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP;
/* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need
* to read-modify-write. */
R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk;
/* Enable MSP monitoring */
R_MPU_SPMON->SP[0].CTL = 1U;
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE
/* Use CM33 stack monitor. */
__set_MSPLIM(BSP_PRV_STACK_LIMIT);
#endif
#if BSP_CFG_C_RUNTIME_INIT
/* Initialize C runtime environment. */
/* Zero out BSS */
#if defined(__ARMCC_VERSION)
memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length);
#elif defined(__GNUC__)
memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__));
#elif defined(__ICCARM__)
memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss"));
#endif
/* Copy initialized RAM data from ROM to RAM. */
#if defined(__ARMCC_VERSION)
memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);
#elif defined(__GNUC__)
memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));
#elif defined(__ICCARM__)
memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),
(uint32_t) __section_size(".data"));
/* Copy functions to be executed from RAM. */
#pragma section=".code_in_ram"
#pragma section=".code_in_ram_init"
memcpy((uint32_t *) __section_begin(".code_in_ram"),
(uint32_t *) __section_begin(".code_in_ram_init"),
(uint32_t) __section_size(".code_in_ram"));
/* Copy main thread TLS to RAM. */
#pragma section="__DLIB_PERTHREAD_init"
#pragma section="__DLIB_PERTHREAD"
memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
(uint32_t) __section_size("__DLIB_PERTHREAD_init"));
#endif
/* Initialize static constructors */
#if defined(__ARMCC_VERSION)
int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base;
for (int32_t i = 0; i < count; i++)
{
void (* p_init_func)(void) =
(void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);
p_init_func();
}
#elif defined(__GNUC__)
int32_t count = __init_array_end - __init_array_start;
for (int32_t i = 0; i < count; i++)
{
__init_array_start[i]();
}
#elif defined(__ICCARM__)
void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
void const * ilimit = __section_end("SHT$$INIT_ARRAY");
__call_ctors(pibase, ilimit);
#endif
#endif // BSP_CFG_C_RUNTIME_INIT
/* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate();
#if !BSP_CFG_PFS_PROTECT
#if BSP_TZ_SECURE_BUILD
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else
R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#endif
#endif
#if FSP_PRIV_TZ_USE_SECURE_REGS
/* Ensure that the PMSAR registers are reset (Soft reset does not reset PMSAR). */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
for (uint32_t i = 0; i < 9; i++)
{
R_PMISC->PMSAR[i].PMSAR = UINT16_MAX;
}
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
#if BSP_TZ_SECURE_BUILD
/* Initialize security features. */
R_BSP_SecurityInit();
#endif
/* Call Post C runtime initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_C);
/* Initialize ELC events that will be used to trigger NVIC interrupts. */
bsp_irq_cfg();
/* Call any BSP specific code. No arguments are needed so NULL is sent. */
bsp_init(NULL);
}
/*******************************************************************************************************************//**
* This function is called at various points during the startup process.
* This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
* implemented version. One of the main uses for this function is to call functional safety code during the startup
* process. To use this function just copy this function into your own code and modify it to meet your needs.
*
* @param[in] event Where the code currently is in the start up process
**********************************************************************************************************************/
void R_BSP_WarmStart (bsp_warm_start_event_t event)
{
if (BSP_WARM_START_RESET == event)
{
/* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */
}
if (BSP_WARM_START_POST_CLOCK == event)
{
/* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */
}
else if (BSP_WARM_START_POST_C == event)
{
/* C runtime environment, system clocks, and pins are all setup. */
}
else
{
/* Do nothing */
}
}
/*******************************************************************************************************************//**
* Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module
* is not in use.
**********************************************************************************************************************/
#if BSP_FEATURE_BSP_RESET_TRNG
static void bsp_reset_trng_circuit (void)
{
volatile uint8_t read_port = 0U;
FSP_PARAMETER_NOT_USED(read_port); /// Prevent compiler 'unused' warning
/* Release register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
* of initial setting flow for an unused circuit") */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
/* Enable TRNG function (disable stop function) */
#if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
R_BSP_MODULE_START(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series.
#elif BSP_FEATURE_BSP_HAS_SCE5
R_BSP_MODULE_START(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series.
#else
#error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
#endif
/* Wait for at least 3 PCLKB cycles */
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
/* Disable TRNG function */
#if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); ///< TRNG Module Stop needs to be started/stopped for RA2 series.
#elif BSP_FEATURE_BSP_HAS_SCE5
R_BSP_MODULE_STOP(FSP_IP_SCE, 0); ///< TRNG Module Stop needs to be started/stopped for RA4 series.
#else
#error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
#endif
/* Reapply register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
* of initial setting flow for an unused circuit") */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_CLOCKS_H
#define BSP_CLOCKS_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_clock_cfg.h"
#include "bsp_api.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */
/* Must match SCKCR.CKSEL values. */
#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator.
#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator.
#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator.
#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator.
#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator.
#define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator.
#define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator.
/* PLLs are not supported in the following scenarios:
* - When using low voltage mode
* - When using an MCU that does not have a PLL
* - When the PLL only accepts the main oscillator as a source and XTAL is not used
*/
#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \
!((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED)
#define BSP_PRV_PLL_SUPPORTED (1)
#if BSP_FEATURE_CGC_HAS_PLL2
#define BSP_PRV_PLL2_SUPPORTED (1)
#else
#define BSP_PRV_PLL2_SUPPORTED (0)
#endif
#else
#define BSP_PRV_PLL_SUPPORTED (0)
#define BSP_PRV_PLL2_SUPPORTED (0)
#endif
/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency
* calculated here is also used to initialize the g_clock_freq array. */
#if BSP_PRV_PLL_SUPPORTED
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE)
#define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
#else
#define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#endif
#endif
#if BSP_PRV_PLL2_SUPPORTED
#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE
#define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
#else
#define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#endif
#endif
/* Frequencies of clocks with fixed freqencies. */
#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz
#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz
#define BSP_MOCO_FREQ_HZ (8000000U) // MOCO frequency is fixed at 8 MHz
#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE
#define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE
#define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE
#define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE
#define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE
#define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE
#if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE)
#if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE
#define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE
#define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ)
#endif
#define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \
(BSP_CFG_PLL_DIV + 1U))
#elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE)
#define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ)
#define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \
(BSP_CFG_PLL_DIV))
#endif
#endif
/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have
* not changed since startup. These macros are not used in FSP modules except for the clock startup code. */
#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_ICLK_DIV)
#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV)
#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV)
#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKC_DIV)
#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV)
#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_BCLK_DIV)
#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_FCLK_DIV)
/* System clock divider options. */
#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1.
#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2.
#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4.
#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8.
#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16.
#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32.
#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64.
#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only).
/* USB clock divider options. */
#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3
#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4
#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5
/* OCTA clock divider options. */
#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1
#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2
#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4
#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6
#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8
/* PLL divider options. */
#define BSP_CLOCKS_PLL_DIV_1 (0)
#define BSP_CLOCKS_PLL_DIV_2 (1)
#define BSP_CLOCKS_PLL_DIV_3 (2)
#define BSP_CLOCKS_PLL_DIV_4 (2)
/* PLL multiplier options. */
#define BSP_CLOCKS_PLL_MUL_8_0 (0xF)
#define BSP_CLOCKS_PLL_MUL_9_0 (0x11)
#define BSP_CLOCKS_PLL_MUL_10_0 (0x13)
#define BSP_CLOCKS_PLL_MUL_10_5 (0x14)
#define BSP_CLOCKS_PLL_MUL_11_0 (0x15)
#define BSP_CLOCKS_PLL_MUL_11_5 (0x16)
#define BSP_CLOCKS_PLL_MUL_12_0 (0x17)
#define BSP_CLOCKS_PLL_MUL_12_5 (0x18)
#define BSP_CLOCKS_PLL_MUL_13_0 (0x19)
#define BSP_CLOCKS_PLL_MUL_13_5 (0x1A)
#define BSP_CLOCKS_PLL_MUL_14_0 (0x1B)
#define BSP_CLOCKS_PLL_MUL_14_5 (0x1c)
#define BSP_CLOCKS_PLL_MUL_15_0 (0x1d)
#define BSP_CLOCKS_PLL_MUL_15_5 (0x1e)
#define BSP_CLOCKS_PLL_MUL_16_0 (0x1f)
#define BSP_CLOCKS_PLL_MUL_16_5 (0x20)
#define BSP_CLOCKS_PLL_MUL_17_0 (0x21)
#define BSP_CLOCKS_PLL_MUL_17_5 (0x22)
#define BSP_CLOCKS_PLL_MUL_18_0 (0x23)
#define BSP_CLOCKS_PLL_MUL_18_5 (0x24)
#define BSP_CLOCKS_PLL_MUL_19_0 (0x25)
#define BSP_CLOCKS_PLL_MUL_19_5 (0x26)
#define BSP_CLOCKS_PLL_MUL_20_0 (0x27)
#define BSP_CLOCKS_PLL_MUL_20_5 (0x28)
#define BSP_CLOCKS_PLL_MUL_21_0 (0x29)
#define BSP_CLOCKS_PLL_MUL_21_5 (0x2A)
#define BSP_CLOCKS_PLL_MUL_22_0 (0x2B)
#define BSP_CLOCKS_PLL_MUL_22_5 (0x2c)
#define BSP_CLOCKS_PLL_MUL_23_0 (0x2d)
#define BSP_CLOCKS_PLL_MUL_23_5 (0x2e)
#define BSP_CLOCKS_PLL_MUL_24_0 (0x2f)
#define BSP_CLOCKS_PLL_MUL_24_5 (0x30)
#define BSP_CLOCKS_PLL_MUL_25_0 (0x31)
#define BSP_CLOCKS_PLL_MUL_25_5 (0x32)
#define BSP_CLOCKS_PLL_MUL_26_0 (0x33)
#define BSP_CLOCKS_PLL_MUL_26_5 (0x34)
#define BSP_CLOCKS_PLL_MUL_27_0 (0x35)
#define BSP_CLOCKS_PLL_MUL_27_5 (0x36)
#define BSP_CLOCKS_PLL_MUL_28_0 (0x37)
#define BSP_CLOCKS_PLL_MUL_28_5 (0x38)
#define BSP_CLOCKS_PLL_MUL_29_0 (0x39)
#define BSP_CLOCKS_PLL_MUL_29_5 (0x3A)
#define BSP_CLOCKS_PLL_MUL_30_0 (0x3B)
#define BSP_CLOCKS_PLL_MUL_31_0 (0x3D)
/* Configuration option used to disable clock output. */
#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU)
/* HOCO cycles per microsecond. */
#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U)
/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */
#if BSP_HOCO_HZ < 48000000U
#define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US)
#else
#define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U)
#endif
/* Create a mask of valid bits in SCKDIVCR. */
#define BSP_PRV_SCKDIVCR_ICLK_MASK (7U << 24)
#if BSP_FEATURE_CGC_HAS_PCLKD
#define BSP_PRV_SCKDIVCR_PCLKD_MASK (7U << 0)
#else
#define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKC
#define BSP_PRV_SCKDIVCR_PCLKC_MASK (7U << 4)
#else
#define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKB
#define BSP_PRV_SCKDIVCR_PCLKB_MASK (7U << 8)
#else
#define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_PCLKA
#define BSP_PRV_SCKDIVCR_PCLKA_MASK (7U << 12)
#else
#define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB
#define BSP_PRV_SCKDIVCR_BCLK_MASK (7U << 16)
#else
#define BSP_PRV_SCKDIVCR_BCLK_MASK (0U)
#endif
#if BSP_FEATURE_CGC_HAS_FCLK
#define BSP_PRV_SCKDIVCR_FCLK_MASK (7U << 28)
#else
#define BSP_PRV_SCKDIVCR_FCLK_MASK (0U)
#endif
#define BSP_PRV_SCKDIVCR_MASK ((((((BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK) | \
BSP_PRV_SCKDIVCR_PCLKC_MASK) | BSP_PRV_SCKDIVCR_PCLKB_MASK) | \
BSP_PRV_SCKDIVCR_PCLKA_MASK) | \
BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK)
/* FLL is only used when enabled, present and the subclock is populated. */
#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED
#define BSP_PRV_HOCO_USE_FLL (1)
#ifndef BSP_PRV_FLL_STABILIZATION_TIME_US
#define BSP_PRV_FLL_STABILIZATION_TIME_US (1800)
#endif
#else
#define BSP_PRV_HOCO_USE_FLL (0)
#define BSP_PRV_FLL_STABILIZATION_TIME_US (0)
#endif
/* Operating power control modes. */
#define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed
#define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed
#define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage
#define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed
#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD
typedef struct
{
uint32_t pll_freq;
} bsp_clock_update_callback_args_t;
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t *
p_callback_args);
#elif defined(__GNUC__)
typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t *
p_callback_args);
#endif
#endif
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_clock_init(void); // Used internally by BSP
#if BSP_TZ_NONSECURE_BUILD
void bsp_clock_freq_var_init(void); // Used internally by BSP
#endif
#if BSP_TZ_SECURE_BUILD
void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback,
bsp_clock_update_callback_args_t * p_callback_memory);
#endif
/* Used internally by CGC */
#if !BSP_CFG_USE_LOW_VOLTAGE_MODE
void bsp_prv_operating_mode_set(uint8_t operating_mode);
#endif
#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED
uint32_t bsp_prv_power_change_mstp_set(void);
void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask);
#endif
void bsp_prv_prepare_pll(uint32_t pll_freq_hz);
void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
*
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ICCARM__)
#define WEAK_ERROR_ATTRIBUTE
#define WEAK_INIT_ATTRIBUTE
#pragma weak fsp_error_log = fsp_error_log_internal
#pragma weak bsp_init = bsp_init_internal
#elif defined(__GNUC__)
#define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal")))
#define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal")))
#endif
#define FSP_SECTION_VERSION ".version"
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/** Prototype of initialization function called before main. This prototype sets the weak association of this
* function to an internal example implementation. If this function is defined in the application code, the
* application code version is used. */
void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE;
void bsp_init_internal(void * p_args); /// Default initialization function
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This
* prototype sets the weak association of this function to an internal example implementation. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE;
void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function
#endif
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/* BSP version structure. */
const fsp_version_t g_bsp_version =
{
.api_version_minor = BSP_API_VERSION_MINOR,
.api_version_major = BSP_API_VERSION_MAJOR,
.code_version_major = BSP_CODE_VERSION_MAJOR,
.code_version_minor = BSP_CODE_VERSION_MINOR
};
/* FSP pack version structure. */
static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
{
.minor = FSP_VERSION_MINOR,
.major = FSP_VERSION_MAJOR,
.build = FSP_VERSION_BUILD,
.patch = FSP_VERSION_PATCH
};
/* Public FSP version name. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_STRING;
/* Unique FSP version ID. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_BUILD_STRING;
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/***********************************************************************************************************************
* DEPRECATED Get the BSP version based on compile time macros.
*
* @param[out] p_version Memory address to return version information to.
*
* @retval FSP_SUCCESS Version information stored.
* @retval FSP_ERR_ASSERTION The parameter p_version is NULL.
**********************************************************************************************************************/
fsp_err_t R_BSP_VersionGet (fsp_version_t * p_version)
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/** Verify parameters are valid */
FSP_ASSERT(NULL != p_version);
#endif
p_version->api_version_major = BSP_API_VERSION_MAJOR;
p_version->api_version_minor = BSP_API_VERSION_MINOR;
p_version->code_version_major = BSP_CODE_VERSION_MAJOR;
p_version->code_version_minor = BSP_CODE_VERSION_MINOR;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Get the FSP version based on compile time macros.
*
* @param[out] p_version Memory address to return version information to.
*
* @retval FSP_SUCCESS Version information stored.
* @retval FSP_ERR_ASSERTION The parameter p_version is NULL.
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version)
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/** Verify parameters are valid */
FSP_ASSERT(NULL != p_version);
#endif
*p_version = g_fsp_version;
return FSP_SUCCESS;
}
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/*******************************************************************************************************************//**
* Default error logger function, used only if fsp_error_log is not defined in the user application.
*
* @param[in] err The error code encountered.
* @param[in] file The file name in which the error code was encountered.
* @param[in] line The line number at which the error code was encountered.
**********************************************************************************************************************/
void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line)
{
/** Do nothing. Do not generate any 'unused' warnings. */
FSP_PARAMETER_NOT_USED(err);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
}
#endif
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* Default initialization function, used only if bsp_init is not defined in the user application.
**********************************************************************************************************************/
void bsp_init_internal (void * p_args)
{
/* Do nothing. */
FSP_PARAMETER_NOT_USED(p_args);
}
#if defined(__ARMCC_VERSION)
/*******************************************************************************************************************//**
* Default implementation of assert for AC6.
**********************************************************************************************************************/
__attribute__((weak, noreturn))
void __aeabi_assert (const char * expr, const char * file, int line) {
FSP_PARAMETER_NOT_USED(expr);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
__BKPT(0);
while (1)
{
/* Do nothing. */
}
}
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_COMMON_H
#define BSP_COMMON_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
#include <string.h>
/* Different compiler support. */
#include "../../inc/fsp_common_api.h"
#include "bsp_compiler_support.h"
#include "bsp_cfg.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** Used to signify that an ELC event is not able to be used as an interrupt. */
#define BSP_IRQ_DISABLED (0xFFU)
/* Version of this module's code and API. */
#define BSP_CODE_VERSION_MAJOR (1U)
#define BSP_CODE_VERSION_MINOR (2U)
#define BSP_API_VERSION_MAJOR (1U)
#define BSP_API_VERSION_MINOR (0U)
#define FSP_CONTEXT_SAVE
#define FSP_CONTEXT_RESTORE
/** Macro to log and return error without an assertion. */
#ifndef FSP_RETURN
#define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
return err;
#endif
/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
* user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
#if (1 == BSP_CFG_ERROR_LOG)
#ifndef FSP_ERROR_LOG
#define FSP_ERROR_LOG(err) \
fsp_error_log((err), __FILE__, __LINE__);
#endif
#else
#define FSP_ERROR_LOG(err)
#endif
/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
* functions. */
#if (3 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a)
#elif (2 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a) {assert(a);}
#else
#define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
#endif // ifndef FSP_ASSERT
/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
* to identify runtime errors in FSP functions. */
#define FSP_ERROR_RETURN(a, err) \
{ \
if ((a)) \
{ \
(void) 0; /* Do nothing */ \
} \
else \
{ \
FSP_ERROR_LOG(err); \
return err; \
} \
}
/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
* This macro can be redefined to add a timeout if necessary. */
#ifndef FSP_HARDWARE_REGISTER_WAIT
#define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
#endif
/** Version data structure used by error logger macro. */
extern const fsp_version_t g_bsp_version;
/****************************************************************
*
* This check is performed to select suitable ASM API with respect to core
*
* The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so
* the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */
#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \
defined(__ARM_ARCH_7EM__) // CM4
#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
#else // CM23
#ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#endif
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
/* This macro defines a variable for saving previous mask value */
#ifndef FSP_CRITICAL_SECTION_DEFINE
#define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U
#endif
/* These macros abstract methods to save and restore the interrupt state for different architectures. */
#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION)
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK
#define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U)
#else
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI
#define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
(8U - __NVIC_PRIO_BITS)))
#endif
/** This macro temporarily saves the current interrupt state and disables interrupts. */
#ifndef FSP_CRITICAL_SECTION_ENTER
#define FSP_CRITICAL_SECTION_ENTER \
old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
#endif
/** This macro restores the previously saved interrupt state, reenabling interrupts. */
#ifndef FSP_CRITICAL_SECTION_EXIT
#define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
#endif
/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */
#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U)
/** Used to signify that the requested IRQ vector is not defined in this system. */
#define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
/* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */
#define FSP_PRIV_SCKDIVCR_DIV_MASK (7)
/* Use the secure registers for secure projects and flat projects. */
#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
#define FSP_PRIV_TZ_USE_SECURE_REGS (1)
#else
#define FSP_PRIV_TZ_USE_SECURE_REGS (0)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Different warm start entry locations in the BSP. */
typedef enum e_bsp_warm_start_event
{
BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up
} bsp_warm_start_event_t;
/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */
typedef enum e_fsp_priv_clock
{
FSP_PRIV_CLOCK_PCLKD = 0,
FSP_PRIV_CLOCK_PCLKC = 4,
FSP_PRIV_CLOCK_PCLKB = 8,
FSP_PRIV_CLOCK_PCLKA = 12,
FSP_PRIV_CLOCK_BCLK = 16,
FSP_PRIV_CLOCK_ICLK = 24,
FSP_PRIV_CLOCK_FCLK = 28,
} fsp_priv_clock_t;
typedef struct st_bsp_unique_id
{
union
{
uint32_t unique_id_words[4];
uint8_t unique_id_bytes[16];
};
} bsp_unique_id_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Global variables (defined in other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Return active interrupt vector number value
*
* @return Active interrupt vector number value
**********************************************************************************************************************/
__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
{
xPSR_Type xpsr_value;
xpsr_value.w = __get_xPSR();
return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS);
}
/*******************************************************************************************************************//**
* Gets the frequency of a system clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
{
uint32_t sckdivcr = R_SYSTEM->SCKDIVCR;
uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK;
uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK;
return (SystemCoreClock << iclk_div) >> clock_div;
}
/*******************************************************************************************************************//**
* Get unique ID for this device.
*
* @return A pointer to the unique identifier structure
**********************************************************************************************************************/
__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet ()
{
return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
}
/*******************************************************************************************************************//**
* Disables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheDisable ()
{
R_FCACHE->FCACHEE = 0U;
#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
/* Disable the C-Cache. */
R_CACHE->CCACTL = 0U;
#endif
}
/*******************************************************************************************************************//**
* Enables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheEnable ()
{
/* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache
* in the RA6M3 manual R01UH0878EJ0100). */
R_FCACHE->FCACHEIV = 1U;
FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
/* Enable flash cache. */
R_FCACHE->FCACHEE = 1U;
#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE
/* Configure the C-Cache line size. */
R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE;
/* Enable the C-Cache. */
R_CACHE->CCACTL = 1U;
#endif
}
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT))
/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
#endif
/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
* alert the user of the error. The user can override this default behavior by defining their own
* BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
*/
#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
#endif
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
#ifndef BSP_COMPILER_SUPPORT_H
#define BSP_COMPILER_SUPPORT_H
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
#include "arm_cmse.h"
#endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ARMCC_VERSION) /* AC6 compiler */
/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load
* memory (ROM) is reserved unnecessarily. */
#define BSP_UNINIT_SECTION_PREFIX ".bss"
#define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__GNUC__) /* GCC compiler */
#define BSP_UNINIT_SECTION_PREFIX
#define BSP_SECTION_HEAP ".heap"
#define BSP_DONT_REMOVE
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__ICCARM__) /* IAR compiler */
#define BSP_UNINIT_SECTION_PREFIX
#define BSP_SECTION_HEAP "HEAP"
#define BSP_DONT_REMOVE __root
#define BSP_ATTRIBUTE_STACKLESS __stackless
#define BSP_FORCE_INLINE _Pragma("inline=forced")
#endif
#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack"
#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
#define BSP_SECTION_ROM_REGISTERS ".rom_registers"
#define BSP_SECTION_ID_CODE ".id_code"
/* Compiler neutral macros. */
#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
#define BSP_PACKED __attribute__((aligned(1)))
#define BSP_WEAK_REFERENCE __attribute__((weak))
/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
#define BSP_STACK_ALIGNMENT (8)
/***********************************************************************************************************************
* TrustZone definitions
**********************************************************************************************************************/
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__)
#if defined(__ICCARM__) /* IAR compiler */
#define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call
#define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry
#else
#define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call))
#define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
#endif
#else
#define BSP_CMSE_NONSECURE_CALL
#define BSP_CMSE_NONSECURE_ENTRY
#endif
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end of addtogroup BSP_MCU) */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#include "bsp_delay.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_DELAY_NS_PER_SECOND (1000000000)
#define BSP_DELAY_NS_PER_US (1000)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Delay for at least the specified duration in units and return.
* @param[in] delay The number of 'units' to delay.
* @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are:
* BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n
* For example:@n
* At 1 MHz one cycle takes 1 microsecond (.000001 seconds).@n
* At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.@n
* Therefore one run through bsp_prv_software_delay_loop() takes:
* ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns.
* A delay of 2 us therefore requires 2000ns/332ns or 6 loops.
*
* The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate.
* @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds.
* @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds
*
* Note that requests for very large delays will be affected by rounding in the calculations and the actual delay
* achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds.
*
* Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called
* at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the
* overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
*
*
* @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires
* that the BSP has already initialized the CGC (which it does as part of the Sysinit).
* Care should be taken to ensure this remains the case if in the future this function were to be called as part
* of the BSP initialization.
**********************************************************************************************************************/
void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
{
uint32_t iclk_hz;
uint32_t cycles_requested;
uint32_t ns_per_cycle;
uint32_t loops_required = 0;
uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */
uint64_t ns_64bits;
iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */
/* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution
* loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting
* to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single
* pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request
* will generate a minimum delay of ~200 us.*/
ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */
/* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */
/* division as that pulls in a division library. */
ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
/* Have we overflowed 32 bits? */
if (ns_64bits <= UINT32_MAX)
{
/* No, we will not overflow. */
cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle);
loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES;
}
else
{
/* We did overflow. Try dividing down first. */
total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES));
ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns.
/* Have we overflowed 32 bits? */
if (ns_64bits <= UINT32_MAX)
{
/* No, we will not overflow. */
loops_required = (uint32_t) ns_64bits;
}
else
{
/* We still overflowed, use the max count for cycles */
loops_required = UINT32_MAX;
}
}
/** Only delay if the supplied parameters constitute a delay. */
if (loops_required > (uint32_t) 0)
{
bsp_prv_software_delay_loop(loops_required);
}
}
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
* occur when the loop exits. The 'naked' attribute indicates that the specified function does not need
* prologue/epilogue sequences generated by the compiler.
* @param[in] loop_cnt The number of loops to iterate.
**********************************************************************************************************************/
BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
{
__asm volatile ("sw_delay_loop: \n"
#if defined(__ICCARM__) || defined(__ARMCC_VERSION)
" subs r0, #1 \n" ///< 1 cycle
#elif defined(__GNUC__)
" sub r0, r0, #1 \n" ///< 1 cycle
#endif
" cmp r0, #0 \n" ///< 1 cycle
/* CM0 and CM23 have a different instruction set */
#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
" bne sw_delay_loop \n" ///< 2 cycles
#else
" bne.n sw_delay_loop \n" ///< 2 cycles
#endif
" bx lr \n"); ///< 2 cycles
}

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_DELAY_H
#define BSP_DELAY_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "bsp_compiler_support.h"
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* The number of cycles required per software delay loop. */
#ifndef BSP_DELAY_LOOP_CYCLES
#define BSP_DELAY_LOOP_CYCLES (4)
#endif
/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle
* count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures
* the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count
* of 0. */
#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U)
/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */
typedef enum
{
BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds
BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds
BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds
} bsp_delay_units_t;
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_GRP_IRQ_TOTAL_ITEMS (16U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** This array holds callback functions. */
static bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_GRP_IRQ_TOTAL_ITEMS] = {0};
void NMI_Handler(void);
static void bsp_group_irq_call(bsp_grp_irq_t irq);
/*******************************************************************************************************************//**
* Calls the callback function for an interrupt if a callback has been registered.
*
* @param[in] irq Which interrupt to check and possibly call.
*
* @retval FSP_SUCCESS Callback was called.
* @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source.
*
* @warning This function is called from within an interrupt
**********************************************************************************************************************/
static void bsp_group_irq_call (bsp_grp_irq_t irq)
{
/** Check for valid callback */
if (NULL != g_bsp_group_irq_sources[irq])
{
/** Callback has been found. Call it. */
g_bsp_group_irq_sources[irq](irq);
}
}
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Register a callback function for supported interrupts. If NULL is passed for the callback argument then any
* previously registered callbacks are unregistered.
*
* @param[in] irq Interrupt for which to register a callback.
* @param[in] p_callback Pointer to function to call when interrupt occurs.
*
* @retval FSP_SUCCESS Callback registered
* @retval FSP_ERR_ASSERTION Callback pointer is NULL
**********************************************************************************************************************/
fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq))
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/* Check pointer for NULL value. */
FSP_ASSERT(p_callback);
#endif
/* Register callback. */
g_bsp_group_irq_sources[irq] = p_callback;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because
* there are many sources that map to the NMI exception.
**********************************************************************************************************************/
void NMI_Handler (void)
{
uint16_t nmisr = R_ICU->NMISR;
/* Loop over all NMI status flags */
for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= BSP_GRP_IRQ_CACHE_PARITY; irq++)
{
/* If the current irq status register is set call the irq callback. */
if (0U != (nmisr & (1U << irq)))
{
(void) bsp_group_irq_call(irq);
}
}
/* Clear status flags that have been handled. */
R_ICU->NMICLR = nmisr;
}
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_GROUP_IRQ_H
#define BSP_GROUP_IRQ_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Which interrupts can have callbacks registered. */
typedef enum e_bsp_grp_irq
{
BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred
BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred
BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt
BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt
BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt
BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected
BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt
BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error
BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error
BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error
BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error
BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error
BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error
BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error
} bsp_grp_irq_t;
/* Callback type. */
typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq);
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_group_interrupt_open(void); // Used internally by BSP
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#include "bsp_guard.h"
/* Only the secure project has nonsecure callable functions. */
#if BSP_TZ_SECURE_BUILD
/* If the CGG Security Attribution is configured to secure access only. */
#if BSP_TZ_CFG_CGFSAR != 0xFFFFFFFFU
/*******************************************************************************************************************//**
* Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed.
*
* @retval FSP_SUCCESS Callback set.
* @retval FSP_ERR_ASSERTION An input parameter is invalid.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet (bsp_clock_update_callback_t p_callback,
bsp_clock_update_callback_args_t * p_callback_memory)
{
bsp_clock_update_callback_t p_callback_checked =
(bsp_clock_update_callback_t) cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE);
bsp_clock_update_callback_args_t * p_callback_memory_checked =
(bsp_clock_update_callback_args_t *) cmse_check_address_range(p_callback_memory,
sizeof(bsp_clock_update_callback_args_t),
CMSE_AU_NONSECURE);
FSP_ASSERT(p_callback == p_callback_checked);
FSP_ASSERT(p_callback_memory == p_callback_memory_checked);
r_bsp_clock_update_callback_set(p_callback_checked, p_callback_memory_checked);
return FSP_SUCCESS;
}
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_GUARD_H
#define BSP_GUARD_H
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD
BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet(bsp_clock_update_callback_t p_callback,
bsp_clock_update_callback_args_t * p_callback_memory);
#endif
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
volatile uint32_t g_protect_pfswe_counter;
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @defgroup BSP_IO BSP I/O access
* @ingroup RENESAS_COMMON
* @brief This module provides basic read/write access to port pins.
*
* @{
**********************************************************************************************************************/
#ifndef BSP_IO_H
#define BSP_IO_H
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Private definition to set enumeration values. */
#define BSP_IO_PRV_PFS_PSEL_OFFSET (24)
#define BSP_IO_PRV_8BIT_MASK (0xFF)
#define BSP_IO_PWPR_B0WI_OFFSET (7U)
#define BSP_IO_PWPR_PFSWE_OFFSET (6U)
#define BSP_IO_PFS_PDR_OUTPUT (4U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Levels that can be set and read for individual pins */
typedef enum e_bsp_io_level
{
BSP_IO_LEVEL_LOW = 0, ///< Low
BSP_IO_LEVEL_HIGH ///< High
} bsp_io_level_t;
/** Direction of individual pins */
typedef enum e_bsp_io_dir
{
BSP_IO_DIRECTION_INPUT = 0, ///< Input
BSP_IO_DIRECTION_OUTPUT ///< Output
} bsp_io_direction_t;
/** Superset list of all possible IO ports. */
typedef enum e_bsp_io_port
{
BSP_IO_PORT_00 = 0x0000, ///< IO port 0
BSP_IO_PORT_01 = 0x0100, ///< IO port 1
BSP_IO_PORT_02 = 0x0200, ///< IO port 2
BSP_IO_PORT_03 = 0x0300, ///< IO port 3
BSP_IO_PORT_04 = 0x0400, ///< IO port 4
BSP_IO_PORT_05 = 0x0500, ///< IO port 5
BSP_IO_PORT_06 = 0x0600, ///< IO port 6
BSP_IO_PORT_07 = 0x0700, ///< IO port 7
BSP_IO_PORT_08 = 0x0800, ///< IO port 8
BSP_IO_PORT_09 = 0x0900, ///< IO port 9
BSP_IO_PORT_10 = 0x0A00, ///< IO port 10
BSP_IO_PORT_11 = 0x0B00, ///< IO port 11
} bsp_io_port_t;
/** Superset list of all possible IO port pins. */
typedef enum e_bsp_io_port_pin_t
{
BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2
BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3
BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4
BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5
BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6
BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7
BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8
BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9
BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10
BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11
BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12
BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13
BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14
BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15
BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2
BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3
BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4
BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5
BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6
BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7
BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8
BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9
BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10
BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11
BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12
BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13
BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14
BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15
BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2
BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3
BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4
BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5
BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6
BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7
BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8
BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9
BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10
BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11
BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12
BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13
BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14
BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15
BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2
BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3
BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4
BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5
BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6
BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7
BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8
BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9
BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10
BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11
BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12
BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13
BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14
BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15
BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2
BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3
BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4
BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5
BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6
BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7
BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8
BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9
BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10
BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11
BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12
BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13
BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14
BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15
BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3
BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4
BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5
BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6
BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7
BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8
BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9
BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10
BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11
BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12
BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13
BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14
BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15
BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2
BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3
BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4
BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5
BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6
BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7
BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8
BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9
BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10
BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11
BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12
BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13
BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14
BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15
BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3
BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4
BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5
BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6
BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7
BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8
BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9
BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10
BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11
BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12
BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13
BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14
BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15
BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3
BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4
BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5
BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6
BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7
BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8
BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9
BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10
BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11
BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12
BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13
BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14
BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15
BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2
BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3
BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4
BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5
BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6
BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7
BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8
BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9
BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10
BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11
BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12
BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13
BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14
BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15
BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2
BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3
BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4
BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5
BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6
BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7
BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8
BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9
BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10
BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11
BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12
BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13
BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14
BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15
BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2
BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3
BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4
BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5
BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6
BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7
BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8
BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9
BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10
BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11
BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12
BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
} bsp_io_port_pin_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
extern volatile uint32_t g_protect_pfswe_counter;
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Read the current input level of the pin.
*
* @param[in] pin The pin
*
* @retval Current input level
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin)
{
/* Read pin level. */
return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR;
}
/*******************************************************************************************************************//**
* Set a pin to output and set the output level to the level provided
*
* @param[in] pin The pin
* @param[in] level The level
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level)
{
/* Set output level and pin direction to output. */
uint32_t lvl = (uint32_t) level;
R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = BSP_IO_PFS_PDR_OUTPUT | lvl;
}
/*******************************************************************************************************************//**
* Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur
* via multiple threads or an ISR re-entering this code.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinAccessEnable (void)
{
#if BSP_CFG_PFS_PROTECT
/** Get the current state of interrupts */
FSP_CRITICAL_SECTION_DEFINE;
FSP_CRITICAL_SECTION_ENTER;
/** If this is first entry then allow writing of PFS. */
if (0 == g_protect_pfswe_counter)
{
#if BSP_TZ_SECURE_BUILD
R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#else
R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
#endif
}
/** Increment the protect counter */
g_protect_pfswe_counter++;
/** Restore the interrupt state */
FSP_CRITICAL_SECTION_EXIT;
#endif
}
/*******************************************************************************************************************//**
* Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via
* multiple threads or an ISR re-entering this code.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_PinAccessDisable (void)
{
#if BSP_CFG_PFS_PROTECT
/** Get the current state of interrupts */
FSP_CRITICAL_SECTION_DEFINE;
FSP_CRITICAL_SECTION_ENTER;
/** Is it safe to disable PFS register? */
if (0 != g_protect_pfswe_counter)
{
/* Decrement the protect counter */
g_protect_pfswe_counter--;
}
/** Is it safe to disable writing of PFS? */
if (0 == g_protect_pfswe_counter)
{
#if BSP_TZ_SECURE_BUILD
R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled
#else
R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled
R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled
#endif
}
/** Restore the interrupt state */
FSP_CRITICAL_SECTION_EXIT;
#endif
}
/** @} (end addtogroup BSP_IO) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

112
board/Renesas_ra6m4/ra/fsp/src/bsp/mcu/all/bsp_irq.c Normal file
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@@ -0,0 +1,112 @@
/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/** ELC event definitions. */
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU)
#define BSP_PRV_BITS_PER_WORD (32)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/* This table is used to store the context in the ISR. */
void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE =
{
(bsp_interrupt_event_t) 0
};
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* Using the vector table information section that has been built by the linker and placed into ROM in the
* .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts
* in the NVIC.
*
**********************************************************************************************************************/
void bsp_irq_cfg (void)
{
#if FSP_PRIV_TZ_USE_SECURE_REGS
/* Unprotect security registers. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
#if !BSP_TZ_SECURE_BUILD
/* Set the DMAC channels to secure access. */
R_CPSCU->ICUSARC = ~R_CPSCU_ICUSARC_SADMACn_Msk;
#endif
/* Place all vectors in non-secure state unless they are used in the secure project. */
uint32_t interrupt_security_state[BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD];
memset(&interrupt_security_state, UINT8_MAX, sizeof(interrupt_security_state));
for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++)
{
if (0U != g_interrupt_event_link_select[i])
{
/* This is a secure vector. Clear the associated bit. */
uint32_t index = i / BSP_PRV_BITS_PER_WORD;
uint32_t bit = i % BSP_PRV_BITS_PER_WORD;
interrupt_security_state[index] &= ~(1U << bit);
}
}
/* The Secure Attribute managed within the ARM CPU NVIC must match the security attribution of IELSEn
* (Reference section 13.2.9 in the RA6M4 manual R01UH0890EJ0050). */
uint32_t volatile * p_icusarg = &R_CPSCU->ICUSARG;
for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES / BSP_PRV_BITS_PER_WORD; i++)
{
p_icusarg[i] = interrupt_security_state[i];
NVIC->ITNS[i] = interrupt_security_state[i];
}
/* Protect security registers. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
for (uint32_t i = 0U; i < BSP_ICU_VECTOR_MAX_ENTRIES; i++)
{
R_ICU->IELSR[i] = (uint32_t) g_interrupt_event_link_select[i];
}
}

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/** @} (end addtogroup BSP_MCU) */
#ifndef BSP_IRQ_H
#define BSP_IRQ_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Sets the ISR context associated with the requested IRQ.
*
* @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
* function.
* @param[in] p_context ISR context for IRQ.
**********************************************************************************************************************/
__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
{
/* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
* being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
gp_renesas_isr_context[irq] = p_context;
}
/*******************************************************************************************************************//**
* Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit
* is set. If it is not cleared in the ISR then the interrupt will trigger again immediately.
*
* @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
{
/* Clear the IR bit in the selected IELSR register. */
R_ICU->IELSR_b[irq].IR = 0U;
}
/*******************************************************************************************************************//**
* Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt.
*
* @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
{
/* Clear the IR bit in the selected IELSR register. */
R_BSP_IrqStatusClear(irq);
/* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
* exceptions every time an interrupt is cleared in the NVIC. */
uint32_t _irq = (uint32_t) irq;
NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
}
/*******************************************************************************************************************//**
* Sets the interrupt priority and context.
*
* @param[in] irq The IRQ to configure.
* @param[in] priority NVIC priority of the interrupt
* @param[in] p_context The interrupt context is a pointer to data required in the ISR.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
{
/* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions
* every time a priority is configured in the NVIC. */
#if (4U == __CORTEX_M)
NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
#elif (33 == __CORTEX_M)
NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX);
#elif (23 == __CORTEX_M)
NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq)));
#else
NVIC_SetPriority(irq, priority);
#endif
/* Store the context. The context is recovered in the ISR. */
R_FSP_IsrContextSet(irq, p_context);
}
/*******************************************************************************************************************//**
* Enable the IRQ in the NVIC (Without clearing the pending bit).
*
* @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex
* Processor Exceptions Numbers.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
{
/* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
* every time an interrupt is enabled in the NVIC. */
uint32_t _irq = (uint32_t) irq;
NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
}
/*******************************************************************************************************************//**
* Clears pending interrupts in both ICU and NVIC, then enables the interrupt.
*
* @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed
* for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
{
/* Clear pending interrupts in the ICU and NVIC. */
R_BSP_IrqClearPending(irq);
/* Enable the IRQ in the NVIC. */
R_BSP_IrqEnableNoClear(irq);
}
/*******************************************************************************************************************//**
* Disables interrupts in the NVIC.
*
* @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are
* only those for the Cortex Processor Exceptions Numbers.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
{
/* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system
* exceptions every time an interrupt is cleared in the NVIC. */
uint32_t _irq = (uint32_t) irq;
NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
__DSB();
__ISB();
}
/*******************************************************************************************************************//**
* Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
*
* @param[in] irq Interrupt number.
* @param[in] priority NVIC priority of the interrupt
* @param[in] p_context The interrupt context is a pointer to data required in the ISR.
*
* @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
{
R_BSP_IrqCfg(irq, priority, p_context);
R_BSP_IrqEnable(irq);
}
/*******************************************************************************************************************//**
* @brief Finds the ISR context associated with the requested IRQ.
*
* @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
* function.
* @return ISR context for IRQ.
**********************************************************************************************************************/
__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
{
/* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
* being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
return gp_renesas_isr_context[irq];
}
/*******************************************************************************************************************//**
* @internal
* @addtogroup BSP_MCU_PRV Internal BSP Documentation
* @ingroup RENESAS_INTERNAL
* @{
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_irq_cfg(void); // Used internally by BSP
/** @} (end addtogroup BSP_MCU_PRV) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_MCU_API_H
#define BSP_MCU_API_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
typedef struct st_bsp_event_info
{
IRQn_Type irq;
elc_event_t event;
} bsp_event_info_t;
typedef enum e_bsp_clocks_octaclk_div
{
BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1
BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2
BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4
BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6
BSP_CLOCKS_OCTACLK_DIV_8 ///< Divide OCTA source clock by 8
} bsp_clocks_octaclk_div_t;
typedef enum e_bsp_clocks_source
{
BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator.
BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator.
BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator.
BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator.
BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator.
BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator.
BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator.
} bsp_clocks_source_t;
typedef struct st_bsp_octaclk_settings
{
bsp_clocks_source_t source_clock; ///< OCTACLK source clock
bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider
} bsp_octaclk_settings_t;
void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect);
void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect);
fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq));
void R_BSP_OctaclkUpdate(bsp_octaclk_settings_t * p_octaclk_setting);
void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units);
fsp_err_t R_BSP_VersionGet(fsp_version_t * p_version);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_MODULE_H
#define BSP_MODULE_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Cancels the module stop state.
*
* @param ip fsp_ip_t enum value for the module to be stopped
* @param channel The channel. Use channel 0 for modules without channels.
**********************************************************************************************************************/
#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \
BSP_MSTP_REG_ ## ip(channel); \
FSP_CRITICAL_SECTION_EXIT;}
/*******************************************************************************************************************//**
* Enables the module stop state.
*
* @param ip fsp_ip_t enum value for the module to be stopped
* @param channel The channel. Use channel 0 for modules without channels.
**********************************************************************************************************************/
#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \
FSP_CRITICAL_SECTION_ENTER; \
BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \
BSP_MSTP_REG_ ## ip(channel); \
FSP_CRITICAL_SECTION_EXIT;}
/** @} (end addtogroup BSP_MCU) */
#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \
channel) ? (1U << 5U) : (1U << 6U));
#define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel));
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U));
#else
#define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE
#define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel));
#define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE)
#define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \
channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U))));
#define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel));
#endif
#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_SYSTEM->MSTPCRA
#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U));
#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_SYSTEM->MSTPCRA
#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U));
#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel));
#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel));
#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel));
#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel));
#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel));
#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel));
#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel));
#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel));
#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel));
#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel));
#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB
#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel));
#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel));
#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel));
#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel));
#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel));
#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel));
#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel));
#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel));
#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel));
#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel));
#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel));
#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel));
#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel));
#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel));
#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel));
#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel));
#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC
#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel));
#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel));
#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel));
#define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U));
#define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U));
#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel));
#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel));
#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U);
#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD
#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel));
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** Used for holding reference counters for protection bits. */
static volatile uint16_t g_protect_counters[] =
{
0U, 0U, 0U, 0U
};
/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */
static const uint16_t g_prcr_masks[] =
{
0x0001U, /* PRC0. */
0x0002U, /* PRC1. */
0x0008U, /* PRC3. */
0x0010U, /* PRC4. */
};
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Enable register protection. Registers that are protected cannot be written to. Register protection is
* enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
*
* @param[in] regs_to_protect Registers which have write protection enabled.
**********************************************************************************************************************/
void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
{
/** Get/save the current state of interrupts */
FSP_CRITICAL_SECTION_DEFINE;
FSP_CRITICAL_SECTION_ENTER;
/* Is it safe to disable write access? */
if (0U != g_protect_counters[regs_to_protect])
{
/* Decrement the protect counter */
g_protect_counters[regs_to_protect]--;
}
/* Is it safe to disable write access? */
if (0U == g_protect_counters[regs_to_protect])
{
/** Enable protection using PRCR register. */
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect]));
}
/** Restore the interrupt state */
FSP_CRITICAL_SECTION_EXIT;
}
/*******************************************************************************************************************//**
* Disable register protection. Registers that are protected cannot be written to. Register protection is
* disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
*
* @param[in] regs_to_unprotect Registers which have write protection disabled.
**********************************************************************************************************************/
void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
{
/** Get/save the current state of interrupts */
FSP_CRITICAL_SECTION_DEFINE;
FSP_CRITICAL_SECTION_ENTER;
/* If this is first entry then disable protection. */
if (0U == g_protect_counters[regs_to_unprotect])
{
/** Disable protection using PRCR register. */
/** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to
* disable writes. */
R_SYSTEM->PRCR = ((R_SYSTEM->PRCR | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]);
}
/** Increment the protect counter */
g_protect_counters[regs_to_unprotect]++;
/** Restore the interrupt state */
FSP_CRITICAL_SECTION_EXIT;
}
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_REGISTER_PROTECTION_H
#define BSP_REGISTER_PROTECTION_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/** The different types of registers that can be protected. */
typedef enum e_bsp_reg_protect
{
/** Enables writing to the registers related to the clock generation circuit. */
BSP_REG_PROTECT_CGC = 0,
/** Enables writing to the registers related to operating modes, low power consumption, and battery backup
* function. */
BSP_REG_PROTECT_OM_LPC_BATT,
/** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0,
* LVD2CR1, LVD2SR. */
BSP_REG_PROTECT_LVD,
/** Enables writing to the registers related to the security function. */
BSP_REG_PROTECT_SAR,
} bsp_reg_protect_t;
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_register_protect_open(void); // Used internally by BSP
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define RA_NOT_DEFINED (0)
/** OR in the HOCO frequency setting from bsp_clock_cfg.h with the OFS1 setting from bsp_cfg.h. */
#define BSP_ROM_REG_OFS1_SETTING \
(((uint32_t) BSP_CFG_ROM_REG_OFS1 & BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK) | \
((uint32_t) BSP_CFG_HOCO_FREQUENCY << BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET))
/** Build up SECMPUAC register based on MPU settings. */
#define BSP_ROM_REG_MPU_CONTROL_SETTING \
((0xFFFFFCF0U) | \
((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_ENABLE << 8) | \
((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_ENABLE << 9) | \
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_ENABLE) | \
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_ENABLE << 1) | \
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_ENABLE << 2) | \
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_ENABLE << 3))
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#if 33U != __CORTEX_M // NOLINT(readability-magic-numbers)
/** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */
BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (BSP_SECTION_ROM_REGISTERS) =
{
(uint32_t) BSP_CFG_ROM_REG_OFS0,
(uint32_t) BSP_ROM_REG_OFS1_SETTING,
((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_START & 0xFFFFFFFCU),
((uint32_t) BSP_CFG_ROM_REG_MPU_PC0_END | 0x00000003U),
((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_START & 0xFFFFFFFCU),
((uint32_t) BSP_CFG_ROM_REG_MPU_PC1_END | 0x00000003U),
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_START & BSP_FEATURE_BSP_MPU_REGION0_MASK & 0xFFFFFFFCU),
(((uint32_t) BSP_CFG_ROM_REG_MPU_REGION0_END & BSP_FEATURE_BSP_MPU_REGION0_MASK) | 0x00000003U),
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_START & 0xFFFFFFFCU),
((uint32_t) BSP_CFG_ROM_REG_MPU_REGION1_END | 0x00000003U),
(((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_START & 0x407FFFFCU) | 0x40000000U),
(((uint32_t) BSP_CFG_ROM_REG_MPU_REGION2_END & 0x407FFFFCU) | 0x40000003U),
(((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_START & 0x407FFFFCU) | 0x40000000U),
(((uint32_t) BSP_CFG_ROM_REG_MPU_REGION3_END & 0x407FFFFCU) | 0x40000003U),
(uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING
};
/** ID code definitions defined here. */
BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) =
{
BSP_CFG_ID_CODE_LONG_1,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_2,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_3,
#if BSP_FEATURE_BSP_OSIS_PADDING
0xFFFFFFFFU,
#endif
BSP_CFG_ID_CODE_LONG_4
};
#else /* CM33 parts */
#if !BSP_TZ_NONSECURE_BUILD
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 =
BSP_CFG_ROM_REG_OFS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_dualsel") g_bsp_rom_dualsel =
BSP_CFG_ROM_REG_DUALSEL;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas =
0xFFFFFFFF;
#else
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1") g_bsp_rom_ofs1 =
BSP_ROM_REG_OFS1_SETTING;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel") g_bsp_rom_banksel =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps0") g_bsp_rom_bps0 =
BSP_CFG_ROM_REG_BPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps1") g_bsp_rom_bps1 =
BSP_CFG_ROM_REG_BPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps2") g_bsp_rom_bps2 =
BSP_CFG_ROM_REG_BPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps0") g_bsp_rom_pbps0 =
BSP_CFG_ROM_REG_PBPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps1") g_bsp_rom_pbps1 =
BSP_CFG_ROM_REG_PBPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps2") g_bsp_rom_pbps2 =
BSP_CFG_ROM_REG_PBPS2;
#endif
#if !BSP_TZ_NONSECURE_BUILD
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1_sec =
BSP_ROM_REG_OFS1_SETTING;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sec") g_bsp_rom_banksel_sec =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps_sec0 =
BSP_CFG_ROM_REG_BPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec1") g_bsp_rom_bps_sec1 =
BSP_CFG_ROM_REG_BPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec2") g_bsp_rom_bps_sec2 =
BSP_CFG_ROM_REG_BPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps_sec0 =
BSP_CFG_ROM_REG_PBPS0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec1") g_bsp_rom_pbps_sec1 =
BSP_CFG_ROM_REG_PBPS1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec2") g_bsp_rom_pbps_sec2 =
BSP_CFG_ROM_REG_PBPS2;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sel") g_bsp_rom_ofs1_sel =
BSP_CFG_ROM_REG_OFS1_SEL;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_banksel_sel") g_bsp_rom_banksel_sel =
0xFFFFFFFF;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel0") g_bsp_rom_bps_sel0 =
BSP_CFG_ROM_REG_BPS_SEL0;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel1") g_bsp_rom_bps_sel1 =
BSP_CFG_ROM_REG_BPS_SEL1;
BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sel2") g_bsp_rom_bps_sel2 =
BSP_CFG_ROM_REG_BPS_SEL2;
#endif
#endif
/** @} (end addtogroup BSP_MCU) */

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
#include "bsp_api.h"
#include <sys/types.h>
#include <errno.h>
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
caddr_t _sbrk(int incr);
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* FSP implementation of the standard library _sbrk() function.
* @param[in] inc The number of bytes being asked for by malloc().
*
* @note This function overrides the _sbrk version that exists in the newlib library that is linked with.
* That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and
* worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc()
* only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by
* malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc().
* @retval Address of allocated area if successful, -1 otherwise.
**********************************************************************************************************************/
caddr_t _sbrk (int incr)
{
extern char _Heap_Begin __asm("__HeapBase"); ///< Defined by the linker.
extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker.
uint32_t bytes = (uint32_t) incr;
static char * current_heap_end = 0;
char * current_block_address;
if (current_heap_end == 0)
{
current_heap_end = &_Heap_Begin;
}
current_block_address = current_heap_end;
/* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support
* unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple
* of 4. */
bytes = (bytes + 3U) & (~3U);
if (current_heap_end + bytes > &_Heap_Limit)
{
/** Heap has overflowed */
errno = ENOMEM;
return (caddr_t) -1;
}
current_heap_end += bytes;
return (caddr_t) current_block_address;
}
#endif
/******************************************************************************************************************//**
* @} (end addtogroup BSP_MCU)
*********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#if BSP_FEATURE_TZ_HAS_TRUSTZONE
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_PRV_TZ_REG_KEY (0xA500U)
#define BSP_PRV_AIRCR_VECTKEY (0x05FA0000U)
#define RA_NOT_DEFINED (0)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
void R_BSP_SecurityInit(void);
void R_BSP_PinCfgSecurityInit(void);
void R_BSP_ElcCfgSecurityInit(void);
/***********************************************************************************************************************
* External symbols
**********************************************************************************************************************/
extern const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES];
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
typedef void (BSP_CMSE_NONSECURE_CALL * bsp_nonsecure_func_t)(void);
#elif defined(__GNUC__)
typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void);
#endif
#if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD
#pragma section=".tz_flash_nsc_start"
#pragma section=".tz_flash_ns_start"
#pragma section=".tz_ram_nsc_start"
#pragma section=".tz_ram_ns_start"
#pragma section=".tz_data_flash_ns_start"
#pragma section=".tz_sdram_ns_start"
#pragma section=".tz_qspi_flash_ns_start"
/* &__tz_<REGION>_C is the address of the non-secure callable section. Must assign value to this variable or
* linker will give error. */
/* &__tz_<REGION>_N is the start address of the non-secure region. */
BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0;
BSP_DONT_REMOVE void const * const __tz_FLASH_N BSP_ALIGN_VARIABLE(32768) @".tz_flash_ns_start" = 0;
BSP_DONT_REMOVE void const * const __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start";
BSP_DONT_REMOVE void const * const __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start";
BSP_DONT_REMOVE void const * const __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start";
#if BSP_FEATURE_SDRAM_START_ADDRESS
BSP_DONT_REMOVE void const * const __tz_SDRAM_N @".tz_sdram_ns_start";
#endif
BSP_DONT_REMOVE void const * const __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start";
#if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS
BSP_DONT_REMOVE void const * const __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start";
#endif
#if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS
BSP_DONT_REMOVE void const * const __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start";
#endif
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N;
#elif defined(__ARMCC_VERSION)
extern const uint32_t Image$$__tz_FLASH_N$$Base;
extern const uint32_t Image$$__tz_FLASH_C$$Base;
extern const uint32_t Image$$__tz_FLASH_S$$Base;
extern const uint32_t Image$$__tz_RAM_N$$Base;
extern const uint32_t Image$$__tz_RAM_C$$Base;
extern const uint32_t Image$$__tz_RAM_S$$Base;
extern const uint32_t Image$$__tz_DATA_FLASH_N$$Base;
extern const uint32_t Image$$__tz_DATA_FLASH_S$$Base;
extern const uint32_t Image$$__tz_QSPI_FLASH_N$$Base;
extern const uint32_t Image$$__tz_QSPI_FLASH_S$$Base;
extern const uint32_t Image$$__tz_SDRAM_N$$Base;
extern const uint32_t Image$$__tz_SDRAM_S$$Base;
extern const uint32_t Image$$__tz_OSPI_DEVICE_0_N$$Base;
extern const uint32_t Image$$__tz_OSPI_DEVICE_0_S$$Base;
extern const uint32_t Image$$__tz_OSPI_DEVICE_1_N$$Base;
extern const uint32_t Image$$__tz_OSPI_DEVICE_1_S$$Base;
extern const uint32_t Image$$__tz_OPTION_SETTING_N$$Base;
extern const uint32_t Image$$__tz_OPTION_SETTING_S$$Base;
extern const uint32_t Image$$__tz_OPTION_SETTING_S_N$$Base;
extern const uint32_t Image$$__tz_OPTION_SETTING_S_S$$Base;
extern const uint32_t Image$$__tz_ID_CODE_N$$Base;
extern const uint32_t Image$$__tz_ID_CODE_S$$Base;
#define __tz_FLASH_N Image$$__tz_FLASH_N$$Base
#define __tz_FLASH_C Image$$__tz_FLASH_C$$Base
#define __tz_FLASH_S Image$$__tz_FLASH_S$$Base
#define __tz_RAM_N Image$$__tz_RAM_N$$Base
#define __tz_RAM_C Image$$__tz_RAM_C$$Base
#define __tz_RAM_S Image$$__tz_RAM_S$$Base
#define __tz_DATA_FLASH_N Image$$__tz_DATA_FLASH_N$$Base
#define __tz_DATA_FLASH_S Image$$__tz_DATA_FLASH_S$$Base
#define __tz_QSPI_FLASH_N Image$$__tz_QSPI_FLASH_N$$Base
#define __tz_QSPI_FLASH_S Image$$__tz_QSPI_FLASH_S$$Base
#define __tz_SDRAM_N Image$$__tz_SDRAM_N$$Base
#define __tz_SDRAM_S Image$$__tz_SDRAM_S$$Base
#define __tz_OSPI_DEVICE_0_N Image$$__tz_OSPI_DEVICE_0_N$$Base
#define __tz_OSPI_DEVICE_0_S Image$$__tz_OSPI_DEVICE_0_S$$Base
#define __tz_OSPI_DEVICE_1_N Image$$__tz_OSPI_DEVICE_1_N$$Base
#define __tz_OSPI_DEVICE_1_S Image$$__tz_OSPI_DEVICE_1_S$$Base
#define __tz_OPTION_SETTING_N Image$$__tz_OPTION_SETTING_N$$Base
#define __tz_OPTION_SETTING_S Image$$__tz_OPTION_SETTING_S$$Base
#define __tz_OPTION_SETTING_S_N Image$$__tz_OPTION_SETTING_S_N$$Base
#define __tz_OPTION_SETTING_S_S Image$$__tz_OPTION_SETTING_S_S$$Base
#define __tz_ID_CODE_N Image$$__tz_ID_CODE_N$$Base
#define __tz_ID_CODE_S Image$$__tz_ID_CODE_S$$Base
/* Assign region addresses to pointers so that AC6 includes symbols that can be used to determine the
* start addresses of Secure, Non-secure and Non-secure Callable regions. */
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_flash = &__tz_FLASH_C;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_flash = &__tz_FLASH_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ram = &__tz_RAM_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_callable_ram = &__tz_RAM_C;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ram = &__tz_RAM_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_data_flash = &__tz_DATA_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_data_flash = &__tz_DATA_FLASH_S;
#if BSP_TZ_SECURE_BUILD
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_qspi_flash = &__tz_QSPI_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_qspi_flash = &__tz_QSPI_FLASH_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_sdram = &__tz_SDRAM_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_sdram = &__tz_SDRAM_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_0 = &__tz_OSPI_DEVICE_0_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_0 = &__tz_OSPI_DEVICE_0_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_ospi_device_1 = &__tz_OSPI_DEVICE_1_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_ospi_device_1 = &__tz_OSPI_DEVICE_1_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_option_setting = &__tz_OPTION_SETTING_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_option_setting = &__tz_OPTION_SETTING_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_option_setting_s = &__tz_OPTION_SETTING_S_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_option_setting_s = &__tz_OPTION_SETTING_S_S;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_id_code = &__tz_ID_CODE_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_secure_id_code = &__tz_ID_CODE_S;
#endif
#elif defined(__GNUC__)
extern const uint32_t __tz_FLASH_N;
BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = &__tz_FLASH_N;
#endif
#if BSP_TZ_SECURE_BUILD
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Enter the non-secure code environment.
*
* This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler.
*
* @note This function (and therefore the non-secure code) should not return.
**********************************************************************************************************************/
void R_BSP_NonSecureEnter (void)
{
/* The NS vector table is at the start of the NS section in flash */
uint32_t const * p_ns_vector_table = gp_start_of_nonsecure_flash;
/* Set up the NS Reset_Handler to be called */
uint32_t const * p_ns_reset_address = (uint32_t const *) ((uint32_t) p_ns_vector_table + sizeof(uint32_t));
bsp_nonsecure_func_t p_ns_reset = (bsp_nonsecure_func_t) (*p_ns_reset_address);
/* Set the NS vector table address */
SCB_NS->VTOR = (uint32_t) p_ns_vector_table;
/* Set the NS stack pointer to the first entry in the NS vector table */
__TZ_set_MSP_NS(p_ns_vector_table[0]);
/* Jump to the NS Reset_Handler */
p_ns_reset();
}
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* Initialize security features for TrustZone.
*
* This function initializes ARM security register and Renesas SAR registers for secure projects.
*
* @note IDAU settings must be configured to match project settings with a separate configuration tool.
**********************************************************************************************************************/
void R_BSP_SecurityInit (void)
{
/* Setting SAU_CTRL.ALLNS to 1 allows the security attribution of all addresses to be set by the IDAU in the
* system. */
SAU->CTRL = SAU_CTRL_ALLNS_Msk;
/* The following section of code to configure SCB->AIRCR, SCB->NSACR, and FPU->FPCCR is taken from
* system_ARMCM33.c in the CMSIS_5 repository. SCB->SCR SLEEPDEEPS bit is not configured because the
* SCB->SCR SLEEPDEEP bit is ignored on RA MCUs. */
#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
/* Configure whether non-secure projects have access to system reset, whether bus fault, hard fault, and NMI target
* secure or non-secure, and whether non-secure interrupt priorities are reduced to the lowest 8 priority levels. */
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
BSP_PRV_AIRCR_VECTKEY |
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
#endif
#if defined(__FPU_USED) && (__FPU_USED == 1U) && \
defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
/* Configure whether the FPU can be accessed in the non-secure project. */
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
/* Configure whether FPU registers are always treated as non-secure (and therefore not preserved on the stack when
* switching from secure to non-secure), and whether the FPU registers should be cleared on exception return. */
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) |
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk);
#endif
/* Disable PRCR for SARs. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
/* Set TrustZone filter to Secure. */
R_TZF->TZFSAR = ~R_TZF_TZFSAR_TZFSA0_Msk;
/* Set TrustZone filter exception response. */
R_TZF->TZFPT = BSP_PRV_TZ_REG_KEY + 1U;
R_TZF->TZFOAD = BSP_PRV_TZ_REG_KEY + BSP_TZ_CFG_EXCEPTION_RESPONSE;
R_TZF->TZFPT = BSP_PRV_TZ_REG_KEY + 0U;
/* Initialize PSARs. */
R_PSCU->PSARB = BSP_TZ_CFG_PSARB;
R_PSCU->PSARC = BSP_TZ_CFG_PSARC;
R_PSCU->PSARD = BSP_TZ_CFG_PSARD;
R_PSCU->PSARE = BSP_TZ_CFG_PSARE;
R_PSCU->MSSAR = BSP_TZ_CFG_MSSAR;
/* Initialize Type 2 SARs. */
R_CPSCU->CSAR = BSP_TZ_CFG_CSAR; /* Cache Security Attribution. */
R_SYSTEM->RSTSAR = BSP_TZ_CFG_RSTSAR; /* RSTSRn Security Attribution. */
R_SYSTEM->LVDSAR = BSP_TZ_CFG_LVDSAR; /* LVD Security Attribution. */
R_SYSTEM->CGFSAR = BSP_TZ_CFG_CGFSAR; /* CGC Security Attribution. */
R_SYSTEM->LPMSAR = BSP_TZ_CFG_LPMSAR; /* LPM Security Attribution. */
R_SYSTEM->DPFSAR = BSP_TZ_CFG_DPFSAR; /* Deep Standby Interrupt Factor Security Attribution. */
R_SYSTEM->BBFSAR = BSP_TZ_CFG_BBFSAR; /* Battery Backup Security Attribution. */
R_CPSCU->ICUSARA = BSP_TZ_CFG_ICUSARA; /* External IRQ Security Attribution. */
R_CPSCU->ICUSARB = BSP_TZ_CFG_ICUSARB; /* NMI Security Attribution. */
R_CPSCU->ICUSARC = BSP_TZ_CFG_ICUSARC; /* DMAC Channel Security Attribution. */
R_CPSCU->ICUSARD = BSP_TZ_CFG_ICUSARD; /* SELSR0 Security Attribution. */
R_CPSCU->ICUSARE = BSP_TZ_CFG_ICUSARE; /* WUPEN0 Security Attribution. */
R_CPSCU->ICUSARF = BSP_TZ_CFG_ICUSARF; /* WUPEN1 Security Attribution. */
R_FCACHE->FSAR = BSP_TZ_CFG_FSAR; /* FLWT and FCKMHZ Security Attribution. */
R_CPSCU->SRAMSAR = BSP_TZ_CFG_SRAMSAR; /* SRAM Security Attribution. */
R_CPSCU->STBRAMSAR = BSP_TZ_CFG_STBRAMSAR; /* Standby RAM Security Attribution. */
R_CPSCU->MMPUSARA = BSP_TZ_CFG_MMPUSARA; /* Security Attribution for the DMAC Bus Master MPU. */
R_CPSCU->BUSSARA = BSP_TZ_CFG_BUSSARA; /* Security Attribution Register A for the BUS Control Registers. */
R_CPSCU->BUSSARB = BSP_TZ_CFG_BUSSARB; /* Security Attribution Register B for the BUS Control Registers. */
#if BSP_TZ_CFG_ICUSARC != UINT32_MAX
R_BSP_MODULE_START(FSP_IP_DMAC, 0);
/* If any DMAC channels are required by secure program, disable nonsecure write access to DMAST
* in order to prevent the nonsecure program from disabling all DMAC channels. */
R_CPSCU->DMACSAR = ~1U; /* Protect DMAST from nonsecure write access. */
/* Ensure that DMAST is set so that the nonsecure program can use DMA. */
R_DMA->DMAST = 1U;
#endif
#if BSP_TZ_CFG_DTC_USED
R_BSP_MODULE_START(FSP_IP_DTC, 0);
/* If the DTC is used by the secure program, disable nonsecure write access to DTCST
* in order to prevent the nonsecure program from disabling all DTC transfers. */
R_CPSCU->DTCSAR = ~1U;
/* Ensure that DTCST is set so that the nonsecure program can use DTC. */
R_DTC->DTCST = 1U;
#endif
/* Initialize security attribution registers for Pins. */
R_BSP_PinCfgSecurityInit();
/* Initialize security attribution registers for ELC. */
R_BSP_ElcCfgSecurityInit();
/* Reenable PRCR for SARs. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
}
/* This function is overridden by tooling. */
BSP_WEAK_REFERENCE void R_BSP_PinCfgSecurityInit (void)
{
}
/* This function is overridden by tooling. */
BSP_WEAK_REFERENCE void R_BSP_ElcCfgSecurityInit (void)
{
}
#endif
#endif

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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_SECURITY_H
#define BSP_SECURITY_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void R_BSP_NonSecureEnter(void);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

310
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/* ${REA_DISCLAIMER_PLACEHOLDER} */
#ifndef BSP_ELC_H
#define BSP_ELC_H
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************
* @addtogroup BSP_MCU_RA6M4
* @{
**********************************************************************************************************************/
/** Sources of event signals to be linked to other peripherals or the CPU
* @note This list may change based on based on the device.
* */
typedef enum e_elc_event_ra6m4
{
ELC_EVENT_NONE = (0), // Link disabled
ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0
ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1
ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2
ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3
ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4
ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5
ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6
ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7
ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8
ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9
ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10
ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11
ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12
ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13
ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14
ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15
ELC_EVENT_DMAC0_INT = (0x020), // DMAC transfer end 0
ELC_EVENT_DMAC1_INT = (0x021), // DMAC transfer end 1
ELC_EVENT_DMAC2_INT = (0x022), // DMAC transfer end 2
ELC_EVENT_DMAC3_INT = (0x023), // DMAC transfer end 3
ELC_EVENT_DMAC4_INT = (0x024), // DMAC transfer end 4
ELC_EVENT_DMAC5_INT = (0x025), // DMAC transfer end 5
ELC_EVENT_DMAC6_INT = (0x026), // DMAC transfer end 6
ELC_EVENT_DMAC7_INT = (0x027), // DMAC transfer end 7
ELC_EVENT_DTC_TRANSFER = (0x028), // DTC transfer
ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete
ELC_EVENT_DTC_END = (0x02A), // DTC transfer end
ELC_EVENT_DMA_TRANSERR = (0x02B), // DTC transfer error
ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode
ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt
ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt
ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt
ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt
ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop
ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry
ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt
ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A
ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B
ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt
ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A
ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B
ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt
ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A
ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B
ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt
ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A
ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B
ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt
ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A
ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B
ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt
ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A
ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B
ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow
ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow
ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt
ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt
ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt
ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA transfer request 0
ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA transfer request 1
ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt
ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt
ELC_EVENT_IIC0_RXI = (0x073), // Receive data full
ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty
ELC_EVENT_IIC0_TEI = (0x075), // Transmit end
ELC_EVENT_IIC0_ERI = (0x076), // Transfer error
ELC_EVENT_IIC0_WUI = (0x077), // Slave address match
ELC_EVENT_IIC1_RXI = (0x078), // Receive data full
ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty
ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end
ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error
ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access
ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access
ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect
ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request
ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty
ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full
ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt
ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt
ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt
ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt
ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt
ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt
ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt
ELC_EVENT_CAN0_ERROR = (0x0A1), // Error interrupt
ELC_EVENT_CAN0_FIFO_RX = (0x0A2), // Receive FIFO interrupt
ELC_EVENT_CAN0_FIFO_TX = (0x0A3), // Transmit FIFO interrupt
ELC_EVENT_CAN0_MAILBOX_RX = (0x0A4), // Reception complete interrupt
ELC_EVENT_CAN0_MAILBOX_TX = (0x0A5), // Transmission complete interrupt
ELC_EVENT_CAN1_ERROR = (0x0A6), // Error interrupt
ELC_EVENT_CAN1_FIFO_RX = (0x0A7), // Receive FIFO interrupt
ELC_EVENT_CAN1_FIFO_TX = (0x0A8), // Transmit FIFO interrupt
ELC_EVENT_CAN1_MAILBOX_RX = (0x0A9), // Reception complete interrupt
ELC_EVENT_CAN1_MAILBOX_TX = (0x0AA), // Transmission complete interrupt
ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event
ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event
ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event
ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event
ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0
ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1
ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable interrupt A
ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable interrupt B
ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable interrupt C
ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable interrupt D
ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A
ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B
ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C
ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D
ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E
ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F
ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow
ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow
ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish
ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Compare match A
ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Compare match B
ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C
ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D
ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E
ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F
ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow
ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow
ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish
ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Compare match A
ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Compare match B
ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C
ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D
ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E
ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F
ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow
ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow
ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Compare match A
ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Compare match B
ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C
ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D
ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E
ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F
ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow
ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow
ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Compare match A
ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Compare match B
ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C
ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D
ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E
ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F
ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow
ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow
ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish
ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Compare match A
ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Compare match B
ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C
ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D
ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E
ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F
ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow
ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow
ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish
ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Compare match A
ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Compare match B
ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C
ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D
ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E
ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F
ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow
ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow
ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish
ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Compare match A
ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Compare match B
ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C
ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D
ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E
ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F
ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow
ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow
ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Compare match A
ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Compare match B
ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C
ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D
ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E
ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F
ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow
ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow
ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Compare match A
ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Compare match B
ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C
ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D
ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E
ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F
ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow
ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow
ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event
ELC_EVENT_ADC0_SCAN_END = (0x160), // A/D scan end interrupt
ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B
ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match
ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match
ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match
ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch
ELC_EVENT_ADC1_SCAN_END = (0x166), // A/D scan end interrupt
ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B
ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match
ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match
ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match
ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch
ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt
ELC_EVENT_SCI0_RXI = (0x180), // Receive data full
ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty
ELC_EVENT_SCI0_TEI = (0x182), // Transmit end
ELC_EVENT_SCI0_ERI = (0x183), // Receive error
ELC_EVENT_SCI0_AM = (0x184), // Address match event
ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive
ELC_EVENT_SCI1_RXI = (0x186), // Received data full
ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty
ELC_EVENT_SCI1_TEI = (0x188), // Transmit end
ELC_EVENT_SCI1_ERI = (0x189), // Receive error
ELC_EVENT_SCI2_RXI = (0x18C), // Received data full
ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty
ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end
ELC_EVENT_SCI2_ERI = (0x18F), // Receive error
ELC_EVENT_SCI3_RXI = (0x192), // Received data full
ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty
ELC_EVENT_SCI3_TEI = (0x194), // Transmit end
ELC_EVENT_SCI3_ERI = (0x195), // Receive error
ELC_EVENT_SCI3_AM = (0x196), // Address match event
ELC_EVENT_SCI4_RXI = (0x198), // Received data full
ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty
ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end
ELC_EVENT_SCI4_ERI = (0x19B), // Receive error
ELC_EVENT_SCI4_AM = (0x19C), // Address match event
ELC_EVENT_SCI5_RXI = (0x19E), // Received data full
ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty
ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end
ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error
ELC_EVENT_SCI5_AM = (0x1A2), // Address match event
ELC_EVENT_SCI6_RXI = (0x1A4), // Received data full
ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty
ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end
ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error
ELC_EVENT_SCI6_AM = (0x1A8), // Address match event
ELC_EVENT_SCI7_RXI = (0x1AA), // Received data full
ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty
ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end
ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error
ELC_EVENT_SCI7_AM = (0x1AE), // Address match event
ELC_EVENT_SCI8_RXI = (0x1B0), // Received data full
ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty
ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end
ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error
ELC_EVENT_SCI8_AM = (0x1B4), // Address match event
ELC_EVENT_SCI9_RXI = (0x1B6), // Received data full
ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty
ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end
ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error
ELC_EVENT_SCI9_AM = (0x1BA), // Address match event
ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI0 extended serial mode event 0
ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI0 extended serial mode event 1
ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI0 extended serial mode event 2
ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI0 extended serial mode event 3
ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI1 extended serial mode event 0
ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI1 extended serial mode event 1
ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI1 extended serial mode event 2
ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI1 extended serial mode event 3
ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full
ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty
ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle
ELC_EVENT_SPI0_ERI = (0x1C7), // Error
ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event
ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full
ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty
ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle
ELC_EVENT_SPI1_ERI = (0x1CC), // Error
ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event
ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt
ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt
ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt
} elc_event_t;
/** @} (end addtogroup BSP_MCU_RA6M4) */
#endif

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board/Renesas_ra6m4/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h Normal file
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/* ${REA_DISCLAIMER_PLACEHOLDER} */
#ifndef BSP_FEATURE_H
#define BSP_FEATURE_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */
#if (BSP_CFG_XTAL_HZ > (19999999))
#define CGC_MAINCLOCK_DRIVE (0x00U)
#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000))
#define CGC_MAINCLOCK_DRIVE (0x01U)
#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000))
#define CGC_MAINCLOCK_DRIVE (0x02U)
#else
#define CGC_MAINCLOCK_DRIVE (0x03U)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU
#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU
#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U)
#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U)
#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC)
#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U)
#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U)
#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U)
#define BSP_FEATURE_ADC_HAS_PGA (0U)
#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U)
#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U)
#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U)
#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U)
#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU)
#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU
#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U)
#define BSP_FEATURE_ADC_TSN_SLOPE (4000)
#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x33FF) // 0 to 9, 12, 13
#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x7F0007) // 0 to 2, 16 to 22
#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U)
#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F)
#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5)
#define BSP_FEATURE_BSP_FLASH_CACHE (1)
#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U)
#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0)
#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1)
#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1)
#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU
#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U)
#define BSP_FEATURE_BSP_HAS_SP_MON (0U)
#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M4 there are specific registers for configuring the USB clock.
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U)
#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U)
#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U)
#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU
#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid.
#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U)
#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU)
#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U)
#define BSP_FEATURE_BSP_OSIS_PADDING (0U)
#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U)
#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U)
#define BSP_FEATURE_BSP_RESET_TRNG (0U)
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC.
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle.
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option).
#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles.
#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U)
#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U)
#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U)
#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U)
#define BSP_FEATURE_CAN_CLOCK (0U)
#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U)
#define BSP_FEATURE_CAN_NUM_CHANNELS (2U)
#define BSP_FEATURE_CGC_HAS_BCLK (1U)
#define BSP_FEATURE_CGC_HAS_FCLK (1U)
#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U)
#define BSP_FEATURE_CGC_HAS_FLWT (1U)
#define BSP_FEATURE_CGC_HAS_FLL (1U)
#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U)
#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U)
#define BSP_FEATURE_CGC_HAS_PCLKA (1U)
#define BSP_FEATURE_CGC_HAS_PCLKB (1U)
#define BSP_FEATURE_CGC_HAS_PCLKC (1U)
#define BSP_FEATURE_CGC_HAS_PCLKD (1U)
#define BSP_FEATURE_CGC_HAS_PLL (1U)
#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M4 there is another PLL that can be used as a clock source for USB and OCTASPI.
#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M4 there is another register to enable write access for SRAMWTSC.
#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U)
#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U)
#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U)
#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4)
#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U)
#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz
#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode
#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode
#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U)
#define BSP_FEATURE_CGC_MODRV_MASK (0x30U)
#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U)
#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U)
#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP
#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U)
#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0)
#define BSP_FEATURE_CGC_SODRV_MASK (0x02U)
#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U)
#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0)
#define BSP_FEATURE_CRYPTO_HAS_AES (1)
#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_ECC (1)
#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_HASH (1)
#define BSP_FEATURE_CRYPTO_HAS_RSA (1)
#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1)
#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1)
#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1)
#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U)
#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U)
#define BSP_FEATURE_CTSU_HAS_TXVSEL (1)
#define BSP_FEATURE_CTSU_VERSION (1)
#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU
#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U)
#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U)
#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U)
#define BSP_FEATURE_DAC_MAX_CHANNELS (2U)
#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U)
#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M4 has Data Watchpoint Cycle Count Register
#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU
#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU)
#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U)
#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U)
#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U)
#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U)
#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U)
#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U)
#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1)
#define BSP_FEATURE_FLASH_HP_VERSION (40U)
#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU
#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0)
#define BSP_FEATURE_GPTE_CHANNEL_MASK (0)
#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU)
#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x1FFU)
#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U)
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU)
#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register
#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U)
#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x03)
#define BSP_FEATURE_IOPORT_ELC_PORTS (4)
#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U)
#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U)
#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U)
#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU)
#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU)
#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
#define BSP_FEATURE_LPM_HAS_STCONR (0U)
#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0)
#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register
#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register
#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U)
#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U)
#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V
#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V
#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V
#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize
#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U)
#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U)
#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U)
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU
#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U)
#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U)
#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U)
#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U)
#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU)
#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_CHANNELS (0x3FFU)
#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U)
#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U)
#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U)
#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U)
#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U)
#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB)
#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported
#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U)
#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU
#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU
#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA)
#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U)
#define BSP_FEATURE_SPI_HAS_SPCR3 (1U)
#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U)
#define BSP_FEATURE_SPI_MAX_CHANNEL (2U)
#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U)
#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U)
#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U)
#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U)
#endif

40
board/Renesas_ra6m4/ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h Normal file
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/* ${REA_DISCLAIMER_PLACEHOLDER} */
/*******************************************************************************************************************//**
* @ingroup BSP_MCU
* @defgroup BSP_MCU_RA6M4 RA6M4
* @includedoc config_bsp_ra6m4_fsp.html
* @{
**********************************************************************************************************************/
/** @} (end defgroup BSP_MCU_RA6M4) */
#ifndef BSP_MCU_INFO_H
#define BSP_MCU_INFO_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* BSP MCU Specific Includes. */
#include "bsp_elc.h"
#include "bsp_feature.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
typedef elc_event_t bsp_interrupt_event_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
#endif

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board/Renesas_ra6m4/ra/fsp/src/r_ioport/r_ioport.c Normal file
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/***********************************************************************************************************************
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <stdint.h>
#include "bsp_api.h"
#include "r_ioport.h"
#include "r_ioport_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* "PORT" in ASCII, used to determine if the module is open */
#define IOPORT_OPEN (0x504F5254U)
#define IOPORT_CLOSED (0x00000000U)
/* Mask to get PSEL bitfield from PFS register. */
#define BSP_PRV_PFS_PSEL_MASK (0x1F000000UL)
/* Shift to get pin 0 on a package in extended data. */
#define IOPORT_PRV_EXISTS_B0_SHIFT (16UL)
/* Mask to determine if any pins on port exist on this package. */
#define IOPORT_PRV_PORT_EXISTS_MASK (0xFFFF0000U)
/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */
#define IOPORT_PRV_PORT_OFFSET (8U)
#ifndef BSP_MCU_VBATT_SUPPORT
#define BSP_MCU_VBATT_SUPPORT (0U)
#endif
#define IOPORT_PRV_PORT_BITS (0xFF00U)
#define IOPORT_PRV_PIN_BITS (0x00FFU)
#define IOPORT_PRV_PCNTR_OFFSET 0x00000020U
#define IOPORT_PRV_PERIPHERAL_FUNCTION (1U << 16)
#define IOPORT_PRV_CLEAR_BITS_MASK (0x1F01FCD5U) ///< Zero bits in mask must be written as zero to PFS register
#define IOPORT_PRV_8BIT_MASK (0xFFU)
#define IOPORT_PRV_16BIT_MASK (0xFFFFU)
#define IOPORT_PRV_UPPER_16BIT_MASK (0xFFFF0000U)
#define IOPORT_PRV_PFENET_MASK (0x30U)
#define IOPORT_PRV_SET_PWPR_PFSWE (0x40U)
#define IOPORT_PRV_SET_PWPR_BOWI (0x80U)
#define IOPORT_PRV_PORT_ADDRESS(port_number) ((uint32_t) (R_PORT1 - R_PORT0) * (port_number) + R_PORT0)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
static void r_ioport_pins_config(const ioport_cfg_t * p_cfg);
static void r_ioport_hw_pin_event_output_data_write(bsp_io_port_t port,
ioport_size_t set_value,
ioport_size_t reset_value,
bsp_io_level_t pin_level);
static void r_ioport_pfs_write(bsp_io_port_pin_t pin, uint32_t value);
#if BSP_MCU_VBATT_SUPPORT
static void bsp_vbatt_init(ioport_cfg_t const * const p_pin_cfg); // Used internally by BSP
#endif
/***********************************************************************************************************************
* Private global variables
**********************************************************************************************************************/
/* Version data structure used by error logger macro. */
static const fsp_version_t g_ioport_version =
{
.api_version_minor = IOPORT_API_VERSION_MINOR,
.api_version_major = IOPORT_API_VERSION_MAJOR,
.code_version_major = IOPORT_CODE_VERSION_MAJOR,
.code_version_minor = IOPORT_CODE_VERSION_MINOR
};
/***********************************************************************************************************************
* Global Variables
**********************************************************************************************************************/
/* IOPort Implementation of IOPort Driver */
const ioport_api_t g_ioport_on_ioport =
{
.open = R_IOPORT_Open,
.close = R_IOPORT_Close,
.pinsCfg = R_IOPORT_PinsCfg,
.pinCfg = R_IOPORT_PinCfg,
.pinEventInputRead = R_IOPORT_PinEventInputRead,
.pinEventOutputWrite = R_IOPORT_PinEventOutputWrite,
.pinEthernetModeCfg = R_IOPORT_EthernetModeCfg,
.pinRead = R_IOPORT_PinRead,
.pinWrite = R_IOPORT_PinWrite,
.portDirectionSet = R_IOPORT_PortDirectionSet,
.portEventInputRead = R_IOPORT_PortEventInputRead,
.portEventOutputWrite = R_IOPORT_PortEventOutputWrite,
.portRead = R_IOPORT_PortRead,
.portWrite = R_IOPORT_PortWrite,
.versionGet = R_IOPORT_VersionGet,
};
#if BSP_MCU_VBATT_SUPPORT
static const bsp_io_port_pin_t g_vbatt_pins_input[] =
{
BSP_IO_PORT_04_PIN_02, ///< Associated with VBTICTLR->VCH0INEN
BSP_IO_PORT_04_PIN_03, ///< Associated with VBTICTLR->VCH1INEN
BSP_IO_PORT_04_PIN_04 ///< Associated with VBTICTLR->VCH2INEN
};
#endif
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Initializes internal driver data, then calls pin configuration function to configure pins.
*
* @retval FSP_SUCCESS Pin configuration data written to PFS register(s)
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_ALREADY_OPEN Module is already open.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
{
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ASSERT(NULL != p_cfg);
FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Set driver status to open */
p_instance_ctrl->open = IOPORT_OPEN;
r_ioport_pins_config(p_cfg);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Resets IOPORT registers. Implements @ref ioport_api_t::close
*
* @retval FSP_SUCCESS The IOPORT was successfully uninitialized
* @retval FSP_ERR_ASSERTION p_ctrl was NULL
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl)
{
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Set state to closed */
p_instance_ctrl->open = IOPORT_CLOSED;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Configures the functions of multiple pins by loading configuration data into pin PFS registers.
* Implements @ref ioport_api_t::pinsCfg.
*
* This function initializes the supplied list of PmnPFS registers with the supplied values. This data can be generated
* by the Pins tab of the RA Configuration editor or manually by the developer. Different pin configurations can be
* loaded for different situations such as low power modes and testing.
*
* @retval FSP_SUCCESS Pin configuration data written to PFS register(s)
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_cfg);
FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
r_ioport_pins_config(p_cfg);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg.
*
* @retval FSP_SUCCESS Pin configured
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is re-entrant for different pins.
* This function will change the configuration of the pin with the new configuration. For example it is not possible
* with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To
* achieve this the original settings with the required change will need to be written using this function.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
#if BSP_MCU_VBATT_SUPPORT
/* Create temporary structure for handling VBATT pins. */
ioport_cfg_t temp_cfg;
ioport_pin_cfg_t temp_pin_cfg;
temp_pin_cfg.pin = pin;
temp_pin_cfg.pin_cfg = cfg;
temp_cfg.number_of_pins = 1U;
temp_cfg.p_pin_cfg_data = &temp_pin_cfg;
/* Handle any VBATT domain pin configuration. */
bsp_vbatt_init(&temp_cfg);
#endif
R_BSP_PinAccessEnable();
r_ioport_pfs_write(pin, cfg);
R_BSP_PinAccessDisable();
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the level on a pin. Implements @ref ioport_api_t::pinRead.
*
* @retval FSP_SUCCESS Pin read
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
* @note This function is re-entrant for different pins.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_pin_value);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
*p_pin_value = (bsp_io_level_t) R_BSP_PinRead(pin);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the value on an IO port. Implements @ref ioport_api_t::portRead.
*
* The specified port will be read, and the levels for all the pins will be returned.
* Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds
* to pin 7, bit 6 to pin 6, and so on.
*
* @retval FSP_SUCCESS Port read
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
* @note This function is re-entrant for different ports.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_port_value);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* Read current value of PCNTR2 register for the specified port */
*p_port_value = p_ioport_regs->PCNTR2 & IOPORT_PRV_16BIT_MASK;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite.
*
* The input value will be written to the specified port. Each bit in the value parameter corresponds to a bit
* on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
* Each bit in the mask parameter corresponds to a pin on the port.
*
* Only the bits with the corresponding bit in the mask value set will be updated.
* For example, value = 0xFFFF, mask = 0x0003 results in only bits 0 and 1 being updated.
*
* @retval FSP_SUCCESS Port written to
* @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointerd
*
* @note This function is re-entrant for different ports. This function makes use of the PCNTR3 register to atomically
* modify the levels on the specified pins on a port.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
ioport_size_t setbits;
ioport_size_t clrbits;
/* High bits */
setbits = value & mask;
/* Low bits */
/* Cast to ensure size */
clrbits = (ioport_size_t) ((~value) & mask);
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* PCNTR3 register: lower word = set data, upper word = reset_data */
p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite.
*
* @retval FSP_SUCCESS Pin written to
* @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opene
* @retval FSP_ERR_ASSERTION NULL pointerd
*
* @note This function is re-entrant for different pins. This function makes use of the PCNTR3 register to atomically
* modify the level on the specified pin on a port.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
ioport_size_t setbits = 0U;
ioport_size_t clrbits = 0U;
bsp_io_port_t port = (bsp_io_port_t) (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin);
ioport_size_t shift = IOPORT_PRV_PIN_BITS & (ioport_size_t) pin;
ioport_size_t pin_mask = (ioport_size_t) (1U << shift);
if (BSP_IO_LEVEL_LOW == level)
{
clrbits = pin_mask;
}
else
{
setbits = pin_mask;
}
/* PCNTR register is updated instead of using PFS as access is atomic and PFS requires seperate enable/disable
* using PWPR register */
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* PCNTR3 register: lower word = set data, upper word = reset_data */
p_ioport_regs->PCNTR3 = (uint32_t) (((uint32_t) clrbits << 16) | setbits);
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet().
*
* Multiple pins on a port can be set to inputs or outputs at once.
* Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to
* pin 7, bit 6 to pin 6, and so on. If a bit is set to 1 then the corresponding pin will be changed to
* an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of
* the pin will not be changed.
*
* @retval FSP_SUCCESS Port direction updated
* @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is re-entrant for different ports.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask)
{
ioport_size_t orig_value;
ioport_size_t set_bits;
ioport_size_t clr_bits;
ioport_size_t write_value;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* Read current value of PCNTR1 register for the specified port */
orig_value = p_ioport_regs->PCNTR1 & IOPORT_PRV_16BIT_MASK;
/* High bits */
set_bits = direction_values & mask;
/* Low bits */
/* Cast to ensure size */
clr_bits = (ioport_size_t) ((~direction_values) & mask);
/* New value to write to port direction register */
write_value = orig_value;
write_value |= set_bits;
/* Cast to ensure size */
write_value &= (ioport_size_t) (~clr_bits);
p_ioport_regs->PCNTR1 = write_value & IOPORT_PRV_16BIT_MASK;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead().
*
* The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port.
* For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on.
*
* The port event data is captured in response to a trigger from the ELC. This function enables this data to be read.
* Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
*
* @retval FSP_SUCCESS Port read
* @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
*
* @note This function is re-entrant for different ports.
*
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_event_data);
uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET;
FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(port >> IOPORT_PRV_PORT_OFFSET & IOPORT_PRV_8BIT_MASK);
/* Read current value of EIDR value from PCNTR2 register for the specified port */
*p_event_data = p_ioport_regs->PCNTR2_b.EIDR;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead.
*
* The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read.
* Using the event system allows the captured data to be stored when it occurs and then read back at a later time.
*
* @retval FSP_SUCCESS Pin read
* @retval FSP_ERR_ASSERTION NULL pointer
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT.
*
* @note This function is re-entrant.
*
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event)
{
ioport_size_t portvalue;
ioport_size_t mask;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ASSERT(NULL != p_pin_event);
uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((pin >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* Read current value of EIDR value from PCNTR2 register for the specified port */
portvalue = p_ioport_regs->PCNTR2_b.EIDR;
mask = (ioport_size_t) (1U << (IOPORT_PRV_PIN_BITS & (bsp_io_port_t) pin));
if ((portvalue & mask) == mask)
{
*p_pin_event = BSP_IO_LEVEL_HIGH;
}
else
{
*p_pin_event = BSP_IO_LEVEL_LOW;
}
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* This function writes the set and reset event output data for a port. Implements
* @ref ioport_api_t::portEventOutputWrite.
*
* Using the event system enables a port state to be stored by this function in advance of being output on the port.
* The output to the port will occur when the ELC event occurs.
*
* The input value will be written to the specified port when an ELC event configured for that port occurs.
* Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7,
* bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port.
*
* @retval FSP_SUCCESS Port event data written
* @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is re-entrant for different ports.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value)
{
ioport_size_t set_bits;
ioport_size_t reset_bits;
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT);
uint32_t port_number = port >> IOPORT_PRV_PORT_OFFSET;
FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
set_bits = event_data & mask_value;
/* Cast to ensure size */
reset_bits = (ioport_size_t) ((~event_data) & mask_value);
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* PCNTR4 register: lower word = set data, upper word = reset_data */
p_ioport_regs->PCNTR4 = (uint32_t) (((uint32_t) reset_bits << 16) | set_bits);
return FSP_SUCCESS;
}
/**********************************************************************************************************************//**
* This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite.
*
* Using the event system enables a pin state to be stored by this function in advance of being output on the pin.
* The output to the pin will occur when the ELC event occurs.
*
* @retval FSP_SUCCESS Pin event data written
* @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is re-entrant for different ports.
*
**********************************************************************************************************************/
fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT);
uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET;
FSP_ERROR_RETURN((port_number != 0) && (port_number <= BSP_FEATURE_IOPORT_ELC_PORTS), FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
#endif
ioport_size_t set_bits;
ioport_size_t reset_bits;
bsp_io_port_t port;
uint16_t pin_to_port;
/* Cast to ensure correct conversion of parameter. */
pin_to_port = (uint16_t) pin;
pin_to_port = pin_to_port & (uint16_t) IOPORT_PRV_PORT_BITS;
port = (bsp_io_port_t) pin_to_port;
set_bits = (ioport_size_t) 0;
reset_bits = (ioport_size_t) 0;
if (BSP_IO_LEVEL_HIGH == pin_value)
{
/* Cast to ensure size */
set_bits = (ioport_size_t) (1U << ((ioport_size_t) pin & IOPORT_PRV_PIN_BITS));
}
else
{
/* Cast to ensure size */
reset_bits = (ioport_size_t) (1U << ((ioport_size_t) pin & IOPORT_PRV_PIN_BITS));
}
r_ioport_hw_pin_event_output_data_write(port, set_bits, reset_bits, pin_value);
return FSP_SUCCESS;
}
/***********************************************************************************************************************
* DEPRECATED Returns IOPort HAL driver version. Implements @ref ioport_api_t::versionGet.
*
* @retval FSP_SUCCESS Version information read
* @retval FSP_ERR_ASSERTION The parameter p_data is NULL
*
* @note This function is reentrant.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_VersionGet (fsp_version_t * p_data)
{
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
/* Verify parameters are valid */
FSP_ASSERT(NULL != p_data);
#endif
*p_data = g_ioport_version;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Configures Ethernet channel PHY mode. Implements @ref ioport_api_t::pinEthernetModeCfg.
*
* @retval FSP_SUCCESS Ethernet PHY mode set
* @retval FSP_ERR_INVALID_ARGUMENT Channel or mode not valid
* @retval FSP_ERR_UNSUPPORTED Ethernet configuration not supported on this device.
* @retval FSP_ERR_NOT_OPEN The module has not been opened
* @retval FSP_ERR_ASSERTION NULL pointer
*
* @note This function is not re-entrant.
**********************************************************************************************************************/
fsp_err_t R_IOPORT_EthernetModeCfg (ioport_ctrl_t * const p_ctrl,
ioport_ethernet_channel_t channel,
ioport_ethernet_mode_t mode)
{
FSP_ERROR_RETURN(1U == BSP_FEATURE_IOPORT_HAS_ETHERNET, FSP_ERR_UNSUPPORTED);
#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE)
ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl;
FSP_ASSERT(NULL != p_instance_ctrl);
FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
FSP_ERROR_RETURN(channel < IOPORT_ETHERNET_CHANNEL_END, FSP_ERR_INVALID_ARGUMENT);
FSP_ERROR_RETURN(mode < IOPORT_ETHERNET_MODE_END, FSP_ERR_INVALID_ARGUMENT);
#else
FSP_PARAMETER_NOT_USED(p_ctrl);
FSP_PARAMETER_NOT_USED(channel);
#endif
R_PMISC->PFENET = (uint8_t) mode;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* @} (end addtogroup IOPORT)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Configures pins.
*
* @param[in] p_cfg Pin configuration data
**********************************************************************************************************************/
void r_ioport_pins_config (const ioport_cfg_t * p_cfg)
{
#if BSP_MCU_VBATT_SUPPORT
/* Handle any VBATT domain pin configuration. */
bsp_vbatt_init(p_cfg);
#endif
uint16_t pin_count;
ioport_cfg_t * p_pin_data;
p_pin_data = (ioport_cfg_t *) p_cfg;
R_BSP_PinAccessEnable(); // Protect PWPR from re-entrancy
for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++)
{
r_ioport_pfs_write(p_pin_data->p_pin_cfg_data[pin_count].pin, p_pin_data->p_pin_cfg_data[pin_count].pin_cfg);
}
R_BSP_PinAccessDisable();
}
/*******************************************************************************************************************//**
* Writes the set and clear values on a pin of the port when an ELC event occurs. This allows accurate timing of
* pin output level.
*
* @param[in] port Port to read event data
* @param[in] set_value Bit in the port to set high (1 = that bit will be set high)
* @param[in] reset_value Bit in the port to clear low (1 = that bit will be cleared low)
* @param[in] pin_level Event data for pin
**********************************************************************************************************************/
static void r_ioport_hw_pin_event_output_data_write (bsp_io_port_t port,
ioport_size_t set_value,
ioport_size_t reset_value,
bsp_io_level_t pin_level)
{
uint32_t port_value = 0;
/* Get the port address */
R_PORT0_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS((port >> IOPORT_PRV_PORT_OFFSET) & IOPORT_PRV_8BIT_MASK);
/* Read current value of PCNTR4 register */
port_value = p_ioport_regs->PCNTR4;
if (BSP_IO_LEVEL_HIGH == pin_level)
{
/* set value contains the bit to be set high (bit mask) */
port_value |= (uint32_t) (set_value);
/* reset value contains the mask to clear the corresponding bit in EOSR because both EOSR and EORR
* bit of a particular pin should not be high at the same time */
port_value &= (((uint32_t) reset_value << 16) | IOPORT_PRV_16BIT_MASK);
}
else
{
/* reset_value contains the bit to be cleared low */
port_value |= (uint32_t) reset_value << 16;
/* set value contains the mask to clear the corresponding bit in EOSR because both EOSR and EORR bit of a
* particular pin should not be high at the same time */
port_value &= (uint32_t) ((set_value | IOPORT_PRV_UPPER_16BIT_MASK));
}
p_ioport_regs->PCNTR4 = port_value;
}
/*******************************************************************************************************************//**
* Writes to the specified pin's PFS register
*
* @param[in] pin Pin to write PFS data for
* @param[in] value Value to be written to the PFS register
*
**********************************************************************************************************************/
static void r_ioport_pfs_write (bsp_io_port_pin_t pin, uint32_t value)
{
/* PMR bits should be cleared before specifying PSEL. Reference section "20.7 Notes on the PmnPFS Register Setting"
* in the RA6M3 manual R01UH0886EJ0100. */
if ((value & IOPORT_PRV_PERIPHERAL_FUNCTION) > 0)
{
/* Clear PMR */
R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PMR = 0;
/* New config with PMR = 0 */
R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin &
BSP_IO_PRV_8BIT_MASK].PmnPFS =
(value & ~((uint32_t) IOPORT_PRV_PERIPHERAL_FUNCTION));
}
/* Write configuration */
R_PFS->PORT[pin >> IOPORT_PRV_PORT_OFFSET].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = value;
}
#if BSP_MCU_VBATT_SUPPORT
/*******************************************************************************************************************//**
* @brief Initializes VBTICTLR register based on pin configuration.
*
* The VBTICTLR register may need to be modified based on the project's pin configuration. There is a set of pins that
* needs to be checked. If one of these pins is found in the pin configuration table then it will be tested to see if
* the appropriate VBTICTLR bit needs to be set or cleared. If one of the pins that is being searched for is not found
* then the accompanying VBTICTLR bit is left as-is.
**********************************************************************************************************************/
static void bsp_vbatt_init (ioport_cfg_t const * const p_pin_cfg)
{
uint32_t pin_index;
uint32_t vbatt_index;
uint8_t local_vbtictlr_set; ///< Will hold bits to set in VBTICTLR
uint8_t local_vbtictlr_clear; ///< Will hold bits to clear in VBTICTLR
/* Make no changes unless required. */
local_vbtictlr_set = 0U;
local_vbtictlr_clear = 0U;
/* Must loop over all pins as pin configuration table is unordered. */
for (pin_index = 0U; pin_index < p_pin_cfg->number_of_pins; pin_index++)
{
/* Loop over VBATT input pins. */
for (vbatt_index = 0U;
vbatt_index < (sizeof(g_vbatt_pins_input) / sizeof(g_vbatt_pins_input[0]));
vbatt_index++)
{
if (p_pin_cfg->p_pin_cfg_data[pin_index].pin == g_vbatt_pins_input[vbatt_index])
{
/* Get PSEL value for pin. */
uint32_t pfs_psel_value = p_pin_cfg->p_pin_cfg_data[pin_index].pin_cfg & BSP_PRV_PFS_PSEL_MASK;
/* Check if pin is being used for RTC or AGT use. */
if ((IOPORT_PERIPHERAL_AGT == pfs_psel_value) || (IOPORT_PERIPHERAL_CLKOUT_COMP_RTC == pfs_psel_value))
{
/* Bit should be set to 1. */
local_vbtictlr_set |= (uint8_t) (1U << vbatt_index);
}
else
{
/* Bit should be cleared to 0. */
local_vbtictlr_clear |= (uint8_t) (1U << vbatt_index);
}
}
}
}
/* Disable write protection on VBTICTLR. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
/* Read value, set and clear bits as needed and write back. */
uint8_t local_vbtictlr = R_SYSTEM->VBTICTLR;
local_vbtictlr |= local_vbtictlr_set; ///< Set appropriate bits
local_vbtictlr &= (uint8_t) ~local_vbtictlr_clear; ///< Clear appropriate bits
R_SYSTEM->VBTICTLR = local_vbtictlr;
/* Enable write protection on VBTICTLR. */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif

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FSP Configuration
Board "Custom User Board (Any Device)"
R7FA6M4AF3CFB
part_number: R7FA6M4AF3CFB
rom_size_bytes: 1048576
ram_size_bytes: 262144
data_flash_size_bytes: 8192
package_style: LQFP
package_pins: 144
RA6M4
series: 6
RA6M4 Family
Security: Exceptions: Exception Response: Non-Maskable Interrupt
Security: Exceptions: BusFault, HardFault, and NMI Target: Secure State
Security: System Reset Request Accessibility: Secure State
Security: Exceptions: Prioritize Secure Exceptions: Disabled
Security: Cache Accessibility: Both Secure and Non-Secure State
Security: System Reset Status Accessibility: Both Secure and Non-Secure State
Security: Battery Backup Accessibility: Both Secure and Non-Secure State
Security: SRAM Accessibility: SRAM Protection: Both Secure and Non-Secure State
Security: SRAM Accessibility: SRAM ECC: Both Secure and Non-Secure State
Security: SRAM Accessibility: Standby RAM: Regions 7-0 are all Secure.
Security: BUS Accessibility: Bus Security Attribution Register A: Both Secure and Non-Secure State
Security: BUS Accessibility: Bus Security Attribution Register B: Both Secure and Non-Secure State
Startup C-Cache Line Size: 32 Bytes
OFS0 register settings: Independent WDT: Start Mode: IWDT is Disabled
OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles
OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128
OFS0 register settings: Independent WDT: Window End Position: 0% (no window end position)
OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position)
OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled
OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby
OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode)
OFS0 register settings: WDT: Timeout Period: 16384 cycles
OFS0 register settings: WDT: Clock Frequency Division Ratio: 128
OFS0 register settings: WDT: Window End Position: 0% (no window end position)
OFS0 register settings: WDT: Window Start Position: 100% (no window start position)
OFS0 register settings: WDT: Reset Interrupt Request: Reset
OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode
OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
OFS1 register settings: Voltage Detection 0 Level: 2.80 V
OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
Block Protection Settings (BPS): BPS0:
Block Protection Settings (BPS): BPS1:
Block Protection Settings (BPS): BPS2:
Permanent Block Protection Settings (PBPS): PBPS0:
Permanent Block Protection Settings (PBPS): PBPS1:
Permanent Block Protection Settings (PBPS): PBPS2:
Dual Bank Mode: Disabled
Clocks: HOCO FLL Function: Disabled
RA Common
Main stack size (bytes): 0x400
Heap size (bytes): 0
MCU Vcc (mV): 3300
Parameter checking: Disabled
Assert Failures: Return FSP_ERR_ASSERTION
Error Log: No Error Log
Soft Reset: Disabled
Main Oscillator Populated: Populated
PFS Protect: Enabled
C Runtime Initialization : Enabled
Main Oscillator Wait Time: 32768 us
Main Oscillator Clock Source: Crystal or Resonator
Subclock Populated: Populated
Subclock Drive (Drive capacitance availability varies by MCU): Standard/Normal mode
Subclock Stabilization Time (ms): 1000
Clocks
XTAL 24000000Hz
HOCO 20MHz
PLL Src: HOCO
PLL Div /2
PLL Mul x20.0
PLL2 Disabled
PLL2 Div /2
PLL2 Mul x20.0
Clock Src: PLL
CLKOUT Disabled
UCLK Disabled
OCTASPICLK Disabled
ICLK Div /1
PCLKA Div /2
PCLKB Div /4
PCLKC Div /4
PCLKD Div /2
BCLK Div /2
BCLK/2
FCLK Div /4
CLKOUT Div /1
UCLK Div /5
OCTASPICLK Div /1
Pin Configurations
R7FA6M4AF3CFB.pincfg -> g_bsp_pin_cfg
AVCC0 127 ANALOG0_AVCC0 - - - - - - - - IO "Read only" -
AVSS0 128 ANALOG0_AVSS0 - - - - - - - - IO "Read only" -
P000 140 - - - - Disabled - - "ADC0: AN00; ADC1: AN00; ICU0: IRQ06" - None - -
P001 139 - - - - Disabled - - "ADC0: AN01; ADC1: AN01; ICU0: IRQ07" - None - -
P002 138 - - - - Disabled - - "ADC0: AN02; ADC1: AN02; ICU0: IRQ08" - None - -
P003 137 - - - - Disabled - - "ADC0: AN03" - None - -
P004 136 - - - - Disabled - - "ADC0: AN04; ICU0: IRQ09" - None - -
P005 135 - - - - Disabled - - "ADC0: AN05; ICU0: IRQ10" - None - -
P006 134 - - - - Disabled - - "ADC0: AN06; ICU0: IRQ11" - None - -
P007 133 - - - - Disabled - - "ADC0: AN07" - None - -
P008 132 - - - - Disabled - - "ADC0: AN08; ICU0: IRQ12" - None - -
P009 131 - - - - Disabled - - "ADC0: AN09; ICU0: IRQ13" - None - -
P014 124 - - - - Disabled - - "ADC0: AN12; DAC0: DA" - None - -
P015 123 - - - - Disabled - - "ADC0: AN13; DAC1: DA; ICU0: IRQ13" - None - -
P100 108 SCI0_RXD - Low None "Peripheral mode" CMOS None "AGT0: AGTIO; BUS_ASYNCH0: D00; GPT_POEG0: GTETRG; GPT5: GTIOCB; ICU0: IRQ02; OSPI0: OMSCLK; QSPI0: QSPCLK; SCI0: RXD; SCI0: SCL; SCI1: SCK; SPI1: MISO" - IO - -
P101 107 SCI0_TXD - Low None "Peripheral mode" CMOS None "AGT0: AGTEE; BUS_ASYNCH0: D01; GPT_POEG1: GTETRG; GPT5: GTIOCA; ICU0: IRQ01; OSPI0: OMSIO7; QSPI0: QIO1; SCI0: SDA; SCI0: TXD; SCI1: CTSRTS; SPI1: MOSI" - IO - -
P102 106 - - - - Disabled - - "ADC0: ADTRG; AGT0: AGTO; BUS_ASYNCH0: D02; CAN0: CRX; GPT_OPS0: GTOWLO; GPT2: GTIOCB; OSPI0: OMSIO1; QSPI0: QIO0; SCI0: SCK; SPI1: RSPCK" - None - -
P103 105 - - - - Disabled - - "AGT2: AGTIO; BUS_ASYNCH0: D03; CAN0: CTX; GPT_OPS0: GTOWUP; GPT2: GTIOCA; OSPI0: OMSIO6; QSPI0: QIO3; SCI0: CTSRTS; SPI1: SSL0" - None - -
P104 104 - - - - Disabled - - "AGT2: AGTEE; BUS_ASYNCH0: D04; GPT_POEG1: GTETRG; GPT1: GTIOCB; ICU0: IRQ01; OSPI0: OMDQS; QSPI0: QIO2; SCI8: RXD; SCI8: SCL; SPI1: SSL1" - None - -
P105 103 - - - - Disabled - - "AGT2: AGTO; BUS_ASYNCH0: D05; GPT_POEG0: GTETRG; GPT1: GTIOCA; ICU0: IRQ00; OSPI0: OMSIO5; SCI8: SDA; SCI8: TXD; SPI1: SSL2" - None - -
P106 102 - - - - Disabled - - "AGT0: AGTOB; BUS_ASYNCH0: D06; GPT8: GTIOCB; OSPI0: OMSIO0; SCI8: SCK; SPI1: SSL3" - None - -
P107 101 - - - - Disabled - - "AGT0: AGTOA; BUS_ASYNCH0: D07; GPT8: GTIOCA; OSPI0: OMSIO3; SCI8: CTSRTS" - None - -
P108 73 DEBUG0_TMS - Low - "Peripheral mode" CMOS None "AGT3: AGTOA; DEBUG0: SWDIO; DEBUG0: TMS; GPT_OPS0: GTOULO; GPT0: GTIOCB; SCI9: CTSRTS; SPI0: SSL0" - IO - -
P109 74 DEBUG0_TDO - Low - "Peripheral mode" CMOS None "AGT3: AGTOB; CAN1: CTX; CGC0: CLKOUT; DEBUG0: TDO; DEBUG0: TRACESWO; GPT_OPS0: GTOVUP; GPT1: GTIOCA; SCI9: SDA; SCI9: TXD; SPI0: MOSI" - IO - -
P110 75 DEBUG0_TDI - Low None "Peripheral mode" CMOS None "AGT3: AGTEE; CAN1: CRX; DEBUG0: TDI; GPT_OPS0: GTOVLO; GPT1: GTIOCB; ICU0: IRQ03; SCI2: CTSRTS; SCI9: RXD; SCI9: SCL; SPI0: MISO" - IO - -
P111 76 - - - - Disabled - - "AGT5: AGTOA; BUS_ASYNCH0: A05; GPT3: GTIOCA; ICU0: IRQ04; SCI2: SCK; SCI9: SCK; SPI0: RSPCK" - None - -
P112 77 - - - - Disabled - - "AGT5: AGTOB; BUS_ASYNCH0: A04; GPT3: GTIOCB; OSPI0: OMCS1; QSPI0: QSSL; SCI1: SCK; SCI2: SDA; SCI2: TXD; SPI0: SSL0; SSI0: SSISCK" - None - -
P113 78 - - - - Disabled - - "AGT5: AGTEE; BUS_ASYNCH0: A03; GPT2: GTIOCA; SCI2: RXD; SCI2: SCL; SSI0: SSIWS" - None - -
P114 79 - - - - Disabled - - "AGT5: AGTIO; BUS_ASYNCH0: A02; GPT2: GTIOCB; SCI9: CTS; SSI0: SSIRXD" - None - -
P115 80 - - - - Disabled - - "BUS_ASYNCH0: A01; GPT4: GTIOCA; SSI0: SSITXD" - None - -
P200 57 - - - - Disabled - - "ICU0: NMI" - None - -
P201 56 - - - - Disabled - - "SYSTEM0: MD" - None - -
P202 46 - - - - Disabled - - "AGT3: AGTOB; BUS_ASYNCH0: BC1; CAN0: CRX; CTSU0: TS19; ETHERC_MII0: ERXD2; GPT5: GTIOCB; ICU0: IRQ03; SCI2: SCK; SCI9: RXD; SCI9: SCL; SDHI0: DAT6; SPI0: MISO" - None - -
P203 45 - - - - Disabled - - "AGT3: AGTOA; BUS_ASYNCH0: A19; CAN0: CTX; CTSU0: TS18; ETHERC_MII0: COL; GPT5: GTIOCA; ICU0: IRQ02; SCI2: CTSRTS; SCI9: SDA; SCI9: TXD; SDHI0: DAT5; SPI0: MOSI" - None - -
P204 44 - - - - Disabled - - "AGT1: AGTIO; BUS_ASYNCH0: A18; CAC0: CACREF; CTSU0: TS00; ETHERC_MII0: RX_DV; GPT_OPS0: GTIW; GPT4: GTIOCB; SCI4: SCK; SCI9: SCK; SDHI0: DAT4; SPI0: RSPCK; SSI0: SSISCK; USB_FS0: OVRCURB" - None - -
P205 43 - - - - Disabled - - "AGT1: AGTO; BUS_ASYNCH0: A16; CGC0: CLKOUT; CTSU0: TS01; ETHERC_MII0: WOL; ETHERC_RMII0: WOL; GPT_OPS0: GTIV; GPT4: GTIOCA; ICU0: IRQ01; IIC1: SCL; SCI4: SDA; SCI4: TXD; SCI9: CTSRTS; SDHI0: DAT3; SPI0: SSL0; SSI0: SSIWS; USB_FS0: OVRCURA" - None - -
P206 42 - - - - Disabled - - "BUS_ASYNCH0: WAIT; CTSU0: TS02; ETHERC_MII0: LINKSTA; ETHERC_RMII0: LINKSTA; GPT_OPS0: GTIU; ICU0: IRQ00; IIC1: SDA; SCI4: RXD; SCI4: SCL; SCI9: CTS; SDHI0: DAT2; SPI0: SSL1; SSI0: SSIDATA; USB_FS0: VBUSEN" - None - -
P207 41 - - - - Disabled - - "BUS_ASYNCH0: A17; CTSU0: TSCAP; QSPI0: QSSL; SCI4: SDA; SCI4: TXD; SPI0: SSL2" - None - -
P208 54 - - - - Disabled - - "BUS_ASYNCH0: CS4; DEBUG_TRACE0: TDATA3; ETHERC_MII0: LINKSTA; ETHERC_RMII0: LINKSTA; GPT_OPS0: GTOVLO; QSPI0: QIO3; SDHI0: DAT0" - None - -
P209 53 - - - - Disabled - - "AGT5: AGTEE; BUS_ASYNCH0: CS5; DEBUG_TRACE0: TDATA2; ETHERC_MII0: EXOUT; ETHERC_RMII0: EXOUT; GPT_OPS0: GTOVUP; QSPI0: QIO2; SDHI0: WP" - None - -
P210 52 - - - - Disabled - - "AGT5: AGTOB; BUS_ASYNCH0: CS6; DEBUG_TRACE0: TDATA1; ETHERC_MII0: WOL; ETHERC_RMII0: WOL; GPT_OPS0: GTIW; QSPI0: QIO1; SDHI0: CD" - None - -
P211 51 - - - - Disabled - - "AGT5: AGTOA; BUS_ASYNCH0: CS7; DEBUG_TRACE0: TDATA0; ETHERC_MII0: MDIO; ETHERC_RMII0: MDIO; GPT_OPS0: GTIV; QSPI0: QIO0; SDHI0: CMD" - None - -
P212 20 - - - - Disabled - - "AGT1: AGTEE; CGC0: EXTAL; GPT_POEG3: GTETRG; GPT0: GTIOCB; ICU0: IRQ03; SCI1: RXD; SCI1: SCL" - None - -
P213 19 - - - - Disabled - - "ADC1: ADTRG; AGT2: AGTEE; CGC0: XTAL; GPT_POEG2: GTETRG; GPT0: GTIOCA; ICU0: IRQ02; SCI1: SDA; SCI1: TXD" - None - -
P214 50 - - - - Disabled - - "AGT5: AGTO; DEBUG_TRACE0: TCLK; ETHERC_MII0: MDC; ETHERC_RMII0: MDC; GPT_OPS0: GTIU; QSPI0: QSPCLK; SDHI0: CLK" - None - -
P300 72 DEBUG0_TCK - Low - "Peripheral mode" CMOS None "DEBUG0: SWCLK; DEBUG0: TCK; GPT_OPS0: GTOUUP; GPT0: GTIOCA; SPI0: SSL1" - IO - -
P301 71 - - - - Disabled - - "AGT0: AGTIO; BUS_ASYNCH0: A06; GPT_OPS0: GTOULO; GPT4: GTIOCB; ICU0: IRQ06; SCI2: RXD; SCI2: SCL; SCI9: CTSRTS; SPI0: SSL2" - None - -
P302 70 - - - - Disabled - - "BUS_ASYNCH0: A07; GPT_OPS0: GTOUUP; GPT4: GTIOCA; ICU0: IRQ05; SCI2: SDA; SCI2: TXD; SPI0: SSL3" - None - -
P303 69 - - - - Disabled - - "BUS_ASYNCH0: A08; GPT7: GTIOCB; SCI9: CTS" - None - -
P304 66 - - - - Disabled - - "AGT2: AGTEE; BUS_ASYNCH0: A09; GPT_OPS0: GTOWLO; GPT7: GTIOCA; ICU0: IRQ09; SCI6: RXD; SCI6: SCL" - None - -
P305 65 - - - - Disabled - - "AGT2: AGTOB; BUS_ASYNCH0: A10; GPT_OPS0: GTOWUP; ICU0: IRQ08; QSPI0: QSPCLK; SCI6: SDA; SCI6: TXD" - None - -
P306 64 - - - - Disabled - - "AGT2: AGTOA; BUS_ASYNCH0: A11; GPT_OPS0: GTOULO; QSPI0: QSSL; SCI6: SCK" - None - -
P307 63 - - - - Disabled - - "AGT4: AGTEE; BUS_ASYNCH0: A12; GPT_OPS0: GTOUUP; QSPI0: QIO0; SCI6: CTSRTS" - None - -
P308 62 - - - - Disabled - - "AGT4: AGTOB; BUS_ASYNCH0: A13; QSPI0: QIO1; SCI3: CTS; SCI6: CTS" - None - -
P309 61 - - - - Disabled - - "AGT4: AGTOA; BUS_ASYNCH0: A14; QSPI0: QIO2; SCI3: RXD; SCI3: SCL" - None - -
P310 60 - - - - Disabled - - "AGT1: AGTEE; BUS_ASYNCH0: A15; QSPI0: QIO3; SCI3: SDA; SCI3: TXD" - None - -
P311 59 - - - - Disabled - - "AGT1: AGTOB; BUS_ASYNCH0: CS2; SCI3: SCK" - None - -
P312 58 - - - - Disabled - - "AGT1: AGTOA; BUS_ASYNCH0: CS3; SCI3: CTSRTS" - None - -
P313 47 - - - - Disabled - - "BUS_ASYNCH0: A20; ETHERC_MII0: ERXD3; SDHI0: DAT7" - None - -
P400 1 - - - - Disabled - - "ADC1: ADTRG; AGT1: AGTIO; ETHERC_MII0: WOL; ETHERC_RMII0: WOL; GPT6: GTIOCA; ICU0: IRQ00; IIC0: SCL; SCI4: SCK; SCI7: SCK; SSI_COMMON0: AUDIO_CLK" - None - -
P401 2 - - - - Disabled - - "CAN0: CTX; ETHERC_MII0: MDC; ETHERC_RMII0: MDC; GPT_POEG0: GTETRG; GPT6: GTIOCB; ICU0: IRQ05; IIC0: SDA; SCI4: CTSRTS; SCI7: SDA; SCI7: TXD" - None - -
P402 3 - - - - Disabled - - "AGT0: AGTIO; AGT1: AGTIO; AGT2: AGTIO; AGT3: AGTIO; CAC0: CACREF; CAN0: CRX; ETHERC_MII0: MDIO; ETHERC_RMII0: MDIO; ICU0: IRQ04; RTC0: RTCIC0; SCI4: CTS; SCI7: RXD; SCI7: SCL; SSI_COMMON0: AUDIO_CLK" - None - -
P403 4 - - - - Disabled - - "AGT0: AGTIO; AGT1: AGTIO; AGT2: AGTIO; AGT3: AGTIO; ETHERC_MII0: LINKSTA; ETHERC_RMII0: LINKSTA; GPT3: GTIOCA; ICU0: IRQ14; RTC0: RTCIC1; SCI7: CTSRTS; SSI0: SSISCK" - None - -
P404 5 - - - - Disabled - - "AGT0: AGTIO; AGT1: AGTIO; AGT2: AGTIO; AGT3: AGTIO; ETHERC_MII0: EXOUT; ETHERC_RMII0: EXOUT; GPT3: GTIOCB; ICU0: IRQ15; RTC0: RTCIC2; SCI7: CTS; SSI0: SSIWS" - None - -
P405 6 - - - - Disabled - - "ETHERC_MII0: TX_EN; ETHERC_RMII0: TXD_EN; GPT1: GTIOCA; SSI0: SSITXD" - None - -
P406 7 - - - - Disabled - - "AGT5: AGTO; ETHERC_MII0: RX_ER; ETHERC_RMII0: TXD1; GPT1: GTIOCB; SPI0: SSL3; SSI0: SSIRXD" - None - -
P407 36 - - - - Disabled - - "ADC0: ADTRG; AGT0: AGTIO; CTSU0: TS03; ETHERC_MII0: EXOUT; ETHERC_RMII0: EXOUT; GPT6: GTIOCA; IIC0: SDA; RTC0: RTCOUT; SCI4: CTSRTS; SPI0: SSL3; USB_FS0: VBUS" - None - -
P408 35 - - - - Disabled - - "AGT2: AGTOB; CTSU0: TS04; ETHERC_MII0: CRS; ETHERC_RMII0: CRS_DV; GPT_OPS0: GTOWLO; GPT6: GTIOCB; ICU0: IRQ07; IIC0: SCL; SCI3: RXD; SCI3: SCL; SCI4: CTS; USB_FS0: ID" - None - -
P409 34 - - - - Disabled - - "AGT2: AGTOA; CTSU0: TS05; ETHERC_MII0: RX_CLK; ETHERC_RMII0: RX_ER; GPT_OPS0: GTOWUP; ICU0: IRQ06; SCI3: SDA; SCI3: TXD; USB_FS0: EXICEN" - None - -
P410 33 - - - - Disabled - - "AGT1: AGTOB; CTSU0: TS06; ETHERC_MII0: ERXD0; ETHERC_RMII0: RXD1; GPT_OPS0: GTOVLO; GPT9: GTIOCB; ICU0: IRQ05; SCI0: RXD; SCI0: SCL; SCI3: SCK; SDHI0: DAT1; SPI1: MISO" - None - -
P411 32 - - - - Disabled - - "AGT1: AGTOA; CTSU0: TS07; ETHERC_MII0: ERXD1; ETHERC_RMII0: RXD0; GPT_OPS0: GTOVUP; GPT9: GTIOCA; ICU0: IRQ04; SCI0: SDA; SCI0: TXD; SCI3: CTSRTS; SDHI0: DAT0; SPI1: MOSI" - None - -
P412 31 - - - - Disabled - - "AGT1: AGTEE; CTSU0: TS08; ETHERC_MII0: ETXD0; ETHERC_RMII0: REF50CK; GPT_OPS0: GTOULO; SCI0: SCK; SCI3: CTS; SDHI0: CMD; SPI1: RSPCK" - None - -
P413 30 - - - - Disabled - - "AGT3: AGTEE; CTSU0: TS09; ETHERC_MII0: ETXD1; ETHERC_RMII0: TXD0; GPT_OPS0: GTOUUP; SCI0: CTSRTS; SDHI0: CLK; SPI1: SSL0" - None - -
P414 29 - - - - Disabled - - "AGT5: AGTIO; CTSU0: TS10; ETHERC_MII0: RX_ER; ETHERC_RMII0: TXD1; GPT0: GTIOCB; ICU0: IRQ09; SCI0: CTS; SDHI0: WP; SPI1: SSL1" - None - -
P415 28 - - - - Disabled - - "AGT4: AGTIO; CTSU0: TS11; ETHERC_MII0: TX_EN; ETHERC_RMII0: TXD_EN; GPT0: GTIOCA; ICU0: IRQ08; SDHI0: CD; SPI1: SSL2; USB_FS0: VBUSEN" - None - -
P500 113 - - - - Disabled - - "ADC1: AN16; AGT0: AGTOA; CAC0: CACREF; GPT_OPS0: GTIU; QSPI0: QSPCLK; SCI5: CTS; USB_FS0: VBUSEN" - None - -
P501 114 - - - - Disabled - - "ADC1: AN17; AGT0: AGTOB; GPT_OPS0: GTIV; ICU0: IRQ11; QSPI0: QSSL; SCI5: SDA; SCI5: TXD; USB_FS0: OVRCURA" - None - -
P502 115 - - - - Disabled - - "ADC1: AN18; AGT2: AGTOA; GPT_OPS0: GTIW; ICU0: IRQ12; QSPI0: QIO0; SCI5: RXD; SCI5: SCL; SCI6: CTS; USB_FS0: OVRCURB" - None - -
P503 116 - - - - Disabled - - "ADC1: AN19; AGT2: AGTOB; GPT_POEG2: GTETRG; QSPI0: QIO1; SCI5: SCK; SCI6: CTSRTS; USB_FS0: EXICEN" - None - -
P504 117 - - - - Disabled - - "ADC1: AN20; AGT3: AGTOA; BUS_ASYNCH0: ALE; GPT_POEG3: GTETRG; QSPI0: QIO2; SCI5: CTSRTS; SCI6: SCK; USB_FS0: ID" - None - -
P505 118 - - - - Disabled - - "ADC1: AN21; AGT3: AGTOB; ICU0: IRQ14; QSPI0: QIO3; SCI6: RXD; SCI6: SCL" - None - -
P506 119 - - - - Disabled - - "ADC1: AN22; ICU0: IRQ15; SCI6: SDA; SCI6: TXD" - None - -
P507 120 - - - - Disabled - - "SCI5: SCK; SCI6: SCK" - None - -
P511 144 - - - - Disabled - - "CAN1: CRX; GPT0: GTIOCB; ICU0: IRQ15; IIC1: SDA; SCI4: RXD; SCI4: SCL" - None - -
P512 143 - - - - Disabled - - "CAN1: CTX; GPT0: GTIOCA; ICU0: IRQ14; IIC1: SCL; SCI4: SDA; SCI4: TXD" - None - -
P600 98 - - - - Disabled - - "AGT3: AGTIO; BUS_ASYNCH0: RD; CAC0: CACREF; CGC0: CLKOUT; GPT6: GTIOCB; OSPI0: OMSIO4; SCI9: SCK" - None - -
P601 97 - - - - Disabled - - "AGT3: AGTEE; BUS_ASYNCH0: WR; GPT6: GTIOCA; OSPI0: OMSIO2; SCI9: RXD; SCI9: SCL" - None - -
P602 96 - - - - Disabled - - "AGT3: AGTO; BUS_ASYNCH0: EBCLK; GPT7: GTIOCB; OSPI0: OMCS1; SCI9: SDA; SCI9: TXD" - None - -
P603 95 - - - - Disabled - - "AGT4: AGTIO; BUS_ASYNCH0: D13; GPT7: GTIOCA; SCI9: CTSRTS" - None - -
P604 94 - - - - Disabled - - "AGT4: AGTEE; BUS_ASYNCH0: D12; GPT8: GTIOCB; SCI9: CTS" - None - -
P605 93 - - - - Disabled - - "AGT4: AGTO; BUS_ASYNCH0: D11; GPT8: GTIOCA; SCI8: CTS" - None - -
P608 83 - - - - Disabled - - "BUS_ASYNCH0: A00; GPT4: GTIOCB" - None - -
P609 84 - - - - Disabled - - "AGT5: AGTO; BUS_ASYNCH0: CS1; CAN1: CTX; GPT5: GTIOCA" - None - -
P610 85 - - - - Disabled - - "AGT4: AGTO; BUS_ASYNCH0: CS0; CAN1: CRX; GPT5: GTIOCB; OSPI0: OMCS0; SCI7: CTS" - None - -
P611 86 - - - - Disabled - - "AGT3: AGTO; CAC0: CACREF; CGC0: CLKOUT; SCI7: CTSRTS" - None - -
P612 87 - - - - Disabled - - "AGT2: AGTO; BUS_ASYNCH0: D08; SCI7: SCK" - None - -
P613 88 - - - - Disabled - - "AGT1: AGTO; BUS_ASYNCH0: D09; SCI7: SDA; SCI7: TXD" - None - -
P614 89 - - - - Disabled - - "AGT0: AGTO; BUS_ASYNCH0: D10; SCI7: RXD; SCI7: SCL" - None - -
P700 8 - - - - Disabled - - "AGT4: AGTO; ETHERC_MII0: ETXD1; ETHERC_RMII0: TXD0; GPT5: GTIOCA; SPI0: MISO" - None - -
P701 9 - - - - Disabled - - "AGT3: AGTO; ETHERC_MII0: ETXD0; ETHERC_RMII0: REF50CK; GPT5: GTIOCB; SPI0: MOSI" - None - -
P702 10 - - - - Disabled - - "AGT2: AGTO; ETHERC_MII0: ERXD1; ETHERC_RMII0: RXD0; GPT6: GTIOCA; SPI0: RSPCK" - None - -
P703 11 - - - - Disabled - - "AGT1: AGTO; ETHERC_MII0: ERXD0; ETHERC_RMII0: RXD1; GPT6: GTIOCB; SPI0: SSL0" - None - -
P704 12 - - - - Disabled - - "AGT0: AGTO; CAN0: CTX; ETHERC_MII0: RX_CLK; ETHERC_RMII0: RX_ER; SPI0: SSL1" - None - -
P705 13 - - - - Disabled - - "AGT0: AGTIO; CAN0: CRX; ETHERC_MII0: CRS; ETHERC_RMII0: CRS_DV; SCI3: CTS; SPI0: SSL2" - None - -
P708 27 - - - - Disabled - - "CAC0: CACREF; CTSU0: TS12; ETHERC_MII0: ETXD3; ICU0: IRQ11; SCI1: RXD; SCI1: SCL; SPI1: SSL3; SSI_COMMON0: AUDIO_CLK" - None - -
P709 26 - - - - Disabled - - "CTSU0: TS13; ETHERC_MII0: ETXD2; ICU0: IRQ10; SCI1: SDA; SCI1: TXD" - None - -
P710 25 - - - - Disabled - - "CTSU0: TS14; ETHERC_MII0: TX_ER; SCI1: SCK" - None - -
P711 24 - - - - Disabled - - "AGT0: AGTEE; CTSU0: TS15; ETHERC_MII0: TX_CLK; SCI1: CTSRTS" - None - -
P712 23 - - - - Disabled - - "AGT0: AGTOB; CTSU0: TS16; GPT2: GTIOCB" - None - -
P713 22 - - - - Disabled - - "AGT0: AGTOA; CTSU0: TS17; GPT2: GTIOCA" - None - -
P800 109 - - - - Disabled - - "AGT4: AGTOA; BUS_ASYNCH0: D14; SCI0: CTS" - None - -
P801 110 - - - - Disabled - - "AGT4: AGTOB; BUS_ASYNCH0: D15; SCI8: CTS" - None - -
RES 55 SYSTEM0_RES - - - - - - - - IO "Read only" -
USBDM 38 USB_FS0_DM - - - - - - - - IO "Read only" -
USBDP 39 USB_FS0_DP - - - - - - - - IO "Read only" -
VBATT 14 SYSTEM0_VBATT - - - - - - - - IO "Read only" -
VCC 21 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 49 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 68 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 81 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 90 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 99 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 111 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 121 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCC 142 SYSTEM0_VCC - - - - - - - - IO "Read only" -
VCCUSB 40 USB_FS0_VCC - - - - - - - - IO "Read only" -
VCL 92 SYSTEM0_VCL - - - - - - - - IO "Read only" -
VCL0 15 SYSTEM0_VCL0 - - - - - - - - IO "Read only" -
VREFH 126 ANALOG0_VREFH - - - - - - - - IO "Read only" -
VREFH0 130 ANALOG0_VREFH0 - - - - - - - - IO "Read only" -
VREFL 125 ANALOG0_VREFL - - - - - - - - IO "Read only" -
VREFL0 129 ANALOG0_VREFL0 - - - - - - - - IO "Read only" -
VSS 18 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 48 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 67 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 82 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 91 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 100 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 112 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 122 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSS 141 SYSTEM0_VSS - - - - - - - - IO "Read only" -
VSSUSB 37 USB_FS0_VSS - - - - - - - - IO "Read only" -
XCIN 16 CGC0_XCIN - - - - - - - - IO "Read only" -
XCOUT 17 CGC0_XCOUT - - - - - - - - IO "Read only" -
User Events
User Event Links
Module "I/O Port Driver on r_ioport"
Parameter Checking: Default (BSP)
Module "UART Driver on r_sci_uart"
Parameter Checking: Default (BSP)
FIFO Support: Disable
DTC Support: Disable
RS232/RS485 Flow Control Support: Disable
HAL
Instance "g_ioport I/O Port Driver on r_ioport"
Name: g_ioport
Port 1 ELC Trigger Source: Disabled
Port 2 ELC Trigger Source: Disabled
Port 3 ELC Trigger Source: Disabled
Port 4 ELC Trigger Source: Disabled
Instance "g_uart0 UART Driver on r_sci_uart"
General: Name: g_uart0
General: Channel: 0
General: Data Bits: 8bits
General: Parity: None
General: Stop Bits: 1bit
Baud: Baud Rate: 115200
Baud: Baud Rate Modulation: Disabled
Baud: Max Error (%): 5
Flow Control: CTS/RTS Selection: RTS (CTS is disabled)
Flow Control: UART Communication Mode: RS232
Flow Control: Pin Control: Disabled
Flow Control: RTS Port: Disabled
Flow Control: RTS Pin: Disabled
Extra: Clock Source: Internal Clock
Extra: Start bit detection: Falling Edge
Extra: Noise Filter: Disable
Extra: Receive FIFO Trigger Level: Max
Interrupts: Callback: user_uart_callback
Interrupts: Receive Interrupt Priority: Priority 12
Interrupts: Transmit Data Empty Interrupt Priority: Priority 12
Interrupts: Transmit End Interrupt Priority: Priority 12
Interrupts: Error Interrupt Priority: Priority 12

5
board/Renesas_ra6m4/ra_cfg/fsp_cfg/bsp/board_cfg.h Normal file
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@@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BOARD_CFG_H_
#define BOARD_CFG_H_
void bsp_init(void * p_args);
#endif /* BOARD_CFG_H_ */

49
board/Renesas_ra6m4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h Normal file
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@@ -0,0 +1,49 @@
/* generated configuration header file - do not edit */
#ifndef BSP_CFG_H_
#define BSP_CFG_H_
#include "bsp_clock_cfg.h"
#include "bsp_mcu_family_cfg.h"
#include "board_cfg.h"
#define RA_NOT_DEFINED 0
#ifndef BSP_CFG_RTOS
#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (2)
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
#define BSP_CFG_RTOS (1)
#else
#define BSP_CFG_RTOS (0)
#endif
#endif
#undef RA_NOT_DEFINED
#define BSP_CFG_MCU_VCC_MV (3300)
#define BSP_CFG_STACK_MAIN_BYTES (0x400)
#define BSP_CFG_HEAP_BYTES (0)
#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
#define BSP_CFG_ASSERT (0)
#define BSP_CFG_ERROR_LOG (0)
#define BSP_CFG_PFS_PROTECT ((1))
#define BSP_CFG_C_RUNTIME_INIT ((1))
#define BSP_CFG_SOFT_RESET_SUPPORTED ((0))
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
#endif
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
#endif
#endif /* BSP_CFG_H_ */

5
board/Renesas_ra6m4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h Normal file
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@@ -0,0 +1,5 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_CFG_H_
#define BSP_MCU_DEVICE_CFG_H_
#define BSP_CFG_MCU_PART_SERIES (6)
#endif /* BSP_MCU_DEVICE_CFG_H_ */

10
board/Renesas_ra6m4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h Normal file
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@@ -0,0 +1,10 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_DEVICE_PN_CFG_H_
#define BSP_MCU_R7FA6M4AF3CFB
#define BSP_ROM_SIZE_BYTES (1048576)
#define BSP_RAM_SIZE_BYTES (262144)
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
#define BSP_PACKAGE_LQFP
#define BSP_PACKAGE_PINS (144)
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

360
board/Renesas_ra6m4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h Normal file
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@@ -0,0 +1,360 @@
/* generated configuration header file - do not edit */
#ifndef BSP_MCU_FAMILY_CFG_H_
#define BSP_MCU_FAMILY_CFG_H_
#include "bsp_mcu_device_pn_cfg.h"
#include "bsp_mcu_device_cfg.h"
#include "../../../ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h"
#include "bsp_clock_cfg.h"
#define BSP_MCU_GROUP_RA6M4 (1)
#define BSP_LOCO_HZ (32768)
#define BSP_MOCO_HZ (8000000)
#define BSP_SUB_CLOCK_HZ (32768)
#if BSP_CFG_HOCO_FREQUENCY == 0
#define BSP_HOCO_HZ (16000000)
#elif BSP_CFG_HOCO_FREQUENCY == 1
#define BSP_HOCO_HZ (18000000)
#elif BSP_CFG_HOCO_FREQUENCY == 2
#define BSP_HOCO_HZ (20000000)
#else
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
#endif
#define BSP_CFG_FLL_ENABLE (0)
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
#define BSP_MCU_VBATT_SUPPORT (1)
#if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
#define BSP_TZ_NONSECURE_BUILD (0)
#elif defined(_RA_TZ_NONSECURE)
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (1)
#else
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (0)
#endif
/* TrustZone Settings */
#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
/* CMSIS TrustZone Settings */
#define SCB_CSR_AIRCR_INIT (1)
#define SCB_AIRCR_BFHFNMINS_VAL (0)
#define SCB_AIRCR_SYSRESETREQS_VAL (1)
#define SCB_AIRCR_PRIS_VAL (0)
#define TZ_FPU_NS_USAGE (1)
#ifndef SCB_NSACR_CP10_11_VAL
#define SCB_NSACR_CP10_11_VAL (3U)
#endif
#ifndef FPU_FPCCR_TS_VAL
#define FPU_FPCCR_TS_VAL (1U)
#endif
#define FPU_FPCCR_CLRONRETS_VAL (1)
#ifndef FPU_FPCCR_CLRONRET_VAL
#define FPU_FPCCR_CLRONRET_VAL (1)
#endif
/* The C-Cache line size that is configured during startup. */
#ifndef BSP_CFG_C_CACHE_LINE_SIZE
#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
#endif
/* Type 1 Peripheral Security Attribution */
/* Peripheral Security Attribution Register (PSAR) Settings */
#ifndef BSP_TZ_CFG_PSARB
#define BSP_TZ_CFG_PSARB (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
(((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
0x33f4f9) /* Unused */
#endif
#ifndef BSP_TZ_CFG_PSARC
#define BSP_TZ_CFG_PSARC (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
0x7fffcef4) /* Unused */
#endif
#ifndef BSP_TZ_CFG_PSARD
#define BSP_TZ_CFG_PSARD (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
0xffae07f0) /* Unused */
#endif
#ifndef BSP_TZ_CFG_PSARE
#define BSP_TZ_CFG_PSARE (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
0x3f3ff8) /* Unused */
#endif
#ifndef BSP_TZ_CFG_MSSAR
#define BSP_TZ_CFG_MSSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
0xfffffffc) /* Unused */
#endif
/* Type 2 Peripheral Security Attribution */
/* Security attribution for Cache registers. */
#ifndef BSP_TZ_CFG_CSAR
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
#endif
/* Security attribution for RSTSRn registers. */
#ifndef BSP_TZ_CFG_RSTSAR
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
#endif
/* Security attribution for registers of LVD channels. */
#ifndef BSP_TZ_CFG_LVDSAR
#define BSP_TZ_CFG_LVDSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
0xFFFFFFFCU)
#endif
/* Security attribution for LPM registers. */
#ifndef BSP_TZ_CFG_LPMSAR
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
#endif
/* Deep Standby Interrupt Factor Security Attribution Register. */
#ifndef BSP_TZ_CFG_DPFSAR
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
#endif
/* Security attribution for CGC registers. */
#ifndef BSP_TZ_CFG_CGFSAR
#if BSP_CFG_CLOCKS_SECURE
/* Protect all CGC registers from Non-secure write access. */
#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
#else
/* Allow Secure and Non-secure write access. */
#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
#endif
#endif
/* Security attribution for Battery Backup registers. */
#ifndef BSP_TZ_CFG_BBFSAR
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
#endif
/* Security attribution for registers for IRQ channels. */
#ifndef BSP_TZ_CFG_ICUSARA
#define BSP_TZ_CFG_ICUSARA (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
0xFFFF0000U)
#endif
/* Security attribution for NMI registers. */
#ifndef BSP_TZ_CFG_ICUSARB
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
#endif
/* Security attribution for registers for DMAC channels */
#ifndef BSP_TZ_CFG_ICUSARC
#define BSP_TZ_CFG_ICUSARC (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
0xFFFFFF00U)
#endif
/* Security attribution registers for SELSR0. */
#ifndef BSP_TZ_CFG_ICUSARD
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
#endif
/* Security attribution registers for WUPEN0. */
#ifndef BSP_TZ_CFG_ICUSARE
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
#endif
/* Security attribution registers for WUPEN1. */
#ifndef BSP_TZ_CFG_ICUSARF
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
#endif
/* Set DTCSTSAR if the Secure program uses the DTC. */
#if RA_NOT_DEFINED == RA_NOT_DEFINED
#define BSP_TZ_CFG_DTC_USED (0U)
#else
#define BSP_TZ_CFG_DTC_USED (1U)
#endif
/* Security attribution of FLWT and FCKMHZ registers. */
#ifndef BSP_TZ_CFG_FSAR
/* If the CGC registers are only accessible in Secure mode, than there is no
* reason for nonsecure applications to access FLWT and FCKMHZ. */
#if BSP_CFG_CLOCKS_SECURE
/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
#define BSP_TZ_CFG_FSAR (0xFEFEU)
#else
/* Allow Secure and Non-secure write access. */
#define BSP_TZ_CFG_FSAR (0xFFFFU)
#endif
#endif
/* Security attribution for SRAM registers. */
#ifndef BSP_TZ_CFG_SRAMSAR
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
#define BSP_TZ_CFG_SRAMSAR (\
1 | \
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
4 | \
0xFFFFFFF8U)
#endif
/* Security attribution for Standby RAM registers. */
#ifndef BSP_TZ_CFG_STBRAMSAR
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
#endif
/* Security attribution for the DMAC Bus Master MPU settings. */
#ifndef BSP_TZ_CFG_MMPUSARA
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
#endif
/* Security Attribution Register A for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARA
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
#endif
/* Security Attribution Register B for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARB
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
#endif
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
#define OFS_SEQ5 (1 << 28) | (1 << 30)
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/* Option Function Select Register 1 Security Attribution */
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
#else
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
#endif
#endif
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
/* Dual Mode Select Register */
#ifndef BSP_CFG_ROM_REG_DUALSEL
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
#endif
/* Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_BPS0
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
#endif
/* Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_BPS1
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
#endif
/* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
#endif
/* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
#endif
/* Permanent Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_PBPS1
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
#endif
/* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
#endif
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
#endif
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
#endif
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
#endif
#endif /* BSP_MCU_FAMILY_CFG_H_ */

8
board/Renesas_ra6m4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h Normal file
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/* generated configuration header file - do not edit */
#ifndef BSP_PIN_CFG_H_
#define BSP_PIN_CFG_H_
#include "r_ioport.h"
extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M4AF3CFB.pincfg */
void BSP_PinConfigSecurityInit();
#endif /* BSP_PIN_CFG_H_ */

5
board/Renesas_ra6m4/ra_cfg/fsp_cfg/r_ioport_cfg.h Normal file
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/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#endif /* R_IOPORT_CFG_H_ */

8
board/Renesas_ra6m4/ra_cfg/fsp_cfg/r_sci_uart_cfg.h Normal file
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/* generated configuration header file - do not edit */
#ifndef R_SCI_UART_CFG_H_
#define R_SCI_UART_CFG_H_
#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define SCI_UART_CFG_FIFO_SUPPORT (0)
#define SCI_UART_CFG_DTC_SUPPORTED (0)
#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0)
#endif /* R_SCI_UART_CFG_H_ */

29
board/Renesas_ra6m4/ra_gen/bsp_clock_cfg.h Normal file
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/* generated configuration header file - do not edit */
#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* PLL Src: HOCO */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCLK Disabled */
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
#define BSP_CFG_BCLK_OUTPUT (2) /* BCLK/2 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
#endif /* BSP_CLOCK_CFG_H_ */

11
board/Renesas_ra6m4/ra_gen/common_data.c Normal file
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/* generated common source file - do not edit */
#include "common_data.h"
ioport_instance_ctrl_t g_ioport_ctrl;
const ioport_instance_t g_ioport =
{
.p_api = &g_ioport_on_ioport,
.p_ctrl = &g_ioport_ctrl,
.p_cfg = &g_bsp_pin_cfg,
};
void g_common_init(void) {
}

16
board/Renesas_ra6m4/ra_gen/common_data.h Normal file
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/* generated common header file - do not edit */
#ifndef COMMON_DATA_H_
#define COMMON_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "r_ioport.h"
#include "bsp_pin_cfg.h"
FSP_HEADER
/* IOPORT Instance */
extern const ioport_instance_t g_ioport;
/* IOPORT control structure. */
extern ioport_instance_ctrl_t g_ioport_ctrl;
void g_common_init(void);
FSP_FOOTER
#endif /* COMMON_DATA_H_ */

84
board/Renesas_ra6m4/ra_gen/hal_data.c Normal file
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/* generated HAL source file - do not edit */
#include "hal_data.h"
sci_uart_instance_ctrl_t g_uart0_ctrl;
baud_setting_t g_uart0_baud_setting =
{
/* Baud rate calculated with 0.469% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t) 256, .brme = false
};
/** UART extended configuration for UARTonSCI HAL driver */
const sci_uart_extended_cfg_t g_uart0_cfg_extend =
{
.clock = SCI_UART_CLOCK_INT,
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
.p_baud_setting = &g_uart0_baud_setting,
.uart_mode = UART_MODE_RS232,
.ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT,
#if 0
.flow_control_pin = BSP_IO_PORT_00_PIN_00,
#else
.flow_control_pin = (bsp_io_port_pin_t) (0xFFFFU),
#endif
};
/** UART interface configuration */
const uart_cfg_t g_uart0_cfg =
{
.channel = 0,
.data_bits = UART_DATA_BITS_8,
.parity = UART_PARITY_OFF,
.stop_bits = UART_STOP_BITS_1,
.p_callback = user_uart_callback,
.p_context = NULL,
.p_extend = &g_uart0_cfg_extend,
#define RA_NOT_DEFINED (1)
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_tx = NULL,
#else
.p_transfer_tx = &RA_NOT_DEFINED,
#endif
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
.p_transfer_rx = NULL,
#else
.p_transfer_rx = &RA_NOT_DEFINED,
#endif
#undef RA_NOT_DEFINED
.rxi_ipl = (12),
.txi_ipl = (12),
.tei_ipl = (12),
.eri_ipl = (12),
#if defined(VECTOR_NUMBER_SCI0_RXI)
.rxi_irq = VECTOR_NUMBER_SCI0_RXI,
#else
.rxi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TXI)
.txi_irq = VECTOR_NUMBER_SCI0_TXI,
#else
.txi_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_TEI)
.tei_irq = VECTOR_NUMBER_SCI0_TEI,
#else
.tei_irq = FSP_INVALID_VECTOR,
#endif
#if defined(VECTOR_NUMBER_SCI0_ERI)
.eri_irq = VECTOR_NUMBER_SCI0_ERI,
#else
.eri_irq = FSP_INVALID_VECTOR,
#endif
};
/* Instance structure to use this module. */
const uart_instance_t g_uart0 =
{
.p_ctrl = &g_uart0_ctrl,
.p_cfg = &g_uart0_cfg,
.p_api = &g_uart_on_sci
};
void g_hal_init(void) {
g_common_init();
}

24
board/Renesas_ra6m4/ra_gen/hal_data.h Normal file
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/* generated HAL header file - do not edit */
#ifndef HAL_DATA_H_
#define HAL_DATA_H_
#include <stdint.h>
#include "bsp_api.h"
#include "common_data.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
FSP_HEADER
/** UART on SCI Instance. */
extern const uart_instance_t g_uart0;
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
extern sci_uart_instance_ctrl_t g_uart0_ctrl;
extern const uart_cfg_t g_uart0_cfg;
extern const sci_uart_extended_cfg_t g_uart0_cfg_extend;
#ifndef user_uart_callback
void user_uart_callback(uart_callback_args_t * p_args);
#endif
void hal_entry(void);
void g_hal_init(void);
FSP_FOOTER
#endif /* HAL_DATA_H_ */

6
board/Renesas_ra6m4/ra_gen/main.c Normal file
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/* generated main source file - do not edit */
#include "hal_data.h"
int main(void) {
hal_entry();
return 0;
}

65
board/Renesas_ra6m4/ra_gen/pin_data.c Normal file
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/* generated pin source file - do not edit */
#include "bsp_api.h"
#include "r_ioport_api.h"
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
{
.pin = BSP_IO_PORT_01_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
},
{
.pin = BSP_IO_PORT_01_PIN_01,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
},
{
.pin = BSP_IO_PORT_01_PIN_08,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
},
{
.pin = BSP_IO_PORT_01_PIN_09,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
},
{
.pin = BSP_IO_PORT_01_PIN_10,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
},
{
.pin = BSP_IO_PORT_03_PIN_00,
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
},
};
const ioport_cfg_t g_bsp_pin_cfg = {
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
};
#if BSP_TZ_SECURE_BUILD
#define BSP_PRV_NUM_PMSAR (sizeof(R_PMISC->PMSAR) / sizeof(R_PMISC->PMSAR[0]))
void R_BSP_PinCfgSecurityInit(void);
/* Initialize SAR registers for secure pins. */
void R_BSP_PinCfgSecurityInit(void)
{
uint16_t pmsar[BSP_PRV_NUM_PMSAR];
memset(pmsar, 0xFF, BSP_PRV_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
{
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
uint32_t port = port_pin >> 8U;
uint32_t pin = port_pin & 0xFFU;
pmsar[port] &= (uint16_t) ~(1U << pin);
}
for(uint32_t i = 0; i < BSP_PRV_NUM_PMSAR; i++)
{
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
}
}
#endif

19
board/Renesas_ra6m4/ra_gen/vector_data.c Normal file
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/* generated vector source file - do not edit */
#include "bsp_api.h"
/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
#if VECTOR_DATA_IRQ_COUNT > 0
BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
{
[0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */
[1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */
[2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */
[3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
[0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */
[1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */
[2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */
[3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */
};
#endif

36
board/Renesas_ra6m4/ra_gen/vector_data.h Normal file
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/* generated vector header file - do not edit */
#ifndef VECTOR_DATA_H
#define VECTOR_DATA_H
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
#define VECTOR_DATA_IRQ_COUNT (4)
#endif
/* ISR prototypes */
void sci_uart_rxi_isr(void);
void sci_uart_txi_isr(void);
void sci_uart_tei_isr(void);
void sci_uart_eri_isr(void);
/* Vector table allocations */
#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 0) /* SCI0 RXI (Receive data full) */
#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 1) /* SCI0 TXI (Transmit data empty) */
#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 2) /* SCI0 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 3) /* SCI0 ERI (Receive error) */
typedef enum IRQn {
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SecureFault_IRQn = -9,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */
SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */
SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */
SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */
} IRQn_Type;
#endif /* VECTOR_DATA_H */

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