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add mqttclient_iot_explorer demo on tos_evb_aiot board

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mculover666
2021-12-25 14:18:16 +08:00
parent e02178dd84
commit 9fb07d7c2c
46 changed files with 14273 additions and 34 deletions
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111
board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_flexspi_nor.scf Normal file
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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#if (defined(__ram_vector_table__))
#define __ram_vector_table_size__ 0x00000400
#else
#define __ram_vector_table_size__ 0x00000000
#endif
#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000
#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x007FDC00
#define m_interrupts_ram_start 0x20000000
#define m_interrupts_ram_size __ram_vector_table_size__
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
#define m_data_size (0x00020000 - m_interrupts_ram_size)
#define m_data2_start 0x20200000
#define m_data2_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (.boot_hdr.conf, +FIRST)
}
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
}
#else
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
#endif
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
#if (defined(__ram_vector_table__))
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
}
#else
VECTOR_RAM m_interrupts_start EMPTY 0 {
}
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (RamFunction)
* (NonCacheable.init)
* (*NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

77
board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/MIMXRT1062xxxxx_ram.scf Normal file
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#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
VECTOR_RAM m_interrupts_start EMPTY 0 {
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (*NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

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board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvoptx Normal file
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2159
board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/TencentOS-Tiny.uvprojx Normal file
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File diff suppressed because it is too large Load Diff

89
board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_flexspi_nor.ini Normal file
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/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void restoreFlexRAM(void)
{
unsigned int value;
unsigned int base;
base = 0x400AC000;
value = _RDWORD(base + 0x44);
value &= ~(0xFFFFFFFF);
value |= 0x55AFFA55;
_WDWORD(base + 0x44, value);
value = _RDWORD(base + 0x40);
value |= (1 << 2);
_WDWORD(base + 0x40, value);
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
restoreFlexRAM();
Setup(); // Setup for Running
}
restoreFlexRAM();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

89
board/TencentOS_tiny_EVB_AIoT/tcp_through_module/KEIL/tosevbrt1062_ram.ini Normal file
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/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void restoreFlexRAM(void)
{
unsigned int value;
unsigned int base;
base = 0x400AC000;
value = _RDWORD(base + 0x44);
value &= ~(0xFFFFFFFF);
value |= 0x55AFFA55;
_WDWORD(base + 0x44, value);
value = _RDWORD(base + 0x40);
value |= (1 << 2);
_WDWORD(base + 0x40, value);
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
restoreFlexRAM();
Setup(); // Setup for Running
}
restoreFlexRAM();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main