add cortex-m33 support, TrustZone-m not supported now

add cortex-m33 support, TrustZone-m not supported now

arch/arm/arm-v8m/cortex-m33/armcc/port.h

@@ -0,0 +1,312 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v8m/cortex-m33/armcc/port_c.c

@@ -0,0 +1,281 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos_k.h"
+#include "core_cm33.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
+{
+    return SysTick_LOAD_RELOAD_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    port_systick_config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+/*------------------ RealView Compiler -----------------*/
+/* V5 */
+#if defined(__CC_ARM)
+
+__PORT__ __ASM__ void HardFault_Handler(void)
+{
+    IMPORT  fault_backtrace
+
+    MOV     r0, lr
+    TST     lr, #0x04
+    ITE     EQ
+    MRSEQ   r1, MSP
+    MRSNE   r1, PSP
+    BL      fault_backtrace
+}
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* ARMCC VERSION */
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v8m/cortex-m33/armcc/port_config.h

@@ -0,0 +1,37 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE                   CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE                   CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH                  CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN                  0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT      1u
+#define TOS_CFG_CPU_BYTE_ORDER                  CPU_BYTE_ORDER_LITTLE_ENDIAN
+
+#if (defined(ARMCC_V5) && !defined(__TARGET_FPU_SOFTVFP)) || \
+    (defined(ARMCC_V6) && defined(__ARM_PCS_VFP))
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v8m/cortex-m33/armcc/port_s.S

@@ -0,0 +1,188 @@
+    EXPORT  port_int_disable
+    EXPORT  port_int_enable
+
+    EXPORT  port_cpsr_save
+    EXPORT  port_cpsr_restore
+
+    EXPORT  port_sched_start
+    EXPORT  port_context_switch
+    EXPORT  port_irq_context_switch
+
+    EXPORT  port_clz
+
+    EXPORT  PendSV_Handler
+
+    IMPORT  k_curr_task
+    IMPORT  k_next_task
+
+SCB_VTOR        EQU     0xE000ED08
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU     0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+
+    GLOBAL port_int_disable
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_int_enable
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_save
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+    GLOBAL port_cpsr_restore
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+    GLOBAL port_clz
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+    GLOBAL port_sched_start
+port_sched_start
+    CPSID   I
+
+    ; set pendsv priority lowest
+    ; otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
+    ; that would be a disaster
+    MOV32   R0, NVIC_SYSPRI14
+    MOV32   R1, NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    ; k_curr_task = k_next_task
+    MOV32   R0, k_curr_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    ; sp = k_next_task->sp
+    LDR     R0, [R2]
+    ; PSP = sp
+    MSR     PSP, R0
+
+    ; using PSP
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    ; restore r4-11 from new process stack
+    LDMFD   SP!, {R4 - R11}
+
+    IF {FPU} != "SoftVFP"
+    ; ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    ENDIF
+
+    ; restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    ; load R12 and LR
+    LDMFD    SP!, {R12, LR}
+    ; load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+    GLOBAL port_context_switch
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL port_irq_context_switch
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+    GLOBAL PendSV_Handler
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save
+    ; R0-R3, R12, LR, PC, xPSR is saved automatically here
+    IF {FPU} != "SoftVFP"
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    ; S0 - S16, FPSCR saved automatically here
+
+    ; save EXC_RETURN
+    STMFD   R0!, {LR}
+    ENDIF
+
+    ; save remaining regs r4-11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    ; k_curr_task->sp = PSP
+    MOV32   R5, k_curr_task
+    LDR     R6, [R5]
+    ; R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore
+    ; k_curr_task = k_next_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ; R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    ; restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    IF {FPU} != "SoftVFP"
+    ; restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    ENDIF
+
+    ; Load PSP with new process SP
+    MSR     PSP, R0
+    CPSIE   I
+    ; R0-R3, R12, LR, PC, xPSR restored automatically here
+    ; S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+    ALIGN
+    END
+

arch/arm/arm-v8m/cortex-m33/gcc/port.h

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v8m/cortex-m33/gcc/port_c.c

@@ -0,0 +1,255 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos_k.h"
+#include "core_cm33.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    port_systick_config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "BL      fault_backtrace\n\t"
+    );
+}
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v8m/cortex-m33/gcc/port_config.h

@@ -0,0 +1,36 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE                   CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE                   CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH                  CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN                  0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT      1u
+#define TOS_CFG_CPU_BYTE_ORDER                  CPU_BYTE_ORDER_LITTLE_ENDIAN
+
+#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+#define TOS_CFG_CPU_ARM_FPU_EN      1u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN      0u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v8m/cortex-m33/gcc/port_s.S

@@ -0,0 +1,202 @@
+    .global port_int_disable
+    .global port_int_enable
+
+    .global port_cpsr_save
+    .global port_cpsr_restore
+
+    .global port_sched_start
+    .global port_context_switch
+    .global port_irq_context_switch
+
+    .global port_clz
+
+    .global PendSV_Handler
+
+    .extern k_curr_task
+    .extern k_next_task
+
+
+.equ SCB_VTOR,              0xE000ED08
+.equ NVIC_INT_CTRL,         0xE000ED04
+.equ NVIC_SYSPRI14,         0xE000ED22
+.equ NVIC_PENDSV_PRI,       0xFF
+.equ NVIC_PENDSVSET,        0x10000000
+
+
+   .text
+   .align 2
+   .thumb
+   .syntax unified
+
+
+.type port_int_disable, %function
+port_int_disable:
+    CPSID   I
+    BX      LR
+
+
+.type port_int_enable, %function
+port_int_enable:
+    CPSIE   I
+    BX      LR
+
+
+.type port_cpsr_save, %function
+port_cpsr_save:
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+.type port_cpsr_restore, %function
+port_cpsr_restore:
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+.type port_clz, %function
+port_clz:
+    CLZ     R0, R0
+    BX      LR
+
+
+.thumb_func
+.type port_sched_start, %function
+port_sched_start:
+    CPSID   I
+
+    @ set pendsv priority lowest
+    @ otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
+    @ that would be a disaster
+    MOVW    R0, #:lower16:NVIC_SYSPRI14
+    MOVT    R0, #:upper16:NVIC_SYSPRI14
+
+    MOVW    R1, #:lower16:NVIC_PENDSV_PRI
+    MOVT    R1, #:upper16:NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    MOVW    R0, #:lower16:SCB_VTOR
+    MOVT    R0, #:upper16:SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    MOVW    R0, #:lower16:k_curr_task
+    MOVT    R0, #:upper16:k_curr_task
+
+    @ k_curr_task = k_next_task;
+    MOVW    R1, #:lower16:k_next_task
+    MOVT    R1, #:upper16:k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    @ sp = k_next_task->sp
+    LDR     R0, [R2]
+    @ PSP = sp
+    MSR     PSP, R0
+
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    @ restore r4-11 from new process stack
+    LDMFD    SP!, {R4 - R11}
+
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    #endif
+
+    @ restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    @ load R12 and LR
+    LDMFD    SP!, {R12, LR}    
+    @ load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+.thumb_func
+.type port_context_switch, %function
+port_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type port_irq_context_switch, %function
+port_irq_context_switch:
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+.thumb_func
+.type PendSV_Handler, %function
+PendSV_Handler:
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save:
+    @ R0-R3, R12, LR, PC, xPSR is saved automatically here
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    @ S0 - S16, FPSCR saved automatically here
+
+    @ save EXC_RETURN
+    STMFD   R0!, {LR}
+    #endif
+
+    @ save remaining regs r4 - 11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    @ k_curr_task->sp = PSP;
+    MOVW    R5, #:lower16:k_curr_task
+    MOVT    R5, #:upper16:k_curr_task
+    LDR     R6, [R5]
+    @ R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore:
+    @ k_curr_task = k_next_task;
+    MOVW    R1, #:lower16:k_next_task
+    MOVT    R1, #:upper16:k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    @ R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    @ restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
+    @ restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    @ is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    #endif
+
+    @ Load PSP with new process SP
+    MSR     PSP, R0
+    
+    CPSIE   I
+
+    @ R0-R3, R12, LR, PC, xPSR restored automatically here
+    @ S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+.end
+

arch/arm/arm-v8m/cortex-m33/iccarm/port.h

@@ -0,0 +1,312 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ * 
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _PORT_H_
+#define  _PORT_H_
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+typedef struct port_fault_regs {
+    union {
+        /* System Handler Control and State Register (0xE000ED24) */
+        uint32_t value;
+        struct {
+            /* Read as 1 if memory management fault is active */
+            uint32_t MEMFAULTACT    : 1;
+            /* Read as 1 if bus fault exception is active */
+            uint32_t BUSFAULTACT    : 1;
+            uint32_t UnusedBits1    : 1;
+            /* Read as 1 if usage fault exception is active */
+            uint32_t USGFAULTACT    : 1;
+            uint32_t UnusedBits2    : 3;
+            /* Read as 1 if SVC exception is active */
+            uint32_t SVCALLACT      : 1;
+            /* Read as 1 if debug monitor exception is active */
+            uint32_t MONITORACT     : 1;
+            uint32_t UnusedBits3    : 1;
+            /* Read as 1 if PendSV exception is active */
+            uint32_t PENDSVACT      : 1;
+            /* Read as 1 if SYSTICK exception is active */
+            uint32_t SYSTICKACT     : 1;
+            /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */
+            uint32_t USGFAULTPENDED : 1;
+            /* Memory management fault pended; memory management fault started but was replaced by a
+               higher-priority exception */
+            uint32_t MEMFAULTPENDED : 1;
+            /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority
+               exception */
+            uint32_t BUSFAULTPENDED : 1;
+            /* SVC pended; SVC was started but was replaced by a higher-priority exception */
+            uint32_t SVCALLPENDED   : 1;
+            /* Memory management fault handler enable */
+            uint32_t MEMFAULTENA    : 1;
+            /* Bus fault handler enable */
+            uint32_t BUSFAULTENA    : 1;
+            /* Usage fault handler enable */
+            uint32_t USGFAULTENA    : 1;
+        } bits;
+    } syshndctrl;                          
+
+    union {
+        uint32_t value;
+
+        struct {
+            union {
+                /* Memory Management Fault Status Register (0xE000ED28) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IACCVIOL    : 1;
+                    /* Data access violation */
+                    uint8_t DACCVIOL    : 1;
+                    uint8_t UnusedBits  : 1;
+                    /* Unstacking error */
+                    uint8_t MUNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t MSTKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t MLSPERR     : 1;
+                    uint8_t UnusedBits2 : 1;
+                    /* Indicates the MMAR is valid */
+                    uint8_t MMARVALID   : 1;
+                } bits;
+            } mfsr;
+
+            union {
+                /* Bus Fault Status Register (0xE000ED29) */
+                uint8_t value;
+                struct {
+                    /* Instruction access violation */
+                    uint8_t IBUSERR    : 1;
+                    /* Precise data access violation */
+                    uint8_t PRECISERR  : 1;
+                    /* Imprecise data access violation */
+                    uint8_t IMPREISERR : 1;
+                    /* Unstacking error */
+                    uint8_t UNSTKERR   : 1;
+                    /* Stacking error */
+                    uint8_t STKERR     : 1;
+                    /* Floating-point lazy state preservation (M4/M7) */
+                    uint8_t LSPERR     : 1;
+                    uint8_t UnusedBits : 1;
+                    /* Indicates BFAR is valid */
+                    uint8_t BFARVALID  : 1;
+                } bits;
+            } bfsr;
+
+            union {
+                /* Usage Fault Status Register (0xE000ED2A) */
+                uint16_t value;
+                struct {
+                    /* Attempts to execute an undefined instruction */
+                    uint16_t UNDEFINSTR : 1;
+                    /* Attempts to switch to an invalid state (e.g., ARM) */
+                    uint16_t INVSTATE   : 1;
+                    /* Attempts to do an exception with a bad value in the EXC_RETURN number */
+                    uint16_t INVPC      : 1;
+                    /* Attempts to execute a coprocessor instruction */
+                    uint16_t NOCP       : 1;
+                    uint16_t UnusedBits : 4;
+                    /* Indicates that an unaligned access fault has taken place */
+                    uint16_t UNALIGNED  : 1;
+                    /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */
+                    uint16_t DIVBYZERO0 : 1;
+                } bits;
+            } ufsr;
+        } part;
+    } cfsr;
+
+    /* Memory Management Fault Address Register (0xE000ED34) */
+    uint32_t mmar;
+
+    /* Bus Fault Manage Address Register (0xE000ED38) */
+    uint32_t bfar;
+
+    union {
+        /* Hard Fault Status Register (0xE000ED2C) */
+        uint32_t value;
+        struct {
+            uint32_t UnusedBits  : 1;
+            /* Indicates hard fault is caused by failed vector fetch */
+            uint32_t VECTBL      : 1;
+            uint32_t UnusedBits2 : 28;
+            /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */
+            uint32_t FORCED      : 1;
+            /* Indicates hard fault is triggered by debug event */
+            uint32_t DEBUGEVT    : 1;
+        } bits;
+    } hfsr;
+
+    union {
+        /* Debug Fault Status Register (0xE000ED30) */
+        uint32_t value;
+        struct {
+            /* Halt requested in NVIC */
+            uint32_t HALTED   : 1;
+            /* BKPT instruction executed */
+            uint32_t BKPT     : 1;
+            /* DWT match occurred */
+            uint32_t DWTTRAP  : 1;
+            /* Vector fetch occurred */
+            uint32_t VCATCH   : 1;
+            /* EDBGRQ signal asserted */
+            uint32_t EXTERNAL : 1;
+        } bits;
+    } dfsr;
+
+    /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */
+    uint32_t afsr;
+} port_fault_regs_t;
+
+enum fault_info {
+    FAULT_INFO_ASSERT_ON_THREAD,
+    FAULT_INFO_HFSR_VECTBL,
+    FAULT_INFO_MFSR_IACCVIOL,
+    FAULT_INFO_MFSR_DACCVIOL,
+    FAULT_INFO_MFSR_MUNSTKERR,
+    FAULT_INFO_MFSR_MSTKERR,
+    FAULT_INFO_MFSR_MLSPERR,
+    FAULT_INFO_BFSR_IBUSERR,
+    FAULT_INFO_BFSR_PRECISERR,
+    FAULT_INFO_BFSR_IMPREISERR,
+    FAULT_INFO_BFSR_UNSTKERR,
+    FAULT_INFO_BFSR_STKERR,
+    FAULT_INFO_BFSR_LSPERR,
+    FAULT_INFO_UFSR_UNDEFINSTR,
+    FAULT_INFO_UFSR_INVSTATE,
+    FAULT_INFO_UFSR_INVPC,
+    FAULT_INFO_UFSR_NOCP,
+    FAULT_INFO_UFSR_UNALIGNED,
+    FAULT_INFO_UFSR_DIVBYZERO0,
+    FAULT_INFO_DFSR_HALTED,
+    FAULT_INFO_DFSR_BKPT,
+    FAULT_INFO_DFSR_DWTTRAP,
+    FAULT_INFO_DFSR_VCATCH,
+    FAULT_INFO_DFSR_EXTERNAL,
+    FAULT_INFO_MMAR,
+    FAULT_INFO_BFAR,
+};
+
+static const char *const fault_msg[] = {
+        [FAULT_INFO_ASSERT_ON_THREAD]      = "Assert on thread %s\n",
+        [FAULT_INFO_HFSR_VECTBL]           = "Hard fault is caused by failed vector fetch\n",
+        [FAULT_INFO_MFSR_IACCVIOL]         = "Memory management fault: instruction access violation\n",
+        [FAULT_INFO_MFSR_DACCVIOL]         = "Memory management fault: data access violation\n",
+        [FAULT_INFO_MFSR_MUNSTKERR]        = "Memory management fault: unstacking error\n",
+        [FAULT_INFO_MFSR_MSTKERR]          = "Memory management fault: stacking error\n",
+        [FAULT_INFO_MFSR_MLSPERR]          = "Memory management fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_BFSR_IBUSERR]          = "Bus fault: instruction access violation\n",
+        [FAULT_INFO_BFSR_PRECISERR]        = "Bus fault: precise data access violation\n",
+        [FAULT_INFO_BFSR_IMPREISERR]       = "Bus fault: imprecise data access violation\n",
+        [FAULT_INFO_BFSR_UNSTKERR]         = "Bus fault: unstacking error\n",
+        [FAULT_INFO_BFSR_STKERR]           = "Bus fault: stacking error\n",
+        [FAULT_INFO_BFSR_LSPERR]           = "Bus fault: floating-point lazy state preservation\n",
+        [FAULT_INFO_UFSR_UNDEFINSTR]       = "Usage fault: undefined instruction\n",
+        [FAULT_INFO_UFSR_INVSTATE]         = "Usage fault: invalid state (e.g., ARM)\n",
+        [FAULT_INFO_UFSR_INVPC]            = "Usage fault: invalid EXC_RETURN\n",
+        [FAULT_INFO_UFSR_NOCP]             = "Usage fault: coprocessor instruction\n",
+        [FAULT_INFO_UFSR_UNALIGNED]        = "Usage fault: unaligned access\n",
+        [FAULT_INFO_UFSR_DIVBYZERO0]       = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n",
+        [FAULT_INFO_DFSR_HALTED]           = "Debug fault: halt requested in NVIC\n",
+        [FAULT_INFO_DFSR_BKPT]             = "Debug fault: BKPT instruction executed\n",
+        [FAULT_INFO_DFSR_DWTTRAP]          = "Debug fault: DWT match occurred\n",
+        [FAULT_INFO_DFSR_VCATCH]           = "Debug fault: Vector fetch occurred\n",
+        [FAULT_INFO_DFSR_EXTERNAL]         = "Debug fault: EDBGRQ signal asserted\n",
+        [FAULT_INFO_MMAR]                  = "The memory management fault occurred address is %08x\n",
+        [FAULT_INFO_BFAR]                  = "The bus fault occurred address is %08x\n",
+};
+
+__PORT__ void       HardFault_Handler(void);
+
+__PORT__ void       port_fault_diagnosis(void);
+#endif
+
+
+#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u)
+__PORT__ uint32_t   port_clz(uint32_t val);
+#endif
+
+__PORT__ void       port_int_disable(void);
+
+__PORT__ void       port_int_enable(void);
+
+__PORT__ cpu_cpsr_t port_cpsr_save(void);
+
+__PORT__ void       port_cpsr_restore(cpu_cpsr_t cpsr);
+
+__PORT__ void       port_cpu_reset(void);
+
+__PORT__ void       port_sched_start(void) __NO_RETURN__;
+
+__PORT__ void       port_context_switch(void);
+
+__PORT__ void       port_irq_context_switch(void);
+
+__PORT__ void       port_systick_config(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_priority_set(uint32_t prio);
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ void       port_systick_resume(void);
+
+__PORT__ void       port_systick_suspend(void);
+
+__PORT__ void       port_systick_reload(uint32_t cycle_per_tick);
+
+__PORT__ void       port_systick_pending_reset(void);
+
+__PORT__ k_time_t   port_systick_max_delay_millisecond(void);
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void       port_sleep_mode_enter(void);
+
+__PORT__ void       port_stop_mode_enter(void);
+
+__PORT__ void       port_standby_mode_enter(void);
+
+#endif
+
+#endif /* _PORT_H_ */
+

arch/arm/arm-v8m/cortex-m33/iccarm/port_c.c

@@ -0,0 +1,261 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tos_k.h"
+#include "core_cm33.h"
+
+__PORT__ void port_cpu_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+__PORT__ void port_systick_config(uint32_t cycle_per_tick)
+{
+    (void)SysTick_Config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_priority_set(uint32_t prio)
+{
+    NVIC_SetPriority(SysTick_IRQn, prio);
+}
+
+#if TOS_CFG_TICKLESS_EN > 0u
+
+__PORT__ k_time_t port_systick_max_delay_millisecond(void)
+{
+    k_time_t max_millisecond;
+    uint32_t max_cycle;
+
+    max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit
+    max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second
+    return max_millisecond;
+}
+
+__PORT__ void port_systick_resume(void)
+{
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+}
+
+__PORT__ void port_systick_suspend(void)
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+__PORT__ k_cycle_t port_systick_max_reload_cycle(void)
+{
+    return SysTick_LOAD_RELOAD_Msk;
+}
+
+__PORT__ void port_systick_reload(uint32_t cycle_per_tick)
+{
+    port_systick_config(cycle_per_tick);
+}
+
+__PORT__ void port_systick_pending_reset(void)
+{
+    SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+}
+
+#endif
+
+#if TOS_CFG_PWR_MGR_EN > 0u
+
+__PORT__ void port_sleep_mode_enter(void)
+{
+#if 1
+    HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#else
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+#endif
+}
+
+__PORT__ void port_stop_mode_enter(void)
+{
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+}
+
+__PORT__ void port_standby_mode_enter(void)
+{
+    HAL_PWR_EnterSTANDBYMode();
+}
+
+#endif
+
+#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
+__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs)
+{
+    k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n");
+
+    if (regs->hfsr.bits.VECTBL) {
+        k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]);
+    }
+    if (regs->hfsr.bits.FORCED) {
+        /* Memory Management Fault */
+        if (regs->cfsr.part.mfsr.value) {
+            if (regs->cfsr.part.mfsr.bits.IACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MUNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]);
+            }
+            if (regs->cfsr.part.mfsr.bits.MSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MLSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]);
+            }
+
+            if (regs->cfsr.part.mfsr.bits.MMARVALID) {
+                if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar);
+                }
+            }
+        }
+        /* Bus Fault */
+        if (regs->cfsr.part.bfsr.value) {
+            if (regs->cfsr.part.bfsr.bits.IBUSERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.IMPREISERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.UNSTKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]);
+            }
+            if (regs->cfsr.part.bfsr.bits.STKERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.LSPERR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]);
+            }
+
+            if (regs->cfsr.part.bfsr.bits.BFARVALID) {
+                if (regs->cfsr.part.bfsr.bits.PRECISERR) {
+                    k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar);
+                }
+            }
+
+        }
+        /* Usage Fault */
+        if (regs->cfsr.part.ufsr.value) {
+            if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVSTATE) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]);
+            }
+            if (regs->cfsr.part.ufsr.bits.INVPC) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]);
+            }
+            if (regs->cfsr.part.ufsr.bits.NOCP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]);
+            }
+            if (regs->cfsr.part.ufsr.bits.UNALIGNED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]);
+            }
+            if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]);
+            }
+        }
+    }
+    /* Debug Fault */
+    if (regs->hfsr.bits.DEBUGEVT) {
+        if (regs->dfsr.value) {
+            if (regs->dfsr.bits.HALTED) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]);
+            }
+            if (regs->dfsr.bits.BKPT) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]);
+            }
+            if (regs->dfsr.bits.DWTTRAP) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]);
+            }
+            if (regs->dfsr.bits.VCATCH) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]);
+            }
+            if (regs->dfsr.bits.EXTERNAL) {
+                k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]);
+            }
+        }
+    }
+}
+
+__PORT__ void port_fault_diagnosis(void)
+{
+    port_fault_regs_t regs;
+
+    regs.syshndctrl.value   = SCB->SHCSR;
+    regs.cfsr.value         = SCB->CFSR;
+    regs.mmar               = SCB->MMFAR;
+    regs.bfar               = SCB->BFAR;
+    regs.hfsr.value         = SCB->HFSR;
+    regs.dfsr.value         = SCB->DFSR;
+    regs.afsr               = SCB->AFSR;
+
+    port_fault_do_diagnosis(&regs);
+}
+
+__PORT__ void __NAKED__ HardFault_Handler(void)
+{
+    __ASM__ __VOLATILE__ (
+        "MOV     r0, lr\n\t"
+        "TST     lr, #0x04\n\t"
+        "ITE     EQ\n\t"
+        "MRSEQ   r1, MSP\n\t"
+        "MRSNE   r1, PSP\n\t"
+        "LDR     r2, =fault_backtrace\n\t"
+        "BX      r2\n\t"
+    );
+}
+
+#endif /* TOS_CFG_FAULT_BACKTRACE_EN */
+

arch/arm/arm-v8m/cortex-m33/iccarm/port_config.h

@@ -0,0 +1,36 @@
+/*----------------------------------------------------------------------------
+ * Tencent is pleased to support the open source community by making TencentOS
+ * available.
+ *
+ * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
+ * If you have downloaded a copy of the TencentOS binary from Tencent, please
+ * note that the TencentOS binary is licensed under the BSD 3-Clause License.
+ *
+ * If you have downloaded a copy of the TencentOS source code from Tencent,
+ * please note that TencentOS source code is licensed under the BSD 3-Clause
+ * License, except for the third-party components listed below which are
+ * subject to different license terms. Your integration of TencentOS into your
+ * own projects may require compliance with the BSD 3-Clause License, as well
+ * as the other licenses applicable to the third-party components included
+ * within TencentOS.
+ *---------------------------------------------------------------------------*/
+
+#ifndef _PORT_CONFIG_H_
+#define  _PORT_CONFIG_H_
+
+#define TOS_CFG_CPU_ADDR_SIZE                   CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_DATA_SIZE                   CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_STK_GROWTH                  CPU_STK_GROWTH_DESCENDING
+// #define TOS_CFG_CPU_HRTIMER_SIZE             CPU_WORD_SIZE_32
+#define TOS_CFG_CPU_HRTIMER_EN                  0u
+#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT      1u
+#define TOS_CFG_CPU_BYTE_ORDER                  CPU_BYTE_ORDER_LITTLE_ENDIAN
+
+#ifndef __ARMVFP__
+#define TOS_CFG_CPU_ARM_FPU_EN 0u
+#else
+#define TOS_CFG_CPU_ARM_FPU_EN 1u
+#endif
+
+#endif /* _PORT_CONFIG_H_ */
+

arch/arm/arm-v8m/cortex-m33/iccarm/port_s.S

@@ -0,0 +1,176 @@
+    PUBLIC  port_int_disable
+    PUBLIC  port_int_enable
+
+    PUBLIC  port_cpsr_save
+    PUBLIC  port_cpsr_restore
+
+    PUBLIC  port_sched_start
+    PUBLIC  port_context_switch
+    PUBLIC  port_irq_context_switch
+
+    PUBLIC  port_clz
+
+    PUBLIC  PendSV_Handler
+
+    EXTERN  k_curr_task
+    EXTERN  k_next_task
+
+SCB_VTOR        EQU     0xE000ED08
+NVIC_INT_CTRL   EQU     0xE000ED04
+NVIC_SYSPRI14   EQU     0xE000ED22
+NVIC_PENDSV_PRI EQU     0xFF
+NVIC_PENDSVSET  EQU     0x10000000
+
+
+    RSEG CODE:CODE:NOROOT(2)
+    THUMB
+
+
+port_int_disable
+    CPSID   I
+    BX      LR
+
+
+port_int_enable
+    CPSIE   I
+    BX      LR
+
+
+port_cpsr_save
+    MRS     R0, PRIMASK
+    CPSID   I
+    BX      LR
+
+
+port_cpsr_restore
+    MSR     PRIMASK, R0
+    BX      LR
+
+
+port_clz
+    CLZ     R0, R0
+    BX      LR
+
+
+port_sched_start
+    CPSID   I
+
+    ; set pendsv priority lowest
+    ; otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq
+    ; that would be a disaster
+    MOV32   R0, NVIC_SYSPRI14
+    MOV32   R1, NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    LDR     R0, =SCB_VTOR
+    LDR     R0, [R0]
+    LDR     R0, [R0]
+    MSR     MSP, R0
+
+    ; k_curr_task = k_next_task
+    MOV32   R0, k_curr_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    ; sp = k_next_task->sp
+    LDR     R0, [R2]
+    ; PSP = sp
+    MSR     PSP, R0
+
+    ; using PSP
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+
+    ISB
+
+    ; restore r4-11 from new process stack
+    LDMFD   SP!, {R4 - R11}
+
+    #if defined(__ARMVFP__)
+    ; ignore EXC_RETURN the first switch
+    LDMFD   SP!, {R0}
+    #endif
+
+    ; restore r0, r3
+    LDMFD    SP!, {R0 - R3}
+    ; load R12 and LR
+    LDMFD    SP!, {R12, LR}
+    ; load PC and discard xPSR
+    LDMFD    SP!, {R1, R2}
+
+    CPSIE    I
+    BX       R1
+
+
+port_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+port_irq_context_switch
+    LDR     R0, =NVIC_INT_CTRL
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+PendSV_Handler
+    CPSID   I
+    MRS     R0, PSP
+
+_context_save
+    ; R0-R3, R12, LR, PC, xPSR is saved automatically here
+    #if defined(__ARMVFP__)
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VSTMDBEQ  R0!, {S16 - S31}
+    ; S0 - S16, FPSCR saved automatically here
+
+    ; save EXC_RETURN
+    STMFD   R0!, {LR}
+    #endif
+
+    ; save remaining regs r4-11 on process stack
+    STMFD   R0!, {R4 - R11}
+
+    ; k_curr_task->sp = PSP
+    MOV32   R5, k_curr_task
+    LDR     R6, [R5]
+    ; R0 is SP of process being switched out
+    STR     R0, [R6]
+
+_context_restore
+    ; k_curr_task = k_next_task
+    MOV32   R1, k_next_task
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ; R0 = k_next_task->sp
+    LDR     R0, [R2]
+
+    ; restore R4 - R11
+    LDMFD   R0!, {R4 - R11}
+
+    #if defined(__ARMVFP__)
+    ; restore EXC_RETURN
+    LDMFD   R0!, {LR}
+    ; is it extended frame?
+    TST     LR, #0x10
+    IT      EQ
+    VLDMIAEQ    R0!, {S16 - S31}
+    #endif
+
+    ; Load PSP with new process SP
+    MSR     PSP, R0
+    CPSIE   I
+    ; R0-R3, R12, LR, PC, xPSR restored automatically here
+    ; S0 - S16, FPSCR restored automatically here if FPCA = 1
+    BX      LR
+
+    END
+

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Hardware/OLED/bmp.h

@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+//
+//存储图片数据，图片大小为64*32像素
+//
+/////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __BMP_H
+#define __BMP_H
+unsigned char BMP1[] =
+{0x00,0x06,0x0A,0xFE,0x0A,0xC6,0x00,0xE0,0x00,0xF0,0x00,0xF8,0x00,0x00,0x00,0x00,
+0x00,0x00,0xFE,0x7D,0xBB,0xC7,0xEF,0xEF,0xEF,0xEF,0xEF,0xEF,0xEF,0xC7,0xBB,0x7D,
+0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,
+0x0C,0xFE,0xFE,0x0C,0x08,0x20,0x60,0xFE,0xFE,0x60,0x20,0x00,0x00,0x00,0x78,0x48,
+0xFE,0x82,0xBA,0xBA,0x82,0xBA,0xBA,0x82,0xBA,0xBA,0x82,0xBA,0xBA,0x82,0xFE,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0xFF,
+0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0xFF,0xFF,0x00,0x00,0xFE,0xFF,0x03,
+0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0xFF,0xFE,0x00,0x00,0x00,0x00,0xC0,0xC0,
+0xC0,0x00,0x00,0x00,0x00,0xFE,0xFF,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,
+0xFF,0xFE,0x00,0x00,0xFE,0xFF,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0xFF,
+0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x0C,
+0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0xFF,0xFF,0x00,0x00,0x00,0x00,0xE1,0xE1,
+0xE1,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0xFF,
+0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x1F,
+0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,0x0F,0x00,0x00,0x0F,0x1F,0x18,
+0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x0F,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,
+0x1F,0x0F,0x00,0x00,0x0F,0x1F,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x1F,
+0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x8C,0x42,0x22,0x12,0x0C,0x00,0xFC,0x02,0x02,0x02,0xFC,0x00,0x00,0x04,
+0xFE,0x00,0x00,0x00,0x20,0x58,0x44,0xFE,0x40,0x00,0x10,0x10,0x10,0x10,0x10,0x00,
+0x00,0x04,0xFE,0x00,0x00,0x00,0xFC,0x02,0x02,0x02,0xFC,0x00,0x10,0x10,0x10,0x10,
+0x10,0x00,0xFC,0x02,0x02,0x02,0xFC,0x00,0x00,0x04,0xFE,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x24,0xA4,0x2E,0x24,0xE4,0x24,0x2E,0xA4,0x24,0x00,0x00,0x00,0xF8,0x4A,0x4C,
+0x48,0xF8,0x48,0x4C,0x4A,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x01,
+0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x01,0x01,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x20,0x10,0x10,
+0x10,0x10,0x20,0xC0,0x00,0x00,0xC0,0x20,0x10,0x10,0x10,0x10,0x20,0xC0,0x00,0x00,
+0x00,0x12,0x0A,0x07,0x02,0x7F,0x02,0x07,0x0A,0x12,0x00,0x00,0x00,0x0B,0x0A,0x0A,
+0x0A,0x7F,0x0A,0x0A,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x40,0x40,
+0x40,0x50,0x20,0x5F,0x80,0x00,0x1F,0x20,0x40,0x40,0x40,0x50,0x20,0x5F,0x80,0x00,
+
+};
+
+#endif
+
+

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Hardware/OLED/oled.c

@@ -0,0 +1,320 @@
+#include "oled.h"
+#include "stdlib.h"
+#include "oledfont.h"
+//OLED的显存
+//存放格式如下.
+//-----------------------------------
+//|x→[0,127]						|
+//|			OLED显示坐标				|
+//|y			范围					|
+//|↓								|
+//|[0,31]							|
+//-----------------------------------
+/**********************************************
+//IIC Start
+**********************************************/
+void IIC_Start(void)
+{
+	OLED_SCLK_Set();
+	OLED_SDIN_Set();
+	OLED_SDIN_Clr();
+	OLED_SCLK_Clr();
+}
+
+/**********************************************
+//IIC Stop
+**********************************************/
+void IIC_Stop(void)
+{
+	OLED_SCLK_Set();
+	OLED_SDIN_Clr();
+	OLED_SDIN_Set();
+}
+
+void IIC_Wait_Ack(void)
+{
+	OLED_SCLK_Set();
+	OLED_SCLK_Clr();
+}
+/**********************************************
+// IIC Write byte
+**********************************************/
+
+void Write_IIC_Byte(unsigned char IIC_Byte)
+{
+	unsigned char i;
+	unsigned char m,da;
+	da=IIC_Byte;
+	OLED_SCLK_Clr();
+	for(i=0;i<8;i++)
+	{
+		m=da;
+		m=m&0x80;
+		if(m==0x80)
+		{
+			OLED_SDIN_Set();
+		}
+		else
+			OLED_SDIN_Clr();
+		da=da<<1;
+		OLED_SCLK_Set();
+		OLED_SCLK_Clr();
+	}
+}
+/**********************************************
+// IIC Write Command
+**********************************************/
+void Write_IIC_Command(unsigned char IIC_Command)
+{
+	IIC_Start();
+	Write_IIC_Byte(0x78);            //Slave address,SA0=0
+	IIC_Wait_Ack();
+	Write_IIC_Byte(0x00);			//write command
+	IIC_Wait_Ack();
+	Write_IIC_Byte(IIC_Command);
+	IIC_Wait_Ack();
+	IIC_Stop();
+}
+/**********************************************
+// IIC Write Data
+**********************************************/
+void Write_IIC_Data(unsigned char IIC_Data)
+{
+	IIC_Start();
+	Write_IIC_Byte(0x78);			//D/C#=0; R/W#=0
+	IIC_Wait_Ack();
+	Write_IIC_Byte(0x40);			//write data
+	IIC_Wait_Ack();
+	Write_IIC_Byte(IIC_Data);
+	IIC_Wait_Ack();
+	IIC_Stop();
+}
+void OLED_WR_Byte(unsigned dat,unsigned cmd)
+{
+	if(cmd)
+	{
+		Write_IIC_Data(dat);
+	}
+	else
+	{
+		Write_IIC_Command(dat);
+	}
+}
+
+
+/********************************************
+// fill_Picture
+********************************************/
+void fill_picture(unsigned char fill_Data)
+{
+	unsigned char m,n;
+	for(m=0;m<8;m++)
+	{
+		OLED_WR_Byte(0xb0+m,0);		//page0-page1
+		OLED_WR_Byte(0x00,0);		//low column start address
+		OLED_WR_Byte(0x10,0);		//high column start address
+		for(n=0;n<128;n++)
+		{
+			OLED_WR_Byte(fill_Data,1);
+		}
+	}
+}
+
+//坐标设置
+void OLED_Set_Pos(unsigned char x, unsigned char y)
+{
+	OLED_WR_Byte(0xb0+y,OLED_CMD);
+	OLED_WR_Byte(((x&0xf0)>>4)|0x10,OLED_CMD);
+	OLED_WR_Byte((x&0x0f),OLED_CMD);
+}
+//开启OLED显示
+void OLED_Display_On(void)
+{
+	OLED_WR_Byte(0X8D,OLED_CMD);  //SET DCDC命令
+	OLED_WR_Byte(0X14,OLED_CMD);  //DCDC ON
+	OLED_WR_Byte(0XAF,OLED_CMD);  //DISPLAY ON
+}
+//关闭OLED显示
+void OLED_Display_Off(void)
+{
+	OLED_WR_Byte(0X8D,OLED_CMD);  //SET DCDC命令
+	OLED_WR_Byte(0X10,OLED_CMD);  //DCDC OFF
+	OLED_WR_Byte(0XAE,OLED_CMD);  //DISPLAY OFF
+}
+//注意：清屏函数,清完屏,整个屏幕是黑色的!和没点亮一样!!!
+void OLED_Clear(void)
+{
+	uint8_t i,n;
+	for(i=0;i<8;i++)
+	{
+		OLED_WR_Byte (0xb0+i,OLED_CMD);    //设置页地址（0~7）
+		OLED_WR_Byte (0x00,OLED_CMD);      //设置显示位置—列低地址
+		OLED_WR_Byte (0x10,OLED_CMD);      //设置显示位置—列高地址
+		for(n=0;n<128;n++)
+			OLED_WR_Byte(0,OLED_DATA);
+	} //更新显示
+}
+void OLED_On(void)
+{
+	uint8_t i,n;
+	for(i=0;i<8;i++)
+	{
+		OLED_WR_Byte (0xb0+i,OLED_CMD);    //设置页地址（0~7）
+		OLED_WR_Byte (0x00,OLED_CMD);      //设置显示位置—列低地址
+		OLED_WR_Byte (0x10,OLED_CMD);      //设置显示位置—列高地址
+		for(n=0;n<128;n++)OLED_WR_Byte(1,OLED_DATA);
+	} //更新显示
+}
+//在指定位置显示一个字符,包括部分字符
+//x:0~127
+//y:0~63
+//
+//size:选择字体 16/12
+void OLED_ShowChar(uint8_t x,uint8_t y,uint8_t chr,uint8_t Char_Size)
+{
+	unsigned char c=0,i=0;
+	c=chr-' ';//得到偏移后的值
+	if(x>Max_Column-1){x=0;y=y+2;}
+	if(Char_Size ==16)
+	{
+		OLED_Set_Pos(x,y);
+		for(i=0;i<8;i++)
+		{
+			OLED_WR_Byte(F8X16[c*16+i],OLED_DATA);
+		}
+		OLED_Set_Pos(x,y+1);
+		for(i=0;i<8;i++){
+			OLED_WR_Byte(F8X16[c*16+i+8],OLED_DATA);
+		}
+	}
+	else
+	{
+		OLED_Set_Pos(x,y);
+		for(i=0;i<6;i++)
+			OLED_WR_Byte(F6x8[c][i],OLED_DATA);
+	}
+}
+//m^n函数
+uint32_t oled_pow(uint8_t m,uint8_t n)
+{
+	uint32_t result=1;
+	while(n--)result*=m;
+	return result;
+}
+//显示2个数字
+//x,y :起点坐标
+//len :数字的位数
+//size:字体大小
+//
+//num:数值(0~4294967295);
+void OLED_ShowNum(uint8_t x,uint8_t y,uint32_t num,uint8_t len,uint8_t size2)
+{
+	uint8_t t,temp;
+	uint8_t enshow=0;
+	for(t=0;t<len;t++)
+	{
+		temp=(num/oled_pow(10,len-t-1))%10;
+		if(enshow==0&&t<(len-1))
+		{
+			if(temp==0)
+			{
+				OLED_ShowChar(x+(size2/2)*t,y,' ',size2);
+				continue;
+			}else
+				enshow=1;
+		}
+		OLED_ShowChar(x+(size2/2)*t,y,temp+'0',size2);
+	}
+}
+//显示一个字符号串
+void OLED_ShowString(uint8_t x,uint8_t y,uint8_t *chr,uint8_t Char_Size)
+{
+	unsigned char j=0;
+	while (chr[j]!='\0')
+	{
+		OLED_ShowChar(x,y,chr[j],Char_Size);
+		x+=8;
+		if(x>120)
+		{
+			x=0;y+=2;
+		}
+		j++;
+	}
+}
+//显示汉字
+void OLED_ShowChinese(uint8_t x,uint8_t y,uint8_t no)
+{      			    
+	uint8_t t,adder=0;
+	OLED_Set_Pos(x,y);
+	for(t=0;t<16;t++)
+	{
+		OLED_WR_Byte(Hzk[2*no][t],OLED_DATA);
+		adder+=1;
+	}
+	OLED_Set_Pos(x,y+1);
+	for(t=0;t<16;t++)
+	{
+		OLED_WR_Byte(Hzk[2*no+1][t],OLED_DATA);
+		adder+=1;
+	}
+}
+/***********功能描述：显示显示BMP图片128×64起始点坐标(x,y),x的范围0〜127，y为页的范围0〜7*****************/
+void OLED_DrawBMP(unsigned char x0, unsigned char y0,unsigned char x1, unsigned char y1,unsigned char BMP[])
+{
+	unsigned int j=0;
+	unsigned char x,y;
+
+	if(y1%8==0) y=y1/8;
+	else y=y1/8+1;
+	for(y=y0;y<y1;y++)
+	{
+		OLED_Set_Pos(x0,y);
+		for(x=x0;x<x1;x++)
+		{
+			OLED_WR_Byte(BMP[j++],OLED_DATA);
+		}
+	}
+}
+
+//初始化OLED
+void OLED_Init(void)
+{
+	HAL_Delay(200);
+	OLED_WR_Byte(0xAE,OLED_CMD);//关闭显示
+
+	OLED_WR_Byte(0x40,OLED_CMD);//---set low column address
+	OLED_WR_Byte(0xB0,OLED_CMD);//---set high column address
+
+	OLED_WR_Byte(0xC8,OLED_CMD);//-not offset
+
+	OLED_WR_Byte(0x81,OLED_CMD);//设置对比度
+	OLED_WR_Byte(0xff,OLED_CMD);
+
+	OLED_WR_Byte(0xa1,OLED_CMD);//段重定向设置
+
+	OLED_WR_Byte(0xa6,OLED_CMD);//
+
+	OLED_WR_Byte(0xa8,OLED_CMD);//设置驱动路数
+	OLED_WR_Byte(0x1f,OLED_CMD);
+
+	OLED_WR_Byte(0xd3,OLED_CMD);
+	OLED_WR_Byte(0x00,OLED_CMD);
+
+	OLED_WR_Byte(0xd5,OLED_CMD);
+	OLED_WR_Byte(0xf0,OLED_CMD);
+
+	OLED_WR_Byte(0xd9,OLED_CMD);
+	OLED_WR_Byte(0x22,OLED_CMD);
+
+	OLED_WR_Byte(0xda,OLED_CMD);
+	OLED_WR_Byte(0x02,OLED_CMD);
+
+	OLED_WR_Byte(0xdb,OLED_CMD);
+	OLED_WR_Byte(0x49,OLED_CMD);
+
+	OLED_WR_Byte(0x8d,OLED_CMD);
+	OLED_WR_Byte(0x14,OLED_CMD);
+
+	OLED_WR_Byte(0xaf,OLED_CMD);
+	OLED_Clear();
+}

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Hardware/OLED/oled.h

@@ -0,0 +1,41 @@
+#ifndef __OLED_H
+#define __OLED_H
+#include "stm32l5xx_hal.h"
+#include "stdlib.h"
+#define OLED_MODE 0
+#define OLED_SIZE 8
+#define XLevelL		0x00
+#define XLevelH		0x10
+#define Max_Column	128
+#define Max_Row		64
+#define	Brightness	0xFF
+#define X_WIDTH 	128
+#define Y_WIDTH 	64
+//-----------------OLED IIC端口定义----------------
+//HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+#define OLED_SCLK_Clr() HAL_GPIO_WritePin(GPIOA,GPIO_PIN_7, GPIO_PIN_RESET);//SDA IIC接口的时钟信号
+#define OLED_SCLK_Set() HAL_GPIO_WritePin(GPIOA,GPIO_PIN_7, GPIO_PIN_SET);
+
+#define OLED_SDIN_Clr() HAL_GPIO_WritePin(GPIOB,GPIO_PIN_4, GPIO_PIN_RESET);//SCL IIC接口的数据信号
+#define OLED_SDIN_Set() HAL_GPIO_WritePin(GPIOB,GPIO_PIN_4, GPIO_PIN_SET);
+
+
+#define OLED_CMD  0	//写命令
+#define OLED_DATA 1	//写数据
+
+
+//OLED接口控制用函数
+void OLED_ShowNum(uint8_t x,uint8_t y,uint32_t num,uint8_t len,uint8_t size);
+void OLED_ShowString(uint8_t x,uint8_t y, uint8_t *p,uint8_t Char_Size);
+void OLED_ShowChinese(uint8_t x,uint8_t y,uint8_t no);
+void OLED_DrawBMP(unsigned char x0, unsigned char y0,unsigned char x1, unsigned char y1,unsigned char BMP[]);
+
+
+
+//OLED基础函数
+void OLED_Init(void);
+void OLED_Clear(void);
+void OLED_Display_On(void);
+void OLED_Display_Off(void);
+void OLED_Set_Pos(unsigned char x, unsigned char y);
+#endif

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Hardware/OLED/oledfont.h

@@ -0,0 +1,230 @@
+#ifndef __OLEDFONT_H
+#define __OLEDFONT_H
+//常用ASCII表
+//偏移量32
+//ASCII字符集
+//偏移量32
+//大小:12*6
+/************************************6*8的点阵************************************/
+const unsigned char F6x8[][6] =
+{
+{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},// sp
+{0x00, 0x00, 0x00, 0x2f, 0x00, 0x00},// !
+{0x00, 0x00, 0x07, 0x00, 0x07, 0x00},// "
+{0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14},// #
+{0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12},// $
+{0x00, 0x62, 0x64, 0x08, 0x13, 0x23},// %
+{0x00, 0x36, 0x49, 0x55, 0x22, 0x50},// &
+{0x00, 0x00, 0x05, 0x03, 0x00, 0x00},// '
+{0x00, 0x00, 0x1c, 0x22, 0x41, 0x00},// (
+{0x00, 0x00, 0x41, 0x22, 0x1c, 0x00},// )
+{0x00, 0x14, 0x08, 0x3E, 0x08, 0x14},// *
+{0x00, 0x08, 0x08, 0x3E, 0x08, 0x08},// +
+{0x00, 0x00, 0x00, 0xA0, 0x60, 0x00},// ,
+{0x00, 0x08, 0x08, 0x08, 0x08, 0x08},// -
+{0x00, 0x00, 0x60, 0x60, 0x00, 0x00},// .
+{0x00, 0x20, 0x10, 0x08, 0x04, 0x02},// /
+{0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E},// 0
+{0x00, 0x00, 0x42, 0x7F, 0x40, 0x00},// 1
+{0x00, 0x42, 0x61, 0x51, 0x49, 0x46},// 2
+{0x00, 0x21, 0x41, 0x45, 0x4B, 0x31},// 3
+{0x00, 0x18, 0x14, 0x12, 0x7F, 0x10},// 4
+{0x00, 0x27, 0x45, 0x45, 0x45, 0x39},// 5
+{0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30},// 6
+{0x00, 0x01, 0x71, 0x09, 0x05, 0x03},// 7
+{0x00, 0x36, 0x49, 0x49, 0x49, 0x36},// 8
+{0x00, 0x06, 0x49, 0x49, 0x29, 0x1E},// 9
+{0x00, 0x00, 0x36, 0x36, 0x00, 0x00},// :
+{0x00, 0x00, 0x56, 0x36, 0x00, 0x00},// ;
+{0x00, 0x08, 0x14, 0x22, 0x41, 0x00},// <
+{0x00, 0x14, 0x14, 0x14, 0x14, 0x14},// =
+{0x00, 0x00, 0x41, 0x22, 0x14, 0x08},// >
+{0x00, 0x02, 0x01, 0x51, 0x09, 0x06},// ?
+{0x00, 0x32, 0x49, 0x59, 0x51, 0x3E},// @
+{0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C},// A
+{0x00, 0x7F, 0x49, 0x49, 0x49, 0x36},// B
+{0x00, 0x3E, 0x41, 0x41, 0x41, 0x22},// C
+{0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C},// D
+{0x00, 0x7F, 0x49, 0x49, 0x49, 0x41},// E
+{0x00, 0x7F, 0x09, 0x09, 0x09, 0x01},// F
+{0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A},// G
+{0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F},// H
+{0x00, 0x00, 0x41, 0x7F, 0x41, 0x00},// I
+{0x00, 0x20, 0x40, 0x41, 0x3F, 0x01},// J
+{0x00, 0x7F, 0x08, 0x14, 0x22, 0x41},// K
+{0x00, 0x7F, 0x40, 0x40, 0x40, 0x40},// L
+{0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F},// M
+{0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F},// N
+{0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E},// O
+{0x00, 0x7F, 0x09, 0x09, 0x09, 0x06},// P
+{0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E},// Q
+{0x00, 0x7F, 0x09, 0x19, 0x29, 0x46},// R
+{0x00, 0x46, 0x49, 0x49, 0x49, 0x31},// S
+{0x00, 0x01, 0x01, 0x7F, 0x01, 0x01},// T
+{0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F},// U
+{0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F},// V
+{0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F},// W
+{0x00, 0x63, 0x14, 0x08, 0x14, 0x63},// X
+{0x00, 0x07, 0x08, 0x70, 0x08, 0x07},// Y
+{0x00, 0x61, 0x51, 0x49, 0x45, 0x43},// Z
+{0x00, 0x00, 0x7F, 0x41, 0x41, 0x00},// [
+{0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55},// 55
+{0x00, 0x00, 0x41, 0x41, 0x7F, 0x00},// ]
+{0x00, 0x04, 0x02, 0x01, 0x02, 0x04},// ^
+{0x00, 0x40, 0x40, 0x40, 0x40, 0x40},// _
+{0x00, 0x00, 0x01, 0x02, 0x04, 0x00},// '
+{0x00, 0x20, 0x54, 0x54, 0x54, 0x78},// a
+{0x00, 0x7F, 0x48, 0x44, 0x44, 0x38},// b
+{0x00, 0x38, 0x44, 0x44, 0x44, 0x20},// c
+{0x00, 0x38, 0x44, 0x44, 0x48, 0x7F},// d
+{0x00, 0x38, 0x54, 0x54, 0x54, 0x18},// e
+{0x00, 0x08, 0x7E, 0x09, 0x01, 0x02},// f
+{0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C},// g
+{0x00, 0x7F, 0x08, 0x04, 0x04, 0x78},// h
+{0x00, 0x00, 0x44, 0x7D, 0x40, 0x00},// i
+{0x00, 0x40, 0x80, 0x84, 0x7D, 0x00},// j
+{0x00, 0x7F, 0x10, 0x28, 0x44, 0x00},// k
+{0x00, 0x00, 0x41, 0x7F, 0x40, 0x00},// l
+{0x00, 0x7C, 0x04, 0x18, 0x04, 0x78},// m
+{0x00, 0x7C, 0x08, 0x04, 0x04, 0x78},// n
+{0x00, 0x38, 0x44, 0x44, 0x44, 0x38},// o
+{0x00, 0xFC, 0x24, 0x24, 0x24, 0x18},// p
+{0x00, 0x18, 0x24, 0x24, 0x18, 0xFC},// q
+{0x00, 0x7C, 0x08, 0x04, 0x04, 0x08},// r
+{0x00, 0x48, 0x54, 0x54, 0x54, 0x20},// s
+{0x00, 0x04, 0x3F, 0x44, 0x40, 0x20},// t
+{0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C},// u
+{0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C},// v
+{0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C},// w
+{0x00, 0x44, 0x28, 0x10, 0x28, 0x44},// x
+{0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C},// y
+{0x00, 0x44, 0x64, 0x54, 0x4C, 0x44},// z
+{0x14, 0x14, 0x14, 0x14, 0x14, 0x14},// horiz lines
+};
+/****************************************8*16的点阵************************************/
+const unsigned char F8X16[]=
+{
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0
+  0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1
+  0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2
+  0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3
+  0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4
+  0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5
+  0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6
+  0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7
+  0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8
+  0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9
+  0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10
+  0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14
+  0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16
+  0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17
+  0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18
+  0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19
+  0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20
+  0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21
+  0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22
+  0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23
+  0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25
+  0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26
+  0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27
+  0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28
+  0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29
+  0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30
+  0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31
+  0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32
+  0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33
+  0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34
+  0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35
+  0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38
+  0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40
+  0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41
+  0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42
+  0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43
+  0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44
+  0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45
+  0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47
+  0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49
+  0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50
+  0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51
+  0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53
+  0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54
+  0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55
+  0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56
+  0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57
+  0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58
+  0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59
+  0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60
+  0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61
+  0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63
+  0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65
+  0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66
+  0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67
+  0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69
+  0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71
+  0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72
+  0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73
+  0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74
+  0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75
+  0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76
+  0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77
+  0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79
+  0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80
+  0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81
+  0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83
+  0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84
+  0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86
+  0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87
+  0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89
+  0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90
+  0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91
+  0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92
+  0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93
+  0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94
+};
+char Hzk[][16]={
+
+{0x40,0x3C,0x10,0xFF,0x10,0x10,0x20,0x10,0x8F,0x78,0x08,0xF8,0x08,0xF8,0x00,0x00},
+{0x02,0x06,0x02,0xFF,0x01,0x01,0x04,0x42,0x21,0x18,0x46,0x81,0x40,0x3F,0x00,0x00},/*"物",0*/
+/* (16 X 16 , 宋体 )*/
+
+{0x02,0xFE,0x92,0x92,0xFE,0x02,0x00,0x10,0x11,0x16,0xF0,0x14,0x13,0x10,0x00,0x00},
+{0x10,0x1F,0x08,0x08,0xFF,0x04,0x81,0x41,0x31,0x0D,0x03,0x0D,0x31,0x41,0x81,0x00},/*"联",1*/
+/* (16 X 16 , 宋体 )*/
+
+{0x00,0xFE,0x02,0x22,0x42,0x82,0x72,0x02,0x22,0x42,0x82,0x72,0x02,0xFE,0x00,0x00},
+{0x00,0xFF,0x10,0x08,0x06,0x01,0x0E,0x10,0x08,0x06,0x01,0x4E,0x80,0x7F,0x00,0x00},/*"网",2*/
+/* (16 X 16 , 宋体 )*/
+
+{0x00,0x80,0x60,0xF8,0x07,0x00,0xFE,0x52,0x52,0x52,0x52,0x52,0xFE,0x00,0x00,0x00},
+{0x01,0x00,0x00,0xFF,0x08,0x88,0x4F,0x29,0x09,0x09,0x09,0x29,0x4F,0x88,0x08,0x00},/*"俱",3*/
+/* (16 X 16 , 宋体 )*/
+
+{0x00,0x00,0xE0,0x9C,0x84,0x84,0x84,0xF4,0x82,0x82,0x83,0x82,0x80,0x80,0x00,0x00},
+{0x00,0x20,0x10,0x08,0x06,0x40,0x80,0x7F,0x00,0x00,0x02,0x04,0x08,0x30,0x00,0x00},/*"乐",4*/
+/* (16 X 16 , 宋体 )*/
+
+{0x40,0x44,0x54,0x65,0x46,0x44,0x64,0x54,0x44,0x40,0xFE,0x02,0x22,0xDA,0x06,0x00},
+{0x00,0x00,0x7E,0x22,0x22,0x22,0x22,0x7E,0x00,0x00,0xFF,0x08,0x10,0x08,0x07,0x00},/*"部",5*/
+/* (16 X 16 , 宋体 )*/
+};
+
+#endif

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/adc.h

@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * File Name          : ADC.h
+  * Description        : This file provides code for the configuration
+  *                      of the ADC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __adc_H
+#define __adc_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern ADC_HandleTypeDef hadc1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_ADC1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ adc_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/dac.h

@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * File Name          : DAC.h
+  * Description        : This file provides code for the configuration
+  *                      of the DAC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __dac_H
+#define __dac_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern DAC_HandleTypeDef hdac1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_DAC1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ dac_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/gpio.h

@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * File Name          : gpio.h
+  * Description        : This file contains all the functions prototypes for
+  *                      the gpio
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __gpio_H
+#define __gpio_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_GPIO_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ pinoutConfig_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/i2c.h

@@ -0,0 +1,60 @@
+/**
+  ******************************************************************************
+  * File Name          : I2C.h
+  * Description        : This file provides code for the configuration
+  *                      of the I2C instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __i2c_H
+#define __i2c_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern I2C_HandleTypeDef hi2c1;
+extern I2C_HandleTypeDef hi2c3;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_I2C1_Init(void);
+void MX_I2C3_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ i2c_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/main.h

@@ -0,0 +1,90 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal.h"
+#include "stm32l5xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED_Pin GPIO_PIN_13
+#define LED_GPIO_Port GPIOC
+#define OLED_SCL_Pin GPIO_PIN_7
+#define OLED_SCL_GPIO_Port GPIOA
+#define KEY2_Pin GPIO_PIN_2
+#define KEY2_GPIO_Port GPIOB
+#define KEY2_EXTI_IRQn EXTI2_IRQn
+#define KEY1_Pin GPIO_PIN_12
+#define KEY1_GPIO_Port GPIOB
+#define KEY1_EXTI_IRQn EXTI12_IRQn
+#define KEY4_Pin GPIO_PIN_13
+#define KEY4_GPIO_Port GPIOB
+#define KEY4_EXTI_IRQn EXTI13_IRQn
+#define KEY3_Pin GPIO_PIN_10
+#define KEY3_GPIO_Port GPIOC
+#define KEY3_EXTI_IRQn EXTI10_IRQn
+#define OLED_SDA_Pin GPIO_PIN_4
+#define OLED_SDA_GPIO_Port GPIOB
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/mcu_init.h

@@ -0,0 +1,26 @@
+#ifndef __MCU_INIT_H
+#define __MCU_INIT_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "main.h"
+#include "adc.h"
+#include "dac.h"
+#include "i2c.h"
+#include "usart.h"
+#include "octospi.h"
+#include "sdmmc.h"
+#include "spi.h"
+#include "gpio.h"
+#include "stdio.h"
+#include "oled.h"
+#include "tos_k.h"
+
+void board_init(void);
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ __MCU_INIT_H */

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/octospi.h

@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * File Name          : OCTOSPI.h
+  * Description        : This file provides code for the configuration
+  *                      of the OCTOSPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __octospi_H
+#define __octospi_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern OSPI_HandleTypeDef hospi1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_OCTOSPI1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ octospi_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/sdmmc.h

@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * File Name          : SDMMC.h
+  * Description        : This file provides code for the configuration
+  *                      of the SDMMC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __sdmmc_H
+#define __sdmmc_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SD_HandleTypeDef hsd1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_SDMMC1_SD_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ sdmmc_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/spi.h

@@ -0,0 +1,60 @@
+/**
+  ******************************************************************************
+  * File Name          : SPI.h
+  * Description        : This file provides code for the configuration
+  *                      of the SPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __spi_H
+#define __spi_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SPI_HandleTypeDef hspi1;
+extern SPI_HandleTypeDef hspi3;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_SPI1_Init(void);
+void MX_SPI3_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ spi_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/stm32l5xx_hal_conf.h

@@ -0,0 +1,436 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CONF_H
+#define STM32L5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+#define HAL_DAC_MODULE_ENABLED
+/*#define HAL_DFSDM_MODULE_ENABLED   */
+/*#define HAL_FDCAN_MODULE_ENABLED   */
+/*#define HAL_GTZC_MODULE_ENABLED   */
+/*#define HAL_HASH_MODULE_ENABLED   */
+#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_MMC_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_OPAMP_MODULE_ENABLED   */
+#define HAL_OSPI_MODULE_ENABLED
+/*#define HAL_OTFDEC_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_RCC_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_ICACHE_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    16000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+ #define HSI48_VALUE   48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                          The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  32000UL       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                          The real value may vary depending on the variations
+                                          in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    32768UL /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000UL   /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/**
+  * @brief External clock source for SAI2 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
+  #define EXTERNAL_SAI2_CLOCK_VALUE    48000UL /*!< Value of the SAI2 External clock source in Hz*/
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+
+#define  VDD_VALUE					  3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0UL    /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32l5xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS      0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS      0U
+#define USE_HAL_HASH_REGISTER_CALLBACKS       0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_MMC_REGISTER_CALLBACKS        0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS       0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS        0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS      0U
+#define USE_HAL_OSPI_REGISTER_CALLBACKS       0U
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS     0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_PKA_REGISTER_CALLBACKS        0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SD_REGISTER_CALLBACKS         0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS       0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_TSC_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME   1U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER            1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32l5xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l5xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32l5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32l5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+  #include "stm32l5xx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32l5xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+  #include "stm32l5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+  #include "stm32l5xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+  #include "stm32l5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+  #include "stm32l5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32l5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+  #include "stm32l5xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32l5xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32l5xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+  #include "stm32l5xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32l5xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+  #include "stm32l5xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32l5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32l5xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+  #include "stm32l5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32l5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+  #include "stm32l5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+  #include "stm32l5xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+  #include "stm32l5xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+  #include "stm32l5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+  #include "stm32l5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+  #include "stm32l5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32l5xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+  #include "stm32l5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32l5xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+  #include "stm32l5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+  #include "stm32l5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+  #include "stm32l5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/stm32l5xx_it.h

@@ -0,0 +1,87 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L5xx_IT_H
+#define __STM32L5xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI2_IRQHandler(void);
+void EXTI10_IRQHandler(void);
+void EXTI12_IRQHandler(void);
+void EXTI13_IRQHandler(void);
+void ADC1_2_IRQHandler(void);
+void DAC_IRQHandler(void);
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void USART1_IRQHandler(void);
+void USART2_IRQHandler(void);
+void USART3_IRQHandler(void);
+void LPUART1_IRQHandler(void);
+void OCTOSPI1_IRQHandler(void);
+void SDMMC1_IRQHandler(void);
+void I2C3_EV_IRQHandler(void);
+void I2C3_ER_IRQHandler(void);
+void SPI3_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L5xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Inc/usart.h

@@ -0,0 +1,64 @@
+/**
+  ******************************************************************************
+  * File Name          : USART.h
+  * Description        : This file provides code for the configuration
+  *                      of the USART instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __usart_H
+#define __usart_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+extern UART_HandleTypeDef huart2;
+extern UART_HandleTypeDef huart3;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_LPUART1_UART_Init(void);
+void MX_USART1_UART_Init(void);
+void MX_USART2_UART_Init(void);
+void MX_USART3_UART_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ usart_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/adc.c

@@ -0,0 +1,153 @@
+/**
+  ******************************************************************************
+  * File Name          : ADC.c
+  * Description        : This file provides code for the configuration
+  *                      of the ADC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "adc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+ADC_HandleTypeDef hadc1;
+
+/* ADC1 init function */
+void MX_ADC1_Init(void)
+{
+  ADC_MultiModeTypeDef multimode = {0};
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /** Common config
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc1.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure the ADC multi-mode
+  */
+  multimode.Mode = ADC_MODE_INDEPENDENT;
+  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_3;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(adcHandle->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+    PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
+    PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSAI1SOURCE_MSI;
+    PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    PeriphClkInit.PLLSAI1.PLLSAI1N = 16;
+    PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_ADC1CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* ADC1 clock enable */
+    __HAL_RCC_ADC_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    /**ADC1 GPIO Configuration
+    PC2     ------> ADC1_IN3
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    /* ADC1 interrupt Init */
+    HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+}
+
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
+{
+
+  if(adcHandle->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC_CLK_DISABLE();
+
+    /**ADC1 GPIO Configuration
+    PC2     ------> ADC1_IN3
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2);
+
+    /* ADC1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(ADC1_2_IRQn);
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/dac.c

@@ -0,0 +1,113 @@
+/**
+  ******************************************************************************
+  * File Name          : DAC.c
+  * Description        : This file provides code for the configuration
+  *                      of the DAC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "dac.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+DAC_HandleTypeDef hdac1;
+
+/* DAC1 init function */
+void MX_DAC1_Init(void)
+{
+  DAC_ChannelConfTypeDef sConfig = {0};
+
+  /** DAC Initialization
+  */
+  hdac1.Instance = DAC1;
+  if (HAL_DAC_Init(&hdac1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** DAC channel OUT2 config
+  */
+  sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
+  sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+  sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+  sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
+  sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
+  if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(dacHandle->Instance==DAC1)
+  {
+  /* USER CODE BEGIN DAC1_MspInit 0 */
+
+  /* USER CODE END DAC1_MspInit 0 */
+    /* DAC1 clock enable */
+    __HAL_RCC_DAC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**DAC1 GPIO Configuration
+    PA5     ------> DAC1_OUT2
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* DAC1 interrupt Init */
+    HAL_NVIC_SetPriority(DAC_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(DAC_IRQn);
+  /* USER CODE BEGIN DAC1_MspInit 1 */
+
+  /* USER CODE END DAC1_MspInit 1 */
+  }
+}
+
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* dacHandle)
+{
+
+  if(dacHandle->Instance==DAC1)
+  {
+  /* USER CODE BEGIN DAC1_MspDeInit 0 */
+
+  /* USER CODE END DAC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_DAC1_CLK_DISABLE();
+
+    /**DAC1 GPIO Configuration
+    PA5     ------> DAC1_OUT2
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+
+    /* DAC1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(DAC_IRQn);
+  /* USER CODE BEGIN DAC1_MspDeInit 1 */
+
+  /* USER CODE END DAC1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/gpio.c

@@ -0,0 +1,92 @@
+/**
+  ******************************************************************************
+  * File Name          : gpio.c
+  * Description        : This file provides code for the configuration
+  *                      of all used GPIO pins.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gpio.h"
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure GPIO                                                             */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/** Configure pins
+     PC14-OSC32_IN (PC14)   ------> RCC_OSC32_IN
+     PC15-OSC32_OUT (PC15)   ------> RCC_OSC32_OUT
+     PH0-OSC_IN (PH0)   ------> RCC_OSC_IN
+     PH1-OSC_OUT (PH1)   ------> RCC_OSC_OUT
+*/
+void MX_GPIO_Init(void)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = LED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PBPin PBPin PBPin */
+  GPIO_InitStruct.Pin = KEY2_Pin|KEY1_Pin|KEY4_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = KEY3_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(KEY3_GPIO_Port, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  HAL_NVIC_SetPriority(EXTI2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(EXTI2_IRQn);
+
+  HAL_NVIC_SetPriority(EXTI10_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(EXTI10_IRQn);
+
+  HAL_NVIC_SetPriority(EXTI12_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(EXTI12_IRQn);
+
+  HAL_NVIC_SetPriority(EXTI13_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(EXTI13_IRQn);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/i2c.c

@@ -0,0 +1,240 @@
+/**
+  ******************************************************************************
+  * File Name          : I2C.c
+  * Description        : This file provides code for the configuration
+  *                      of the I2C instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "i2c.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+I2C_HandleTypeDef hi2c1;
+I2C_HandleTypeDef hi2c3;
+
+/* I2C1 init function */
+void MX_I2C1_Init(void)
+{
+
+  hi2c1.Instance = I2C1;
+  hi2c1.Init.Timing = 0x10909CEC;
+  hi2c1.Init.OwnAddress1 = 0;
+  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c1.Init.OwnAddress2 = 0;
+  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+/* I2C3 init function */
+void MX_I2C3_Init(void)
+{
+
+  hi2c3.Instance = I2C3;
+  hi2c3.Init.Timing = 0x10909CEC;
+  hi2c3.Init.OwnAddress1 = 0;
+  hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+  hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+  hi2c3.Init.OwnAddress2 = 0;
+  hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+  hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+  hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+  if (HAL_I2C_Init(&hi2c3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Analogue filter
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Configure Digital filter
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(i2cHandle->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspInit 0 */
+
+  /* USER CODE END I2C1_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+    PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C1 GPIO Configuration
+    PB6     ------> I2C1_SCL
+    PB7     ------> I2C1_SDA
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* I2C1 clock enable */
+    __HAL_RCC_I2C1_CLK_ENABLE();
+
+    /* I2C1 interrupt Init */
+    HAL_NVIC_SetPriority(I2C1_EV_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C1_ER_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C1_ER_IRQn);
+  /* USER CODE BEGIN I2C1_MspInit 1 */
+
+  /* USER CODE END I2C1_MspInit 1 */
+  }
+  else if(i2cHandle->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspInit 0 */
+
+  /* USER CODE END I2C3_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C3;
+    PeriphClkInit.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**I2C3 GPIO Configuration
+    PA7     ------> I2C3_SCL
+    PB4 (NJTRST)     ------> I2C3_SDA
+    */
+    GPIO_InitStruct.Pin = OLED_SCL_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(OLED_SCL_GPIO_Port, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = OLED_SDA_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
+    HAL_GPIO_Init(OLED_SDA_GPIO_Port, &GPIO_InitStruct);
+
+    /* I2C3 clock enable */
+    __HAL_RCC_I2C3_CLK_ENABLE();
+
+    /* I2C3 interrupt Init */
+    HAL_NVIC_SetPriority(I2C3_EV_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C3_EV_IRQn);
+    HAL_NVIC_SetPriority(I2C3_ER_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(I2C3_ER_IRQn);
+  /* USER CODE BEGIN I2C3_MspInit 1 */
+
+  /* USER CODE END I2C3_MspInit 1 */
+  }
+}
+
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
+{
+
+  if(i2cHandle->Instance==I2C1)
+  {
+  /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+  /* USER CODE END I2C1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C1_CLK_DISABLE();
+
+    /**I2C1 GPIO Configuration
+    PB6     ------> I2C1_SCL
+    PB7     ------> I2C1_SDA
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
+
+    /* I2C1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(I2C1_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C1_ER_IRQn);
+  /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+  /* USER CODE END I2C1_MspDeInit 1 */
+  }
+  else if(i2cHandle->Instance==I2C3)
+  {
+  /* USER CODE BEGIN I2C3_MspDeInit 0 */
+
+  /* USER CODE END I2C3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_I2C3_CLK_DISABLE();
+
+    /**I2C3 GPIO Configuration
+    PA7     ------> I2C3_SCL
+    PB4 (NJTRST)     ------> I2C3_SDA
+    */
+    HAL_GPIO_DeInit(OLED_SCL_GPIO_Port, OLED_SCL_Pin);
+
+    HAL_GPIO_DeInit(OLED_SDA_GPIO_Port, OLED_SDA_Pin);
+
+    /* I2C3 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(I2C3_EV_IRQn);
+    HAL_NVIC_DisableIRQ(I2C3_ER_IRQn);
+  /* USER CODE BEGIN I2C3_MspDeInit 1 */
+
+  /* USER CODE END I2C3_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/main.c

@@ -0,0 +1,24 @@
+#include "mcu_init.h"
+#include "cmsis_os.h"
+
+#define APPLICATION_TASK_STK_SIZE       4096
+
+extern void application_entry(void *arg);
+osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE);
+
+__weak void application_entry(void *arg)
+{
+    while (1) {
+        printf("This is a demo task,please use your task entry!\r\n");
+        tos_task_delay(1000);
+    }
+}
+
+int main(void)
+{
+    board_init();
+    printf("Welcome to TencentOS tiny\r\n");
+    osKernelInitialize(); // TOS Tiny kernel initialize
+    osThreadCreate(osThread(application_entry), NULL); // Create TOS Tiny task
+    osKernelStart(); // Start TOS Tiny
+}

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/mcu_init.c

@@ -0,0 +1,169 @@
+#include "mcu_init.h"
+
+int fputc(int ch, FILE *f)
+{
+    if (ch == '\n') {
+        HAL_UART_Transmit(&huart2, (void *)"\r", 1, 30000);
+    }
+    HAL_UART_Transmit(&huart2, (uint8_t *)&ch, 1, 0xFFFF);
+    return ch;
+
+}
+int _write(int fd, char *ptr, int len)
+{
+    (void)HAL_UART_Transmit(&huart2, (uint8_t *)ptr, len, 0xFFFF);
+    return len;
+}
+
+int fgetc(FILE *f)
+{
+  uint8_t ch = 0;
+  HAL_UART_Receive(&huart2, &ch, 1,30000);
+  return ch;
+}
+
+void OLED_GPIO_Init(void)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+	
+  HAL_GPIO_WritePin(GPIOA, GPIO_PIN_7, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = GPIO_PIN_7;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+}
+
+void board_init(void)
+{
+  char *str = "TencentOS Tiny!";
+
+  HAL_Init();
+  SystemClock_Config();
+  MX_GPIO_Init();
+  MX_ADC1_Init();
+  MX_DAC1_Init();
+  MX_I2C1_Init();
+  MX_I2C3_Init();
+  MX_LPUART1_UART_Init();
+  MX_USART1_UART_Init();
+  MX_USART2_UART_Init();
+  MX_USART3_UART_Init();
+  MX_OCTOSPI1_Init();
+  MX_SDMMC1_SD_Init();
+  MX_SPI1_Init();
+  MX_SPI3_Init();
+  OLED_GPIO_Init();
+  OLED_Init();
+  OLED_Clear();
+  OLED_ShowChinese(0,0,0);
+  OLED_ShowChinese(18,0,1);
+  OLED_ShowChinese(36,0,2);
+  OLED_ShowChinese(54,0,3);
+  OLED_ShowChinese(72,0,4);
+  OLED_ShowChinese(90,0,5);
+  OLED_ShowString(0,2,(uint8_t*)str,16);
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_8;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/octospi.c

@@ -0,0 +1,131 @@
+/**
+  ******************************************************************************
+  * File Name          : OCTOSPI.c
+  * Description        : This file provides code for the configuration
+  *                      of the OCTOSPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "octospi.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+OSPI_HandleTypeDef hospi1;
+
+/* OCTOSPI1 init function */
+void MX_OCTOSPI1_Init(void)
+{
+
+  hospi1.Instance = OCTOSPI1;
+  hospi1.Init.FifoThreshold = 1;
+  hospi1.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
+  hospi1.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;
+  hospi1.Init.DeviceSize = 32;
+  hospi1.Init.ChipSelectHighTime = 1;
+  hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
+  hospi1.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;
+  hospi1.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
+  hospi1.Init.ClockPrescaler = 1;
+  hospi1.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE;
+  hospi1.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE;
+  hospi1.Init.ChipSelectBoundary = 0;
+  hospi1.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED;
+  hospi1.Init.Refresh = 0;
+  if (HAL_OSPI_Init(&hospi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_OSPI_MspInit(OSPI_HandleTypeDef* ospiHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(ospiHandle->Instance==OCTOSPI1)
+  {
+  /* USER CODE BEGIN OCTOSPI1_MspInit 0 */
+
+  /* USER CODE END OCTOSPI1_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI;
+    PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* OCTOSPI1 clock enable */
+    __HAL_RCC_OSPI1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**OCTOSPI1 GPIO Configuration
+    PB0     ------> OCTOSPI1_IO1
+    PB1     ------> OCTOSPI1_IO0
+    PB10     ------> OCTOSPI1_CLK
+    PB11     ------> OCTOSPI1_NCS
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* OCTOSPI1 interrupt Init */
+    HAL_NVIC_SetPriority(OCTOSPI1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(OCTOSPI1_IRQn);
+  /* USER CODE BEGIN OCTOSPI1_MspInit 1 */
+
+  /* USER CODE END OCTOSPI1_MspInit 1 */
+  }
+}
+
+void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef* ospiHandle)
+{
+
+  if(ospiHandle->Instance==OCTOSPI1)
+  {
+  /* USER CODE BEGIN OCTOSPI1_MspDeInit 0 */
+
+  /* USER CODE END OCTOSPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_OSPI1_CLK_DISABLE();
+
+    /**OCTOSPI1 GPIO Configuration
+    PB0     ------> OCTOSPI1_IO1
+    PB1     ------> OCTOSPI1_IO0
+    PB10     ------> OCTOSPI1_CLK
+    PB11     ------> OCTOSPI1_NCS
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_11);
+
+    /* OCTOSPI1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(OCTOSPI1_IRQn);
+  /* USER CODE BEGIN OCTOSPI1_MspDeInit 1 */
+
+  /* USER CODE END OCTOSPI1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/sdmmc.c

@@ -0,0 +1,132 @@
+/**
+  ******************************************************************************
+  * File Name          : SDMMC.c
+  * Description        : This file provides code for the configuration
+  *                      of the SDMMC instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "sdmmc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SD_HandleTypeDef hsd1;
+
+/* SDMMC1 init function */
+
+void MX_SDMMC1_SD_Init(void)
+{
+
+  hsd1.Instance = SDMMC1;
+  hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+  hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_1B;
+  hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd1.Init.ClockDiv = 0;
+  hsd1.Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+  if (HAL_SD_Init(&hsd1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(sdHandle->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1;
+    PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLLP;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* SDMMC1 clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC1 GPIO Configuration
+    PC8     ------> SDMMC1_D0
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* SDMMC1 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+}
+
+void HAL_SD_MspDeInit(SD_HandleTypeDef* sdHandle)
+{
+
+  if(sdHandle->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+  /* USER CODE END SDMMC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+    /**SDMMC1 GPIO Configuration
+    PC8     ------> SDMMC1_D0
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_12);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+    /* SDMMC1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+  /* USER CODE END SDMMC1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/spi.c

@@ -0,0 +1,216 @@
+/**
+  ******************************************************************************
+  * File Name          : SPI.c
+  * Description        : This file provides code for the configuration
+  *                      of the SPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "spi.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SPI_HandleTypeDef hspi1;
+SPI_HandleTypeDef hspi3;
+
+/* SPI1 init function */
+void MX_SPI1_Init(void)
+{
+
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 7;
+  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+/* SPI3 init function */
+void MX_SPI3_Init(void)
+{
+
+  hspi3.Instance = SPI3;
+  hspi3.Init.Mode = SPI_MODE_MASTER;
+  hspi3.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi3.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi3.Init.NSS = SPI_NSS_HARD_OUTPUT;
+  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
+  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi3.Init.CRCPolynomial = 7;
+  hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  if (HAL_SPI_Init(&hspi3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(spiHandle->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* SPI1 clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration
+    PA1     ------> SPI1_SCK
+    PA4     ------> SPI1_NSS
+    PA11     ------> SPI1_MISO
+    PA12     ------> SPI1_MOSI
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* SPI1 interrupt Init */
+    HAL_NVIC_SetPriority(SPI1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SPI1_IRQn);
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+  else if(spiHandle->Instance==SPI3)
+  {
+  /* USER CODE BEGIN SPI3_MspInit 0 */
+
+  /* USER CODE END SPI3_MspInit 0 */
+    /* SPI3 clock enable */
+    __HAL_RCC_SPI3_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI3 GPIO Configuration
+    PA15 (JTDI)     ------> SPI3_NSS
+    PC11     ------> SPI3_MISO
+    PB3 (JTDO/TRACESWO)     ------> SPI3_SCK
+    PB5     ------> SPI3_MOSI
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* SPI3 interrupt Init */
+    HAL_NVIC_SetPriority(SPI3_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SPI3_IRQn);
+  /* USER CODE BEGIN SPI3_MspInit 1 */
+
+  /* USER CODE END SPI3_MspInit 1 */
+  }
+}
+
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
+{
+
+  if(spiHandle->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+
+    /**SPI1 GPIO Configuration
+    PA1     ------> SPI1_SCK
+    PA4     ------> SPI1_NSS
+    PA11     ------> SPI1_MISO
+    PA12     ------> SPI1_MOSI
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_11|GPIO_PIN_12);
+
+    /* SPI1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SPI1_IRQn);
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+  else if(spiHandle->Instance==SPI3)
+  {
+  /* USER CODE BEGIN SPI3_MspDeInit 0 */
+
+  /* USER CODE END SPI3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI3_CLK_DISABLE();
+
+    /**SPI3 GPIO Configuration
+    PA15 (JTDI)     ------> SPI3_NSS
+    PC11     ------> SPI3_MISO
+    PB3 (JTDO/TRACESWO)     ------> SPI3_SCK
+    PB5     ------> SPI3_MOSI
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
+
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_5);
+
+    /* SPI3 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SPI3_IRQn);
+  /* USER CODE BEGIN SPI3_MspDeInit 1 */
+
+  /* USER CODE END SPI3_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/stm32l5xx_hal_msp.c

@@ -0,0 +1,88 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32l5xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
+  */
+  HAL_PWREx_DisableUCPDDeadBattery();
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/stm32l5xx_it.c

@@ -0,0 +1,473 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32l5xx_it.h"
+#include "tos_k.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern ADC_HandleTypeDef hadc1;
+extern DAC_HandleTypeDef hdac1;
+extern I2C_HandleTypeDef hi2c1;
+extern I2C_HandleTypeDef hi2c3;
+extern UART_HandleTypeDef hlpuart1;
+extern UART_HandleTypeDef huart1;
+extern UART_HandleTypeDef huart2;
+extern UART_HandleTypeDef huart3;
+extern OSPI_HandleTypeDef hospi1;
+extern SD_HandleTypeDef hsd1;
+extern SPI_HandleTypeDef hspi1;
+extern SPI_HandleTypeDef hspi3;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+__weak void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  if (tos_knl_is_running())
+  {
+    tos_knl_irq_enter();
+    tos_tick_handler();
+    tos_knl_irq_leave();
+  }
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32L5xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32l5xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line2 interrupt.
+  */
+void EXTI2_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI2_IRQn 0 */
+
+  /* USER CODE END EXTI2_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
+  /* USER CODE BEGIN EXTI2_IRQn 1 */
+
+  /* USER CODE END EXTI2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles EXTI line10 interrupt.
+  */
+void EXTI10_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI10_IRQn 0 */
+
+  /* USER CODE END EXTI10_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
+  /* USER CODE BEGIN EXTI10_IRQn 1 */
+
+  /* USER CODE END EXTI10_IRQn 1 */
+}
+
+/**
+  * @brief This function handles EXTI line12 interrupt.
+  */
+void EXTI12_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI12_IRQn 0 */
+
+  /* USER CODE END EXTI12_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
+  /* USER CODE BEGIN EXTI12_IRQn 1 */
+
+  /* USER CODE END EXTI12_IRQn 1 */
+}
+
+/**
+  * @brief This function handles EXTI line13 interrupt.
+  */
+void EXTI13_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI13_IRQn 0 */
+
+  /* USER CODE END EXTI13_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
+  /* USER CODE BEGIN EXTI13_IRQn 1 */
+
+  /* USER CODE END EXTI13_IRQn 1 */
+}
+
+/**
+  * @brief This function handles ADC1 and ADC2 interrupts.
+  */
+void ADC1_2_IRQHandler(void)
+{
+  /* USER CODE BEGIN ADC1_2_IRQn 0 */
+
+  /* USER CODE END ADC1_2_IRQn 0 */
+  HAL_ADC_IRQHandler(&hadc1);
+  /* USER CODE BEGIN ADC1_2_IRQn 1 */
+
+  /* USER CODE END ADC1_2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DAC1 interrupt.
+  */
+void DAC_IRQHandler(void)
+{
+  /* USER CODE BEGIN DAC_IRQn 0 */
+
+  /* USER CODE END DAC_IRQn 0 */
+  HAL_DAC_IRQHandler(&hdac1);
+  /* USER CODE BEGIN DAC_IRQn 1 */
+
+  /* USER CODE END DAC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C1 event interrupt / I2C1 wake-up interrupt through EXTI line 23.
+  */
+void I2C1_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C1_EV_IRQn 0 */
+
+  /* USER CODE END I2C1_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c1);
+  /* USER CODE BEGIN I2C1_EV_IRQn 1 */
+
+  /* USER CODE END I2C1_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C1 error interrupt.
+  */
+void I2C1_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C1_ER_IRQn 0 */
+
+  /* USER CODE END I2C1_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c1);
+  /* USER CODE BEGIN I2C1_ER_IRQn 1 */
+
+  /* USER CODE END I2C1_ER_IRQn 1 */
+}
+
+/**
+  * @brief This function handles SPI1 global interrupt.
+  */
+void SPI1_IRQHandler(void)
+{
+  /* USER CODE BEGIN SPI1_IRQn 0 */
+
+  /* USER CODE END SPI1_IRQn 0 */
+  HAL_SPI_IRQHandler(&hspi1);
+  /* USER CODE BEGIN SPI1_IRQn 1 */
+
+  /* USER CODE END SPI1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART1 global interrupt / USART1 wake-up interrupt through EXTI line 26.
+  */
+void USART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 27.
+  */
+void USART2_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART2_IRQn 0 */
+
+  /* USER CODE END USART2_IRQn 0 */
+  HAL_UART_IRQHandler(&huart2);
+  /* USER CODE BEGIN USART2_IRQn 1 */
+
+  /* USER CODE END USART2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART3 global interrupt / USART3 wake-up interrupt through EXTI line 28.
+  */
+void USART3_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART3_IRQn 0 */
+
+  /* USER CODE END USART3_IRQn 0 */
+  HAL_UART_IRQHandler(&huart3);
+  /* USER CODE BEGIN USART3_IRQn 1 */
+
+  /* USER CODE END USART3_IRQn 1 */
+}
+
+/**
+  * @brief This function handles LPUART1 global interrupt / LPUART1 wake-up interrupt through EXTI line 31.
+  */
+void LPUART1_IRQHandler(void)
+{
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles OCTOSPI1 global interrupt.
+  */
+void OCTOSPI1_IRQHandler(void)
+{
+  /* USER CODE BEGIN OCTOSPI1_IRQn 0 */
+
+  /* USER CODE END OCTOSPI1_IRQn 0 */
+  HAL_OSPI_IRQHandler(&hospi1);
+  /* USER CODE BEGIN OCTOSPI1_IRQn 1 */
+
+  /* USER CODE END OCTOSPI1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles SDMMC1 global interrupt.
+  */
+void SDMMC1_IRQHandler(void)
+{
+  /* USER CODE BEGIN SDMMC1_IRQn 0 */
+
+  /* USER CODE END SDMMC1_IRQn 0 */
+  HAL_SD_IRQHandler(&hsd1);
+  /* USER CODE BEGIN SDMMC1_IRQn 1 */
+
+  /* USER CODE END SDMMC1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C3 event interrupt / I2C3 wake-up interrupt through EXTI line 25.
+  */
+void I2C3_EV_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C3_EV_IRQn 0 */
+
+  /* USER CODE END I2C3_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c3);
+  /* USER CODE BEGIN I2C3_EV_IRQn 1 */
+
+  /* USER CODE END I2C3_EV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles I2C3 error interrupt.
+  */
+void I2C3_ER_IRQHandler(void)
+{
+  /* USER CODE BEGIN I2C3_ER_IRQn 0 */
+
+  /* USER CODE END I2C3_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c3);
+  /* USER CODE BEGIN I2C3_ER_IRQn 1 */
+
+  /* USER CODE END I2C3_ER_IRQn 1 */
+}
+
+/**
+  * @brief This function handles SPI3 global interrupt.
+  */
+void SPI3_IRQHandler(void)
+{
+  /* USER CODE BEGIN SPI3_IRQn 0 */
+
+  /* USER CODE END SPI3_IRQn 0 */
+  HAL_SPI_IRQHandler(&hspi3);
+  /* USER CODE BEGIN SPI3_IRQn 1 */
+
+  /* USER CODE END SPI3_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/system_stm32l5xx.c

@@ -0,0 +1,344 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l5xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_SRC                            | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_M                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_N                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_SRC                            | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_M                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_N                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB FS,              | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l5xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 4000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint32_t MSIRangeTable[16] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \
+                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
+                                      0U,       0U,       0U,        0U};  /* MISRAC-2012: 0U for unexpected value */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+  if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
+  { /* MSISRANGE from RCC_CSR applies */
+    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
+  }
+  else
+  { /* MSIRANGE from RCC_CR applies */
+    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
+  }
+  /*MSI frequency range in HZ*/
+  msirange = MSIRangeTable[msirange];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:  /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C:  /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
+
+      switch (pllsource)
+      {
+        case 0x02:  /* HSI used as PLL clock source */
+          pllvco = (HSI_VALUE / pllm);
+          break;
+
+        case 0x03:  /* HSE used as PLL clock source */
+          pllvco = (HSE_VALUE / pllm);
+          break;
+
+        default:    /* MSI used as PLL clock source */
+          pllvco = (msirange / pllm);
+          break;
+      }
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/BSP/Src/usart.c

@@ -0,0 +1,412 @@
+/**
+  ******************************************************************************
+  * File Name          : USART.c
+  * Description        : This file provides code for the configuration
+  *                      of the USART instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usart.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+UART_HandleTypeDef hlpuart1;
+UART_HandleTypeDef huart1;
+UART_HandleTypeDef huart2;
+UART_HandleTypeDef huart3;
+
+/* LPUART1 init function */
+
+void MX_LPUART1_UART_Init(void)
+{
+
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 209700;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+/* USART1 init function */
+
+void MX_USART1_UART_Init(void)
+{
+
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+/* USART2 init function */
+
+void MX_USART2_UART_Init(void)
+{
+
+  huart2.Instance = USART2;
+  huart2.Init.BaudRate = 115200;
+  huart2.Init.WordLength = UART_WORDLENGTH_8B;
+  huart2.Init.StopBits = UART_STOPBITS_1;
+  huart2.Init.Parity = UART_PARITY_NONE;
+  huart2.Init.Mode = UART_MODE_TX_RX;
+  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+/* USART3 init function */
+
+void MX_USART3_UART_Init(void)
+{
+
+  huart3.Instance = USART3;
+  huart3.Init.BaudRate = 115200;
+  huart3.Init.WordLength = UART_WORDLENGTH_8B;
+  huart3.Init.StopBits = UART_STOPBITS_1;
+  huart3.Init.Parity = UART_PARITY_NONE;
+  huart3.Init.Mode = UART_MODE_TX_RX;
+  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(uartHandle->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+  /* USER CODE END LPUART1_MspInit 0 */
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* LPUART1 clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration
+    PC0     ------> LPUART1_RX
+    PC1     ------> LPUART1_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+  /* USER CODE END LPUART1_MspInit 1 */
+  }
+  else if(uartHandle->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+    PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* USART1 clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART1 GPIO Configuration
+    PA9     ------> USART1_TX
+    PA10     ------> USART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* USART1 interrupt Init */
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+  else if(uartHandle->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspInit 0 */
+
+  /* USER CODE END USART2_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
+    PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* USART2 clock enable */
+    __HAL_RCC_USART2_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART2 GPIO Configuration
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* USART2 interrupt Init */
+    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART2_IRQn);
+  /* USER CODE BEGIN USART2_MspInit 1 */
+
+  /* USER CODE END USART2_MspInit 1 */
+  }
+  else if(uartHandle->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspInit 0 */
+
+  /* USER CODE END USART3_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART3;
+    PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* USART3 clock enable */
+    __HAL_RCC_USART3_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    /**USART3 GPIO Configuration
+    PC4     ------> USART3_TX
+    PC5     ------> USART3_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    /* USART3 interrupt Init */
+    HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART3_IRQn);
+  /* USER CODE BEGIN USART3_MspInit 1 */
+
+  /* USER CODE END USART3_MspInit 1 */
+  }
+}
+
+void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
+{
+
+  if(uartHandle->Instance==LPUART1)
+  {
+  /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+  /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+
+    /**LPUART1 GPIO Configuration
+    PC0     ------> LPUART1_RX
+    PC1     ------> LPUART1_TX
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1);
+
+    /* LPUART1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(LPUART1_IRQn);
+  /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+  /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+  else if(uartHandle->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+
+    /**USART1 GPIO Configuration
+    PA9     ------> USART1_TX
+    PA10     ------> USART1_RX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+    /* USART1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(USART1_IRQn);
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+  else if(uartHandle->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+  /* USER CODE END USART2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART2_CLK_DISABLE();
+
+    /**USART2 GPIO Configuration
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
+
+    /* USART2 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(USART2_IRQn);
+  /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+  /* USER CODE END USART2_MspDeInit 1 */
+  }
+  else if(uartHandle->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+  /* USER CODE END USART3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART3_CLK_DISABLE();
+
+    /**USART3 GPIO Configuration
+    PC4     ------> USART3_TX
+    PC5     ------> USART3_RX
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
+
+    /* USART3 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(USART3_IRQn);
+  /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+  /* USER CODE END USART3_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

board/TencentOS_Tiny_EVB_MX_Pro_L5/KEIL/hello_world/TencentOS_Tiny_EVB_MX_Pro_L5.uvprojx

@@ -0,0 +1,853 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>TencentOS_Tiny_EVB_MX_Pro_L5</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L562RETx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32L5xx_DFP.1.2.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000-0x2003FFFF) IROM(0x8000000-0x807FFFF) CLOCK(8000000) FPU3(SFPU) CPUTYPE("Cortex-M33") ELITTLE TZ</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32L562RETx$CMSIS\SVD\STM32L562.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
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+              <Define>USE_HAL_DRIVER,STM32L562xx</Define>
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+            <IncludeLibs></IncludeLibs>
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+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
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+            </File>
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+              <FilePath>..\..\BSP\Src\stm32l5xx_it.c</FilePath>
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+              <FileName>stm32l5xx_hal_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_hal_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l5xx_hal_spi_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_hal_spi_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l5xx_hal_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_hal_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l5xx_hal_tim_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_hal_tim_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l5xx_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_hal_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l5xx_hal_uart_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_hal_uart_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32l5xx_ll_sdmmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\platform\vendor_bsp\st\STM32L5xx_HAL_Driver\Src\stm32l5xx_ll_sdmmc.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers/CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32l5xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\BSP\Src\system_stm32l5xx.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>HardWare</GroupName>
+          <Files>
+            <File>
+              <FileName>oled.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\BSP\Hardware\OLED\oled.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>tos/arch</GroupName>
+          <Files>
+            <File>
+              <FileName>tos_cpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\arch\arm\arm-v8m\common\tos_cpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>port_c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\arch\arm\arm-v8m\cortex-m33\armcc\port_c.c</FilePath>
+            </File>
+            <File>
+              <FileName>port_s.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\..\arch\arm\arm-v8m\cortex-m33\armcc\port_s.S</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>tos/kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>tos_barrier.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_barrier.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_binary_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_bitmap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_bitmap.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_char_fifo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_countdownlatch.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_event.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_global.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_global.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_mail_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_message_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_mmblk.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_mmblk.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_mmheap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_mutex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_mutex.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_pend.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_priority_mail_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_priority_message_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_priority_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_ring_queue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_robin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_robin.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_rwlock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_rwlock.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_sched.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_sched.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_sem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_sem.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_stopwatch.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_stopwatch.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_sys.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_sys.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_task.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_task.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_tick.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_tick.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_time.c</FilePath>
+            </File>
+            <File>
+              <FileName>tos_timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>tos/cmsis</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_os.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\osal\cmsis_os\cmsis_os.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>example</GroupName>
+          <Files>
+            <File>
+              <FileName>hello_world.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\..\examples\hello_world\hello_world.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.3.0" condition="CMSIS Core">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.5.0"/>
+        <targetInfos>
+          <targetInfo name="TencentOS_Tiny_EVB_MX_Pro_L5"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayDesc></LayDesc>
+        <LayUrl></LayUrl>
+        <LayKeys></LayKeys>
+        <LayCat></LayCat>
+        <LayLic></LayLic>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>

board/TencentOS_Tiny_EVB_MX_Pro_L5/KEIL/hello_world/startup_stm32l562xx.s

@@ -0,0 +1,514 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l562xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L562xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size		EQU     0x400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size      EQU     0x200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     SecureFault_Handler       ; Secure Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler        ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     RTC_IRQHandler            ; RTC non-secure interrupts through the EXTI line
+                DCD     RTC_S_IRQHandler          ; RTC secure interrupts through the EXTI line
+                DCD     TAMP_IRQHandler           ; Tamper non-secure interrupts through the EXTI line
+                DCD     TAMP_S_IRQHandler         ; Tamper secure interrupts through the EXTI line
+                DCD     FLASH_IRQHandler          ; FLASH non-secure interrupts
+                DCD     FLASH_S_IRQHandler        ; FLASH secure global interrupts
+                DCD     GTZC_IRQHandler           ; GTZC global interrupts
+                DCD     RCC_IRQHandler            ; RCC non-secure global interrupts
+                DCD     RCC_S_IRQHandler          ; RCC secure global interrupts
+                DCD     EXTI0_IRQHandler          ; EXTI Line0
+                DCD     EXTI1_IRQHandler          ; EXTI Line1
+                DCD     EXTI2_IRQHandler          ; EXTI Line2
+                DCD     EXTI3_IRQHandler          ; EXTI Line3
+                DCD     EXTI4_IRQHandler          ; EXTI Line4
+                DCD     EXTI5_IRQHandler          ; EXTI Line5
+                DCD     EXTI6_IRQHandler          ; EXTI Line6
+                DCD     EXTI7_IRQHandler          ; EXTI Line7
+                DCD     EXTI8_IRQHandler          ; EXTI Line8
+                DCD     EXTI9_IRQHandler          ; EXTI Line9
+                DCD     EXTI10_IRQHandler         ; EXTI Line10
+                DCD     EXTI11_IRQHandler         ; EXTI Line11
+                DCD     EXTI12_IRQHandler         ; EXTI Line12
+                DCD     EXTI13_IRQHandler         ; EXTI Line13
+                DCD     EXTI14_IRQHandler         ; EXTI Line14
+                DCD     EXTI15_IRQHandler         ; EXTI Line15
+                DCD     DMAMUX1_IRQHandler        ; DMAMUX1 non-secure
+                DCD     DMAMUX1_S_IRQHandler      ; DMAMUX1 secure
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     DMA1_Channel8_IRQHandler  ; DMA1 Channel 8
+                DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+                DCD     DAC_IRQHandler            ; DAC1&2 underrun errors
+                DCD     FDCAN1_IT0_IRQHandler     ; FDCAN1 Interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler     ; FDCAN1 Interrupt 1
+                DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     TIM5_IRQHandler           ; TIM5
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+                DCD     TIM8_BRK_IRQHandler       ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler        ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler   ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler        ; TIM8 Capture Compare
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     UART4_IRQHandler          ; UART4
+                DCD     UART5_IRQHandler          ; UART5
+                DCD     LPUART1_IRQHandler        ; LP UART1
+                DCD     LPTIM1_IRQHandler         ; LP TIM1
+                DCD     LPTIM2_IRQHandler         ; LP TIM2
+                DCD     TIM15_IRQHandler          ; TIM15
+                DCD     TIM16_IRQHandler          ; TIM16
+                DCD     TIM17_IRQHandler          ; TIM17
+                DCD     COMP_IRQHandler           ; COMP1&2
+                DCD     USB_FS_IRQHandler         ; USB FS
+                DCD     CRS_IRQHandler            ; CRS
+                DCD     FMC_IRQHandler            ; FMC
+                DCD     OCTOSPI1_IRQHandler       ; OctoSPI1 global interrupt
+                DCD     0                         ; Reserved
+                DCD     SDMMC1_IRQHandler         ; SDMMC1
+                DCD     0                         ; Reserved
+                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+                DCD     DMA2_Channel6_IRQHandler  ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler  ; DMA2 Channel 7
+                DCD     DMA2_Channel8_IRQHandler  ; DMA2 Channel 8
+                DCD     I2C3_EV_IRQHandler        ; I2C3 event
+                DCD     I2C3_ER_IRQHandler        ; I2C3 error
+                DCD     SAI1_IRQHandler           ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler           ; Serial Audio Interface 2 global interrupt
+                DCD     TSC_IRQHandler            ; Touch Sense Controller global interrupt
+                DCD     AES_IRQHandler            ; AES global interrupt
+                DCD     RNG_IRQHandler            ; RNG global interrupt
+                DCD     FPU_IRQHandler            ; FPU
+                DCD     HASH_IRQHandler           ; HASH
+                DCD     PKA_IRQHandler            ; PKA
+                DCD     LPTIM3_IRQHandler         ; LP TIM3
+                DCD     SPI3_IRQHandler           ; SPI3
+                DCD     I2C4_ER_IRQHandler        ; I2C4 error
+                DCD     I2C4_EV_IRQHandler        ; I2C4 event
+                DCD     DFSDM1_FLT0_IRQHandler    ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler    ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler    ; DFSDM1 Filter 2 global Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler    ; DFSDM1 Filter 3 global Interrupt
+                DCD     UCPD1_IRQHandler          ; UCPD1
+                DCD     ICACHE_IRQHandler         ; ICACHE
+                DCD     OTFDEC1_IRQHandler        ; OTFDEC1
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler           [WEAK]
+                EXPORT  PVD_PVM_IRQHandler        [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  RTC_S_IRQHandler          [WEAK]
+                EXPORT  TAMP_IRQHandler           [WEAK]
+                EXPORT  TAMP_S_IRQHandler         [WEAK]
+                EXPORT  FLASH_IRQHandler          [WEAK]
+                EXPORT  FLASH_S_IRQHandler        [WEAK]
+                EXPORT  GTZC_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler            [WEAK]
+                EXPORT  RCC_S_IRQHandler          [WEAK]
+                EXPORT  EXTI0_IRQHandler          [WEAK]
+                EXPORT  EXTI1_IRQHandler          [WEAK]
+                EXPORT  EXTI2_IRQHandler          [WEAK]
+                EXPORT  EXTI3_IRQHandler          [WEAK]
+                EXPORT  EXTI4_IRQHandler          [WEAK]
+                EXPORT  EXTI5_IRQHandler          [WEAK]
+                EXPORT  EXTI6_IRQHandler          [WEAK]
+                EXPORT  EXTI7_IRQHandler          [WEAK]
+                EXPORT  EXTI8_IRQHandler          [WEAK]
+                EXPORT  EXTI9_IRQHandler          [WEAK]
+                EXPORT  EXTI10_IRQHandler         [WEAK]
+                EXPORT  EXTI11_IRQHandler         [WEAK]
+                EXPORT  EXTI12_IRQHandler         [WEAK]
+                EXPORT  EXTI13_IRQHandler         [WEAK]
+                EXPORT  EXTI14_IRQHandler         [WEAK]
+                EXPORT  EXTI15_IRQHandler         [WEAK]
+                EXPORT  DMAMUX1_IRQHandler        [WEAK]
+                EXPORT  DMAMUX1_S_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel8_IRQHandler  [WEAK]
+                EXPORT  ADC1_2_IRQHandler         [WEAK]
+                EXPORT  DAC_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler     [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler     [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM1_UP_IRQHandler        [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM1_CC_IRQHandler        [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  TIM3_IRQHandler           [WEAK]
+                EXPORT  TIM4_IRQHandler           [WEAK]
+                EXPORT  TIM5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler           [WEAK]
+                EXPORT  TIM7_IRQHandler           [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM8_UP_IRQHandler        [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM8_CC_IRQHandler        [WEAK]
+                EXPORT  I2C1_EV_IRQHandler        [WEAK]
+                EXPORT  I2C1_ER_IRQHandler        [WEAK]
+                EXPORT  I2C2_EV_IRQHandler        [WEAK]
+                EXPORT  I2C2_ER_IRQHandler        [WEAK]
+                EXPORT  SPI1_IRQHandler           [WEAK]
+                EXPORT  SPI2_IRQHandler           [WEAK]
+                EXPORT  USART1_IRQHandler         [WEAK]
+                EXPORT  USART2_IRQHandler         [WEAK]
+                EXPORT  USART3_IRQHandler         [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  UART5_IRQHandler          [WEAK]
+                EXPORT  LPUART1_IRQHandler        [WEAK]
+                EXPORT  LPTIM1_IRQHandler         [WEAK]
+                EXPORT  LPTIM2_IRQHandler         [WEAK]
+                EXPORT  TIM15_IRQHandler          [WEAK]
+                EXPORT  TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM17_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler           [WEAK]
+                EXPORT  USB_FS_IRQHandler         [WEAK]
+                EXPORT  CRS_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler       [WEAK]
+                EXPORT  SDMMC1_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel8_IRQHandler  [WEAK]
+                EXPORT  I2C3_EV_IRQHandler        [WEAK]
+                EXPORT  I2C3_ER_IRQHandler        [WEAK]
+                EXPORT  SAI1_IRQHandler           [WEAK]
+                EXPORT  SAI2_IRQHandler           [WEAK]
+                EXPORT  TSC_IRQHandler            [WEAK]
+                EXPORT  AES_IRQHandler            [WEAK]
+                EXPORT  RNG_IRQHandler            [WEAK]
+                EXPORT  FPU_IRQHandler            [WEAK]
+                EXPORT  HASH_IRQHandler           [WEAK]
+                EXPORT  PKA_IRQHandler            [WEAK]
+                EXPORT  LPTIM3_IRQHandler         [WEAK]
+                EXPORT  SPI3_IRQHandler           [WEAK]
+                EXPORT  I2C4_ER_IRQHandler        [WEAK]
+                EXPORT  I2C4_EV_IRQHandler        [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler    [WEAK]
+                EXPORT  UCPD1_IRQHandler          [WEAK]
+                EXPORT  ICACHE_IRQHandler         [WEAK]
+                EXPORT  OTFDEC1_IRQHandler        [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+TAMP_S_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+DMAMUX1_IRQHandler
+DMAMUX1_S_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+DMA1_Channel8_IRQHandler
+ADC1_2_IRQHandler
+DAC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+COMP_IRQHandler
+USB_FS_IRQHandler
+CRS_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMA2_Channel8_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_IRQHandler
+PKA_IRQHandler
+LPTIM3_IRQHandler
+SPI3_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+UCPD1_IRQHandler
+ICACHE_IRQHandler
+OTFDEC1_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

board/TencentOS_Tiny_EVB_MX_Pro_L5/TOS_CONFIG/tos_config.h

@@ -0,0 +1,55 @@
+#ifndef _TOS_CONFIG_H_
+#define  _TOS_CONFIG_H_
+
+#include "stm32l5xx.h"
+
+#define TOS_CFG_TASK_PRIO_MAX           10u
+
+#define TOS_CFG_ROUND_ROBIN_EN          0u
+
+#define TOS_CFG_OBJECT_VERIFY_EN           1u
+
+#define TOS_CFG_TASK_DYNAMIC_CREATE_EN  1u
+
+#define TOS_CFG_EVENT_EN                1u
+
+#define TOS_CFG_MMBLK_EN                1u
+
+#define TOS_CFG_MMHEAP_EN               1u
+
+#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN  1u
+
+#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE        0x8000
+
+#define TOS_CFG_MUTEX_EN                1u
+
+#define TOS_CFG_MESSAGE_QUEUE_EN        1u
+
+#define TOS_CFG_MAIL_QUEUE_EN           1u
+
+#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN	1u
+
+#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN	1u
+
+#define TOS_CFG_TIMER_EN                1u
+
+#define TOS_CFG_PWR_MGR_EN              0u
+
+#define TOS_CFG_TICKLESS_EN             0u
+
+#define TOS_CFG_SEM_EN                  1u
+
+#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN      1u
+
+#define TOS_CFG_FAULT_BACKTRACE_EN      0u
+
+#define TOS_CFG_IDLE_TASK_STK_SIZE      128u
+
+#define TOS_CFG_CPU_TICK_PER_SECOND     1000u
+
+#define TOS_CFG_CPU_CLOCK               (SystemCoreClock)
+
+#define TOS_CFG_TIMER_AS_PROC           1u
+
+#endif
+

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Include/Templates/partition_stm32l552xx.h

@@ -0,0 +1,646 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32l552xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32L552xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM33 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2019 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef PARTITION_STM32L552XX_H
+#define PARTITION_STM32L552XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   1
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C03E000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C03FFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08040000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x0807FFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20018000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x2003FFFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_PVM_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TAMP_S_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> DMAMUX1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMAMUX1_S_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> DMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> DMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> DMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  DMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  DMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  DMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  DMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM8_BRK_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM8_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM8_TRG_COM_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM8_CC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.23> I2C1_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.24> I2C1_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.25> I2C2_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.26> I2C2_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.30> USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.3>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  COMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  USB_FS_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> CRS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> OCTOSPI1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.13> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.17> DMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.18> DMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.19> DMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.20> DMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> DMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> DMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> DMA2_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> I2C3_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.25> I2C3_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.26> SAI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SAI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> TSC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..108)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..108
+//   <o.0>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C4_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C4_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DFSDM1_FLT0_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.7>  DFSDM1_FLT1_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.8>  DFSDM1_FLT2_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DFSDM1_FLT3_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.10> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> ICACHE_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32L552XX_H */

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Include/Templates/partition_stm32l562xx.h

@@ -0,0 +1,648 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32l562xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32L562xx Device Initial Setup for Secure / Non-Secure Zones
+  *          for ARMCM33 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
+  *
+  *          This file contains:
+  *           - Initialize Security Attribution Unit (SAU) CTRL register
+  *           - Setup behavior of Sleep and Exception Handling
+  *           - Setup behavior of Floating Point Unit
+  *           - Setup Interrupt Target
+  *
+  ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Portions Copyright (c) 2019 STMicroelectronics, all rights reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_STM32L562XX_H
+#define PARTITION_STM32L562XX_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL          1
+
+/*
+//   <q> Enable SAU
+//   <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE   1
+
+/*
+//   <o> When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//   <i> Value for SAU->CTRL register bit ALLNS
+//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   <e>Initialize SAU Region 0
+//   <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0C03E000      /* start address of SAU region 0 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0C03FFFF      /* end address of SAU region 0 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 1
+//   <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x08040000      /* start address of SAU region 1 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x0807FFFF      /* end address of SAU region 1 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 2
+//   <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x20018000      /* start address of SAU region 2 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x2003FFFF      /* end address of SAU region 2 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 3
+//   <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x4FFFFFFF      /* end address of SAU region 3 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 4
+//   <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     0x60000000      /* start address of SAU region 4 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x9FFFFFFF      /* end address of SAU region 4 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 5
+//   <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5    1
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x0BF90000      /* start address of SAU region 5 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x0BFA8FFF      /* end address of SAU region 5 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 6
+//   <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize SAU Region 7
+//   <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7    0
+
+/*
+//     <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */
+
+/*
+//     <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */
+
+/*
+//     <o>Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  0
+
+/*
+//   <o> Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//   <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   <o>System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   <o>Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x04-0x07
+//   <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/*
+//   <o>BusFault, HardFault, and NMI target
+//     <0=> Secure state
+//     <1=> Non-Secure state
+//   <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point Unit
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point Unit usage
+//     <0=> Secure state only
+//     <3=> Secure and Non-Secure state
+//   <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL       3
+
+/*
+// <o>Treat floating-point registers as Secure
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL            0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//   <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL     0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+//     <0=> Disabled
+//     <1=> Enabled
+//   <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL      1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+//   <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0    1
+
+/*
+// Interrupts 0..31
+//   <o.0>  WWDG_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PVD_PVM_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.2>  RTC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.3>  RTC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.4>  TAMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TAMP_S_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.6>  FLASH_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FLASH_S_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.8>  GTZC_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  RCC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.10> RCC_S_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> EXTI0_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.12> EXTI1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.13> EXTI2_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.14> EXTI3_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.15> EXTI4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.16> EXTI5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.17> EXTI6_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.18> EXTI7_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.19> EXTI8_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.20> EXTI9_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.21> EXTI10_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.22> EXTI11_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.23> EXTI12_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.24> EXTI13_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.25> EXTI14_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.26> EXTI15_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.27> DMAMUX1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.28> DMAMUX1_S_IRQn      <0=> Secure state <1=> Non-Secure state
+//   <o.29> DMA1_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.30> DMA1_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.31> DMA1_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1    1
+
+/*
+// Interrupts 32..63
+//   <o.0>  DMA1_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.1>  DMA1_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.2>  DMA1_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.3>  DMA1_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.4>  DMA1_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.5>  ADC1_2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DAC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.7>  FDCAN1_IT0_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.8>  FDCAN1_IT1_IRQn     <0=> Secure state <1=> Non-Secure state
+//   <o.9>  TIM1_BRK_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.10> TIM1_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.11> TIM1_TRG_COM_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.12> TIM1_CC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.13> TIM2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.14> TIM3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.15> TIM4_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.16> TIM5_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.17> TIM6_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.18> TIM7_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.19> TIM8_BRK_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.20> TIM8_UP_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.21> TIM8_TRG_COM_IRQn   <0=> Secure state <1=> Non-Secure state
+//   <o.22> TIM8_CC_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.23> I2C1_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.24> I2C1_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.25> I2C2_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.26> I2C2_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.27> SPI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> SPI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.29> USART1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.30> USART2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.31> USART3_IRQn         <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2    1
+
+/*
+// Interrupts 64..95
+//   <o.0>  UART4_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.1>  UART5_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPUART1_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.3>  LPTIM1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.4>  LPTIM2_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.5>  TIM15_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.6>  TIM16_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.7>  TIM17_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.8>  COMP_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.9>  USB_FS_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.10> CRS_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.11> FMC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.12> OCTOSPI1_IRQn       <0=> Secure state <1=> Non-Secure state
+//   <o.13> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.14> SDMMC1_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.15> Reserved            <0=> Secure state <1=> Non-Secure state
+//   <o.16> DMA2_Channel1_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.17> DMA2_Channel2_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.18> DMA2_Channel3_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.19> DMA2_Channel4_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.20> DMA2_Channel5_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.21> DMA2_Channel6_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.22> DMA2_Channel7_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.23> DMA2_Channel8_IRQn  <0=> Secure state <1=> Non-Secure state
+//   <o.24> I2C3_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.25> I2C3_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.26> SAI1_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.27> SAI2_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.28> TSC_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.29> AES_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.30> RNG_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.31> FPU_IRQn            <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+//   <e>Initialize ITNS 3 (Interrupts 96..108)
+*/
+#define NVIC_INIT_ITNS3    1
+
+/*
+// Interrupts 96..108
+//   <o.0>  HASH_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.1>  PKA_IRQn            <0=> Secure state <1=> Non-Secure state
+//   <o.2>  LPTIM3_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.3>  SPI3_IRQn           <0=> Secure state <1=> Non-Secure state
+//   <o.4>  I2C4_EV_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.5>  I2C4_ER_IRQn        <0=> Secure state <1=> Non-Secure state
+//   <o.6>  DFSDM1_FLT0_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.7>  DFSDM1_FLT1_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.8>  DFSDM1_FLT2_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.9>  DFSDM1_FLT3_IRQn    <0=> Secure state <1=> Non-Secure state
+//   <o.10> UCPD1_IRQn          <0=> Secure state <1=> Non-Secure state
+//   <o.11> ICACHE_IRQn         <0=> Secure state <1=> Non-Secure state
+//   <o.12> OTFDEC1_IRQn        <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL      0x00000000
+
+/*
+//   </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+    max 8 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+  #endif
+
+  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+  #endif
+
+  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+  #endif
+
+  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+  #endif
+
+  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+  #endif
+
+  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+  #endif
+
+  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+  #endif
+
+  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+  #endif
+
+  /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+  #endif
+
+  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |
+                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |
+                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)        )                     |
+                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |
+                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |
+                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
+  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
+      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+
+    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |
+                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+  #endif
+
+  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+  #endif
+
+  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+  #endif
+
+}
+
+#endif  /* PARTITION_STM32L562XX_H */

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Include/partition_stm32l5xx.h

@@ -0,0 +1,71 @@
+/**
+  ******************************************************************************
+  * @file    partition_stm32l5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32L5xx Device Header File for Initial Setup for
+  *          Secure / Non-Secure Zones based on CMSIS CORE V5.3.1
+  *
+  *          The file is included in system_stm32l5xx_s.c in secure application.
+  *          It includes the configuration section that allows to select the
+  *          STM32L5xx device partitioning file for system core secure attributes
+  *          and interrupt secure and non-secure assignment.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l5xx
+  * @{
+  */
+
+#ifndef PARTITION_STM32L5XX_H
+#define PARTITION_STM32L5XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Secure_configuration_section
+  * @{
+  */
+
+#if defined(STM32L552xx)
+  #include "partition_stm32l552xx.h"
+#elif defined(STM32L562xx)
+  #include "partition_stm32l562xx.h"
+#else
+  #error "Please select first the target STM32L5xx device used in your application (in stm32l5xx.h file)"
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* PARTITION_STM32L5XX_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h

@@ -0,0 +1,180 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32L5xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L5xx device used in the target application
+  *              - To use or not the peripheral<61>s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral<61>s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l5xx
+  * @{
+  */
+
+#ifndef STM32L5xx_H
+#define STM32L5xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L5)
+#define STM32L5
+#endif /* STM32L5 */
+
+/* Uncomment the line below according to the target STM32L5 device used in your
+   application
+  */
+
+#if !defined (STM32L552xx) && !defined (STM32L562xx)
+  /* #define STM32L552xx */   /*!< STM32L552xx Devices */
+  /* #define STM32L562xx */   /*!< STM32L562xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32L5_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32L5_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
+#define __STM32L5_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32L5_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32L5_CMSIS_VERSION        ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
+                                       |(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\
+                                       |(__STM32L5_CMSIS_VERSION_SUB2 << 8U )\
+                                       |(__STM32L5_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L552xx)
+  #include "stm32l552xx.h"
+#elif defined(STM32L562xx)
+  #include "stm32l562xx.h"
+#else
+ #error "Please select first the target STM32L5xx device used in your application (in stm32l5xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l5xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32L5xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Include/system_stm32l5xx.h

@@ -0,0 +1,110 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l5xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device System Source File for STM32L5xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_system
+  * @{
+  */
+
+#ifndef SYSTEM_STM32L5XX_H
+#define SYSTEM_STM32L5XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32L5xx_System_Includes
+  * @{
+  */
+#include <stdint.h>
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[16];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Exported_Functions
+  * @{
+  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable from secure application and return its value
+          when security is implemented in the system (Non-secure callable function).
+
+   Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
+ */
+extern uint32_t SECURE_SystemCoreClockUpdate(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_STM32L5XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/arm/startup_stm32l552xx.s

@@ -0,0 +1,508 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l552xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L552xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     SecureFault_Handler       ; Secure Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler        ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     RTC_IRQHandler            ; RTC non-secure interrupts through the EXTI line
+                DCD     RTC_S_IRQHandler          ; RTC secure interrupts through the EXTI line
+                DCD     TAMP_IRQHandler           ; Tamper non-secure interrupts through the EXTI line
+                DCD     TAMP_S_IRQHandler         ; Tamper secure interrupts through the EXTI line
+                DCD     FLASH_IRQHandler          ; FLASH non-secure interrupts
+                DCD     FLASH_S_IRQHandler        ; FLASH secure global interrupts
+                DCD     GTZC_IRQHandler           ; GTZC global interrupts
+                DCD     RCC_IRQHandler            ; RCC non-secure global interrupts
+                DCD     RCC_S_IRQHandler          ; RCC secure global interrupts
+                DCD     EXTI0_IRQHandler          ; EXTI Line0
+                DCD     EXTI1_IRQHandler          ; EXTI Line1
+                DCD     EXTI2_IRQHandler          ; EXTI Line2
+                DCD     EXTI3_IRQHandler          ; EXTI Line3
+                DCD     EXTI4_IRQHandler          ; EXTI Line4
+                DCD     EXTI5_IRQHandler          ; EXTI Line5
+                DCD     EXTI6_IRQHandler          ; EXTI Line6
+                DCD     EXTI7_IRQHandler          ; EXTI Line7
+                DCD     EXTI8_IRQHandler          ; EXTI Line8
+                DCD     EXTI9_IRQHandler          ; EXTI Line9
+                DCD     EXTI10_IRQHandler         ; EXTI Line10
+                DCD     EXTI11_IRQHandler         ; EXTI Line11
+                DCD     EXTI12_IRQHandler         ; EXTI Line12
+                DCD     EXTI13_IRQHandler         ; EXTI Line13
+                DCD     EXTI14_IRQHandler         ; EXTI Line14
+                DCD     EXTI15_IRQHandler         ; EXTI Line15
+                DCD     DMAMUX1_IRQHandler        ; DMAMUX1 non-secure
+                DCD     DMAMUX1_S_IRQHandler      ; DMAMUX1 secure
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     DMA1_Channel8_IRQHandler  ; DMA1 Channel 8
+                DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+                DCD     DAC_IRQHandler            ; DAC1&2 underrun errors
+                DCD     FDCAN1_IT0_IRQHandler     ; FDCAN1 Interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler     ; FDCAN1 Interrupt 1
+                DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     TIM5_IRQHandler           ; TIM5
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+                DCD     TIM8_BRK_IRQHandler       ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler        ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler   ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler        ; TIM8 Capture Compare
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     UART4_IRQHandler          ; UART4
+                DCD     UART5_IRQHandler          ; UART5
+                DCD     LPUART1_IRQHandler        ; LP UART1
+                DCD     LPTIM1_IRQHandler         ; LP TIM1
+                DCD     LPTIM2_IRQHandler         ; LP TIM2
+                DCD     TIM15_IRQHandler          ; TIM15
+                DCD     TIM16_IRQHandler          ; TIM16
+                DCD     TIM17_IRQHandler          ; TIM17
+                DCD     COMP_IRQHandler           ; COMP1&2
+                DCD     USB_FS_IRQHandler         ; USB FS
+                DCD     CRS_IRQHandler            ; CRS
+                DCD     FMC_IRQHandler            ; FMC
+                DCD     OCTOSPI1_IRQHandler       ; OctoSPI1 global interrupt
+                DCD     0                         ; Reserved
+                DCD     SDMMC1_IRQHandler         ; SDMMC1
+                DCD     0                         ; Reserved
+                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+                DCD     DMA2_Channel6_IRQHandler  ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler  ; DMA2 Channel 7
+                DCD     DMA2_Channel8_IRQHandler  ; DMA2 Channel 8
+                DCD     I2C3_EV_IRQHandler        ; I2C3 event
+                DCD     I2C3_ER_IRQHandler        ; I2C3 error
+                DCD     SAI1_IRQHandler           ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler           ; Serial Audio Interface 2 global interrupt
+                DCD     TSC_IRQHandler            ; Touch Sense Controller global interrupt
+                DCD     0                         ; Reserved
+                DCD     RNG_IRQHandler            ; RNG global interrupt
+                DCD     FPU_IRQHandler            ; FPU
+                DCD     HASH_IRQHandler           ; HASH
+                DCD     0                         ; Reserved
+                DCD     LPTIM3_IRQHandler         ; LP TIM3
+                DCD     SPI3_IRQHandler           ; SPI3
+                DCD     I2C4_ER_IRQHandler        ; I2C4 error
+                DCD     I2C4_EV_IRQHandler        ; I2C4 event
+                DCD     DFSDM1_FLT0_IRQHandler    ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler    ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler    ; DFSDM1 Filter 2 global Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler    ; DFSDM1 Filter 3 global Interrupt
+                DCD     UCPD1_IRQHandler          ; UCPD1
+                DCD     ICACHE_IRQHandler         ; ICACHE
+                DCD     0                         ; Reserved
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler           [WEAK]
+                EXPORT  PVD_PVM_IRQHandler        [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  RTC_S_IRQHandler          [WEAK]
+                EXPORT  TAMP_IRQHandler           [WEAK]
+                EXPORT  TAMP_S_IRQHandler         [WEAK]
+                EXPORT  FLASH_IRQHandler          [WEAK]
+                EXPORT  FLASH_S_IRQHandler        [WEAK]
+                EXPORT  GTZC_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler            [WEAK]
+                EXPORT  RCC_S_IRQHandler          [WEAK]
+                EXPORT  EXTI0_IRQHandler          [WEAK]
+                EXPORT  EXTI1_IRQHandler          [WEAK]
+                EXPORT  EXTI2_IRQHandler          [WEAK]
+                EXPORT  EXTI3_IRQHandler          [WEAK]
+                EXPORT  EXTI4_IRQHandler          [WEAK]
+                EXPORT  EXTI5_IRQHandler          [WEAK]
+                EXPORT  EXTI6_IRQHandler          [WEAK]
+                EXPORT  EXTI7_IRQHandler          [WEAK]
+                EXPORT  EXTI8_IRQHandler          [WEAK]
+                EXPORT  EXTI9_IRQHandler          [WEAK]
+                EXPORT  EXTI10_IRQHandler         [WEAK]
+                EXPORT  EXTI11_IRQHandler         [WEAK]
+                EXPORT  EXTI12_IRQHandler         [WEAK]
+                EXPORT  EXTI13_IRQHandler         [WEAK]
+                EXPORT  EXTI14_IRQHandler         [WEAK]
+                EXPORT  EXTI15_IRQHandler         [WEAK]
+                EXPORT  DMAMUX1_IRQHandler        [WEAK]
+                EXPORT  DMAMUX1_S_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel8_IRQHandler  [WEAK]
+                EXPORT  ADC1_2_IRQHandler         [WEAK]
+                EXPORT  DAC_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler     [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler     [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM1_UP_IRQHandler        [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM1_CC_IRQHandler        [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  TIM3_IRQHandler           [WEAK]
+                EXPORT  TIM4_IRQHandler           [WEAK]
+                EXPORT  TIM5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler           [WEAK]
+                EXPORT  TIM7_IRQHandler           [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM8_UP_IRQHandler        [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM8_CC_IRQHandler        [WEAK]
+                EXPORT  I2C1_EV_IRQHandler        [WEAK]
+                EXPORT  I2C1_ER_IRQHandler        [WEAK]
+                EXPORT  I2C2_EV_IRQHandler        [WEAK]
+                EXPORT  I2C2_ER_IRQHandler        [WEAK]
+                EXPORT  SPI1_IRQHandler           [WEAK]
+                EXPORT  SPI2_IRQHandler           [WEAK]
+                EXPORT  USART1_IRQHandler         [WEAK]
+                EXPORT  USART2_IRQHandler         [WEAK]
+                EXPORT  USART3_IRQHandler         [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  UART5_IRQHandler          [WEAK]
+                EXPORT  LPUART1_IRQHandler        [WEAK]
+                EXPORT  LPTIM1_IRQHandler         [WEAK]
+                EXPORT  LPTIM2_IRQHandler         [WEAK]
+                EXPORT  TIM15_IRQHandler          [WEAK]
+                EXPORT  TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM17_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler           [WEAK]
+                EXPORT  USB_FS_IRQHandler         [WEAK]
+                EXPORT  CRS_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler       [WEAK]
+                EXPORT  SDMMC1_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel8_IRQHandler  [WEAK]
+                EXPORT  I2C3_EV_IRQHandler        [WEAK]
+                EXPORT  I2C3_ER_IRQHandler        [WEAK]
+                EXPORT  SAI1_IRQHandler           [WEAK]
+                EXPORT  SAI2_IRQHandler           [WEAK]
+                EXPORT  TSC_IRQHandler            [WEAK]
+                EXPORT  RNG_IRQHandler            [WEAK]
+                EXPORT  FPU_IRQHandler            [WEAK]
+                EXPORT  HASH_IRQHandler           [WEAK]
+                EXPORT  LPTIM3_IRQHandler         [WEAK]
+                EXPORT  SPI3_IRQHandler           [WEAK]
+                EXPORT  I2C4_ER_IRQHandler        [WEAK]
+                EXPORT  I2C4_EV_IRQHandler        [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler    [WEAK]
+                EXPORT  UCPD1_IRQHandler          [WEAK]
+                EXPORT  ICACHE_IRQHandler         [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+TAMP_S_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+DMAMUX1_IRQHandler
+DMAMUX1_S_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+DMA1_Channel8_IRQHandler
+ADC1_2_IRQHandler
+DAC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+COMP_IRQHandler
+USB_FS_IRQHandler
+CRS_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMA2_Channel8_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+TSC_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_IRQHandler
+LPTIM3_IRQHandler
+SPI3_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+UCPD1_IRQHandler
+ICACHE_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/arm/startup_stm32l562xx.s

@@ -0,0 +1,514 @@
+;*******************************************************************************
+;* File Name          : startup_stm32l562xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L562xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;* <<< Use Configuration Wizard in Context Menu >>>
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     SecureFault_Handler       ; Secure Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler        ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     RTC_IRQHandler            ; RTC non-secure interrupts through the EXTI line
+                DCD     RTC_S_IRQHandler          ; RTC secure interrupts through the EXTI line
+                DCD     TAMP_IRQHandler           ; Tamper non-secure interrupts through the EXTI line
+                DCD     TAMP_S_IRQHandler         ; Tamper secure interrupts through the EXTI line
+                DCD     FLASH_IRQHandler          ; FLASH non-secure interrupts
+                DCD     FLASH_S_IRQHandler        ; FLASH secure global interrupts
+                DCD     GTZC_IRQHandler           ; GTZC global interrupts
+                DCD     RCC_IRQHandler            ; RCC non-secure global interrupts
+                DCD     RCC_S_IRQHandler          ; RCC secure global interrupts
+                DCD     EXTI0_IRQHandler          ; EXTI Line0
+                DCD     EXTI1_IRQHandler          ; EXTI Line1
+                DCD     EXTI2_IRQHandler          ; EXTI Line2
+                DCD     EXTI3_IRQHandler          ; EXTI Line3
+                DCD     EXTI4_IRQHandler          ; EXTI Line4
+                DCD     EXTI5_IRQHandler          ; EXTI Line5
+                DCD     EXTI6_IRQHandler          ; EXTI Line6
+                DCD     EXTI7_IRQHandler          ; EXTI Line7
+                DCD     EXTI8_IRQHandler          ; EXTI Line8
+                DCD     EXTI9_IRQHandler          ; EXTI Line9
+                DCD     EXTI10_IRQHandler         ; EXTI Line10
+                DCD     EXTI11_IRQHandler         ; EXTI Line11
+                DCD     EXTI12_IRQHandler         ; EXTI Line12
+                DCD     EXTI13_IRQHandler         ; EXTI Line13
+                DCD     EXTI14_IRQHandler         ; EXTI Line14
+                DCD     EXTI15_IRQHandler         ; EXTI Line15
+                DCD     DMAMUX1_IRQHandler        ; DMAMUX1 non-secure
+                DCD     DMAMUX1_S_IRQHandler      ; DMAMUX1 secure
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     DMA1_Channel8_IRQHandler  ; DMA1 Channel 8
+                DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+                DCD     DAC_IRQHandler            ; DAC1&2 underrun errors
+                DCD     FDCAN1_IT0_IRQHandler     ; FDCAN1 Interrupt 0
+                DCD     FDCAN1_IT1_IRQHandler     ; FDCAN1 Interrupt 1
+                DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     TIM5_IRQHandler           ; TIM5
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+                DCD     TIM8_BRK_IRQHandler       ; TIM8 Break
+                DCD     TIM8_UP_IRQHandler        ; TIM8 Update
+                DCD     TIM8_TRG_COM_IRQHandler   ; TIM8 Trigger and Commutation
+                DCD     TIM8_CC_IRQHandler        ; TIM8 Capture Compare
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     UART4_IRQHandler          ; UART4
+                DCD     UART5_IRQHandler          ; UART5
+                DCD     LPUART1_IRQHandler        ; LP UART1
+                DCD     LPTIM1_IRQHandler         ; LP TIM1
+                DCD     LPTIM2_IRQHandler         ; LP TIM2
+                DCD     TIM15_IRQHandler          ; TIM15
+                DCD     TIM16_IRQHandler          ; TIM16
+                DCD     TIM17_IRQHandler          ; TIM17
+                DCD     COMP_IRQHandler           ; COMP1&2
+                DCD     USB_FS_IRQHandler         ; USB FS
+                DCD     CRS_IRQHandler            ; CRS
+                DCD     FMC_IRQHandler            ; FMC
+                DCD     OCTOSPI1_IRQHandler       ; OctoSPI1 global interrupt
+                DCD     0                         ; Reserved
+                DCD     SDMMC1_IRQHandler         ; SDMMC1
+                DCD     0                         ; Reserved
+                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
+                DCD     DMA2_Channel6_IRQHandler  ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler  ; DMA2 Channel 7
+                DCD     DMA2_Channel8_IRQHandler  ; DMA2 Channel 8
+                DCD     I2C3_EV_IRQHandler        ; I2C3 event
+                DCD     I2C3_ER_IRQHandler        ; I2C3 error
+                DCD     SAI1_IRQHandler           ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler           ; Serial Audio Interface 2 global interrupt
+                DCD     TSC_IRQHandler            ; Touch Sense Controller global interrupt
+                DCD     AES_IRQHandler            ; AES global interrupt
+                DCD     RNG_IRQHandler            ; RNG global interrupt
+                DCD     FPU_IRQHandler            ; FPU
+                DCD     HASH_IRQHandler           ; HASH
+                DCD     PKA_IRQHandler            ; PKA
+                DCD     LPTIM3_IRQHandler         ; LP TIM3
+                DCD     SPI3_IRQHandler           ; SPI3
+                DCD     I2C4_ER_IRQHandler        ; I2C4 error
+                DCD     I2C4_EV_IRQHandler        ; I2C4 event
+                DCD     DFSDM1_FLT0_IRQHandler    ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler    ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler    ; DFSDM1 Filter 2 global Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler    ; DFSDM1 Filter 3 global Interrupt
+                DCD     UCPD1_IRQHandler          ; UCPD1
+                DCD     ICACHE_IRQHandler         ; ICACHE
+                DCD     OTFDEC1_IRQHandler        ; OTFDEC1
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler\
+                PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SecureFault_Handler\
+                PROC
+                EXPORT  SecureFault_Handler       [WEAK]
+                B       .
+                ENDP
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler           [WEAK]
+                EXPORT  PVD_PVM_IRQHandler        [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  RTC_S_IRQHandler          [WEAK]
+                EXPORT  TAMP_IRQHandler           [WEAK]
+                EXPORT  TAMP_S_IRQHandler         [WEAK]
+                EXPORT  FLASH_IRQHandler          [WEAK]
+                EXPORT  FLASH_S_IRQHandler        [WEAK]
+                EXPORT  GTZC_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler            [WEAK]
+                EXPORT  RCC_S_IRQHandler          [WEAK]
+                EXPORT  EXTI0_IRQHandler          [WEAK]
+                EXPORT  EXTI1_IRQHandler          [WEAK]
+                EXPORT  EXTI2_IRQHandler          [WEAK]
+                EXPORT  EXTI3_IRQHandler          [WEAK]
+                EXPORT  EXTI4_IRQHandler          [WEAK]
+                EXPORT  EXTI5_IRQHandler          [WEAK]
+                EXPORT  EXTI6_IRQHandler          [WEAK]
+                EXPORT  EXTI7_IRQHandler          [WEAK]
+                EXPORT  EXTI8_IRQHandler          [WEAK]
+                EXPORT  EXTI9_IRQHandler          [WEAK]
+                EXPORT  EXTI10_IRQHandler         [WEAK]
+                EXPORT  EXTI11_IRQHandler         [WEAK]
+                EXPORT  EXTI12_IRQHandler         [WEAK]
+                EXPORT  EXTI13_IRQHandler         [WEAK]
+                EXPORT  EXTI14_IRQHandler         [WEAK]
+                EXPORT  EXTI15_IRQHandler         [WEAK]
+                EXPORT  DMAMUX1_IRQHandler        [WEAK]
+                EXPORT  DMAMUX1_S_IRQHandler      [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler  [WEAK]
+                EXPORT  DMA1_Channel8_IRQHandler  [WEAK]
+                EXPORT  ADC1_2_IRQHandler         [WEAK]
+                EXPORT  DAC_IRQHandler            [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler     [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler     [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM1_UP_IRQHandler        [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM1_CC_IRQHandler        [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  TIM3_IRQHandler           [WEAK]
+                EXPORT  TIM4_IRQHandler           [WEAK]
+                EXPORT  TIM5_IRQHandler           [WEAK]
+                EXPORT  TIM6_IRQHandler           [WEAK]
+                EXPORT  TIM7_IRQHandler           [WEAK]
+                EXPORT  TIM8_BRK_IRQHandler       [WEAK]
+                EXPORT  TIM8_UP_IRQHandler        [WEAK]
+                EXPORT  TIM8_TRG_COM_IRQHandler   [WEAK]
+                EXPORT  TIM8_CC_IRQHandler        [WEAK]
+                EXPORT  I2C1_EV_IRQHandler        [WEAK]
+                EXPORT  I2C1_ER_IRQHandler        [WEAK]
+                EXPORT  I2C2_EV_IRQHandler        [WEAK]
+                EXPORT  I2C2_ER_IRQHandler        [WEAK]
+                EXPORT  SPI1_IRQHandler           [WEAK]
+                EXPORT  SPI2_IRQHandler           [WEAK]
+                EXPORT  USART1_IRQHandler         [WEAK]
+                EXPORT  USART2_IRQHandler         [WEAK]
+                EXPORT  USART3_IRQHandler         [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  UART5_IRQHandler          [WEAK]
+                EXPORT  LPUART1_IRQHandler        [WEAK]
+                EXPORT  LPTIM1_IRQHandler         [WEAK]
+                EXPORT  LPTIM2_IRQHandler         [WEAK]
+                EXPORT  TIM15_IRQHandler          [WEAK]
+                EXPORT  TIM16_IRQHandler          [WEAK]
+                EXPORT  TIM17_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler           [WEAK]
+                EXPORT  USB_FS_IRQHandler         [WEAK]
+                EXPORT  CRS_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler       [WEAK]
+                EXPORT  SDMMC1_IRQHandler         [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler  [WEAK]
+                EXPORT  DMA2_Channel8_IRQHandler  [WEAK]
+                EXPORT  I2C3_EV_IRQHandler        [WEAK]
+                EXPORT  I2C3_ER_IRQHandler        [WEAK]
+                EXPORT  SAI1_IRQHandler           [WEAK]
+                EXPORT  SAI2_IRQHandler           [WEAK]
+                EXPORT  TSC_IRQHandler            [WEAK]
+                EXPORT  AES_IRQHandler            [WEAK]
+                EXPORT  RNG_IRQHandler            [WEAK]
+                EXPORT  FPU_IRQHandler            [WEAK]
+                EXPORT  HASH_IRQHandler           [WEAK]
+                EXPORT  PKA_IRQHandler            [WEAK]
+                EXPORT  LPTIM3_IRQHandler         [WEAK]
+                EXPORT  SPI3_IRQHandler           [WEAK]
+                EXPORT  I2C4_ER_IRQHandler        [WEAK]
+                EXPORT  I2C4_EV_IRQHandler        [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler    [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler    [WEAK]
+                EXPORT  UCPD1_IRQHandler          [WEAK]
+                EXPORT  ICACHE_IRQHandler         [WEAK]
+                EXPORT  OTFDEC1_IRQHandler        [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_IRQHandler
+RTC_S_IRQHandler
+TAMP_IRQHandler
+TAMP_S_IRQHandler
+FLASH_IRQHandler
+FLASH_S_IRQHandler
+GTZC_IRQHandler
+RCC_IRQHandler
+RCC_S_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+EXTI5_IRQHandler
+EXTI6_IRQHandler
+EXTI7_IRQHandler
+EXTI8_IRQHandler
+EXTI9_IRQHandler
+EXTI10_IRQHandler
+EXTI11_IRQHandler
+EXTI12_IRQHandler
+EXTI13_IRQHandler
+EXTI14_IRQHandler
+EXTI15_IRQHandler
+DMAMUX1_IRQHandler
+DMAMUX1_S_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+DMA1_Channel8_IRQHandler
+ADC1_2_IRQHandler
+DAC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+TIM5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+COMP_IRQHandler
+USB_FS_IRQHandler
+CRS_IRQHandler
+FMC_IRQHandler
+OCTOSPI1_IRQHandler
+SDMMC1_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMA2_Channel8_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+TSC_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+HASH_IRQHandler
+PKA_IRQHandler
+LPTIM3_IRQHandler
+SPI3_IRQHandler
+I2C4_ER_IRQHandler
+I2C4_EV_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+UCPD1_IRQHandler
+ICACHE_IRQHandler
+OTFDEC1_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l552xx.s

@@ -0,0 +1,609 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l552xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L552xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	TAMP_S_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	DMAMUX1_IRQHandler
+	.word	DMAMUX1_S_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	DMA1_Channel8_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	DAC_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	TIM16_IRQHandler
+	.word	TIM17_IRQHandler
+	.word	COMP_IRQHandler
+	.word	USB_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	0
+	.word	SDMMC1_IRQHandler
+	.word	0
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	DMA2_Channel8_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	TSC_IRQHandler
+	.word	0
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+	.word	HASH_IRQHandler
+	.word	0
+	.word	LPTIM3_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	I2C4_ER_IRQHandler
+	.word	I2C4_EV_IRQHandler
+	.word	DFSDM1_FLT0_IRQHandler
+	.word	DFSDM1_FLT1_IRQHandler
+	.word	DFSDM1_FLT2_IRQHandler
+	.word	DFSDM1_FLT3_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	0
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	TAMP_S_IRQHandler
+	.thumb_set TAMP_S_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	DMAMUX1_IRQHandler
+	.thumb_set DMAMUX1_IRQHandler,Default_Handler
+
+	.weak	DMAMUX1_S_IRQHandler
+	.thumb_set DMAMUX1_S_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel8_IRQHandler
+	.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	DAC_IRQHandler
+	.thumb_set DAC_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+
+	.weak	USB_FS_IRQHandler
+	.thumb_set USB_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel8_IRQHandler
+	.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	I2C4_ER_IRQHandler
+	.thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+	.weak	I2C4_EV_IRQHandler
+	.thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT0_IRQHandler
+	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT1_IRQHandler
+	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT2_IRQHandler
+	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT3_IRQHandler
+	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/startup_stm32l562xx.s

@@ -0,0 +1,618 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l562xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L562xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M33 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m33
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+	bl	main
+
+LoopForever:
+    b LoopForever
+
+.size	Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	SecureFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	RTC_IRQHandler
+	.word	RTC_S_IRQHandler
+	.word	TAMP_IRQHandler
+	.word	TAMP_S_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	FLASH_S_IRQHandler
+	.word	GTZC_IRQHandler
+	.word	RCC_IRQHandler
+	.word	RCC_S_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	EXTI5_IRQHandler
+	.word	EXTI6_IRQHandler
+	.word	EXTI7_IRQHandler
+	.word	EXTI8_IRQHandler
+	.word	EXTI9_IRQHandler
+	.word	EXTI10_IRQHandler
+	.word	EXTI11_IRQHandler
+	.word	EXTI12_IRQHandler
+	.word	EXTI13_IRQHandler
+	.word	EXTI14_IRQHandler
+	.word	EXTI15_IRQHandler
+	.word	DMAMUX1_IRQHandler
+	.word	DMAMUX1_S_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	DMA1_Channel8_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	DAC_IRQHandler
+	.word	FDCAN1_IT0_IRQHandler
+	.word	FDCAN1_IT1_IRQHandler
+	.word	TIM1_BRK_IRQHandler
+	.word	TIM1_UP_IRQHandler
+	.word	TIM1_TRG_COM_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	TIM6_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	TIM15_IRQHandler
+	.word	TIM16_IRQHandler
+	.word	TIM17_IRQHandler
+	.word	COMP_IRQHandler
+	.word	USB_FS_IRQHandler
+	.word	CRS_IRQHandler
+	.word	FMC_IRQHandler
+	.word	OCTOSPI1_IRQHandler
+	.word	0
+	.word	SDMMC1_IRQHandler
+	.word	0
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	DMA2_Channel8_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	TSC_IRQHandler
+	.word	AES_IRQHandler
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+	.word	HASH_IRQHandler
+	.word	PKA_IRQHandler
+	.word	LPTIM3_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	I2C4_ER_IRQHandler
+	.word	I2C4_EV_IRQHandler
+	.word	DFSDM1_FLT0_IRQHandler
+	.word	DFSDM1_FLT1_IRQHandler
+	.word	DFSDM1_FLT2_IRQHandler
+	.word	DFSDM1_FLT3_IRQHandler
+	.word	UCPD1_IRQHandler
+	.word	ICACHE_IRQHandler
+	.word	OTFDEC1_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SecureFault_Handler
+	.thumb_set SecureFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	RTC_IRQHandler
+	.thumb_set RTC_IRQHandler,Default_Handler
+
+	.weak	RTC_S_IRQHandler
+	.thumb_set RTC_S_IRQHandler,Default_Handler
+
+	.weak	TAMP_IRQHandler
+	.thumb_set TAMP_IRQHandler,Default_Handler
+
+	.weak	TAMP_S_IRQHandler
+	.thumb_set TAMP_S_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	FLASH_S_IRQHandler
+	.thumb_set FLASH_S_IRQHandler,Default_Handler
+
+	.weak	GTZC_IRQHandler
+	.thumb_set GTZC_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	RCC_S_IRQHandler
+	.thumb_set RCC_S_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	EXTI5_IRQHandler
+	.thumb_set EXTI5_IRQHandler,Default_Handler
+
+	.weak	EXTI6_IRQHandler
+	.thumb_set EXTI6_IRQHandler,Default_Handler
+
+	.weak	EXTI7_IRQHandler
+	.thumb_set EXTI7_IRQHandler,Default_Handler
+
+	.weak	EXTI8_IRQHandler
+	.thumb_set EXTI8_IRQHandler,Default_Handler
+
+	.weak	EXTI9_IRQHandler
+	.thumb_set EXTI9_IRQHandler,Default_Handler
+
+	.weak	EXTI10_IRQHandler
+	.thumb_set EXTI10_IRQHandler,Default_Handler
+
+	.weak	EXTI11_IRQHandler
+	.thumb_set EXTI11_IRQHandler,Default_Handler
+
+	.weak	EXTI12_IRQHandler
+	.thumb_set EXTI12_IRQHandler,Default_Handler
+
+	.weak	EXTI13_IRQHandler
+	.thumb_set EXTI13_IRQHandler,Default_Handler
+
+	.weak	EXTI14_IRQHandler
+	.thumb_set EXTI14_IRQHandler,Default_Handler
+
+	.weak	EXTI15_IRQHandler
+	.thumb_set EXTI15_IRQHandler,Default_Handler
+
+	.weak	DMAMUX1_IRQHandler
+	.thumb_set DMAMUX1_IRQHandler,Default_Handler
+
+	.weak	DMAMUX1_S_IRQHandler
+	.thumb_set DMAMUX1_S_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel8_IRQHandler
+	.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	DAC_IRQHandler
+	.thumb_set DAC_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT0_IRQHandler
+	.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+	.weak	FDCAN1_IT1_IRQHandler
+	.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	TIM6_IRQHandler
+	.thumb_set TIM6_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	TIM15_IRQHandler
+	.thumb_set TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+
+	.weak	USB_FS_IRQHandler
+	.thumb_set USB_FS_IRQHandler,Default_Handler
+
+	.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	OCTOSPI1_IRQHandler
+	.thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel8_IRQHandler
+	.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+
+	.weak	AES_IRQHandler
+	.thumb_set AES_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+	.weak	HASH_IRQHandler
+	.thumb_set HASH_IRQHandler,Default_Handler
+
+	.weak	PKA_IRQHandler
+	.thumb_set PKA_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	I2C4_ER_IRQHandler
+	.thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+	.weak	I2C4_EV_IRQHandler
+	.thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT0_IRQHandler
+	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT1_IRQHandler
+	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT2_IRQHandler
+	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT3_IRQHandler
+	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+	.weak	UCPD1_IRQHandler
+	.thumb_set UCPD1_IRQHandler,Default_Handler
+
+	.weak	ICACHE_IRQHandler
+	.thumb_set ICACHE_IRQHandler,Default_Handler
+
+	.weak	OTFDEC1_IRQHandler
+	.thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_SRAM1_start__  = 0x20000000;
+define symbol __region_SRAM1_end__    = 0x2002FFFF;
+define symbol __region_SRAM2_start__  = 0x20030000;
+define symbol __region_SRAM2_end__    = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in SRAM1_region { };
+place in SRAM2_region { };
+                        

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash_ns.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08020000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08020000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20018000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_SRAM1_start__  = 0x20018000;
+define symbol __region_SRAM1_end__    = 0x2002FFFF;
+define symbol __region_SRAM2_start__  = 0x20030000;
+define symbol __region_SRAM2_end__    = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP, block CSTACK};
+place in SRAM1_region { };
+place in SRAM2_region { };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xc_flash_s.icf

@@ -0,0 +1,51 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0C01FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x30017FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NSC_start__   = 0x0C01E000;
+define symbol __region_ROM_NSC_end__     = 0x0C01FFFF;
+define symbol __region_SRAM1_start__     = 0x30000000;
+define symbol __region_SRAM1_end__       = 0x30017FFF;
+define symbol __region_SRAM2_start__     = 0;
+define symbol __region_SRAM2_end__       = 0;
+define symbol __region_ROM_NS_start__    = 0x08020000;
+define symbol __region_ROM_NS_end__      = 0x0803FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__      to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __region_ROM_NSC_start__          to __region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__      to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define exported symbol __NSC_region_start       = __region_ROM_NSC_start__;
+define exported symbol __NSC_region_end         = __region_ROM_NSC_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };
+place in SRAM1_region   { };
+place in SRAM2_region   { };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_SRAM1_start__  = 0x20000000;
+define symbol __region_SRAM1_end__    = 0x2002FFFF;
+define symbol __region_SRAM2_start__  = 0x20030000;
+define symbol __region_SRAM2_end__    = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in SRAM1_region { };
+place in SRAM2_region { };
+                        

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash_ns.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08040000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08040000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20018000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_SRAM1_start__  = 0x20018000;
+define symbol __region_SRAM1_end__    = 0x2002FFFF;
+define symbol __region_SRAM2_start__  = 0x20030000;
+define symbol __region_SRAM2_end__    = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP, block CSTACK};
+place in SRAM1_region { };
+place in SRAM2_region { };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xe_flash_s.icf

@@ -0,0 +1,51 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0C03FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x30017FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NSC_start__   = 0x0C03E000;
+define symbol __region_ROM_NSC_end__     = 0x0C03FFFF;
+define symbol __region_SRAM1_start__     = 0x30000000;
+define symbol __region_SRAM1_end__       = 0x30017FFF;
+define symbol __region_SRAM2_start__     = 0;
+define symbol __region_SRAM2_end__       = 0;
+define symbol __region_ROM_NS_start__    = 0x08040000;
+define symbol __region_ROM_NS_end__      = 0x0807FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__      to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __region_ROM_NSC_start__          to __region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__      to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define exported symbol __NSC_region_start       = __region_ROM_NSC_start__;
+define exported symbol __NSC_region_end         = __region_ROM_NSC_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };
+place in SRAM1_region   { };
+place in SRAM2_region   { };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram.icf

@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0;
+define symbol __ICFEDIT_region_ROM_end__   = 0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram_ns.icf

@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20018000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0;
+define symbol __ICFEDIT_region_ROM_end__   = 0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20018000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region     { readonly };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l552xx_sram_s.icf

@@ -0,0 +1,48 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x30000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0;
+define symbol __ICFEDIT_region_ROM_end__   = 0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x30017EFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NSC_start__   = 0;
+define symbol __region_ROM_NSC_end__     = 0;
+define symbol __region_RAM_NSC_start__   = 0x30017F00;
+define symbol __region_RAM_NSC_end__     = 0x30017FFF;
+define symbol __region_ROM_NS_start__    = 0;
+define symbol __region_ROM_NS_end__      = 0;
+define symbol __region_RAM_NS_start__    = 0x20018000;
+define symbol __region_RAM_NS_end__      = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __region_ROM_NSC_start__       to __region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_NSC_region  = mem:[from __region_RAM_NSC_start__       to __region_RAM_NSC_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_RAM_NS_start__;
+
+define exported symbol __NSC_region_start       = __region_RAM_NSC_start__;
+define exported symbol __NSC_region_end         = __region_RAM_NSC_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region     { readonly };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };
+place in RAM_NSC_region { section Veneer$$CMSE };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash.icf

@@ -0,0 +1,41 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_SRAM1_start__  = 0x20000000;
+define symbol __region_SRAM1_end__    = 0x2002FFFF;
+define symbol __region_SRAM2_start__  = 0x20030000;
+define symbol __region_SRAM2_end__    = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in SRAM1_region { };
+place in SRAM2_region { };
+                        

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash_ns.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08040000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08040000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20018000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_SRAM1_start__  = 0x20018000;
+define symbol __region_SRAM1_end__    = 0x2002FFFF;
+define symbol __region_SRAM2_start__  = 0x20030000;
+define symbol __region_SRAM2_end__    = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP, block CSTACK};
+place in SRAM1_region { };
+place in SRAM2_region { };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xe_flash_s.icf

@@ -0,0 +1,51 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0C03FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x30017FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NSC_start__   = 0x0C03E000;
+define symbol __region_ROM_NSC_end__     = 0x0C03FFFF;
+define symbol __region_SRAM1_start__     = 0x30000000;
+define symbol __region_SRAM1_end__       = 0x30017FFF;
+define symbol __region_SRAM2_start__     = 0;
+define symbol __region_SRAM2_end__       = 0;
+define symbol __region_ROM_NS_start__    = 0x08040000;
+define symbol __region_ROM_NS_end__      = 0x0807FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__      to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __region_ROM_NSC_start__          to __region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__      to __ICFEDIT_region_RAM_end__];
+define region SRAM1_region    = mem:[from __region_SRAM1_start__   to __region_SRAM1_end__];
+define region SRAM2_region    = mem:[from __region_SRAM2_start__   to __region_SRAM2_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_ROM_NS_start__;
+
+define exported symbol __NSC_region_start       = __region_ROM_NSC_start__;
+define exported symbol __NSC_region_end         = __region_ROM_NSC_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region     { readonly };
+place in ROM_NSC_region { section Veneer$$CMSE };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };
+place in SRAM1_region   { };
+place in SRAM2_region   { };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram.icf

@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0;
+define symbol __ICFEDIT_region_ROM_end__   = 0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram_ns.icf

@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20018000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0;
+define symbol __ICFEDIT_region_ROM_end__   = 0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20018000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region     { readonly };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/linker/stm32l562xx_sram_s.icf

@@ -0,0 +1,48 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x30000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0;
+define symbol __ICFEDIT_region_ROM_end__   = 0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x30017EFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_ROM_NSC_start__   = 0;
+define symbol __region_ROM_NSC_end__     = 0;
+define symbol __region_RAM_NSC_start__   = 0x30017F00;
+define symbol __region_RAM_NSC_end__     = 0x30017FFF;
+define symbol __region_ROM_NS_start__    = 0;
+define symbol __region_ROM_NS_end__      = 0;
+define symbol __region_RAM_NS_start__    = 0x20018000;
+define symbol __region_RAM_NS_end__      = 0x2003FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region ROM_NSC_region  = mem:[from __region_ROM_NSC_start__       to __region_ROM_NSC_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_NSC_region  = mem:[from __region_RAM_NSC_start__       to __region_RAM_NSC_end__];
+
+define exported symbol __VTOR_TABLE_start       = __ICFEDIT_intvec_start__;
+define exported symbol __VTOR_TABLE_NS_start    = __region_RAM_NS_start__;
+
+define exported symbol __NSC_region_start       = __region_RAM_NSC_start__;
+define exported symbol __NSC_region_end         = __region_RAM_NSC_end__;
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in RAM_region     { readonly };
+place in RAM_region     { readwrite, block HEAP, block CSTACK };
+place in RAM_NSC_region { section Veneer$$CMSE };

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/startup_stm32l552xx.s

@@ -0,0 +1,775 @@
+;********************************************************************************
+;* File Name          : startup_stm32l552xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L552xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler              ; Reset Handler
+
+        DCD     NMI_Handler                ; NMI Handler
+        DCD     HardFault_Handler          ; Hard Fault Handler
+        DCD     MemManage_Handler          ; MPU Fault Handler
+        DCD     BusFault_Handler           ; Bus Fault Handler
+        DCD     UsageFault_Handler         ; Usage Fault Handler
+        DCD     SecureFault_Handler        ; Secure Fault Handler
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     SVC_Handler                ; SVCall Handler
+        DCD     DebugMon_Handler           ; Debug Monitor Handler
+        DCD     0                          ; Reserved
+        DCD     PendSV_Handler             ; PendSV Handler
+        DCD     SysTick_Handler            ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     RTC_IRQHandler                    ; RTC non-secure interrupts through the EXTI line
+        DCD     RTC_S_IRQHandler                  ; RTC secure interrupts through the EXTI line
+        DCD     TAMP_IRQHandler                   ; Tamper non-secure interrupts through the EXTI line
+        DCD     TAMP_S_IRQHandler                 ; Tamper secure interrupts through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH non-secure interrupts
+        DCD     FLASH_S_IRQHandler                ; FLASH secure global interrupts
+        DCD     GTZC_IRQHandler                   ; GTZC global interrupts
+        DCD     RCC_IRQHandler                    ; RCC non-secure global interrupts
+        DCD     RCC_S_IRQHandler                  ; RCC secure global interrupts
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     EXTI5_IRQHandler                  ; EXTI Line5
+        DCD     EXTI6_IRQHandler                  ; EXTI Line6
+        DCD     EXTI7_IRQHandler                  ; EXTI Line7
+        DCD     EXTI8_IRQHandler                  ; EXTI Line8
+        DCD     EXTI9_IRQHandler                  ; EXTI Line9
+        DCD     EXTI10_IRQHandler                 ; EXTI Line10
+        DCD     EXTI11_IRQHandler                 ; EXTI Line11
+        DCD     EXTI12_IRQHandler                 ; EXTI Line12
+        DCD     EXTI13_IRQHandler                 ; EXTI Line13
+        DCD     EXTI14_IRQHandler                 ; EXTI Line14
+        DCD     EXTI15_IRQHandler                 ; EXTI Line15
+        DCD     DMAMUX1_IRQHandler                ; DMAMUX1 non-secure
+        DCD     DMAMUX1_S_IRQHandler              ; DMAMUX1 secure
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     DMA1_Channel8_IRQHandler          ; DMA1 Channel 8
+        DCD     ADC1_2_IRQHandler                 ; ADC1 & ADC2
+        DCD     DAC_IRQHandler                    ; DAC1&2 underrun errors
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 Interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 Interrupt 1
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     TIM6_IRQHandler                   ; TIM6
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     LPUART1_IRQHandler                ; LP UART1
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2
+        DCD     TIM15_IRQHandler                  ; TIM15
+        DCD     TIM16_IRQHandler                  ; TIM16
+        DCD     TIM17_IRQHandler                  ; TIM17
+        DCD     COMP_IRQHandler                   ; COMP1&2
+        DCD     USB_FS_IRQHandler                 ; USB FS
+        DCD     CRS_IRQHandler                    ; CRS
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     0                                 ; Reserved
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     0                                 ; Reserved
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     DMA2_Channel8_IRQHandler          ; DMA2 Channel 8
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     HASH_IRQHandler                   ; HASH
+        DCD     0                                 ; Reserved
+        DCD     LPTIM3_IRQHandler                 ; LP TIM3
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     UCPD1_IRQHandler                  ; UCPD1
+        DCD     ICACHE_IRQHandler                 ; ICACHE
+        DCD     0                                 ; Reserved
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK TAMP_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_S_IRQHandler
+        B TAMP_S_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK DMAMUX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_IRQHandler
+        B DMAMUX1_IRQHandler
+
+        PUBWEAK DMAMUX1_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_S_IRQHandler
+        B DMAMUX1_S_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK DMA1_Channel8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel8_IRQHandler
+        B DMA1_Channel8_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK USB_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_FS_IRQHandler
+        B USB_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMA2_Channel8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel8_IRQHandler
+        B DMA2_Channel8_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/iar/startup_stm32l562xx.s

@@ -0,0 +1,790 @@
+;********************************************************************************
+;* File Name          : startup_stm32l562xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32L562xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler              ; Reset Handler
+
+        DCD     NMI_Handler                ; NMI Handler
+        DCD     HardFault_Handler          ; Hard Fault Handler
+        DCD     MemManage_Handler          ; MPU Fault Handler
+        DCD     BusFault_Handler           ; Bus Fault Handler
+        DCD     UsageFault_Handler         ; Usage Fault Handler
+        DCD     SecureFault_Handler        ; Secure Fault Handler
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     SVC_Handler                ; SVCall Handler
+        DCD     DebugMon_Handler           ; Debug Monitor Handler
+        DCD     0                          ; Reserved
+        DCD     PendSV_Handler             ; PendSV Handler
+        DCD     SysTick_Handler            ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     RTC_IRQHandler                    ; RTC non-secure interrupts through the EXTI line
+        DCD     RTC_S_IRQHandler                  ; RTC secure interrupts through the EXTI line
+        DCD     TAMP_IRQHandler                   ; Tamper non-secure interrupts through the EXTI line
+        DCD     TAMP_S_IRQHandler                 ; Tamper secure interrupts through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH non-secure interrupts
+        DCD     FLASH_S_IRQHandler                ; FLASH secure global interrupts
+        DCD     GTZC_IRQHandler                   ; GTZC global interrupts
+        DCD     RCC_IRQHandler                    ; RCC non-secure global interrupts
+        DCD     RCC_S_IRQHandler                  ; RCC secure global interrupts
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     EXTI5_IRQHandler                  ; EXTI Line5
+        DCD     EXTI6_IRQHandler                  ; EXTI Line6
+        DCD     EXTI7_IRQHandler                  ; EXTI Line7
+        DCD     EXTI8_IRQHandler                  ; EXTI Line8
+        DCD     EXTI9_IRQHandler                  ; EXTI Line9
+        DCD     EXTI10_IRQHandler                 ; EXTI Line10
+        DCD     EXTI11_IRQHandler                 ; EXTI Line11
+        DCD     EXTI12_IRQHandler                 ; EXTI Line12
+        DCD     EXTI13_IRQHandler                 ; EXTI Line13
+        DCD     EXTI14_IRQHandler                 ; EXTI Line14
+        DCD     EXTI15_IRQHandler                 ; EXTI Line15
+        DCD     DMAMUX1_IRQHandler                ; DMAMUX1 non-secure
+        DCD     DMAMUX1_S_IRQHandler              ; DMAMUX1 secure
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     DMA1_Channel8_IRQHandler          ; DMA1 Channel 8
+        DCD     ADC1_2_IRQHandler                 ; ADC1 & ADC2
+        DCD     DAC_IRQHandler                    ; DAC1&2 underrun errors
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 Interrupt 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 Interrupt 1
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     TIM6_IRQHandler                   ; TIM6
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     LPUART1_IRQHandler                ; LP UART1
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2
+        DCD     TIM15_IRQHandler                  ; TIM15
+        DCD     TIM16_IRQHandler                  ; TIM16
+        DCD     TIM17_IRQHandler                  ; TIM17
+        DCD     COMP_IRQHandler                   ; COMP1&2
+        DCD     USB_FS_IRQHandler                 ; USB FS
+        DCD     CRS_IRQHandler                    ; CRS
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     OCTOSPI1_IRQHandler               ; OctoSPI1 global interrupt
+        DCD     0                                 ; Reserved
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     0                                 ; Reserved
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     DMA2_Channel8_IRQHandler          ; DMA2 Channel 8
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     AES_IRQHandler                    ; AES global interrupt
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     HASH_IRQHandler                   ; HASH
+        DCD     PKA_IRQHandler                    ; PKA
+        DCD     LPTIM3_IRQHandler                 ; LP TIM3
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     UCPD1_IRQHandler                  ; UCPD1
+        DCD     ICACHE_IRQHandler                 ; ICACHE
+        DCD     OTFDEC1_IRQHandler                ; OTFDEC1
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SecureFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SecureFault_Handler
+        B SecureFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK RTC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_S_IRQHandler
+        B RTC_S_IRQHandler
+
+        PUBWEAK TAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_IRQHandler
+        B TAMP_IRQHandler
+
+        PUBWEAK TAMP_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_S_IRQHandler
+        B TAMP_S_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK FLASH_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_S_IRQHandler
+        B FLASH_S_IRQHandler
+
+        PUBWEAK GTZC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GTZC_IRQHandler
+        B GTZC_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK RCC_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_S_IRQHandler
+        B RCC_S_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK EXTI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_IRQHandler
+        B EXTI5_IRQHandler
+
+        PUBWEAK EXTI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_IRQHandler
+        B EXTI6_IRQHandler
+
+        PUBWEAK EXTI7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_IRQHandler
+        B EXTI7_IRQHandler
+
+        PUBWEAK EXTI8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_IRQHandler
+        B EXTI8_IRQHandler
+
+        PUBWEAK EXTI9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_IRQHandler
+        B EXTI9_IRQHandler
+
+        PUBWEAK EXTI10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_IRQHandler
+        B EXTI10_IRQHandler
+
+        PUBWEAK EXTI11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_IRQHandler
+        B EXTI11_IRQHandler
+
+        PUBWEAK EXTI12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_IRQHandler
+        B EXTI12_IRQHandler
+
+        PUBWEAK EXTI13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_IRQHandler
+        B EXTI13_IRQHandler
+
+        PUBWEAK EXTI14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_IRQHandler
+        B EXTI14_IRQHandler
+
+        PUBWEAK EXTI15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_IRQHandler
+        B EXTI15_IRQHandler
+
+        PUBWEAK DMAMUX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_IRQHandler
+        B DMAMUX1_IRQHandler
+
+        PUBWEAK DMAMUX1_S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_S_IRQHandler
+        B DMAMUX1_S_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK DMA1_Channel8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel8_IRQHandler
+        B DMA1_Channel8_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK USB_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_FS_IRQHandler
+        B USB_FS_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK OCTOSPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK DMA2_Channel8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel8_IRQHandler
+        B DMA2_Channel8_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK HASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_IRQHandler
+        B HASH_IRQHandler
+
+        PUBWEAK PKA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PKA_IRQHandler
+        B PKA_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK UCPD1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UCPD1_IRQHandler
+        B UCPD1_IRQHandler
+
+        PUBWEAK ICACHE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ICACHE_IRQHandler
+        B ICACHE_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c

@@ -0,0 +1,344 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l5xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file configures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_SRC                            | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_M                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_N                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_SRC                            | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_M                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_N                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB FS,              | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l5xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 4000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint32_t MSIRangeTable[16] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \
+                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
+                                      0U,       0U,       0U,        0U};  /* MISRAC-2012: 0U for unexpected value */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+  if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
+  { /* MSISRANGE from RCC_CSR applies */
+    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
+  }
+  else
+  { /* MSIRANGE from RCC_CR applies */
+    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
+  }
+  /*MSI frequency range in HZ*/
+  msirange = MSIRangeTable[msirange];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:  /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C:  /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
+
+      switch (pllsource)
+      {
+        case 0x02:  /* HSI used as PLL clock source */
+          pllvco = (HSI_VALUE / pllm);
+          break;
+
+        case 0x03:  /* HSE used as PLL clock source */
+          pllvco = (HSE_VALUE / pllm);
+          break;
+
+        default:    /* MSI used as PLL clock source */
+          pllvco = (msirange / pllm);
+          break;
+      }
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c

@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l5xx_ns.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *          to be used in non-secure application when the system implements
+  *          the TrustZone-M security.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at non-secure startup before
+  *                      branch to non-secure main program.
+  *                      This call is made inside the "startup_stm32l5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
+  *   configure the system clock before to branch to main secure program.
+  *   Later, when non-secure SystemInit() function is called, in "startup_stm32l5xx.s"
+  *   file, the system clock may have been updated from reset value by the main
+  *   secure program.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l5xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE_NS   /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00018000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE_NS   /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00040000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 4000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint32_t MSIRangeTable[16] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \
+                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
+                                      0U,       0U,       0U,        0U};  /* MISRAC-2012: 0U for unexpected value */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* Vector table location and FPU setup done by secure application */
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#endif
+
+  /* Non-secure main application shall call SystemCoreClockUpdate() to update */
+  /* the SystemCoreClock variable to insure non-secure application relies on  */
+  /* the initial clock reference set by secure application.                   */
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   From the non-secure application, the SystemCoreClock value is
+  *         retrieved from the secure domain via a Non-Secure Callable function
+  *         since the RCC peripheral may be protected with security attributes
+  *         that prevent to compute the SystemCoreClock variable from the RCC
+  *         peripheral registers.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  /* Get the SystemCoreClock value from the secure domain */
+  SystemCoreClock = SECURE_SystemCoreClockUpdate();
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c

@@ -0,0 +1,385 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l5xx_s.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
+  *          to be used in secure application when the system implements
+  *          the TrustZone-M security.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at secure startup just after reset
+  *                      and before branch to secure main program.
+  *                      This call is made inside the "startup_stm32l5xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *      - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
+  *                                        the variable SystemCoreClock and return
+  *                                        its value to the non-secure calling 
+  *                                        application. It must be called whenever
+  *                                        the core clock is changed during program
+  *                                        execution.
+  *
+  *   After each device reset the MSI (4 MHz) is used as system clock source.
+  *   Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
+  *   configure the system clock before to branch to main program.
+  *
+  *   This file insures the system clock as follows:
+  *=============================================================================
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | MSI
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 4000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 4000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_SRC                                | No clock
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 1
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_R                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_SRC                            | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_M                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_N                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_Q                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI1_R                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_SRC                            | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_M                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_N                              | NA
+  *-----------------------------------------------------------------------------
+  *        PLLSAI2_P                              | NA
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB FS,              | Disabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System
+  * @{
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l5xx.h"
+#include "partition_stm32l5xx.h"  /* Trustzone-M core secure attributes */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+#if defined ( __ICCARM__ )
+#  define CMSE_NS_ENTRY __cmse_nonsecure_entry
+#else
+#  define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    16000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE_S    /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE_S    /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 4000000U;
+
+  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint32_t MSIRangeTable[16] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \
+                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
+                                      0U,       0U,       0U,        0U};  /* MISRAC-2012: 0U for unexpected value */
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L5xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+  /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
+  TZ_SAU_Setup();
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
+#endif
+
+  /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+
+  SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U));  /* set CP10 and CP11 Full Access */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Depending on secure or non-secure compilation, the adequate RCC peripheral
+  *         memory are is accessed thanks to RCC alias defined in stm32l5xxxx.h device file
+  *         so either from RCC_S peripheral register mapped memory in secure or from
+  *         RCC_NS peripheral register mapped memory in non-secure.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              16 MHz) but the real value may vary depending on the variations
+  *              in voltage and temperature.
+  *
+  *         (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
+
+  /* Get MSI Range frequency--------------------------------------------------*/
+  if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
+  { /* MSISRANGE from RCC_CSR applies */
+    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
+  }
+  else
+  { /* MSIRANGE from RCC_CR applies */
+    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
+  }
+  /*MSI frequency range in HZ*/
+  msirange = MSIRangeTable[msirange];
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case 0x00:  /* MSI used as system clock source */
+      SystemCoreClock = msirange;
+      break;
+
+    case 0x04:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+
+    case 0x08:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+
+    case 0x0C:  /* PLL used as system clock  source */
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLR
+         */
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
+
+      switch (pllsource)
+      {
+        case 0x02:  /* HSI used as PLL clock source */
+          pllvco = (HSI_VALUE / pllm);
+          break;
+
+        case 0x03:  /* HSE used as PLL clock source */
+          pllvco = (HSE_VALUE / pllm);
+          break;
+
+        default:    /* MSI used as PLL clock source */
+          pllvco = (msirange / pllm);
+          break;
+      }
+      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
+      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
+      SystemCoreClock = pllvco/pllr;
+      break;
+
+    default:
+      SystemCoreClock = msirange;
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+/**
+  * @brief  Secure Non-Secure-Callable function to return the current
+  *         SystemCoreClock value after SystemCoreClock update.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  * @retval SystemCoreClock value (HCLK)
+  */
+CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
+{
+  SystemCoreClockUpdate();
+  
+  return SystemCoreClock;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32_assert_template.h

@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_ASSERT_H
+#define STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal.h

@@ -0,0 +1,702 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_H
+#define STM32L5xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_conf.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Types HAL Exported Types
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+  * @{
+  */
+#define SYSCFG_IT_FPU_IOC              SYSCFG_FPUIMR_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC              SYSCFG_FPUIMR_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC              SYSCFG_FPUIMR_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC              SYSCFG_FPUIMR_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC              SYSCFG_FPUIMR_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC              SYSCFG_FPUIMR_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_SRAM2WRP_0_31 SRAM2 Page Write protection (0 to 31)
+  * @{
+  */
+#define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_P0WP /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_P1WP /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_P2WP /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_P3WP /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_P4WP /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_P5WP /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_P6WP /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_P7WP /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_P8WP /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_P9WP /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_P10WP /*!< SRAM2 Write protection page 10 */
+#define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_P11WP /*!< SRAM2 Write protection page 11 */
+#define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_P12WP /*!< SRAM2 Write protection page 12 */
+#define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_P13WP /*!< SRAM2 Write protection page 13 */
+#define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_P14WP /*!< SRAM2 Write protection page 14 */
+#define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_P15WP /*!< SRAM2 Write protection page 15 */
+#define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_P16WP /*!< SRAM2 Write protection page 16 */
+#define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_P17WP /*!< SRAM2 Write protection page 17 */
+#define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_P18WP /*!< SRAM2 Write protection page 18 */
+#define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_P19WP /*!< SRAM2 Write protection page 19 */
+#define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_P20WP /*!< SRAM2 Write protection page 20 */
+#define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_P21WP /*!< SRAM2 Write protection page 21 */
+#define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_P22WP /*!< SRAM2 Write protection page 22 */
+#define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_P23WP /*!< SRAM2 Write protection page 23 */
+#define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_P24WP /*!< SRAM2 Write protection page 24 */
+#define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_P25WP /*!< SRAM2 Write protection page 25 */
+#define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_P26WP /*!< SRAM2 Write protection page 26 */
+#define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_P27WP /*!< SRAM2 Write protection page 27 */
+#define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_P28WP /*!< SRAM2 Write protection page 28 */
+#define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_P29WP /*!< SRAM2 Write protection page 29 */
+#define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_P30WP /*!< SRAM2 Write protection page 30 */
+#define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_P31WP /*!< SRAM2 Write protection page 31 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
+  * @{
+  */
+#define SYSCFG_SRAM2WRP_PAGE32         SYSCFG_SWPR2_P32WP /*!< SRAM2 Write protection page 32 */
+#define SYSCFG_SRAM2WRP_PAGE33         SYSCFG_SWPR2_P33WP /*!< SRAM2 Write protection page 33 */
+#define SYSCFG_SRAM2WRP_PAGE34         SYSCFG_SWPR2_P34WP /*!< SRAM2 Write protection page 34 */
+#define SYSCFG_SRAM2WRP_PAGE35         SYSCFG_SWPR2_P35WP /*!< SRAM2 Write protection page 35 */
+#define SYSCFG_SRAM2WRP_PAGE36         SYSCFG_SWPR2_P36WP /*!< SRAM2 Write protection page 36 */
+#define SYSCFG_SRAM2WRP_PAGE37         SYSCFG_SWPR2_P37WP /*!< SRAM2 Write protection page 37 */
+#define SYSCFG_SRAM2WRP_PAGE38         SYSCFG_SWPR2_P38WP /*!< SRAM2 Write protection page 38 */
+#define SYSCFG_SRAM2WRP_PAGE39         SYSCFG_SWPR2_P39WP /*!< SRAM2 Write protection page 39 */
+#define SYSCFG_SRAM2WRP_PAGE40         SYSCFG_SWPR2_P40WP /*!< SRAM2 Write protection page 40 */
+#define SYSCFG_SRAM2WRP_PAGE41         SYSCFG_SWPR2_P41WP /*!< SRAM2 Write protection page 41 */
+#define SYSCFG_SRAM2WRP_PAGE42         SYSCFG_SWPR2_P42WP /*!< SRAM2 Write protection page 42 */
+#define SYSCFG_SRAM2WRP_PAGE43         SYSCFG_SWPR2_P43WP /*!< SRAM2 Write protection page 43 */
+#define SYSCFG_SRAM2WRP_PAGE44         SYSCFG_SWPR2_P44WP /*!< SRAM2 Write protection page 44 */
+#define SYSCFG_SRAM2WRP_PAGE45         SYSCFG_SWPR2_P45WP /*!< SRAM2 Write protection page 45 */
+#define SYSCFG_SRAM2WRP_PAGE46         SYSCFG_SWPR2_P46WP /*!< SRAM2 Write protection page 46 */
+#define SYSCFG_SRAM2WRP_PAGE47         SYSCFG_SWPR2_P47WP /*!< SRAM2 Write protection page 47 */
+#define SYSCFG_SRAM2WRP_PAGE48         SYSCFG_SWPR2_P48WP /*!< SRAM2 Write protection page 48 */
+#define SYSCFG_SRAM2WRP_PAGE49         SYSCFG_SWPR2_P49WP /*!< SRAM2 Write protection page 49 */
+#define SYSCFG_SRAM2WRP_PAGE50         SYSCFG_SWPR2_P50WP /*!< SRAM2 Write protection page 50 */
+#define SYSCFG_SRAM2WRP_PAGE51         SYSCFG_SWPR2_P51WP /*!< SRAM2 Write protection page 51 */
+#define SYSCFG_SRAM2WRP_PAGE52         SYSCFG_SWPR2_P52WP /*!< SRAM2 Write protection page 52 */
+#define SYSCFG_SRAM2WRP_PAGE53         SYSCFG_SWPR2_P53WP /*!< SRAM2 Write protection page 53 */
+#define SYSCFG_SRAM2WRP_PAGE54         SYSCFG_SWPR2_P54WP /*!< SRAM2 Write protection page 54 */
+#define SYSCFG_SRAM2WRP_PAGE55         SYSCFG_SWPR2_P55WP /*!< SRAM2 Write protection page 55 */
+#define SYSCFG_SRAM2WRP_PAGE56         SYSCFG_SWPR2_P56WP /*!< SRAM2 Write protection page 56 */
+#define SYSCFG_SRAM2WRP_PAGE57         SYSCFG_SWPR2_P57WP /*!< SRAM2 Write protection page 57 */
+#define SYSCFG_SRAM2WRP_PAGE58         SYSCFG_SWPR2_P58WP /*!< SRAM2 Write protection page 58 */
+#define SYSCFG_SRAM2WRP_PAGE59         SYSCFG_SWPR2_P59WP /*!< SRAM2 Write protection page 59 */
+#define SYSCFG_SRAM2WRP_PAGE60         SYSCFG_SWPR2_P60WP /*!< SRAM2 Write protection page 60 */
+#define SYSCFG_SRAM2WRP_PAGE61         SYSCFG_SWPR2_P61WP /*!< SRAM2 Write protection page 61 */
+#define SYSCFG_SRAM2WRP_PAGE62         SYSCFG_SWPR2_P62WP /*!< SRAM2 Write protection page 62 */
+#define SYSCFG_SRAM2WRP_PAGE63         SYSCFG_SWPR2_P63WP /*!< SRAM2 Write protection page 63 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0U              /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0U              /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_flags_definition Flags
+  * @{
+  */
+
+#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */
+#define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCFG_Lock_items SYSCFG Lock items
+  * @brief SYSCFG items to set lock on
+  * @{
+  */
+#define SYSCFG_MPU_NSEC                SYSCFG_CNSLCKR_LOCKNSMPU            /*!< Non-secure MPU lock (privileged secure or non-secure only) */
+#define SYSCFG_VTOR_NSEC               SYSCFG_CNSLCKR_LOCKNSVTOR           /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU                     (SYSCFG_CSLCKR_LOCKSAU << 16U)      /*!< SAU lock (privileged secure code only) */
+#define SYSCFG_MPU_SEC                 (SYSCFG_CSLCKR_LOCKSMPU << 16U)     /*!< Secure MPU lock (privileged secure code only) */
+#define SYSCFG_VTOR_AIRCR_SEC          (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */
+#define SYSCFG_LOCK_ALL                (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC)  /*!< All */
+#else
+#define SYSCFG_LOCK_ALL                (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC)  /*!< All (privileged secure or non-secure only) */
+#endif /* __ARM_FEATURE_CMSE */
+/**
+  * @}
+  */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items
+  * @brief SYSCFG items to configure secure or non-secure attributes on
+  * @{
+  */
+#define SYSCFG_CLK                     SYSCFG_SECCFGR_SYSCFGSEC   /*!< SYSCFG clock control */
+#define SYSCFG_CLASSB                  SYSCFG_SECCFGR_CLASSBSEC   /*!< Class B */
+#define SYSCFG_SRAM2                   SYSCFG_SECCFGR_SRAM2SEC    /*!< SRAM2 */
+#define SYSCFG_FPU                     SYSCFG_SECCFGR_FPUSEC      /*!< FPU */
+#define SYSCFG_ALL                     (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_SRAM2 | SYSCFG_FPU) /*!< All */
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_attributes SYSCFG attributes
+  * @brief SYSCFG secure or non-secure attributes
+  * @{
+  */
+#define SYSCFG_SEC                     0x00000001U   /*!< Secure attribute      */
+#define SYSCFG_NSEC                    0x00000000U   /*!< Non-secure attribute  */
+/**
+  * @}
+  */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_FDCAN1_STOP)
+#define __HAL_DBGMCU_FREEZE_FDCAN1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_FDCAN1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_FDCAN1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_FDCAN1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM3()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM3()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM3_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  SRAM2 page 0 to 31 write protection enable macro
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_0_31
+  * @note   Write protection can only be disabled by a system reset
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+                                                                SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
+                                                            }while(0)
+
+/** @brief  SRAM2 page 32 to 63 write protection enable macro
+  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
+  * @note   Write protection can only be disabled by a system reset
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+                                                                SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
+                                                            }while(0)
+
+/** @brief  SRAM2 page write protection unlock prior to erase
+  * @note   Writing a wrong key reactivates the write protection
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\
+                                                 SYSCFG->SKR = 0x53;\
+                                                }while(0)
+
+/** @brief  SRAM2 erase
+  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
+  */
+#define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
+
+/** @brief  Floating Point Unit interrupt enable/disable macros
+  * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+  */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
+                                                            }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\
+                                                            }while(0)
+
+/** @brief  SYSCFG Break ECC lock.
+  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief  SYSCFG Break Cortex-M33 Lockup lock.
+  *         Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief  SYSCFG Break SRAM2 parity lock.
+  *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief  Check SYSCFG flag is set or not.
+  * @param  __FLAG__  specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
+  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
+
+/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
+  */
+#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__  This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+  * @{
+  */
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+
+#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC)  ||\
+                                              ((__ATTRIBUTES__) == SYSCFG_NSEC))
+
+#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK)   == SYSCFG_CLK)    || \
+                                              (((__ITEM__) & SYSCFG_CLK)   == SYSCFG_CLASSB) || \
+                                              (((__ITEM__) & SYSCFG_SRAM2) == SYSCFG_SRAM2)  || \
+                                              (((__ITEM__) & SYSCFG_FPU)   == SYSCFG_CLK)    || \
+                                              (((__ITEM__) & ~(SYSCFG_ALL)) == 0U))
+
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC)       == SYSCFG_MPU_NSEC)       || \
+                                        (((__ITEM__) & SYSCFG_VTOR_NSEC)      == SYSCFG_VTOR_NSEC)      || \
+                                        (((__ITEM__) & SYSCFG_SAU)            == SYSCFG_SAU)            || \
+                                        (((__ITEM__) & SYSCFG_MPU_SEC)        == SYSCFG_MPU_SEC)        || \
+                                        (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \
+                                        (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U))
+
+#else
+
+#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC)  == SYSCFG_MPU_NSEC)    || \
+                                        (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC)   || \
+                                        (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U))
+
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void              HAL_MspInit(void);
+void              HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void               HAL_IncTick(void);
+void               HAL_Delay(uint32_t Delay);
+uint32_t           HAL_GetTick(void);
+uint32_t           HAL_GetTickPrio(void);
+HAL_StatusTypeDef  HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void               HAL_SuspendTick(void);
+void               HAL_ResumeTick(void);
+uint32_t           HAL_GetHalVersion(void);
+uint32_t           HAL_GetREVID(void);
+uint32_t           HAL_GetDEVID(void);
+uint32_t           HAL_GetUIDw0(void);
+uint32_t           HAL_GetUIDw1(void);
+uint32_t           HAL_GetUIDw2(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+  * @{
+  */
+
+/* DBGMCU Peripheral Control functions  *****************************************/
+void              HAL_DBGMCU_EnableDBGStopMode(void);
+void              HAL_DBGMCU_DisableDBGStopMode(void);
+void              HAL_DBGMCU_EnableDBGStandbyMode(void);
+void              HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+  * @{
+  */
+
+/* SYSCFG Control functions  ****************************************************/
+void              HAL_SYSCFG_SRAM2Erase(void);
+
+void              HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void              HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void              HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void              HAL_SYSCFG_DisableVREFBUF(void);
+
+void              HAL_SYSCFG_EnableIOAnalogBooster(void);
+void              HAL_SYSCFG_DisableIOAnalogBooster(void);
+void              HAL_SYSCFG_EnableIOAnalogSwitchVdd(void);
+void              HAL_SYSCFG_DisableIOAnalogSwitchVdd(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group5
+  * @{
+  */
+
+/* SYSCFG Lock functions ********************************************/
+void              HAL_SYSCFG_Lock(uint32_t Item);
+HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem);
+
+/**
+  * @}
+  */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/** @addtogroup HAL_Exported_Functions_Group6
+  * @{
+  */
+
+/* SYSCFG Attributes functions ********************************************/
+void              HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes);
+HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
+
+/**
+  * @}
+  */
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_comp.h

@@ -0,0 +1,751 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_comp.h
+  * @author  MCD Application Team
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_COMP_H
+#define STM32L5xx_HAL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+#include "stm32l5xx_ll_exti.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+  * @{
+  */
+
+/**
+  * @brief  COMP Init structure definition
+  */
+typedef struct
+{
+
+  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
+                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
+                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
+                                    This parameter can be a value of @ref COMP_WindowMode */
+
+  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
+                                    Note: For the characteristics of comparator power modes
+                                          (propagation delay and power consumption), refer to device datasheet.
+                                    This parameter can be a value of @ref COMP_PowerMode */
+
+  uint32_t InputPlus;          /*!< Set comparator input plus (non-inverting input).
+                                    This parameter can be a value of @ref COMP_InputPlus */
+
+  uint32_t InputMinus;         /*!< Set comparator input minus (inverting input).
+                                    This parameter can be a value of @ref COMP_InputMinus */
+
+  uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
+                                    This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t OutputPol;          /*!< Set comparator output polarity.
+                                    This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t BlankingSrce;       /*!< Set comparator blanking source.
+                                    This parameter can be a value of @ref COMP_BlankingSrce */
+
+  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
+                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
+
+} COMP_InitTypeDef;
+
+/**
+  * @brief  HAL COMP state machine: HAL COMP states definition
+  */
+#define COMP_STATE_BITFIELD_LOCK  (0x10U)
+typedef enum
+{
+  HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
+  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
+  HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
+  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
+  HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
+  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
+} HAL_COMP_StateTypeDef;
+
+/**
+  * @brief  COMP Handle Structure definition
+  */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+typedef struct __COMP_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  HAL_LockTypeDef    Lock;            /*!< Locking object           */
+  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
+  __IO uint32_t      ErrorCode;       /*!< COMP error code */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+  void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
+  void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
+  void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+} COMP_HandleTypeDef;
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL COMP Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
+  HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
+  HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
+} HAL_COMP_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL COMP Callback pointer definition
+  */
+typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_Error_Code COMP Error Code
+  * @{
+  */
+#define HAL_COMP_ERROR_NONE             (0x00UL)  /*!< No error */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)  /*!< Invalid Callback error */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_WindowMode COMP Window Mode
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLE                 (0x00000000UL)         /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_PowerMode COMP power mode
+  * @{
+  */
+/* Note: For the characteristics of comparator power modes                    */
+/*       (propagation delay and power consumption),                           */
+/*       refer to device datasheet.                                           */
+#define COMP_POWERMODE_HIGHSPEED       (0x00000000UL)         /*!< High Speed */
+#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
+#define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CSR_PWRMODE)     /*!< Ultra-low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
+  * @{
+  */
+#define COMP_INPUT_PLUS_IO1            (0x00000000UL)         /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
+#define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
+#define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1, not available for COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputMinus COMP input minus (inverting input)
+  * @{
+  */
+#define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
+#define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
+#define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
+#define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define COMP_INPUT_MINUS_DAC1_CH2      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */ 
+#define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Hysteresis COMP hysteresis
+  * @{
+  */
+#define COMP_HYSTERESIS_NONE           (0x00000000UL)                       /*!< No hysteresis */
+#define COMP_HYSTERESIS_LOW            (                  COMP_CSR_HYST_0)  /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1                  )  /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)  /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputPolarity COMP output Polarity
+  * @{
+  */
+#define COMP_OUTPUTPOL_NONINVERTED     (0x00000000UL)         /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
+#define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_BlankingSrce  COMP blanking source
+  * @{
+  */
+#define COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP1  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1) */
+#define COMP_BLANKINGSRC_TIM2_OC3_COMP1  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1) */
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP1  (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1) */
+#define COMP_BLANKINGSRC_TIM3_OC4_COMP2  (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP2) */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2) */
+#define COMP_BLANKINGSRC_TIM15_OC1_COMP2 (COMP_CSR_BLANKING_2)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP2) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+  * @{
+  */
+/* Note: Comparator output level values are fixed to "0" and "1",             */
+/* corresponding COMP register bit is managed by HAL function to match        */
+/* with these values (independently of bit position in register).             */
+
+/* When output polarity is not inverted, comparator output is low when
+   the input plus is at a lower voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_LOW              (0x00000000UL)
+/* When output polarity is not inverted, comparator output is high when
+   the input plus is at a higher voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_HIGH             (0x00000001UL)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
+  * @{
+  */
+#define COMP_TRIGGERMODE_NONE                 (0x00000000UL)                                            /*!< Comparator output triggering no External Interrupt Line */
+#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
+#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
+#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
+#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+  * @{
+  */
+
+/** @defgroup COMP_Handle_Management  COMP Handle Management
+  * @{
+  */
+
+/** @brief  Reset COMP handle state.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
+                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
+                                                      (__HANDLE__)->MspInitCallback = NULL;            \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                    } while(0)
+#else
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+#endif
+
+/**
+  * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
+  * @param __HANDLE__ COMP handle
+  * @retval None
+  */
+#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
+
+/**
+  * @brief  Enable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Disable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Lock the specified comparator configuration.
+  * @note   Using this macro induce HAL COMP handle state machine being no
+  *         more in line with COMP instance state.
+  *         To keep HAL COMP handle state machine updated, it is recommended
+  *         to use function "HAL_COMP_Lock')".
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
+
+/**
+  * @brief  Check whether the specified comparator is locked.
+  * @param  __HANDLE__  COMP handle
+  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
+  */
+#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exti_Management  COMP external interrupt line management
+  * @{
+  */
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Generate a software interrupt on the COMP1 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Check whether the COMP1 EXTI line rising flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG()       LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Clear the COMP1 EXTI rising flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG()     LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Check whether the COMP1 EXTI line falling flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG()      LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Clear the COMP1 EXTI falling flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG()    LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
+                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+                                                             } while(0)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */                                         
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
+                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+                                                             } while(0)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Generate a software interrupt on the COMP2 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Check whether the COMP2 EXTI line rising flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG()       LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Clear the COMP2 EXTI rising flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG()     LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Check whether the COMP2 EXTI line falling flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG()      LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Clear the COMP2 EXTI falling flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG()    LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+  * @{
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_LINE_COMP1           (LL_EXTI_LINE_21)  /*!< EXTI line 21 connected to COMP1 output */
+#define COMP_EXTI_LINE_COMP2           (LL_EXTI_LINE_22)  /*!< EXTI line 22 connected to COMP2 output */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_IT                        (0x00000001UL)  /*!< EXTI line event with interruption */
+#define COMP_EXTI_EVENT                     (0x00000002UL)  /*!< EXTI line event only (without interruption) */
+#define COMP_EXTI_RISING                    (0x00000010UL)  /*!< EXTI line event on rising edge */
+#define COMP_EXTI_FALLING                   (0x00000020UL)  /*!< EXTI line event on falling edge */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+  * @{
+  */
+
+/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
+  * @{
+  */
+/**
+  * @brief  Get the specified EXTI line for a comparator instance.
+  * @param  __INSTANCE__  specifies the COMP instance.
+  * @retval value of @ref COMP_ExtiLine
+  */
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
+                                             : COMP_EXTI_LINE_COMP2)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
+  * @{
+  */
+#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
+                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
+
+#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
+                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
+
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) ((__COMP_INSTANCE__ == COMP1)                     \
+                                                               ? (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) ||  \
+                                                                  ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) ||  \
+                                                                  ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)   ) \
+                                                               :                                                \
+                                                               (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) ||    \
+                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)   )   \
+                                                              )
+
+/* Note: On this STM32 series, comparator input minus parameters are          */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
+
+#define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)                    \
+  (   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2)    \
+  )
+
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
+   ((((__INSTANCE__) == COMP1) &&                                               \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)))        \
+    ||                                                                          \
+    (((__INSTANCE__) == COMP2) &&                                               \
+     (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)           ||      \
+      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2) ||      \
+      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) ||      \
+      ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP2))))
+
+
+#define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
+                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
+                                            pCOMP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+/* Callback in interrupt mode */
+void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+  * @{
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* COMP1 || COMP2 */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_conf_template.h

@@ -0,0 +1,439 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l5xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CONF_H
+#define STM32L5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_GTZC_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_ICACHE_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_OTFDEC_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PKA_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE          16000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT 100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE          4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE          16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE        48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                          The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE           32000UL    /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                  /*!< Value of the Internal Low Speed oscillator in Hz
+                                          The real value may vary depending on the variations
+                                          in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE          32768UL    /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT 5000UL    /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE  48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/**
+  * @brief External clock source for SAI2 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
+  #define EXTERNAL_SAI2_CLOCK_VALUE   48000UL /*!< Value of the SAI2 External clock source in Hz*/
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define VDD_VALUE          3300UL /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY  ((1UL<<__NVIC_PRIO_BITS) - 1UL)  /*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS           0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT               1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32l5xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS      0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS      0U
+#define USE_HAL_HASH_REGISTER_CALLBACKS       0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_MMC_REGISTER_CALLBACKS        0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS       0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS        0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS      0U
+#define USE_HAL_OSPI_REGISTER_CALLBACKS       0U
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS     0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_PKA_REGISTER_CALLBACKS        0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SD_REGISTER_CALLBACKS         0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS       0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_TSC_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   1U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME   1U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER            0U
+
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32l5xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l5xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32l5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32l5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+  #include "stm32l5xx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32l5xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+  #include "stm32l5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+  #include "stm32l5xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+  #include "stm32l5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+  #include "stm32l5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32l5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+  #include "stm32l5xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32l5xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32l5xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+  #include "stm32l5xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32l5xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+  #include "stm32l5xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32l5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32l5xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+  #include "stm32l5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32l5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+  #include "stm32l5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+  #include "stm32l5xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+  #include "stm32l5xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+  #include "stm32l5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+  #include "stm32l5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+  #include "stm32l5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32l5xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+  #include "stm32l5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32l5xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+  #include "stm32l5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+  #include "stm32l5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+  #include "stm32l5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h

@@ -0,0 +1,168 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CORTEX_H
+#define STM32L5xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+  * @brief   Cortex control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) > SysTick_IRQn)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_crc.h

@@ -0,0 +1,343 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_crc.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CRC_H
+#define STM32L5xx_HAL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CRC_Exported_Types CRC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  CRC HAL State Structure definition
+  */
+typedef enum
+{
+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
+} HAL_CRC_StateTypeDef;
+
+/**
+  * @brief CRC Init Structure definition
+  */
+typedef struct
+{
+  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+                                            In that case, there is no need to set GeneratingPolynomial field.
+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+
+  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
+
+  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
+                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
+
+  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
+                                           Value can be either one of
+                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
+                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
+
+  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */
+
+  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+                                           Can be either one of the following values
+                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
+                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+
+  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
+                                            Can be either
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
+} CRC_InitTypeDef;
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct
+{
+  CRC_TypeDef                 *Instance;   /*!< Register base address        */
+
+  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
+
+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
+
+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
+
+  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+                                            Can be either
+                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
+
+                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
+                                           must occur if InputBufferFormat is not one of the three values listed above  */
+} CRC_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Constants CRC Exported Constants
+  * @{
+  */
+
+/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
+  * @{
+  */
+#define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
+  * @{
+  */
+#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
+  * @{
+  */
+#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
+#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
+  * @{
+  */
+#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
+#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
+  * @{
+  */
+#define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
+#define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+  * @{
+  */
+#define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
+#define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
+  * @{
+  */
+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
+#define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRC_Exported_Macros CRC Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRC handle state.
+  * @param  __HANDLE__ CRC handle.
+  * @retval None
+  */
+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
+
+/**
+  * @brief  Reset CRC Data Register.
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
+
+/**
+  * @brief  Set CRC INIT non-default value
+  * @param  __HANDLE__ CRC handle
+  * @param  __INIT__ 32-bit initial value
+  * @retval None
+  */
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+
+/**
+  * @brief Store data in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @param __VALUE__  Value to be stored in the ID register
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval None
+  */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+  * @brief Return the data stored in the Independent Data (ID) register.
+  * @param __HANDLE__ CRC handle
+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+  * @retval Value of the ID register
+  */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
+  * @}
+  */
+
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup  CRC_Private_Macros CRC Private Macros
+  * @{
+  */
+
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+
+#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
+                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
+                                       ((LENGTH) == CRC_POLYLENGTH_7B))
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+  * @}
+  */
+
+/* Include CRC HAL Extended module */
+#include "stm32l5xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_crc_ex.h

@@ -0,0 +1,153 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CRC_EX_H
+#define STM32L5xx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
+#define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
+#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Set CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__ CRC handle
+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+  * @retval None
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+  * @{
+  */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp.h

@@ -0,0 +1,648 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_cryp.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CRYP_H
+#define STM32L5xx_HAL_CRYP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+#if defined(AES)
+
+/** @defgroup CRYP CRYP
+  * @brief CRYP HAL module driver.
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Types CRYP Exported Types
+  * @{
+  */
+
+/**
+  * @brief CRYP Init Structure definition
+  */
+
+typedef struct
+{
+  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
+                                        This parameter can be a value of @ref CRYP_Data_Type */
+  uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
+                                        128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
+  uint32_t *pKey;                      /*!< The key used for encryption/decryption */
+  uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
+                                         counter in CTR mode */
+  uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
+                                        AES Algorithm ECB/CBC/CTR/GCM or CCM
+                                        This parameter can be a value of @ref CRYP_Algorithm_Mode */
+  uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
+                                        GCM : also known as Additional Authentication Data
+                                        CCM : named B1 composed of the associated data length and Associated Data. */
+  uint32_t HeaderSize;                 /*!< The size of header buffer */
+  uint32_t *B0;                        /*!< B0 is first authentication block used only  in AES CCM mode */
+  uint32_t DataWidthUnit;              /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+  uint32_t HeaderWidthUnit;            /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
+  uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+                                           Vector only once and to skip configuration for consecutive processings.
+                                           This parameter can be a value of @ref CRYP_Configuration_Skip */
+
+} CRYP_ConfigTypeDef;
+
+
+/**
+  * @brief  CRYP State Structure definition
+  */
+
+typedef enum
+{
+  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
+  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
+  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP BUSY, internal processing is ongoing  */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+  HAL_CRYP_STATE_SUSPENDED         = 0x03U,   /*!< CRYP suspended                        */
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+} HAL_CRYP_STATETypeDef;
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+/**
+  * @brief HAL CRYP mode suspend definitions
+  */
+typedef enum
+{
+  HAL_CRYP_SUSPEND_NONE            = 0x00U,    /*!< CRYP processing suspension not requested */
+  HAL_CRYP_SUSPEND                 = 0x01U     /*!< CRYP processing suspension requested     */
+}HAL_SuspendTypeDef;
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+/**
+  * @brief  CRYP handle Structure definition
+  */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
+typedef struct __CRYP_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  AES_TypeDef                       *Instance;            /*!< AES Register base address */
+
+  CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
+
+  FunctionalState                   AutoKeyDerivation;   /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
+                                                         This parameter can be a value of ENABLE/DISABLE */
+
+  uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+  uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
+
+  __IO uint16_t                     CrypHeaderCount;   /*!< Counter of header data */
+
+  __IO uint16_t                     CrypInCount;      /*!< Counter of input data */
+
+  __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */
+
+  uint16_t                          Size;             /*!< length of input data in words */
+
+  uint32_t                          Phase;            /*!< CRYP peripheral phase */
+
+  DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
+
+  DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
+
+  HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
+
+  __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
+
+  __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
+
+  uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
+                                                           configuration can be skipped */
+
+  uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
+                                                           for a single signature computation after several
+                                                           messages processing */
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+  void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
+  void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
+  void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
+
+  void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
+  void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
+
+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
+
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+
+  __IO HAL_SuspendTypeDef     SuspendRequest;          /*!< CRYP peripheral suspension request flag */
+
+  CRYP_ConfigTypeDef          Init_saved;              /*!< copy of CRYP required parameters when processing is suspended */
+
+  uint32_t                    *pCrypInBuffPtr_saved;   /*!< copy of CRYP input pointer when processing is suspended */
+
+  uint32_t                    *pCrypOutBuffPtr_saved;  /*!< copy of CRYP output pointer when processing is suspended */
+
+  uint32_t                    CrypInCount_saved;       /*!< copy of CRYP input data counter when processing is suspended */
+
+  uint32_t                    CrypOutCount_saved;      /*!< copy of CRYP output data counter when processing is suspended */
+
+  uint32_t                    Phase_saved;             /*!< copy of CRYP authentication phase when processing is suspended */
+
+  __IO HAL_CRYP_STATETypeDef  State_saved;             /*!< copy of CRYP peripheral state when processing is suspended */
+
+  uint32_t                    IV_saved[4];             /*!< copy of Initialisation Vector registers */
+
+  uint32_t                    SUSPxR_saved[8];         /*!< copy of suspension registers */
+
+  uint32_t                    CR_saved;                /*!< copy of CRYP control register  when processing is suspended*/
+
+  uint32_t                    Key_saved[8];            /*!< copy of key registers */
+
+  uint16_t                    Size_saved;              /*!< copy of input buffer size */
+
+  uint16_t                    CrypHeaderCount_saved;   /*!< copy of CRYP header data counter when processing is suspended */
+
+  uint32_t                    SizesSum_saved;          /*!< copy of SizesSum when processing is suspended */
+
+  uint32_t                    ResumingFlag;            /*!< resumption flag to bypass steps already carried out */
+
+  FunctionalState             AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
+
+#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+
+} CRYP_HandleTypeDef;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
+  * @brief  HAL CRYP Callback ID enumeration definition
+  * @{
+  */
+typedef enum
+{
+  HAL_CRYP_MSPINIT_CB_ID           = 0x00U,    /*!< CRYP MspInit callback ID                        */
+  HAL_CRYP_MSPDEINIT_CB_ID         = 0x01U,     /*!< CRYP MspDeInit callback ID                      */
+  HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x02U,    /*!< CRYP Input FIFO transfer completed callback ID  */
+  HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x03U,    /*!< CRYP Output FIFO transfer completed callback ID */
+  HAL_CRYP_ERROR_CB_ID             = 0x04U,    /*!< CRYP Error callback ID                          */
+} HAL_CRYP_CallbackIDTypeDef;
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
+  * @brief  HAL CRYP Callback pointer definition
+  * @{
+  */
+
+typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
+
+/**
+  * @}
+  */
+
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Error_Definition   CRYP Error Definition
+  * @{
+  */
+#define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
+#define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
+#define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
+#define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
+#define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
+#define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
+#define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
+  * @{
+  */
+
+#define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+  * @{
+  */
+
+#define CRYP_HEADERWIDTHUNIT_WORD   0x00000000U  /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< By default, header size unit is byte */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
+  * @{
+  */
+
+#define CRYP_AES_ECB            0x00000000U                       /*!< Electronic codebook chaining algorithm                   */
+#define CRYP_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
+#define CRYP_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
+#define CRYP_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
+#define CRYP_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Key_Size CRYP Key Size
+  * @{
+  */
+
+#define CRYP_KEYSIZE_128B         0x00000000U          /*!< 128-bit long key */
+#define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE       /*!< 256-bit long key */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Data_Type CRYP Data Type
+  * @{
+  */
+
+#define CRYP_DATATYPE_32B         0x00000000U  /*!< 32-bit data type (no swapping)        */
+#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
+#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
+#define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Interrupt  CRYP Interrupt
+  * @{
+  */
+
+#define CRYP_IT_CCFIE     AES_CR_CCFIE /*!< Computation Complete interrupt enable */
+#define CRYP_IT_ERRIE     AES_CR_ERRIE /*!< Error interrupt enable                */
+#define CRYP_IT_WRERR     AES_SR_WRERR  /*!< Write Error           */
+#define CRYP_IT_RDERR     AES_SR_RDERR  /*!< Read Error            */
+#define CRYP_IT_CCF       AES_SR_CCF    /*!< Computation completed */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Flags CRYP Flags
+  * @{
+  */
+
+/* status flags */
+#define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
+#define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
+#define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
+#define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
+/* clearing flags */
+#define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
+#define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+  * @{
+  */
+
+#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
+  * @{
+  */
+
+/** @brief Reset CRYP handle state
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @retval None
+  */
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
+                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;\
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                     }while(0U)
+#else
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable/Disable the CRYP peripheral.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @retval None
+  */
+
+#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
+
+
+/** @brief  Check whether the specified CRYP status flag is set or not.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values for TinyAES:
+  *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
+  *            @arg @ref CRYP_IT_WRERR Write Error
+  *            @arg @ref CRYP_IT_RDERR Read Error
+  *            @arg @ref CRYP_IT_CCF Computation Complete
+  *         This parameter can be one of the following values for CRYP:
+  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
+  *                                 or a key preparation (for AES decryption).
+  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
+  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
+  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
+  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
+  *            @arg CRYP_FLAG_OFFU: Output FIFO is full
+  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+
+#define CRYP_FLAG_MASK  0x0000001FU
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the CRYP pending status flag.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *         This parameter can be one of the following values:
+  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
+  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
+  * @retval None
+  */
+
+#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
+
+
+/** @brief  Check whether the specified CRYP interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param __INTERRUPT__ CRYP interrupt source to check
+  *         This parameter can be one of the following values for TinyAES:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  * @retval State of interruption (TRUE or FALSE).
+  */
+
+#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Check whether the specified CRYP interrupt is set or not.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param  __INTERRUPT__ specifies the interrupt to check.
+  *         This parameter can be one of the following values for TinyAES:
+  *            @arg @ref CRYP_IT_WRERR Write Error
+  *            @arg @ref CRYP_IT_RDERR Read Error
+  *            @arg @ref CRYP_IT_CCF  Computation Complete
+  *         This parameter can be one of the following values for CRYP:
+  *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
+  *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
+  */
+
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Enable the CRYP interrupt.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param  __INTERRUPT__ CRYP Interrupt.
+  *         This parameter can be one of the following values for TinyAES:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  *         This parameter can be one of the following values for CRYP:
+  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
+  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+  * @retval None
+  */
+
+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the CRYP interrupt.
+  * @param  __HANDLE__ specifies the CRYP handle.
+  * @param  __INTERRUPT__ CRYP Interrupt.
+  *         This parameter can be one of the following values for TinyAES:
+  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
+  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
+  *         This parameter can be one of the following values for CRYP:
+  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
+  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
+  * @retval None
+  */
+
+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Include CRYP HAL Extended module */
+#include "stm32l5xx_hal_cryp_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
+void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
+HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
+#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
+/**
+  * @}
+  */
+
+/** @addtogroup CRYP_Exported_Functions_Group2
+  * @{
+  */
+
+/* encryption/decryption ***********************************/
+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup CRYP_Exported_Functions_Group3
+  * @{
+  */
+/* Interrupt Handler functions  **********************************************/
+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRYP_Private_Macros CRYP Private Macros
+  * @{
+  */
+
+/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
+  * @{
+  */
+
+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB)      || \
+                                      ((ALGORITHM)  == CRYP_AES_CBC)     || \
+                                      ((ALGORITHM)  == CRYP_AES_CTR)     || \
+                                      ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
+                                      ((ALGORITHM)  == CRYP_AES_CCM))
+
+
+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
+                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))
+
+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
+                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
+                                   ((DATATYPE) == CRYP_DATATYPE_8B)  || \
+                                   ((DATATYPE) == CRYP_DATATYPE_1B))
+
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+
+#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)                                             \
+       (((((ALGO) == CRYP_AES_CTR)) &&                                             \
+            ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
+             (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
+         (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC)                  || \
+          ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Constants CRYP Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup CRYP_Private_Defines CRYP Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Variables CRYP Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYP_Private_Functions CRYP Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* AES */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CRYP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h

@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYPEx HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_CRYP_EX_H
+#define STM32L5xx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+#if defined(AES)
+
+/** @defgroup CRYPEx CRYPEx
+  * @brief CRYP Extension HAL module driver.
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+  * @{
+  */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+  * @{
+  */
+void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
+void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* AES */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h

@@ -0,0 +1,550 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_dac.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DAC_H
+#define STM32L5xx_HAL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+#if defined(DAC1)
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
+
+} HAL_DAC_StateTypeDef;
+
+/**
+  * @brief  DAC handle Structure definition
+  */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+typedef struct __DAC_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+
+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
+
+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
+
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
+
+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
+
+  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
+  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+} DAC_HandleTypeDef;
+
+/**
+  * @brief   DAC Configuration sample and hold Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+} DAC_SampleAndHoldConfTypeDef;
+
+/**
+  * @brief   DAC Configuration regular Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_HighFrequency;            /*!< Specifies the frequency interface mode
+                                              This parameter can be a value of @ref DAC_HighFrequency */
+
+  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
+                                              This parameter can be a value of @ref DAC_SampleAndHold */
+
+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref DAC_output_buffer */
+
+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
+
+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
+                                              This parameter must be a value of @ref DAC_UserTrimming
+                                              DAC_UserTrimming is either factory or user trimming */
+
+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
+
+} DAC_ChannelConfTypeDef;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DAC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
+  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
+  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
+  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
+  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
+  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
+  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
+  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
+  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
+  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
+  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
+} HAL_DAC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL DAC Callback pointer definition
+  */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+  * @{
+  */
+#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
+#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+  * @{
+  */
+#define DAC_TRIGGER_NONE                0x00000000U                                                                       /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_SOFTWARE            (                                                                    DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T1_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */
+#define DAC_TRIGGER_T2_TRGO             (                                DAC_CR_TSEL1_1                    | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO             (                                DAC_CR_TSEL1_1   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO             (                 DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO            (DAC_CR_TSEL1_3                                                    | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_LPTIM1_OUT          (DAC_CR_TSEL1_3 |                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_LPTIM2_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                    |DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
+#define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+  * @{
+  */
+#define DAC_CHANNEL_1                      0x00000000U
+#define DAC_CHANNEL_2                      0x00000010U
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment DAC data alignment
+  * @{
+  */
+#define DAC_ALIGN_12B_R                    0x00000000U
+#define DAC_ALIGN_12B_L                    0x00000004U
+#define DAC_ALIGN_8B_R                     0x00000008U
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+  * @{
+  */
+#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_IT_definition  DAC IT definition
+  * @{
+  */
+#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+  * @{
+  */
+#define DAC_CHIPCONNECT_DISABLE    0x00000000U
+#define DAC_CHIPCONNECT_ENABLE     (DAC_MCR_MODE1_0)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_UserTrimming DAC User Trimming
+  * @{
+  */
+#define DAC_TRIMMING_FACTORY        0x00000000U           /*!< Factory trimming */
+#define DAC_TRIMMING_USER           0x00000001U           /*!< User trimming */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_SampleAndHold DAC power mode
+  * @{
+  */
+#define DAC_SAMPLEANDHOLD_DISABLE     0x00000000U
+#define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
+
+/**
+  * @}
+  */
+/** @defgroup DAC_HighFrequency DAC high frequency interface mode
+  * @{
+  */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE        0x00000000U        /*!< High frequency interface mode disabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ    (DAC_CR_HFSEL)     /*!< High frequency interface mode compatible to AHB>80MHz enabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC      0x00000002U        /*!< High frequency interface mode automatic */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @brief Reset DAC handle state.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @retval None
+  */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
+                                                     } while(0)
+#else
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/** @brief Enable the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __DAC_Channel__ specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Disable the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __DAC_Channel__ specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Set DHR12R1 alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
+
+/** @brief  Set DHR12R2 alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
+
+/** @brief  Set DHR12RD alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief  Check whether the specified DAC interrupt source is enabled or not.
+  * @param __HANDLE__ DAC handle
+  * @param __INTERRUPT__ DAC interrupt source to check
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Get the selected DAC's flag status.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to get.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @retval None
+  */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the DAC's flag.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @retval None
+  */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+  * @{
+  */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                 ((CHANNEL) == DAC_CHANNEL_2))
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
+
+#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFU)
+
+/**
+  * @}
+  */
+
+/* Include DAC HAL Extended module */
+#include "stm32l5xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+                                    uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+                                               pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions DAC Private Functions
+  * @{
+  */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*STM32L5xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac_ex.h

@@ -0,0 +1,241 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_dac_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DAC_EX_H
+#define STM32L5xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+#if defined(DAC1)
+
+/** @addtogroup DACEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL State structures definition
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+  * @{
+  */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                0x00000000U                                                         /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            0x00000000U                                                         /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+  * @{
+  */
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#define  IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE)         || \
+                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ)     || \
+                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
+
+#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
+
+#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)
+
+#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
+                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
+
+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
+
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+                                   ((TRIMMING) == DAC_TRIMMING_USER))
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+                                          uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+                                            uint32_t NewTrimmingValue);
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Private_Functions
+  * @{
+  */
+
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*STM32L5xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_def.h

@@ -0,0 +1,213 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DEF_H
+#define STM32L5xx_HAL_DEF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+#include <arm_cmse.h>
+#endif
+
+#include "stm32l5xx.h"
+#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \
+                        do{                                                      \
+                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                            (__DMA_HANDLE__).Parent = (__HANDLE__);              \
+                        } while(0)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  /* Reserved for future use */
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+  #ifndef __packed
+    #define __packed  __attribute__((packed))
+  #endif
+#elif defined (__GNUC__) /* GNU Compiler */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed  __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif
+  #ifndef __ALIGN_END
+    #define __ALIGN_END  __attribute__((aligned (4)))
+  #endif
+#elif defined (__GNUC__) /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END  __attribute__((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __ICCARM__ */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+/* ARM Compiler V6
+   ---------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined (__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC  __ramfunc
+
+#elif defined (__GNUC__)
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC  __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+  * @brief  __NOINLINE definition
+  */
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__)
+/* ARM V6 & GNU Compiler
+   ---------------------
+*/
+#define __NOINLINE __attribute__((noinline))
+
+#elif defined (__ICCARM__)
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_DEF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dfsdm.h

@@ -0,0 +1,793 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_dfsdm.h
+  * @author  MCD Application Team
+  * @brief   Header file of DFSDM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DFSDM_H
+#define STM32L5xx_HAL_DFSDM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL DFSDM Channel states definition
+  */
+typedef enum
+{
+  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
+  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
+  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
+} HAL_DFSDM_Channel_StateTypeDef;
+
+/**
+  * @brief  DFSDM channel output clock structure definition
+  */
+typedef struct
+{
+  FunctionalState Activation; /*!< Output clock enable/disable */
+  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
+                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+  uint32_t        Divider;    /*!< Output clock divider.
+                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
+} DFSDM_Channel_OutputClockTypeDef;
+
+/**
+  * @brief  DFSDM channel input structure definition
+  */
+typedef struct
+{
+  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
+                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
+  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
+                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */
+  uint32_t Pins;        /*!< Input pins are taken from same or following channel.
+                             This parameter can be a value of @ref DFSDM_Channel_InputPins */
+} DFSDM_Channel_InputTypeDef;
+
+/**
+  * @brief  DFSDM channel serial interface structure definition
+  */
+typedef struct
+{
+  uint32_t Type;     /*!< SPI or Manchester modes.
+                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
+  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
+                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */
+} DFSDM_Channel_SerialInterfaceTypeDef;
+
+/**
+  * @brief  DFSDM channel analog watchdog structure definition
+  */
+typedef struct
+{
+  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
+                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
+  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
+                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+} DFSDM_Channel_AwdTypeDef;
+
+/**
+  * @brief  DFSDM channel init structure definition
+  */
+typedef struct
+{
+  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
+  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
+  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
+  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
+  int32_t                              Offset;          /*!< DFSDM channel offset.
+                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
+                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+} DFSDM_Channel_InitTypeDef;
+
+/**
+  * @brief  DFSDM channel handle structure definition
+  */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+typedef struct __DFSDM_Channel_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
+{
+  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
+  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
+  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+  void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);       /*!< DFSDM channel clock absence detection callback */
+  void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);        /*!< DFSDM channel short circuit detection callback */
+  void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);    /*!< DFSDM channel MSP init callback */
+  void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);  /*!< DFSDM channel MSP de-init callback */
+#endif
+} DFSDM_Channel_HandleTypeDef;
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  DFSDM channel callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U, /*!< DFSDM channel clock absence detection callback ID */
+  HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
+  HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */
+  HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */
+} HAL_DFSDM_Channel_CallbackIDTypeDef;
+
+/**
+  * @brief  DFSDM channel callback pointer definition
+  */
+typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+#endif
+
+/**
+  * @brief  HAL DFSDM Filter states definition
+  */
+typedef enum
+{
+  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
+  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
+  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
+  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
+  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
+  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
+} HAL_DFSDM_Filter_StateTypeDef;
+
+/**
+  * @brief  DFSDM filter regular conversion parameters structure definition
+  */
+typedef struct
+{
+  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
+                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
+  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
+} DFSDM_Filter_RegularParamTypeDef;
+
+/**
+  * @brief  DFSDM filter injected conversion parameters structure definition
+  */
+typedef struct
+{
+  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
+                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */
+  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
+  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
+  uint32_t        ExtTrigger;     /*!< External trigger.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
+  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
+} DFSDM_Filter_InjectedParamTypeDef;
+
+/**
+  * @brief  DFSDM filter parameters structure definition
+  */
+typedef struct
+{
+  uint32_t SincOrder;       /*!< Sinc filter order.
+                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
+  uint32_t Oversampling;    /*!< Filter oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+  uint32_t IntOversampling; /*!< Integrator oversampling ratio.
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
+} DFSDM_Filter_FilterParamTypeDef;
+
+/**
+  * @brief  DFSDM filter init structure definition
+  */
+typedef struct
+{
+  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
+  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
+  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
+} DFSDM_Filter_InitTypeDef;
+
+/**
+  * @brief  DFSDM filter handle structure definition
+  */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+typedef struct __DFSDM_Filter_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
+{
+  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
+  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
+  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
+  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
+  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
+  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
+  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
+  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
+  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
+  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
+  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
+  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
+  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+  void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                      uint32_t Channel, uint32_t Threshold);                            /*!< DFSDM filter analog watchdog callback */
+  void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter regular conversion complete callback */
+  void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half regular conversion complete callback */
+  void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);      /*!< DFSDM filter injected conversion complete callback */
+  void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);  /*!< DFSDM filter half injected conversion complete callback */
+  void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);            /*!< DFSDM filter error callback */
+  void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);          /*!< DFSDM filter MSP init callback */
+  void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);        /*!< DFSDM filter MSP de-init callback */
+#endif
+} DFSDM_Filter_HandleTypeDef;
+
+/**
+  * @brief  DFSDM filter analog watchdog parameters structure definition
+  */
+typedef struct
+{
+  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
+                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
+  uint32_t Channel;         /*!< Analog watchdog channel selection.
+                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
+  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
+  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */
+} DFSDM_Filter_AwdParamTypeDef;
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  DFSDM filter callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */
+  HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */
+  HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */
+  HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */
+  HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */
+  HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */
+  HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */
+} HAL_DFSDM_Filter_CallbackIDTypeDef;
+
+/**
+  * @brief  DFSDM filter callback pointer definition
+  */
+typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+#endif
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
+  * @{
+  */
+
+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U             /*!< Source for output clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for output clock is audio clock */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
+  * @{
+  */
+#define DFSDM_CHANNEL_EXTERNAL_INPUTS    0x00000000U             /*!< Data are taken from external inputs */
+#define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */
+#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
+  * @{
+  */
+#define DFSDM_CHANNEL_STANDARD_MODE         0x00000000U             /*!< Standard data packing mode */
+#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
+#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
+  * @{
+  */
+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U             /*!< Input from pins on same channel */
+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_RISING         0x00000000U             /*!< SPI with rising edge */
+#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */
+#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */
+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
+  * @{
+  */
+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
+  * @{
+  */
+#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */
+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
+  * @{
+  */
+#define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */
+#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
+#define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
+  * @{
+  */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1  (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
+                                          DFSDM_FLTCR1_JEXTSEL_2)                          /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  DFSDM_FLTCR1_JEXTSEL_3                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15     (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
+                                          DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
+                                          DFSDM_FLTCR1_JEXTSEL_4)                          /*!< For all DFSDM filters */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
+  * @{
+  */
+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
+  * @{
+  */
+#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */
+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
+#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
+#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
+  * @{
+  */
+#define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
+  * @{
+  */
+#define DFSDM_FILTER_ERROR_NONE             0x00000000U /*!< No error */
+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */
+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
+#define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_BreakSignals DFSDM break signals
+  * @{
+  */
+#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
+#define DFSDM_BREAK_SIGNAL_0  0x00000001U /*!< Break signal 0 */
+#define DFSDM_BREAK_SIGNAL_1  0x00000002U /*!< Break signal 1 */
+#define DFSDM_BREAK_SIGNAL_2  0x00000004U /*!< Break signal 2 */
+#define DFSDM_BREAK_SIGNAL_3  0x00000008U /*!< Break signal 3 */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
+  * @{
+  */
+/* DFSDM Channels ------------------------------------------------------------*/
+/* The DFSDM channels are defined as follows:
+   - in 16-bit LSB the channel mask is set
+   - in 16-bit MSB the channel number is set
+   e.g. for channel 5 definition:
+        - the channel mask is 0x00000020 (bit 5 is set)
+        - the channel number 5 is 0x00050000
+        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
+#define DFSDM_CHANNEL_0                              0x00000001U
+#define DFSDM_CHANNEL_1                              0x00010002U
+#define DFSDM_CHANNEL_2                              0x00020004U
+#define DFSDM_CHANNEL_3                              0x00030008U
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
+  * @{
+  */
+#define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U /*!< Conversion are not continuous */
+#define DFSDM_CONTINUOUS_CONV_ON             0x00000001U /*!< Conversion are continuous */
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
+  * @{
+  */
+#define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U /*!< Analog watchdog high threshold */
+#define DFSDM_AWD_LOW_THRESHOLD             0x00000001U /*!< Analog watchdog low threshold */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
+ * @{
+ */
+
+/** @brief  Reset DFSDM channel handle state.
+  * @param  __HANDLE__ DFSDM channel handle.
+  * @retval None
+  */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \
+                                                               (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
+                                                               (__HANDLE__)->MspInitCallback = NULL;                \
+                                                               (__HANDLE__)->MspDeInitCallback = NULL;              \
+                                                             } while(0)
+#else
+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
+#endif
+
+/** @brief  Reset DFSDM filter handle state.
+  * @param  __HANDLE__ DFSDM filter handle.
+  * @retval None
+  */
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \
+                                                              (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
+                                                              (__HANDLE__)->MspInitCallback = NULL;               \
+                                                              (__HANDLE__)->MspDeInitCallback = NULL;             \
+                                                            } while(0)
+#else
+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
+#endif
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Include DFSDM HAL Extension module */
+#include "stm32l5xx_hal_dfsdm_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
+  * @{
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
+  * @{
+  */
+/* Channel initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/* Channel callbacks register/unregister functions ****************************/
+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
+                                                     HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
+                                                     pDFSDM_Channel_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
+                                                       HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
+  * @{
+  */
+/* Channel operation functions ************************************************/
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+
+int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
+
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+
+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
+  * @{
+  */
+/* Channel state function *****************************************************/
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
+  * @{
+  */
+/* Filter initialization and de-initialization functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
+/* Filter callbacks register/unregister functions ****************************/
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
+                                                    HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
+                                                    pDFSDM_Filter_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
+                                                      HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,
+                                                       pDFSDM_Filter_AwdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
+  * @{
+  */
+/* Filter control functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel,
+                                                   uint32_t                    ContinuousMode);
+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                                   uint32_t                    Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
+  * @{
+  */
+/* Filter operation functions *********************/
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+                                              DFSDM_Filter_AwdParamTypeDef *awdParam);
+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
+
+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
+  * @{
+  */
+/* Filter state functions *****************************************************/
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
+* @{
+*/
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
+                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
+                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
+                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))
+#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)
+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)
+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
+                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))
+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))
+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
+                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
+#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)
+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \
+                                                       ((CHANNEL) == DFSDM_CHANNEL_3))
+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
+#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
+                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_DFSDM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dfsdm_ex.h

@@ -0,0 +1,89 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_dfsdm_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DFSDM HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DFSDM_EX_H
+#define STM32L5xx_HAL_DFSDM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);
+HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros
+  * @{
+  */
+
+#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE)   ((VALUE) < 64U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_DFSDM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dma.h

@@ -0,0 +1,780 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DMA_H
+#define STM32L5xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
+                                           This parameter can be a value of @ref DMA_request */
+
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
+                                           from memory to memory or from peripheral to memory.
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
+                                           This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_mode
+                                           @note The circular buffer mode cannot be used if the memory-to-memory
+                                                 data transfer is configured on the selected Channel */
+
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+
+/**
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */
+
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef    *Instance;                                                     /*!< Register base address                */
+
+  DMA_InitTypeDef       Init;                                                           /*!< DMA communication parameters         */
+
+  HAL_LockTypeDef       Lock;                                                           /*!< DMA locking object                   */
+
+  __IO HAL_DMA_StateTypeDef  State;                                                     /*!< DMA transfer state                   */
+
+  void                  *Parent;                                                        /*!< Parent object state                  */
+
+  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer complete callback       */
+
+  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA Half transfer complete callback  */
+
+  void                  (* XferM1CpltCallback)(struct __DMA_HandleTypeDef * hdma);      /*!< DMA transfer complete Memory1 callback        */
+
+  void                  (* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef * hdma);  /*!< DMA transfer Half complete Memory1 callback   */
+
+  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer error callback          */
+
+  void                  (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer abort callback          */
+
+  __IO uint32_t         ErrorCode;                                                      /*!< DMA Error code                       */
+
+  DMA_TypeDef           *DmaBaseAddress;                                                /*!< DMA Channel Base Address             */
+
+  uint32_t              ChannelIndex;                                                   /*!< DMA Channel Index                    */
+
+  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                      /*!< Register base address                */
+
+  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                /*!< DMAMUX Channels Status Base Address  */
+
+  uint32_t                         DMAmuxChannelStatusMask;                             /*!< DMAMUX Channel Status Mask           */
+
+  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                   /*!< DMAMUX request generator Base Address */
+
+  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                             /*!< DMAMUX request generator Address     */
+
+  uint32_t                         DMAmuxRequestGenStatusMask;                          /*!< DMAMUX request generator Status mask */
+
+
+}DMA_HandleTypeDef;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */
+#define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */
+#define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */
+#define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */
+#define HAL_DMA_ERROR_SYNC                 0x00000200U    /*!< DMAMUX sync overrun  error              */
+#define HAL_DMA_ERROR_REQGEN               0x00000400U    /*!< DMAMUX request generator overrun  error */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_request DMA request
+  * @{
+  */
+#define DMA_REQUEST_MEM2MEM            0U  /*!< memory to memory transfer   */
+
+#define DMA_REQUEST_GENERATOR0         1U  /*!< DMAMUX1 request generator 0 */
+#define DMA_REQUEST_GENERATOR1         2U  /*!< DMAMUX1 request generator 1 */
+#define DMA_REQUEST_GENERATOR2         3U  /*!< DMAMUX1 request generator 2 */
+#define DMA_REQUEST_GENERATOR3         4U  /*!< DMAMUX1 request generator 3 */
+
+#define DMA_REQUEST_ADC1               5U  /*!< DMAMUX1 ADC1 request      */
+#define DMA_REQUEST_ADC2               6U  /*!< DMAMUX1 ADC2 request      */
+
+#define DMA_REQUEST_DAC1_CH1           7U   /*!< DMAMUX1 DAC1 CH1 request  */
+#define DMA_REQUEST_DAC1_CH2           8U   /*!< DMAMUX1 DAC1 CH2 request  */
+
+#define DMA_REQUEST_TIM6_UP            9U   /*!< DMAMUX1 TIM6 UP request   */
+#define DMA_REQUEST_TIM7_UP           10U   /*!< DMAMUX1 TIM7 UP request   */
+
+#define DMA_REQUEST_SPI1_RX           11U   /*!< DMAMUX1 SPI1 RX request   */
+#define DMA_REQUEST_SPI1_TX           12U   /*!< DMAMUX1 SPI1 TX request   */
+#define DMA_REQUEST_SPI2_RX           13U   /*!< DMAMUX1 SPI2 RX request   */
+#define DMA_REQUEST_SPI2_TX           14U   /*!< DMAMUX1 SPI2 TX request   */
+#define DMA_REQUEST_SPI3_RX           15U   /*!< DMAMUX1 SPI3 RX request   */
+#define DMA_REQUEST_SPI3_TX           16U   /*!< DMAMUX1 SPI3 TX request   */
+
+#define DMA_REQUEST_I2C1_RX           17U   /*!< DMAMUX1 I2C1 RX request   */
+#define DMA_REQUEST_I2C1_TX           18U   /*!< DMAMUX1 I2C1 TX request   */
+#define DMA_REQUEST_I2C2_RX           19U   /*!< DMAMUX1 I2C2 RX request   */
+#define DMA_REQUEST_I2C2_TX           20U   /*!< DMAMUX1 I2C2 TX request   */
+#define DMA_REQUEST_I2C3_RX           21U   /*!< DMAMUX1 I2C3 RX request   */
+#define DMA_REQUEST_I2C3_TX           22U   /*!< DMAMUX1 I2C3 TX request   */
+#define DMA_REQUEST_I2C4_RX           23U   /*!< DMAMUX1 I2C4 RX request   */
+#define DMA_REQUEST_I2C4_TX           24U   /*!< DMAMUX1 I2C4 TX request   */
+
+#define DMA_REQUEST_USART1_RX         25U   /*!< DMAMUX1 USART1 RX request */
+#define DMA_REQUEST_USART1_TX         26U   /*!< DMAMUX1 USART1 TX request */
+#define DMA_REQUEST_USART2_RX         27U   /*!< DMAMUX1 USART2 RX request */
+#define DMA_REQUEST_USART2_TX         28U   /*!< DMAMUX1 USART2 TX request */
+#define DMA_REQUEST_USART3_RX         29U   /*!< DMAMUX1 USART3 RX request */
+#define DMA_REQUEST_USART3_TX         30U   /*!< DMAMUX1 USART3 TX request */
+
+#define DMA_REQUEST_UART4_RX          31U  /*!< DMAMUX1 UART4 RX request  */
+#define DMA_REQUEST_UART4_TX          32U  /*!< DMAMUX1 UART4 TX request  */
+#define DMA_REQUEST_UART5_RX          33U  /*!< DMAMUX1 UART5 RX request  */
+#define DMA_REQUEST_UART5_TX          34U  /*!< DMAMUX1 UART5 TX request  */
+
+#define DMA_REQUEST_LPUART1_RX        35U  /*!< DMAMUX1 LP_UART1_RX request */
+#define DMA_REQUEST_LPUART1_TX        36U  /*!< DMAMUX1 LP_UART1_RX request */
+
+#define DMA_REQUEST_SAI1_A            37U  /*!< DMAMUX1 SAI1 A request    */
+#define DMA_REQUEST_SAI1_B            38U  /*!< DMAMUX1 SAI1 B request    */
+#define DMA_REQUEST_SAI2_A            39U  /*!< DMAMUX1 SAI2 A request    */
+#define DMA_REQUEST_SAI2_B            40U  /*!< DMAMUX1 SAI2 B request    */
+
+#define DMA_REQUEST_OCTOSPI1          41U  /*!< DMAMUX1 OCTOSPI1 request  */
+
+#define DMA_REQUEST_TIM1_CH1          42U  /*!< DMAMUX1 TIM1 CH1 request  */
+#define DMA_REQUEST_TIM1_CH2          43U  /*!< DMAMUX1 TIM1 CH2 request  */
+#define DMA_REQUEST_TIM1_CH3          44U  /*!< DMAMUX1 TIM1 CH3 request  */
+#define DMA_REQUEST_TIM1_CH4          45U  /*!< DMAMUX1 TIM1 CH4 request  */
+#define DMA_REQUEST_TIM1_UP           46U  /*!< DMAMUX1 TIM1 UP  request  */
+#define DMA_REQUEST_TIM1_TRIG         47U  /*!< DMAMUX1 TIM1 TRIG request */
+#define DMA_REQUEST_TIM1_COM          48U  /*!< DMAMUX1 TIM1 COM request  */
+
+#define DMA_REQUEST_TIM8_CH1          49U  /*!< DMAMUX1 TIM8 CH1 request  */
+#define DMA_REQUEST_TIM8_CH2          50U  /*!< DMAMUX1 TIM8 CH2 request  */
+#define DMA_REQUEST_TIM8_CH3          51U  /*!< DMAMUX1 TIM8 CH3 request  */
+#define DMA_REQUEST_TIM8_CH4          52U  /*!< DMAMUX1 TIM8 CH4 request  */
+#define DMA_REQUEST_TIM8_UP           53U  /*!< DMAMUX1 TIM8 UP  request  */
+#define DMA_REQUEST_TIM8_TRIG         54U  /*!< DMAMUX1 TIM8 TRIG request */
+#define DMA_REQUEST_TIM8_COM          55U  /*!< DMAMUX1 TIM8 COM request  */
+
+#define DMA_REQUEST_TIM2_CH1          56U  /*!< DMAMUX1 TIM2 CH1 request  */
+#define DMA_REQUEST_TIM2_CH2          57U  /*!< DMAMUX1 TIM2 CH2 request  */
+#define DMA_REQUEST_TIM2_CH3          58U  /*!< DMAMUX1 TIM2 CH3 request  */
+#define DMA_REQUEST_TIM2_CH4          59U  /*!< DMAMUX1 TIM2 CH4 request  */
+#define DMA_REQUEST_TIM2_UP           60U  /*!< DMAMUX1 TIM2 UP  request  */
+
+#define DMA_REQUEST_TIM3_CH1          61U  /*!< DMAMUX1 TIM3 CH1 request  */
+#define DMA_REQUEST_TIM3_CH2          62U  /*!< DMAMUX1 TIM3 CH2 request  */
+#define DMA_REQUEST_TIM3_CH3          63U  /*!< DMAMUX1 TIM3 CH3 request  */
+#define DMA_REQUEST_TIM3_CH4          64U  /*!< DMAMUX1 TIM3 CH4 request  */
+#define DMA_REQUEST_TIM3_UP           65U  /*!< DMAMUX1 TIM3 UP  request  */
+#define DMA_REQUEST_TIM3_TRIG         66U  /*!< DMAMUX1 TIM3 TRIG request */
+
+#define DMA_REQUEST_TIM4_CH1          67U  /*!< DMAMUX1 TIM4 CH1 request  */
+#define DMA_REQUEST_TIM4_CH2          68U  /*!< DMAMUX1 TIM4 CH2 request  */
+#define DMA_REQUEST_TIM4_CH3          69U  /*!< DMAMUX1 TIM4 CH3 request  */
+#define DMA_REQUEST_TIM4_CH4          70U  /*!< DMAMUX1 TIM4 CH4 request  */
+#define DMA_REQUEST_TIM4_UP           71U  /*!< DMAMUX1 TIM4 UP  request  */
+
+#define DMA_REQUEST_TIM5_CH1          72U  /*!< DMAMUX1 TIM5 CH1 request  */
+#define DMA_REQUEST_TIM5_CH2          73U  /*!< DMAMUX1 TIM5 CH2 request  */
+#define DMA_REQUEST_TIM5_CH3          74U  /*!< DMAMUX1 TIM5 CH3 request  */
+#define DMA_REQUEST_TIM5_CH4          75U  /*!< DMAMUX1 TIM5 CH4 request  */
+#define DMA_REQUEST_TIM5_UP           76U  /*!< DMAMUX1 TIM5 UP  request  */
+#define DMA_REQUEST_TIM5_TRIG         77U  /*!< DMAMUX1 TIM5 TRIG request */
+
+#define DMA_REQUEST_TIM15_CH1         78U  /*!< DMAMUX1 TIM15 CH1 request */
+#define DMA_REQUEST_TIM15_UP          79U  /*!< DMAMUX1 TIM15 UP  request */
+#define DMA_REQUEST_TIM15_TRIG        80U  /*!< DMAMUX1 TIM15 TRIG request */
+#define DMA_REQUEST_TIM15_COM         81U  /*!< DMAMUX1 TIM15 COM request */
+
+#define DMA_REQUEST_TIM16_CH1         82U  /*!< DMAMUX1 TIM16 CH1 request */
+#define DMA_REQUEST_TIM16_UP          83U  /*!< DMAMUX1 TIM16 UP  request */
+#define DMA_REQUEST_TIM17_CH1         84U  /*!< DMAMUX1 TIM17 CH1 request */
+#define DMA_REQUEST_TIM17_UP          85U  /*!< DMAMUX1 TIM17 UP  request */
+
+#define DMA_REQUEST_DFSDM1_FLT0       86U  /*!< DMAMUX1 DFSDM1 Filter0 request */
+#define DMA_REQUEST_DFSDM1_FLT1       87U  /*!< DMAMUX1 DFSDM1 Filter1 request */
+#define DMA_REQUEST_DFSDM1_FLT2       88U  /*!< DMAMUX1 DFSDM1 Filter2 request */
+#define DMA_REQUEST_DFSDM1_FLT3       89U  /*!< DMAMUX1 DFSDM1 Filter3 request */
+
+#define DMA_REQUEST_AES_IN            90U  /*!< DMAMUX1 AES IN request    */
+#define DMA_REQUEST_AES_OUT           91U  /*!< DMAMUX1 AES OUT request   */
+
+#define DMA_REQUEST_HASH_IN           92U  /*!< DMAMUX1 HASH IN request   */
+
+#define DMA_REQUEST_UCPD1_TX          93U  /*!< DMAMUX1 UCPD1 TX request   */
+#define DMA_REQUEST_UCPD1_RX          94U  /*!< DMAMUX1 UCPD1 RX request   */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          0x00000000U       /*!< Peripheral data alignment : Byte     */
+#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0   /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1   /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          0x00000000U       /*!< Memory data alignment : Byte     */
+#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0   /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1   /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL                   0x00000000U                /*!< Normal mode                                    */
+#define DMA_CIRCULAR                 DMA_CCR_CIRC               /*!< Circular mode                                  */
+#define DMA_DOUBLE_BUFFER_M0         DMA_CCR_DBM                /*!< Double buffer mode with first target memory M0 */
+#define DMA_DOUBLE_BUFFER_M1         (DMA_CCR_DBM | DMA_CCR_CT) /*!< Double buffer mode with first target memory M1 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW             0x00000000U     /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0    /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            DMA_CCR_PL_1    /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL      /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                         DMA_CCR_TCIE
+#define DMA_IT_HT                         DMA_CCR_HTIE
+#define DMA_IT_TE                         DMA_CCR_TEIE
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_GL1                      DMA_ISR_GIF1
+#define DMA_FLAG_TC1                      DMA_ISR_TCIF1
+#define DMA_FLAG_HT1                      DMA_ISR_HTIF1
+#define DMA_FLAG_TE1                      DMA_ISR_TEIF1
+#define DMA_FLAG_GL2                      DMA_ISR_GIF2
+#define DMA_FLAG_TC2                      DMA_ISR_TCIF2
+#define DMA_FLAG_HT2                      DMA_ISR_HTIF2
+#define DMA_FLAG_TE2                      DMA_ISR_TEIF2
+#define DMA_FLAG_GL3                      DMA_ISR_GIF3
+#define DMA_FLAG_TC3                      DMA_ISR_TCIF3
+#define DMA_FLAG_HT3                      DMA_ISR_HTIF3
+#define DMA_FLAG_TE3                      DMA_ISR_TEIF3
+#define DMA_FLAG_GL4                      DMA_ISR_GIF4
+#define DMA_FLAG_TC4                      DMA_ISR_TCIF4
+#define DMA_FLAG_HT4                      DMA_ISR_HTIF4
+#define DMA_FLAG_TE4                      DMA_ISR_TEIF4
+#define DMA_FLAG_GL5                      DMA_ISR_GIF5
+#define DMA_FLAG_TC5                      DMA_ISR_TCIF5
+#define DMA_FLAG_HT5                      DMA_ISR_HTIF5
+#define DMA_FLAG_TE5                      DMA_ISR_TEIF5
+#define DMA_FLAG_GL6                      DMA_ISR_GIF6
+#define DMA_FLAG_TC6                      DMA_ISR_TCIF6
+#define DMA_FLAG_HT6                      DMA_ISR_HTIF6
+#define DMA_FLAG_TE6                      DMA_ISR_TEIF6
+#define DMA_FLAG_GL7                      DMA_ISR_GIF7
+#define DMA_FLAG_TC7                      DMA_ISR_TCIF7
+#define DMA_FLAG_HT7                      DMA_ISR_HTIF7
+#define DMA_FLAG_TE7                      DMA_ISR_TEIF7
+#define DMA_FLAG_GL8                      DMA_ISR_GIF8
+#define DMA_FLAG_TC8                      DMA_ISR_TCIF8
+#define DMA_FLAG_HT8                      DMA_ISR_HTIF8
+#define DMA_FLAG_TE8                      DMA_ISR_TEIF8
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
+  * @brief DMA channel secure or non-secure and privileged or non-privileged attributes
+  * @note Secure and non-secure attributes are only available from secure when the system
+  *       implements the security (TZEN=1)
+  * @{
+  */
+
+#define DMA_CHANNEL_ATTR_PRIV_MASK         (DMA_CCR_PRIV >> 16U)
+#define DMA_CHANNEL_ATTR_SEC_MASK          (DMA_CCR_SECM >> 16U)
+#define DMA_CHANNEL_ATTR_SEC_SRC_MASK      (DMA_CCR_SSEC >> 16U)
+#define DMA_CHANNEL_ATTR_SEC_DEST_MASK     (DMA_CCR_DSEC >> 16U)
+
+#define DMA_CHANNEL_PRIV          (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV)     /*!< Channel is privileged             */
+#define DMA_CHANNEL_NPRIV         (DMA_CHANNEL_ATTR_PRIV_MASK)                    /*!< Channel is unprivileged           */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define DMA_CHANNEL_SEC           (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM)      /*!< Channel is secure                 */
+#define DMA_CHANNEL_NSEC          (DMA_CHANNEL_ATTR_SEC_MASK)                     /*!< Channel is non-secure             */
+#define DMA_CHANNEL_SRC_SEC       (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC)  /*!< Channel source is secure          */
+#define DMA_CHANNEL_SRC_NSEC      (DMA_CHANNEL_ATTR_SEC_SRC_MASK)                 /*!< Channel source is non-secure      */
+#define DMA_CHANNEL_DEST_SEC      (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure     */
+#define DMA_CHANNEL_DEST_NSEC     (DMA_CHANNEL_ATTR_SEC_DEST_MASK)                /*!< Channel destination is non-secure */
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
+   DMA_FLAG_TC8)
+
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
+   DMA_FLAG_HT8)
+
+/**
+  * @brief  Return the current DMA Channel transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
+   DMA_FLAG_TE8)
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
+   DMA_ISR_GIF8)
+
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be from 1 to 8 to select the DMA Channel x flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be from 1 to 8 to select the DMA Channel x flag.
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
+ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__ DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+  * @}
+  */
+
+/* Include DMA HAL Extension module */
+#include "stm32l5xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group4
+  * @{
+  */
+/* DMA Attributes functions ********************************************/
+HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes);
+HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_UCPD1_RX)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR) || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M0) || \
+                           ((MODE) == DMA_DOUBLE_BUFFER_M1))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U))
+#else
+#define IS_DMA_ATTRIBUTES(ATTRIBUTE)    (((ATTRIBUTE) == DMA_CHANNEL_PRIV)     || \
+                                         ((ATTRIBUTE) == DMA_CHANNEL_NPRIV))
+#endif
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dma_ex.h

@@ -0,0 +1,286 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_DMA_EX_H
+#define STM32L5xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL DMA Memory definition
+  */
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U,    /*!< Memory 1     */
+
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @brief  HAL DMA Synchro definition
+  */
+
+
+/**
+  * @brief  HAL DMAMUX Synchronization configuration structure definition
+  */
+typedef struct
+{
+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
+
+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
+
+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled
+                                    This parameter can take the value ENABLE or DISABLE*/
+
+
+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+                                       This parameter can take the value ENABLE or DISABLE */
+
+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
+                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+
+
+}HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+  * @brief  HAL DMAMUX request generator parameters structure definition
+  */
+typedef struct
+{
+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator
+                              This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
+
+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.
+                             This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
+
+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
+
+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
+  * @{
+  */
+
+/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
+  * @{
+  */
+#define HAL_DMAMUX1_SYNC_EXTI0                0U           /*!<  Synchronization Signal is EXTI0  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI1                1U           /*!<  Synchronization Signal is EXTI1  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI2                2U           /*!<  Synchronization Signal is EXTI2  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI3                3U           /*!<  Synchronization Signal is EXTI3  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI4                4U           /*!<  Synchronization Signal is EXTI4  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI5                5U           /*!<  Synchronization Signal is EXTI5  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI6                6U           /*!<  Synchronization Signal is EXTI6  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI7                7U           /*!<  Synchronization Signal is EXTI7  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI8                8U           /*!<  Synchronization Signal is EXTI8  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI9                9U           /*!<  Synchronization Signal is EXTI9  IT   */
+#define HAL_DMAMUX1_SYNC_EXTI10              10U           /*!<  Synchronization Signal is EXTI10 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI11              11U           /*!<  Synchronization Signal is EXTI11 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI12              12U           /*!<  Synchronization Signal is EXTI12 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI13              13U           /*!<  Synchronization Signal is EXTI13 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI14              14U           /*!<  Synchronization Signal is EXTI14 IT   */
+#define HAL_DMAMUX1_SYNC_EXTI15              15U           /*!<  Synchronization Signal is EXTI15 IT   */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT     16U           /*!<  Synchronization Signal is DMAMUX1 Channel0 Event  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT     17U           /*!<  Synchronization Signal is DMAMUX1 Channel1 Event  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT     18U           /*!<  Synchronization Signal is DMAMUX1 Channel2 Event  */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT     19U           /*!<  Synchronization Signal is DMAMUX1 Channel3 Event  */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT          20U           /*!<  Synchronization Signal is LPTIM1 OUT */
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT          21U           /*!<  Synchronization Signal is LPTIM2 OUT */
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT          22U           /*!<  Synchronization Signal is LPTIM3 OUT */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_SYNC_NO_EVENT                               0U    /*!< block synchronization events        */
+#define HAL_DMAMUX_SYNC_RISING                 DMAMUX_CxCR_SPOL_0    /*!< synchronize with rising edge events */
+#define HAL_DMAMUX_SYNC_FALLING                DMAMUX_CxCR_SPOL_1    /*!< synchronize with falling edge events */
+#define HAL_DMAMUX_SYNC_RISING_FALLING         DMAMUX_CxCR_SPOL      /*!< synchronize with rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
+  * @{
+  */
+
+#define HAL_DMAMUX1_REQ_GEN_EXTI0                0U        /*!< Request generator Signal is EXTI0 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI1                1U        /*!< Request generator Signal is EXTI1 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI2                2U        /*!< Request generator Signal is EXTI2 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI3                3U        /*!< Request generator Signal is EXTI3 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI4                4U        /*!< Request generator Signal is EXTI4 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI5                5U        /*!< Request generator Signal is EXTI5 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI6                6U        /*!< Request generator Signal is EXTI6 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI7                7U        /*!< Request generator Signal is EXTI7 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI8                8U        /*!< Request generator Signal is EXTI8 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI9                9U        /*!< Request generator Signal is EXTI9 IT    */
+#define HAL_DMAMUX1_REQ_GEN_EXTI10              10U        /*!< Request generator Signal is EXTI10 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI11              11U        /*!< Request generator Signal is EXTI11 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI12              12U        /*!< Request generator Signal is EXTI12 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI13              13U        /*!< Request generator Signal is EXTI13 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI14              14U        /*!< Request generator Signal is EXTI14 IT   */
+#define HAL_DMAMUX1_REQ_GEN_EXTI15              15U        /*!< Request generator Signal is EXTI15 IT   */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT     16U        /*!< Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT     17U        /*!< Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT     18U        /*!< Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT     19U        /*!< Request generator Signal is DMAMUX1 Channel3 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT          20U        /*!< Request generator Signal is LPTIM1 OUT  */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT          21U        /*!< Request generator Signal is LPTIM2 OUT  */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT          22U        /*!< Request generator Signal is LPTIM3 OUT  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
+  * @{
+  */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT       0U                     /*!< block request generator events        */
+#define HAL_DMAMUX_REQ_GEN_RISING         DMAMUX_RGxCR_GPOL_0    /*!< generate request on rising edge events */
+#define HAL_DMAMUX_REQ_GEN_FALLING        DMAMUX_RGxCR_GPOL_1    /*!< generate request on falling edge events */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL      /*!< generate request on rising and falling edge events */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  * @{
+  */
+/* ------------------------- Double Buffering --------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/* ------------------------- REQUEST -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
+             HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
+/* -------------------------------------------------------------------------- */
+
+/* ------------------------- SYNCHRO -----------------------------------------*/
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+/* -------------------------------------------------------------------------- */
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
+  * @brief    DMAEx private macros
+  * @{
+  */
+
+#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM3_OUT)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \
+                                     ((EVENT) == ENABLE))
+
+#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)   || \
+                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
+                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
+                                               ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_DMA_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_exti.h

@@ -0,0 +1,369 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_EXTI_H
+#define STM32L5xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U,
+  HAL_EXTI_RISING_CB_ID          = 0x01U,
+  HAL_EXTI_FALLING_CB_ID         = 0x02U,
+}EXTI_CallbackIDTypeDef;
+
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* RisingCallback) (void);   /*!<  Exti rising callback */
+  void (* FallingCallback) (void);  /*!<  Exti falling callback */
+}EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+}EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_REG1 | 0x00U)
+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_REG1 | 0x01U)
+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_REG1 | 0x02U)
+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_REG1 | 0x03U)
+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_REG1 | 0x04U)
+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_REG1 | 0x05U)
+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_REG1 | 0x06U)
+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_REG1 | 0x07U)
+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_REG1 | 0x08U)
+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_REG1 | 0x09U)
+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_REG1 | 0x0AU)
+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_REG1 | 0x0BU)
+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_REG1 | 0x0CU)
+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_REG1 | 0x0DU)
+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_REG1 | 0x0EU)
+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_REG1 | 0x0FU)
+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_REG1 | 0x10U)
+#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_REG1 | 0x11U)
+#define EXTI_LINE_18                        (EXTI_DIRECT   | EXTI_REG1 | 0x12U)
+#define EXTI_LINE_19                        (EXTI_DIRECT   | EXTI_REG1 | 0x13U)
+#define EXTI_LINE_20                        (EXTI_DIRECT   | EXTI_REG1 | 0x14U)
+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_REG1 | 0x15U)
+#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_REG1 | 0x16U)
+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_REG1 | 0x17U)
+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_REG1 | 0x18U)
+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_REG1 | 0x19U)
+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_REG1 | 0x1AU)
+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_REG1 | 0x1BU)
+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_REG1 | 0x1CU)
+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_REG1 | 0x1DU)
+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_REG1 | 0x1EU)
+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_REG1 | 0x1FU)
+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_REG2 | 0x00U)
+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_REG2 | 0x01U)
+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_REG2 | 0x02U)
+#define EXTI_LINE_35                        (EXTI_CONFIG   | EXTI_REG2 | 0x03U)
+#define EXTI_LINE_36                        (EXTI_CONFIG   | EXTI_REG2 | 0x04U)
+#define EXTI_LINE_37                        (EXTI_CONFIG   | EXTI_REG2 | 0x05U)
+#define EXTI_LINE_38                        (EXTI_CONFIG   | EXTI_REG2 | 0x06U)
+#define EXTI_LINE_39                        (EXTI_RESERVED | EXTI_REG2 | 0x07U)
+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_REG2 | 0x08U)
+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_REG2 | 0x09U)
+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_REG2 | 0x0AU)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000U
+#define EXTI_MODE_INTERRUPT                 0x00000001U
+#define EXTI_MODE_EVENT                     0x00000002U
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_NONE                   0x00000000U
+#define EXTI_TRIGGER_RISING                 0x00000001U
+#define EXTI_TRIGGER_FALLING                0x00000002U
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000U
+#define EXTI_GPIOB                          0x00000001U
+#define EXTI_GPIOC                          0x00000002U
+#define EXTI_GPIOD                          0x00000003U
+#define EXTI_GPIOE                          0x00000004U
+#define EXTI_GPIOF                          0x00000005U
+#define EXTI_GPIOG                          0x00000006U
+#define EXTI_GPIOH                          0x00000007U
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Line_attributes EXTI line attributes
+  * @brief EXTI line secure or non-secure and privileged or non-privileged attributes
+  * @note secure and non-secure attributes are only available from secure state when the system
+  *       implement the security (TZEN=1)
+  * @{
+  */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define  EXTI_LINE_SEC                      (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U)   /*!< Secure line attribute          */
+#define  EXTI_LINE_NSEC                     (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U)   /*!< Non-secure line attribute      */
+#endif /* __ARM_FEATURE_CMSE */
+#define  EXTI_LINE_PRIV                     (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U)   /*!< Privileged line attribute      */
+#define  EXTI_LINE_NPRIV                    (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U)   /*!< Non-privileged line attribute  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                  24U
+#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI Register and bit usage
+  */
+#define EXTI_REG_SHIFT                      16U
+#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)
+#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
+#define EXTI_PIN_MASK                       0x0000001FU
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#define EXTI_LINE_NB                        43UL
+
+/**
+  * @brief  EXTI Mask for secure & privilege attributes
+  */
+#define EXTI_LINE_ATTR_SEC_MASK             0x100U
+#define EXTI_LINE_ATTR_PRIV_MASK            0x200U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
+                                        ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
+                                         (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))))
+
+#define IS_EXTI_MODE(__LINE__)          ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \
+                                         (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U))
+
+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \
+                                         ((__LINE__) == EXTI_TRIGGER_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00U)
+
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \
+                                                 (((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \
+                                                 (((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
+                                                 (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
+                                                 (((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
+
+#else
+
+#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
+                                                 (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
+                                                 (((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
+
+#endif /* __ARM_FEATURE_CMSE */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
+ * @{
+ */
+
+/* EXTI line attributes management functions **********************************/
+void              HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_flash_ex.h

@@ -0,0 +1,203 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_FLASH_EX_H
+#define STM32L5xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Extended Private Constants
+  * @{
+  */
+#define FLASH_BLOCKBASED_NB_REG (4U) /*!< Number of block-based registers available */
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Block-based security structure definition
+  */
+typedef struct
+{
+  uint32_t Bank;                                        /*!< Configuration of the associated bank of Block-based Secure Area.
+                                                            This parameter must be a value of @ref FLASH_Banks */
+  uint32_t BBAttributesType;                            /*!< Block-Based Attributes type.
+                                                             This parameter must be a value of @ref FLASHEx_BB_Attributes */     
+  uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration of a page.
+                                                             0 means non-secure, 1 means secure */
+} FLASH_BBAttributesTypeDef;
+/**
+  * @}
+  */
+#endif
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASH Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_PRIV_MODE_CFG FLASH privilege mode configuration
+  * @{
+  */
+#define FLASH_PRIV_GRANTED   0x00000000U          /*!< access to Flash registers is granted */
+#define FLASH_PRIV_DENIED    FLASH_PRIVCFGR_PRIV /*!< access to Flash registers is denied to non-privilege access */
+/**
+  * @}
+  */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/** @defgroup FLASHEx_SEC_INVERSION_CFG FLASH security inversion configuration
+  * @{
+  */
+#define FLASH_INV_DISABLE    0x00000000U        /*!< Security state of Flash is not inverted */
+#define FLASH_INV_ENABLE     FLASH_SECCR_SECINV /*!< Security state of Flash is inverted */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup FLASHEx_LVE_PIN_CFG FLASH LVE pin configuration
+  * @{
+  */
+#define FLASH_LVE_PIN_CTRL   0x00000000U       /*!< LVEA/B FLASH pin controlled by power controller */
+#define FLASH_LVE_PIN_FORCED FLASH_ACR_LVEN    /*!< LVEA/B FLASH pin enforced to low */
+/**
+  * @}
+  */
+
+/** @defgroup FLASHEx_BB_Attributes FLASH Block-Based Attributes
+  * @{
+  */
+#define FLASH_BB_SEC         0x00000001U       /*!< Flash Block-Based Security Attributes */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/* Extended Program operation functions  *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
+void              HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes);
+void              HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks);
+#endif
+/**
+  * @}
+  */
+
+/* Extended Peripheral Control functions  ************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group2
+  * @{
+  */
+void              HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode);
+uint32_t          HAL_FLASHEx_GetPrivMode(void);
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState);
+uint32_t          HAL_FLASHEx_GetSecInversion(void);
+#endif
+HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE);
+uint32_t          HAL_FLASHEx_GetLVEPin(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks);
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Extended Private Macros
+ *  @{
+ */
+#define IS_FLASH_CFGPRIVMODE(CFG)          (((CFG) == FLASH_PRIV_GRANTED) || \
+                                            ((CFG) == FLASH_PRIV_DENIED))
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define IS_FLASH_CFGSECINV(CFG)            (((CFG) == FLASH_INV_DISABLE) || \
+                                            ((CFG) == FLASH_INV_ENABLE))
+#endif
+
+#define IS_FLASH_CFGLVEPIN(CFG)            (((CFG) == FLASH_LVE_PIN_CTRL) || \
+                                            ((CFG) == FLASH_LVE_PIN_FORCED))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

platform/vendor_bsp/st/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_flash_ramfunc.h

@@ -0,0 +1,75 @@
+/**
+  ******************************************************************************
+  * @file    stm32l5xx_hal_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L5xx_HAL_FLASH_RAMFUNC_H
+#define STM32L5xx_HAL_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l5xx_hal_def.h"
+
+/** @addtogroup STM32L5xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L5xx_HAL_FLASH_RAMFUNC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/