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reduce one instruction when switch to irq stack

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This commit is contained in:
acevest
2019-10-06 23:32:09 +08:00
parent 93ae1c96ca
commit ae3ada8dfe
4 changed files with 29 additions and 27 deletions
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20
arch/risc-v/bumblebee/gcc/riscv_port.h
View File

@@ -25,16 +25,16 @@
#define CLINT_MTIME 0x0000
// the bumblebee mstatus register is different
// name bit detail
// INTERRUPT 31 0: exception or nmi, 1 irq
// MINHV 30 reading irq vector table
// MPP 29:28 == mstatus.MPP
// MPIE 27 == mstatus.MPIE
// Reserved 26:24 0
// MPIL 23:16 previous interrupt level
// Reserved 15:12 0
// EXCCODE 11:0 exception code
#define SOC_MCAUSE_EXP_MASK 0x00000FFF
// name bit detail
// INTERRUPT 31 0: exception or nmi, 1 irq
// MINHV 30 reading irq vector table
// MPP 29:28 == mstatus.MPP
// MPIE 27 == mstatus.MPIE
// Reserved 26:24 0
// MPIL 23:16 previous interrupt level
// Reserved 15:12 0
// EXCCODE 11:0 exception code
#define MCAUSE_EXP_CODE_MASK 0x00000FFF
#ifndef __ASSEMBLER__
void port_cpu_init();

29
arch/risc-v/common/tos_cpu.c
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@@ -7,7 +7,7 @@
#endif
k_stack_t k_irq_stk[TOS_CFG_IRQ_STK_SIZE];
const k_stack_t *k_irq_stk_top = (k_stack_t *) ((char *)(k_irq_stk + TOS_CFG_IRQ_STK_SIZE) - sizeof(cpu_data_t));
k_stack_t *k_irq_stk_top = k_irq_stk + TOS_CFG_IRQ_STK_SIZE;
__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
{
@@ -16,6 +16,12 @@ __KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
}
__KERNEL__ void cpu_init(void) {
// reserve storage space for sp registers
k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) - sizeof(cpu_data_t));
k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) & 0xFFFFFFFC);
k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second;
cpu_systick_init(k_cpu_cycle_per_tick);
@@ -97,27 +103,26 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
cpu_context_t *regs = 0;
sp = (cpu_data_t *)&stk_base[stk_size];
sp = (cpu_data_t *)((cpu_addr_t)(sp) & 0xFFFFFFF8);
sp = (cpu_data_t *)((cpu_addr_t)(sp) & 0xFFFFFFFC);
sp -= (sizeof(cpu_context_t)/sizeof(cpu_data_t));
regs = (cpu_context_t*) sp;
for(int i=0; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i++) {
#define _V(v) ((unsigned int)((v/10) << 4 | (v % 10)))
*(sp + i) = (_V(i) << 24) | (_V(i) << 16) | (_V(i) << 8) | _V(i);
#undef _V
for(int i=1; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i+=2) {
// every task begin with "Tencent"
*(sp + i - 1) = 0x0054656E;
*(sp + i - 0) = 0x63656E74;
}
cpu_data_t gp = 0;
__ASM__ __VOLATILE__ ("mv %0, gp":"=r"(gp));
regs->gp = (cpu_data_t)gp; // gp: global pointer
regs->a0 = (cpu_data_t)arg; // a0: argument
regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address
regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt
regs->mepc = (cpu_data_t)entry;
regs->gp = (cpu_data_t)gp; // global pointer
regs->a0 = (cpu_data_t)arg; // argument
regs->ra = (cpu_data_t)0xACE00ACE; // return address
regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt
regs->epc = (cpu_data_t)entry; // task entry
return (k_stack_t*)sp;
}

5
arch/risc-v/rv32i/gcc/port_s.S
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@@ -226,7 +226,6 @@ port_context_switch:
sw x30, __reg_x30_OFFSET(sp)
sw x31, __reg_x31_OFFSET(sp)
sw ra, __reg_mepc_OFFSET(sp)
csrr t0, mstatus
@@ -324,12 +323,10 @@ rv32_exception_entry:
mv t0, sp
la t1, k_irq_stk_top
lw sp, (t1)
andi sp, sp, 0xFFFFFFF0
sw t0, (sp)
// get irq num and call irq handler
li t0, SOC_MCAUSE_EXP_MASK
li t0, MCAUSE_EXP_CODE_MASK
csrr a0, mcause
and a0, a0, t0
call cpu_irq_entry

2
arch/risc-v/spike/gcc/riscv_port.h
View File

@@ -23,7 +23,7 @@
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIME 0xBFF8
#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
#define MCAUSE_EXP_CODE_MASK 0x7FFFFFFF
#ifndef __ASSEMBLER__
void port_cpu_init();