reduce one instruction when switch to irq stack
This commit is contained in:
@@ -34,7 +34,7 @@
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// MPIL 23:16 previous interrupt level
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// MPIL 23:16 previous interrupt level
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// Reserved 15:12 0
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// Reserved 15:12 0
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// EXCCODE 11:0 exception code
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// EXCCODE 11:0 exception code
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#define SOC_MCAUSE_EXP_MASK 0x00000FFF
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#define MCAUSE_EXP_CODE_MASK 0x00000FFF
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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void port_cpu_init();
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void port_cpu_init();
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@@ -7,7 +7,7 @@
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#endif
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#endif
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k_stack_t k_irq_stk[TOS_CFG_IRQ_STK_SIZE];
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k_stack_t k_irq_stk[TOS_CFG_IRQ_STK_SIZE];
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const k_stack_t *k_irq_stk_top = (k_stack_t *) ((char *)(k_irq_stk + TOS_CFG_IRQ_STK_SIZE) - sizeof(cpu_data_t));
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k_stack_t *k_irq_stk_top = k_irq_stk + TOS_CFG_IRQ_STK_SIZE;
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__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
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__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
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{
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{
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@@ -16,6 +16,12 @@ __KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick)
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}
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}
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__KERNEL__ void cpu_init(void) {
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__KERNEL__ void cpu_init(void) {
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// reserve storage space for sp registers
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k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) - sizeof(cpu_data_t));
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k_irq_stk_top = (k_stack_t *)(((cpu_addr_t) k_irq_stk_top) & 0xFFFFFFFC);
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k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second;
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k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second;
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cpu_systick_init(k_cpu_cycle_per_tick);
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cpu_systick_init(k_cpu_cycle_per_tick);
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@@ -97,27 +103,26 @@ __KERNEL__ k_stack_t *cpu_task_stk_init(void *entry,
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cpu_context_t *regs = 0;
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cpu_context_t *regs = 0;
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sp = (cpu_data_t *)&stk_base[stk_size];
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sp = (cpu_data_t *)&stk_base[stk_size];
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sp = (cpu_data_t *)((cpu_addr_t)(sp) & 0xFFFFFFF8);
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sp = (cpu_data_t *)((cpu_addr_t)(sp) & 0xFFFFFFFC);
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sp -= (sizeof(cpu_context_t)/sizeof(cpu_data_t));
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sp -= (sizeof(cpu_context_t)/sizeof(cpu_data_t));
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regs = (cpu_context_t*) sp;
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regs = (cpu_context_t*) sp;
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for(int i=0; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i++) {
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for(int i=1; i<(sizeof(cpu_context_t)/sizeof(cpu_data_t)); i+=2) {
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#define _V(v) ((unsigned int)((v/10) << 4 | (v % 10)))
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// every task begin with "Tencent"
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*(sp + i) = (_V(i) << 24) | (_V(i) << 16) | (_V(i) << 8) | _V(i);
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*(sp + i - 1) = 0x0054656E;
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#undef _V
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*(sp + i - 0) = 0x63656E74;
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}
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}
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cpu_data_t gp = 0;
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cpu_data_t gp = 0;
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__ASM__ __VOLATILE__ ("mv %0, gp":"=r"(gp));
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__ASM__ __VOLATILE__ ("mv %0, gp":"=r"(gp));
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regs->gp = (cpu_data_t)gp; // gp: global pointer
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regs->gp = (cpu_data_t)gp; // global pointer
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regs->a0 = (cpu_data_t)arg; // a0: argument
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regs->a0 = (cpu_data_t)arg; // argument
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regs->ra = (cpu_data_t)0xACE00ACE; // ra: return address
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regs->ra = (cpu_data_t)0xACE00ACE; // return address
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regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt
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regs->mstatus = (cpu_data_t)0x00001880; // return to machine mode and enable interrupt
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regs->mepc = (cpu_data_t)entry;
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regs->epc = (cpu_data_t)entry; // task entry
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return (k_stack_t*)sp;
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return (k_stack_t*)sp;
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}
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}
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@@ -226,7 +226,6 @@ port_context_switch:
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sw x30, __reg_x30_OFFSET(sp)
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sw x30, __reg_x30_OFFSET(sp)
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sw x31, __reg_x31_OFFSET(sp)
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sw x31, __reg_x31_OFFSET(sp)
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sw ra, __reg_mepc_OFFSET(sp)
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sw ra, __reg_mepc_OFFSET(sp)
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csrr t0, mstatus
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csrr t0, mstatus
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@@ -324,12 +323,10 @@ rv32_exception_entry:
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mv t0, sp
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mv t0, sp
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la t1, k_irq_stk_top
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la t1, k_irq_stk_top
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lw sp, (t1)
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lw sp, (t1)
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andi sp, sp, 0xFFFFFFF0
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sw t0, (sp)
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sw t0, (sp)
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// get irq num and call irq handler
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// get irq num and call irq handler
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li t0, SOC_MCAUSE_EXP_MASK
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li t0, MCAUSE_EXP_CODE_MASK
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csrr a0, mcause
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csrr a0, mcause
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and a0, a0, t0
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and a0, a0, t0
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call cpu_irq_entry
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call cpu_irq_entry
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@@ -23,7 +23,7 @@
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#define CLINT_MTIMECMP 0x4000
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#define CLINT_MTIMECMP 0x4000
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#define CLINT_MTIME 0xBFF8
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#define CLINT_MTIME 0xBFF8
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#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
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#define MCAUSE_EXP_CODE_MASK 0x7FFFFFFF
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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void port_cpu_init();
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void port_cpu_init();
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