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port TencentOS tiny to RISC-V

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This commit is contained in:
acezhao
2019-09-13 00:45:38 +08:00
parent b95368685f
commit af245f2e5b
20 changed files with 3437 additions and 0 deletions
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72
arch/risc-v/rv32i/port.h Normal file
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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_H_
#define _PORT_H_
__PORT__ void port_int_disable(void);
__PORT__ void port_int_enable(void);
__PORT__ cpu_cpsr_t port_cpsr_save(void);
__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr);
__PORT__ void port_cpu_reset(void);
__PORT__ void port_sched_start(void) __NO_RETURN__;
__PORT__ void port_context_switch(void);
__PORT__ void port_irq_context_switch(void);
__PORT__ void port_systick_config(uint32_t cycle_per_tick);
__PORT__ void port_systick_priority_set(uint32_t prio);
#if TOS_CFG_TICKLESS_EN > 0u
__PORT__ void port_systick_resume(void);
__PORT__ void port_systick_suspend(void);
__PORT__ void port_systick_reload(uint32_t cycle_per_tick);
__PORT__ void port_systick_pending_reset(void);
__PORT__ k_time_t port_systick_max_delay_millisecond(void);
#endif
#if TOS_CFG_PWR_MGR_EN > 0u
__PORT__ void port_sleep_mode_enter(void);
__PORT__ void port_stop_mode_enter(void);
__PORT__ void port_standby_mode_enter(void);
#endif
#if TOS_CFG_FAULT_BACKTRACE_EN > 0u
__PORT__ void HardFault_Handler(void);
__PORT__ void port_fault_diagnosis(void);
#endif
#endif /* _PORT_H_ */

148
arch/risc-v/rv32i/port_c.c Normal file
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/*
* port_c.c
*
* Created on: Sep 9, 2019
* Author: ace
*/
#include "riscv_encoding.h"
#include <tos.h>
#define CLINT_CTRL_ADDR 0x2000000
#define CLINT_MSIP 0x0000
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIME 0xBFF8
static uint32_t mtime_lo(void)
{
return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME);
}
static uint32_t mtime_hi(void)
{
return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
}
uint64_t get_mtime_val()
{
while (1) {
uint32_t hi = mtime_hi();
uint32_t lo = mtime_lo();
uint32_t nhi = mtime_hi();
if (hi == nhi) {
return (((uint64_t)hi) << 32) | lo;
} {
uint32_t a = hi;
uint32_t b = nhi;
}
}
}
void set_mtimecmp_lo(uint32_t v)
{
*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP) = v;
}
void set_mtimecmp_hi(uint32_t v)
{
*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = v;
}
void set_mtimecmp_val(uint64_t v)
{
uint32_t hi = (v >> 32) & 0xFFFFFFFF;
uint32_t lo = (v >> 0) & 0xFFFFFFFF;
set_mtimecmp_lo(0xFFFFFFFF); // No smaller than old value.
set_mtimecmp_hi(hi); // No smaller than new value.
set_mtimecmp_lo(lo); // New value.
}
__PORT__ void port_systick_config(uint32_t cycle_per_tick)
{
#if 0
asm("csrc mie, %0"::"r"(MIP_MTIP));
#if 1
uint64_t mtime = get_mtime_val();
#else
static uint64_t last_mtime = 0;
if(last_mtime == 0) {
last_mtime = get_mtime_val();
}
uint64_t mtime = get_mtime_val();
if((mtime - last_mtime)/cycle_per_tick >= 4) {
mtime = last_mtime+2*cycle_per_tick;
}
last_mtime = mtime;
#endif
uint64_t mtimecmp;
do {
tick_inc();
mtimecmp = ((uint64_t)tos_get_tick())* cycle_per_tick;
} while(mtimecmp <= mtime);
set_mtimecmp_val(mtimecmp);
asm("csrs mie, %0"::"r"(MIP_MTIP));
#endif
#if 0
clear_csr(mie, MIP_MTIP);
static uint64_t then = 0;
volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
if(then != 0) {
//next timer irq is 1 second from previous
then += 1*cycle_per_tick;
} else{ //first time setting the timer
uint64_t now = *mtime;
then = now + 1*cycle_per_tick;
}
*mtimecmp = then;
set_csr(mie, MIP_MTIP);
#endif
//asm("csrc mie, %0"::"r"(MIP_MTIP));
#if 0
uint64_t next_tick = get_mtime_val();
next_tick += cycle_per_tick;
set_mtimecmp_val(next_tick);
#endif
#if 0
uint64_t new_tick = get_mtime_val() + cycle_per_tick;
uint64_t tick = 0;
if(new_tick - next_tick > 50000) {
tick = get_mtime_val() + cycle_per_tick;
}
next_tick = new_tick;
set_mtimecmp_val(next_tick);
#endif
#if 1
// this is illegal in ricsv-32
// it cost cpu read two times, first mtime_lo and then mtime_hi
// if mtime_lo == 0xFFFFFFFF and mtime_hi = 0 at first read
// then mtime_lo == 0 and mtime_hi = 1 at next read
// the result will be 0x1FFFFFFFF, not 0x100000000
//*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = 0xFFFFFFFF;
//*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = 0xFFFFFFFF;
uint64_t mtime = *(volatile uint64_t *)(CLINT_CTRL_ADDR + CLINT_MTIME);
mtime += cycle_per_tick;
*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 4) = (mtime >> 32) & 0xFFFFFFFF;
asm("csrc mip, %0"::"r"(MIP_MTIP));
*(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIMECMP + 0) = (mtime >> 0) & 0xFFFFFFFF;
//asm("csrc mip, %0"::"r"(MIP_MTIP));
#endif
//asm("csrs mie, %0"::"r"(MIP_MTIP));
}
__PORT__ void port_systick_priority_set(uint32_t prio)
{
//NVIC_SetPriority(SysTick_IRQn, prio);
}

27
arch/risc-v/rv32i/port_config.h Normal file
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/*----------------------------------------------------------------------------
* Tencent is pleased to support the open source community by making TencentOS
* available.
*
* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
* If you have downloaded a copy of the TencentOS binary from Tencent, please
* note that the TencentOS binary is licensed under the BSD 3-Clause License.
*
* If you have downloaded a copy of the TencentOS source code from Tencent,
* please note that TencentOS source code is licensed under the BSD 3-Clause
* License, except for the third-party components listed below which are
* subject to different license terms. Your integration of TencentOS into your
* own projects may require compliance with the BSD 3-Clause License, as well
* as the other licenses applicable to the third-party components included
* within TencentOS.
*---------------------------------------------------------------------------*/
#ifndef _PORT_CONFIG_H_
#define _PORT_CONFIG_H_
#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32
#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING
#define TOS_CFG_CPU_HRTIMER_EN 0u
#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u
#endif /* _PORT_CONFIG_H_ */

407
arch/risc-v/rv32i/port_s.S Normal file
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.global port_int_disable
.global port_int_enable
.global port_cpsr_save
.global port_cpsr_restore
.global port_sched_start
.global port_context_switch
.global port_irq_context_switch
#include "riscv_encoding.h"
.text
.align 2
.type port_int_disable, %function
port_int_disable:
csrci mstatus, MSTATUS_MIE
ret
.type port_int_enable, %function
port_int_enable:
csrsi mstatus, MSTATUS_MIE
ret
.type port_cpsr_save, %function
port_cpsr_save:
csrrci a0, mstatus, MSTATUS_MIE
#csrrci a0, mstatus, MSTATUS_MPIE
ret
.type port_cpsr_restore, %function
port_cpsr_restore:
csrw mstatus, a0
ret
#define REGBYTES 4
#define LOAD lw
#define STORE sw
.extern k_curr_task
.type port_sched_start, %function
port_sched_start:
// enable timer interrupt
li t0, MIE_MTIE
csrs mie, t0
la t0, k_curr_task // t0 = &k_curr_task
LOAD t0, (t0) // t0 = &(k_curr_task->sp)
LOAD sp, (t0) // k_curr_task->sp = sp
// save sp
addi t1, sp, 32*REGBYTES
STORE t1, (t0)
LOAD t0, 0*REGBYTES(sp)
csrw mepc, t0
LOAD t0, 1*REGBYTES(sp)
csrw mstatus, t0
LOAD x1, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
.align 2
.global machine_trap_entry
machine_trap_entry:
addi sp, sp, -32*REGBYTES
STORE x1, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
#if 1
//li t0, MSTATUS_MPP | MSTATUS_MPIE // acutally MPIE is not need
csrr t0, mstatus
STORE t0, 1*REGBYTES(sp)
csrr t0, mepc // just save information for handler
STORE t0, 0*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
LOAD t1, (t0)
STORE sp, (t1)
csrr a0, mcause
mv a1, sp
bltz a0, irq
call cpu_trap_entry
j restore
irq:
slli a0, a0, 1
srli a0, a0, 1
call cpu_irq_entry
restore:
LOAD t0, 0*REGBYTES(sp)
csrw mepc, t0
LOAD t0, 1*REGBYTES(sp)
csrw mstatus, t0
#else
// for debug timer interrupt only
csrr a0, mcause
slli a0, a0, 1
srli a0, a0, 1
call cpu_irq_entry
#endif
LOAD x1, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
.align 2
.type port_context_switch, %function
port_context_switch:
nop
nop
addi sp, sp, -32*REGBYTES
STORE x1, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
li t0, MSTATUS_MPP // force use machine mode
csrr t1, mstatus
and t1, t1, MSTATUS_MIE
beqz t1, save_mstatus
or t0, t0, MSTATUS_MPIE
save_mstatus:
STORE t0, 1*REGBYTES(sp)
la t0, port_context_switch_return // just save information for handler
STORE t0, 0*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
LOAD t1, (t0)
STORE sp, (t1)
// k_curr_task = k_next_task
la t1, k_next_task // t1 = &k_next_task
LOAD t1, (t1) // t1 = k_next_task
STORE t1, (t0)
// load sp from k_next_task.sp
LOAD sp, (t1)
LOAD t0, 0*REGBYTES(sp)
csrw mepc, t0
LOAD t0, 1*REGBYTES(sp)
csrw mstatus, t0
LOAD x1, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
.align 2
port_context_switch_return:
ret
.align 2
.type port_irq_context_switch, %function
port_irq_context_switch:
addi sp, sp, -32*REGBYTES
STORE x1, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
li t0, MSTATUS_MPP
STORE t0, 1*REGBYTES(sp)
la t0, irq_context_return
STORE t0, 0*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
LOAD t1, (t0)
STORE sp, (t1)
// k_curr_task = k_next_task
la t1, k_next_task // t1 = &k_next_task
LOAD t1, (t1) // t1 = k_next_task
STORE t1, (t0)
// load sp from k_next_task.sp
LOAD sp, (t1)
LOAD t0, 1*REGBYTES(sp)
csrw mstatus, t0
LOAD t0, 0*REGBYTES(sp)
csrw mepc, t0
LOAD x1, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
irq_context_return:
ret

209
arch/risc-v/rv32i/start.S Normal file
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// See LICENSE for license details.
#include "riscv_encoding.h"
.section .text.entry
.globl _start
.type _start,@function
_start:
csrc mstatus, MSTATUS_MIE
csrw mie, 0
la t0, machine_trap_entry
csrw mtvec, t0
#if 1
// before kernel run, the stack is unused
// so just borrow to use
la t0, k_idle_task_stk_addr
lw t1, k_idle_task_stk_size
add sp, t0, t1
#else
// uncomment in link.ld
la sp, _stack_top
#endif
/* Load data section */
la a0, _load_data
la a1, _data
la a2, _edata
bgeu a1, a2, begin_clear_bss
clear_data:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, clear_data
begin_clear_bss:
// clear bss section
la a0, _bss
la a1, _ebss
bgeu a0, a1, init_finish
clear_bss:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, clear_bss
init_finish:
call main
__die:
j __die
.section .text
.weak eclic_msip_handler
.weak eclic_mtip_handler
.weak SysTick_IRQHandler
.weak eclic_bwei_handler
.weak eclic_pmovi_handler
.weak WWDGT_IRQHandler
.weak LVD_IRQHandler
.weak TAMPER_IRQHandler
.weak RTC_IRQHandler
.weak FMC_IRQHandler
.weak RCU_IRQHandler
.weak EXTI0_IRQHandler
.weak EXTI1_IRQHandler
.weak EXTI2_IRQHandler
.weak EXTI3_IRQHandler
.weak EXTI4_IRQHandler
.weak DMA0_Channel0_IRQHandler
.weak DMA0_Channel1_IRQHandler
.weak DMA0_Channel2_IRQHandler
.weak DMA0_Channel3_IRQHandler
.weak DMA0_Channel4_IRQHandler
.weak DMA0_Channel5_IRQHandler
.weak DMA0_Channel6_IRQHandler
.weak ADC0_1_IRQHandler
.weak CAN0_TX_IRQHandler
.weak CAN0_RX0_IRQHandler
.weak CAN0_RX1_IRQHandler
.weak CAN0_EWMC_IRQHandler
.weak EXTI5_9_IRQHandler
.weak TIMER0_BRK_IRQHandler
.weak TIMER0_UP_IRQHandler
.weak TIMER0_TRG_CMT_IRQHandler
.weak TIMER0_Channel_IRQHandler
.weak TIMER1_IRQHandler
.weak TIMER2_IRQHandler
.weak TIMER3_IRQHandler
.weak I2C0_EV_IRQHandler
.weak I2C0_ER_IRQHandler
.weak I2C1_EV_IRQHandler
.weak I2C1_ER_IRQHandler
.weak SPI0_IRQHandler
.weak SPI1_IRQHandler
.weak USART0_IRQHandler
.weak USART1_IRQHandler
.weak USART2_IRQHandler
.weak EXTI10_15_IRQHandler
.weak RTC_Alarm_IRQHandler
.weak USBFS_WKUP_IRQHandler
.weak EXMC_IRQHandler
.weak TIMER4_IRQHandler
.weak SPI2_IRQHandler
.weak UART3_IRQHandler
.weak UART4_IRQHandler
.weak TIMER5_IRQHandler
.weak TIMER6_IRQHandler
.weak DMA1_Channel0_IRQHandler
.weak DMA1_Channel1_IRQHandler
.weak DMA1_Channel2_IRQHandler
.weak DMA1_Channel3_IRQHandler
.weak DMA1_Channel4_IRQHandler
.weak CAN1_TX_IRQHandler
.weak CAN1_RX0_IRQHandler
.weak CAN1_RX1_IRQHandler
.weak CAN1_EWMC_IRQHandler
.weak USBFS_IRQHandler
.global handler_vector_table
.align 2
handler_vector_table:
.word 0
.word 0
.word 0
.word eclic_msip_handler
.word 0
.word 0
.word 0
.word SysTick_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word eclic_bwei_handler
.word eclic_pmovi_handler
.word WWDGT_IRQHandler
.word LVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FMC_IRQHandler
.word RCU_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA0_Channel0_IRQHandler
.word DMA0_Channel1_IRQHandler
.word DMA0_Channel2_IRQHandler
.word DMA0_Channel3_IRQHandler
.word DMA0_Channel4_IRQHandler
.word DMA0_Channel5_IRQHandler
.word DMA0_Channel6_IRQHandler
.word ADC0_1_IRQHandler
.word CAN0_TX_IRQHandler
.word CAN0_RX0_IRQHandler
.word CAN0_RX1_IRQHandler
.word CAN0_EWMC_IRQHandler
.word EXTI5_9_IRQHandler
.word TIMER0_BRK_IRQHandler
.word TIMER0_UP_IRQHandler
.word TIMER0_TRG_CMT_IRQHandler
.word TIMER0_Channel_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word TIMER3_IRQHandler
.word I2C0_EV_IRQHandler
.word I2C0_ER_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word SPI0_IRQHandler
.word SPI1_IRQHandler
.word USART0_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word EXTI10_15_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBFS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word EXMC_IRQHandler
.word 0
.word TIMER4_IRQHandler
.word SPI2_IRQHandler
.word UART3_IRQHandler
.word UART4_IRQHandler
.word TIMER5_IRQHandler
.word TIMER6_IRQHandler
.word DMA1_Channel0_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word 0
.word 0
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_EWMC_IRQHandler
.word USBFS_IRQHandler