Merge pull request #35 from acevest/master
reduce two instructions in risc-v irq handler
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@@ -1,3 +1,20 @@
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/*----------------------------------------------------------------------------
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* Tencent is pleased to support the open source community by making TencentOS
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* available.
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*
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* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
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* If you have downloaded a copy of the TencentOS binary from Tencent, please
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* note that the TencentOS binary is licensed under the BSD 3-Clause License.
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*
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* If you have downloaded a copy of the TencentOS source code from Tencent,
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* please note that TencentOS source code is licensed under the BSD 3-Clause
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* License, except for the third-party components listed below which are
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* subject to different license terms. Your integration of TencentOS into your
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* own projects may require compliance with the BSD 3-Clause License, as well
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* as the other licenses applicable to the third-party components included
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* within TencentOS.
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*---------------------------------------------------------------------------*/
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.global irq_entry
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.global trap_entry
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@@ -1,3 +1,20 @@
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/*----------------------------------------------------------------------------
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* Tencent is pleased to support the open source community by making TencentOS
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* available.
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*
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* Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved.
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* If you have downloaded a copy of the TencentOS binary from Tencent, please
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* note that the TencentOS binary is licensed under the BSD 3-Clause License.
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*
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* If you have downloaded a copy of the TencentOS source code from Tencent,
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* please note that TencentOS source code is licensed under the BSD 3-Clause
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* License, except for the third-party components listed below which are
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* subject to different license terms. Your integration of TencentOS into your
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* own projects may require compliance with the BSD 3-Clause License, as well
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* as the other licenses applicable to the third-party components included
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* within TencentOS.
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*---------------------------------------------------------------------------*/
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#include "riscv_port.h"
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.global port_int_disable
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@@ -142,8 +159,7 @@ port_sched_start:
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csrs mie, t0
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// load sp from k_curr_task->sp
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la t0, k_curr_task // t0 = &k_curr_task
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lw t0, (t0) // t0 = &(k_curr_task->sp)
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lw t0, k_curr_task
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lw sp, (t0) // sp = k_curr_task->sp
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j restore_context
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@@ -280,10 +296,10 @@ rv32_exception_entry:
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csrr t0, mstatus
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sw t0, __reg_mstatus__OFFSET(sp)
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// switch to irq stack
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mv t0, sp
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la t1, k_irq_stk_top
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lw sp, (t1)
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// switch to irq stack
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lw sp, k_irq_stk_top
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// save task stack pointer
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sw t0, (sp)
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// get irq num and call irq handler
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@@ -293,8 +309,7 @@ rv32_exception_entry:
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call cpu_irq_entry
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// switch back to task stack
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lw t0, (sp)
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mv sp, t0
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lw sp, (sp)
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la t0, k_curr_task
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la t1, k_next_task
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