Add NUCLEO_STM32F446RE BSP
This commit is contained in:
niannianyouyu
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// File: STM32F446.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F446xx reference manual (RM0390)
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// refer to STM32F446xx datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// <o.1> DBG_STOP <i> Debug Stop Mode
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// <o.0> DBG_SLEEP <i> Debug Sleep Mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
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// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
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// <o.24> DBG_I2CFMP_SMBUS_TIMEOUT <i> I2CFMP SMBUS timeout mode stopped when core is halted
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// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
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// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
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// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
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// <i> TRACECLK: Pin PE2
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// <o1> TRACED0
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// <i> ETM Trace Data 0
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// <0x00040003=> Pin PE3
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// <0x00020008=> Pin PC8
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// <o2> TRACED1
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// <i> ETM Trace Data 1
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// <0x00040004=> Pin PE4
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// <0x00030003=> Pin PD3
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// <o3> TRACED2
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// <i> ETM Trace Data 2
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// <0x00040005=> Pin PE5
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// <0x0006000D=> Pin PG13
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// <o4> TRACED3
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// <i> ETM Trace Data 3
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// <0x00040006=> Pin PE6
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// <0x0006000E=> Pin PG14
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// </h>
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TraceClk_Pin = 0x00040002;
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TraceD0_Pin = 0x00040003;
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TraceD1_Pin = 0x00040004;
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TraceD2_Pin = 0x00040005;
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TraceD3_Pin = 0x00040006;
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// <<< end of configuration section >>>
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@@ -0,0 +1,73 @@
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// File: STM32F446.dbgconf
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// Version: 1.0.0
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// Note: refer to STM32F446xx reference manual (RM0390)
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// refer to STM32F446xx datasheets
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU configuration register (DBGMCU_CR)
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// <o.2> DBG_STANDBY <i> Debug Standby Mode
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// <o.1> DBG_STOP <i> Debug Stop Mode
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// <o.0> DBG_SLEEP <i> Debug Sleep Mode
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// </h>
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DbgMCU_CR = 0x00000007;
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// <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
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// <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
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// <o.24> DBG_I2CFMP_SMBUS_TIMEOUT <i> I2CFMP SMBUS timeout mode stopped when core is halted
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// <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
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// <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
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// <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
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// <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
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// <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
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// <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
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// <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
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// <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
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// <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
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// <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
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// <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
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// <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
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// <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
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// <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
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// <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
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// </h>
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DbgMCU_APB1_Fz = 0x00000000;
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// <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
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// <i> Reserved bits must be kept at reset value
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// <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
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// <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
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// <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
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// <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
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// <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
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// </h>
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DbgMCU_APB2_Fz = 0x00000000;
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// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
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// <i> TRACECLK: Pin PE2
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// <o1> TRACED0
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// <i> ETM Trace Data 0
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// <0x00040003=> Pin PE3
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// <0x00020008=> Pin PC8
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// <o2> TRACED1
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// <i> ETM Trace Data 1
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// <0x00040004=> Pin PE4
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// <0x00030003=> Pin PD3
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// <o3> TRACED2
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// <i> ETM Trace Data 2
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// <0x00040005=> Pin PE5
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// <0x0006000D=> Pin PG13
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// <o4> TRACED3
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// <i> ETM Trace Data 3
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// <0x00040006=> Pin PE6
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// <0x0006000E=> Pin PG14
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// </h>
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TraceClk_Pin = 0x00040002;
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TraceD0_Pin = 0x00040003;
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TraceD1_Pin = 0x00040004;
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TraceD2_Pin = 0x00040005;
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TraceD3_Pin = 0x00040006;
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// <<< end of configuration section >>>
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1860
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvguix.luc
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1860
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvguix.luc
Normal file
File diff suppressed because one or more lines are too long
892
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvoptx
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892
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvoptx
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@@ -0,0 +1,892 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
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<SchemaVersion>1.0</SchemaVersion>
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<Header>### uVision Project, (C) Keil Software</Header>
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<Extensions>
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<cExt>*.c</cExt>
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<aExt>*.s*; *.src; *.a*</aExt>
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<oExt>*.obj; *.o</oExt>
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<lExt>*.lib</lExt>
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<tExt>*.txt; *.h; *.inc</tExt>
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<pExt>*.plm</pExt>
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<CppX>*.cpp</CppX>
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<nMigrate>0</nMigrate>
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</Extensions>
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<DaveTm>
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<dwLowDateTime>0</dwLowDateTime>
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<dwHighDateTime>0</dwHighDateTime>
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</DaveTm>
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<Target>
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<TargetName>NUCLEO_STM32F446RE</TargetName>
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<ToolsetNumber>0x4</ToolsetNumber>
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<ToolsetName>ARM-ADS</ToolsetName>
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<TargetOption>
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<CLKADS>32000000</CLKADS>
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<OPTTT>
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<gFlags>1</gFlags>
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<BeepAtEnd>1</BeepAtEnd>
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<RunSim>0</RunSim>
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<RunTarget>1</RunTarget>
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<RunAbUc>0</RunAbUc>
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</OPTTT>
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<OPTHX>
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<HexSelection>1</HexSelection>
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<FlashByte>65535</FlashByte>
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<HexRangeLowAddress>0</HexRangeLowAddress>
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<HexRangeHighAddress>0</HexRangeHighAddress>
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<HexOffset>0</HexOffset>
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</OPTHX>
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<OPTLEX>
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<PageWidth>79</PageWidth>
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<PageLength>66</PageLength>
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<TabStop>8</TabStop>
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<ListingPath></ListingPath>
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</OPTLEX>
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<ListingPage>
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<CreateCListing>1</CreateCListing>
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<CreateAListing>1</CreateAListing>
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<CreateLListing>1</CreateLListing>
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<CreateIListing>0</CreateIListing>
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<AsmCond>1</AsmCond>
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<AsmSymb>1</AsmSymb>
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<AsmXref>0</AsmXref>
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<CCond>1</CCond>
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<CCode>0</CCode>
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<CListInc>0</CListInc>
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<CSymb>0</CSymb>
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<LinkerCodeListing>0</LinkerCodeListing>
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</ListingPage>
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<OPTXL>
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<LMap>1</LMap>
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<LComments>1</LComments>
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<LGenerateSymbols>1</LGenerateSymbols>
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<LLibSym>1</LLibSym>
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<LLines>1</LLines>
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<LLocSym>1</LLocSym>
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<LPubSym>1</LPubSym>
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<LXref>0</LXref>
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<LExpSel>0</LExpSel>
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</OPTXL>
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<OPTFL>
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<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<IsCurrentTarget>1</IsCurrentTarget>
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</OPTFL>
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<CpuCode>18</CpuCode>
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<DebugOpt>
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<uSim>0</uSim>
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<uTrg>1</uTrg>
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<sLdApp>1</sLdApp>
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<sGomain>1</sGomain>
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<sRbreak>1</sRbreak>
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<sRwatch>1</sRwatch>
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<sRmem>1</sRmem>
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<sRfunc>1</sRfunc>
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<sRbox>1</sRbox>
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<tLdApp>1</tLdApp>
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<tGomain>1</tGomain>
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<tRbreak>1</tRbreak>
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<tRwatch>1</tRwatch>
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<tRmem>1</tRmem>
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<tRfunc>1</tRfunc>
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<tRbox>1</tRbox>
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<tRtrace>1</tRtrace>
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<sRSysVw>1</sRSysVw>
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<tRSysVw>1</tRSysVw>
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<sRunDeb>0</sRunDeb>
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<sLrtime>0</sLrtime>
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<bEvRecOn>1</bEvRecOn>
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<bSchkAxf>0</bSchkAxf>
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<bTchkAxf>0</bTchkAxf>
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<nTsel>6</nTsel>
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<sDll></sDll>
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<sDllPa></sDllPa>
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<sDlgDll></sDlgDll>
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<sDlgPa></sDlgPa>
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<sIfile></sIfile>
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<tDll></tDll>
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<tDllPa></tDllPa>
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<tDlgDll></tDlgDll>
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<tDlgPa></tDlgPa>
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<tIfile></tIfile>
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<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
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</DebugOpt>
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<TargetDriverDllRegistry>
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<SetRegEntry>
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<Number>0</Number>
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<Key>UL2CM3</Key>
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<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F446RETx$CMSIS\Flash\STM32F4xx_512.FLM))</Name>
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</SetRegEntry>
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<SetRegEntry>
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<Number>0</Number>
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<Key>ST-LINKIII-KEIL_SWO</Key>
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<Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F446RETx$CMSIS\Flash\STM32F4xx_512.FLM)</Name>
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</SetRegEntry>
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</TargetDriverDllRegistry>
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<Breakpoint/>
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<Tracepoint>
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<THDelay>0</THDelay>
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</Tracepoint>
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<DebugFlag>
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<trace>0</trace>
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||||
<periodic>1</periodic>
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||||
<aLwin>0</aLwin>
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||||
<aCover>0</aCover>
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||||
<aSer1>0</aSer1>
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<aSer2>0</aSer2>
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||||
<aPa>0</aPa>
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||||
<viewmode>0</viewmode>
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||||
<vrSel>0</vrSel>
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||||
<aSym>0</aSym>
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||||
<aTbox>0</aTbox>
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||||
<AscS1>0</AscS1>
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||||
<AscS2>0</AscS2>
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||||
<AscS3>0</AscS3>
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||||
<aSer3>0</aSer3>
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||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
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||||
<aPa1>0</aPa1>
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||||
<AscS4>0</AscS4>
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||||
<aSer4>0</aSer4>
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||||
<StkLoc>0</StkLoc>
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||||
<TrcWin>0</TrcWin>
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||||
<newCpu>0</newCpu>
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||||
<uProt>0</uProt>
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||||
</DebugFlag>
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||||
<LintExecutable></LintExecutable>
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||||
<LintConfigFile></LintConfigFile>
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||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
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||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>1</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Application/MDK-ARM</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>startup_stm32f446xx.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_stm32f446xx.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Application/User</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>../Src/main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
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|
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<tvExp>0</tvExp>
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<tvExp>0</tvExp>
|
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<tvExpOptDlg>0</tvExpOptDlg>
|
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<bDave2>0</bDave2>
|
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<PathWithFileName>..\..\..\kernel\core\tos_mmblk.c</PathWithFileName>
|
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<FilenameWithoutPath>tos_mmblk.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
|
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<bShared>0</bShared>
|
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</File>
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<File>
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|
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<FileType>1</FileType>
|
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<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
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<bDave2>0</bDave2>
|
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<PathWithFileName>..\..\..\kernel\core\tos_mmheap.c</PathWithFileName>
|
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<FilenameWithoutPath>tos_mmheap.c</FilenameWithoutPath>
|
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<RteFlg>0</RteFlg>
|
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<bShared>0</bShared>
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<File>
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<GroupNumber>6</GroupNumber>
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<FileNumber>38</FileNumber>
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<FileType>1</FileType>
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<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
|
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<bDave2>0</bDave2>
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<PathWithFileName>..\..\..\kernel\core\tos_mutex.c</PathWithFileName>
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<RteFlg>0</RteFlg>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bDave2>0</bDave2>
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<FilenameWithoutPath>tos_pend.c</FilenameWithoutPath>
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<RteFlg>0</RteFlg>
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<File>
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<tvExp>0</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<bDave2>0</bDave2>
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<PathWithFileName>..\..\..\kernel\core\tos_priority_mail_queue.c</PathWithFileName>
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<FilenameWithoutPath>tos_tick.c</FilenameWithoutPath>
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<tvExpOptDlg>0</tvExpOptDlg>
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<FilenameWithoutPath>tos_time.c</FilenameWithoutPath>
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<RteFlg>0</RteFlg>
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<bShared>0</bShared>
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</Group>
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|
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<Group>
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<GroupName>tos/cmsis_os</GroupName>
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<tvExp>0</tvExp>
|
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<tvExpOptDlg>0</tvExpOptDlg>
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</Group>
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|
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<Group>
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<GroupName>TOS_CONFIG</GroupName>
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<tvExp>1</tvExp>
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<tvExpOptDlg>0</tvExpOptDlg>
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<Group>
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<GroupName>::CMSIS</GroupName>
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|
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707
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvprojx
Normal file
707
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE.uvprojx
Normal file
@@ -0,0 +1,707 @@
|
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
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<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
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|
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<SchemaVersion>2.1</SchemaVersion>
|
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|
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<Header>### uVision Project, (C) Keil Software</Header>
|
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|
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<Targets>
|
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<Target>
|
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<TargetName>NUCLEO_STM32F446RE</TargetName>
|
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<ToolsetNumber>0x4</ToolsetNumber>
|
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<ToolsetName>ARM-ADS</ToolsetName>
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<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
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<uAC6>0</uAC6>
|
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<TargetOption>
|
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<TargetCommonOption>
|
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<Device>STM32F446RETx</Device>
|
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<Vendor>STMicroelectronics</Vendor>
|
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<PackID>Keil.STM32F4xx_DFP.2.14.0</PackID>
|
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<PackURL>http://www.keil.com/pack/</PackURL>
|
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<Cpu>IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x807FFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4")</Cpu>
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<FlashUtilSpec></FlashUtilSpec>
|
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<StartupFile></StartupFile>
|
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<FlashDriverDll></FlashDriverDll>
|
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<DeviceId></DeviceId>
|
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<RegisterFile></RegisterFile>
|
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<MemoryEnv></MemoryEnv>
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<Cmp></Cmp>
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<Asm></Asm>
|
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<Linker></Linker>
|
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<OHString></OHString>
|
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<InfinionOptionDll></InfinionOptionDll>
|
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<SLE66CMisc></SLE66CMisc>
|
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<SLE66AMisc></SLE66AMisc>
|
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<SLE66LinkerMisc></SLE66LinkerMisc>
|
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<SFDFile>$$Device:STM32F446RETx$CMSIS\SVD\STM32F446x.svd</SFDFile>
|
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<bCustSvd>0</bCustSvd>
|
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<UseEnv>0</UseEnv>
|
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<BinPath></BinPath>
|
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<IncludePath></IncludePath>
|
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<LibPath></LibPath>
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<RegisterFilePath></RegisterFilePath>
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<DBRegisterFilePath></DBRegisterFilePath>
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<TargetStatus>
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<Error>0</Error>
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<ExitCodeStop>0</ExitCodeStop>
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<ButtonStop>0</ButtonStop>
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<NotGenerated>0</NotGenerated>
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<InvalidFlash>1</InvalidFlash>
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</TargetStatus>
|
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<OutputDirectory>tencentos\</OutputDirectory>
|
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<OutputName>NUCLEO_STM32F446RE</OutputName>
|
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<CreateExecutable>1</CreateExecutable>
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<CreateLib>0</CreateLib>
|
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<CreateHexFile>1</CreateHexFile>
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<DebugInformation>1</DebugInformation>
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<BrowseInformation>1</BrowseInformation>
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<ListingPath></ListingPath>
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<HexFormatSelection>1</HexFormatSelection>
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<Merge32K>0</Merge32K>
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<CreateBatchFile>0</CreateBatchFile>
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<BeforeCompile>
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<RunUserProg1>0</RunUserProg1>
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<RunUserProg2>0</RunUserProg2>
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<UserProg1Name></UserProg1Name>
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<UserProg2Name></UserProg2Name>
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<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
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<nStopU1X>0</nStopU1X>
|
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<nStopU2X>0</nStopU2X>
|
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</BeforeCompile>
|
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<BeforeMake>
|
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<RunUserProg1>0</RunUserProg1>
|
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<RunUserProg2>0</RunUserProg2>
|
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<UserProg1Name></UserProg1Name>
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<UserProg2Name></UserProg2Name>
|
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<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
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<nStopB1X>0</nStopB1X>
|
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<nStopB2X>0</nStopB2X>
|
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</BeforeMake>
|
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<AfterMake>
|
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<RunUserProg1>0</RunUserProg1>
|
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<RunUserProg2>0</RunUserProg2>
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<UserProg1Name></UserProg1Name>
|
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<UserProg2Name></UserProg2Name>
|
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<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
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<nStopA1X>0</nStopA1X>
|
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<nStopA2X>0</nStopA2X>
|
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</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
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<SVCSIdString></SVCSIdString>
|
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</TargetCommonOption>
|
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<CommonProperty>
|
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<UseCPPCompiler>0</UseCPPCompiler>
|
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<RVCTCodeConst>0</RVCTCodeConst>
|
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<RVCTZI>0</RVCTZI>
|
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<RVCTOtherData>0</RVCTOtherData>
|
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<ModuleSelection>0</ModuleSelection>
|
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<IncludeInBuild>1</IncludeInBuild>
|
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<AlwaysBuild>0</AlwaysBuild>
|
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<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
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<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>0</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments>-REMAP -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments>-MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
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<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
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<HexRangeLowAddress>0</HexRangeLowAddress>
|
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<HexRangeHighAddress>0</HexRangeHighAddress>
|
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<HexOffset>0</HexOffset>
|
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<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4101</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USE_HAL_DRIVER,STM32F446xx</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>../Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../../../arch/arm/arm-v7m/common/include;../../../arch/arm/arm-v7m/cortex-m4/armcc;../../../kernel/core/include;../../../kernel/pm/include;../../../osal/cmsis_os;../TOS_CONFIG</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Application/MDK-ARM</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_stm32f446xx.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>startup_stm32f446xx.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Application/User</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>sys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/sys.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_it.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/stm32f4xx_it.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_msp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/stm32f4xx_hal_msp.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Drivers/STM32F4xx_HAL_Driver</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_tim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_tim_ex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_uart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_rcc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_rcc_ex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_flash_ex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_flash_ramfunc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_dma_ex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_dma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_pwr.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_pwr_ex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_cortex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f4xx_hal_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Drivers/CMSIS</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_stm32f4xx.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Src/system_stm32f4xx.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/arch</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_cpu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\arch\arm\arm-v7m\common\tos_cpu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_s.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_binary_heap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_binary_heap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_char_fifo.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_char_fifo.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_completion.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_countdownlatch.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_event.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_event.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_global.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_global.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmblk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_mmblk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmheap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_mmheap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_mutex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_pend.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_pend.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_priority_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_ring_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_ring_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_robin.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_robin.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sched.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_sched.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_sem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_sys.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_task.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_task.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_tick.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_tick.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_time.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_time.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\kernel\core\tos_timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/cmsis_os</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>cmsis_os.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\osal\cmsis_os\cmsis_os.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>TOS_CONFIG</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_config.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\tos_config.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.3.0" condition="CMSIS Core">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.5.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="NUCLEO_STM32F446RE"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,111 @@
|
||||
<html>
|
||||
<body>
|
||||
<pre>
|
||||
<h1><EFBFBD>Vision Build Log</h1>
|
||||
<h2>Tool Versions:</h2>
|
||||
IDE-Version: <20><>Vision V5.28.0.0
|
||||
Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
|
||||
License Information: 1 luc, 1, LIC=UJWSB-2J7NB-JJ66S-LG5T2-3DTAU-TCK43
|
||||
|
||||
Tool Versions:
|
||||
Toolchain: MDK-ARM Plus Version: 5.28.0.0
|
||||
Toolchain Path: E:\Keil_v5\ARM\ARMCC\Bin
|
||||
C Compiler: Armcc.exe V5.06 update 6 (build 750)
|
||||
Assembler: Armasm.exe V5.06 update 6 (build 750)
|
||||
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
|
||||
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
|
||||
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
|
||||
CPU DLL: SARMCM3.DLL V5.28.0.0
|
||||
Dialog DLL: DCM.DLL V1.17.3.0
|
||||
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.6.0
|
||||
Dialog DLL: TCM.DLL V1.36.2.0
|
||||
|
||||
<h2>Project:</h2>
|
||||
G:\TencentOS\test1\board\STM32F446RE\MDK-ARM\tencentos.uvprojx
|
||||
Project File Date: 02/09/2020
|
||||
|
||||
<h2>Output:</h2>
|
||||
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'E:\Keil_v5\ARM\ARMCC\Bin'
|
||||
Build target 'NUCLEO_STM32F446RE'
|
||||
assembling startup_stm32f446xx.s...
|
||||
compiling sys.c...
|
||||
compiling gpio.c...
|
||||
compiling main.c...
|
||||
compiling stm32f4xx_hal_msp.c...
|
||||
compiling usart.c...
|
||||
compiling stm32f4xx_it.c...
|
||||
compiling stm32f4xx_hal_tim.c...
|
||||
compiling stm32f4xx_hal_tim_ex.c...
|
||||
compiling stm32f4xx_hal_uart.c...
|
||||
compiling stm32f4xx_hal_flash.c...
|
||||
compiling stm32f4xx_hal_rcc.c...
|
||||
compiling stm32f4xx_hal_rcc_ex.c...
|
||||
compiling stm32f4xx_hal_flash_ramfunc.c...
|
||||
compiling stm32f4xx_hal_flash_ex.c...
|
||||
compiling stm32f4xx_hal_gpio.c...
|
||||
compiling stm32f4xx_hal_pwr.c...
|
||||
compiling stm32f4xx_hal_dma.c...
|
||||
compiling stm32f4xx_hal_dma_ex.c...
|
||||
compiling stm32f4xx_hal.c...
|
||||
compiling stm32f4xx_hal_cortex.c...
|
||||
compiling stm32f4xx_hal_pwr_ex.c...
|
||||
compiling system_stm32f4xx.c...
|
||||
compiling stm32f4xx_hal_exti.c...
|
||||
assembling port_s.S...
|
||||
compiling tos_cpu.c...
|
||||
compiling port_c.c...
|
||||
compiling tos_binary_heap.c...
|
||||
compiling tos_char_fifo.c...
|
||||
compiling tos_completion.c...
|
||||
compiling tos_countdownlatch.c...
|
||||
compiling tos_event.c...
|
||||
compiling tos_global.c...
|
||||
compiling tos_message_queue.c...
|
||||
compiling tos_mail_queue.c...
|
||||
compiling tos_mmblk.c...
|
||||
compiling tos_mutex.c...
|
||||
compiling tos_mmheap.c...
|
||||
compiling tos_priority_message_queue.c...
|
||||
compiling tos_pend.c...
|
||||
compiling tos_priority_mail_queue.c...
|
||||
compiling tos_robin.c...
|
||||
compiling tos_priority_queue.c...
|
||||
compiling tos_ring_queue.c...
|
||||
compiling tos_sched.c...
|
||||
compiling tos_sem.c...
|
||||
compiling tos_sys.c...
|
||||
compiling tos_time.c...
|
||||
compiling tos_tick.c...
|
||||
compiling tos_task.c...
|
||||
compiling tos_timer.c...
|
||||
compiling cmsis_os.c...
|
||||
linking...
|
||||
Program Size: Code=9852 RO-data=596 RW-data=100 ZI-data=6092
|
||||
FromELF: creating hex file...
|
||||
"tencentos\NUCLEO_STM32F446RE.axf" - 0 Error(s), 0 Warning(s).
|
||||
|
||||
<h2>Software Packages used:</h2>
|
||||
|
||||
Package Vendor: ARM
|
||||
http://www.keil.com/pack/ARM.CMSIS.5.5.1.pack
|
||||
ARM.CMSIS.5.5.1
|
||||
CMSIS (Cortex Microcontroller Software Interface Standard)
|
||||
* Component: CORE Version: 5.2.0
|
||||
|
||||
Package Vendor: Keil
|
||||
http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.14.0.pack
|
||||
Keil.STM32F4xx_DFP.2.14.0
|
||||
STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
|
||||
|
||||
<h2>Collection of Component include folders:</h2>
|
||||
.\RTE\_NUCLEO_STM32F446RE
|
||||
E:\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include
|
||||
E:\Arm\Packs\Keil\STM32F4xx_DFP\2.14.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
|
||||
|
||||
<h2>Collection of Component Files used:</h2>
|
||||
|
||||
* Component: ARM::CMSIS:CORE:5.2.0
|
||||
Build Time Elapsed: 00:03:13
|
||||
</pre>
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
1696
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.htm
Normal file
1696
board/NUCLEO_STM32F446RE/KEIL/NUCLEO_STM32F446RE/tencentos.htm
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
828
board/NUCLEO_STM32F446RE/KEIL/Nu_Link_Driver.ini
Normal file
828
board/NUCLEO_STM32F446RE/KEIL/Nu_Link_Driver.ini
Normal file
@@ -0,0 +1,828 @@
|
||||
[Version]
|
||||
Nu_LinkVersion=V5.6
|
||||
[Process]
|
||||
ProcessID=0x00000000
|
||||
ProcessCreationTime_L=0x00000000
|
||||
ProcessCreationTime_H=0x00000000
|
||||
NuLinkID=0x00000000
|
||||
[ChipSelect]
|
||||
;ChipName=<NUC1xx|NUC2xx|M05x|N571|N572|Nano100|N512|Mini51|NUC505|General>
|
||||
ChipName=NUC1xx
|
||||
[NUC505]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=NUC505_SPIFLASH.FLM
|
||||
[NUC4xx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=NUC400_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x014fb180
|
||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[NUC2xx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NUC200_AP_128.FLM
|
||||
[NUC126]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=NUC126_AP_256.FLM
|
||||
[NUC121]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NUC121_AP_32.FLM
|
||||
[NUC1xx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NUC100_AP_128.FLM
|
||||
[NUC029]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NUC029_AP_16.FLM
|
||||
[NM1820]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NM1820_AP_17_5.FLM
|
||||
[NM1810]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NM1810_AP_29_5.FLM
|
||||
[NM1500]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NM1500_AP_128.FLM
|
||||
[NM1330]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NM1330_AP_64.FLM
|
||||
[NM1320]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NM1320_AP_32.FLM
|
||||
[NM1230]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=NM1230_AP_64.FLM
|
||||
[NM1200]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NM1200_AP_8.FLM
|
||||
[NM1120]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NM1120_AP_29_5.FLM
|
||||
[TF5100]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=TF5100_AP_64.FLM
|
||||
[NDA102]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=NDA102_AP_29_5.FLM
|
||||
[Nano103]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=Nano103_AP_64.FLM
|
||||
[Nano100]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=Nano100_AP_64.FLM
|
||||
[N576]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=N576_AP_145.FLM
|
||||
[N575]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=N575_AP_145.FLM
|
||||
[N572]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=N572Fxxx.FLM
|
||||
[N571]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=N571E000.FLM
|
||||
[N570]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=N570_AP_64.FLM
|
||||
[N569]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=N569_AP_64.FLM
|
||||
[N512]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=N512_AP_64.FLM
|
||||
[Mini57]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=Mini57_AP_29_5.FLM
|
||||
[Mini51]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=Mini51_AP_16.FLM
|
||||
[M481]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M481_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x00b71b00
|
||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[M480LD]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M480LD_AP_256.FLM
|
||||
[M451]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M451_AP_256.FLM
|
||||
[M251]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=M251_AP_192.FLM
|
||||
[M2351]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=1
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M2351_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x00b71b00
|
||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[M261]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=1
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=M261_AP_512.FLM
|
||||
TraceConf0=0x00000002
|
||||
TraceConf1=0x00b71b00
|
||||
TraceConf2=0x00000800
|
||||
TraceConf3=0x00000000
|
||||
TraceConf4=0x00000001
|
||||
TraceConf5=0x00000000
|
||||
[M0564]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x2000
|
||||
ProgramAlgorithm=M0564_AP_256.FLM
|
||||
[M0519]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=M0519_AP_128.FLM
|
||||
[M0518]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=M0518_AP_64.FLM
|
||||
[M05x]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=M0516_AP_64.FLM
|
||||
[M031]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=1
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x800
|
||||
ProgramAlgorithm=M031_AP_128.FLM
|
||||
[NPCX]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=NPCX_AP_512.FLM
|
||||
[I94000]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=I94000_AP_512.FLM
|
||||
[ISD9300]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=ISD9300_AP_145.FLM
|
||||
[I9200]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=I9200_AP_128.FLM
|
||||
[ISD9xxx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=ISD9100_AP_145.FLM
|
||||
[ISD9000]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=ISD9000_AP_64.FLM
|
||||
[AU9xxx]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
FlashSelect=APROM
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableFlashBreakpoint=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x1000
|
||||
ProgramAlgorithm=AU9100_AP_145.FLM
|
||||
[General]
|
||||
Connect=0
|
||||
Reset=Autodetect
|
||||
MaxClock=1MHz
|
||||
MemoryVerify=0
|
||||
IOVoltage=3300
|
||||
Erase=1
|
||||
Program=1
|
||||
Verify=1
|
||||
ResetAndRun=0
|
||||
EnableLog=0
|
||||
MemAccessWhileRun=0
|
||||
RAMForAlgorithmStart=0x20000000
|
||||
RAMForAlgorithmSize=0x4000
|
||||
ProgramAlgorithm=
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'NUCLEO_STM32F446RE'
|
||||
* Target: 'NUCLEO_STM32F446RE'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
@@ -0,0 +1,21 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'NUCLEO_STM32F446RE'
|
||||
* Target: 'tencentos'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
|
||||
/*
|
||||
* Define the Device Header File:
|
||||
*/
|
||||
#define CMSIS_device_header "stm32f4xx.h"
|
||||
|
||||
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
460
board/NUCLEO_STM32F446RE/KEIL/startup_stm32f446xx.s
Normal file
460
board/NUCLEO_STM32F446RE/KEIL/startup_stm32f446xx.s
Normal file
@@ -0,0 +1,460 @@
|
||||
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f446xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32F446x devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SAI2_IRQHandler ; SAI2
|
||||
DCD QUADSPI_IRQHandler ; QuadSPI
|
||||
DCD CEC_IRQHandler ; CEC
|
||||
DCD SPDIF_RX_IRQHandler ; SPDIF RX
|
||||
DCD FMPI2C1_EV_IRQHandler ; FMPI2C Event
|
||||
DCD FMPI2C1_ER_IRQHandler ; FMPI2C Error
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT SAI2_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT SPDIF_RX_IRQHandler [WEAK]
|
||||
EXPORT FMPI2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT FMPI2C1_ER_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
FPU_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
SAI2_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
CEC_IRQHandler
|
||||
SPDIF_RX_IRQHandler
|
||||
FMPI2C1_EV_IRQHandler
|
||||
FMPI2C1_ER_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
@@ -0,0 +1,56 @@
|
||||
<html>
|
||||
<body>
|
||||
<pre>
|
||||
<h1><EFBFBD>Vision Build Log</h1>
|
||||
<h2>Tool Versions:</h2>
|
||||
IDE-Version: <20><>Vision V5.28.0.0
|
||||
Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
|
||||
License Information: 1 luc, 1, LIC=UJWSB-2J7NB-JJ66S-LG5T2-3DTAU-TCK43
|
||||
|
||||
Tool Versions:
|
||||
Toolchain: MDK-ARM Plus Version: 5.28.0.0
|
||||
Toolchain Path: E:\Keil_v5\ARM\ARMCC\Bin
|
||||
C Compiler: Armcc.exe V5.06 update 6 (build 750)
|
||||
Assembler: Armasm.exe V5.06 update 6 (build 750)
|
||||
Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
|
||||
Library Manager: ArmAr.exe V5.06 update 6 (build 750)
|
||||
Hex Converter: FromElf.exe V5.06 update 6 (build 750)
|
||||
CPU DLL: SARMCM3.DLL V5.28.0.0
|
||||
Dialog DLL: DCM.DLL V1.17.3.0
|
||||
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.6.0
|
||||
Dialog DLL: TCM.DLL V1.36.2.0
|
||||
|
||||
<h2>Project:</h2>
|
||||
G:\TencentOS\test1\board\STM32F446RE\MDK-ARM\NUCLEO_STM32F446RE.uvprojx
|
||||
Project File Date: 02/09/2020
|
||||
|
||||
<h2>Output:</h2>
|
||||
*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'E:\Keil_v5\ARM\ARMCC\Bin'
|
||||
Build target 'NUCLEO_STM32F446RE'
|
||||
"tencentos\NUCLEO_STM32F446RE.axf" - 0 Error(s), 0 Warning(s).
|
||||
|
||||
<h2>Software Packages used:</h2>
|
||||
|
||||
Package Vendor: ARM
|
||||
http://www.keil.com/pack/ARM.CMSIS.5.5.1.pack
|
||||
ARM.CMSIS.5.5.1
|
||||
CMSIS (Cortex Microcontroller Software Interface Standard)
|
||||
* Component: CORE Version: 5.2.0
|
||||
|
||||
Package Vendor: Keil
|
||||
http://www.keil.com/pack/Keil.STM32F4xx_DFP.2.14.0.pack
|
||||
Keil.STM32F4xx_DFP.2.14.0
|
||||
STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
|
||||
|
||||
<h2>Collection of Component include folders:</h2>
|
||||
.\RTE\_NUCLEO_STM32F446RE
|
||||
E:\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include
|
||||
E:\Arm\Packs\Keil\STM32F4xx_DFP\2.14.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include
|
||||
|
||||
<h2>Collection of Component Files used:</h2>
|
||||
|
||||
* Component: ARM::CMSIS:CORE:5.2.0
|
||||
Build Time Elapsed: 00:00:00
|
||||
</pre>
|
||||
</body>
|
||||
</html>
|
||||
1696
board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.htm
Normal file
1696
board/NUCLEO_STM32F446RE/KEIL/tencentos/NUCLEO_STM32F446RE.htm
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,16 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user