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1. Updated the BSP for i.MX RT1050

Browse Source 
2. Added the Keil Workspace
3. Changed the hello_world.c for RT1050

Signed-off-by: Howard Liu <howardliu7874@hotmail.com>
This commit is contained in:
Howard Liu
2020-01-18 19:35:05 +08:00
parent 91c470239d
commit d8f32035a1
1073 changed files with 103162 additions and 429588 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
board/NXP_EVKB_IMXRT1050/BSP/Inc/pin_mux.h
View File

@@ -52,7 +52,10 @@ void BOARD_InitBootPins(void);
#define BOARD_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
#define BOARD_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5]/USER_LED */
#define BOARD_USER_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_USER_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_USER_LED_PIN 9U /*!< GPIO1 pin index: 9 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*

47
board/NXP_EVKB_IMXRT1050/BSP/Src/hello_world.c
View File

@@ -16,7 +16,8 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#define EXAMPLE_LED_GPIO BOARD_USER_LED_GPIO
#define EXAMPLE_LED_GPIO_PIN BOARD_USER_LED_PIN
/*******************************************************************************
* Prototypes
@@ -33,29 +34,40 @@ osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
void task2(void *arg);
osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
void task1(void *arg)
{
int count = 0;
while(1)
{
PRINTF("********This is Task 1, count is %d \r\n",count++);
osDelay(1000);
}
/* The PIN status */
static volatile bool g_pinSet = false;
int count = 0;
while(1)
{
PRINTF("++++++++This is Task 1, count is %d \r\n",count++);
if (g_pinSet)
{
GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 0U);
g_pinSet = false;
}
else
{
GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U);
g_pinSet = true;
}
/* Delay 1000 ms */
osDelay(1000U);
}
}
void task2(void *arg)
{
int count = 0;
while(1)
{
PRINTF("++++++++This is Task 2, count is %d \r\n",count++);
osDelay(2000);
}
int count = 0;
while(1)
{
PRINTF("********This is Task 2, count is %d \r\n",count++);
osDelay(2000U);
}
}
/*!
* @brief Main function
*/
@@ -67,10 +79,11 @@ int main(void)
BOARD_InitBootClocks();
BOARD_InitDebugConsole();
PRINTF("hello world.\r\n");
PRINTF("Hello world from i.MX RT1050.\r\n");
PRINTF("Welcome to TencentOS tiny\r\n");
osKernelInitialize(); // TencentOS Tiny kernel initialize
osThreadCreate(osThread(task1), NULL); // Create task1
osThreadCreate(osThread(task2), NULL); // Create task2
osKernelStart(); // Start TencentOS Tiny
return 0;
}

25
board/NXP_EVKB_IMXRT1050/BSP/Src/pin_mux.c
View File

@@ -24,6 +24,7 @@ board: IMXRT1050-EVKB
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
@@ -83,6 +84,30 @@ void BOARD_InitPins(void) {
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
/* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
}
/***********************************************************************************************************************

72
platform/vendor_bsp/nxp/MIMXRT1052/xip/evkbimxrt1050_sdram_ini_dcd.h → board/NXP_EVKB_IMXRT1050/IAR/hello_world/evkbimxrt1050.mac
View File

@@ -1,11 +1,8 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -18,7 +15,6 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -31,17 +27,61 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__
#define __EVKBIMXRT1050_DCD_SDRAM_INIT__
_load_dcdc_trim()
{
__var ocotp_base;
__var ocotp_fuse_bank0_base;
__var dcdc_base;
__var reg;
__var trim_value;
__var dcdc_trim_loaded;
__var index;
#include <stdint.h>
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
dcdc_base = 0x40080000;
/*************************************
* DCD Data
*************************************/
#define DCD_TAG_HEADER (0xD2)
#define DCD_TAG_HEADER_SHIFT (24)
#define DCD_VERSION (0x40)
#define DCD_ARRAY_SIZE 1
dcdc_trim_loaded = 0;
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
dcdc_trim_loaded = 1;
}
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay 1ms for dcdc to get stable
__delay(1);
__message "DCDC trim value loaded.\n";
}
}
execUserPreload()
{
_load_dcdc_trim();
}
execUserReset()
{
_load_dcdc_trim();
}
#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */

261
board/NXP_EVKB_IMXRT1050/IAR/hello_world/evkbimxrt1050_sdram_init.mac Normal file
View File

@@ -0,0 +1,261 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
_load_dcdc_trim()
{
__var dcdc_trim_loaded;
__var ocotp_base;
__var ocotp_fuse_bank0_base;
__var dcdc_base;
__var reg;
__var trim_value;
__var index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
dcdc_trim_loaded = 1;
}
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay 1ms for dcdc to get stable
__delay(1);
__message "DCDC trim value loaded.\n";
}
}
SDRAM_WaitIpCmdDone()
{
__var reg;
do
{
reg = __readMemory32(0x402F003C, "Memory");
}while((reg & 0x3) == 0);
__writeMemory32(0x00000003, 0x402F003C, "Memory"); // clear IPCMDERR and IPCMDDONE bits
}
_clock_init()
{
__var reg;
// Enable all clocks
__writeMemory32(0xffffffff, 0x400FC068, "Memory");
__writeMemory32(0xffffffff, 0x400FC06C, "Memory");
__writeMemory32(0xffffffff, 0x400FC070, "Memory");
__writeMemory32(0xffffffff, 0x400FC074, "Memory");
__writeMemory32(0xffffffff, 0x400FC078, "Memory");
__writeMemory32(0xffffffff, 0x400FC07C, "Memory");
__writeMemory32(0xffffffff, 0x400FC080, "Memory");
// PERCLK_PODF: 1 divide by 2
__writeMemory32(0x04900001, 0x400FC01C, "Memory");
// Enable SYS PLL but keep it bypassed.
__writeMemory32(0x00012001, 0x400D8030, "Memory");
do
{
reg = __readMemory32(0x400D8030, "Memory");
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
__writeMemory32(0x00002001, 0x400D8030, "Memory");
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
__writeMemory32(0x001d0000, 0x400D8100, "Memory");
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
__writeMemory32(0x00010D40, 0x400FC014, "Memory");
__message "clock init done\n";
}
_sdr_Init()
{
// Config IOMUX
__writeMemory32(0x00000000, 0x401F8014, "Memory");
__writeMemory32(0x00000000, 0x401F8018, "Memory");
__writeMemory32(0x00000000, 0x401F801C, "Memory");
__writeMemory32(0x00000000, 0x401F8020, "Memory");
__writeMemory32(0x00000000, 0x401F8024, "Memory");
__writeMemory32(0x00000000, 0x401F8028, "Memory");
__writeMemory32(0x00000000, 0x401F802C, "Memory");
__writeMemory32(0x00000000, 0x401F8030, "Memory");
__writeMemory32(0x00000000, 0x401F8034, "Memory");
__writeMemory32(0x00000000, 0x401F8038, "Memory");
__writeMemory32(0x00000000, 0x401F803C, "Memory");
__writeMemory32(0x00000000, 0x401F8040, "Memory");
__writeMemory32(0x00000000, 0x401F8044, "Memory");
__writeMemory32(0x00000000, 0x401F8048, "Memory");
__writeMemory32(0x00000000, 0x401F804C, "Memory");
__writeMemory32(0x00000000, 0x401F8050, "Memory");
__writeMemory32(0x00000000, 0x401F8054, "Memory");
__writeMemory32(0x00000000, 0x401F8058, "Memory");
__writeMemory32(0x00000000, 0x401F805C, "Memory");
__writeMemory32(0x00000000, 0x401F8060, "Memory");
__writeMemory32(0x00000000, 0x401F8064, "Memory");
__writeMemory32(0x00000000, 0x401F8068, "Memory");
__writeMemory32(0x00000000, 0x401F806C, "Memory");
__writeMemory32(0x00000000, 0x401F8070, "Memory");
__writeMemory32(0x00000000, 0x401F8074, "Memory");
__writeMemory32(0x00000000, 0x401F8078, "Memory");
__writeMemory32(0x00000000, 0x401F807C, "Memory");
__writeMemory32(0x00000000, 0x401F8080, "Memory");
__writeMemory32(0x00000000, 0x401F8084, "Memory");
__writeMemory32(0x00000000, 0x401F8088, "Memory");
__writeMemory32(0x00000000, 0x401F808C, "Memory");
__writeMemory32(0x00000000, 0x401F8090, "Memory");
__writeMemory32(0x00000000, 0x401F8094, "Memory");
__writeMemory32(0x00000000, 0x401F8098, "Memory");
__writeMemory32(0x00000000, 0x401F809C, "Memory");
__writeMemory32(0x00000000, 0x401F80A0, "Memory");
__writeMemory32(0x00000000, 0x401F80A4, "Memory");
__writeMemory32(0x00000000, 0x401F80A8, "Memory");
__writeMemory32(0x00000000, 0x401F80AC, "Memory");
__writeMemory32(0x00000010, 0x401F80B0, "Memory"); // EMC_39, DQS PIN, enable SION
__writeMemory32(0x00000000, 0x401F80B4, "Memory");
__writeMemory32(0x00000000, 0x401F80B8, "Memory");
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
__writeMemory32(0x000110F9, 0x401F8204, "Memory");
__writeMemory32(0x000110F9, 0x401F8208, "Memory");
__writeMemory32(0x000110F9, 0x401F820C, "Memory");
__writeMemory32(0x000110F9, 0x401F8210, "Memory");
__writeMemory32(0x000110F9, 0x401F8214, "Memory");
__writeMemory32(0x000110F9, 0x401F8218, "Memory");
__writeMemory32(0x000110F9, 0x401F821C, "Memory");
__writeMemory32(0x000110F9, 0x401F8220, "Memory");
__writeMemory32(0x000110F9, 0x401F8224, "Memory");
__writeMemory32(0x000110F9, 0x401F8228, "Memory");
__writeMemory32(0x000110F9, 0x401F822C, "Memory");
__writeMemory32(0x000110F9, 0x401F8230, "Memory");
__writeMemory32(0x000110F9, 0x401F8234, "Memory");
__writeMemory32(0x000110F9, 0x401F8238, "Memory");
__writeMemory32(0x000110F9, 0x401F823C, "Memory");
__writeMemory32(0x000110F9, 0x401F8240, "Memory");
__writeMemory32(0x000110F9, 0x401F8244, "Memory");
__writeMemory32(0x000110F9, 0x401F8248, "Memory");
__writeMemory32(0x000110F9, 0x401F824C, "Memory");
__writeMemory32(0x000110F9, 0x401F8250, "Memory");
__writeMemory32(0x000110F9, 0x401F8254, "Memory");
__writeMemory32(0x000110F9, 0x401F8258, "Memory");
__writeMemory32(0x000110F9, 0x401F825C, "Memory");
__writeMemory32(0x000110F9, 0x401F8260, "Memory");
__writeMemory32(0x000110F9, 0x401F8264, "Memory");
__writeMemory32(0x000110F9, 0x401F8268, "Memory");
__writeMemory32(0x000110F9, 0x401F826C, "Memory");
__writeMemory32(0x000110F9, 0x401F8270, "Memory");
__writeMemory32(0x000110F9, 0x401F8274, "Memory");
__writeMemory32(0x000110F9, 0x401F8278, "Memory");
__writeMemory32(0x000110F9, 0x401F827C, "Memory");
__writeMemory32(0x000110F9, 0x401F8280, "Memory");
__writeMemory32(0x000110F9, 0x401F8284, "Memory");
__writeMemory32(0x000110F9, 0x401F8288, "Memory");
__writeMemory32(0x000110F9, 0x401F828C, "Memory");
__writeMemory32(0x000110F9, 0x401F8290, "Memory");
__writeMemory32(0x000110F9, 0x401F8294, "Memory");
__writeMemory32(0x000110F9, 0x401F8298, "Memory");
__writeMemory32(0x000110F9, 0x401F829C, "Memory");
__writeMemory32(0x000110F9, 0x401F82A0, "Memory");
__writeMemory32(0x000110F9, 0x401F82A4, "Memory");
__writeMemory32(0x000110F9, 0x401F82A8, "Memory");
// Config SDR Controller Registers/
__writeMemory32(0x10000004, 0x402F0000, "Memory"); // MCR
__writeMemory32(0x00030524, 0x402F0008, "Memory"); // BMCR0
__writeMemory32(0x06030524, 0x402F000C, "Memory"); // BMCR1
__writeMemory32(0x8000001B, 0x402F0010, "Memory"); // BR0, 32MB
__writeMemory32(0x00000F31, 0x402F0040, "Memory"); // SDRAMCR0
__writeMemory32(0x00662A22, 0x402F0044, "Memory"); // SDRAMCR1
__writeMemory32(0x000A0A0A, 0x402F0048, "Memory"); // SDRAMCR2
__writeMemory32(0x08080A00, 0x402F004C, "Memory"); // SDRAMCR3
__writeMemory32(0x80000000, 0x402F0090, "Memory"); // IPCR0
__writeMemory32(0x00000002, 0x402F0094, "Memory"); // IPCR1
__writeMemory32(0x00000000, 0x402F0098, "Memory"); // IPCR2
__writeMemory32(0xA55A000F, 0x402F009C, "Memory"); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
__writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
__writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
__writeMemory32(0x00000033, 0x402F00A0, "Memory"); // IPTXDAT
__writeMemory32(0xA55A000A, 0x402F009C, "Memory"); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
__writeMemory32(0x08080A01, 0x402F004C, "Memory"); // enable sdram self refresh after initialization done.
__message "SDRAM init done\n";
}
execUserPreload()
{
_load_dcdc_trim();
_clock_init();
_sdr_Init();
__message "execUserPreload() done.\n";
}
execUserReset()
{
_load_dcdc_trim();
_clock_init();
_sdr_Init();
__message "execUserReset() done.\n";
}

14
board/NXP_EVKB_IMXRT1050/IAR/hello_world/hello_world.ewd
View File

@@ -1529,7 +1529,7 @@
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MK70FN1M0xxx12.ddf</state>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1052xxx6B.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@@ -1573,7 +1573,7 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>7.80.4.12487</state>
<state>8.40.2.22864</state>
</option>
<option>
<name>UseFlashLoader</name>
@@ -1597,7 +1597,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashK70Fxxx128K.board</state>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@@ -3014,7 +3014,7 @@
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MK70FN1M0xxx12.ddf</state>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1052xxx6B.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@@ -3058,7 +3058,7 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>7.80.4.12487</state>
<state>8.40.2.22864</state>
</option>
<option>
<name>UseFlashLoader</name>
@@ -3082,7 +3082,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashK70Fxxx128K.board</state>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@@ -3270,7 +3270,7 @@
<option>
<name>CMSISDAPResetList</name>
<version>1</version>
<state>5</state>
<state>4</state>
</option>
<option>
<name>CMSISDAPHWResetDuration</name>

231
board/NXP_EVKB_IMXRT1050/IAR/hello_world/hello_world.ewp
View File

@@ -354,14 +354,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -1435,14 +1435,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -2515,14 +2515,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -3598,14 +3598,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -4678,14 +4678,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -5757,14 +5757,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -6836,14 +6836,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -7917,14 +7917,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -8997,14 +8997,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -10080,14 +10080,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -11160,14 +11160,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -12239,14 +12239,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -12970,83 +12970,83 @@
<group>
<name>serial_manager</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_manager.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_manager.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_manager.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_manager.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_port_internal.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_port_internal.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_port_uart.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_port_uart.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_port_uart.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_port_uart.h</name>
</file>
</group>
<group>
<name>uart</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart\lpuart_adapter.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart\lpuart_adapter.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart\uart.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart\uart.h</name>
</file>
</group>
</group>
<group>
<name>device</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\fsl_device_registers.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\fsl_device_registers.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\MIMXRT1052.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\MIMXRT1052.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\MIMXRT1052_features.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\MIMXRT1052_features.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\system_MIMXRT1052.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\system_MIMXRT1052.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\system_MIMXRT1052.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\system_MIMXRT1052.h</name>
</file>
</group>
<group>
<name>drivers</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_clock.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_clock.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_clock.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_clock.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_common.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_common.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_common.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_common.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_gpio.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_gpio.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_gpio.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_gpio.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_iomuxc.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_iomuxc.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_lpuart.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_lpuart.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_lpuart.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_lpuart.h</name>
</file>
</group>
<group>
<name>startup</name>
<file>
<name>$PROJ_DIR$\startup_MIMXRT1052.s</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\iar\startup_MIMXRT1052.s</name>
</file>
</group>
<group>
@@ -13282,26 +13282,29 @@
<file>
<name>$PROJ_DIR$\..\..\BSP\Inc\pin_mux.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\TOS_CONFIG\tos_config.h</name>
</file>
</group>
<group>
<name>utilities</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\fsl_assert.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_assert.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console\fsl_debug_console.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console\fsl_debug_console.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console\fsl_debug_console.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console\fsl_debug_console.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console\fsl_debug_console_conf.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console\fsl_debug_console_conf.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str\fsl_str.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str\fsl_str.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str\fsl_str.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str\fsl_str.h</name>
</file>
</group>
<group>
@@ -13319,10 +13322,10 @@
<name>$PROJ_DIR$\..\..\BSP\Inc\evkbimxrt1050_sdram_ini_dcd.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\xip\fsl_flexspi_nor_boot.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\xip\fsl_flexspi_nor_boot.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\xip\fsl_flexspi_nor_boot.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\xip\fsl_flexspi_nor_boot.h</name>
</file>
</group>
</project>

69
board/NXP_EVKB_IMXRT1050/IAR/hello_world/readme.txt Normal file
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Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1050.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

94
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/MIMXRT1052xxxxx_flexspi_nor.scf Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000
#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x03FFDC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x00040000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (.boot_hdr.conf, +FIRST)
}
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
}
#else
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
#endif
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

75
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/MIMXRT1052xxxxx_ram.scf Normal file
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@@ -0,0 +1,75 @@
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x00040000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

83
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/MIMXRT1052xxxxx_sdram.scf Normal file
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@@ -0,0 +1,83 @@
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x80000000
#define m_data_size 0x01E00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
#define m_data2_start 0x20000000
#define m_data2_size 0x00020000
#define m_data3_start 0x20200000
#define m_data3_size 0x00040000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
*(m_usb_dma_init_data)
*(m_usb_dma_noninit_data)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

90
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/evkbimxrt1050_flexspi_nor.ini Normal file
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@@ -0,0 +1,90 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

91
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/evkbimxrt1050_ram.ini Normal file
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@@ -0,0 +1,91 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

260
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/evkbimxrt1050_sdram_init.ini Normal file
View File

@@ -0,0 +1,260 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
_WDWORD(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
}
FUNC void _clock_init(void)
{
unsigned int reg;
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
// PERCLK_PODF: 1 divide by 2
_WDWORD(0x400FC01C, 0x04900001);
// Enable SYS PLL but keep it bypassed.
_WDWORD(0x400D8030, 0x00012001);
do
{
reg = _RDWORD(0x400D8030);
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
_WDWORD(0x400D8030, 0x00002001);
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
_WDWORD(0x400D8100, 0x001d0000);
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
_WDWORD(0x400FC014, 0x00010D40);
}
FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
_clock_init();
_sdr_Init();
Setup(); // Setup for Running
}
_clock_init();
_sdr_Init();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

2566
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/hello_world.uvoptx Normal file
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File diff suppressed because it is too large Load Diff

5825
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/hello_world.uvprojx Normal file
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File diff suppressed because it is too large Load Diff

69
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/readme.txt Normal file
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@@ -0,0 +1,69 @@
Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1050.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

2
board/NXP_EVK_IMXRT1010/bsp/Src/hello_world.c
View File

@@ -67,7 +67,7 @@ int main(void)
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
PRINTF("hello world from i.MX RT1010.\r\n");
PRINTF("Hello world from i.MX RT1010.\r\n");
PRINTF("Welcome to TencentOS tiny\r\n");
osKernelInitialize(); // TencentOS Tiny kernel initialize
osThreadCreate(osThread(task1), NULL); // Create task1

42
board/NXP_EVK_IMXRT1010/iar/hello_world/hello_world.ewp
View File

@@ -32,11 +32,11 @@
</option>
<option>
<name>Input description</name>
<state>Automatic choice of formatter.</state>
<state>No specifier n, no float nor long long, no scan set, no assignment suppressing, without multibyte support.</state>
</option>
<option>
<name>Output description</name>
<state>Automatic choice of formatter.</state>
<state>No specifier a, A, no specifier n, no float nor long long, without multibyte support.</state>
</option>
<option>
<name>GOutputBinary</name>
@@ -58,7 +58,7 @@
</option>
<option>
<name>RTDescription</name>
<state>0</state>
<state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
</option>
<option>
<name>OGProductVersion</name>
@@ -229,15 +229,15 @@
</option>
<option>
<name>CCPreprocFile</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CCPreprocComments</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CCPreprocLine</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>CCListCFile</name>
@@ -6473,21 +6473,6 @@
<data />
</settings>
</configuration>
<group>
<name>user</name>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\board.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\clock_config.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\hello_world.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\pin_mux.c</name>
</file>
</group>
<group>
<name>CMSIS</name>
<file>
@@ -6818,6 +6803,21 @@
<name>$PROJ_DIR$\..\..\..\..\kernel\core\include\tos_timer.h</name>
</file>
</group>
<group>
<name>user</name>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\board.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\clock_config.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\hello_world.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\bsp\Src\pin_mux.c</name>
</file>
</group>
<group>
<name>utilities</name>
<file>

69
board/NXP_EVK_IMXRT1010/iar/hello_world/readme.txt Normal file
View File

@@ -0,0 +1,69 @@
Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1010.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

16
board/NXP_EVK_IMXRT1010/keil/hello_world/hello_world.uvoptx
View File

@@ -463,7 +463,7 @@
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<CpuCode>8</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@@ -636,11 +636,11 @@
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>0</CpuCode>
<CpuCode>8</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@@ -1987,7 +1987,7 @@
<Group>
<GroupName>xip</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@@ -2121,12 +2121,4 @@
</File>
</Group>
<Group>
<GroupName>New Group</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
</Group>
</ProjectOpt>

12
board/NXP_EVK_IMXRT1010/keil/hello_world/hello_world.uvprojx
View File

@@ -962,9 +962,6 @@
</File>
</Files>
</Group>
<Group>
<GroupName>New Group</GroupName>
</Group>
</Groups>
</Target>
<Target>
@@ -1923,9 +1920,6 @@
</File>
</Files>
</Group>
<Group>
<GroupName>New Group</GroupName>
</Group>
</Groups>
</Target>
<Target>
@@ -2884,9 +2878,6 @@
</File>
</Files>
</Group>
<Group>
<GroupName>New Group</GroupName>
</Group>
</Groups>
</Target>
<Target>
@@ -3845,9 +3836,6 @@
</File>
</Files>
</Group>
<Group>
<GroupName>New Group</GroupName>
</Group>
</Groups>
</Target>
</Targets>

69
board/NXP_EVK_IMXRT1010/keil/hello_world/readme.txt Normal file
View File

@@ -0,0 +1,69 @@
Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1010.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

4
board/NXP_EVK_IMXRT1060/bsp/Src/hello_world.c
View File

@@ -25,11 +25,11 @@
/*******************************************************************************
* Code
******************************************************************************/
#define TASK1_STK_SIZE 1024
#define TASK1_STK_SIZE 512
void task1(void *arg);
osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
#define TASK2_STK_SIZE 1024
#define TASK2_STK_SIZE 512
void task2(void *arg);
osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);

95
board/NXP_EVK_IMXRT1060/iar/hello_world/MIMXRT1062xxxxx_sdram.icf Normal file
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/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;
define symbol m_text_start = 0x00000400;
define symbol m_text_end = 0x0001FFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x202BFFFF;
define symbol m_data3_start = 0x80000000;
define symbol m_data3_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __NCACHE_REGION_START = m_ncache_start;
define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1;
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { first readwrite, section m_usb_dma_init_data };
define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA3_region { block RW };
place in DATA3_region { block ZI };
if (isdefinedsymbol(__heap_noncacheable__)) {
place in NCACHE_region { last block HEAP };
} else {
place in DATA3_region { last block HEAP };
}
place in CSTACK_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };

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board/NXP_EVK_IMXRT1060/iar/hello_world/MIMXRT1062xxxxx_sdram_txt.icf Normal file
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/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191030
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x80000000;
define symbol m_interrupts_end = 0x800003FF;
define symbol m_text_start = 0x80000400;
define symbol m_text_end = 0x801FFFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x202BFFFF;
define symbol m_data3_start = 0x80200000;
define symbol m_data3_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __NCACHE_REGION_START = m_ncache_start;
define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1;
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end];
define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__];
define region DATA3_region = mem:[from m_data3_start to m_data3_end];
define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { first readwrite, section m_usb_dma_init_data };
define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA2_region { block RW };
place in DATA2_region { block ZI };
if (isdefinedsymbol(__heap_noncacheable__)) {
place in NCACHE_region { last block HEAP };
} else {
place in DATA2_region { last block HEAP };
}
place in CSTACK_region { block CSTACK };
place in NCACHE_region { block NCACHE_VAR };

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board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.ewd
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board/NXP_EVK_IMXRT1060/iar/hello_world/hello_world.ewp
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Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1060.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

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board/NXP_EVK_IMXRT1060/keil/hello_world/MIMXRT1062xxxxx_flexspi_nor.scf Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000
#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x007FDC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (.boot_hdr.conf, +FIRST)
}
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
}
#else
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
#endif
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

102
board/NXP_EVK_IMXRT1060/keil/hello_world/MIMXRT1062xxxxx_flexspi_nor_sdram.scf Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000
#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x007FDC00
#define m_data_start 0x80000000
#define m_data_size 0x01E00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
#define m_data2_start 0x20000000
#define m_data2_size 0x00020000
#define m_data3_start 0x20200000
#define m_data3_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (.boot_hdr.conf, +FIRST)
}
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
}
#else
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
#endif
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
*(m_usb_dma_init_data)
*(m_usb_dma_noninit_data)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

75
board/NXP_EVK_IMXRT1060/keil/hello_world/MIMXRT1062xxxxx_ram.scf Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

75
board/NXP_EVK_IMXRT1060/keil/hello_world/MIMXRT1062xxxxx_ram_0x1400.scf Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b190730
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00001400
#define m_interrupts_size 0x00000400
#define m_text_start 0x00001800
#define m_text_size 0x0001E800
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

83
board/NXP_EVK_IMXRT1060/keil/hello_world/MIMXRT1062xxxxx_sdram.scf Normal file
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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x80000000
#define m_data_size 0x01E00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
#define m_data2_start 0x20000000
#define m_data2_size 0x00020000
#define m_data3_start 0x20200000
#define m_data3_size 0x000C0000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
*(m_usb_dma_init_data)
*(m_usb_dma_noninit_data)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

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#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b191015
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x80000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x80000400
#define m_text_size 0x001FFC00
#define m_data_start 0x20200000
#define m_data_size 0x000C0000
#define m_data2_start 0x20000000
#define m_data2_size 0x00020000
#define m_data3_start 0x80200000
#define m_data3_size 0x01C00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
*(m_usb_dma_init_data)
*(m_usb_dma_noninit_data)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

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/*
* Copyright 2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

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/*
* Copyright 2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
_WDWORD(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
}
FUNC void _clock_init(void)
{
unsigned int reg;
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
// PERCLK_PODF: 1 divide by 2
_WDWORD(0x400FC01C, 0x04900001);
// Enable SYS PLL but keep it bypassed.
_WDWORD(0x400D8030, 0x00012001);
do
{
reg = _RDWORD(0x400D8030);
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
_WDWORD(0x400D8030, 0x00002001);
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
_WDWORD(0x400D8100, 0x001d0000);
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
_WDWORD(0x400FC014, 0x00010D40);
}
FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
_clock_init();
_sdr_Init();
Setup(); // Setup for Running
}
_clock_init();
_sdr_Init();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

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/*
* Copyright 2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

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/*
* Copyright 2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00001400); // Setup Stack Pointer
PC = _RDWORD(0x00001404); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00001400); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

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/*
* Copyright 2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
_WDWORD(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
}
FUNC void _clock_init(void)
{
unsigned int reg;
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
// PERCLK_PODF: 1 divide by 2
_WDWORD(0x400FC01C, 0x04900001);
// Enable SYS PLL but keep it bypassed.
_WDWORD(0x400D8030, 0x00012001);
do
{
reg = _RDWORD(0x400D8030);
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
_WDWORD(0x400D8030, 0x00002001);
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
_WDWORD(0x400D8100, 0x001d0000);
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
_WDWORD(0x400FC014, 0x00010D40);
}
FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
_clock_init();
_sdr_Init();
Setup(); // Setup for Running
}
_clock_init();
_sdr_Init();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

260
board/NXP_EVK_IMXRT1060/keil/hello_world/evkmimxrt1060_sdram_txt_init.ini Normal file
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/*
* Copyright 2018 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
_WDWORD(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
}
FUNC void _clock_init(void)
{
unsigned int reg;
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
// PERCLK_PODF: 1 divide by 2
_WDWORD(0x400FC01C, 0x04900001);
// Enable SYS PLL but keep it bypassed.
_WDWORD(0x400D8030, 0x00012001);
do
{
reg = _RDWORD(0x400D8030);
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
_WDWORD(0x400D8030, 0x00002001);
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
_WDWORD(0x400D8100, 0x001d0000);
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
_WDWORD(0x400FC014, 0x00010D40);
}
FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x80000000); // Setup Stack Pointer
PC = _RDWORD(0x80000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x80000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
_clock_init();
_sdr_Init();
Setup(); // Setup for Running
}
_clock_init();
_sdr_Init();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
g, main

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board/NXP_EVK_IMXRT1060/keil/hello_world/hello_world.uvprojx Normal file
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Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1060.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

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platform/vendor_bsp/nxp/MIMXRT1011/mcuxpresso/startup_mimxrt1011.c
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//*****************************************************************************
// MIMXRT1011 startup code for use with MCUXpresso IDE
//
// Version : 120419
//*****************************************************************************
//
// Copyright 2016-2019 NXP
// All rights reserved.
//
// SPDX-License-Identifier: BSD-3-Clause
//*****************************************************************************
#if defined (DEBUG)
#pragma GCC push_options
#pragma GCC optimize ("Og")
#endif // (DEBUG)
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
// Variable to store CRP value in. Will be placed automatically
// by the linker when "Enable Code Read Protect" selected.
// See crp.h header for more information
//*****************************************************************************
//*****************************************************************************
// Declaration of external SystemInit function
//*****************************************************************************
#if defined (__USE_CMSIS)
extern void SystemInit(void);
#endif // (__USE_CMSIS)
//*****************************************************************************
// Forward declaration of the core exception handlers.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions.
// If your application is a C++ one, then any interrupt handlers defined
// in C++ files within in your main application will need to have C linkage
// rather than C++ linkage. To do this, make sure that you are using extern "C"
// { .... } around the interrupt handler within your main application code.
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
// Forward declaration of the application IRQ handlers. When the application
// defines a handler (with the same name), this will automatically take
// precedence over weak definitions below
//*****************************************************************************
WEAK void DMA0_IRQHandler(void);
WEAK void DMA1_IRQHandler(void);
WEAK void DMA2_IRQHandler(void);
WEAK void DMA3_IRQHandler(void);
WEAK void DMA4_IRQHandler(void);
WEAK void DMA5_IRQHandler(void);
WEAK void DMA6_IRQHandler(void);
WEAK void DMA7_IRQHandler(void);
WEAK void DMA8_IRQHandler(void);
WEAK void DMA9_IRQHandler(void);
WEAK void DMA10_IRQHandler(void);
WEAK void DMA11_IRQHandler(void);
WEAK void DMA12_IRQHandler(void);
WEAK void DMA13_IRQHandler(void);
WEAK void DMA14_IRQHandler(void);
WEAK void DMA15_IRQHandler(void);
WEAK void DMA_ERROR_IRQHandler(void);
WEAK void CTI0_ERROR_IRQHandler(void);
WEAK void CTI1_ERROR_IRQHandler(void);
WEAK void CORE_IRQHandler(void);
WEAK void LPUART1_IRQHandler(void);
WEAK void LPUART2_IRQHandler(void);
WEAK void LPUART3_IRQHandler(void);
WEAK void LPUART4_IRQHandler(void);
WEAK void PIT_IRQHandler(void);
WEAK void USB_OTG1_IRQHandler(void);
WEAK void FLEXSPI_IRQHandler(void);
WEAK void FLEXRAM_IRQHandler(void);
WEAK void LPI2C1_IRQHandler(void);
WEAK void LPI2C2_IRQHandler(void);
WEAK void GPT1_IRQHandler(void);
WEAK void GPT2_IRQHandler(void);
WEAK void LPSPI1_IRQHandler(void);
WEAK void LPSPI2_IRQHandler(void);
WEAK void PWM1_0_IRQHandler(void);
WEAK void PWM1_1_IRQHandler(void);
WEAK void PWM1_2_IRQHandler(void);
WEAK void PWM1_3_IRQHandler(void);
WEAK void PWM1_FAULT_IRQHandler(void);
WEAK void KPP_IRQHandler(void);
WEAK void SRC_IRQHandler(void);
WEAK void GPR_IRQ_IRQHandler(void);
WEAK void CCM_1_IRQHandler(void);
WEAK void CCM_2_IRQHandler(void);
WEAK void EWM_IRQHandler(void);
WEAK void WDOG2_IRQHandler(void);
WEAK void SNVS_HP_WRAPPER_IRQHandler(void);
WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void);
WEAK void SNVS_LP_WRAPPER_IRQHandler(void);
WEAK void CSU_IRQHandler(void);
WEAK void DCP_IRQHandler(void);
WEAK void DCP_VMI_IRQHandler(void);
WEAK void Reserved68_IRQHandler(void);
WEAK void TRNG_IRQHandler(void);
WEAK void Reserved70_IRQHandler(void);
WEAK void Reserved71_IRQHandler(void);
WEAK void SAI1_IRQHandler(void);
WEAK void RTWDOG_IRQHandler(void);
WEAK void SAI3_RX_IRQHandler(void);
WEAK void SAI3_TX_IRQHandler(void);
WEAK void SPDIF_IRQHandler(void);
WEAK void PMU_IRQHandler(void);
WEAK void XBAR1_IRQ_0_1_2_3_IRQHandler(void);
WEAK void TEMP_LOW_HIGH_IRQHandler(void);
WEAK void TEMP_PANIC_IRQHandler(void);
WEAK void USB_PHY_IRQHandler(void);
WEAK void GPC_IRQHandler(void);
WEAK void ADC1_IRQHandler(void);
WEAK void FLEXIO1_IRQHandler(void);
WEAK void DCDC_IRQHandler(void);
WEAK void GPIO1_Combined_0_15_IRQHandler(void);
WEAK void GPIO1_Combined_16_31_IRQHandler(void);
WEAK void GPIO2_Combined_0_15_IRQHandler(void);
WEAK void GPIO5_Combined_0_15_IRQHandler(void);
WEAK void WDOG1_IRQHandler(void);
WEAK void ADC_ETC_IRQ0_IRQHandler(void);
WEAK void ADC_ETC_IRQ1_IRQHandler(void);
WEAK void ADC_ETC_IRQ2_IRQHandler(void);
WEAK void ADC_ETC_IRQ3_IRQHandler(void);
WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void);
//*****************************************************************************
// Forward declaration of the driver IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the driver
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//*****************************************************************************
void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA11_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA12_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA13_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved71_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PMU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void XBAR1_IRQ_0_1_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TEMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void USB_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
// External declaration for the pointer to the stack top from the Linker Script
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
// The vector table.
// This relies on the linker script to place at correct location in memory.
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
__attribute__ ((used, section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM7
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - MIMXRT1011
DMA0_IRQHandler, // 16: DMA channel 0 transfer complete
DMA1_IRQHandler, // 17: DMA channel 1 transfer complete
DMA2_IRQHandler, // 18: DMA channel 2 transfer complete
DMA3_IRQHandler, // 19: DMA channel 3 transfer complete
DMA4_IRQHandler, // 20: DMA channel 4 transfer complete
DMA5_IRQHandler, // 21: DMA channel 5 transfer complete
DMA6_IRQHandler, // 22: DMA channel 6 transfer complete
DMA7_IRQHandler, // 23: DMA channel 7 transfer complete
DMA8_IRQHandler, // 24: DMA channel 8 transfer complete
DMA9_IRQHandler, // 25: DMA channel 9 transfer complete
DMA10_IRQHandler, // 26: DMA channel 10 transfer complete
DMA11_IRQHandler, // 27: DMA channel 11 transfer complete
DMA12_IRQHandler, // 28: DMA channel 12 transfer complete
DMA13_IRQHandler, // 29: DMA channel 13 transfer complete
DMA14_IRQHandler, // 30: DMA channel 14 transfer complete
DMA15_IRQHandler, // 31: DMA channel 15 transfer complete
DMA_ERROR_IRQHandler, // 32: DMA error interrupt channels 0-15
CTI0_ERROR_IRQHandler, // 33: CTI trigger outputs
CTI1_ERROR_IRQHandler, // 34: CTI trigger outputs
CORE_IRQHandler, // 35: CorePlatform exception IRQ
LPUART1_IRQHandler, // 36: LPUART1 TX interrupt and RX interrupt
LPUART2_IRQHandler, // 37: LPUART2 TX interrupt and RX interrupt
LPUART3_IRQHandler, // 38: LPUART3 TX interrupt and RX interrupt
LPUART4_IRQHandler, // 39: LPUART4 TX interrupt and RX interrupt
PIT_IRQHandler, // 40: PIT interrupt
USB_OTG1_IRQHandler, // 41: USBO2 USB OTG1
FLEXSPI_IRQHandler, // 42: FlexSPI0 interrupt
FLEXRAM_IRQHandler, // 43: FlexRAM address out of range Or access hit IRQ
LPI2C1_IRQHandler, // 44: LPI2C1 interrupt
LPI2C2_IRQHandler, // 45: LPI2C2 interrupt
GPT1_IRQHandler, // 46: GPT1 interrupt
GPT2_IRQHandler, // 47: GPT2 interrupt
LPSPI1_IRQHandler, // 48: LPSPI1 single interrupt vector for all sources
LPSPI2_IRQHandler, // 49: LPSPI2 single interrupt vector for all sources
PWM1_0_IRQHandler, // 50: PWM1 capture 0, compare 0, or reload 0 interrupt
PWM1_1_IRQHandler, // 51: PWM1 capture 1, compare 1, or reload 0 interrupt
PWM1_2_IRQHandler, // 52: PWM1 capture 2, compare 2, or reload 0 interrupt
PWM1_3_IRQHandler, // 53: PWM1 capture 3, compare 3, or reload 0 interrupt
PWM1_FAULT_IRQHandler, // 54: PWM1 fault or reload error interrupt
KPP_IRQHandler, // 55: Keypad nterrupt
SRC_IRQHandler, // 56: SRC interrupt
GPR_IRQ_IRQHandler, // 57: Used to notify cores on exception condition while boot
CCM_1_IRQHandler, // 58: CCM IRQ1 interrupt
CCM_2_IRQHandler, // 59: CCM IRQ2 interrupt
EWM_IRQHandler, // 60: EWM interrupt
WDOG2_IRQHandler, // 61: WDOG2 interrupt
SNVS_HP_WRAPPER_IRQHandler, // 62: SNVS Functional Interrupt
SNVS_HP_WRAPPER_TZ_IRQHandler, // 63: SNVS Security Interrupt
SNVS_LP_WRAPPER_IRQHandler, // 64: ON-OFF button press shorter than 5 secs (pulse event)
CSU_IRQHandler, // 65: CSU interrupt
DCP_IRQHandler, // 66: Combined DCP channel interrupts(except channel 0) and CRC interrupt
DCP_VMI_IRQHandler, // 67: IRQ of DCP channel 0
Reserved68_IRQHandler, // 68: Reserved interrupt
TRNG_IRQHandler, // 69: TRNG interrupt
Reserved70_IRQHandler, // 70: Reserved interrupt
Reserved71_IRQHandler, // 71: Reserved interrupt
SAI1_IRQHandler, // 72: SAI1 interrupt
RTWDOG_IRQHandler, // 73: RTWDOG interrupt
SAI3_RX_IRQHandler, // 74: SAI3 interrupt
SAI3_TX_IRQHandler, // 75: SAI3 interrupt
SPDIF_IRQHandler, // 76: SPDIF interrupt
PMU_IRQHandler, // 77: PMU interrupt
XBAR1_IRQ_0_1_2_3_IRQHandler, // 78: XBAR1 interrupt
TEMP_LOW_HIGH_IRQHandler, // 79: TEMPMON interrupt
TEMP_PANIC_IRQHandler, // 80: TEMPMON interrupt
USB_PHY_IRQHandler, // 81: USBPHY (OTG1 UTMI), Interrupt
GPC_IRQHandler, // 82: GPC interrupt
ADC1_IRQHandler, // 83: ADC1 interrupt
FLEXIO1_IRQHandler, // 84: FLEXIO1 interrupt
DCDC_IRQHandler, // 85: DCDC interrupt
GPIO1_Combined_0_15_IRQHandler, // 86: Combined interrupt indication for GPIO1 signal 0 throughout 15
GPIO1_Combined_16_31_IRQHandler, // 87: Combined interrupt indication for GPIO1 signal 16 throughout 31
GPIO2_Combined_0_15_IRQHandler, // 88: Combined interrupt indication for GPIO2 signal 0 throughout 15
GPIO5_Combined_0_15_IRQHandler, // 89: Combined interrupt indication for GPIO5 signal 0 throughout 15
WDOG1_IRQHandler, // 90: WDOG1 interrupt
ADC_ETC_IRQ0_IRQHandler, // 91: ADCETC IRQ0 interrupt
ADC_ETC_IRQ1_IRQHandler, // 92: ADCETC IRQ1 interrupt
ADC_ETC_IRQ2_IRQHandler, // 93: ADCETC IRQ2 interrupt
ADC_ETC_IRQ3_IRQHandler, // 94: ADCETC IRQ3 interrupt
ADC_ETC_ERROR_IRQ_IRQHandler, // 95: ADCETC Error IRQ interrupt
}; /* End of g_pfnVectors */
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors.init_data")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors.init_bss")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors.reset")))
void ResetISR(void) {
// Disable interrupts
__asm volatile ("cpsid i");
#if defined (__USE_CMSIS)
// If __USE_CMSIS defined, then call CMSIS SystemInit code
SystemInit();
#else
// Disable Watchdog
volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000;
*WDOG1_WCR = *WDOG1_WCR & ~(1 << 2);
volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000;
*WDOG2_WCR = *WDOG2_WCR & ~(1 << 2);
// Write watchdog update key to unlock
*((volatile unsigned int *)0x400BC004) = 0xD928C520;
// Set timeout value
*((volatile unsigned int *)0x400BC008) = 0xFFFF;
// Now disable watchdog via control register
volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000;
*RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5);
#endif // (__USE_CMSIS)
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if !defined (__USE_CMSIS)
// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
// will setup the VTOR register
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
#endif // (__USE_CMSIS)
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
// Reenable interrupts
__asm volatile ("cpsie i");
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default core exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
WEAK_AV void NMI_Handler(void)
{ while(1) {}
}
WEAK_AV void HardFault_Handler(void)
{ while(1) {}
}
WEAK_AV void SVC_Handler(void)
{ while(1) {}
}
WEAK_AV void PendSV_Handler(void)
{ while(1) {}
}
WEAK_AV void SysTick_Handler(void)
{ while(1) {}
}
//*****************************************************************************
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//*****************************************************************************
WEAK_AV void IntDefaultHandler(void)
{ while(1) {}
}
//*****************************************************************************
// Default application exception handlers. Override the ones here by defining
// your own handler routines in your application code. These routines call
// driver exception handlers or IntDefaultHandler() if no driver exception
// handler is included.
//*****************************************************************************
WEAK void DMA0_IRQHandler(void)
{ DMA0_DriverIRQHandler();
}
WEAK void DMA1_IRQHandler(void)
{ DMA1_DriverIRQHandler();
}
WEAK void DMA2_IRQHandler(void)
{ DMA2_DriverIRQHandler();
}
WEAK void DMA3_IRQHandler(void)
{ DMA3_DriverIRQHandler();
}
WEAK void DMA4_IRQHandler(void)
{ DMA4_DriverIRQHandler();
}
WEAK void DMA5_IRQHandler(void)
{ DMA5_DriverIRQHandler();
}
WEAK void DMA6_IRQHandler(void)
{ DMA6_DriverIRQHandler();
}
WEAK void DMA7_IRQHandler(void)
{ DMA7_DriverIRQHandler();
}
WEAK void DMA8_IRQHandler(void)
{ DMA8_DriverIRQHandler();
}
WEAK void DMA9_IRQHandler(void)
{ DMA9_DriverIRQHandler();
}
WEAK void DMA10_IRQHandler(void)
{ DMA10_DriverIRQHandler();
}
WEAK void DMA11_IRQHandler(void)
{ DMA11_DriverIRQHandler();
}
WEAK void DMA12_IRQHandler(void)
{ DMA12_DriverIRQHandler();
}
WEAK void DMA13_IRQHandler(void)
{ DMA13_DriverIRQHandler();
}
WEAK void DMA14_IRQHandler(void)
{ DMA14_DriverIRQHandler();
}
WEAK void DMA15_IRQHandler(void)
{ DMA15_DriverIRQHandler();
}
WEAK void DMA_ERROR_IRQHandler(void)
{ DMA_ERROR_DriverIRQHandler();
}
WEAK void CTI0_ERROR_IRQHandler(void)
{ CTI0_ERROR_DriverIRQHandler();
}
WEAK void CTI1_ERROR_IRQHandler(void)
{ CTI1_ERROR_DriverIRQHandler();
}
WEAK void CORE_IRQHandler(void)
{ CORE_DriverIRQHandler();
}
WEAK void LPUART1_IRQHandler(void)
{ LPUART1_DriverIRQHandler();
}
WEAK void LPUART2_IRQHandler(void)
{ LPUART2_DriverIRQHandler();
}
WEAK void LPUART3_IRQHandler(void)
{ LPUART3_DriverIRQHandler();
}
WEAK void LPUART4_IRQHandler(void)
{ LPUART4_DriverIRQHandler();
}
WEAK void PIT_IRQHandler(void)
{ PIT_DriverIRQHandler();
}
WEAK void USB_OTG1_IRQHandler(void)
{ USB_OTG1_DriverIRQHandler();
}
WEAK void FLEXSPI_IRQHandler(void)
{ FLEXSPI_DriverIRQHandler();
}
WEAK void FLEXRAM_IRQHandler(void)
{ FLEXRAM_DriverIRQHandler();
}
WEAK void LPI2C1_IRQHandler(void)
{ LPI2C1_DriverIRQHandler();
}
WEAK void LPI2C2_IRQHandler(void)
{ LPI2C2_DriverIRQHandler();
}
WEAK void GPT1_IRQHandler(void)
{ GPT1_DriverIRQHandler();
}
WEAK void GPT2_IRQHandler(void)
{ GPT2_DriverIRQHandler();
}
WEAK void LPSPI1_IRQHandler(void)
{ LPSPI1_DriverIRQHandler();
}
WEAK void LPSPI2_IRQHandler(void)
{ LPSPI2_DriverIRQHandler();
}
WEAK void PWM1_0_IRQHandler(void)
{ PWM1_0_DriverIRQHandler();
}
WEAK void PWM1_1_IRQHandler(void)
{ PWM1_1_DriverIRQHandler();
}
WEAK void PWM1_2_IRQHandler(void)
{ PWM1_2_DriverIRQHandler();
}
WEAK void PWM1_3_IRQHandler(void)
{ PWM1_3_DriverIRQHandler();
}
WEAK void PWM1_FAULT_IRQHandler(void)
{ PWM1_FAULT_DriverIRQHandler();
}
WEAK void KPP_IRQHandler(void)
{ KPP_DriverIRQHandler();
}
WEAK void SRC_IRQHandler(void)
{ SRC_DriverIRQHandler();
}
WEAK void GPR_IRQ_IRQHandler(void)
{ GPR_IRQ_DriverIRQHandler();
}
WEAK void CCM_1_IRQHandler(void)
{ CCM_1_DriverIRQHandler();
}
WEAK void CCM_2_IRQHandler(void)
{ CCM_2_DriverIRQHandler();
}
WEAK void EWM_IRQHandler(void)
{ EWM_DriverIRQHandler();
}
WEAK void WDOG2_IRQHandler(void)
{ WDOG2_DriverIRQHandler();
}
WEAK void SNVS_HP_WRAPPER_IRQHandler(void)
{ SNVS_HP_WRAPPER_DriverIRQHandler();
}
WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void)
{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler();
}
WEAK void SNVS_LP_WRAPPER_IRQHandler(void)
{ SNVS_LP_WRAPPER_DriverIRQHandler();
}
WEAK void CSU_IRQHandler(void)
{ CSU_DriverIRQHandler();
}
WEAK void DCP_IRQHandler(void)
{ DCP_DriverIRQHandler();
}
WEAK void DCP_VMI_IRQHandler(void)
{ DCP_VMI_DriverIRQHandler();
}
WEAK void Reserved68_IRQHandler(void)
{ Reserved68_DriverIRQHandler();
}
WEAK void TRNG_IRQHandler(void)
{ TRNG_DriverIRQHandler();
}
WEAK void Reserved70_IRQHandler(void)
{ Reserved70_DriverIRQHandler();
}
WEAK void Reserved71_IRQHandler(void)
{ Reserved71_DriverIRQHandler();
}
WEAK void SAI1_IRQHandler(void)
{ SAI1_DriverIRQHandler();
}
WEAK void RTWDOG_IRQHandler(void)
{ RTWDOG_DriverIRQHandler();
}
WEAK void SAI3_RX_IRQHandler(void)
{ SAI3_RX_DriverIRQHandler();
}
WEAK void SAI3_TX_IRQHandler(void)
{ SAI3_TX_DriverIRQHandler();
}
WEAK void SPDIF_IRQHandler(void)
{ SPDIF_DriverIRQHandler();
}
WEAK void PMU_IRQHandler(void)
{ PMU_DriverIRQHandler();
}
WEAK void XBAR1_IRQ_0_1_2_3_IRQHandler(void)
{ XBAR1_IRQ_0_1_2_3_DriverIRQHandler();
}
WEAK void TEMP_LOW_HIGH_IRQHandler(void)
{ TEMP_LOW_HIGH_DriverIRQHandler();
}
WEAK void TEMP_PANIC_IRQHandler(void)
{ TEMP_PANIC_DriverIRQHandler();
}
WEAK void USB_PHY_IRQHandler(void)
{ USB_PHY_DriverIRQHandler();
}
WEAK void GPC_IRQHandler(void)
{ GPC_DriverIRQHandler();
}
WEAK void ADC1_IRQHandler(void)
{ ADC1_DriverIRQHandler();
}
WEAK void FLEXIO1_IRQHandler(void)
{ FLEXIO1_DriverIRQHandler();
}
WEAK void DCDC_IRQHandler(void)
{ DCDC_DriverIRQHandler();
}
WEAK void GPIO1_Combined_0_15_IRQHandler(void)
{ GPIO1_Combined_0_15_DriverIRQHandler();
}
WEAK void GPIO1_Combined_16_31_IRQHandler(void)
{ GPIO1_Combined_16_31_DriverIRQHandler();
}
WEAK void GPIO2_Combined_0_15_IRQHandler(void)
{ GPIO2_Combined_0_15_DriverIRQHandler();
}
WEAK void GPIO5_Combined_0_15_IRQHandler(void)
{ GPIO5_Combined_0_15_DriverIRQHandler();
}
WEAK void WDOG1_IRQHandler(void)
{ WDOG1_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ0_IRQHandler(void)
{ ADC_ETC_IRQ0_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ1_IRQHandler(void)
{ ADC_ETC_IRQ1_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ2_IRQHandler(void)
{ ADC_ETC_IRQ2_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ3_IRQHandler(void)
{ ADC_ETC_IRQ3_DriverIRQHandler();
}
WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void)
{ ADC_ETC_ERROR_IRQ_DriverIRQHandler();
}
//*****************************************************************************
#if defined (DEBUG)
#pragma GCC pop_options
#endif // (DEBUG)

865
platform/vendor_bsp/nxp/MIMXRT1011/mcuxpresso/startup_mimxrt1011.cpp
View File

@@ -1,865 +0,0 @@
//*****************************************************************************
// MIMXRT1011 startup code for use with MCUXpresso IDE
//
// Version : 120419
//*****************************************************************************
//
// Copyright 2016-2019 NXP
// All rights reserved.
//
// SPDX-License-Identifier: BSD-3-Clause
//*****************************************************************************
#if defined (DEBUG)
#pragma GCC push_options
#pragma GCC optimize ("Og")
#endif // (DEBUG)
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
// Variable to store CRP value in. Will be placed automatically
// by the linker when "Enable Code Read Protect" selected.
// See crp.h header for more information
//*****************************************************************************
//*****************************************************************************
// Declaration of external SystemInit function
//*****************************************************************************
#if defined (__USE_CMSIS)
extern void SystemInit(void);
#endif // (__USE_CMSIS)
//*****************************************************************************
// Forward declaration of the core exception handlers.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions.
// If your application is a C++ one, then any interrupt handlers defined
// in C++ files within in your main application will need to have C linkage
// rather than C++ linkage. To do this, make sure that you are using extern "C"
// { .... } around the interrupt handler within your main application code.
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
// Forward declaration of the application IRQ handlers. When the application
// defines a handler (with the same name), this will automatically take
// precedence over weak definitions below
//*****************************************************************************
WEAK void DMA0_IRQHandler(void);
WEAK void DMA1_IRQHandler(void);
WEAK void DMA2_IRQHandler(void);
WEAK void DMA3_IRQHandler(void);
WEAK void DMA4_IRQHandler(void);
WEAK void DMA5_IRQHandler(void);
WEAK void DMA6_IRQHandler(void);
WEAK void DMA7_IRQHandler(void);
WEAK void DMA8_IRQHandler(void);
WEAK void DMA9_IRQHandler(void);
WEAK void DMA10_IRQHandler(void);
WEAK void DMA11_IRQHandler(void);
WEAK void DMA12_IRQHandler(void);
WEAK void DMA13_IRQHandler(void);
WEAK void DMA14_IRQHandler(void);
WEAK void DMA15_IRQHandler(void);
WEAK void DMA_ERROR_IRQHandler(void);
WEAK void CTI0_ERROR_IRQHandler(void);
WEAK void CTI1_ERROR_IRQHandler(void);
WEAK void CORE_IRQHandler(void);
WEAK void LPUART1_IRQHandler(void);
WEAK void LPUART2_IRQHandler(void);
WEAK void LPUART3_IRQHandler(void);
WEAK void LPUART4_IRQHandler(void);
WEAK void PIT_IRQHandler(void);
WEAK void USB_OTG1_IRQHandler(void);
WEAK void FLEXSPI_IRQHandler(void);
WEAK void FLEXRAM_IRQHandler(void);
WEAK void LPI2C1_IRQHandler(void);
WEAK void LPI2C2_IRQHandler(void);
WEAK void GPT1_IRQHandler(void);
WEAK void GPT2_IRQHandler(void);
WEAK void LPSPI1_IRQHandler(void);
WEAK void LPSPI2_IRQHandler(void);
WEAK void PWM1_0_IRQHandler(void);
WEAK void PWM1_1_IRQHandler(void);
WEAK void PWM1_2_IRQHandler(void);
WEAK void PWM1_3_IRQHandler(void);
WEAK void PWM1_FAULT_IRQHandler(void);
WEAK void KPP_IRQHandler(void);
WEAK void SRC_IRQHandler(void);
WEAK void GPR_IRQ_IRQHandler(void);
WEAK void CCM_1_IRQHandler(void);
WEAK void CCM_2_IRQHandler(void);
WEAK void EWM_IRQHandler(void);
WEAK void WDOG2_IRQHandler(void);
WEAK void SNVS_HP_WRAPPER_IRQHandler(void);
WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void);
WEAK void SNVS_LP_WRAPPER_IRQHandler(void);
WEAK void CSU_IRQHandler(void);
WEAK void DCP_IRQHandler(void);
WEAK void DCP_VMI_IRQHandler(void);
WEAK void Reserved68_IRQHandler(void);
WEAK void TRNG_IRQHandler(void);
WEAK void Reserved70_IRQHandler(void);
WEAK void Reserved71_IRQHandler(void);
WEAK void SAI1_IRQHandler(void);
WEAK void RTWDOG_IRQHandler(void);
WEAK void SAI3_RX_IRQHandler(void);
WEAK void SAI3_TX_IRQHandler(void);
WEAK void SPDIF_IRQHandler(void);
WEAK void PMU_IRQHandler(void);
WEAK void XBAR1_IRQ_0_1_2_3_IRQHandler(void);
WEAK void TEMP_LOW_HIGH_IRQHandler(void);
WEAK void TEMP_PANIC_IRQHandler(void);
WEAK void USB_PHY_IRQHandler(void);
WEAK void GPC_IRQHandler(void);
WEAK void ADC1_IRQHandler(void);
WEAK void FLEXIO1_IRQHandler(void);
WEAK void DCDC_IRQHandler(void);
WEAK void GPIO1_Combined_0_15_IRQHandler(void);
WEAK void GPIO1_Combined_16_31_IRQHandler(void);
WEAK void GPIO2_Combined_0_15_IRQHandler(void);
WEAK void GPIO5_Combined_0_15_IRQHandler(void);
WEAK void WDOG1_IRQHandler(void);
WEAK void ADC_ETC_IRQ0_IRQHandler(void);
WEAK void ADC_ETC_IRQ1_IRQHandler(void);
WEAK void ADC_ETC_IRQ2_IRQHandler(void);
WEAK void ADC_ETC_IRQ3_IRQHandler(void);
WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void);
//*****************************************************************************
// Forward declaration of the driver IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the driver
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//*****************************************************************************
void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA11_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA12_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA13_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved71_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PMU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void XBAR1_IRQ_0_1_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TEMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void USB_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
// External declaration for the pointer to the stack top from the Linker Script
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
// The vector table.
// This relies on the linker script to place at correct location in memory.
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
__attribute__ ((used, section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM7
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - MIMXRT1011
DMA0_IRQHandler, // 16: DMA channel 0 transfer complete
DMA1_IRQHandler, // 17: DMA channel 1 transfer complete
DMA2_IRQHandler, // 18: DMA channel 2 transfer complete
DMA3_IRQHandler, // 19: DMA channel 3 transfer complete
DMA4_IRQHandler, // 20: DMA channel 4 transfer complete
DMA5_IRQHandler, // 21: DMA channel 5 transfer complete
DMA6_IRQHandler, // 22: DMA channel 6 transfer complete
DMA7_IRQHandler, // 23: DMA channel 7 transfer complete
DMA8_IRQHandler, // 24: DMA channel 8 transfer complete
DMA9_IRQHandler, // 25: DMA channel 9 transfer complete
DMA10_IRQHandler, // 26: DMA channel 10 transfer complete
DMA11_IRQHandler, // 27: DMA channel 11 transfer complete
DMA12_IRQHandler, // 28: DMA channel 12 transfer complete
DMA13_IRQHandler, // 29: DMA channel 13 transfer complete
DMA14_IRQHandler, // 30: DMA channel 14 transfer complete
DMA15_IRQHandler, // 31: DMA channel 15 transfer complete
DMA_ERROR_IRQHandler, // 32: DMA error interrupt channels 0-15
CTI0_ERROR_IRQHandler, // 33: CTI trigger outputs
CTI1_ERROR_IRQHandler, // 34: CTI trigger outputs
CORE_IRQHandler, // 35: CorePlatform exception IRQ
LPUART1_IRQHandler, // 36: LPUART1 TX interrupt and RX interrupt
LPUART2_IRQHandler, // 37: LPUART2 TX interrupt and RX interrupt
LPUART3_IRQHandler, // 38: LPUART3 TX interrupt and RX interrupt
LPUART4_IRQHandler, // 39: LPUART4 TX interrupt and RX interrupt
PIT_IRQHandler, // 40: PIT interrupt
USB_OTG1_IRQHandler, // 41: USBO2 USB OTG1
FLEXSPI_IRQHandler, // 42: FlexSPI0 interrupt
FLEXRAM_IRQHandler, // 43: FlexRAM address out of range Or access hit IRQ
LPI2C1_IRQHandler, // 44: LPI2C1 interrupt
LPI2C2_IRQHandler, // 45: LPI2C2 interrupt
GPT1_IRQHandler, // 46: GPT1 interrupt
GPT2_IRQHandler, // 47: GPT2 interrupt
LPSPI1_IRQHandler, // 48: LPSPI1 single interrupt vector for all sources
LPSPI2_IRQHandler, // 49: LPSPI2 single interrupt vector for all sources
PWM1_0_IRQHandler, // 50: PWM1 capture 0, compare 0, or reload 0 interrupt
PWM1_1_IRQHandler, // 51: PWM1 capture 1, compare 1, or reload 0 interrupt
PWM1_2_IRQHandler, // 52: PWM1 capture 2, compare 2, or reload 0 interrupt
PWM1_3_IRQHandler, // 53: PWM1 capture 3, compare 3, or reload 0 interrupt
PWM1_FAULT_IRQHandler, // 54: PWM1 fault or reload error interrupt
KPP_IRQHandler, // 55: Keypad nterrupt
SRC_IRQHandler, // 56: SRC interrupt
GPR_IRQ_IRQHandler, // 57: Used to notify cores on exception condition while boot
CCM_1_IRQHandler, // 58: CCM IRQ1 interrupt
CCM_2_IRQHandler, // 59: CCM IRQ2 interrupt
EWM_IRQHandler, // 60: EWM interrupt
WDOG2_IRQHandler, // 61: WDOG2 interrupt
SNVS_HP_WRAPPER_IRQHandler, // 62: SNVS Functional Interrupt
SNVS_HP_WRAPPER_TZ_IRQHandler, // 63: SNVS Security Interrupt
SNVS_LP_WRAPPER_IRQHandler, // 64: ON-OFF button press shorter than 5 secs (pulse event)
CSU_IRQHandler, // 65: CSU interrupt
DCP_IRQHandler, // 66: Combined DCP channel interrupts(except channel 0) and CRC interrupt
DCP_VMI_IRQHandler, // 67: IRQ of DCP channel 0
Reserved68_IRQHandler, // 68: Reserved interrupt
TRNG_IRQHandler, // 69: TRNG interrupt
Reserved70_IRQHandler, // 70: Reserved interrupt
Reserved71_IRQHandler, // 71: Reserved interrupt
SAI1_IRQHandler, // 72: SAI1 interrupt
RTWDOG_IRQHandler, // 73: RTWDOG interrupt
SAI3_RX_IRQHandler, // 74: SAI3 interrupt
SAI3_TX_IRQHandler, // 75: SAI3 interrupt
SPDIF_IRQHandler, // 76: SPDIF interrupt
PMU_IRQHandler, // 77: PMU interrupt
XBAR1_IRQ_0_1_2_3_IRQHandler, // 78: XBAR1 interrupt
TEMP_LOW_HIGH_IRQHandler, // 79: TEMPMON interrupt
TEMP_PANIC_IRQHandler, // 80: TEMPMON interrupt
USB_PHY_IRQHandler, // 81: USBPHY (OTG1 UTMI), Interrupt
GPC_IRQHandler, // 82: GPC interrupt
ADC1_IRQHandler, // 83: ADC1 interrupt
FLEXIO1_IRQHandler, // 84: FLEXIO1 interrupt
DCDC_IRQHandler, // 85: DCDC interrupt
GPIO1_Combined_0_15_IRQHandler, // 86: Combined interrupt indication for GPIO1 signal 0 throughout 15
GPIO1_Combined_16_31_IRQHandler, // 87: Combined interrupt indication for GPIO1 signal 16 throughout 31
GPIO2_Combined_0_15_IRQHandler, // 88: Combined interrupt indication for GPIO2 signal 0 throughout 15
GPIO5_Combined_0_15_IRQHandler, // 89: Combined interrupt indication for GPIO5 signal 0 throughout 15
WDOG1_IRQHandler, // 90: WDOG1 interrupt
ADC_ETC_IRQ0_IRQHandler, // 91: ADCETC IRQ0 interrupt
ADC_ETC_IRQ1_IRQHandler, // 92: ADCETC IRQ1 interrupt
ADC_ETC_IRQ2_IRQHandler, // 93: ADCETC IRQ2 interrupt
ADC_ETC_IRQ3_IRQHandler, // 94: ADCETC IRQ3 interrupt
ADC_ETC_ERROR_IRQ_IRQHandler, // 95: ADCETC Error IRQ interrupt
}; /* End of g_pfnVectors */
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors.init_data")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors.init_bss")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors.reset")))
void ResetISR(void) {
// Disable interrupts
__asm volatile ("cpsid i");
#if defined (__USE_CMSIS)
// If __USE_CMSIS defined, then call CMSIS SystemInit code
SystemInit();
#else
// Disable Watchdog
volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000;
*WDOG1_WCR = *WDOG1_WCR & ~(1 << 2);
volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000;
*WDOG2_WCR = *WDOG2_WCR & ~(1 << 2);
// Write watchdog update key to unlock
*((volatile unsigned int *)0x400BC004) = 0xD928C520;
// Set timeout value
*((volatile unsigned int *)0x400BC008) = 0xFFFF;
// Now disable watchdog via control register
volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000;
*RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5);
#endif // (__USE_CMSIS)
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if !defined (__USE_CMSIS)
// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
// will setup the VTOR register
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
#endif // (__USE_CMSIS)
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
// Reenable interrupts
__asm volatile ("cpsie i");
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default core exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
WEAK_AV void NMI_Handler(void)
{ while(1) {}
}
WEAK_AV void HardFault_Handler(void)
{ while(1) {}
}
WEAK_AV void SVC_Handler(void)
{ while(1) {}
}
WEAK_AV void PendSV_Handler(void)
{ while(1) {}
}
WEAK_AV void SysTick_Handler(void)
{ while(1) {}
}
//*****************************************************************************
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//*****************************************************************************
WEAK_AV void IntDefaultHandler(void)
{ while(1) {}
}
//*****************************************************************************
// Default application exception handlers. Override the ones here by defining
// your own handler routines in your application code. These routines call
// driver exception handlers or IntDefaultHandler() if no driver exception
// handler is included.
//*****************************************************************************
WEAK void DMA0_IRQHandler(void)
{ DMA0_DriverIRQHandler();
}
WEAK void DMA1_IRQHandler(void)
{ DMA1_DriverIRQHandler();
}
WEAK void DMA2_IRQHandler(void)
{ DMA2_DriverIRQHandler();
}
WEAK void DMA3_IRQHandler(void)
{ DMA3_DriverIRQHandler();
}
WEAK void DMA4_IRQHandler(void)
{ DMA4_DriverIRQHandler();
}
WEAK void DMA5_IRQHandler(void)
{ DMA5_DriverIRQHandler();
}
WEAK void DMA6_IRQHandler(void)
{ DMA6_DriverIRQHandler();
}
WEAK void DMA7_IRQHandler(void)
{ DMA7_DriverIRQHandler();
}
WEAK void DMA8_IRQHandler(void)
{ DMA8_DriverIRQHandler();
}
WEAK void DMA9_IRQHandler(void)
{ DMA9_DriverIRQHandler();
}
WEAK void DMA10_IRQHandler(void)
{ DMA10_DriverIRQHandler();
}
WEAK void DMA11_IRQHandler(void)
{ DMA11_DriverIRQHandler();
}
WEAK void DMA12_IRQHandler(void)
{ DMA12_DriverIRQHandler();
}
WEAK void DMA13_IRQHandler(void)
{ DMA13_DriverIRQHandler();
}
WEAK void DMA14_IRQHandler(void)
{ DMA14_DriverIRQHandler();
}
WEAK void DMA15_IRQHandler(void)
{ DMA15_DriverIRQHandler();
}
WEAK void DMA_ERROR_IRQHandler(void)
{ DMA_ERROR_DriverIRQHandler();
}
WEAK void CTI0_ERROR_IRQHandler(void)
{ CTI0_ERROR_DriverIRQHandler();
}
WEAK void CTI1_ERROR_IRQHandler(void)
{ CTI1_ERROR_DriverIRQHandler();
}
WEAK void CORE_IRQHandler(void)
{ CORE_DriverIRQHandler();
}
WEAK void LPUART1_IRQHandler(void)
{ LPUART1_DriverIRQHandler();
}
WEAK void LPUART2_IRQHandler(void)
{ LPUART2_DriverIRQHandler();
}
WEAK void LPUART3_IRQHandler(void)
{ LPUART3_DriverIRQHandler();
}
WEAK void LPUART4_IRQHandler(void)
{ LPUART4_DriverIRQHandler();
}
WEAK void PIT_IRQHandler(void)
{ PIT_DriverIRQHandler();
}
WEAK void USB_OTG1_IRQHandler(void)
{ USB_OTG1_DriverIRQHandler();
}
WEAK void FLEXSPI_IRQHandler(void)
{ FLEXSPI_DriverIRQHandler();
}
WEAK void FLEXRAM_IRQHandler(void)
{ FLEXRAM_DriverIRQHandler();
}
WEAK void LPI2C1_IRQHandler(void)
{ LPI2C1_DriverIRQHandler();
}
WEAK void LPI2C2_IRQHandler(void)
{ LPI2C2_DriverIRQHandler();
}
WEAK void GPT1_IRQHandler(void)
{ GPT1_DriverIRQHandler();
}
WEAK void GPT2_IRQHandler(void)
{ GPT2_DriverIRQHandler();
}
WEAK void LPSPI1_IRQHandler(void)
{ LPSPI1_DriverIRQHandler();
}
WEAK void LPSPI2_IRQHandler(void)
{ LPSPI2_DriverIRQHandler();
}
WEAK void PWM1_0_IRQHandler(void)
{ PWM1_0_DriverIRQHandler();
}
WEAK void PWM1_1_IRQHandler(void)
{ PWM1_1_DriverIRQHandler();
}
WEAK void PWM1_2_IRQHandler(void)
{ PWM1_2_DriverIRQHandler();
}
WEAK void PWM1_3_IRQHandler(void)
{ PWM1_3_DriverIRQHandler();
}
WEAK void PWM1_FAULT_IRQHandler(void)
{ PWM1_FAULT_DriverIRQHandler();
}
WEAK void KPP_IRQHandler(void)
{ KPP_DriverIRQHandler();
}
WEAK void SRC_IRQHandler(void)
{ SRC_DriverIRQHandler();
}
WEAK void GPR_IRQ_IRQHandler(void)
{ GPR_IRQ_DriverIRQHandler();
}
WEAK void CCM_1_IRQHandler(void)
{ CCM_1_DriverIRQHandler();
}
WEAK void CCM_2_IRQHandler(void)
{ CCM_2_DriverIRQHandler();
}
WEAK void EWM_IRQHandler(void)
{ EWM_DriverIRQHandler();
}
WEAK void WDOG2_IRQHandler(void)
{ WDOG2_DriverIRQHandler();
}
WEAK void SNVS_HP_WRAPPER_IRQHandler(void)
{ SNVS_HP_WRAPPER_DriverIRQHandler();
}
WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void)
{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler();
}
WEAK void SNVS_LP_WRAPPER_IRQHandler(void)
{ SNVS_LP_WRAPPER_DriverIRQHandler();
}
WEAK void CSU_IRQHandler(void)
{ CSU_DriverIRQHandler();
}
WEAK void DCP_IRQHandler(void)
{ DCP_DriverIRQHandler();
}
WEAK void DCP_VMI_IRQHandler(void)
{ DCP_VMI_DriverIRQHandler();
}
WEAK void Reserved68_IRQHandler(void)
{ Reserved68_DriverIRQHandler();
}
WEAK void TRNG_IRQHandler(void)
{ TRNG_DriverIRQHandler();
}
WEAK void Reserved70_IRQHandler(void)
{ Reserved70_DriverIRQHandler();
}
WEAK void Reserved71_IRQHandler(void)
{ Reserved71_DriverIRQHandler();
}
WEAK void SAI1_IRQHandler(void)
{ SAI1_DriverIRQHandler();
}
WEAK void RTWDOG_IRQHandler(void)
{ RTWDOG_DriverIRQHandler();
}
WEAK void SAI3_RX_IRQHandler(void)
{ SAI3_RX_DriverIRQHandler();
}
WEAK void SAI3_TX_IRQHandler(void)
{ SAI3_TX_DriverIRQHandler();
}
WEAK void SPDIF_IRQHandler(void)
{ SPDIF_DriverIRQHandler();
}
WEAK void PMU_IRQHandler(void)
{ PMU_DriverIRQHandler();
}
WEAK void XBAR1_IRQ_0_1_2_3_IRQHandler(void)
{ XBAR1_IRQ_0_1_2_3_DriverIRQHandler();
}
WEAK void TEMP_LOW_HIGH_IRQHandler(void)
{ TEMP_LOW_HIGH_DriverIRQHandler();
}
WEAK void TEMP_PANIC_IRQHandler(void)
{ TEMP_PANIC_DriverIRQHandler();
}
WEAK void USB_PHY_IRQHandler(void)
{ USB_PHY_DriverIRQHandler();
}
WEAK void GPC_IRQHandler(void)
{ GPC_DriverIRQHandler();
}
WEAK void ADC1_IRQHandler(void)
{ ADC1_DriverIRQHandler();
}
WEAK void FLEXIO1_IRQHandler(void)
{ FLEXIO1_DriverIRQHandler();
}
WEAK void DCDC_IRQHandler(void)
{ DCDC_DriverIRQHandler();
}
WEAK void GPIO1_Combined_0_15_IRQHandler(void)
{ GPIO1_Combined_0_15_DriverIRQHandler();
}
WEAK void GPIO1_Combined_16_31_IRQHandler(void)
{ GPIO1_Combined_16_31_DriverIRQHandler();
}
WEAK void GPIO2_Combined_0_15_IRQHandler(void)
{ GPIO2_Combined_0_15_DriverIRQHandler();
}
WEAK void GPIO5_Combined_0_15_IRQHandler(void)
{ GPIO5_Combined_0_15_DriverIRQHandler();
}
WEAK void WDOG1_IRQHandler(void)
{ WDOG1_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ0_IRQHandler(void)
{ ADC_ETC_IRQ0_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ1_IRQHandler(void)
{ ADC_ETC_IRQ1_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ2_IRQHandler(void)
{ ADC_ETC_IRQ2_DriverIRQHandler();
}
WEAK void ADC_ETC_IRQ3_IRQHandler(void)
{ ADC_ETC_IRQ3_DriverIRQHandler();
}
WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void)
{ ADC_ETC_ERROR_IRQ_DriverIRQHandler();
}
//*****************************************************************************
#if defined (DEBUG)
#pragma GCC pop_options
#endif // (DEBUG)

286
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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_debug_console.h"
#include "board.h"
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
#include "fsl_lpi2c.h"
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#include "fsl_iomuxc.h"
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/* Get debug console frequency. */
uint32_t BOARD_DebugConsoleSrcFreq(void)
{
uint32_t freq;
/* To make it simple, we assume default PLL and divider settings, and the only variable
from application is use PLL3 source or OSC source */
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
{
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
else
{
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}
return freq;
}
/* Initialize debug console. */
void BOARD_InitDebugConsole(void)
{
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
}
/* MPU configuration. */
void BOARD_ConfigMPU(void)
{
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
0 :
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
#endif
uint32_t i = 0;
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
{
SCB_DisableICache();
}
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
{
SCB_DisableDCache();
}
/* Disable MPU */
ARM_MPU_Disable();
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
#endif
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
while ((size >> i) > 0x1U)
{
i++;
}
if (i != 0)
{
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t)(1 << i));
assert(i >= 5);
/* Region 7 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(7, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
{
lpi2c_master_config_t lpi2cConfig = {0};
/*
* lpi2cConfig.debugEnable = false;
* lpi2cConfig.ignoreAck = false;
* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
* lpi2cConfig.baudRate_Hz = 100000U;
* lpi2cConfig.busIdleTimeout_ns = 0;
* lpi2cConfig.pinLowTimeout_ns = 0;
* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
*/
LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
}
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *txBuff,
uint8_t txBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Write;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = txBuff;
xfer.dataSize = txBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subAddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize)
{
lpi2c_master_transfer_t xfer;
xfer.flags = kLPI2C_TransferDefaultFlag;
xfer.slaveAddress = deviceAddress;
xfer.direction = kLPI2C_Read;
xfer.subaddress = subAddress;
xfer.subaddressSize = subAddressSize;
xfer.data = rxBuff;
xfer.dataSize = rxBuffSize;
return LPI2C_MasterTransferBlocking(base, &xfer);
}
void BOARD_Accel_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
}
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
{
uint8_t data = (uint8_t)txBuff;
return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
}
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
}
void BOARD_Codec_I2C_Init(void)
{
BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
}
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
{
return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
txBuffSize);
}
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
{
return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
}
#endif /*SDK_I2C_BASED_COMPONENT_USED */
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* SystemInitHook */
void SystemInitHook(void)
{
/* When set this bit, FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. */
FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK;
}
#endif

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include "clock_config.h"
#include "fsl_common.h"
#include "fsl_gpio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief The board name */
#define BOARD_NAME "MIMXRT1010-EVK"
/* The UART to use for debug messages. */
#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
#define BOARD_DEBUG_UART_INSTANCE 1U
#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
#define BOARD_UART_IRQ LPUART1_IRQn
#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
#ifndef BOARD_DEBUG_UART_BAUDRATE
#define BOARD_DEBUG_UART_BAUDRATE (115200U)
#endif /* BOARD_DEBUG_UART_BAUDRATE */
/* @Brief Board accelerator sensor configuration */
#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
#define BOARD_CODEC_I2C_BASEADDR LPI2C1
#define BOARD_CODEC_I2C_INSTANCE 1U
#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
/*! @brief The USER_LED used for board */
#define LOGIC_LED_ON (0U)
#define LOGIC_LED_OFF (1U)
#ifndef BOARD_USER_LED_GPIO
#define BOARD_USER_LED_GPIO GPIO1
#endif
#ifndef BOARD_USER_LED_GPIO_PIN
#define BOARD_USER_LED_GPIO_PIN (11U)
#endif
#define USER_LED_INIT(output) \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
#define USER_LED_OFF() \
GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
#define USER_LED_ON() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
#define USER_LED_TOGGLE() \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
/*! @brief Define the port interrupt number for the board switches */
#ifndef BOARD_USER_BUTTON_GPIO
#define BOARD_USER_BUTTON_GPIO GPIO2
#endif
#ifndef BOARD_USER_BUTTON_GPIO_PIN
#define BOARD_USER_BUTTON_GPIO_PIN (5U)
#endif
#define BOARD_USER_BUTTON_IRQ GPIO2_Combined_0_15_IRQn
#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO2_Combined_0_15_IRQHandler
#define BOARD_USER_BUTTON_NAME "SW4"
/*! @brief The flash size */
#define BOARD_FLASH_SIZE (0x1000000U)
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
#define BOARD_ARDUINO_I2C_INDEX (1)
/*! @brief The WIFI-QCA shield pin. */
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 8U /*!< PIO1 pin index: 8 */
#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_08 /*!< Pin name */
#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 4U /*!< PIO1 pin index: 4 */
#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_04 /*!< Pin name */
#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* API
******************************************************************************/
uint32_t BOARD_DebugConsoleSrcFreq(void);
void BOARD_InitDebugConsole(void);
void BOARD_ConfigMPU(void);
#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
void BOARD_InitDebugConsole(void);
void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
status_t BOARD_LPI2C_Send(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *txBuff,
uint8_t txBuffSize);
status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
uint8_t deviceAddress,
uint32_t subAddress,
uint8_t subaddressSize,
uint8_t *rxBuff,
uint8_t rxBuffSize);
void BOARD_Accel_I2C_Init(void);
status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
status_t BOARD_Accel_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
void BOARD_Codec_I2C_Init(void);
status_t BOARD_Codec_I2C_Send(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
status_t BOARD_Codec_I2C_Receive(
uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
#endif /* SDK_I2C_BASED_COMPONENT_USED */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _BOARD_H_ */

345
platform/vendor_bsp/nxp/MIMXRT1011/project_template/clock_config.c
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@@ -1,345 +0,0 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v6.0
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 0.0.1
board: MIMXRT1010-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
settings:
- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
- {id: CCM_ANALOG.PLL2.div, value: '22'}
- {id: CCM_ANALOG.PLL2.num, value: '0'}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Xbar1);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
#endif
/* Disable ADC_ACLK_EN clock gate. */
CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
/* Set ADC_ACLK_PODF. */
CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

104
platform/vendor_bsp/nxp/MIMXRT1011/project_template/clock_config.h
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@@ -1,104 +0,0 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

51
platform/vendor_bsp/nxp/MIMXRT1011/project_template/peripherals.c
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@@ -1,51 +0,0 @@
/*
* Copyright 2019 NXP.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Peripherals v6.0
processor: MIMXRT1011xxxxx
mcu_data: ksdk2_0
processor_version: 0.0.8
functionalGroups:
- name: BOARD_InitPeripherals
called_from_default_init: true
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
component:
- type: 'system'
- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
- global_system_definitions: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */
/***********************************************************************************************************************
* Included files
**********************************************************************************************************************/
#include "peripherals.h"
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void)
{
}
/***********************************************************************************************************************
* BOARD_InitBootPeripherals function
**********************************************************************************************************************/
void BOARD_InitBootPeripherals(void)
{
BOARD_InitPeripherals();
}

34
platform/vendor_bsp/nxp/MIMXRT1011/project_template/peripherals.h
View File

@@ -1,34 +0,0 @@
/*
* Copyright 2019 NXP.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PERIPHERALS_H_
#define _PERIPHERALS_H_
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/***********************************************************************************************************************
* Initialization functions
**********************************************************************************************************************/
void BOARD_InitPeripherals(void);
/***********************************************************************************************************************
* BOARD_InitBootPeripherals function
**********************************************************************************************************************/
void BOARD_InitBootPeripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* _PERIPHERALS_H_ */

55
platform/vendor_bsp/nxp/MIMXRT1011/project_template/pin_mux.c
View File

@@ -1,55 +0,0 @@
/*
* Copyright 2019 NXP.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v6.0
processor: MIMXRT1011xxxxx
mcu_data: ksdk2_0
processor_version: 0.0.8
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', enableClock: 'true'}
- pin_list: []
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

65
platform/vendor_bsp/nxp/MIMXRT1011/project_template/pin_mux.h
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@@ -1,65 +0,0 @@
/*
* Copyright 2019 NXP.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

60
platform/vendor_bsp/nxp/MIMXRT1011/template/RTE_Device.h
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@@ -1,60 +0,0 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2019 , NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
/* UART Select, UART0 - UART5. */
#define RTE_USART1 1
#define RTE_USART1_DMA_EN 1
#define RTE_USART2 0
#define RTE_USART2_DMA_EN 0
#define RTE_USART3 0
#define RTE_USART3_DMA_EN 0
#define RTE_USART4 0
#define RTE_USART4_DMA_EN 0
/* UART configuration. */
#define RTE_USART1_DMA_TX_CH 0
#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Tx
#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX
#define RTE_USART1_DMA_TX_DMA_BASE DMA0
#define RTE_USART1_DMA_RX_CH 1
#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Rx
#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX
#define RTE_USART1_DMA_RX_DMA_BASE DMA0
#define RTE_USART2_DMA_TX_CH 2
#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Tx
#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX
#define RTE_USART2_DMA_TX_DMA_BASE DMA0
#define RTE_USART2_DMA_RX_CH 3
#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Rx
#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX
#define RTE_USART2_DMA_RX_DMA_BASE DMA0
#define RTE_USART3_DMA_TX_CH 4
#define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Tx
#define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX
#define RTE_USART3_DMA_TX_DMA_BASE DMA0
#define RTE_USART3_DMA_RX_CH 5
#define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Rx
#define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX
#define RTE_USART3_DMA_RX_DMA_BASE DMA0
#define RTE_USART4_DMA_TX_CH 6
#define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Tx
#define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX
#define RTE_USART4_DMA_TX_DMA_BASE DMA0
#define RTE_USART4_DMA_RX_CH 7
#define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Rx
#define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX
#define RTE_USART4_DMA_RX_DMA_BASE DMA0
#endif /* __RTE_DEVICE_H */

0
platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.ini → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.ini
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvoptx → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvoptx
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvprojx → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example.uvprojx
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c
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0
platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c
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0
platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s
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0
platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example.ini → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example.ini
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example.uvoptx → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example.uvoptx
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example.uvprojx → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example.uvprojx
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.ini → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.ini
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvoptx → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvoptx
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvprojx → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example.uvprojx
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c
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platform/vendor_bsp/nxp/MIMXRT1052_ver270/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s → platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s
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