PowLu/TencentOS-tiny
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

1. Updated the BSP for i.MX RT1050

Browse Source 
2. Added the Keil Workspace
3. Changed the hello_world.c for RT1050

Signed-off-by: Howard Liu <howardliu7874@hotmail.com>
This commit is contained in:
Howard Liu
2020-01-18 19:35:05 +08:00
parent 91c470239d
commit d8f32035a1
1073 changed files with 103162 additions and 429588 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
board/NXP_EVKB_IMXRT1050/BSP/Inc/pin_mux.h
View File

@@ -52,7 +52,10 @@ void BOARD_InitBootPins(void);
#define BOARD_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
#define BOARD_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5]/USER_LED */
#define BOARD_USER_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_USER_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_USER_LED_PIN 9U /*!< GPIO1 pin index: 9 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*

47
board/NXP_EVKB_IMXRT1050/BSP/Src/hello_world.c
View File

@@ -16,7 +16,8 @@
/*******************************************************************************
* Definitions
******************************************************************************/
#define EXAMPLE_LED_GPIO BOARD_USER_LED_GPIO
#define EXAMPLE_LED_GPIO_PIN BOARD_USER_LED_PIN
/*******************************************************************************
* Prototypes
@@ -33,29 +34,40 @@ osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
void task2(void *arg);
osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
void task1(void *arg)
{
int count = 0;
while(1)
{
PRINTF("********This is Task 1, count is %d \r\n",count++);
osDelay(1000);
}
/* The PIN status */
static volatile bool g_pinSet = false;
int count = 0;
while(1)
{
PRINTF("++++++++This is Task 1, count is %d \r\n",count++);
if (g_pinSet)
{
GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 0U);
g_pinSet = false;
}
else
{
GPIO_PinWrite(EXAMPLE_LED_GPIO, EXAMPLE_LED_GPIO_PIN, 1U);
g_pinSet = true;
}
/* Delay 1000 ms */
osDelay(1000U);
}
}
void task2(void *arg)
{
int count = 0;
while(1)
{
PRINTF("++++++++This is Task 2, count is %d \r\n",count++);
osDelay(2000);
}
int count = 0;
while(1)
{
PRINTF("********This is Task 2, count is %d \r\n",count++);
osDelay(2000U);
}
}
/*!
* @brief Main function
*/
@@ -67,10 +79,11 @@ int main(void)
BOARD_InitBootClocks();
BOARD_InitDebugConsole();
PRINTF("hello world.\r\n");
PRINTF("Hello world from i.MX RT1050.\r\n");
PRINTF("Welcome to TencentOS tiny\r\n");
osKernelInitialize(); // TencentOS Tiny kernel initialize
osThreadCreate(osThread(task1), NULL); // Create task1
osThreadCreate(osThread(task2), NULL); // Create task2
osKernelStart(); // Start TencentOS Tiny
return 0;
}

25
board/NXP_EVKB_IMXRT1050/BSP/Src/pin_mux.c
View File

@@ -24,6 +24,7 @@ board: IMXRT1050-EVKB
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
@@ -83,6 +84,30 @@ void BOARD_InitPins(void) {
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
/* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0x10B0U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
}
/***********************************************************************************************************************

87
board/NXP_EVKB_IMXRT1050/IAR/hello_world/evkbimxrt1050.mac Normal file
View File

@@ -0,0 +1,87 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
_load_dcdc_trim()
{
__var ocotp_base;
__var ocotp_fuse_bank0_base;
__var dcdc_base;
__var reg;
__var trim_value;
__var dcdc_trim_loaded;
__var index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
dcdc_trim_loaded = 1;
}
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay 1ms for dcdc to get stable
__delay(1);
__message "DCDC trim value loaded.\n";
}
}
execUserPreload()
{
_load_dcdc_trim();
}
execUserReset()
{
_load_dcdc_trim();
}

261
board/NXP_EVKB_IMXRT1050/IAR/hello_world/evkbimxrt1050_sdram_init.mac Normal file
View File

@@ -0,0 +1,261 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
_load_dcdc_trim()
{
__var dcdc_trim_loaded;
__var ocotp_base;
__var ocotp_fuse_bank0_base;
__var dcdc_base;
__var reg;
__var trim_value;
__var index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory");
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24);
__writeMemory32(reg, dcdc_base + 0x4, "Memory");
dcdc_trim_loaded = 1;
}
reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory");
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index);
__writeMemory32(reg, dcdc_base + 0xC, "Memory");
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay 1ms for dcdc to get stable
__delay(1);
__message "DCDC trim value loaded.\n";
}
}
SDRAM_WaitIpCmdDone()
{
__var reg;
do
{
reg = __readMemory32(0x402F003C, "Memory");
}while((reg & 0x3) == 0);
__writeMemory32(0x00000003, 0x402F003C, "Memory"); // clear IPCMDERR and IPCMDDONE bits
}
_clock_init()
{
__var reg;
// Enable all clocks
__writeMemory32(0xffffffff, 0x400FC068, "Memory");
__writeMemory32(0xffffffff, 0x400FC06C, "Memory");
__writeMemory32(0xffffffff, 0x400FC070, "Memory");
__writeMemory32(0xffffffff, 0x400FC074, "Memory");
__writeMemory32(0xffffffff, 0x400FC078, "Memory");
__writeMemory32(0xffffffff, 0x400FC07C, "Memory");
__writeMemory32(0xffffffff, 0x400FC080, "Memory");
// PERCLK_PODF: 1 divide by 2
__writeMemory32(0x04900001, 0x400FC01C, "Memory");
// Enable SYS PLL but keep it bypassed.
__writeMemory32(0x00012001, 0x400D8030, "Memory");
do
{
reg = __readMemory32(0x400D8030, "Memory");
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
__writeMemory32(0x00002001, 0x400D8030, "Memory");
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
__writeMemory32(0x001d0000, 0x400D8100, "Memory");
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
__writeMemory32(0x00010D40, 0x400FC014, "Memory");
__message "clock init done\n";
}
_sdr_Init()
{
// Config IOMUX
__writeMemory32(0x00000000, 0x401F8014, "Memory");
__writeMemory32(0x00000000, 0x401F8018, "Memory");
__writeMemory32(0x00000000, 0x401F801C, "Memory");
__writeMemory32(0x00000000, 0x401F8020, "Memory");
__writeMemory32(0x00000000, 0x401F8024, "Memory");
__writeMemory32(0x00000000, 0x401F8028, "Memory");
__writeMemory32(0x00000000, 0x401F802C, "Memory");
__writeMemory32(0x00000000, 0x401F8030, "Memory");
__writeMemory32(0x00000000, 0x401F8034, "Memory");
__writeMemory32(0x00000000, 0x401F8038, "Memory");
__writeMemory32(0x00000000, 0x401F803C, "Memory");
__writeMemory32(0x00000000, 0x401F8040, "Memory");
__writeMemory32(0x00000000, 0x401F8044, "Memory");
__writeMemory32(0x00000000, 0x401F8048, "Memory");
__writeMemory32(0x00000000, 0x401F804C, "Memory");
__writeMemory32(0x00000000, 0x401F8050, "Memory");
__writeMemory32(0x00000000, 0x401F8054, "Memory");
__writeMemory32(0x00000000, 0x401F8058, "Memory");
__writeMemory32(0x00000000, 0x401F805C, "Memory");
__writeMemory32(0x00000000, 0x401F8060, "Memory");
__writeMemory32(0x00000000, 0x401F8064, "Memory");
__writeMemory32(0x00000000, 0x401F8068, "Memory");
__writeMemory32(0x00000000, 0x401F806C, "Memory");
__writeMemory32(0x00000000, 0x401F8070, "Memory");
__writeMemory32(0x00000000, 0x401F8074, "Memory");
__writeMemory32(0x00000000, 0x401F8078, "Memory");
__writeMemory32(0x00000000, 0x401F807C, "Memory");
__writeMemory32(0x00000000, 0x401F8080, "Memory");
__writeMemory32(0x00000000, 0x401F8084, "Memory");
__writeMemory32(0x00000000, 0x401F8088, "Memory");
__writeMemory32(0x00000000, 0x401F808C, "Memory");
__writeMemory32(0x00000000, 0x401F8090, "Memory");
__writeMemory32(0x00000000, 0x401F8094, "Memory");
__writeMemory32(0x00000000, 0x401F8098, "Memory");
__writeMemory32(0x00000000, 0x401F809C, "Memory");
__writeMemory32(0x00000000, 0x401F80A0, "Memory");
__writeMemory32(0x00000000, 0x401F80A4, "Memory");
__writeMemory32(0x00000000, 0x401F80A8, "Memory");
__writeMemory32(0x00000000, 0x401F80AC, "Memory");
__writeMemory32(0x00000010, 0x401F80B0, "Memory"); // EMC_39, DQS PIN, enable SION
__writeMemory32(0x00000000, 0x401F80B4, "Memory");
__writeMemory32(0x00000000, 0x401F80B8, "Memory");
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
__writeMemory32(0x000110F9, 0x401F8204, "Memory");
__writeMemory32(0x000110F9, 0x401F8208, "Memory");
__writeMemory32(0x000110F9, 0x401F820C, "Memory");
__writeMemory32(0x000110F9, 0x401F8210, "Memory");
__writeMemory32(0x000110F9, 0x401F8214, "Memory");
__writeMemory32(0x000110F9, 0x401F8218, "Memory");
__writeMemory32(0x000110F9, 0x401F821C, "Memory");
__writeMemory32(0x000110F9, 0x401F8220, "Memory");
__writeMemory32(0x000110F9, 0x401F8224, "Memory");
__writeMemory32(0x000110F9, 0x401F8228, "Memory");
__writeMemory32(0x000110F9, 0x401F822C, "Memory");
__writeMemory32(0x000110F9, 0x401F8230, "Memory");
__writeMemory32(0x000110F9, 0x401F8234, "Memory");
__writeMemory32(0x000110F9, 0x401F8238, "Memory");
__writeMemory32(0x000110F9, 0x401F823C, "Memory");
__writeMemory32(0x000110F9, 0x401F8240, "Memory");
__writeMemory32(0x000110F9, 0x401F8244, "Memory");
__writeMemory32(0x000110F9, 0x401F8248, "Memory");
__writeMemory32(0x000110F9, 0x401F824C, "Memory");
__writeMemory32(0x000110F9, 0x401F8250, "Memory");
__writeMemory32(0x000110F9, 0x401F8254, "Memory");
__writeMemory32(0x000110F9, 0x401F8258, "Memory");
__writeMemory32(0x000110F9, 0x401F825C, "Memory");
__writeMemory32(0x000110F9, 0x401F8260, "Memory");
__writeMemory32(0x000110F9, 0x401F8264, "Memory");
__writeMemory32(0x000110F9, 0x401F8268, "Memory");
__writeMemory32(0x000110F9, 0x401F826C, "Memory");
__writeMemory32(0x000110F9, 0x401F8270, "Memory");
__writeMemory32(0x000110F9, 0x401F8274, "Memory");
__writeMemory32(0x000110F9, 0x401F8278, "Memory");
__writeMemory32(0x000110F9, 0x401F827C, "Memory");
__writeMemory32(0x000110F9, 0x401F8280, "Memory");
__writeMemory32(0x000110F9, 0x401F8284, "Memory");
__writeMemory32(0x000110F9, 0x401F8288, "Memory");
__writeMemory32(0x000110F9, 0x401F828C, "Memory");
__writeMemory32(0x000110F9, 0x401F8290, "Memory");
__writeMemory32(0x000110F9, 0x401F8294, "Memory");
__writeMemory32(0x000110F9, 0x401F8298, "Memory");
__writeMemory32(0x000110F9, 0x401F829C, "Memory");
__writeMemory32(0x000110F9, 0x401F82A0, "Memory");
__writeMemory32(0x000110F9, 0x401F82A4, "Memory");
__writeMemory32(0x000110F9, 0x401F82A8, "Memory");
// Config SDR Controller Registers/
__writeMemory32(0x10000004, 0x402F0000, "Memory"); // MCR
__writeMemory32(0x00030524, 0x402F0008, "Memory"); // BMCR0
__writeMemory32(0x06030524, 0x402F000C, "Memory"); // BMCR1
__writeMemory32(0x8000001B, 0x402F0010, "Memory"); // BR0, 32MB
__writeMemory32(0x00000F31, 0x402F0040, "Memory"); // SDRAMCR0
__writeMemory32(0x00662A22, 0x402F0044, "Memory"); // SDRAMCR1
__writeMemory32(0x000A0A0A, 0x402F0048, "Memory"); // SDRAMCR2
__writeMemory32(0x08080A00, 0x402F004C, "Memory"); // SDRAMCR3
__writeMemory32(0x80000000, 0x402F0090, "Memory"); // IPCR0
__writeMemory32(0x00000002, 0x402F0094, "Memory"); // IPCR1
__writeMemory32(0x00000000, 0x402F0098, "Memory"); // IPCR2
__writeMemory32(0xA55A000F, 0x402F009C, "Memory"); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
__writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
__writeMemory32(0xA55A000C, 0x402F009C, "Memory"); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
__writeMemory32(0x00000033, 0x402F00A0, "Memory"); // IPTXDAT
__writeMemory32(0xA55A000A, 0x402F009C, "Memory"); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
__writeMemory32(0x08080A01, 0x402F004C, "Memory"); // enable sdram self refresh after initialization done.
__message "SDRAM init done\n";
}
execUserPreload()
{
_load_dcdc_trim();
_clock_init();
_sdr_Init();
__message "execUserPreload() done.\n";
}
execUserReset()
{
_load_dcdc_trim();
_clock_init();
_sdr_Init();
__message "execUserReset() done.\n";
}

14
board/NXP_EVKB_IMXRT1050/IAR/hello_world/hello_world.ewd
View File

@@ -1529,7 +1529,7 @@
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MK70FN1M0xxx12.ddf</state>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1052xxx6B.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@@ -1573,7 +1573,7 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>7.80.4.12487</state>
<state>8.40.2.22864</state>
</option>
<option>
<name>UseFlashLoader</name>
@@ -1597,7 +1597,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashK70Fxxx128K.board</state>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@@ -3014,7 +3014,7 @@
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MK70FN1M0xxx12.ddf</state>
<state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\MIMXRT1052xxx6B.ddf</state>
</option>
<option>
<name>RunToEnable</name>
@@ -3058,7 +3058,7 @@
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>7.80.4.12487</state>
<state>8.40.2.22864</state>
</option>
<option>
<name>UseFlashLoader</name>
@@ -3082,7 +3082,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashK70Fxxx128K.board</state>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1050_EVK_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@@ -3270,7 +3270,7 @@
<option>
<name>CMSISDAPResetList</name>
<version>1</version>
<state>5</state>
<state>4</state>
</option>
<option>
<name>CMSISDAPHWResetDuration</name>

231
board/NXP_EVKB_IMXRT1050/IAR/hello_world/hello_world.ewp
View File

@@ -354,14 +354,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -1435,14 +1435,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -2515,14 +2515,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -3598,14 +3598,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -4678,14 +4678,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -5757,14 +5757,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -6836,14 +6836,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -7917,14 +7917,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -8997,14 +8997,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -10080,14 +10080,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -11160,14 +11160,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -12239,14 +12239,14 @@
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/..</state>
<state>$PROJ_DIR$/../../..</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager</state>
<state>$PROJ_DIR$\..\..\BSP\Inc</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270</state>
<state>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052</state>
<state>$PROJ_DIR$\..\..\..\..\kernel\core\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\common\include</state>
<state>$PROJ_DIR$\..\..\..\..\arch\arm\arm-v7m\cortex-m7\iccarm</state>
@@ -12970,83 +12970,83 @@
<group>
<name>serial_manager</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_manager.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_manager.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_manager.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_manager.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_port_internal.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_port_internal.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_port_uart.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_port_uart.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\serial_manager\serial_port_uart.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\serial_manager\serial_port_uart.h</name>
</file>
</group>
<group>
<name>uart</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart\lpuart_adapter.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart\lpuart_adapter.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\components\uart\uart.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\components\uart\uart.h</name>
</file>
</group>
</group>
<group>
<name>device</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\fsl_device_registers.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\fsl_device_registers.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\MIMXRT1052.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\MIMXRT1052.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\MIMXRT1052_features.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\MIMXRT1052_features.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\system_MIMXRT1052.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\system_MIMXRT1052.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\system_MIMXRT1052.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\system_MIMXRT1052.h</name>
</file>
</group>
<group>
<name>drivers</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_clock.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_clock.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_clock.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_clock.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_common.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_common.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_common.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_common.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_gpio.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_gpio.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_gpio.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_gpio.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_iomuxc.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_iomuxc.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_lpuart.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_lpuart.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\drivers\fsl_lpuart.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_lpuart.h</name>
</file>
</group>
<group>
<name>startup</name>
<file>
<name>$PROJ_DIR$\startup_MIMXRT1052.s</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\iar\startup_MIMXRT1052.s</name>
</file>
</group>
<group>
@@ -13282,26 +13282,29 @@
<file>
<name>$PROJ_DIR$\..\..\BSP\Inc\pin_mux.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\TOS_CONFIG\tos_config.h</name>
</file>
</group>
<group>
<name>utilities</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\fsl_assert.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_assert.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console\fsl_debug_console.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console\fsl_debug_console.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console\fsl_debug_console.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console\fsl_debug_console.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\debug_console\fsl_debug_console_conf.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\debug_console\fsl_debug_console_conf.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str\fsl_str.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str\fsl_str.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\utilities\str\fsl_str.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str\fsl_str.h</name>
</file>
</group>
<group>
@@ -13319,10 +13322,10 @@
<name>$PROJ_DIR$\..\..\BSP\Inc\evkbimxrt1050_sdram_ini_dcd.h</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\xip\fsl_flexspi_nor_boot.c</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\xip\fsl_flexspi_nor_boot.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052_ver270\xip\fsl_flexspi_nor_boot.h</name>
<name>$PROJ_DIR$\..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\xip\fsl_flexspi_nor_boot.h</name>
</file>
</group>
</project>

69
board/NXP_EVKB_IMXRT1050/IAR/hello_world/readme.txt Normal file
View File

@@ -0,0 +1,69 @@
Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1050.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================

972
board/NXP_EVKB_IMXRT1050/IAR/hello_world/startup_MIMXRT1052.s
View File

@@ -1,972 +0,0 @@
; -------------------------------------------------------------------------
; @file: startup_MIMXRT1052.s
; @purpose: CMSIS Cortex-M7 Core Device Startup File
; MIMXRT1052
; @version: 1.3
; @date: 2019-4-29
; @build: b190919
; -------------------------------------------------------------------------
;
; Copyright 1997-2016 Freescale Semiconductor, Inc.
; Copyright 2016-2019 NXP
; All rights reserved.
;
; SPDX-License-Identifier: BSD-3-Clause
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
__vector_table_0x1c
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete
DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete
DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete
DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete
DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete
DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete
DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete
DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete
DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete
DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete
DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete
DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete
DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete
DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete
DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete
DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete
DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31
DCD CTI0_ERROR_IRQHandler ;CTI0_Error
DCD CTI1_ERROR_IRQHandler ;CTI1_Error
DCD CORE_IRQHandler ;CorePlatform exception IRQ
DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt
DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt
DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt
DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt
DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt
DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt
DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt
DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt
DCD LPI2C1_IRQHandler ;LPI2C1 interrupt
DCD LPI2C2_IRQHandler ;LPI2C2 interrupt
DCD LPI2C3_IRQHandler ;LPI2C3 interrupt
DCD LPI2C4_IRQHandler ;LPI2C4 interrupt
DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources
DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources
DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources
DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources
DCD CAN1_IRQHandler ;CAN1 interrupt
DCD CAN2_IRQHandler ;CAN2 interrupt
DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ
DCD KPP_IRQHandler ;Keypad nterrupt
DCD TSC_DIG_IRQHandler ;TSC interrupt
DCD GPR_IRQ_IRQHandler ;GPR interrupt
DCD LCDIF_IRQHandler ;LCDIF interrupt
DCD CSI_IRQHandler ;CSI interrupt
DCD PXP_IRQHandler ;PXP interrupt
DCD WDOG2_IRQHandler ;WDOG2 interrupt
DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ
DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ
DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event)
DCD CSU_IRQHandler ;CSU interrupt
DCD DCP_IRQHandler ;DCP_IRQ interrupt
DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt
DCD Reserved68_IRQHandler ;Reserved interrupt
DCD TRNG_IRQHandler ;TRNG interrupt
DCD SJC_IRQHandler ;SJC interrupt
DCD BEE_IRQHandler ;BEE interrupt
DCD SAI1_IRQHandler ;SAI1 interrupt
DCD SAI2_IRQHandler ;SAI1 interrupt
DCD SAI3_RX_IRQHandler ;SAI3 interrupt
DCD SAI3_TX_IRQHandler ;SAI3 interrupt
DCD SPDIF_IRQHandler ;SPDIF interrupt
DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt
DCD Reserved78_IRQHandler ;Reserved interrupt
DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt
DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt
DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
DCD ADC2_IRQHandler ;ADC2 interrupt
DCD DCDC_IRQHandler ;DCDC interrupt
DCD Reserved86_IRQHandler ;Reserved interrupt
DCD Reserved87_IRQHandler ;Reserved interrupt
DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO
DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO
DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO
DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO
DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO
DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO
DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO
DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO
DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15
DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31
DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15
DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31
DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15
DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31
DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15
DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31
DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15
DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31
DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt
DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt
DCD WDOG1_IRQHandler ;WDOG1 interrupt
DCD RTWDOG_IRQHandler ;RTWDOG interrupt
DCD EWM_IRQHandler ;EWM interrupt
DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt
DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt
DCD GPC_IRQHandler ;GPC interrupt
DCD SRC_IRQHandler ;SRC interrupt
DCD Reserved115_IRQHandler ;Reserved interrupt
DCD GPT1_IRQHandler ;GPT1 interrupt
DCD GPT2_IRQHandler ;GPT2 interrupt
DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt
DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt
DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt
DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt
DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt
DCD Reserved123_IRQHandler ;Reserved interrupt
DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt
DCD SEMC_IRQHandler ;Reserved interrupt
DCD USDHC1_IRQHandler ;USDHC1 interrupt
DCD USDHC2_IRQHandler ;USDHC2 interrupt
DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2
DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1
DCD ENET_IRQHandler ;ENET interrupt
DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt
DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt
DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt
DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt
DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt
DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt
DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt
DCD PIT_IRQHandler ;PIT interrupt
DCD ACMP1_IRQHandler ;ACMP interrupt
DCD ACMP2_IRQHandler ;ACMP interrupt
DCD ACMP3_IRQHandler ;ACMP interrupt
DCD ACMP4_IRQHandler ;ACMP interrupt
DCD Reserved143_IRQHandler ;Reserved interrupt
DCD Reserved144_IRQHandler ;Reserved interrupt
DCD ENC1_IRQHandler ;ENC1 interrupt
DCD ENC2_IRQHandler ;ENC2 interrupt
DCD ENC3_IRQHandler ;ENC3 interrupt
DCD ENC4_IRQHandler ;ENC4 interrupt
DCD TMR1_IRQHandler ;TMR1 interrupt
DCD TMR2_IRQHandler ;TMR2 interrupt
DCD TMR3_IRQHandler ;TMR3 interrupt
DCD TMR4_IRQHandler ;TMR4 interrupt
DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt
DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt
DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt
DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt
DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt
DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt
DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt
DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt
DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt
DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt
DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt
DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt
DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt
DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt
DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
DCD DefaultISR ;240
DCD DefaultISR ;241
DCD DefaultISR ;242
DCD DefaultISR ;243
DCD DefaultISR ;244
DCD DefaultISR ;245
DCD DefaultISR ;246
DCD DefaultISR ;247
DCD DefaultISR ;248
DCD DefaultISR ;249
DCD DefaultISR ;250
DCD DefaultISR ;251
DCD DefaultISR ;252
DCD DefaultISR ;253
DCD DefaultISR ;254
DCD 0xFFFFFFFF ; Reserved for user TRIM value
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__vector_table
STR R1, [R0]
LDR R2, [R1]
MSR MSP, R2
LDR R0, =SystemInit
BLX R0
CPSIE I ; Unmask interrupts
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B .
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B .
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK DMA0_DMA16_IRQHandler
PUBWEAK DMA0_DMA16_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA0_DMA16_IRQHandler
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
PUBWEAK DMA1_DMA17_IRQHandler
PUBWEAK DMA1_DMA17_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA1_DMA17_IRQHandler
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
PUBWEAK DMA2_DMA18_IRQHandler
PUBWEAK DMA2_DMA18_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA2_DMA18_IRQHandler
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
PUBWEAK DMA3_DMA19_IRQHandler
PUBWEAK DMA3_DMA19_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA3_DMA19_IRQHandler
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
PUBWEAK DMA4_DMA20_IRQHandler
PUBWEAK DMA4_DMA20_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA4_DMA20_IRQHandler
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
PUBWEAK DMA5_DMA21_IRQHandler
PUBWEAK DMA5_DMA21_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA5_DMA21_IRQHandler
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
PUBWEAK DMA6_DMA22_IRQHandler
PUBWEAK DMA6_DMA22_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA6_DMA22_IRQHandler
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
PUBWEAK DMA7_DMA23_IRQHandler
PUBWEAK DMA7_DMA23_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA7_DMA23_IRQHandler
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
PUBWEAK DMA8_DMA24_IRQHandler
PUBWEAK DMA8_DMA24_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA8_DMA24_IRQHandler
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
PUBWEAK DMA9_DMA25_IRQHandler
PUBWEAK DMA9_DMA25_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA9_DMA25_IRQHandler
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
PUBWEAK DMA10_DMA26_IRQHandler
PUBWEAK DMA10_DMA26_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA10_DMA26_IRQHandler
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
PUBWEAK DMA11_DMA27_IRQHandler
PUBWEAK DMA11_DMA27_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA11_DMA27_IRQHandler
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
PUBWEAK DMA12_DMA28_IRQHandler
PUBWEAK DMA12_DMA28_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA12_DMA28_IRQHandler
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
PUBWEAK DMA13_DMA29_IRQHandler
PUBWEAK DMA13_DMA29_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA13_DMA29_IRQHandler
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
PUBWEAK DMA14_DMA30_IRQHandler
PUBWEAK DMA14_DMA30_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA14_DMA30_IRQHandler
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
PUBWEAK DMA15_DMA31_IRQHandler
PUBWEAK DMA15_DMA31_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA15_DMA31_IRQHandler
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
PUBWEAK DMA_ERROR_IRQHandler
PUBWEAK DMA_ERROR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DMA_ERROR_IRQHandler
LDR R0, =DMA_ERROR_DriverIRQHandler
BX R0
PUBWEAK CTI0_ERROR_IRQHandler
PUBWEAK CTI1_ERROR_IRQHandler
PUBWEAK CORE_IRQHandler
PUBWEAK LPUART1_IRQHandler
PUBWEAK LPUART1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART1_IRQHandler
LDR R0, =LPUART1_DriverIRQHandler
BX R0
PUBWEAK LPUART2_IRQHandler
PUBWEAK LPUART2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART2_IRQHandler
LDR R0, =LPUART2_DriverIRQHandler
BX R0
PUBWEAK LPUART3_IRQHandler
PUBWEAK LPUART3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART3_IRQHandler
LDR R0, =LPUART3_DriverIRQHandler
BX R0
PUBWEAK LPUART4_IRQHandler
PUBWEAK LPUART4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART4_IRQHandler
LDR R0, =LPUART4_DriverIRQHandler
BX R0
PUBWEAK LPUART5_IRQHandler
PUBWEAK LPUART5_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART5_IRQHandler
LDR R0, =LPUART5_DriverIRQHandler
BX R0
PUBWEAK LPUART6_IRQHandler
PUBWEAK LPUART6_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART6_IRQHandler
LDR R0, =LPUART6_DriverIRQHandler
BX R0
PUBWEAK LPUART7_IRQHandler
PUBWEAK LPUART7_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART7_IRQHandler
LDR R0, =LPUART7_DriverIRQHandler
BX R0
PUBWEAK LPUART8_IRQHandler
PUBWEAK LPUART8_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPUART8_IRQHandler
LDR R0, =LPUART8_DriverIRQHandler
BX R0
PUBWEAK LPI2C1_IRQHandler
PUBWEAK LPI2C1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C1_IRQHandler
LDR R0, =LPI2C1_DriverIRQHandler
BX R0
PUBWEAK LPI2C2_IRQHandler
PUBWEAK LPI2C2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C2_IRQHandler
LDR R0, =LPI2C2_DriverIRQHandler
BX R0
PUBWEAK LPI2C3_IRQHandler
PUBWEAK LPI2C3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C3_IRQHandler
LDR R0, =LPI2C3_DriverIRQHandler
BX R0
PUBWEAK LPI2C4_IRQHandler
PUBWEAK LPI2C4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPI2C4_IRQHandler
LDR R0, =LPI2C4_DriverIRQHandler
BX R0
PUBWEAK LPSPI1_IRQHandler
PUBWEAK LPSPI1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI1_IRQHandler
LDR R0, =LPSPI1_DriverIRQHandler
BX R0
PUBWEAK LPSPI2_IRQHandler
PUBWEAK LPSPI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI2_IRQHandler
LDR R0, =LPSPI2_DriverIRQHandler
BX R0
PUBWEAK LPSPI3_IRQHandler
PUBWEAK LPSPI3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI3_IRQHandler
LDR R0, =LPSPI3_DriverIRQHandler
BX R0
PUBWEAK LPSPI4_IRQHandler
PUBWEAK LPSPI4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
LPSPI4_IRQHandler
LDR R0, =LPSPI4_DriverIRQHandler
BX R0
PUBWEAK CAN1_IRQHandler
PUBWEAK CAN1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN1_IRQHandler
LDR R0, =CAN1_DriverIRQHandler
BX R0
PUBWEAK CAN2_IRQHandler
PUBWEAK CAN2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CAN2_IRQHandler
LDR R0, =CAN2_DriverIRQHandler
BX R0
PUBWEAK FLEXRAM_IRQHandler
PUBWEAK KPP_IRQHandler
PUBWEAK TSC_DIG_IRQHandler
PUBWEAK GPR_IRQ_IRQHandler
PUBWEAK LCDIF_IRQHandler
PUBWEAK CSI_IRQHandler
PUBWEAK PXP_IRQHandler
PUBWEAK WDOG2_IRQHandler
PUBWEAK SNVS_HP_WRAPPER_IRQHandler
PUBWEAK SNVS_HP_WRAPPER_TZ_IRQHandler
PUBWEAK SNVS_LP_WRAPPER_IRQHandler
PUBWEAK CSU_IRQHandler
PUBWEAK DCP_IRQHandler
PUBWEAK DCP_VMI_IRQHandler
PUBWEAK Reserved68_IRQHandler
PUBWEAK TRNG_IRQHandler
PUBWEAK SJC_IRQHandler
PUBWEAK BEE_IRQHandler
PUBWEAK SAI1_IRQHandler
PUBWEAK SAI1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI1_IRQHandler
LDR R0, =SAI1_DriverIRQHandler
BX R0
PUBWEAK SAI2_IRQHandler
PUBWEAK SAI2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI2_IRQHandler
LDR R0, =SAI2_DriverIRQHandler
BX R0
PUBWEAK SAI3_RX_IRQHandler
PUBWEAK SAI3_RX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI3_RX_IRQHandler
LDR R0, =SAI3_RX_DriverIRQHandler
BX R0
PUBWEAK SAI3_TX_IRQHandler
PUBWEAK SAI3_TX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SAI3_TX_IRQHandler
LDR R0, =SAI3_TX_DriverIRQHandler
BX R0
PUBWEAK SPDIF_IRQHandler
PUBWEAK SPDIF_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPDIF_IRQHandler
LDR R0, =SPDIF_DriverIRQHandler
BX R0
PUBWEAK PMU_EVENT_IRQHandler
PUBWEAK Reserved78_IRQHandler
PUBWEAK TEMP_LOW_HIGH_IRQHandler
PUBWEAK TEMP_PANIC_IRQHandler
PUBWEAK USB_PHY1_IRQHandler
PUBWEAK USB_PHY2_IRQHandler
PUBWEAK ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
PUBWEAK DCDC_IRQHandler
PUBWEAK Reserved86_IRQHandler
PUBWEAK Reserved87_IRQHandler
PUBWEAK GPIO1_INT0_IRQHandler
PUBWEAK GPIO1_INT1_IRQHandler
PUBWEAK GPIO1_INT2_IRQHandler
PUBWEAK GPIO1_INT3_IRQHandler
PUBWEAK GPIO1_INT4_IRQHandler
PUBWEAK GPIO1_INT5_IRQHandler
PUBWEAK GPIO1_INT6_IRQHandler
PUBWEAK GPIO1_INT7_IRQHandler
PUBWEAK GPIO1_Combined_0_15_IRQHandler
PUBWEAK GPIO1_Combined_16_31_IRQHandler
PUBWEAK GPIO2_Combined_0_15_IRQHandler
PUBWEAK GPIO2_Combined_16_31_IRQHandler
PUBWEAK GPIO3_Combined_0_15_IRQHandler
PUBWEAK GPIO3_Combined_16_31_IRQHandler
PUBWEAK GPIO4_Combined_0_15_IRQHandler
PUBWEAK GPIO4_Combined_16_31_IRQHandler
PUBWEAK GPIO5_Combined_0_15_IRQHandler
PUBWEAK GPIO5_Combined_16_31_IRQHandler
PUBWEAK FLEXIO1_IRQHandler
PUBWEAK FLEXIO1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXIO1_IRQHandler
LDR R0, =FLEXIO1_DriverIRQHandler
BX R0
PUBWEAK FLEXIO2_IRQHandler
PUBWEAK FLEXIO2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXIO2_IRQHandler
LDR R0, =FLEXIO2_DriverIRQHandler
BX R0
PUBWEAK WDOG1_IRQHandler
PUBWEAK RTWDOG_IRQHandler
PUBWEAK EWM_IRQHandler
PUBWEAK CCM_1_IRQHandler
PUBWEAK CCM_2_IRQHandler
PUBWEAK GPC_IRQHandler
PUBWEAK SRC_IRQHandler
PUBWEAK Reserved115_IRQHandler
PUBWEAK GPT1_IRQHandler
PUBWEAK GPT2_IRQHandler
PUBWEAK PWM1_0_IRQHandler
PUBWEAK PWM1_1_IRQHandler
PUBWEAK PWM1_2_IRQHandler
PUBWEAK PWM1_3_IRQHandler
PUBWEAK PWM1_FAULT_IRQHandler
PUBWEAK Reserved123_IRQHandler
PUBWEAK FLEXSPI_IRQHandler
PUBWEAK FLEXSPI_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
FLEXSPI_IRQHandler
LDR R0, =FLEXSPI_DriverIRQHandler
BX R0
PUBWEAK SEMC_IRQHandler
PUBWEAK USDHC1_IRQHandler
PUBWEAK USDHC1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
USDHC1_IRQHandler
LDR R0, =USDHC1_DriverIRQHandler
BX R0
PUBWEAK USDHC2_IRQHandler
PUBWEAK USDHC2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
USDHC2_IRQHandler
LDR R0, =USDHC2_DriverIRQHandler
BX R0
PUBWEAK USB_OTG2_IRQHandler
PUBWEAK USB_OTG1_IRQHandler
PUBWEAK ENET_IRQHandler
PUBWEAK ENET_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_IRQHandler
LDR R0, =ENET_DriverIRQHandler
BX R0
PUBWEAK ENET_1588_Timer_IRQHandler
PUBWEAK ENET_1588_Timer_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
ENET_1588_Timer_IRQHandler
LDR R0, =ENET_1588_Timer_DriverIRQHandler
BX R0
PUBWEAK XBAR1_IRQ_0_1_IRQHandler
PUBWEAK XBAR1_IRQ_2_3_IRQHandler
PUBWEAK ADC_ETC_IRQ0_IRQHandler
PUBWEAK ADC_ETC_IRQ1_IRQHandler
PUBWEAK ADC_ETC_IRQ2_IRQHandler
PUBWEAK ADC_ETC_ERROR_IRQ_IRQHandler
PUBWEAK PIT_IRQHandler
PUBWEAK ACMP1_IRQHandler
PUBWEAK ACMP2_IRQHandler
PUBWEAK ACMP3_IRQHandler
PUBWEAK ACMP4_IRQHandler
PUBWEAK Reserved143_IRQHandler
PUBWEAK Reserved144_IRQHandler
PUBWEAK ENC1_IRQHandler
PUBWEAK ENC2_IRQHandler
PUBWEAK ENC3_IRQHandler
PUBWEAK ENC4_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK TMR4_IRQHandler
PUBWEAK PWM2_0_IRQHandler
PUBWEAK PWM2_1_IRQHandler
PUBWEAK PWM2_2_IRQHandler
PUBWEAK PWM2_3_IRQHandler
PUBWEAK PWM2_FAULT_IRQHandler
PUBWEAK PWM3_0_IRQHandler
PUBWEAK PWM3_1_IRQHandler
PUBWEAK PWM3_2_IRQHandler
PUBWEAK PWM3_3_IRQHandler
PUBWEAK PWM3_FAULT_IRQHandler
PUBWEAK PWM4_0_IRQHandler
PUBWEAK PWM4_1_IRQHandler
PUBWEAK PWM4_2_IRQHandler
PUBWEAK PWM4_3_IRQHandler
PUBWEAK PWM4_FAULT_IRQHandler
PUBWEAK DefaultISR
SECTION .text:CODE:REORDER:NOROOT(1)
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_ERROR_DriverIRQHandler
CTI0_ERROR_IRQHandler
CTI1_ERROR_IRQHandler
CORE_IRQHandler
LPUART1_DriverIRQHandler
LPUART2_DriverIRQHandler
LPUART3_DriverIRQHandler
LPUART4_DriverIRQHandler
LPUART5_DriverIRQHandler
LPUART6_DriverIRQHandler
LPUART7_DriverIRQHandler
LPUART8_DriverIRQHandler
LPI2C1_DriverIRQHandler
LPI2C2_DriverIRQHandler
LPI2C3_DriverIRQHandler
LPI2C4_DriverIRQHandler
LPSPI1_DriverIRQHandler
LPSPI2_DriverIRQHandler
LPSPI3_DriverIRQHandler
LPSPI4_DriverIRQHandler
CAN1_DriverIRQHandler
CAN2_DriverIRQHandler
FLEXRAM_IRQHandler
KPP_IRQHandler
TSC_DIG_IRQHandler
GPR_IRQ_IRQHandler
LCDIF_IRQHandler
CSI_IRQHandler
PXP_IRQHandler
WDOG2_IRQHandler
SNVS_HP_WRAPPER_IRQHandler
SNVS_HP_WRAPPER_TZ_IRQHandler
SNVS_LP_WRAPPER_IRQHandler
CSU_IRQHandler
DCP_IRQHandler
DCP_VMI_IRQHandler
Reserved68_IRQHandler
TRNG_IRQHandler
SJC_IRQHandler
BEE_IRQHandler
SAI1_DriverIRQHandler
SAI2_DriverIRQHandler
SAI3_RX_DriverIRQHandler
SAI3_TX_DriverIRQHandler
SPDIF_DriverIRQHandler
PMU_EVENT_IRQHandler
Reserved78_IRQHandler
TEMP_LOW_HIGH_IRQHandler
TEMP_PANIC_IRQHandler
USB_PHY1_IRQHandler
USB_PHY2_IRQHandler
ADC1_IRQHandler
ADC2_IRQHandler
DCDC_IRQHandler
Reserved86_IRQHandler
Reserved87_IRQHandler
GPIO1_INT0_IRQHandler
GPIO1_INT1_IRQHandler
GPIO1_INT2_IRQHandler
GPIO1_INT3_IRQHandler
GPIO1_INT4_IRQHandler
GPIO1_INT5_IRQHandler
GPIO1_INT6_IRQHandler
GPIO1_INT7_IRQHandler
GPIO1_Combined_0_15_IRQHandler
GPIO1_Combined_16_31_IRQHandler
GPIO2_Combined_0_15_IRQHandler
GPIO2_Combined_16_31_IRQHandler
GPIO3_Combined_0_15_IRQHandler
GPIO3_Combined_16_31_IRQHandler
GPIO4_Combined_0_15_IRQHandler
GPIO4_Combined_16_31_IRQHandler
GPIO5_Combined_0_15_IRQHandler
GPIO5_Combined_16_31_IRQHandler
FLEXIO1_DriverIRQHandler
FLEXIO2_DriverIRQHandler
WDOG1_IRQHandler
RTWDOG_IRQHandler
EWM_IRQHandler
CCM_1_IRQHandler
CCM_2_IRQHandler
GPC_IRQHandler
SRC_IRQHandler
Reserved115_IRQHandler
GPT1_IRQHandler
GPT2_IRQHandler
PWM1_0_IRQHandler
PWM1_1_IRQHandler
PWM1_2_IRQHandler
PWM1_3_IRQHandler
PWM1_FAULT_IRQHandler
Reserved123_IRQHandler
FLEXSPI_DriverIRQHandler
SEMC_IRQHandler
USDHC1_DriverIRQHandler
USDHC2_DriverIRQHandler
USB_OTG2_IRQHandler
USB_OTG1_IRQHandler
ENET_DriverIRQHandler
ENET_1588_Timer_DriverIRQHandler
XBAR1_IRQ_0_1_IRQHandler
XBAR1_IRQ_2_3_IRQHandler
ADC_ETC_IRQ0_IRQHandler
ADC_ETC_IRQ1_IRQHandler
ADC_ETC_IRQ2_IRQHandler
ADC_ETC_ERROR_IRQ_IRQHandler
PIT_IRQHandler
ACMP1_IRQHandler
ACMP2_IRQHandler
ACMP3_IRQHandler
ACMP4_IRQHandler
Reserved143_IRQHandler
Reserved144_IRQHandler
ENC1_IRQHandler
ENC2_IRQHandler
ENC3_IRQHandler
ENC4_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
TMR4_IRQHandler
PWM2_0_IRQHandler
PWM2_1_IRQHandler
PWM2_2_IRQHandler
PWM2_3_IRQHandler
PWM2_FAULT_IRQHandler
PWM3_0_IRQHandler
PWM3_1_IRQHandler
PWM3_2_IRQHandler
PWM3_3_IRQHandler
PWM3_FAULT_IRQHandler
PWM4_0_IRQHandler
PWM4_1_IRQHandler
PWM4_2_IRQHandler
PWM4_3_IRQHandler
PWM4_FAULT_IRQHandler
DefaultISR
B DefaultISR
END

94
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/MIMXRT1052xxxxx_flexspi_nor.scf Normal file
View File

@@ -0,0 +1,94 @@
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_flash_config_start 0x60000000
#define m_flash_config_size 0x00001000
#define m_ivt_start 0x60001000
#define m_ivt_size 0x00001000
#define m_interrupts_start 0x60002000
#define m_interrupts_size 0x00000400
#define m_text_start 0x60002400
#define m_text_size 0x03FFDC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x00040000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
* (.boot_hdr.conf, +FIRST)
}
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
* (.boot_hdr.ivt, +FIRST)
* (.boot_hdr.boot_data)
* (.boot_hdr.dcd_data)
}
#else
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
#endif
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

75
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/MIMXRT1052xxxxx_ram.scf Normal file
View File

@@ -0,0 +1,75 @@
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x20000000
#define m_data_size 0x00020000
#define m_data2_start 0x20200000
#define m_data2_size 0x00040000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
* (NonCacheable.init)
* (NonCacheable)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_data2_start EMPTY 0 {
}
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

83
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/MIMXRT1052xxxxx_sdram.scf Normal file
View File

@@ -0,0 +1,83 @@
#! armcc -E
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
#define m_interrupts_start 0x00000000
#define m_interrupts_size 0x00000400
#define m_text_start 0x00000400
#define m_text_size 0x0001FC00
#define m_data_start 0x80000000
#define m_data_size 0x01E00000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
#define m_data2_start 0x20000000
#define m_data2_size 0x00020000
#define m_data3_start 0x20200000
#define m_data3_size 0x00040000
/* Sizes */
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#endif
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
.ANY (+RW +ZI)
*(m_usb_dma_init_data)
*(m_usb_dma_noninit_data)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data
* (NonCacheable.init)
* (NonCacheable)
}
RW_m_ncache_unused +0 EMPTY m_ncache_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
}
}

90
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/evkbimxrt1050_flexspi_nor.ini Normal file
View File

@@ -0,0 +1,90 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x60002000); // Setup Stack Pointer
PC = _RDWORD(0x60002004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

91
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/evkbimxrt1050_ram.ini Normal file
View File

@@ -0,0 +1,91 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
Setup(); // Setup for Running
}
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

260
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/evkbimxrt1050_sdram_init.ini Normal file
View File

@@ -0,0 +1,260 @@
/*
* Copyright 2017 NXP
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
FUNC void _loadDcdcTrim(void)
{
unsigned int dcdc_trim_loaded;
unsigned long ocotp_base;
unsigned long ocotp_fuse_bank0_base;
unsigned long dcdc_base;
unsigned long reg;
unsigned long trim_value;
unsigned int index;
ocotp_base = 0x401F4000;
ocotp_fuse_bank0_base = ocotp_base + 0x400;
dcdc_base = 0x40080000;
dcdc_trim_loaded = 0;
reg = _RDWORD(ocotp_fuse_bank0_base + 0x90);
if (reg & (1<<10))
{
// DCDC: REG0->VBG_TRM
trim_value = (reg & (0x1F << 11)) >> 11;
reg = (_RDWORD(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
_WDWORD(dcdc_base + 0x4, reg);
dcdc_trim_loaded = 1;
}
reg = _RDWORD(ocotp_fuse_bank0_base + 0x80);
if (reg & (1<<30))
{
index = (reg & (3 << 28)) >> 28;
if (index < 4)
{
// DCDC: REG3->TRG
reg = (_RDWORD(dcdc_base + 0xC) & ~(0x1F)) | ((0xF + index));
_WDWORD(dcdc_base + 0xC, reg);
dcdc_trim_loaded = 1;
}
}
if (dcdc_trim_loaded)
{
// delay about 400us till dcdc is stable.
_Sleep_(1);
}
}
FUNC void SDRAM_WaitIpCmdDone(void)
{
unsigned long reg;
do
{
reg = _RDWORD(0x402F003C);
}while((reg & 0x3) == 0);
_WDWORD(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
}
FUNC void _clock_init(void)
{
unsigned int reg;
// Enable all clocks
_WDWORD(0x400FC068,0xffffffff);
_WDWORD(0x400FC06C,0xffffffff);
_WDWORD(0x400FC070,0xffffffff);
_WDWORD(0x400FC074,0xffffffff);
_WDWORD(0x400FC078,0xffffffff);
_WDWORD(0x400FC07C,0xffffffff);
_WDWORD(0x400FC080,0xffffffff);
// PERCLK_PODF: 1 divide by 2
_WDWORD(0x400FC01C, 0x04900001);
// Enable SYS PLL but keep it bypassed.
_WDWORD(0x400D8030, 0x00012001);
do
{
reg = _RDWORD(0x400D8030);
}while((reg & 0x80000000) == 0);
// Disable bypass of SYS PLL
_WDWORD(0x400D8030, 0x00002001);
// PFD2_FRAC: 29, PLL2 PFD2=528*18/PFD2_FRAC=327
// Ungate SYS PLL PFD2
_WDWORD(0x400D8100, 0x001d0000);
// SEMC_PODF: 001, AHB_PODF: 011, IPG_PODF: 01
// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
_WDWORD(0x400FC014, 0x00010D40);
}
FUNC void _sdr_Init(void)
{
// Config IOMUX
_WDWORD(0x401F8014, 0x00000000);
_WDWORD(0x401F8018, 0x00000000);
_WDWORD(0x401F801C, 0x00000000);
_WDWORD(0x401F8020, 0x00000000);
_WDWORD(0x401F8024, 0x00000000);
_WDWORD(0x401F8028, 0x00000000);
_WDWORD(0x401F802C, 0x00000000);
_WDWORD(0x401F8030, 0x00000000);
_WDWORD(0x401F8034, 0x00000000);
_WDWORD(0x401F8038, 0x00000000);
_WDWORD(0x401F803C, 0x00000000);
_WDWORD(0x401F8040, 0x00000000);
_WDWORD(0x401F8044, 0x00000000);
_WDWORD(0x401F8048, 0x00000000);
_WDWORD(0x401F804C, 0x00000000);
_WDWORD(0x401F8050, 0x00000000);
_WDWORD(0x401F8054, 0x00000000);
_WDWORD(0x401F8058, 0x00000000);
_WDWORD(0x401F805C, 0x00000000);
_WDWORD(0x401F8060, 0x00000000);
_WDWORD(0x401F8064, 0x00000000);
_WDWORD(0x401F8068, 0x00000000);
_WDWORD(0x401F806C, 0x00000000);
_WDWORD(0x401F8070, 0x00000000);
_WDWORD(0x401F8074, 0x00000000);
_WDWORD(0x401F8078, 0x00000000);
_WDWORD(0x401F807C, 0x00000000);
_WDWORD(0x401F8080, 0x00000000);
_WDWORD(0x401F8084, 0x00000000);
_WDWORD(0x401F8088, 0x00000000);
_WDWORD(0x401F808C, 0x00000000);
_WDWORD(0x401F8090, 0x00000000);
_WDWORD(0x401F8094, 0x00000000);
_WDWORD(0x401F8098, 0x00000000);
_WDWORD(0x401F809C, 0x00000000);
_WDWORD(0x401F80A0, 0x00000000);
_WDWORD(0x401F80A4, 0x00000000);
_WDWORD(0x401F80A8, 0x00000000);
_WDWORD(0x401F80AC, 0x00000000);
_WDWORD(0x401F80B0, 0x00000010); // EMC_39, DQS PIN, enable SION
_WDWORD(0x401F80B4, 0x00000000);
_WDWORD(0x401F80B8, 0x00000000);
// PAD ctrl
// drive strength = 0x7 to increase drive strength
// otherwise the data7 bit may fail.
_WDWORD(0x401F8204, 0x000110F9);
_WDWORD(0x401F8208, 0x000110F9);
_WDWORD(0x401F820C, 0x000110F9);
_WDWORD(0x401F8210, 0x000110F9);
_WDWORD(0x401F8214, 0x000110F9);
_WDWORD(0x401F8218, 0x000110F9);
_WDWORD(0x401F821C, 0x000110F9);
_WDWORD(0x401F8220, 0x000110F9);
_WDWORD(0x401F8224, 0x000110F9);
_WDWORD(0x401F8228, 0x000110F9);
_WDWORD(0x401F822C, 0x000110F9);
_WDWORD(0x401F8230, 0x000110F9);
_WDWORD(0x401F8234, 0x000110F9);
_WDWORD(0x401F8238, 0x000110F9);
_WDWORD(0x401F823C, 0x000110F9);
_WDWORD(0x401F8240, 0x000110F9);
_WDWORD(0x401F8244, 0x000110F9);
_WDWORD(0x401F8248, 0x000110F9);
_WDWORD(0x401F824C, 0x000110F9);
_WDWORD(0x401F8250, 0x000110F9);
_WDWORD(0x401F8254, 0x000110F9);
_WDWORD(0x401F8258, 0x000110F9);
_WDWORD(0x401F825C, 0x000110F9);
_WDWORD(0x401F8260, 0x000110F9);
_WDWORD(0x401F8264, 0x000110F9);
_WDWORD(0x401F8268, 0x000110F9);
_WDWORD(0x401F826C, 0x000110F9);
_WDWORD(0x401F8270, 0x000110F9);
_WDWORD(0x401F8274, 0x000110F9);
_WDWORD(0x401F8278, 0x000110F9);
_WDWORD(0x401F827C, 0x000110F9);
_WDWORD(0x401F8280, 0x000110F9);
_WDWORD(0x401F8284, 0x000110F9);
_WDWORD(0x401F8288, 0x000110F9);
_WDWORD(0x401F828C, 0x000110F9);
_WDWORD(0x401F8290, 0x000110F9);
_WDWORD(0x401F8294, 0x000110F9);
_WDWORD(0x401F8298, 0x000110F9);
_WDWORD(0x401F829C, 0x000110F9);
_WDWORD(0x401F82A0, 0x000110F9);
_WDWORD(0x401F82A4, 0x000110F9);
_WDWORD(0x401F82A8, 0x000110F9);
// Config SDR Controller Registers/
_WDWORD(0x402F0000,0x10000004); // MCR
_WDWORD(0x402F0008,0x00030524); // BMCR0
_WDWORD(0x402F000C,0x06030524); // BMCR1
_WDWORD(0x402F0010,0x8000001B); // BR0, 32MB
_WDWORD(0x402F0040,0x00000F31); // SDRAMCR0
_WDWORD(0x402F0044,0x00652922); // SDRAMCR1
_WDWORD(0x402F0048,0x00010920); // SDRAMCR2
_WDWORD(0x402F004C,0x50210A08); // SDRAMCR3
_WDWORD(0x402F0090,0x80000000); // IPCR0
_WDWORD(0x402F0094,0x00000002); // IPCR1
_WDWORD(0x402F0098,0x00000000); // IPCR2
_WDWORD(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F009C,0xA55A000C); // SD_CC_IAF
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F00A0,0x00000033); // IPTXDAT
_WDWORD(0x402F009C,0xA55A000A); // SD_CC_IMS
SDRAM_WaitIpCmdDone();
_WDWORD(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.
}
FUNC void Setup (void) {
_loadDcdcTrim();
SP = _RDWORD(0x00000000); // Setup Stack Pointer
PC = _RDWORD(0x00000004); // Setup Program Counter
_WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register
}
FUNC void OnResetExec (void) { // executes upon software RESET
_clock_init();
_sdr_Init();
Setup(); // Setup for Running
}
_clock_init();
_sdr_Init();
LOAD %L INCREMENTAL // Download
Setup(); // Setup for Running
// g, main

2566
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/hello_world.uvoptx Normal file
View File

File diff suppressed because it is too large Load Diff

5825
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/hello_world.uvprojx Normal file
View File

File diff suppressed because it is too large Load Diff

69
board/NXP_EVKB_IMXRT1050/KEIL/hello_world/readme.txt Normal file
View File

@@ -0,0 +1,69 @@
Overview
========
The Hello World demo application provides a sanity check for the TencentOS-tiny porting on i.MXRT1050. The Hello
World demo creates two tasks. Two tasks print the information with task number and the count of being run by OS.
The task 1 also turns to shine the LED.
Toolchain supported
===================
- IAR embedded Workbench 8.40.2
- Keil MDK 5.29 (ARM Compiler 5 only)
Hardware requirements
=====================
- Mini/micro USB cable
- EVKB-IMXRT1050 board
- Personal Computer
Board settings
==============
No special settings are required.
Prepare the Demo
================
1. Connect a USB cable between the host PC and the OpenSDA USB port on the target board.
2. Open a serial terminal with the following settings:
- 115200 baud rate
- 8 data bits
- No parity
- One stop bit
- No flow control
3. Download the program to the target board.
4. Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
Running the demo
================
The log below shows the output of the hello world demo in the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hello world from i.MX RT1050.
Welcome to TencentOS tiny
++++++++This is Task 1, count is 0
********This is Task 2, count is 0
++++++++This is Task 1, count is 1
++++++++This is Task 1, count is 2
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Note:
To download binary into hyper flash and boot from hyperflash directly, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project, and get the binaray file "hello_world.bin"
3. Set the SW7: 1 off 2 off 3 off 4 on, then power on the board and connect USB cable to J28
4. Drop the binaray into disk "EVK-MIMXRT"
5. Wait for the disk disappear and appear again which will take around ~10s, then power off the board
6. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
7. After power on the baord, program has already started to run, reset SW4 is recommended.
Note:
To debug in hyper flash in MDK, following steps are needed:
1. Select the target flexspi_nor_debug or flexspi_nor_release.
2. Compile the project.
3. Press F8 or click the download button, to program the application into hyper flash.
4. Set the SW7: 1 off 2 on 3 on 4 off, then power on the board
5. Push SW4 to reset.
6. Start to debug.
Customization options
=====================