698 lines
22 KiB
C
698 lines
22 KiB
C
/**************************************************************************//**
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* @file fmc.h
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* @version V3.0
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* @brief M251 Series Flash Memory Controller(FMC) driver header file
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*
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* @note
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* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
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*
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******************************************************************************/
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#ifndef __FMC_H__
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#define __FMC_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup FMC_Driver FMC Driver
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@{
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*/
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/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* Global constant definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define ISBEN 0
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/*---------------------------------------------------------------------------------------------------------*/
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/* Define Base Address */
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/*---------------------------------------------------------------------------------------------------------*/
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#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
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#define FMC_APROM_END 0x00040000UL /*!< APROM end address */
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#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
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#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address */
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#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */
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#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
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#define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */
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#define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 0x4UL) /*!< CONFIG 1 Address */
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#define FMC_CONFIG2_ADDR (FMC_CONFIG_BASE + 0x8UL) /*!< CONFIG 2 Address */
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#define FMC_XOMR0BASE_ADDR (FMC_XOM_BASE) /*!< XOMR 0 Base Address */
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#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */
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#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) */
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#define FMC_FLASH_PAGE_SIZE 0x200UL /*!< Flash Page Size (512 Bytes) */
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#define FMC_PAGE_ADDR_MASK 0xFFFFFE00UL /*!< Flash page address mask */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ISPCTL constant definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define FMC_ISPCTL_BS_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */
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#define FMC_ISPCTL_BS_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */
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/*---------------------------------------------------------------------------------------------------------*/
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/* ISPCMD constant definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */
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#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */
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#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */
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#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */
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#define FMC_ISPCMD_READ_PID 0x0CUL /*!< ISP Command: Read Device ID */
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#define FMC_ISPCMD_CHECKSUM 0x0DUL /*!< ISP Command: Read Checksum */
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#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */
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#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */
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#define FMC_ISPCMD_MULTI_PROG 0x27UL /*!< ISP Command: Flash Multi-Word Program */
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#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification*/
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#define FMC_ISPCMD_CAL_CHECKSUM 0x2DUL /*!< ISP Command: Run Check Calculation */
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#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */
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#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */
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#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */
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#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */
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/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
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/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* FMC Macro Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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/**
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* @brief Enable ISP Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will set ISPEN bit of ISPCTL control register to enable ISP function.
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*
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*/
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#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */
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/**
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* @brief Disable ISP Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
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*
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*/
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#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */
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/**
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* @brief Enable LDROM Update Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.
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* User needs to set LDUEN bit before they can update LDROM.
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*
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*/
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#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */
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/**
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* @brief Disable LDROM Update Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
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*
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*/
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#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */
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/**
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* @brief Enable User Configuration Update Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
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* User needs to set CFGUEN bit before they can update User Configuration area.
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*
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*/
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#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
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/**
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* @brief Disable User Configuration Update Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
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*
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*/
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#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
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/**
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* @brief Enable APROM Update Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will set APUEN bit of ISPCTL control register to enable APROM update function.
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* User needs to set APUEN bit before they can update APROM in APROM boot mode.
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*
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*/
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#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */
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/**
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* @brief Disable APROM Update Function
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*
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* @param None
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*
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* @return None
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*
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* @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
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*
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*/
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#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */
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/**
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* @brief Next Booting Selection function
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*
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* @param[in] x Booting from APROM(0)/LDROM(1)
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*
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* @return None
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*
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* @details This function will set MCU next booting from LDROM/APROM.
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*
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* @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set.
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*
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*/
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#define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */
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/**
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* @brief Get MCU Booting Status
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*
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* @param None
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*
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* @return None
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*
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* @details This function will get status of chip next booting from LDROM/APROM.
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*
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*/
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#define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */
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/**
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* @brief Get ISP fail flag
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*
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* @param None
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*
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* @return None
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*
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* @details This function will get the status of ISP falil flag
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*
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*/
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#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */
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/**
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* @brief Clear ISP fail flag
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*
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* @param None
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*
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* @return None
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*
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* @details This function will clear the status of ISP falil flag
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*
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*/
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#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */
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/**
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* @brief Disable APROM update function
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*
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* @param None
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*
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* @return None
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*
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* @details Disable APROM update function will forbid APROM programming when boot form APROM.
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* APROM update is default to be disable.
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*
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*/
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#define FMC_DisableAPUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable AP update */
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/**
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* @brief Disable User Configuration update function
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*
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* @param None
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*
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* @return None
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*
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* @details Disable User Configuration update function will forbid User Configuration programming.
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* User Configuration update is default to be disable.
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*/
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#define FMC_DisableConfigUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable config update */
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/**
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* @brief Disable LDROM update function
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*
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* @param None
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*
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* @return None
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* @details Disable LDROM update function will forbid LDROM programming.
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* LDROM update is default to be disable.
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*/
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#define FMC_DisableLDUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LD update */
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/**
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* @brief Enable APROM update function
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*
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* @param None
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*
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* @return None
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*
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* @details Enable APROM to be able to program when boot from APROM.
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*
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*/
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#define FMC_EnableAPUpdate() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable AP update */
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/**
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* @brief Enable User Configuration update function
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*
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* @param None
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*
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* @return None
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*
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* @details Enable User Configuration to be able to program.
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*
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*/
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#define FMC_EnableConfigUpdate() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable config update */
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/**
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* @brief Enable LDROM update function
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*
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* @param None
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*
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* @return None
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*
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* @details Enable LDROM to be able to program.
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*
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*/
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#define FMC_EnableLDUpdate() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LD update */
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/*---------------------------------------------------------------------------------------------------------*/
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/* inline functions */
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/*---------------------------------------------------------------------------------------------------------*/
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static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index);
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static __INLINE uint32_t FMC_ReadCID(void);
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static __INLINE uint32_t FMC_ReadPID(void);
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static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);
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static __INLINE uint32_t FMC_ReadVBGCode(void);
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static __INLINE uint32_t FMC_ReadVTEMPCode(void);
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static __INLINE uint32_t FMC_ReadADCOffset(void);
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static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
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static __INLINE uint32_t FMC_GetVECMAP(void);
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static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size);
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static __INLINE void FMC_Write128(uint32_t u32Addr, uint32_t pu32Buf[]);
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/**
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* @brief Read Unique ID
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*
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* @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
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*
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* @return The 32-bit unique ID data of specified UID index.
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*
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* @details To read out 96-bit Unique ID.
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*
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*/
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static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_UID;
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FMC->ISPADDR = ((uint32_t)u8Index << 2u);
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FMC->ISPDAT = 0u;
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FMC->ISPTRG = 0x1u;
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#if ISBEN
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__ISB();
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#endif
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while (FMC->ISPTRG) {}
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return FMC->ISPDAT;
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}
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/**
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* @brief Read company ID
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*
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* @param None
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*
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* @return The company ID (32-bit)
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*
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* @details The company ID of Nuvoton is fixed to be 0xDA
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*
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*/
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static __INLINE uint32_t FMC_ReadCID(void)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
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FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */
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FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
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#if ISBEN
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__ISB();
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#endif /* To make sure ISP/CPU be Synchronized */
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while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
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return FMC->ISPDAT;
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}
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/**
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* @brief Read product ID
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*
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* @param None
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*
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* @return The product ID (32-bit)
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*
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* @details This function is used to read product ID.
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*
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*/
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static __INLINE uint32_t FMC_ReadPID(void)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_PID; /* Set ISP Command Code */
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FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */
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FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
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#if ISBEN
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__ISB();
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#endif /* To make sure ISP/CPU be Synchronized */
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while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
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return FMC->ISPDAT;
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}
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/**
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* @brief To read UCID
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*
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* @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
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*
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* @return The UCID of specified index
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*
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* @details This function is used to read unique chip ID (UCID).
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*
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*/
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static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
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FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */
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FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
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#if ISBEN
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__ISB();
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#endif /* To make sure ISP/CPU be Synchronized */
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while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
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return FMC->ISPDAT;
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}
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/**
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* @brief To read bang-gap voltage code
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*
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* @param[in] None
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*
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* @return The bang-gap voltage code
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*
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* @details This function is used to read bang-gap voltage code
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*
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*/
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static __INLINE uint32_t FMC_ReadVBGCode(void)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
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FMC->ISPADDR = 0x70; /* The VBG is at offset 0x70 with word alignment. */
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FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
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#if ISBEN
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__ISB();
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#endif /* To make sure ISP/CPU be Synchronized */
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while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
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return FMC->ISPDAT;
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}
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/**
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* @brief To read the temperature sensor ADC code
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*
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* @param[in] None
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*
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* @return The temperature sensor ADC code
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*
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* @details This function is used to read temperature sensor ADC code
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*
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*/
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static __INLINE uint32_t FMC_ReadVTEMPCode(void)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
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FMC->ISPADDR = 0x74; /* The VTEMP code is at offset 0x74 with word alignment */
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FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
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#if ISBEN
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__ISB();
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#endif /* To make sure ISP/CPU be Synchronized */
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while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
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return FMC->ISPDAT;
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}
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/**
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* @brief To read the calibration value for ADC offset
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*
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* @param[in] None
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*
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* @return The calibration value for ADC offset
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*
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* @details This function is used to read the calibration value for ADC offset
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*
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*/
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static __INLINE uint32_t FMC_ReadADCOffset(void)
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{
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FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
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FMC->ISPADDR = 0x78; /* The calibration value for ADC offset is at offset 0x78 with word alignment */
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FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
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#if ISBEN
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__ISB();
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#endif /* To make sure ISP/CPU be Synchronized */
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while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
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return FMC->ISPDAT;
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}
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/**
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* @brief Set vector mapping address
|
|
*
|
|
* @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
|
|
*
|
|
* @return To set VECMAP to remap specified page address to 0x0.
|
|
*
|
|
* @details This function is used to set VECMAP to map specified page to vector page (0x0).
|
|
*
|
|
* @note
|
|
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
|
|
*
|
|
*/
|
|
static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
|
|
{
|
|
FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
|
|
FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
|
|
FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */
|
|
#if ISBEN
|
|
__ISB();
|
|
#endif /* To make sure ISP/CPU be Synchronized */
|
|
|
|
while (FMC->ISPTRG) {} /* Waiting for ISP Done */
|
|
}
|
|
|
|
/**
|
|
* @brief Get current vector mapping address.
|
|
*
|
|
* @param None
|
|
*
|
|
* @return The current vector mapping address.
|
|
*
|
|
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
|
|
*
|
|
* @note
|
|
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
|
|
*
|
|
*/
|
|
static __INLINE uint32_t FMC_GetVECMAP(void)
|
|
{
|
|
return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
|
|
}
|
|
|
|
/**
|
|
* @brief Get Flash Checksum
|
|
*
|
|
* @param[in] u32Addr Specific flash start address
|
|
* @param[in] i32Size Specific a size of Flash area
|
|
*
|
|
* @return A checksum value of a flash block.
|
|
*
|
|
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
|
|
*
|
|
*/
|
|
static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size)
|
|
{
|
|
FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
|
|
FMC->ISPADDR = u32Addr;
|
|
FMC->ISPDAT = (uint32_t)i32Size;
|
|
FMC->ISPTRG = 0x1u;
|
|
#if ISBEN
|
|
__ISB();
|
|
#endif
|
|
|
|
while (FMC->ISPTRG) {}
|
|
|
|
FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
|
|
FMC->ISPTRG = 0x1u;
|
|
|
|
while (FMC->ISPTRG) {}
|
|
|
|
return FMC->ISPDAT;
|
|
}
|
|
|
|
/**
|
|
* @brief Program Multi-Word data into specified address of flash
|
|
*
|
|
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
|
|
* @param[in] pu32Buf A data pointer is point to a data buffer start address;
|
|
*
|
|
* @return None
|
|
*
|
|
* @details To program multi-words data into Flash include APROM, LDROM, and CONFIG.
|
|
*
|
|
*/
|
|
static __INLINE void FMC_Write128(uint32_t u32Addr, uint32_t pu32Buf[])
|
|
{
|
|
|
|
uint32_t i, idx, u32OnProg;
|
|
int32_t err;
|
|
|
|
idx = 0u;
|
|
FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
|
|
FMC->ISPADDR = u32Addr;
|
|
|
|
do
|
|
{
|
|
err = 0;
|
|
u32OnProg = 1u;
|
|
FMC->MPDAT0 = pu32Buf[idx + 0u];
|
|
FMC->MPDAT1 = pu32Buf[idx + 1u];
|
|
FMC->MPDAT2 = pu32Buf[idx + 2u];
|
|
FMC->MPDAT3 = pu32Buf[idx + 3u];
|
|
FMC->ISPTRG = 0x1u;
|
|
idx += 4u;
|
|
|
|
for (i = idx; i < 128u / 4u; i += 4u) /* Max data length is 128 bytes (128/4 words)*/
|
|
{
|
|
__set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/
|
|
|
|
do
|
|
{
|
|
if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
|
|
{
|
|
__set_PRIMASK(0u);
|
|
|
|
FMC->ISPADDR = FMC->MPADDR & (~0xful);
|
|
idx = (FMC->ISPADDR - u32Addr) / 4u;
|
|
err = -1;
|
|
}
|
|
}
|
|
while ((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0));
|
|
|
|
if (err == 0)
|
|
{
|
|
/* Update new data for D0 */
|
|
FMC->MPDAT0 = pu32Buf[i];
|
|
FMC->MPDAT1 = pu32Buf[i + 1u];
|
|
|
|
do
|
|
{
|
|
if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
|
|
{
|
|
__set_PRIMASK(0u);
|
|
FMC->ISPADDR = FMC->MPADDR & (~0xful);
|
|
idx = (FMC->ISPADDR - u32Addr) / 4u;
|
|
err = -1;
|
|
}
|
|
}
|
|
while ((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0));
|
|
|
|
if (err == 0)
|
|
{
|
|
/* Update new data for D2*/
|
|
FMC->MPDAT2 = pu32Buf[i + 2u];
|
|
FMC->MPDAT3 = pu32Buf[i + 3u];
|
|
__set_PRIMASK(0u);
|
|
}
|
|
}
|
|
|
|
if (err < 0)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (err == 0)
|
|
{
|
|
u32OnProg = 0u;
|
|
|
|
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {}
|
|
}
|
|
}
|
|
while (u32OnProg);
|
|
}
|
|
|
|
void FMC_Open(void);
|
|
void FMC_Close(void);
|
|
int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
|
|
int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count);
|
|
void FMC_SetBootSource(int32_t i32BootSrc);
|
|
int32_t FMC_GetBootSource(void);
|
|
uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
|
|
uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
|
|
int32_t FMC_Is_XOM_Actived(uint32_t xom_num);
|
|
int32_t FMC_Erase_XOM(uint32_t xom_num);
|
|
int32_t FMC_Erase(uint32_t u32Addr);
|
|
int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page);
|
|
uint32_t FMC_Read(uint32_t u32Addr);
|
|
void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
|
|
|
|
|
|
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
|
|
|
|
/*@}*/ /* end of group FMC_Driver */
|
|
|
|
/*@}*/ /* end of group Standard_Driver */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __FMC_H__ */
|
|
|
|
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
|
|