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This commit is contained in:
Grey Huang
2019-10-25 16:24:23 +08:00
parent f48e74764a
commit 112704aa8a
165 changed files with 71469 additions and 0 deletions
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39
board/Nuvoton_M251/CMSIS/cmsis_version.h Normal file
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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board/Nuvoton_M251/CMSIS/core_armv8mbl.h Normal file
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board/Nuvoton_M251/CMSIS/core_cm23.h Normal file
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board/Nuvoton_M251/Project/Nu_Link_Driver.ini Normal file
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[Version]
Nu_LinkVersion=V5.6
[Process]
ProcessID=0x00000494
ProcessCreationTime_L=0x872a3db0
ProcessCreationTime_H=0x01d58acd
NuLinkID=0x06160233
NuLinkIDs_Count=0x00000001
NuLinkID0=0x06160233
[ChipSelect]
;ChipName=<NUC1xx|NUC2xx|M05x|N571|N572|Nano100|N512|Mini51|NUC505|General>
ChipName=M251
[NUC505]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=NUC505_SPIFLASH.FLM
[NUC4xx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=NUC400_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x014fb180
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[NUC2xx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC200_AP_128.FLM
[NUC126]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=NUC126_AP_256.FLM
[NUC121]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC121_AP_32.FLM
[NUC1xx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC100_AP_128.FLM
[NUC029]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NUC029_AP_16.FLM
[NM1820]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1820_AP_17_5.FLM
[NM1810]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1810_AP_29_5.FLM
[NM1500]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1500_AP_128.FLM
[NM1330]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1330_AP_64.FLM
[NM1320]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1320_AP_32.FLM
[NM1230]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1230_AP_64.FLM
[NM1200]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1200_AP_8.FLM
[NM1120]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1120_AP_29_5.FLM
[TF5100]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=TF5100_AP_64.FLM
[NDA102]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NDA102_AP_29_5.FLM
[Nano103]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=Nano103_AP_64.FLM
[Nano100]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=Nano100_AP_64.FLM
[N576]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N576_AP_145.FLM
[N575]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N575_AP_145.FLM
[N572]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=N572Fxxx.FLM
[N571]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=N571E000.FLM
[N570]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N570_AP_64.FLM
[N569]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N569_AP_64.FLM
[N512]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N512_AP_64.FLM
[Mini57]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=Mini57_AP_29_5.FLM
[Mini51]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=Mini51_AP_16.FLM
[M481]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M481_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[M480LD]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M480LD_AP_256.FLM
[M451]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M451_AP_256.FLM
[M251]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=M251_AP_192.FLM
[M2351]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=1
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M2351_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[M261]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=1
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M261_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[M0564]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=M0564_AP_256.FLM
[M0519]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=M0519_AP_128.FLM
[M0518]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=M0518_AP_64.FLM
[M05x]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=M0516_AP_64.FLM
[M031]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=M031_AP_128.FLM
[NPCX]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=NPCX_AP_512.FLM
[I94000]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=I94000_AP_512.FLM
[ISD9300]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=ISD9300_AP_145.FLM
[I9200]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=I9200_AP_128.FLM
[ISD9xxx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=ISD9100_AP_145.FLM
[ISD9000]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=ISD9000_AP_64.FLM
[AU9xxx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=AU9100_AP_145.FLM
[General]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=

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board/Nuvoton_M251/Project/NuvotonTos.uvguix.Administrator Normal file
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board/Nuvoton_M251/Project/NuvotonTos.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
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590
board/Nuvoton_M251/Project/NuvotonTos.uvprojx Normal file
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<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName></SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll></SimDlgDll>
<SimDlgDllArguments></SimDlgDllArguments>
<TargetDllName>SARMV8M.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM23</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>0</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2V8M.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M23"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>7</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>1</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\CMSIS;..\STARTUP;..\StdDriver\inc;..\TencentOS\arch\include;..\TencentOS\kernel\core\include;..\TencentOS\kernel\pm\include;..\TencentOS\TOS_CONFIG;..\TencentOS\arch;..\STARTUP\Include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>STARTUP</GroupName>
<Files>
<File>
<FileName>system_M251.c</FileName>
<FileType>1</FileType>
<FilePath>..\STARTUP\system_M251.c</FilePath>
</File>
<File>
<FileName>startup_M251.s</FileName>
<FileType>2</FileType>
<FilePath>..\STARTUP\startup_M251.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>StdDriver</GroupName>
<Files>
<File>
<FileName>clk.c</FileName>
<FileType>1</FileType>
<FilePath>..\StdDriver\src\clk.c</FilePath>
</File>
<File>
<FileName>retarget.c</FileName>
<FileType>1</FileType>
<FilePath>..\StdDriver\src\retarget.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\StdDriver\src\uart.c</FilePath>
</File>
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\StdDriver\src\gpio.c</FilePath>
</File>
<File>
<FileName>sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\StdDriver\src\sys.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>USER</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>.\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Tos/arch</GroupName>
<Files>
<File>
<FileName>port_c.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\arch\port_c.c</FilePath>
</File>
<File>
<FileName>tos_cpu.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\arch\tos_cpu.c</FilePath>
</File>
<File>
<FileName>tos_fault.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\arch\tos_fault.c</FilePath>
</File>
<File>
<FileName>port_s.S</FileName>
<FileType>2</FileType>
<FilePath>..\TencentOS\arch\port_s.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Tos/kernel</GroupName>
<Files>
<File>
<FileName>tos_event.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_event.c</FilePath>
</File>
<File>
<FileName>tos_fifo.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_fifo.c</FilePath>
</File>
<File>
<FileName>tos_global.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_global.c</FilePath>
</File>
<File>
<FileName>tos_mmblk.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_mmblk.c</FilePath>
</File>
<File>
<FileName>tos_mmheap.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_mmheap.c</FilePath>
</File>
<File>
<FileName>tos_msg.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_msg.c</FilePath>
</File>
<File>
<FileName>tos_mutex.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_mutex.c</FilePath>
</File>
<File>
<FileName>tos_pend.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_pend.c</FilePath>
</File>
<File>
<FileName>tos_queue.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_queue.c</FilePath>
</File>
<File>
<FileName>tos_robin.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_robin.c</FilePath>
</File>
<File>
<FileName>tos_sched.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_sched.c</FilePath>
</File>
<File>
<FileName>tos_sem.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_sem.c</FilePath>
</File>
<File>
<FileName>tos_sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_sys.c</FilePath>
</File>
<File>
<FileName>tos_task.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_task.c</FilePath>
</File>
<File>
<FileName>tos_tick.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_tick.c</FilePath>
</File>
<File>
<FileName>tos_time.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_time.c</FilePath>
</File>
<File>
<FileName>tos_timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\core\tos_timer.c</FilePath>
</File>
<File>
<FileName>tos_pm.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\pm\tos_pm.c</FilePath>
</File>
<File>
<FileName>tos_tickless.c</FileName>
<FileType>1</FileType>
<FilePath>..\TencentOS\kernel\pm\tos_tickless.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Tos/config</GroupName>
<Files>
<File>
<FileName>tos_config.h</FileName>
<FileType>5</FileType>
<FilePath>..\TencentOS\TOS_CONFIG\tos_config.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.1" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.1"/>
<targetInfos>
<targetInfo name="Target 1"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
</Project>

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<html>
<body>
<pre>
<h1><EFBFBD>Vision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: <20><>Vision V5.24.2.0
Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: qqwwaa Microsoft, Microsoft, LIC=ZB4HL-04R1B-VEVHA-1PZ8J-GB9KG-3WE7B
Tool Versions:
Toolchain: MDK-ARM Plus Version: 5.24.1
Toolchain Path: D:\MDK\ARM\ARMCLANG\Bin
C Compiler: ArmClang.exe V6.7
Assembler: Armasm.exe V6.7
Linker/Locator: ArmLink.exe V6.7
Library Manager: ArmAr.exe V6.7
Hex Converter: FromElf.exe V6.7
CPU DLL:
Dialog DLL:
Target DLL: NULink\Nu_Link.dll V3.00
Dialog DLL: TCM.DLL V1.32.0.0
<h2>Project:</h2>
C:\Users\Administrator\Desktop\Nuvoton_code\Nuvoton_M251\Project\NuvotonTos.uvprojx
Project File Date: 10/25/2019
<h2>Output:</h2>
*** Using Compiler 'V6.7', folder: 'D:\MDK\ARM\ARMCLANG\Bin'
Rebuild target 'Target 1'
compiling system_M251.c...
assembling startup_M251.s...
compiling clk.c...
compiling retarget.c...
compiling uart.c...
compiling gpio.c...
compiling sys.c...
compiling main.c...
compiling port_c.c...
compiling tos_cpu.c...
compiling tos_fault.c...
assembling port_s.S...
compiling tos_event.c...
compiling tos_fifo.c...
compiling tos_global.c...
compiling tos_mmblk.c...
compiling tos_mmheap.c...
compiling tos_msg.c...
compiling tos_mutex.c...
compiling tos_pend.c...
compiling tos_queue.c...
compiling tos_robin.c...
compiling tos_sched.c...
compiling tos_sem.c...
compiling tos_sys.c...
compiling tos_task.c...
compiling tos_tick.c...
compiling tos_time.c...
compiling tos_timer.c...
compiling tos_pm.c...
compiling tos_tickless.c...
linking...
Program Size: Code=7956 RO-data=552 RW-data=64 ZI-data=6880
".\Objects\NuvotonTos.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.0.1.pack
ARM.CMSIS.5.0.1
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.0.1
Package Vendor: Nuvoton
http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack/Nuvoton.NuMicro_DFP.1.3.4.pack
Nuvoton.NuMicro_DFP.1.3.4
Nuvoton ARM Cortex-M NuMicro Family Device Support
<h2>Collection of Component include folders:</h2>
.\RTE\_Target_1
D:\MDK\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include
D:\MDK\ARM\PACK\Nuvoton\NuMicro_DFP\1.3.4\Device\M251\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.0.1
Build Time Elapsed: 00:00:16
</pre>
</body>
</html>

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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00008000 { ; RW data
.ANY (+RW +ZI)
}
}

20
board/Nuvoton_M251/Project/RTE/_Target_1/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'NuvotonTos'
* Target: 'Target 1'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "M251.h"
#endif /* RTE_COMPONENTS_H */

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#include "stdio.h"
#include "NuMicro.h"
#include "tos.h"
#define task1_size 240 // size of task1 stack
#define task2_size 240
k_task_t task1; //structure of task1
k_task_t task2;
k_stack_t task1_stack[task1_size]; //stack of task1
k_stack_t task2_stack[task2_size];
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode to prevent leakage */
PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
/* Disable digital input path of analog pin XT1_OUT to prevent leakage */
GPIO_DISABLE_DIGITAL_PATH(PF, BIT2 | BIT3);
/* Enable<6C><65> HXT clock */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Switch HCLK clock source to external */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1)); //here switch zhe MCU clock to external
/*Set the core clock freq*/
CLK_SetCoreClock(FREQ_32MHZ); //set the core clock freq,should not higher than your HCLK clock freq
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HIRC and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
Uart0DefaultMPF();
}
void UART0_Init()
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
/* Reset UART module */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 baud rate */
UART_Open(UART0, 115200);
}
//task1 function
void task1_fun(void *Parameter)
{
while(1)
{
printf("Task1 <20><>Thansplant CORTEX-M23 Succeed\r\n");
PB14 =~ PB14;
tos_task_delay(1000);
}
}
//task2 function
void task2_task(void *Parameter)
{
k_err_t err;
while(1)
{
printf("Task2: hello world, hello Nuvoton \r\n");
tos_task_delay(100);
}
}
int main()
{
k_err_t err;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
tos_knl_init(); //tos init ,include SystickInit,should init after protected registers unlock
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("system clock to %d Hz, PLL clock to %d Hz...................... ", SystemCoreClock, CLK_SetCoreClock(FREQ_32MHZ));
GPIO_SetMode(PB, BIT14, GPIO_MODE_OUTPUT);
err = tos_task_create(
&task1,
"Task1",
task1_fun,
NULL,
2,
task1_stack,
task1_size,
100
);
err = tos_task_create(
&task2,
"display",
task2_task,
NULL,
2,
task2_stack,
task2_size,
100);
if(err != K_ERR_NONE)
printf("TenentOS creat task fail! code is %d\r\n",err);
tos_knl_start(); //Start TOS TINY
}

647
board/Nuvoton_M251/STARTUP/Include/M251.h Normal file
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/**************************************************************************//**
* @file M251.h
* @version V1.0
* @brief Peripheral Access Layer Header File
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
/**
\mainpage NuMicro M251/M252 Series CMSIS BSP Driver Reference
*
* <b>Introduction</b>
*
* This user manual describes the usage of M251/M252 Series MCU device driver
*
* <b>Disclaimer</b>
*
* The Software is furnished "AS IS", without warranty as to performance or results, and
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
* warranties, express, implied or otherwise, with regard to the Software, its use, or
* operation, including without limitation any and all warranties of merchantability, fitness
* for a particular purpose, and non-infringement of intellectual property rights.
*
* <b>Important Notice</b>
*
* Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
* any malfunction or failure of which may cause loss of human life, bodily injury or severe
* property damage. Such applications are deemed, "Insecure Usage".
*
* Insecure usage includes, but is not limited to: equipment for surgical implementation,
* atomic energy control instruments, airplane or spaceship instruments, the control or
* operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
* instruments, all types of safety devices, and other applications intended to support or
* sustain life.
*
* All Insecure Usage shall be made at customer's risk, and in the event that third parties
* lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
* the damages and liabilities thus incurred by Nuvoton.
*
* Please note that all data and specifications are subject to change without notice. All the
* trademarks of products and companies mentioned in this datasheet belong to their respective
* owners.
*
* <b>Copyright Notice</b>
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*/
#ifndef __M251_H__
#define __M251_H__
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup CMSIS_Device CMSIS Definitions
Configuration of the Cortex-M23 Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
/**
* @details Interrupt Number Definition.
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***********************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** ARMIKMCU Swift specific Interrupt Numbers ********************************************/
BOD_IRQn = 0, /*!< Brown-Out Low Voltage Detected Interrupt */
IRCTRIM_IRQn = 1, /*!< Watch Dog Timer Interrupt */
PWRWU_IRQn = 2, /*!< EINT0, EINT2 and EINT4 Interrupt */
RESERVE0 = 3, /*!< Reserve 0 */
CLKFAIL_IRQn = 4, /*!< Clock fail dector Interrupt */
RESERVE1 = 5, /*!< Reserve 1 */
RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
WDT_IRQn = 8, /*!< Watch Dog Timer Interrupt */
WWDT_IRQn = 9, /*!< Window Watch Dog Timer Interrupt */
EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
GPA_IRQn = 16, /*!< GPIO PORT A Interrupt */
GPB_IRQn = 17, /*!< GPIO PORT B Interrupt */
GPC_IRQn = 18, /*!< GPIO PORT C Interrupt */
GPD_IRQn = 19, /*!< GPIO PORT D Interrupt */
GPE_IRQn = 20, /*!< GPIO PORT E Interrupt */
GPF_IRQn = 21, /*!< GPIO PORT F Interrupt */
QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */
SPI0_IRQn = 23, /*!< SPI0 Interrupt */
BRAKE0_IRQn = 24, /*!< PWM Brake0 Interrupt */
PWM0_P0_IRQn = 25, /*!< PWM0 P0 Interrupt */
PWM0_P1_IRQn = 26, /*!< PWM0 P1 Interrupt */
PWM0_P2_IRQn = 27, /*!< PWM0 P2 Interrupt */
BRAKE1_IRQn = 28, /*!< PWM Brake1 Interrupt */
PWM1_P0_IRQn = 29, /*!< PWM1 P0 Interrupt */
PWM1_P1_IRQn = 30, /*!< PWM1 P1 Interrupt */
PWM1_P2_IRQn = 31, /*!< PWM1 P2 Interrupt */
TMR0_IRQn = 32, /*!< TIMER0 Interrupt */
TMR1_IRQn = 33, /*!< TIMER1 Interrupt */
TMR2_IRQn = 34, /*!< TIMER2 Interrupt */
TMR3_IRQn = 35, /*!< TIMER3 Interrupt */
UART0_IRQn = 36, /*!< UART0 Interrupt */
UART1_IRQn = 37, /*!< UART1 Interrupt */
I2C0_IRQn = 38, /*!< I2C0 Interrupt */
I2C1_IRQn = 39, /*!< I2C1 Interrupt */
PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
DAC_IRQn = 41, /*!< DAC Interrupt */
EADC_INT0_IRQn = 42, /*!< Enhance ADC Interrupt 0 */
EADC_INT1_IRQn = 43, /*!< Enhance ADC Interrupt 1 */
ACMP01_IRQn = 44, /*!< ACMP0 Interrupt */
BPWM0_IRQn = 45, /*!< BPWM0 Interrupt */
EADC_INT2_IRQn = 46, /*!< Enhance EADC Interrupt 2 */
EADC_INT3_IRQn = 47, /*!< Enhance EADC Interrupt 3 */
UART2_IRQn = 48, /*!< UART2 Interrupt */
RESERVE2 = 49, /*!< Reserve 2 */
USCI0_IRQn = 50, /*!< USCI0 Interrupt */
RESERVE3 = 51, /*!< Reserve 3 */
USCI1_IRQn = 52, /*!< USCI1 Interrupt */
USBD_IRQn = 53, /*!< USB Device Interrupt */
BPWM1_IRQn = 54, /*!< BPWM1 Interrupt */
PSIO_IRQn = 55, /*!< PSIO Interrupt */
RESERVE4 = 56, /*!< Reserve 4 */
CRPT_IRQn = 57, /*!< Cryption Interrupt */
SC0_IRQn = 58, /*!< Smart Card0 Interrupt */
RESERVE5 = 59, /*!< Reserve 5 */
USCI2_IRQn = 60, /*!< USCI2 Interrupt */
RESERVE6 = 61, /*!< Reserve 6 */
OPA_IRQn = 62, /*!< OPA Interrupt */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
#define __SAU_PRESENT 0U /* SAU present */
#define __MPU_PRESENT 4U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define USE_ASSERT 0U /* Define to use Assert function or not */
/*@}*/ /* end of group CMSIS_Device */
#include "core_armv8mbl.h" /* Processor and core peripherals */
#include "system_M251.h" /* System Header */
/**
* Initialize the system clock
*
* @param none
* @return none
*
* @brief Setup the micro controller system
* Initialize the PLL and update the SystemFrequency variable
*/
extern void SystemInit(void);
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
#include "acmp_reg.h"
#include "bpwm_reg.h"
#include "clk_reg.h"
#include "crc_reg.h"
#include "crypto_reg.h"
#include "dac_reg.h"
#include "eadc_reg.h"
#include "ebi_reg.h"
#include "fmc_reg.h"
#include "gpio_reg.h"
#include "i2c_reg.h"
#include "opa_reg.h"
#include "pdma_reg.h"
#include "psio_reg.h"
#include "pwm_reg.h"
#include "rtc_reg.h"
#include "sc_reg.h"
#include "qspi_reg.h"
#include "spi_reg.h"
#include "sys_reg.h"
#include "timer_reg.h"
#include "uart_reg.h"
#include "uuart_reg.h"
#include "ui2c_reg.h"
#include "uspi_reg.h"
#include "usbd_reg.h"
#include "wdt_reg.h"
#include "wwdt_reg.h"
/**@}*/ /* end of REGISTER group */
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base
Memory Mapped Structure for Series Peripheral
@{
*/
/* Peripheral and SRAM base address */
#define FLASH_BASE ((uint32_t)0x00000000UL) /*!< Flash Base Address */
#define SRAM_BASE ((uint32_t)0x20000000UL) /*!< SRAM Base Address */
#define PERIPH_BASE ((uint32_t)0x40000000UL) /*!< Peripheral Base Address */
/* Peripheral memory map */
#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */
#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) /*!< APB Base Address */
/*!< AHB peripherals */
#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL)
#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL)
/*!< APB0 peripherals */
#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define OPA_BASE (APBPERIPH_BASE + 0x06000UL)
#define TIMER01_BASE (APBPERIPH_BASE + 0x10000UL)
#define PWM0_BASE (APBPERIPH_BASE + 0x18000UL)
#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
#define USCI2_BASE (APBPERIPH_BASE + 0x92000UL)
/*!< APB1 peripherals */
#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
#define DAC_BASE (APBPERIPH_BASE + 0x07000UL)
#define TIMER23_BASE (APBPERIPH_BASE + 0x11000UL)
#define PWM1_BASE (APBPERIPH_BASE + 0x19000UL)
#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
#define PSIO_BASE (APBPERIPH_BASE + 0x83000UL)
#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
/**@}*/ /* end of group PERIPHERAL_BASE */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer
The Declaration of Peripheral Pointer
@{
*/
/*!< AHB peripherals */
#define SYS ((SYS_T *) SYS_BASE)
#define CLK ((CLK_T *) CLK_BASE)
#define PA ((GPIO_T *) GPIOA_BASE)
#define PB ((GPIO_T *) GPIOB_BASE)
#define PC ((GPIO_T *) GPIOC_BASE)
#define PD ((GPIO_T *) GPIOD_BASE)
#define PE ((GPIO_T *) GPIOE_BASE)
#define PF ((GPIO_T *) GPIOF_BASE)
#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
#define PDMA ((PDMA_T *) PDMA_BASE)
#define FMC ((FMC_T *) FMC_BASE)
#define EBI ((EBI_T *) EBI_BASE)
#define CRC ((CRC_T *) CRC_BASE)
#define CRPT ((CRPT_T *) CRPT_BASE)
/*!< APB0 peripherals */
#define WDT ((WDT_T *) WDT_BASE)
#define WWDT ((WWDT_T *) WWDT_BASE)
#define OPA ((OPA_T *) OPA_BASE)
#define TIMER0 ((TIMER_T *) TIMER01_BASE)
#define TIMER1 ((TIMER_T *) (TIMER01_BASE + 0x100UL))
#define PWM0 ((PWM_T *) PWM0_BASE)
#define BPWM0 ((BPWM_T *) BPWM0_BASE)
#define QSPI0 ((QSPI_T *) QSPI0_BASE)
#define UART0 ((UART_T *) UART0_BASE)
#define UART2 ((UART_T *) UART2_BASE)
#define I2C0 ((I2C_T *) I2C0_BASE)
#define SC0 ((SC_T *) SC0_BASE)
#define USBD ((USBD_T *) USBD_BASE)
#define UI2C0 ((UI2C_T *) USCI0_BASE)
#define USPI0 ((USPI_T *) USCI0_BASE)
#define UUART0 ((UUART_T *) USCI0_BASE)
#define UI2C2 ((UI2C_T *) USCI2_BASE)
#define USPI2 ((USPI_T *) USCI2_BASE)
#define UUART2 ((UUART_T *) USCI2_BASE)
/*!< APB1 peripherals */
#define RTC ((RTC_T *) RTC_BASE)
#define EADC ((EADC_T *) EADC_BASE)
#define ACMP01 ((ACMP_T *) ACMP01_BASE)
#define DAC ((DAC_T *) DAC_BASE)
#define TIMER2 ((TIMER_T *) TIMER23_BASE)
#define TIMER3 ((TIMER_T *) (TIMER23_BASE+ 0x100UL))
#define PWM1 ((PWM_T *) PWM1_BASE)
#define BPWM1 ((BPWM_T *) BPWM1_BASE)
#define SPI0 ((SPI_T *) SPI0_BASE)
#define UART1 ((UART_T *) UART1_BASE)
#define I2C1 ((I2C_T *) I2C1_BASE)
#define PSIO ((PSIO_T *) PSIO_BASE)
#define UI2C1 ((UI2C_T *) USCI1_BASE)
#define USPI1 ((USPI_T *) USCI1_BASE)
#define UUART1 ((UUART_T *) USCI1_BASE)
/**@}*/ /* end of group PERIPHERAL_DECLARATION */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
/*=============================================================================*/
/** @addtogroup IO_ROUTINE I/O Routines
The Declaration of I/O Routines
@{
*/
typedef volatile unsigned char vu8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
/**
* @brief Get a 8-bit unsigned value from specified address
* @param[in] addr Address to get 8-bit data from
* @return 8-bit unsigned value stored in specified address
*/
#define M8(addr) (*((vu8 *) (addr)))
/**
* @brief Get a 16-bit unsigned value from specified address
* @param[in] addr Address to get 16-bit data from
* @return 16-bit unsigned value stored in specified address
* @note The input address must be 16-bit aligned
*/
#define M16(addr) (*((vu16 *) (addr)))
/**
* @brief Get a 32-bit unsigned value from specified address
* @param[in] addr Address to get 32-bit data from
* @return 32-bit unsigned value stored in specified address
* @note The input address must be 32-bit aligned
*/
#define M32(addr) (*((vu32 *) (addr)))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inpw(port) ((*((volatile unsigned int *)(port))))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inps(port) ((*((volatile unsigned short *)(port))))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inpb(port) ((*((volatile unsigned char *)(port))))
/**
* @brief Set a 32-bit unsigned value to specified I/O port
* @param[in] port Port address to set 32-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 32-bit aligned
*/
#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
/**
* @brief Get a 32-bit unsigned value from specified I/O port
* @param[in] port Port address to get 32-bit data from
* @return 32-bit unsigned value stored in specified I/O port
* @note The input port must be 32-bit aligned
*/
#define inp32(port) ((*((volatile unsigned int *)(port))))
/**
* @brief Set a 16-bit unsigned value to specified I/O port
* @param[in] port Port address to set 16-bit data
* @param[in] value Value to write to I/O port
* @return None
* @note The output port must be 16-bit aligned
*/
#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
/**
* @brief Get a 16-bit unsigned value from specified I/O port
* @param[in] port Port address to get 16-bit data from
* @return 16-bit unsigned value stored in specified I/O port
* @note The input port must be 16-bit aligned
*/
#define inp16(port) ((*((volatile unsigned short *)(port))))
/**
* @brief Set a 8-bit unsigned value to specified I/O port
* @param[in] port Port address to set 8-bit data
* @param[in] value Value to write to I/O port
* @return None
*/
#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
/**
* @brief Get a 8-bit unsigned value from specified I/O port
* @param[in] port Port address to get 8-bit data from
* @return 8-bit unsigned value stored in specified I/O port
*/
#define inp8(port) ((*((volatile unsigned char *)(port))))
/*@}*/ /* end of group IO_ROUTINE */
/******************************************************************************/
/* Legacy Constants */
/******************************************************************************/
/** @addtogroup Legacy_Constants Legacy Constants
Legacy Constants
@{
*/
#define E_SUCCESS (0)
#ifndef NULL
#define NULL (0) ///< NULL pointer
#endif
#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value
#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value
#define ENABLE (1UL) ///< Enable, define to use in API parameters
#define DISABLE (0UL) ///< Disable, define to use in API parameters
/* Define one bit mask */
#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer
#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer
#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer
#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer
#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer
#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer
#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer
#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer
#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer
#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer
#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer
#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer
#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer
#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer
#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer
#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer
#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer
#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer
#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer
#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer
#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer
#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer
#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer
#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer
#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer
#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer
#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer
#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer
#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer
#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer
#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer
#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer
#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer
#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer
#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer
#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/*@}*/ /* end of group Legacy_Constants */
/******************************************************************************/
/* Peripheral header files */
/******************************************************************************/
#include "bpwm.h"
#include "sys.h"
#include "clk.h"
#include "uart.h"
#include "opa.h"
#include "acmp.h"
#include "rtc.h"
#include "fmc.h"
#include "gpio.h"
#include "i2c.h"
#include "pdma.h"
#include "pwm.h"
#include "qspi.h"
#include "spi.h"
#include "timer.h"
#include "timer_pwm.h"
#include "usci_i2c.h"
#include "usci_spi.h"
#include "usci_uart.h"
#include "usbd.h"
#include "rtc.h"
#include "crc.h"
#include "wdt.h"
#include "wwdt.h"
#include "eadc.h"
#include "dac.h"
#include "crypto.h"
#include "ebi.h"
#include "psio.h"
#include "sc.h"
#include "scuart.h"
#endif /* __M251_H__ */
/* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. */

15
board/Nuvoton_M251/STARTUP/Include/NuMicro.h Normal file
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@@ -0,0 +1,15 @@
/**************************************************************************//**
* @file NuMicro.h
* @version V1.00
* @brief NuMicro peripheral access layer header file.
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "M251.h"
#endif /* __NUMICRO_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file acmp_reg.h
* @version V1.00
* @brief ACMP register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_REG_H__
#define __ACMP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup ACMP Analog Comparator Controller (ACMP)
Memory Mapped Structure for ACMP Controller
@{ */
typedef struct
{
/**
* @var ACMP_T::CTL
* Offset: 0x00~0x04 Analog Comparator 0/1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPEN |Comparator Enable Bit
* | | |0 = Comparator x Disabled.
* | | |1 = Comparator x Enabled.
* |[1] |ACMPIE |Comparator Interrupt Enable Bit
* | | |0 = Comparator x interrupt Disabled.
* | | |1 = Comparator x interrupt Enabled
* | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
* |[3] |ACMPOINV |Comparator Output Inverse
* | | |0 = Comparator x output inverse Disabled.
* | | |1 = Comparator x output inverse Enabled.
* |[5:4] |NEGSEL |Comparator Negative Input Selection
* | | |00 = ACMPx_N pin.
* | | |01 = Internal comparator reference voltage (CRV).
* | | |10 = Band-gap voltage.
* | | |11 = DAC output.
* |[7:6] |POSSEL |Comparator Positive Input Selection
* | | |00 = Input from ACMPx_P0.
* | | |01 = Input from ACMPx_P1.
* | | |10 = Input from ACMPx_P2.
* | | |11 = Input from ACMPx_P3.
* |[9:8] |INTPOL |Interrupt Condition Polarity Selection
* | | |ACMPIFx will be set to 1 when comparator output edge condition is detected.
* | | |00 = Rising edge or falling edge.
* | | |01 = Rising edge.
* | | |10 = Falling edge.
* | | |11 = Reserved.
* |[12] |OUTSEL |Comparator Output Select
* | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output.
* | | |1 = Comparator x output to ACMPx_O pin is from filter output.
* |[15:13] |FILTSEL |Comparator Output Filter Count Selection
* | | |000 = Filter function is Disabled.
* | | |001 = ACMPx output is sampled 1 consecutive PCLK.
* | | |010 = ACMPx output is sampled 2 consecutive PCLKs.
* | | |011 = ACMPx output is sampled 4 consecutive PCLKs.
* | | |100 = ACMPx output is sampled 8 consecutive PCLKs.
* | | |101 = ACMPx output is sampled 16 consecutive PCLKs.
* | | |110 = ACMPx output is sampled 32 consecutive PCLKs.
* | | |111 = ACMPx output is sampled 64 consecutive PCLKs.
* |[16] |WKEN |Power-down Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[17] |WLATEN |Window Latch Mode Enable Bit
* | | |0 = Window Latch Mode Disabled.
* | | |1 = Window Latch Mode Enabled.
* |[18] |WCMPSEL |Window Compare Mode Selection
* | | |0 = Window Compare Mode Disabled.
* | | |1 = Window Compare Mode is Selected.
* |[25:24] |HYSSEL |Hysteresis Mode Selection
* | | |00 = Hysteresis is 0mV.
* | | |01 = Hysteresis is 10mV.
* | | |10 = Hysteresis is 20mV.
* | | |11 = Hysteresis is 30mV.
* |[29:28] |MODESEL |Propagation Delay Mode Selection
* | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
* | | |01 = Max propagation delay is 2uS, operation current is 3uA.
* | | |10 = Max propagation delay is 600nS, operation current is 10uA.
* | | |11 = Max propagation delay is 200nS, operation current is 75uA.
* @var ACMP_T::STATUS
* Offset: 0x08 Analog Comparator Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
* | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
* | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
* | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
* | | |Note: Write 1 to clear this bit to 0.
* |[4] |ACMPO0 |Comparator 0 Output
* | | |Synchronized to the PCLK to allow reading by software.
* | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[5] |ACMPO1 |Comparator 1 Output
* | | |Synchronized to the PCLK to allow reading by software.
* | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag
* | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
* | | |0 = No power-down wake-up occurred.
* | | |1 = Power-down wake-up occurred.
* | | |Note: Write 1 to clear this bit to 0.
* |[12] |ACMPS0 |Comparator 0 Status
* | | |Synchronized to the PCLK to allow reading by software.
* | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
* |[13] |ACMPS1 |Comparator 1 Status
* | | |Synchronized to the PCLK to allow reading by software
* | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
* |[16] |ACMPWO |Comparator Window Output
* | | |This bit shows the output status of window compare mode
* | | |0 = The positive input voltage is outside the window.
* | | |1 = The positive input voltage is in the window.
* @var ACMP_T::VREF
* Offset: 0x0C Analog Comparator Reference Voltage Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CRVCTL |Comparator Reference Voltage Setting
* | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
* |[6] |CRVSSEL |CRV Source Voltage Selection
* | | |0 = AVDD is selected as CRV source voltage.
* | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
*/
__IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */
__IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */
__IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */
} ACMP_T;
/**
@addtogroup ACMP_CONST ACMP Bit Field Definition
Constant Definitions for ACMP Controller
@{ */
#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */
#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */
#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */
#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */
#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */
#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */
#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */
#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */
#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */
#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */
#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */
#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */
#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */
#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */
#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
/**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __ACMP_REG_H__ */

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/**************************************************************************//**
* @file crc_reg.h
* @version V1.00
* @brief CRC register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_REG_H__
#define __CRC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup CRC Cyclic Redundancy Check Controller (CRC)
Memory Mapped Structure for CRC Controller
@{ */
typedef struct
{
/**
* @var CRC_T::CTL
* Offset: 0x00 CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCEN |CRC Channel Enable Bit
* | | |0 = No effect.
* | | |1 = CRC operation Enabled.
* |[1] |CHKSINIT |Checksum Initialization
* | | |0 = No effect.
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
* | | |Note: This bit will be cleared automatically.
* |[24] |DATREV |Write Data Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
* | | |0 = Bit order reversed for CRC write data in Disabled.
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
* |[25] |CHKSREV |Checksum Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
* | | |0 = Bit order reverse for CRC checksum Disabled.
* | | |1 = Bit order reverse for CRC checksum Enabled.
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
* |[26] |DATFMT |Write Data 1's Complement
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
* | | |0 = 1's complement for CRC writes data in Disabled.
* | | |1 = 1's complement for CRC writes data in Enabled.
* |[27] |CHKSFMT |Checksum 1's Complement
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
* | | |0 = 1's complement for CRC checksum Disabled.
* | | |1 = 1's complement for CRC checksum Enabled.
* |[29:28] |DATLEN |CPU Write Data Length
* | | |This field indicates the write data length.
* | | |00 = Data length is 8-bit mode.
* | | |01 = Data length is 16-bit mode.
* | | |1x = Data length is 32-bit mode.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
* |[31:30] |CRCMODE |CRC Polynomial Mode
* | | |This field indicates the CRC operation polynomial mode.
* | | |00 = CRC-CCITT Polynomial mode.
* | | |01 = CRC-8 Polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |11 = CRC-32 Polynomial mode.
* @var CRC_T::DAT
* Offset: 0x04 CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |CRC Write Data Bits
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* @var CRC_T::SEED
* Offset: 0x08 CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |CRC Seed Value
* | | |This field indicates the CRC seed value.
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
* @var CRC_T::CHECKSUM
* Offset: 0x0C CRC Checksum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CHECKSUM |CRC Checksum Results
* | | |This field indicates the CRC checksum result.
*/
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
} CRC_T;
/**
@addtogroup CRC_CONST CRC Bit Field Definition
Constant Definitions for CRC Controller
@{ */
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
/**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CRC_REG_H__ */

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/**************************************************************************//**
* @file crypto_reg.h
* @version V1.00
* @brief CRYPTO register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRYPTO_REG_H__
#define __CRYPTO_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup CRPT Cryptographic Accelerator (CRPT)
Memory Mapped Structure for Cryptographic Accelerator
@{ */
typedef struct
{
/**
* @var CRPT_T::INTEN
* Offset: 0x00 Crypto Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AESIEN |AES Interrupt Enable Bit
* | | |0 = AES interrupt Disabled.
* | | |1 = AES interrupt Enabled.
* | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
* | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
* |[1] |AESEIEN |AES Error Flag Enable Bit
* | | |0 = AES error interrupt flag Disabled.
* | | |1 = AES error interrupt flag Enabled.
* |[16] |PRNGIEN |PRNG Interrupt Enable Bit
* | | |0 = PRNG interrupt Disabled.
* | | |1 = PRNG interrupt Enabled.
* @var CRPT_T::INTSTS
* Offset: 0x04 Crypto Interrupt Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |AESIF |AES Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No AES interrupt.
* | | |1 = AES encryption/decryption done interrupt.
* |[1] |AESEIF |AES Error Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No AES error.
* | | |1 = AES encryption/decryption error interrupt.
* |[16] |PRNGIF |PRNG Finish Interrupt Flag
* | | |This bit is cleared by writing 1, and it has no effect by writing 0.
* | | |0 = No PRNG interrupt.
* | | |1 = PRNG key generation done interrupt.
* @var CRPT_T::PRNG_CTL
* Offset: 0x08 PRNG Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |Start PRNG Engine
* | | |0 = Stop PRNG engine.
* | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated.
* |[1] |SEEDRLD |Reload New Seed for PRNG Engine
* | | |0 = Generating key based on the current seed.
* | | |1 = Reload new seed.
* |[3:2] |KEYSZ |PRNG Generate Key Size
* | | |00 = 64 bits.
* | | |01 = 128 bits.
* | | |10 = 192 bits.
* | | |11 = 256 bits.
* |[8] |BUSY |PRNG Busy (Read Only)
* | | |0 = PRNG engine is idle.
* | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
* @var CRPT_T::PRNG_SEED
* Offset: 0x0C Seed for PRNG
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |Seed for PRNG (Write Only)
* | | |The bits store the seed for PRNG engine.
* @var CRPT_T::PRNG_KEY[8]
* Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |Store PRNG Generated Key (Read Only)
* | | |The bits store the key that is generated by PRNG.
* @var CRPT_T::AES_FDBCK[4]
* Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data After Cryptographic Operation
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |FDBCK |AES Feedback Information
* | | |The feedback value is 128 bits in size.
* | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode.
* | | |The AES engine outputs feedback information for IV in the next block's operation
* | | |Software can store that feedback value temporarily
* | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same operation, and then continue the operation with the original setting.
* @var CRPT_T::AES_CTL
* Offset: 0x100 AES Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |START |AES Engine Start
* | | |0 = No effect.
* | | |1 = Start AES engine. BUSY flag will be set.
* | | |Note: This bit is always 0 when it's read back.
* |[1] |STOP |AES Engine Stop
* | | |0 = No effect.
* | | |1 = Stop AES engine.
* | | |Note: This bit is always 0 when it's read back.
* |[3:2] |KEYSZ |AES Key Size
* | | |This bit defines three different key size for AES operation.
* | | |2'b00 = 128 bits key.
* | | |2'b01 = 192 bits key.
* | | |2'b10 = 256 bits key.
* | | |2'b11 = Reserved.
* | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
* |[5] |DMALAST |AES Last Block
* | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
* | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
* | | |This bit is always 0 when it's read back. Must be written again once START is triggered.
* |[6] |DMACSCAD |AES Engine DMA with Cascade Mode
* | | |0 = DMA cascade function Disabled.
* | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
* |[7] |DMAEN |AES Engine DMA Enable Bit
* | | |0 = AES DMA engine Disabled.
* | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN.
* | | |1 = AES_DMA engine Enabled.
* | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
* |[15:8] |OPMODE |AES Engine Operation Modes
* | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode).
* | | |0x02 = CFB (Cipher Feedback Mode).
* | | |0x03 = OFB (Output Feedback Mode).
* | | |0x04 = CTR (Counter Mode).
* | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
* | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
* | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
* |[16] |ENCRYPTO |AES Encryption/Decryption
* | | |0 = AES engine executes decryption operation.
* | | |1 = AES engine executes encryption operation.
* |[22] |OUTSWAP |AES Engine Output Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[23] |INSWAP |AES Engine Input Data Swap
* | | |0 = Keep the original order.
* | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
* |[30:26] |KEYUNPRT |Unprotect Key
* | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key.
* | | |The KEYUNPRT can be read and written
* | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
* |[31] |KEYPRT |Protect Key
* | | |Read as a flag to reflect KEYPRT.
* | | |0 = No effect.
* | | |1 = Protect the content of the AES key from reading
* | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx
* | | |Once it is set, it can be cleared by asserting KEYUNPRT
* | | |And the key content would be cleared as well.
* @var CRPT_T::AES_STS
* Offset: 0x104 AES Engine Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |AES Engine Busy
* | | |0 = The AES engine is idle or finished.
* | | |1 = The AES engine is under processing.
* |[8] |INBUFEMPTY|AES Input Buffer Empty
* | | |0 = There are some data in input buffer waiting for the AES engine to process.
* | | |1 = AES input buffer is empty
* | | |Software needs to feed data to the AES engine
* | | |Otherwise, the AES engine will be pending to wait for input data.
* |[9] |INBUFFULL |AES Input Buffer Full Flag
* | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.
* | | |1 = AES input buffer is full
* | | |Software cannot feed data to the AES engine
* | | |Otherwise, the flag INBUFERR will be set to 1.
* |[10] |INBUFERR |AES Input Buffer Error Flag
* | | |0 = No error.
* | | |1 = Error happens during feeding data to the AES engine.
* |[12] |CNTERR |CRPT_AES_CNT Setting Error
* | | |0 = No error in CRPT_AES_CNT setting.
* | | |1 = CRPT_AES_CNT is 0 if DMAEN (CRPT_AES_CTL[7]) is enabled.
* |[16] |OUTBUFEMPTY|AES Out Buffer Empty
* | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
* | | |1 = AES output buffer is empty
* | | |Software cannot get data from CRPT_AES_DATOUT
* | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
* |[17] |OUTBUFFULL|AES Out Buffer Full Flag
* | | |0 = AES output buffer is not full.
* | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
* | | |Otherwise, the AES engine will be pending since the output buffer is full.
* |[18] |OUTBUFERR |AES Out Buffer Error Flag
* | | |0 = No error.
* | | |1 = Error happens during getting the result from AES engine.
* |[20] |BUSERR |AES DMA Access Bus Error Flag
* | | |0 = No error.
* | | |1 = Bus error will stop DMA operation and AES engine.
* @var CRPT_T::AES_DATIN
* Offset: 0x108 AES Engine Data Input Port Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATIN |AES Engine Input Port
* | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
* @var CRPT_T::AES_DATOUT
* Offset: 0x10C AES Engine Data Output Port Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATOUT |AES Engine Output Port
* | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
* | | |Get data as OUTBUFEMPTY is 0.
* @var CRPT_T::AES_KEY[8]
* Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |KEY |CRPT_AESn_KEYx
* | | |The KEY keeps the security key for AES operation.
* | | |x = 0, 1..7.
* | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
* | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation
* | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation
* | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation.
* @var CRPT_T::AES_IV[4]
* Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |IV |AES Initial Vectors
* | | |x = 0, 1..3.
* | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode
* | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
* @var CRPT_T::AES_SADDR
* Offset: 0x140 AES DMA Source Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |AES DMA Source Address
* | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO
* | | |The SADDR keeps the source address of the data buffer where the source text is stored
* | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation
* | | |The start of source address should be located at word boundary
* | | |In other words, bit 1 and 0 of SADDR are ignored.
* | | |SADDR can be read and written
* | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of SADDR will be updated later on
* | | |Consequently, software can prepare the DMA source address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START.
* | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same.
* @var CRPT_T::AES_DADDR
* Offset: 0x144 AES DMA Destination Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DADDR |AES DMA Destination Address
* | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO
* | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
* | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished
* | | |The start of destination address should be located at word boundary
* | | |In other words, bit 1 and 0 of DADDR are ignored.
* | | |DADDR can be read and written
* | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of DADDR will be updated later on
* | | |Consequently, software can prepare the destination address for the next AES operation.
* | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START.
* | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same.
* @var CRPT_T::AES_CNT
* Offset: 0x148 AES Byte Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |AES Byte Count
* | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
* | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
* | | |CRPT_AESn_CNT can be read and written
* | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesn't affect the current AES operation
* | | |But the value of CRPT_AESn_CNT will be updated later on
* | | |Consequently, software can prepare the byte count of data for the next AES operation.
* | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes
* | | |Operations that are qual or less than one block will output unexpected result.
* | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data
* | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
*/
__IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */
__IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */
__O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */
__I uint32_t PRNG_KEY[8]; /*!< [0x0010 ~ 0x002c] PRNG Generated Key0 ~ 7 */
__I uint32_t RESERVE0[8];
__I uint32_t AES_FDBCK[4]; /*!< [0x0050 ~ 0x005c] AES Engine Output Feedback Data After Cryptographic Operation*/
__I uint32_t RESERVE1[40];
__IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */
__I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */
__IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */
__I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */
__IO uint32_t AES_KEY[8]; /*!< [0x0110 ~ 0x012c] AES Key Word 0 ~ 7 Register */
__IO uint32_t AES_IV[4]; /*!< [0x0130 ~ 0x013c] AES Initial Vector Word 0 ~3 Register */
__IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */
__IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */
__IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */
} CRPT_T;
/**
@addtogroup CRPT_CONST CRYPTO Bit Field Definition
Constant Definitions for CRYPTO Controller
@{ */
#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */
#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */
#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */
#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */
#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */
#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */
#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */
#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */
#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */
#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */
#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */
#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */
#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */
#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */
#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */
#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */
#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */
#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */
#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */
#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */
#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */
#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */
#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */
#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY:[8] KEY Mask */
#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */
#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */
#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */
#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */
#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */
#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */
#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */
#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */
#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */
#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */
#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */
#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */
#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */
#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */
#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */
#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */
#define CRPT_AES_CTL_ENCRYPTO_Pos (16) /*!< CRPT_T::AES_CTL: ENCRYPTO Position */
#define CRPT_AES_CTL_ENCRYPTO_Msk (0x1ul << CRPT_AES_CTL_ENCRYPTO_Pos) /*!< CRPT_T::AES_CTL: ENCRYPTO Mask */
#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */
#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */
#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */
#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */
#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */
#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */
#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */
#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */
#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */
#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */
#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */
#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */
#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */
#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */
#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */
#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */
#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */
#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */
#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/
#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */
#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */
#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */
#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */
#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */
#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */
#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */
#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */
#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */
#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */
#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */
#define CRPT_AES_KEYx_KEY_Pos (0) /*!< CRPT_T::AES_KEY[8]: KEY Position */
#define CRPT_AES_KEYx_KEY_Msk (0xfffffffful << CRPT_AES_KEYx_KEY_Pos) /*!< CRPT_T::AES_KEY[8]: KEY Mask */
#define CRPT_AES_IVx_IV_Pos (0) /*!< CRPT_T::AES_IV[4]: IV Position */
#define CRPT_AES_IVx_IV_Msk (0xfffffffful << CRPT_AES_IVx_IV_Pos) /*!< CRPT_T::AES_IV[4]: IV Mask */
#define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */
#define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */
#define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */
#define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */
#define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */
#define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */
/**@}*/ /* CRPT_CONST CRYPTO */
/**@}*/ /* end of CRYPTO register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CRYPTO_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/dac_reg.h Normal file
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@@ -0,0 +1,203 @@
/**************************************************************************//**
* @file dac_reg.h
* @version V1.00
* @brief DAC register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DAC_REG_H__
#define __DAC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup DAC Digital to Analog Converter (DAC)
Memory Mapped Structure for DAC Controller
@{ */
typedef struct
{
/**
* @var DAC_T::CTL
* Offset: 0x00 DAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DACEN |DAC Enable Bit
* | | |0 = DAC is Disabled.
* | | |1 = DAC is Enabled.
* |[1] |DACIEN |DAC Interrupt Enable Bit
* | | |0 = Interrupt is Disabled.
* | | |1 = Interrupt is Enabled.
* |[2] |DMAEN |DMA Mode Enable Bit
* | | |0 = DMA mode Disabled.
* | | |1 = DMA mode Enabled.
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
* | | |0 = DMA underrun interrupt Disabled.
* | | |1 = DMA underrun interrupt Enabled.
* |[4] |TRGEN |Trigger Mode Enable Bit
* | | |0 = DAC event trigger mode Disabled.
* | | |1 = DAC event trigger mode Enabled.
* |[7:5] |TRGSEL |Trigger Source Selection
* | | |000 = Software trigger.
* | | |001 = External pin DAC_ST trigger.
* | | |010 = Timer 0 trigger.
* | | |011 = Timer 1 trigger.
* | | |100 = Timer 2 trigger.
* | | |101 = Timer 3 trigger.
* | | |Others = reserved.
* |[8] |BYPASS |Bypass Buffer Mode
* | | |0 = Output voltage buffer Enabled.
* | | |1 = Output voltage buffer Disabled.
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
* | | |0 = Right alignment.
* | | |1 = Left alignment.
* |[13:12] |ETRGSEL |External Pin Trigger Selection
* | | |00 = Low level trigger.
* | | |01 = High level trigger.
* | | |10 = Falling edge trigger.
* | | |11 = Rising edge trigger.
* |[15:14] |BWSEL |DAC Data Bit-width Selection
* | | |00 = data is 12 bits.
* | | |01 = data is 8 bits.
* | | |Others = reserved.
* @var DAC_T::SWTRG
* Offset: 0x04 DAC Software Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWTRG |Software Trigger
* | | |0 = Software trigger Disabled.
* | | |1 = Software trigger Enabled.
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
* @var DAC_T::DAT
* Offset: 0x08 DAC Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DACDAT |DAC 12-bit Holding Data
* | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
* | | |DAC 8-bit Holding Data
* | | |The unused bits DAC_DAT[15:8] are ignored by DAC controller hardware.
* | | |Note: Conversion data and DAC output data is 12-bit
* @var DAC_T::DATOUT
* Offset: 0x0C DAC Data Output Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DATOUT |DAC 12-bit Output Data
* | | |These bits are current digital data for DAC output conversion.
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
* @var DAC_T::STATUS
* Offset: 0x10 DAC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |DAC Conversion Complete Finish Flag
* | | |0 = DAC is in conversion state.
* | | |1 = DAC conversion finish.
* | | |This bit set to 1 when conversion time counter counts to SETTLET
* | | |It is cleared to 0 when DAC starts a new conversion
* | | |User writes 1 to clear this bit to 0.
* |[1] |DMAUDR |DMA Under Run Interrupt Flag
* | | |0 = No DMA under-run error condition occurred.
* | | |1 = DMA under-run error condition occurred.
* | | |User writes 1 to clear this bit.
* |[8] |BUSY |DAC Busy Flag (Read Only)
* | | |0 = DAC is ready for next conversion.
* | | |1 = DAC is busy in conversion.
* | | |This is read only bit.
* @var DAC_T::TCTL
* Offset: 0x14 DAC Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |SETTLET |DAC Output Settling Time
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
* | | |For example, DAC controller clock speed is 50MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x32.
*/
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
} DAC_T;
/**
@addtogroup DAC_CONST DAC Bit Field Definition
Constant Definitions for DAC Controller
@{ */
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
/**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __DAC_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/eadc_reg.h Normal file
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/**************************************************************************//**
* @file eadc_reg.h
* @version V1.00
* @brief EADC register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EADC_REG_H__
#define __EADC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup EADC Enhanced Analog to Digital Converter (EADC)
Memory Mapped Structure for EADC Controller
@{ */
typedef struct
{
/**
* @var EADC_T::DAT[19]
* Offset: 0x00~0x48 A/D Data Register 0~18 for Sample Module 0 ~ 18
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RESULT |A/D Conversion Result
* | | |This field contains 12 bits conversion result.
* |[16] |OV |Overrun Flag
* | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
* | | |0 = Data in RESULT[11:0] is recent conversion result.
* | | |1 = Data in RESULT[11:0] is overwrite.
* | | |Note: It is cleared by hardware after EADC_DAT register is read.
* |[17] |VALID |Valid Flag
* | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
* | | |0 = Data in RESULT[11:0] bits is not valid.
* | | |1 = Data in RESULT[11:0] bits is valid.
* @var EADC_T::CURDAT
* Offset: 0x4C EADC PDMA Current Transfer Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |CURDAT |ADC PDMA Current Transfer Data (Read Only)
* | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
* | | |This is a read only register.
* | | |NOTE: After PDMA read this register, the VAILD of the shadow EADC_DAT register will be automatically cleared.
* @var EADC_T::CTL
* Offset: 0x50 A/D Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADCEN |A/D Converter Enable Bit
* | | |0 = ADC Disabled.
* | | |1 = ADC Enabled.
* | | |Note: Before starting A/D conversion function, this bit should be set to 1
* | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
* |[1] |ADCRST |ADC A/D Converter Control Circuits Reset
* | | |0 = No effect.
* | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
* | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
* |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
* | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion
* | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
* | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
* | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
* |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
* | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion
* | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
* | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
* | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
* |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
* | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion
* | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
* | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
* | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
* |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
* | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion
* | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
* | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
* | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
* @var EADC_T::SWTRG
* Offset: 0x54 A/D Sample Module Software Start Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |SWTRG |A/D Sample Module 0~18 Software Force to Start ADC Conversion
* | | |0 = No effect.
* | | |1 = Cause an ADC conversion when the priority is given to sample module.
* | | |Note: After writing this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion
* | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
* @var EADC_T::PENDSTS
* Offset: 0x58 A/D Start of Conversion Pending Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |STPF |A/D Sample Module 0~18 Start of Conversion Pending Flag
* | | |Read:
* | | |0 = There is no pending conversion for sample module.
* | | |1 = Sample module ADC start of conversion is pending.
* | | |Write:
* | | |1 = Clear pending flag and stop conversion for corresponding sample module.
* | | |Note1: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0.
* | | |Note2: After stopping current conversion, the corresponding EADC_DATn (n=0~18) keeps its original value
* @var EADC_T::OVSTS
* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag
* | | |0 = No sample module event overrun.
* | | |1 = Indicates a new sample module event is generated while an old one event is pending.
* | | |Note: This bit is cleared by writing 1 to it.
* @var EADC_T::SCTL[16]
* Offset: 0x80~0xBC A/D Sample Module 0 ~ 15 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CHSEL |A/D Sample Module Channel Selection
* | | |00H = EADC_CH0.
* | | |01H = EADC_CH1.
* | | |02H = EADC_CH2.
* | | |03H = EADC_CH3.
* | | |04H = EADC_CH4.
* | | |05H = EADC_CH5.
* | | |06H = EADC_CH6.
* | | |07H = EADC_CH7.
* | | |08H = EADC_CH8.
* | | |09H = EADC_CH9.
* | | |0AH = EADC_CH10.
* | | |0BH = EADC_CH11.
* | | |0CH = EADC_CH12.
* | | |0DH = EADC_CH13.
* | | |0EH = EADC_CH14.
* | | |0FH = EADC_CH15.
* | | |Note: when internal ADC channel16, 17 or 18 is selected, EADC_CH15 is useless.
* |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
* | | |0 = Rising edge Disabled when A/D selects EADC0_ST as trigger source.
* | | |1 = Rising edge Enabled when A/D selects EADC0_ST trigger source.
* |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
* | | |0 = Falling edge Disabled when A/D selects EADC0_ST as trigger source.
* | | |1 = Falling edge Enabled when A/D selects EADC0_ST as trigger source.
* |[7:6] |TRGDLYDIV |A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection
* | | |Trigger delay clock frequency:
* | | |00 = ADC_CLK/1.
* | | |01 = ADC_CLK/2.
* | | |10 = ADC_CLK/4.
* | | |11 = ADC_CLK/16.
* |[15:8] |TRGDLYCNT |A/D Sample Module Start of Conversion Trigger Delay Time
* | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
* | | |Note: If TRGDLYCNT is set to 1, Trigger delay time is actullay the same as TRGDLYCNT is set to 2 for hardware operation.
* |[20:16] |TRGSEL |A/D Sample Module Start of Conversion Trigger Source Selection
* | | |0H = Disable trigger.
* | | |1H = External trigger from EADC0_ST pin input.
* | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
* | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
* | | |4H = Timer0 overflow pulse trigger.
* | | |5H = Timer1 overflow pulse trigger.
* | | |6H = Timer2 overflow pulse trigger.
* | | |7H = Timer3 overflow pulse trigger.
* | | |8H = PWM0TG0.
* | | |9H = PWM0TG1.
* | | |AH = PWM0TG2.
* | | |BH = PWM0TG3.
* | | |CH = PWM0TG4.
* | | |DH = PWM0TG5.
* | | |EH = PWM1TG0.
* | | |FH = PWM1TG1.
* | | |10H = PWM1TG2.
* | | |11H = PWM1TG3.
* | | |12H = PWM1TG4.
* | | |13H = PWM1TG5.
* | | |14H =BPWM0TG.
* | | |15H =BPWM1TG.
* | | |other = Reserved.
* | | |NOTE: Refer PWM_EADCTS0, PWM_EADCTS1, BPWM_EADCTS0, BPWM_ EADCTS1 and TIMERn_CTL (n=0~3) to get more information for PWM, BPWM trigger and timer trigger.
* |[22] |INTPOS |Interrupt Flag Position Select
* | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
* | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
* |[31:24] |EXTSMPT |ADC Sampling Time Extend
* | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time
* | | |EXTSMPT can be set from 0~8'd251.
* @var EADC_T::SCTL0[3]
* Offset: 0xc0~0xC8 A/D Sample Module 16 ~ 18 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMAEN |PDMA Transfer Enable Bit
* | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 16 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
* | | |0 = PDMA data transfer Disabled.
* | | |1 = PDMA data transfer Enabled.
* | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
* |[31:24] |EXTSMPT |ADC Sampling Time Extend
* | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time
* | | |EXTSMPT can be set from 0~8'd251.
* @var EADC_T::INTSRC[4]
* Offset: 0xD0~0xDC ADC Interrupt 0~4 Source Enable Control Register.
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
* | | |0 = Sample Module 0 interrupt Disabled.
* | | |1 = Sample Module 0 interrupt Enabled.
* |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
* | | |0 = Sample Module 1 interrupt Disabled.
* | | |1 = Sample Module 1 interrupt Enabled.
* |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
* | | |0 = Sample Module 2 interrupt Disabled.
* | | |1 = Sample Module 2 interrupt Enabled.
* |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
* | | |0 = Sample Module 3 interrupt Disabled.
* | | |1 = Sample Module 3 interrupt Enabled.
* |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
* | | |0 = Sample Module 4 interrupt Disabled.
* | | |1 = Sample Module 4 interrupt Enabled.
* |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
* | | |0 = Sample Module 5 interrupt Disabled.
* | | |1 = Sample Module 5 interrupt Enabled.
* |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
* | | |0 = Sample Module 6 interrupt Disabled.
* | | |1 = Sample Module 6 interrupt Enabled.
* |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
* | | |0 = Sample Module 7 interrupt Disabled.
* | | |1 = Sample Module 7 interrupt Enabled.
* |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
* | | |0 = Sample Module 8 interrupt Disabled.
* | | |1 = Sample Module 8 interrupt Enabled.
* |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
* | | |0 = Sample Module 9 interrupt Disabled.
* | | |1 = Sample Module 9 interrupt Enabled.
* |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
* | | |0 = Sample Module 10 interrupt Disabled.
* | | |1 = Sample Module 10 interrupt Enabled.
* |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
* | | |0 = Sample Module 11 interrupt Disabled.
* | | |1 = Sample Module 11 interrupt Enabled.
* |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
* | | |0 = Sample Module 12 interrupt Disabled.
* | | |1 = Sample Module 12 interrupt Enabled.
* |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
* | | |0 = Sample Module 13 interrupt Disabled.
* | | |1 = Sample Module 13 interrupt Enabled.
* |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
* | | |0 = Sample Module 14 interrupt Disabled.
* | | |1 = Sample Module 14 interrupt Enabled.
* |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
* | | |0 = Sample Module 15 interrupt Disabled.
* | | |1 = Sample Module 15 interrupt Enabled.
* |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
* | | |0 = Sample Module 16 interrupt Disabled.
* | | |1 = Sample Module 16 interrupt Enabled.
* |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
* | | |0 = Sample Module 17 interrupt Disabled.
* | | |1 = Sample Module 17 interrupt Enabled.
* |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
* | | |0 = Sample Module 18 interrupt Disabled.
* | | |1 = Sample Module 18 interrupt Enabled.
* @var EADC_T::CMP[4]
* Offset: 0xE0~0xEC A/D Result Compare Register 0 ~ 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADCMPEN |A/D Result Compare Enable Bit
* | | |0 = Compare Disabled.
* | | |1 = Compare Enabled.
* | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
* |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit
* | | |0 = Compare function interrupt Disabled.
* | | |1 = Compare function interrupt Enabled.
* | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
* |[2] |CMPCOND |Compare Condition
* | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
* | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
* | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the ADCMPFn bit will be set.
* |[7:3] |CMPSPL |Compare Sample Module Selection
* | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
* | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
* | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
* | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
* | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
* | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
* | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
* | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
* | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
* | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
* | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
* | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
* | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
* | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
* | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
* | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
* | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
* | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
* | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
* |[11:8] |CMPMCNT |Compare Match Count
* | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1
* | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0
* | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
* |[15] |CMPWEN |Compare Window Mode Enable Bit
* | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched
* | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
* | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched
* | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
* | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
* |[27:16] |CMPDAT |Comparison Data
* | | |The 12 bits data is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
* @var EADC_T::STATUS0
* Offset: 0xF0 A/D Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
* | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~15).
* |[31:16] |OV |EADC_DAT0~15 Overrun Flag
* | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~15).
* @var EADC_T::STATUS1
* Offset: 0xF4 A/D Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
* | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=16~18).
* |[18:16] |OV |EADC_DAT16~18 Overrun Flag
* | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=16~18).
* @var EADC_T::STATUS2
* Offset: 0xF8 A/D Status Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
* | | |0 = No ADINT0 interrupt pulse received.
* | | |1 = ADINT0 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
* |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
* | | |0 = No ADINT1 interrupt pulse received.
* | | |1 = ADINT1 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
* |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
* | | |0 = No ADINT2 interrupt pulse received.
* | | |1 = ADINT2 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
* |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
* | | |0 = No ADINT3 interrupt pulse received.
* | | |1 = ADINT3 interrupt pulse has been received.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
* |[4] |ADCMPF0 |ADC Compare 0 Flag
* | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[5] |ADCMPF1 |ADC Compare 1 Flag
* | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[6] |ADCMPF2 |ADC Compare 2 Flag
* | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[7] |ADCMPF3 |ADC Compare 3 Flag
* | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
* | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
* | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
* | | |Note: This bit is cleared by writing 1 to it.
* |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun
* | | |0 = ADINT0 interrupt flag is not overwritten to 1.
* | | |1 = ADINT0 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun
* | | |0 = ADINT1 interrupt flag is not overwritten to 1.
* | | |1 = ADINT1 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun
* | | |0 = ADINT2 interrupt flag is not overwritten to 1.
* | | |1 = ADINT2 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun
* | | |0 = ADINT3 interrupt flag is not overwritten to 1.
* | | |1 = ADINT3 interrupt flag is overwritten to 1.
* | | |Note: This bit is cleared by writing 1 to it.
* |[12] |ADCMPO0 |ADC Compare 0 Output Status
* | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.
* |[13] |ADCMPO1 |ADC Compare 1 Output Status
* | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.
* |[14] |ADCMPO2 |ADC Compare 2 Output Status
* | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.
* |[15] |ADCMPO3 |ADC Compare 3 Output Status
* | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module
* | | |User can use it to monitor the external analog input pin voltage status.
* | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
* | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.
* |[20:16] |CHANNEL |Current Conversion Channel
* | | |This filed reflects ADC current conversion channel when BUSY=1.
* | | |It is read only.
* | | |00H = EADC_CH0.
* | | |01H = EADC_CH1.
* | | |02H = EADC_CH2.
* | | |03H = EADC_CH3.
* | | |04H = EADC_CH4.
* | | |05H = EADC_CH5.
* | | |06H = EADC_CH6.
* | | |07H = EADC_CH7.
* | | |08H = EADC_CH8.
* | | |09H = EADC_CH9.
* | | |0AH = EADC_CH10.
* | | |0BH = EADC_CH11.
* | | |0CH = EADC_CH12.
* | | |0DH = EADC_CH13.
* | | |0EH = EADC_CH14.
* | | |0FH = EADC_CH15.
* | | |10H = VBG.
* | | |11H = VTEMP.
* | | |12H = VBAT/4.
* | | |Note: These bit are read only.
* |[23] |BUSY |A/D Conveter Busy/Idle Status
* | | |0 = EADC is in idle state.
* | | |1 = EADC is busy for sample or conversion.
* | | |Note: This bit is read only
* | | |Once trigger source is coming, it must wait 2 ADC_CLK synchronization then the BUSY status will be high
* | | |This status will be high to low when the current conversion done.
* |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
* | | |n=0~3.
* | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
* | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
* | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
* |[25] |STOVF |for All A/D Sample Module Start of Conversion Overrun Flags Check
* | | |n=0~18.
* | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
* | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
* | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
* |[26] |AVALID |for All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
* | | |n=0~18.
* | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
* | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
* | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
* |[27] |AOV |for All Sample Module A/D Result Data Register Overrun Flags Check
* | | |n=0~18.
* | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
* | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
* | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
* @var EADC_T::STATUS3
* Offset: 0xFC A/D Status Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |CURSPL |ADC Current Sample Module
* | | |This register show the current ADC is controlled by which sample module control logic modules.
* | | |If the ADC is Idle, this bit filed will set to 0x1F.
* | | |Note: This is a read only register.
* @var EADC_T::PWRCTL
* Offset: 0x110 ADC Power Management Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |READY |ADC Start-up Completely and Ready for Conversion (Read Only)
* | | |0 = Power-on sequence is still in progress.
* | | |1 = ADC is ready for conversion.
* |[5] |AUTOFF |Auto Off Mode
* | | |0 = Function of auto off disabled.
* | | |1 = Function of auto off enabled
* | | |When AUTOFF is set to 1, ADC will be power off automatically to save power
* |[19:8] |STUPT |ADC Start-up Time
* | | |Set this bit fields to adjust start-up time. The minimum start-up time of ADC is 10us.
* | | |ADC start-up time = (1/ADC_CLK) x STUPT.
* |[23:20] |AUTOPDTHT |Auto Power Down Threshold Time
* | | |Auto Power Down Threshold Time = (1/ADC_CLK) x AUTOPDTHT.
* | | |0111 = 8 ADC clock for power down threshold time.
* | | |1000 = 16 ADC clock for power down threshold time.
* | | |1001 = 32 ADC clock for power down threshold time.
* | | |1010 = 64 ADC clock for power down threshold time.
* | | |1011 = 128 ADC clock for power down threshold time.
* | | |1100 = 256 ADC clock for power down threshold time.
* | | |Others = 256 ADC clock for power down threshold time.
* @var EADC_T::PDMACTL
* Offset: 0x130 ADC PDMA Control Rgister
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[18:0] |PDMATEN |PDMA Transfer Enable Bit
* | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
* | | |0 = PDMA data transfer Disabled.
* | | |1 = PDMA data transfer Enabled.
* | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
* @var EADC_T::MCTL1[16]
* Offset: 0x140~0x17C A/D Sample Module 0~15 Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ALIGN |Alignment Selection
* | | |0 = The conversion result will be right aligned in data register.
* | | |1 = The conversion result will be left aligned in data register.
* |[1] |AVG |Average Mode Selection
* | | |0 = Conversion results will be stored in data register without averaging.
* | | |1 = Conversion results in data register will be averaged.
* | | |This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~15).
* |[7:4] |ACU |Number of Accumulated Conversion Results Selection
* | | |0H = 1 conversion result will be accumulated.
* | | |1H = 2 conversion result will be accumulated.
* | | |2H = 4 conversion result will be accumulated.
* | | |3H = 8 conversion result will be accumulated.
* | | |4H = 16 conversion result will be accumulated.
* | | |5H = 32 conversion result will be accumulated.
* | | |6H = 64 conversion result will be accumulated.
* | | |7H = 128 conversion result will be accumulated.
* | | |8H = 256 conversion result will be accumulated.
* @var EADC_T::OFFSETCAL
* Offset: 0x208 A/D Result Offset Cancellation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |OFFSETCANCEL|A/D Offset Cancellation Trim Bits
* | | |When CALEN(EADC_CTL[8]) is set to 1, the offset cancellation trim bits will compensate A/D result offset
* | | |When this bit is set to 0, the offset cancellation trim bits have no effect to A/D result.
* | | |Note:These 5 bits trim value wouln't latched into EADC_OFFSETCAL automatically when flash initalization
* | | |User must read DCR2 by ISP command first, then write the value to OFFSETCANCEL.
* | | |Note: OFFSETCANCEL is signed format
* | | |OFFSETCANCEL will sign extension to 12 bit by hardware to perform signed addition with ADC conversion result if CALEN is enabled.
*/
__I uint32_t DAT[19]; /*!< [0x0000~0x0048] A/D Data Register n for Sample Module n, n=0~18 */
__I uint32_t CURDAT; /*!< [0x004c] EADC PDMA Current Transfer Data Register */
__IO uint32_t CTL; /*!< [0x0050] A/D Control Register */
__O uint32_t SWTRG; /*!< [0x0054] A/D Sample Module Software Start Register */
__IO uint32_t PENDSTS; /*!< [0x0058] A/D Start of Conversion Pending Flag Register */
__IO uint32_t OVSTS; /*!< [0x005c] A/D Sample Module Start of Conversion Overrun Flag Register */
__I uint32_t RESERVE0[8];
__IO uint32_t SCTL[16]; /*!< [0x0080~0x00bc] A/D Sample Module n Control Register n=0~15 */
__IO uint32_t SCTL0[3]; /*!< [0x00c0~0x00c8] A/D Sample Module n Control Register n=16~18 */
__I uint32_t RESERVE1[1];
__IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC Interrupt n Source Enable Control Register. n=0~3 */
__IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] A/D Result Compare Register n, n=0~3 */
__I uint32_t STATUS0; /*!< [0x00f0] A/D Status Register 0 */
__I uint32_t STATUS1; /*!< [0x00f4] A/D Status Register 1 */
__IO uint32_t STATUS2; /*!< [0x00f8] A/D Status Register 2 */
__I uint32_t STATUS3; /*!< [0x00fc] A/D Status Register 3 */
__I uint32_t RESERVE2[4];
__IO uint32_t PWRCTL; /*!< [0x0110] ADC Power Management Control Register */
__I uint32_t RESERVE3[7];
__IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Rgister */
__I uint32_t RESERVE4[3];
__IO uint32_t MCTL1[16]; /*!< [0x0140~0x017c] A/D Sample Module n Control Register 1, n=0~15 */
__I uint32_t RESERVE5[34];
__IO uint32_t OFFSETCAL; /*!< [0x0208] A/D Result Offset Cancellation Register */
} EADC_T;
/**
@addtogroup EADC_CONST EADC Bit Field Definition
Constant Definitions for EADC Controller
@{ */
#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DATn: RESULT Position */
#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DATn: RESULT Mask */
#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DATn: OV Position */
#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DATn: OV Mask */
#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DATn: VALID Position */
#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DATn: VALID Mask */
#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */
#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */
#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
#define EADC_CTL_CALEN_Pos (8) /*!< EADC_T::CTL: CALEN Position */
#define EADC_CTL_CALEN_Msk (0x1ul << EADC_CTL_CALEN_Pos) /*!< EADC_T::CTL: CALEN Mask */
#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTLn: CHSEL Position */
#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTLn: CHSEL Mask */
#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTLn: EXTREN Position */
#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTLn: EXTREN Mask */
#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTLn: EXTFEN Position */
#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTLn: EXTFEN Mask */
#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTLn: TRGDLYDIV Position */
#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTLn: TRGDLYDIV Mask */
#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTLn: TRGDLYCNT Position */
#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTLn: TRGDLYCNT Mask */
#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTLn: TRGSEL Position */
#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTLn: TRGSEL Mask */
#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTLn: INTPOS Position */
#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTLn: INTPOS Mask */
#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTLn: EXTSMPT Position */
#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTLn: EXTSMPT Mask */
#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0n: EXTSMPT Position */
#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0n: EXTSMPT Mask */
#define EADC_INTSRC_SPLIE0_Pos (0) /*!< EADC_T::INTSRCn: SPLIE0 Position */
#define EADC_INTSRC_SPLIE0_Msk (0x1ul << EADC_INTSRC_SPLIE0_Pos) /*!< EADC_T::INTSRCn: SPLIE0 Mask */
#define EADC_INTSRC_SPLIE1_Pos (1) /*!< EADC_T::INTSRCn: SPLIE1 Position */
#define EADC_INTSRC_SPLIE1_Msk (0x1ul << EADC_INTSRC_SPLIE1_Pos) /*!< EADC_T::INTSRCn: SPLIE1 Mask */
#define EADC_INTSRC_SPLIE2_Pos (2) /*!< EADC_T::INTSRCn: SPLIE2 Position */
#define EADC_INTSRC_SPLIE2_Msk (0x1ul << EADC_INTSRC_SPLIE2_Pos) /*!< EADC_T::INTSRCn: SPLIE2 Mask */
#define EADC_INTSRC_SPLIE3_Pos (3) /*!< EADC_T::INTSRCn: SPLIE3 Position */
#define EADC_INTSRC_SPLIE3_Msk (0x1ul << EADC_INTSRC_SPLIE3_Pos) /*!< EADC_T::INTSRCn: SPLIE3 Mask */
#define EADC_INTSRC_SPLIE4_Pos (4) /*!< EADC_T::INTSRCn: SPLIE4 Position */
#define EADC_INTSRC_SPLIE4_Msk (0x1ul << EADC_INTSRC_SPLIE4_Pos) /*!< EADC_T::INTSRCn: SPLIE4 Mask */
#define EADC_INTSRC_SPLIE5_Pos (5) /*!< EADC_T::INTSRCn: SPLIE5 Position */
#define EADC_INTSRC_SPLIE5_Msk (0x1ul << EADC_INTSRC_SPLIE5_Pos) /*!< EADC_T::INTSRCn: SPLIE5 Mask */
#define EADC_INTSRC_SPLIE6_Pos (6) /*!< EADC_T::INTSRCn: SPLIE6 Position */
#define EADC_INTSRC_SPLIE6_Msk (0x1ul << EADC_INTSRC_SPLIE6_Pos) /*!< EADC_T::INTSRCn: SPLIE6 Mask */
#define EADC_INTSRC_SPLIE7_Pos (7) /*!< EADC_T::INTSRCn: SPLIE7 Position */
#define EADC_INTSRC_SPLIE7_Msk (0x1ul << EADC_INTSRC_SPLIE7_Pos) /*!< EADC_T::INTSRCn: SPLIE7 Mask */
#define EADC_INTSRC_SPLIE8_Pos (8) /*!< EADC_T::INTSRCn: SPLIE8 Position */
#define EADC_INTSRC_SPLIE8_Msk (0x1ul << EADC_INTSRC_SPLIE8_Pos) /*!< EADC_T::INTSRCn: SPLIE8 Mask */
#define EADC_INTSRC_SPLIE9_Pos (9) /*!< EADC_T::INTSRCn: SPLIE9 Position */
#define EADC_INTSRC_SPLIE9_Msk (0x1ul << EADC_INTSRC_SPLIE9_Pos) /*!< EADC_T::INTSRCn: SPLIE9 Mask */
#define EADC_INTSRC_SPLIE10_Pos (10) /*!< EADC_T::INTSRCn: SPLIE10 Position */
#define EADC_INTSRC_SPLIE10_Msk (0x1ul << EADC_INTSRC_SPLIE10_Pos) /*!< EADC_T::INTSRCn: SPLIE10 Mask */
#define EADC_INTSRC_SPLIE11_Pos (11) /*!< EADC_T::INTSRCn: SPLIE11 Position */
#define EADC_INTSRC_SPLIE11_Msk (0x1ul << EADC_INTSRC_SPLIE11_Pos) /*!< EADC_T::INTSRCn: SPLIE11 Mask */
#define EADC_INTSRC_SPLIE12_Pos (12) /*!< EADC_T::INTSRCn: SPLIE12 Position */
#define EADC_INTSRC_SPLIE12_Msk (0x1ul << EADC_INTSRC_SPLIE12_Pos) /*!< EADC_T::INTSRCn: SPLIE12 Mask */
#define EADC_INTSRC_SPLIE13_Pos (13) /*!< EADC_T::INTSRCn: SPLIE13 Position */
#define EADC_INTSRC_SPLIE13_Msk (0x1ul << EADC_INTSRC_SPLIE13_Pos) /*!< EADC_T::INTSRCn: SPLIE13 Mask */
#define EADC_INTSRC_SPLIE14_Pos (14) /*!< EADC_T::INTSRCn: SPLIE14 Position */
#define EADC_INTSRC_SPLIE14_Msk (0x1ul << EADC_INTSRC_SPLIE14_Pos) /*!< EADC_T::INTSRCn: SPLIE14 Mask */
#define EADC_INTSRC_SPLIE15_Pos (15) /*!< EADC_T::INTSRCn: SPLIE15 Position */
#define EADC_INTSRC_SPLIE15_Msk (0x1ul << EADC_INTSRC_SPLIE15_Pos) /*!< EADC_T::INTSRCn: SPLIE15 Mask */
#define EADC_INTSRC_SPLIE16_Pos (16) /*!< EADC_T::INTSRCn: SPLIE16 Position */
#define EADC_INTSRC_SPLIE16_Msk (0x1ul << EADC_INTSRC_SPLIE16_Pos) /*!< EADC_T::INTSRCn: SPLIE16 Mask */
#define EADC_INTSRC_SPLIE17_Pos (17) /*!< EADC_T::INTSRCn: SPLIE17 Position */
#define EADC_INTSRC_SPLIE17_Msk (0x1ul << EADC_INTSRC_SPLIE17_Pos) /*!< EADC_T::INTSRCn: SPLIE17 Mask */
#define EADC_INTSRC_SPLIE18_Pos (18) /*!< EADC_T::INTSRCn: SPLIE18 Position */
#define EADC_INTSRC_SPLIE18_Msk (0x1ul << EADC_INTSRC_SPLIE18_Pos) /*!< EADC_T::INTSRCn: SPLIE18 Mask */
#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMPn: ADCMPEN Position */
#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMPn: ADCMPEN Mask */
#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMPn: ADCMPIE Position */
#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMPn: ADCMPIE Mask */
#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMPn: CMPCOND Position */
#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMPn: CMPCOND Mask */
#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMPn: CMPSPL Position */
#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMPn: CMPSPL Mask */
#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMPn: CMPMCNT Position */
#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMPn: CMPMCNT Mask */
#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMPn: CMPWEN Position */
#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMPn: CMPWEN Mask */
#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMPn: CMPDAT Position */
#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMPn: CMPDAT Mask */
#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
#define EADC_MCTL1_ALIGN_Pos (0) /*!< EADC_T::MnCTL1: ALIGN Position */
#define EADC_MCTL1_ALIGN_Msk (0x1ul << EADC_MCTL1_ALIGN_Pos) /*!< EADC_T::MnCTL1: ALIGN Mask */
#define EADC_MCTL1_AVG_Pos (1) /*!< EADC_T::MnCTL1: AVG Position */
#define EADC_MCTL1_AVG_Msk (0x1ul << EADC_MCTL1_AVG_Pos) /*!< EADC_T::MnCTL1: AVG Mask */
#define EADC_MCTL1_ACU_Pos (4) /*!< EADC_T::MnCTL1: ACU Position */
#define EADC_MCTL1_ACU_Msk (0xful << EADC_MCTL1_ACU_Pos) /*!< EADC_T::MnCTL1: ACU Mask */
#define EADC_PWRCTL_READY_Pos (0) /*!< EADC_T::PWRCTL: READY Position */
#define EADC_PWRCTL_READY_Msk (0x1ul << EADC_PWRCTL_READY_Pos) /*!< EADC_T::PWRCTL: READY Mask */
#define EADC_PWRCTL_AUTOFF_Pos (5) /*!< EADC_T::PWRCTL: AUTOFF Position */
#define EADC_PWRCTL_AUTOFF_Msk (0x1ul << EADC_PWRCTL_AUTOFF_Pos) /*!< EADC_T::PWRCTL: AUTOFF Mask */
#define EADC_PWRCTL_STUPT_Pos (8) /*!< EADC_T::PWRCTL: STUPT Position */
#define EADC_PWRCTL_STUPT_Msk (0xffful << EADC_PWRCTL_STUPT_Pos) /*!< EADC_T::PWRCTL: STUPT Mask */
#define EADC_PWRCTL_AUTOPDTHT_Pos (20) /*!< EADC_T::PWRCTL: AUTOPDTHT Position */
#define EADC_PWRCTL_AUTOPDTHT_Msk (0xful << EADC_PWRCTL_AUTOPDTHT_Pos) /*!< EADC_T::PWRCTL: AUTOPDTHT Mask */
#define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */
#define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */
#define EADC_OFFSETCAL_OFFSETCANCEL_Pos (0) /*!< EADC_T::OFFSETCAL: OFFSETCANCEL Position*/
#define EADC_OFFSETCAL_OFFSETCANCEL_Msk (0x1ful << EADC_OFFSETCAL_OFFSETCANCEL_Pos) /*!< EADC_T::OFFSETCAL: OFFSETCANCEL Mask */
/**@}*/ /* EADC_CONST */
/**@}*/ /* end of EADC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EADC_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/ebi_reg.h Normal file
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/**************************************************************************//**
* @file ebi_reg.h
* @version V1.00
* @brief EBI register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_REG_H__
#define __EBI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup EBI External Bus Interface Controller (EBI)
Memory Mapped Structure for EBI Controller
@{ */
typedef struct
{
/**
* @var EBI_T::CTL0
* Offset: 0x00 External Bus Interface Bank0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL0
* Offset: 0x04 External Bus Interface Bank0 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC defines data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD defines data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
* @var EBI_T::CTL1
* Offset: 0x10 External Bus Interface Bank1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL1
* Offset: 0x14 External Bus Interface Bank1 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC defines data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD defines data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
* @var EBI_T::CTL2
* Offset: 0x20 External Bus Interface Bank2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL2
* Offset: 0x24 External Bus Interface Bank2 Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC defines data access time (tACC).
* | | |tACC = (TACC +1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD defines data access hold time (tAHD).
* | | |tAHD = (TAHD +1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled.
* | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{ */
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EBI_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/fmc_reg.h Normal file
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/**************************************************************************//**
* @file fmc_reg.h
* @version V1.00
* @brief FMC register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __FMC_REG_H__
#define __FMC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup FMC Flash Memory Controller (FMC)
Memory Mapped Structure for FMC Controller
@{ */
typedef struct
{
/**
* @var FMC_T::ISPCTL
* Offset: 0x00 ISP Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPEN |ISP Enable Bit (Write Protect)
* | | |ISP function enable bit. Set this bit to enable ISP function.
* | | |0 = ISP function Disabled.
* | | |1 = ISP function Enabled.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[1] |BS |Boot Select (Write Protect)
* | | |Set/clear this bit to select next booting from LDROM/APROM, respectively
* | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
* | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
* | | |0 = Booting from APROM.
* | | |1 = Booting from LDROM.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[3] |APUEN |APROM Update Enable Bit (Write Protect)
* | | |0 = APROM cannot be updated when the chip runs in APROM.
* | | |1 = APROM can be updated when the chip runs in APROM.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
* | | |0 = CONFIG cannot be updated.
* | | |1 = CONFIG can be updated.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
* | | |LDROM update enable bit.
* | | |0 = LDROM cannot be updated.
* | | |1 = LDROM can be updated.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |This bit needs to be cleared by writing 1 to it.
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* | | |(8) ISP CMD in XOM region, except mass erase, page erase and chksum command
* | | |(9) The wrong setting of page erase ISP CMD in XOM
* | | |(10) Violate XOM setting one time protection
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::ISPADDR
* Offset: 0x04 ISP Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPADDR |ISP Address
* | | |For Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
* @var FMC_T::ISPDAT
* Offset: 0x08 ISP Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT |ISP Data
* | | |Write data to this register before ISP program operation.
* | | |Read data from this register after ISP read operation.
* | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment
* | | |For ISP Read Checksum command, ISPDAT is the checksum result
* | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect.
* @var FMC_T::ISPCMD
* Offset: 0x0C ISP CMD Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |CMD |ISP CMD
* | | |ISP command table is shown below:
* | | |0x00= FLASH Read.
* | | |0x04= Read Unique ID.
* | | |0x0B= Read Company ID.
* | | |0x0C= Read Device ID.
* | | |0x0D= Read Checksum.
* | | |0x21= FLASH 32-bit Program.
* | | |0x22= FLASH Page Erase.
* | | |0x27= FLASH Multi-Word Program.
* | | |0x28= Run Flash All-One Verification.
* | | |0x2D= Run Checksum Calculation.
* | | |0x2E= Vector Remap.
* | | |The other commands are invalid.
* @var FMC_T::ISPTRG
* Offset: 0x10 ISP Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPGO |ISP Start Trigger (Write Protect)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::FTCTL
* Offset: 0x18 Flash Access Time Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9] |CACHEINV |Flash Cache Invalidation (Write Protect)
* | | |Write 1 to start cache invalidation. The value will be change to 0 once the process finishes.
* | | |0 = Flash Cache Invalidation.(default)
* | | |1 = Flash Cache Invalidation.
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::ISPSTS
* Offset: 0x40 ISP Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ISPBUSY |ISP Busy Flag (Read Only)
* | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP operation is finished.
* | | |1 = ISP is progressed.
* |[2:1] |CBS |Boot Selection of CONFIG (Read Only)
* | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
* | | |00 = LDROM with IAP mode.
* | | |01 = LDROM without IAP mode.
* | | |10 = APROM with IAP mode.
* | | |11 = APROM without IAP mode.
* |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
* | | |This bit is set if data is mismatched at ISP programming verification
* | | |This bit is clear by performing ISP Flash erase or ISP read CID operation
* | | |0 = Flash Program is success.
* | | |1 = Flash Program is fail. Program data is different with data in the Flash memory
* |[6] |ISPFF |ISP Fail Flag (Write Protect)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* | | |(8) ISP CMD in XOM region, except mass erase, page erase and chksum command
* | | |(9) The wrong setting of page erase ISP CMD in XOM
* | | |(10) Violate XOM setting one time protection
* | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
* |[7] |ALLONE |Flash All-one Verification Flag
* | | |This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1
* | | |0 = Flash bits are not all 1 after "Run Flash All-One Verification" complete.
* | | |1 = All of Flash bits are 1 after "Run Flash All-One Verification" complete.
* |[29:9] |VECMAP |Vector Page Mapping Address (Read Only)
* | | |All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}.
* | | |VECMAP [20:19] = 00 system vector address is mapped to Flash memory.
* | | |VECMAP [20:19] = 10 system vector address is mapped to SRAM memory.
* | | |VECMAP [18:12] should be 0.
* @var FMC_T::CYCCTL
* Offset: 0x4C Flash Access Cycle Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
* | | |This register is updated automaticly by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1)
* | | |0001 = CPU access with zero wait cycle ; Flash access cycle is 1;.
* | | |The HCLK working frequency range is <19MHz; Cache is disabled by hardware.
* | | |0010 = CPU access with one wait cycles if cache miss; Flash access cycle is 2;.
* | | | The optimized HCLK working frequency range is 18~33 MHz
* | | |0011 = CPU access with two wait cycles if cahce miss; Flash access cycle is 3;.
* | | | The optimized HCLK working frequency range is 33~50 MHz
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var FMC_T::MPDAT0
* Offset: 0x80 ISP Data0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT0 |ISP Data 0
* | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
* @var FMC_T::MPDAT1
* Offset: 0x84 ISP Data1 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT1 |ISP Data 1
* | | |This register is the second 32-bit data for 64-bit/multi-word programming.
* @var FMC_T::MPDAT2
* Offset: 0x88 ISP Data2 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT2 |ISP Data 2
* | | |This register is the third 32-bit data for multi-word programming.
* @var FMC_T::MPDAT3
* Offset: 0x8C ISP Data3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |ISPDAT3 |ISP Data 3
* | | |This register is the fourth 32-bit data for multi-word programming.
* @var FMC_T::MPSTS
* Offset: 0xC0 ISP Multi-program Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
* | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
* | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
* | | |0 = ISP Multi-Word program operation is finished.
* | | |1 = ISP Multi-Word program operation is progressed.
* |[1] |PPGO |ISP Multi-program Status (Read Only)
* | | |0 = ISP multi-word program operation is not active.
* | | |1 = ISP multi-word program operation is in progress.
* |[2] |ISPFF |ISP Fail Flag (Read Only)
* | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
* | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
* | | |(1) APROM writes to itself if APUEN is set to 0.
* | | |(2) LDROM writes to itself if LDUEN is set to 0.
* | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
* | | |(4) Page Erase command at LOCK mode with ICE connection
* | | |(5) Erase or Program command at brown-out detected
* | | |(6) Destination address is illegal, such as over an available range.
* | | |(7) Invalid ISP commands
* |[4] |D0 |ISP DATA 0 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
* | | |0 = FMC_MPDAT0 register is empty, or program to Flash complete.
* | | |1 = FMC_MPDAT0 register has been written, and not program to Flash complete.
* |[5] |D1 |ISP DATA 1 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
* | | |0 = FMC_MPDAT1 register is empty, or program to Flash complete.
* | | |1 = FMC_MPDAT1 register has been written, and not program to Flash complete.
* |[6] |D2 |ISP DATA 2 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
* | | |0 = FMC_MPDAT2 register is empty, or program to Flash complete.
* | | |1 = FMC_MPDAT2 register has been written, and not program to Flash complete.
* |[7] |D3 |ISP DATA 3 Flag (Read Only)
* | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
* | | |0 = FMC_MPDAT3 register is empty, or program to Flash complete.
* | | |1 = FMC_MPDAT3 register has been written, and not program to Flash complete.
* @var FMC_T::MPADDR
* Offset: 0xC4 ISP Multi-program Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |MPADDR |ISP Multi-word Program Address
* | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
* | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
* @var FMC_T::XOMR0STS0
* Offset: 0xD0 XOM Region 0 Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |BASE |XOM Region 0 Base Address (Page-aligned)
* | | |BASE is the base address of XOM Region 0.
* @var FMC_T::XOMR0STS1
* Offset: 0xD4 XOM Region 0 Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |SIZE |XOM Region 0 Size (Page-aligned)
* | | |SIZE is the page number of XOM Region 0.
* @var FMC_T::XOMSTS
* Offset: 0xE0 XOM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |XOMR0ON |XOM Region 0 On
* | | |XOM Region 0 active status.
* | | |0 = No active.
* | | |1 = XOM region 0 is active.
* |[4] |XOMPEF |XOM Page Erase Function Fail
* | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
* | | |0 = Sucess.
* | | |1 = Fail.
*/
__IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
__IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
__IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
__IO uint32_t ISPCMD; /*!< [0x000c] ISP CMD Register */
__IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
__I uint32_t RESERVE0;
__IO uint32_t FTCTL; /*!< [0x0018] Flash Access Time Control Register */
__I uint32_t RESERVE1[9];
__IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
__I uint32_t RESERVE2[2];
__IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
__I uint32_t RESERVE3[12];
__IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
__IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
__IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
__IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
__I uint32_t RESERVE4[12];
__I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-program Status Register */
__I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-program Address Register */
__I uint32_t RESERVE5[2];
__I uint32_t XOMR0STS0; /*!< [0x00d0] XOM Region 0 Status Register 0 */
__I uint32_t XOMR0STS1; /*!< [0x00d4] XOM Region 0 Status Register 1 */
__I uint32_t RESERVE6[2];
__I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
} FMC_T;
/**
@addtogroup FMC_CONST FMC Bit Field Definition
Constant Definitions for FMC Controller
@{ */
#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
#define FMC_FTCTL_CACHEINV_Pos (9) /*!< FMC_T::FTCTL: CACHEINV Position */
#define FMC_FTCTL_CACHEINV_Msk (0x1ul << FMC_FTCTL_CACHEINV_Pos) /*!< FMC_T::FTCTL: CACHEINV Mask */
#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
#define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
#define FMC_XOMR0STS0_BASE_Pos (0) /*!< FMC_T::XOMR0STS0: BASE Position */
#define FMC_XOMR0STS0_BASE_Msk (0xfffffful << FMC_XOMR0STS0_BASE_Pos) /*!< FMC_T::XOMR0STS0: BASE Mask */
#define FMC_XOMR0STS1_SIZE_Pos (0) /*!< FMC_T::XOMR0STS1: SIZE Position */
#define FMC_XOMR0STS1_SIZE_Msk (0x1fful << FMC_XOMR0STS1_SIZE_Pos) /*!< FMC_T::XOMR0STS1: SIZE Mask */
#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
/**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __FMC_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/gpio_reg.h Normal file
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/**************************************************************************//**
* @file gpio_reg.h
* @version V1.00
* @brief GPIO register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __GPIO_REG_H__
#define __GPIO_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup GPIO General Purpose Input/Output Controller (GPIO)
Memory Mapped Structure for GPIO Controller
@{ */
typedef struct
{
/**
* @var GPIO_T::MODE
* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
* | | |Determine each I/O mode of Px.n pins.
* | | |00 = Px.n is in Input mode.
* | | |01 = Px.n is in Push-pull Output mode.
* | | |10 = Px.n is in Open-drain Output mode.
* | | |11 = Px.n is in Quasi-bidirectional mode.
* | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10])
* | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on
* | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
* | | |Note2: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::DINOFF
* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Bit
* | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled
* | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
* | | |0 = Px.n digital input path Enabled.
* | | |1 = Px.n digital input path Disabled (digital input tied to low).
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::DOUT
* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DOUTn |Port A-F Pin[n] Output Value
* | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
* | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::DATMSK
* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DATMSKn |Port A-F Pin[n] Data Output Write Mask
* | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit
* | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected
* | | |If the write signal is masked, writing data to the protect bit is ignored.
* | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
* | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
* | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
* | | |Note2: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::PIN
* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-H Pin Value
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |PINn |Port A-F Pin[n] Pin Value
* | | |Each bit of the register reflects the actual status of the respective Px.n pin
* | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::DBEN
* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |DBENn |Port A-F Pin[n] Input Signal De-bounce Enable Bit
* | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt
* | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
* | | |0 = Px.n de-bounce function Disabled.
* | | |1 = Px.n de-bounce function Enabled.
* | | |The de-bounce function is valid only for edge triggered interrupt
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::INTTYPE
* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |TYPEn |Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control
* | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger
* | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
* | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt.
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n])
* | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid only for edge triggered interrupt
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::INTEN
* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
* | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
* | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
* | | |0 = Px.n level low or high to low interrupt Disabled.
* | | |1 = Px.n level low or high to low interrupt Enabled.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* |[n+16] |RHIENn |Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
* | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin
* | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
* | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
* | | |0 = Px.n level high or low to high interrupt Disabled.
* | | |1 = Px.n level high or low to high interrupt Enabled.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::INTSRC
* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
* | | |Write Operation :
* | | |0 = No action.
* | | |1 = Clear the corresponding pending interrupt.
* | | |Read Operation :
* | | |0 = No interrupt at Px.n.
* | | |1 = Px.n generates an interrupt.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::SMTEN
* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
* | | |0 = Px.n input schmitt trigger function Disabled.
* | | |1 = Px.n input schmitt trigger function Enabled.
* | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
* @var GPIO_T::SLEWCTL
* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|HSRENn |Port A-F Pin[n] High Slew Rate Control
* | | |00 = Px.n output with normal slew rate mode.
* | | |01 = Px.n output with high slew rate mode.
* | | |10 = Reserved.
* | | |11 = Reserved.
* | | |Note1: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |Note2: Please refer to the M251 Datasheet for detailed pin operation voltage
* | | | information about VDD, VDDIO and VBAT electrical characteristics.
* @var GPIO_T::PUSEL
* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170 Port A-F Pull-up and Pull-down Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2n+1:2n]|PUSELn |Port A-F Pin[n] Pull-up and Pull-down Enable Register
* | | |Determine each I/O Pull-up/pull-down of Px.n pins.
* | | |00 = Px.n pull-up and pull-down disable.
* | | |01 = Px.n pull-up enable.
* | | |10 = Px.n pull-down enable.
* | | |11 = Px.n pull-up and pull-down disable.
* | | |Note1:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation
* | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode
* | | |The independent pull-down control register only valid when MODEn set as tri-state mode
* | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode
* | | |Note2: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored.
* | | |
*/
__IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xc0/0x100/0x140] PA~PF I/O Mode Control */
__IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xc4/0x104/0x144] PA~PF Digital Input Path Disable Control */
__IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xc8/0x108/0x148] PA~PF Data Output Value */
__IO uint32_t DATMSK; /*!< [0x0c/0x4c/0x8c/0xcc/0x10c/0x14c] PA~PF Data Output Write Mask */
__I uint32_t PIN; /*!< [0x10/0x50/0x90/0xd0/0x110/0x150] PA~PF Pin Value */
__IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xd4/0x114/0x154] PA~PF De-bounce Enable Control Register */
__IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xd8/0x118/0x158] PA~PF Interrupt Trigger Type Control */
__IO uint32_t INTEN; /*!< [0x1c/0x5c/0x9c/0xdc/0x11c/0x15c] PA~PF Interrupt Enable Control Register */
__IO uint32_t INTSRC; /*!< [0x20/0x60/0xa0/0xe0/0x120/0x160] PA~PF Interrupt Source Flag */
__IO uint32_t SMTEN; /*!< [0x24/0x64/0xa4/0xe4/0x124/0x164] PA~PF Input Schmitt Trigger Enable Register*/
__IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xa8/0xe8/0x128/0x168] PA~PF High Slew Rate Control Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170] PA~PF Pull-up and Pull-down Selection Register*/
} GPIO_T;
typedef struct
{
/**
* @var GPIO_DBCTL_T::DBCTL
* Offset: 0x440 Interrupt De-bounce Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection
* | | |0000 = Sample interrupt input once per 1 clocks.
* | | |0001 = Sample interrupt input once per 2 clocks.
* | | |0010 = Sample interrupt input once per 4 clocks.
* | | |0011 = Sample interrupt input once per 8 clocks.
* | | |0100 = Sample interrupt input once per 16 clocks.
* | | |0101 = Sample interrupt input once per 32 clocks.
* | | |0110 = Sample interrupt input once per 64 clocks.
* | | |0111 = Sample interrupt input once per 128 clocks.
* | | |1000 = Sample interrupt input once per 256 clocks.
* | | |1001 = Sample interrupt input once per 2*256 clocks.
* | | |1010 = Sample interrupt input once per 4*256 clocks.
* | | |1011 = Sample interrupt input once per 8*256 clocks.
* | | |1100 = Sample interrupt input once per 16*256 clocks.
* | | |1101 = Sample interrupt input once per 32*256 clocks.
* | | |1110 = Sample interrupt input once per 64*256 clocks.
* | | |1111 = Sample interrupt input once per 128*256 clocks.
* |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection
* | | |0 = De-bounce counter clock source is the HCLK.
* | | |1 = De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC).
* |[21:16] |ICLKONx |Interrupt Clock on Mode
* | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
* | | |1 = All I/O pins edge detection circuit is always active after reset.
* | | |Note: It is recommended to disable this bit to save system power if no special application concern.
*/
__IO uint32_t DBCTL; /*!< [0x0440] Interrupt De-bounce Control Register */
} GPIO_DBCTL_T;
/**
@addtogroup GPIO_CONST GPIO Bit Field Definition
Constant Definitions for GPIO Controller
@{ */
#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */
#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */
#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */
#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */
#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */
#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */
#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */
#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */
#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */
#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */
#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */
#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */
#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */
#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */
#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */
#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */
#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */
#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */
#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */
#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */
#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */
#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */
#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */
#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */
#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */
#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */
#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */
#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */
#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */
#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */
#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */
#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */
#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */
#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */
#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */
#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */
#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */
#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */
#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */
#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */
#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */
#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */
#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */
#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */
#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */
#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */
#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */
#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */
#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */
#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */
#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */
#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */
#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */
#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */
#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */
#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */
#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */
#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */
#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */
#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */
#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */
#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */
#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */
#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */
#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
#define GPIO_DBCTL_ICLKONA_Pos (16) /*!< GPIO_T::DBCTL: ICLKONA Position */
#define GPIO_DBCTL_ICLKONA_Msk (0x1ul << GPIO_DBCTL_ICLKONA_Pos) /*!< GPIO_T::DBCTL: ICLKONA Mask */
#define GPIO_DBCTL_ICLKONB_Pos (17) /*!< GPIO_T::DBCTL: ICLKONB Position */
#define GPIO_DBCTL_ICLKONB_Msk (0x1ul << GPIO_DBCTL_ICLKONB_Pos) /*!< GPIO_T::DBCTL: ICLKONB Mask */
#define GPIO_DBCTL_ICLKONC_Pos (18) /*!< GPIO_T::DBCTL: ICLKONC Position */
#define GPIO_DBCTL_ICLKONC_Msk (0x1ul << GPIO_DBCTL_ICLKONC_Pos) /*!< GPIO_T::DBCTL: ICLKONC Mask */
#define GPIO_DBCTL_ICLKOND_Pos (19) /*!< GPIO_T::DBCTL: ICLKOND Position */
#define GPIO_DBCTL_ICLKOND_Msk (0x1ul << GPIO_DBCTL_ICLKOND_Pos) /*!< GPIO_T::DBCTL: ICLKOND Mask */
#define GPIO_DBCTL_ICLKONE_Pos (20) /*!< GPIO_T::DBCTL: ICLKONE Position */
#define GPIO_DBCTL_ICLKONE_Msk (0x1ul << GPIO_DBCTL_ICLKONE_Pos) /*!< GPIO_T::DBCTL: ICLKONE Mask */
#define GPIO_DBCTL_ICLKONF_Pos (21) /*!< GPIO_T::DBCTL: ICLKONF Position */
#define GPIO_DBCTL_ICLKONF_Msk (0x1ul << GPIO_DBCTL_ICLKONF_Pos) /*!< GPIO_T::DBCTL: ICLKONF Mask */
/**@}*/ /* GPIO_CONST */
/**@}*/ /* end of GPIO register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __GPIO_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/i2c_reg.h Normal file
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/**************************************************************************//**
* @file i2c_reg.h
* @version V1.00
* @brief I2C register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/*---------------------- Inter-IC Bus Controller -------------------------*/
/**
@addtogroup I2C Inter-IC Bus Controller (I2C)
Memory Mapped Structure for I2C Controller
@{ */
typedef struct
{
/**
* @var I2C_T::CTL0
* Offset: 0x00 I2C Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
* |[3] |SI |I2C Interrupt Flag
* | | |When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware
* | | |If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested
* | | |SI must be cleared by software.
* | | |Clear SI by writing 1 to this bit.
* | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
* |[4] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
* | | |This bit will be cleared by hardware automatically.
* |[5] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[6] |I2CEN |I2C Controller Enable Bit
* | | |Set to enable I2C serial function controller
* | | |When I2CEN=1 the I2C serial function enable
* | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
* | | |0 = I2C controller Disabled.
* | | |1 = I2C controller Enabled.
* |[7] |INTEN |Enable Interrupt
* | | |0 = I2C interrupt Disabled.
* | | |1 = I2C interrupt Enabled.
* @var I2C_T::DAT
* Offset: 0x08 I2C Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |I2C Data
* | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
* @var I2C_T::STATUS0
* Offset: 0x0C I2C Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |STATUS |I2C Status
* | | |The three least significant bits are always 0
* | | |The five most significant bits contain the status code
* | | |There are 28 possible status codes
* | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested
* | | |Others I2C_STATUS0 values correspond to defined I2C states
* | | |When each of these states is entered, a status interrupt is requested (SI = 1)
* | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
* | | |In addition, states 00H stands for a Bus Error
* | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
* @var I2C_T::CLKDIV
* Offset: 0x10 I2C Clock Divided Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DIVIDER |I2C Clock Divided
* | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
* | | |Note: The minimum value of I2C_CLKDIV is 4.
* @var I2C_T::TOCTL
* Offset: 0x14 I2C Time-out Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIF |Time-out Flag
* | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
* | | |Note: Software can write 1 to clear this bit.
* |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4
* | | |When enabled, the time-out period is extended 4 times.
* | | |0 = Time-out period is extend 4 times Disabled.
* | | |1 = Time-out period is extend 4 times Enabled.
* |[2] |TOCEN |Time-out Counter Enable Bit
* | | |When enabled, the 14-bit time-out counter will start counting when SI is cleared
* | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
* | | |0 = Time-out counter Disabled.
* | | |1 = Time-out counter Enabled.
* @var I2C_T::ADDR0~3
* Offset: 0x04/0x18/0x1x/0x20 I2C Slave Address0~3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[10:1] |ADDR |I2C Address
* | | |The content of this register is irrelevant when I2C is in Master mode
* | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address
* | | |The I2C hardware will react if either of the address is matched.
* | | |Note: When software set 10'h000, the address can not be used.
* @var I2C_T::ADDRMSK0~3
* Offset: 0x24/0x28/0x2C/0x30 I2C Slave Address Mask0~3 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:1] |ADDRMSK |I2C Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |I2C bus controllers support multiple address recognition with four address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var I2C_T::WKCTL
* Offset: 0x3C I2C Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |I2C Wake-up Enable Bit
* | | |0 = I2C wake-up function Disabled.
* | | |1 = I2C wake-up function Enabled.
* |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit
* | | |0 = I2C hold bus after wake-up.
* | | |1 = I2C don't hold bus after wake-up.
* | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
* | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
* @var I2C_T::WKSTS
* Offset: 0x40 I2C Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKIF |I2C Wake-up Flag
* | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
* |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame (Read Only)
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* | | |Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit.
* @var I2C_T::CTL1
* Offset: 0x44 I2C Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[1] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the I2C request to PDMA.
* |[3] |OVRIEN |I2C over Run Interrupt Control Bit
* | | |Setting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer.
* |[4] |UDRIEN |I2C Under Run Interrupt Control Bit
* | | |Setting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer.
* |[5] |TWOBUFEN |Two-level BUFFER Enable Bit
* | | |0 = Two-level buffer Disabled.
* | | |1 = Two-level buffer Enabled.
* | | |Set to enable the two-level buffer for I2C transmitted or received buffer.
* | | |It is used to improve the performance of the I2C bus.
* | | |If this bit is set = 1, the control bit of STA for repeat start or STO bit should be set after the current SI is cleared.
* | | |For example: if there are 4 data shall be transmitted and then stop it.
* | | |The STO bit shall be set after the 3rd data's SI event being clear.
* | | |In this time, the 4th data can be transmitted and the I2C stop after the 4th data transmission done.
* |[6] |BUFRST |Two-level BUFFER Reset
* | | |0 = No effect.
* | | |1 = Reset the related counters, two-level buffer state machine, and the content of data buffer.
* |[7] |NSTRETCH |No Stretch on the I2C Bus
* | | |0 = The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode.
* | | |1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode.
* |[8] |PDMASTR |PDMA Stretch Bit
* | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
* | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
* | | |(only master TX)
* |[9] |ADDR10EN |Address 10-bit Function Enable Bit
* | | |0 = Address match 10-bit function Disabled.
* | | |1 = Address match 10-bit function Enabled.
* @var I2C_T::STATUS1
* Offset: 0x48 I2C Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |I2C Address 0 Match Status
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |I2C Address 1 Match Status
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[2] |ADMAT2 |I2C Address 2 Match Status
* | | |When address 2 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[3] |ADMAT3 |I2C Address 3 Match Status
* | | |When address 3 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[4] |FULL |TWO-lEVEL BUFFER FULL
* | | |This bit indicates two-level buffer TX or RX full or not when the TWOBUFEN = 1.
* | | |This bit is set when POINTER is equal to 2.
* | | |Note:This bit is read only.
* |[5] |EMPTY |TWO-lEVEL BUFFER EMPTY
* | | |This bit indicates two-level buffer TX or RX empty or not when the TWOBUFEN = 1.
* | | |This bit is set when POINTER is equal to 0.
* | | |Note:This bit is read only.
* |[6] |OVR |I2C over Run Status Bit
* | | |This bit indicates the received two-level buffer TX or RX is over run when the TWOBUFEN = 1.
* | | |Note:This bit is read only.
* |[7] |UDR |I2C Under Run Status Bit
* | | |This bit indicates the transmitted two-level buffer TX or RX is under run when the TWOBUFEN = 1.
* | | |Note:This bit is read only.
* |[8] |ONBUSY |On Bus Busy (Read Only)
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected.
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* @var I2C_T::TMCTL
* Offset: 0x4C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control
* | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
* | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
* | | |Note: Setup time setting should not make SCL output less than three PCLKs.
* |[24:16] |HTCTL |Hold Time Configure Control
* | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
* @var I2C_T::BUSCTL
* Offset: 0x50 I2C Bus Management Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ACKMEN |Acknowledge Control by Manual
* | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
* | | |0 = Slave byte control Disabled.
* | | |1 = Slave byte control Enabled
* | | |The 9th bit can response the ACK or NACK according the received data by user
* | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
* | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS0 will be fixed as 0xF0 in slave receive condition.
* |[1] |PECEN |Packet Error Checking Calculation Enable Bit
* | | |0 = Packet Error Checking Calculation Disabled.
* | | |1 = Packet Error Checking Calculation Enabled.
* | | |Note: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation.
* |[2] |BMDEN |Bus Management Device Default Address Enable Bit
* | | |0 = Device default address Disable
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
* | | |1 = Device default address Enabled
* | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
* |[3] |BMHEN |Bus Management Host Enable Bit
* | | |0 = Host function Disabled.
* | | |1 = Host function Enabled.
* |[4] |ALERTEN |Bus Management Alert Enable Bit
* | | |Device Mode (BMHEN =0).
* | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
* | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
* | | |Host Mode (BMHEN =1).
* | | |0 = BM_ALERT pin not supported.
* | | |1 = BM_ALERT pin supported.
* |[5] |SCTLOSTS |Suspend/Control Data Output Status
* | | |0 = The output of SUSCON pin is low.
* | | |1 = The output of SUSCON pin is high.
* |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit
* | | |0 = The SUSCON pin in input.
* | | |1 = The output enable is active on the SUSCON pin.
* |[7] |BUSEN |BUS Enable Bit
* | | |0 = The system management function Disabled.
* | | |1 = The system management function Enabled.
* | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
* |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
* | | |0 = No PEC transfer.
* | | |1 = PEC transmission is requested.
* | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
* |[9] |TIDLE |Timer Check in Idle State
* | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
* | | |This bit is used to define which condition is enabled.
* | | |0 = BUSTOUT is used to calculate the clock low period in bus active.
* | | |1 = BUSTOUT is used to calculate the IDLE period in bus Idle.
* | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
* |[10] |PECCLR |PEC Clear at Repeat Start
* | | |The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected
* | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
* | | |0 = PEC calculation is cleared by "Repeat Start" function Disabled.
* | | |1 = PEC calculation is cleared by "Repeat Start" function Enabled.
* |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
* | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
* | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
* |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
* | | |0 = Byte count done interrupt Disabled.
* | | |1 = Byte count done interrupt Enabled.
* | | |Note: This bit is used in PECEN =1.
* |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
* | | |0 = PEC transfer done interrupt Disabled.
* | | |1 = PEC transfer done interrupt Enabled.
* | | |Note: This bit is used in PECEN =1.
* @var I2C_T::BUSTCTL
* Offset: 0x54 I2C Bus Management Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSTOEN |Bus Time Out Enable Bit
* | | |0 = Bus clock low time-out detection Disabled.
* | | |1 = Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1)
* |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
* | | |0 = Cumulative clock low time-out detection Disabled.
* | | |1 = Cumulative clock low time-out detection Enabled.
* | | |For Master, it calculates the period from START to ACK
* | | |For Slave, it calculates the period from START to STOP
* |[2] |BUSTOIEN |Time-out Interrupt Enable Bit
* | | |BUSY =1.
* | | |0 = SCLK low time-out interrupt Disabled.
* | | |1 = SCLK low time-out interrupt Enabled.
* | | |BUSY =0.
* | | |0 = Bus IDLE time-out interrupt Disabled.
* | | |1 = Bus IDLE time-out interrupt Enabled.
* |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
* | | |0 = Clock time out interrupt Disabled.
* | | |1 = Clock time out interrupt Enabled.
* |[4] |TORSTEN |Time Out Reset Enable Bit
* | | |0 = I2C state machine reset Disabled.
* | | |1 = I2C state machine reset Enabled. (The clock and data bus will be released to high)
* @var I2C_T::BUSSTS
* Offset: 0x58 I2C Bus Management Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Bus Busy (Read Only)
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = Bus is IDLE (both SCLK and SDA High).
* | | |1 = Bus is busy.
* |[1] |BCDONE |Byte Count Transmission/Receive Done
* | | |0 = Byte count transmission/ receive is not finished when the PECEN is set.
* | | |1 = Byte count transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* |[2] |PECERR |PEC Error in Reception
* | | |0 = PEC value equal the received PEC data packet.
* | | |1 = PEC value doesn't match the receive PEC data packet.
* | | |Note: Software can write 1 to clear this bit.
* |[3] |ALERT |SMBus Alert Status
* | | |Device Mode (BMHEN =0).
* | | |0 = Indicates SMBALERT pin state is low.
* | | |1 = Indicates SMBALERT pin state is high.
* | | |Host Mode (BMHEN =1).
* | | |0 = No SMBALERT event.
* | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
* | | |Note:
* | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
* | | |2. Software can write 1 to clear this bit.
* |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status (Read Only)
* | | |0 = The input status of SUSCON pin is 0.
* | | |1 = The input status of SUSCON pin is 1.
* |[5] |BUSTO |Bus Time-out Status
* | | |0 = There is no any time-out or external clock time-out.
* | | |1 = A time-out or external clock time-out occurred.
* | | |In bus busy, the bit indicates the total clock low time-out event occurred; otherwise, it indicates the bus idle time-out event occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[6] |CLKTO |Clock Low Cumulate Time-out Status
* | | |0 = Cumulative clock low is no any time-out.
* | | |1 = Cumulative clock low time-out occurred.
* | | |Note: Software can write 1 to clear this bit.
* |[7] |PECDONE |PEC Byte Transmission/Receive Done
* | | |0 = PEC transmission/ receive is not finished when the PECEN is set.
* | | |1 = PEC transmission/ receive is finished when the PECEN is set.
* | | |Note: Software can write 1 to clear this bit.
* @var I2C_T::PKTSIZE
* Offset: 0x5C I2C Packet Error Checking Byte Number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |PLDSIZE |Transfer Byte Number
* | | |The transmission or receive byte number in one transaction when the PECEN is set
* | | |The maximum transaction or receive byte is 256 Bytes.
* | | |Note: The byte number counting includes address, command code, and data frame.
* @var I2C_T::PKTCRC
* Offset: 0x60 I2C Packet Error Checking Byte Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PECCRC |Packet Error Checking Byte Value
* | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
* | | |It is read only.
* @var I2C_T::BUSTOUT
* Offset: 0x64 I2C Bus Management Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |BUSTO |Bus Management Time-out Value
* | | |Indicates the bus time-out value in bus is IDLE or SCLK low.
* | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
* @var I2C_T::CLKTOUT
* Offset: 0x68 I2C Bus Management Clock Low Timer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLKTO |Bus Clock Low Timer
* | | |The field is used to configure the cumulative clock extension time-out.
* | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
*/
__IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */
__IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */
__IO uint32_t DAT; /*!< [0x0008] I2C Data Register */
__I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */
__IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */
__IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */
__IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */
__IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */
__IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */
__IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */
__IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */
__IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */
__IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */
__I uint32_t RESERVE0[2];
__IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */
__IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */
__IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */
__IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */
__IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */
__IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */
__IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */
__IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */
__I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */
__IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */
__IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */
} I2C_T;
/**
@addtogroup I2C_CONST I2C Bit Field Definition
Constant Definitions for I2C Controller
@{ */
#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */
#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */
#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */
#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */
#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */
#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */
#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */
#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */
#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */
#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */
#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */
#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */
#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */
#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */
#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */
#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */
#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */
#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */
#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */
#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */
#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */
#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */
#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */
#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */
#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */
#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */
#define I2C_CTL1_OVRIEN_Pos (3) /*!< I2C_T::CTL1: OVRIEN Position */
#define I2C_CTL1_OVRIEN_Msk (0x1ul << I2C_CTL1_OVRIEN_Pos) /*!< I2C_T::CTL1: OVRIEN Mask */
#define I2C_CTL1_UDRIEN_Pos (4) /*!< I2C_T::CTL1: UDRIEN Position */
#define I2C_CTL1_UDRIEN_Msk (0x1ul << I2C_CTL1_UDRIEN_Pos) /*!< I2C_T::CTL1: UDRIEN Mask */
#define I2C_CTL1_TWOBUFEN_Pos (5) /*!< I2C_T::CTL1: TWOBUFEN Position */
#define I2C_CTL1_TWOBUFEN_Msk (0x1ul << I2C_CTL1_TWOBUFEN_Pos) /*!< I2C_T::CTL1: TWOBUFEN Mask */
#define I2C_CTL1_BUFRST_Pos (6) /*!< I2C_T::CTL1: BUFRST Position */
#define I2C_CTL1_BUFRST_Msk (0x1ul << I2C_CTL1_BUFRST_Pos) /*!< I2C_T::CTL1: BUFRST Mask */
#define I2C_CTL1_NSTRETCH_Pos (7) /*!< I2C_T::CTL1: NSTRETCH Position */
#define I2C_CTL1_NSTRETCH_Msk (0x1ul << I2C_CTL1_NSTRETCH_Pos) /*!< I2C_T::CTL1: NSTRETCH Mask */
#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */
#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */
#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */
#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */
#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */
#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */
#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */
#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */
#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */
#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */
#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */
#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */
#define I2C_STATUS1_FULL_Pos (4) /*!< I2C_T::STATUS1: FULL Position */
#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos) /*!< I2C_T::STATUS1: FULL Mask */
#define I2C_STATUS1_EMPTY_Pos (5) /*!< I2C_T::STATUS1: EMPTY Position */
#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos) /*!< I2C_T::STATUS1: EMPTY Mask */
#define I2C_STATUS1_OVR_Pos (6) /*!< I2C_T::STATUS1: OVR Position */
#define I2C_STATUS1_OVR_Msk (0x1ul << I2C_STATUS1_OVR_Pos) /*!< I2C_T::STATUS1: OVR Mask */
#define I2C_STATUS1_UDR_Pos (7) /*!< I2C_T::STATUS1: UDR Position */
#define I2C_STATUS1_UDR_Msk (0x1ul << I2C_STATUS1_UDR_Pos) /*!< I2C_T::STATUS1: UDR Mask */
#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */
#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */
#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */
#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */
#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */
#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */
#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */
#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */
#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */
#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */
#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */
#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */
#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
/**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __I2C_REG_H__ */

136
board/Nuvoton_M251/STARTUP/Include/opa_reg.h Normal file
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@@ -0,0 +1,136 @@
/**************************************************************************//**
* @file opa_reg.h
* @version V1.00
* @brief OPA register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OPA_REG_H__
#define __OPA_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup OPA OP Amplifier (OPA)
Memory Mapped Structure for OPA Controller
@{ */
typedef struct
{
/**
* @var OPA_T::CTL
* Offset: 0x00 OP Amplifier Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPEN0 |OP Amplifier 0 Enable Bit
* | | |0 = Disable OP amplifier0.
* | | |1 = Enabled OP amplifier0.
* | | |Note: OP Amplifier 0 output needs wait stable 20us after OPEN0 is set.
* |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
* | | |0 = Disable OP amplifier0 schmitt trigger non-invert buffer.
* | | |1 = Enable OP amplifier0 schmitt trigger non-invert buffer.
* |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit
* | | |0 = OP Amplifier 0 digital output interrupt function Disabled.
* | | |1 = OP Amplifier 0 digital output interrupt function Enabled.
* | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital
* | | |output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
* @var OPA_T::STATUS
* Offset: 0x04 OP Amplifier Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |OPDO0 |OP Amplifier 0 Digital Output
* | | |Synchronized to the APB clock to allow reading by software.
* | | |Cleared when the Schmitt trigger buffer is disabled (OPDOEN0 = 0)
* |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
* | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital
* | | |output changes state. This bit is cleared by writing 1 to it.
* @var OPA_T::CALCTL
* Offset: 0x08 OP Amplifier Calibration Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit
* | | |0 = Stop, hardware auto clear.
* | | |1 = Start.
* | | |Note: Before enable this bit, it should set OPEN0 in advance.
* |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection
* | | |0 = VREF is 1/2 AVDD.
* | | |1 = VREF from high vcm to low vcm.
* @var OPA_T::CALST
* Offset: 0x0C OP Amplifier Calibration Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DONE0 |OP Amplifier 0 Calibration Done Status
* | | |0 = Calibrating.
* | | |1 = Calibration Done.
* |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS
* | | |0 = Pass.
* | | |1 = Fail.
* |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS
* | | |0 = Pass.
* | | |1 = Fail.
*/
__IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */
__IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */
__IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */
__I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */
} OPA_T;
/**
@addtogroup OPA_CONST OPA Bit Field Definition
Constant Definitions for OPA Controller
@{ */
#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */
#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */
#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */
#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */
#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */
#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */
#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */
#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */
#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */
#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */
#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */
#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */
#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */
#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */
#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */
#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */
#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */
#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */
#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */
#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */
/**@}*/ /* OPA_CONST */
/**@}*/ /* end of OPA register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __OPA_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/pdma_reg.h Normal file
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/**************************************************************************//**
* @file pdma_reg.h
* @version V1.00
* @brief PDMA register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PDMA_REG_H__
#define __PDMA_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup PDMA Peripheral Direct Memory Access Controller (PDMA)
Memory Mapped Structure for PDMA Controller
@{ */
typedef struct
{
/**
* @var DSCT_T::CTL
* Offset: 0x00 Descriptor Table Control Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE |PDMA Operation Mode Selection
* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
* | | |01 = Basic mode: The descriptor table only has one task
* | | |When this task is finished, the PDMA_INTSTS[n] will be asserted.
* | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
* | | |11 = Reserved.
* | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
* |[2] |TXTYPE |Transfer Type
* | | |0 = Burst transfer type.
* | | |1 = Single transfer type.
* |[6:4] |BURSIZE |Burst Size
* | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
* | | |000 = 128 Transfers.
* | | |001 = 64 Transfers.
* | | |010 = 32 Transfers.
* | | |011 = 16 Transfers.
* | | |100 = 8 Transfers.
* | | |101 = 4 Transfers.
* | | |110 = 2 Transfers.
* | | |111 = 1 Transfers.
* | | |Note: This field is only useful in burst transfer type.
* |[7] |TBINTDIS |Table Interrupt Disable Bit
* | | |This field can be used to decide whether to enable table interrupt or not
* | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
* | | |0 = Table interrupt Enabled.
* | | |1 = Table interrupt Disabled.
* |[9:8] |SAINC |Source Address Increment
* | | |This field is used to set the source address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[11:10] |DAINC |Destination Address Increment
* | | |This field is used to set the destination address increment size.
* | | |11 = No increment (fixed address).
* | | |Others = Increment and size is depended on TXWIDTH selection.
* |[13:12] |TXWIDTH |Transfer Width Selection
* | | |This field is used for transfer width.
* | | |00 = One byte (8 bit) is transferred for every operation.
* | | |01= One half-word (16 bit) is transferred for every operation.
* | | |10 = One word (32-bit) is transferred for every operation.
* | | |11 = Reserved.
* | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
* |[14] |TXACK |Transfer Acknowledge Selection
* | | |0 = transfer ack when transfer done.
* | | |1 = transfer ack when PDMA get transfer data.
* | | |Note: This function only support UART_RX and SPI_RX.
* |[15] |STRIDEEN |Stride Mode Enable Bit
* | | |0 = Stride transfer mode Disabled.
* | | |1 = Stride transfer mode Enabled.
* |[31:16] |TXCNT |Transfer Count
* | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
* | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
* @var DSCT_T::SA
* Offset: 0x04 Source Address Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SA |PDMA Transfer Source Address
* | | |This field indicates a 32-bit source address of PDMA controller.
* @var DSCT_T::DA
* Offset: 0x08 Destination Address Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DA |PDMA Transfer Destination Address
* | | |This field indicates a 32-bit destination address of PDMA controller.
* @var DSCT_T::NEXT
* Offset: 0x0C Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |NEXT |PDMA Next Descriptor Table Offset
* | | |This field indicates the offset of the next descriptor table address in system memory.
* | | |Write Operation:
* | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
* | | |Read Operation:
* | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.
* | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become scatter-gather mode control indicator as below.
* | | |0 = Idle mode.
* | | |1 = operating in the basic mode (final scatter-gather table).
* | | |2 = loading scatter-gather table from SRAM.
* | | |3 = operating in the scatter-gather mode.
* | | |Note1: The descriptor table address must be word boundary.
* | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
* |[31:16] |EXENEXT |PDMA Execution Next Descriptor Table Offset
* | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory.
* | | |Note: write operation is useless in this field.
*/
__IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */
__IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */
__IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */
__IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */
} DSCT_T;
typedef struct
{
/**
* @var STRIDE_T::STC
* Offset: 0x500 Stride Transfer Count Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |STC |PDMA Stride Transfer Count
* | | |The 16-bit register defines the stride transfer count of each row.
* @var STRIDE_T::ASOCR
* Offset: 0x504 Address Stride Offset Register of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |SASOL |VDMA Source Address Stride Offset Length
* | | |The 16-bit register defines the source address stride transfer offset count of each row.
* |[31:16] |DASOL |VDMA Destination Address Stride Offset Length
* | | |The 16-bit register defines the destination address stride transfer offset count of each row.
*/
__IO uint32_t STC; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */
__IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */
} STRIDE_T;
typedef struct
{
/**
* @var PDMA_T::CURSCAT
* Offset: 0x100 Current Scatter-gather Descriptor Table Address of PDMA Channel n
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |PDMA Current Description Address (Read Only)
* | | |This field indicates a 32-bit current external description address of PDMA controller.
* | | |Note: This field is read only and used for Scatter-Gather mode only to indicate the current external description address.
* @var PDMA_T::CHCTL
* Offset: 0x400 PDMA Channel Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CHENn |PDMA Channel Enable Bits
* | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
* | | |0 = PDMA channel [n] Disabled.
* | | |1 = PDMA channel [n] Enabled.
* | | |Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
* @var PDMA_T::PAUSE
* Offset: 0x404 PDMA Transfer Pause Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PAUSEn |PDMA Channel N Transfer Pause Control (Write Only)
* | | |User can set PAUSEn bit field to pause the PDMA transfer
* | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
* | | |If the paused channel is re-enabled again, the remaining transfers will be processed.
* | | |0 = No effect.
* | | |1 = Pause PDMA channel n transfer.
* @var PDMA_T::SWREQ
* Offset: 0x408 PDMA Software Request Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |SWREQn |PDMA Software Request (Write Only)
* | | |Set this bit to 1 to generate a software request to PDMA [n].
* | | |0 = No effect.
* | | |1 = Generate a software request.
* | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active
* | | |Active flag may be triggered by software request or peripheral request.
* | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
* @var PDMA_T::TRGSTS
* Offset: 0x40C PDMA Channel Request Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |REQSTSn |PDMA Channel Request Status (Read Only)
* | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
* | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
* | | |0 = PDMA Channel n has no request.
* | | |1 = PDMA Channel n has a request.
* | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
* @var PDMA_T::PRISET
* Offset: 0x410 PDMA Fixed Priority Setting Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |FPRISETn |PDMA Fixed Priority Setting
* | | |Set this bit to 1 to enable fixed priority level.
* | | |Write Operation:
* | | |0 = No effect.
* | | |1 = Set PDMA channel [n] to fixed priority channel.
* | | |Read Operation:
* | | |0 = Corresponding PDMA channel is round-robin priority.
* | | |1 = Corresponding PDMA channel is fixed priority.
* | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
* @var PDMA_T::PRICLR
* Offset: 0x414 PDMA Fixed Priority Clear Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |FPRICLRn |PDMA Fixed Priority Clear Bits (Write Only)
* | | |Set this bit to 1 to clear fixed priority level.
* | | |0 = No effect.
* | | |1 = Clear PDMA channel [n] fixed priority setting.
* | | |Note: User can read PDMA_PRISET register to know the channel priority.
* @var PDMA_T::INTEN
* Offset: 0x418 PDMA Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |INTENn |PDMA Interrupt Enable Bits
* | | |This field is used to enable PDMA channel[n] interrupt.
* | | |0 = PDMA channel n interrupt Disabled.
* | | |1 = PDMA channel n interrupt Enabled.
* @var PDMA_T::INTSTS
* Offset: 0x41C PDMA Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
* | | |0 = No AHB bus ERROR response received.
* | | |1 = AHB bus ERROR response received.
* |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
* | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
* | | |0 = Not finished yet.
* | | |1 = PDMA channel has finished transmission.
* |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* |[8] |REQTOF0 |Request Time-out Flag for Channel 0
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* |[9] |REQTOF1 |Request Time-out Flag for Channel 1
* | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
* | | |0 = No request time-out.
* | | |1 = Peripheral request time-out.
* @var PDMA_T::ABTSTS
* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
* | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
* | | |0 = No AHB bus ERROR response received when channel n transfer.
* | | |1 = AHB bus ERROR response received when channel n transfer.
* @var PDMA_T::TDSTS
* Offset: 0x424 PDMA Channel Transfer Done Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TDIF0 |Transfer Done Flag
* | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
* | | |0 = PDMA channel transfer has not finished.
* | | |1 = PDMA channel has finished transmission.
* @var PDMA_T::ALIGN
* Offset: 0x428 PDMA Transfer Alignment Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |ALIGNn |Transfer Alignment Flag
* | | |0 = PDMA channel source address and destination address both follow transfer width setting.
* | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
* @var PDMA_T::TACTSTS
* Offset: 0x42C PDMA Transfer Active Flag Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |TXACTFn |Transfer on Active Flag (Read Only)
* | | |This bit indicates which PDMA channel is in active.
* | | |0 = PDMA channel is not finished.
* | | |1 = PDMA channel is active.
* @var PDMA_T::TOUTPSC
* Offset: 0x430 PDMA Time-out Prescaler Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 0 time-out clock source is HCLK/28.
* | | |001 = PDMA channel 0 time-out clock source is HCLK/29.
* | | |010 = PDMA channel 0 time-out clock source is HCLK/210.
* | | |011 = PDMA channel 0 time-out clock source is HCLK/211.
* | | |100 = PDMA channel 0 time-out clock source is HCLK/212.
* | | |101 = PDMA channel 0 time-out clock source is HCLK/213.
* | | |110 = PDMA channel 0 time-out clock source is HCLK/214.
* | | |111 = PDMA channel 0 time-out clock source is HCLK/215.
* |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
* | | |000 = PDMA channel 1 time-out clock source is HCLK/28.
* | | |001 = PDMA channel 1 time-out clock source is HCLK/29.
* | | |010 = PDMA channel 1 time-out clock source is HCLK/210.
* | | |011 = PDMA channel 1 time-out clock source is HCLK/211.
* | | |100 = PDMA channel 1 time-out clock source is HCLK/212.
* | | |101 = PDMA channel 1 time-out clock source is HCLK/213.
* | | |110 = PDMA channel 1 time-out clock source is HCLK/214.
* | | |111 = PDMA channel 1 time-out clock source is HCLK/215.
* @var PDMA_T::TOUTEN
* Offset: 0x434 PDMA Time-out Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |TOUTENn |PDMA Time-out Enable Bits
* | | |0 = PDMA Channel n time-out function Disabled.
* | | |1 = PDMA Channel n time-out function Enabled.
* @var PDMA_T::TOUTIEN
* Offset: 0x438 PDMA Time-out Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits
* | | |0 = PDMA Channel n time-out interrupt Disabled.
* | | |1 = PDMA Channel n time-out interrupt Enabled.
* @var PDMA_T::SCATBA
* Offset: 0x43C PDMA Scatter-gather Descriptor Table Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address
* | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address
* | | |The next link address equation is
* | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
* | | |Note: Only useful in Scatter-Gather mode.
* @var PDMA_T::TOC0_1
* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TOC0 |Time-out Counter for Channel 0
* | | |This controls the period of time-out function for channel 0
* | | |The calculation unit is based on 10 kHz clock.
* |[31:16] |TOC1 |Time-out Counter for Channel 1
* | | |This controls the period of time-out function for channel 1
* | | |The calculation unit is based on 10 kHz clock.
* @var PDMA_T::CHRST
* Offset: 0x460 PDMA Channel Reset Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CHnRST |Channel N Reset
* | | |0 = corresponding channel n is not reset.
* | | |1 = corresponding channel n is reset.
* @var PDMA_T::REQSEL0_3
* Offset: 0x480 PDMA Request Source Select Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC0 |Channel 0 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 0
* | | |User can configure the peripheral by setting REQSRC0.
* | | |0 = Disable PDMA peripheral request.
* | | |1 = Reserved.
* | | |2 = Channel connects to USB_TX.
* | | |3 = Channel connects to USB_RX.
* | | |4 = Channel connects to UART0_TX.
* | | |5 = Channel connects to UART0_RX.
* | | |6 = Channel connects to UART1_TX.
* | | |7 = Channel connects to UART1_RX.
* | | |8 = Channel connects to UART2_TX.
* | | |9 = Channel connects to UART2_RX.
* | | |10=Channel connects to UART3_TX.
* | | |11 = Channel connects to UART3_RX.
* | | |12 = Channel connects to UART4_TX.
* | | |13 = Channel connects to UART4_RX.
* | | |14 = Channel connects to UART5_TX.
* | | |15 = Channel connects to UART5_RX.
* | | |16 = Channel connects to USCI0_TX.
* | | |17 = Channel connects to USCI0_RX.
* | | |18 = Channel connects to USCI1_TX.
* | | |19 = Channel connects to USCI1_RX.
* | | |20 = Channel connects to SPI0_TX.
* | | |21 = Channel connects to SPI0_RX.
* | | |22 = Channel connects to SPI1_TX.
* | | |23 = Channel connects to SPI1_RX.
* | | |24 = Channel connects to SPI2_TX.
* | | |25 = Channel connects to SPI2_RX.
* | | |26 = Channel connects to SPI3_TX.
* | | |27 = Channel connects to SPI3_RX.
* | | |28 = Channel connects to SPI4_TX.
* | | |29 = Channel connects to SPI4_RX.
* | | |30 = Reserved.
* | | |31 = Reserved.
* | | |32 = Channel connects to PWM0_P1_RX.
* | | |33 = Channel connects to PWM0_P2_RX.
* | | |34 = Channel connects to PWM0_P3_RX.
* | | |35 = Channel connects to PWM1_P1_RX.
* | | |36 = Channel connects to PWM1_P2_RX.
* | | |37 = Channel connects to PWM1_P3_RX.
* | | |38 = Channel connects to I2C0_TX.
* | | |39 = Channel connects to I2C0_RX.
* | | |40 = Channel connects to I2C1_TX.
* | | |41 = Channel connects to I2C1_RX.
* | | |42 = Channel connects to I2C2_TX.
* | | |43 = Channel connects to I2C2_RX.
* | | |44 = Channel connects to I2S0_TX.
* | | |45 = Channel connects to I2S0_RX.
* | | |46 = Channel connects to TMR0.
* | | |47 = Channel connects to TMR1.
* | | |48 = Channel connects to TMR2.
* | | |49 = Channel connects to TMR3.
* | | |50 = Channel connects to ADC_RX.
* | | |51 = Channel connects to DAC0_TX.
* | | |52 = Channel connects to DAC1_TX.
* | | |53 = Channel connects to PWM0_CH0_TX.
* | | |54 = Channel connects to PWM0_CH1_TX.
* | | |55 = Channel connects to PWM0_CH2_TX.
* | | |56 = Channel connects to PWM0_CH3_TX.
* | | |57 = Channel connects to PWM0_CH4_TX.
* | | |58 = Channel connects to PWM0_CH5_TX.
* | | |59 = Channel connects to PWM1_CH0_TX.
* | | |60 = Channel connects to PWM1_CH1_TX.
* | | |61 = Channel connects to PWM1_CH2_TX.
* | | |62 = Channel connects to PWM1_CH3_TX.
* | | |63 = Channel connects to PWM1_CH4_TX.
* | | |64 = Channel connects to PWM1_CH5_TX.
* | | |65 = Channel connects to ETMC_RX.
* | | |Others = Reserved.
* | | |Note 1: A peripheral cannot be assigned to two channels at the same time.
* | | |Note 2: This field is useless when transfer between memory and memory.
* |[14:8] |REQSRC1 |Channel 1 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 1
* | | |User can configure the peripheral setting by REQSRC1.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC2 |Channel 2 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 2
* | | |User can configure the peripheral setting by REQSRC2.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC3 |Channel 3 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 3
* | | |User can configure the peripheral setting by REQSRC3.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* @var PDMA_T::REQSEL4_7
* Offset: 0x484 PDMA Request Source Select Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |REQSRC4 |Channel 4 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 4
* | | |User can configure the peripheral setting by REQSRC4.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[14:8] |REQSRC5 |Channel 5 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 5
* | | |User can configure the peripheral setting by REQSRC5.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[22:16] |REQSRC6 |Channel 6 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 6
* | | |User can configure the peripheral setting by REQSRC6.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
* |[30:24] |REQSRC7 |Channel 7 Request Source Selection
* | | |This filed defines which peripheral is connected to PDMA channel 7
* | | |User can configure the peripheral setting by REQSRC7.
* | | |Note: The channel configuration is the same as REQSRC0 field
* | | |Please refer to the explanation of REQSRC0.
*/
DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] Control Register of PDMA Channel 0 ~ 7 */
__I uint32_t RESERVE0[32];
__I uint32_t CURSCAT[8]; /*!< [0x0100 ~ 0x11c] Current Scatter-gather Descriptor Table Address of PDMA Channel n */
__I uint32_t RESERVE1[184];
__IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
__O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
__O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
__I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
__IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
__O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
__IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
__IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
__IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
__IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
__I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
__IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
__IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
__IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
__IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-gather Descriptor Table Base Address Register */
__IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */
__I uint32_t RESERVE2[7];
__IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
__I uint32_t RESERVE3[7];
__IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */
__IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */
__I uint32_t RESERVE4[30];
STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x528] Stride Register of PDMA Channel 0 ~ 5 */
} PDMA_T;
/**
@addtogroup PDMA_CONST PDMA Bit Field Definition
Constant Definitions for PDMA Controller
@{ */
#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */
#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */
#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */
#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */
#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */
#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */
#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */
#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */
#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */
#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */
#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */
#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */
#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */
#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */
#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */
#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */
#define PDMA_DSCT_CTL_STRIDE_EN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */
#define PDMA_DSCT_CTL_STRIDE_EN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDE_EN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */
#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */
#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */
#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */
#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */
#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */
#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */
#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */
#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */
#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_NEXT: EXENEXT Position */
#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT0_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_NEXT: EXENEXT Mask */
#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
#define PDMA_CHCTL_CHENn_Msk (0xfful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
#define PDMA_PAUSE_PAUSEn_Msk (0xfful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
#define PDMA_SWREQ_SWREQn_Msk (0xfful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
#define PDMA_TRGSTS_REQSTSn_Msk (0xfful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
#define PDMA_PRISET_FPRISETn_Msk (0xfful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
#define PDMA_PRICLR_FPRICLRn_Msk (0xfful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
#define PDMA_ALIGN_ALIGNn_Msk (0xfful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
#define PDMA_TACTSTS_TXACTFn_Msk (0xfful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
#define PDMA_STCR_STC_Pos (0) /*!< PDMA_T::STCR: STC Position */
#define PDMA_STCR_STC_Msk (0xfffful << PDMA_STCR_STC_Pos) /*!< PDMA_T::STCR: STC Mask */
#define PDMA_ASOCR_SASOL_Pos (0) /*!< PDMA_T::ASOCR: SASOL Position */
#define PDMA_ASOCR_SASOL_Msk (0xfffful << PDMA_ASOCR_SASOL_Pos) /*!< PDMA_T::ASOCR: SASOL Mask */
#define PDMA_ASOCR_DASOL_Pos (16) /*!< PDMA_T::ASOCR: DASOL Position */
#define PDMA_ASOCR_DASOL_Msk (0xfffful << PDMA_ASOCR_DASOL_Pos) /*!< PDMA_T::ASOCR: DASOL Mask */
/**@}*/ /* PDMA_CONST */
/**@}*/ /* end of PDMA register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __PDMA_REG_H__ */

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/**************************************************************************//**
* @file qspi_reg.h
* @version V1.00
* @brief QSPI register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QSPI_REG_H__
#define __QSPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup QSPI Quad Serial Peripheral Interface Controller (QSPI)
Memory Mapped Structure for QSPI Controller
@{ */
typedef struct
{
/**
* @var QSPI_T::CTL
* Offset: 0x00 QSPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |QSPIEN |QSPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = QSPI bus clock is idle low.
* | | |1 = QSPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
* | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
* | | |.....
* | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
* | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 .... 8 bits.
* | | |DWIDTH = 0x09 .... 9 bits.
* | | |.....
* | | |DWIDTH = 0x1F .... 31 bits.
* | | |DWIDTH = 0x00 .... 32 bits.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
* |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for QSPI transfer
* | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = QSPI operates in full-duplex transfer.
* | | |1 = QSPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0)
* | | |0 = 2-Bit Transfer mode Disabled.
* | | |1 = 2-Bit Transfer mode Enabled.
* | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = QSPI unit transfer interrupt Disabled.
* | | |1 = QSPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = QSPI data is input direction.
* | | |1 = QSPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0)
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0)
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* @var QSPI_T::CLKDIV
* Offset: 0x04 QSPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* @var QSPI_T::SSCTL
* Offset: 0x08 QSPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the QSPIx_SS line to inactive state.
* | | |1 = set the QSPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the QSPIx_SS line at inactive state.
* | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (QSPIx_SS).
* | | |0 = The slave selection signal QSPIx_SS is active low.
* | | |1 = The slave selection signal QSPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0)
* | | |Slave 3-wire mode is only available in QSPI0
* | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0)
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0)
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0)
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var QSPI_T::PDMACTL
* Offset: 0x0C QSPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
* @var QSPI_T::FIFOCTL
* Offset: 0x10 QSPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* @var QSPI_T::STATUS
* Offset: 0x14 QSPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = QSPI controller is in idle state.
* | | |1 = QSPI controller is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
* | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = QSPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0)
* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurs.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurs.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |QSPIENSTS |QSPI Enable Status (Read Only)
* | | |0 = The QSPI controller is disabled.
* | | |1 = The QSPI controller is enabled.
* | | |Note: The QSPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var QSPI_T::TX
* Offset: 0x20 QSPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.
* | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid
* | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var QSPI_T::RX
* Offset: 0x30 QSPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register
* | | |There are 4-level FIFO buffers in this controller
* | | |The data receive register holds the data received from QSPI data input pin
* | | |This is a read only register.
*/
__IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[2];
/// @endcond //HIDDEN_SYMBOLS
__O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[3];
/// @endcond //HIDDEN_SYMBOLS
__I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */
} QSPI_T;
/**
@addtogroup QSPI_CONST QSPI Bit Field Definition
Constant Definitions for QSPI Controller
@{ */
#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */
#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */
#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */
#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */
#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */
#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */
#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */
#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */
#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */
#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */
#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */
#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */
#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */
#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */
#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */
#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */
#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */
#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */
#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */
#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */
#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */
#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */
#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */
#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */
#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */
#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */
#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */
#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */
#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */
#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */
#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */
#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */
#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */
#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */
#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */
#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */
#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */
#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */
#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */
#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */
#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */
#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */
#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */
#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */
#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */
#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */
#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */
#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */
#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */
#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */
#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */
#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */
#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */
#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */
#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */
#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */
#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */
#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */
#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */
#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */
#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */
#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */
#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */
#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */
#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */
#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */
#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */
#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */
#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */
#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */
#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */
#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */
#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */
#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */
#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */
#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */
#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */
#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */
#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */
#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */
#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */
#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */
#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */
#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */
#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */
#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */
#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */
#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */
#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */
#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */
#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */
#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */
#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */
#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */
#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */
#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */
#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */
#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */
#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */
#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */
#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */
#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */
#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */
#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */
#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */
#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */
#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */
#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */
#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */
#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */
#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */
#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */
#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */
#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */
#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */
#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */
#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */
#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */
#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */
#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */
#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */
#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */
#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */
#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */
#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */
#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */
#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */
#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */
#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */
#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */
#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */
#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */
/**@}*/ /* QSPI_CONST */
/**@}*/ /* end of QSPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __QSPI_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/rtc_reg.h Normal file
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/**************************************************************************//**
* @file rtc_reg.h
* @version V1.00
* @brief RTC register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __RTC_REG_H__
#define __RTC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup RTC Real Time Clock Controller (RTC)
Memory Mapped Structure for RTC Controller
@{ */
typedef struct
{
/**
* @var RTC_T::INIT
* Offset: 0x00 RTC Initiation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
* | | |0 = RTC is at reset state.
* | | |1 = RTC is at normal active state.
* |[31:1] |INIT |RTC Initiation (Write Only)
* | | |When RTC block is powered on, RTC is at reset state.
* | | |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state.
* | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
* | | |The INIT is a write-only field and read value will be always 0.
* @var RTC_T::FREQADJ
* Offset: 0x08 RTC Frequency Compensation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |FRACTION |Fraction Part
* | | |Formula: FRACTION = (fraction part of detected value) X 64.
* | | |Note: Digit in FCR must be expressed as hexadecimal number.
* |[12:8] |INTEGER |Integer Part
* | | |00000 = Integer part of detected value is 32752.
* | | |00001 = Integer part of detected value is 32753.
* | | |00010 = Integer part of detected value is 32754.
* | | |00011 = Integer part of detected value is 32755.
* | | |00100 = Integer part of detected value is 32756.
* | | |00101 = Integer part of detected value is 32757.
* | | |00110 = Integer part of detected value is 32758.
* | | |00111 = Integer part of detected value is 32759.
* | | |01000 = Integer part of detected value is 32760.
* | | |01001 = Integer part of detected value is 32761.
* | | |01010 = Integer part of detected value is 32762.
* | | |01011 = Integer part of detected value is 32763.
* | | |01100 = Integer part of detected value is 32764.
* | | |01101 = Integer part of detected value is 32765.
* | | |01110 = Integer part of detected value is 32766.
* | | |01111 = Integer part of detected value is 32767.
* | | |10000 = Integer part of detected value is 32768.
* | | |10001 = Integer part of detected value is 32769.
* | | |10010 = Integer part of detected value is 32770.
* | | |10011 = Integer part of detected value is 32771.
* | | |10100 = Integer part of detected value is 32772.
* | | |10101 = Integer part of detected value is 32773.
* | | |10110 = Integer part of detected value is 32774.
* | | |10111 = Integer part of detected value is 32775.
* | | |11000 = Integer part of detected value is 32776.
* | | |11001 = Integer part of detected value is 32777.
* | | |11010 = Integer part of detected value is 32778.
* | | |11011 = Integer part of detected value is 32779.
* | | |11100 = Integer part of detected value is 32780.
* | | |11101 = Integer part of detected value is 32781.
* | | |11110 = Integer part of detected value is 32782.
* | | |11111 = Integer part of detected value is 32783.
* @var RTC_T::TIME
* Offset: 0x0C RTC Time Loading Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SEC |1-Sec Time Digit (0~9)
* |[6:4] |TENSEC |10-Sec Time Digit (0~5)
* |[11:8] |MIN |1-Min Time Digit (0~9)
* |[14:12] |TENMIN |10-Min Time Digit (0~5)
* |[19:16] |HR |1-Hour Time Digit (0~9)
* |[21:20] |TENHR |10-Hour Time Digit (0~2)
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0])
* | | |means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
* @var RTC_T::CAL
* Offset: 0x10 RTC Calendar Loading Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DAY |1-Day Calendar Digit (0~9)
* |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
* |[11:8] |MON |1-Month Calendar Digit (0~9)
* |[12] |TENMON |10-Month Calendar Digit (0~1)
* |[19:16] |YEAR |1-Year Calendar Digit (0~9)
* |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
* @var RTC_T::CLKFMT
* Offset: 0x14 RTC Time Scale Selection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |24HEN |24-hour / 12-hour Time Scale Selection
* | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale.
* | | |0 = 12-hour time scale with AM and PM indication selected.
* | | |1 = 24-hour time scale selected.
* @var RTC_T::WEEKDAY
* Offset: 0x18 RTC Day of the Week Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |WEEKDAY |Day of the Week Register
* | | |000 = Sunday.
* | | |001 = Monday.
* | | |010 = Tuesday.
* | | |011 = Wednesday.
* | | |100 = Thursday.
* | | |101 = Friday.
* | | |110 = Saturday.
* | | |111 = Reserved.
* @var RTC_T::TALM
* Offset: 0x1C RTC Time Alarm Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
* |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
* |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
* |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
* |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
* |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
* | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0])
* | | |means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
* @var RTC_T::CALM
* Offset: 0x20 RTC Calendar Alarm Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
* |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
* |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
* |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
* |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
* |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
* @var RTC_T::LEAPYEAR
* Offset: 0x24 RTC Leap Year Indicator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
* | | |0 = This year is not a leap year.
* | | |1 = This year is leap year.
* @var RTC_T::INTEN
* Offset: 0x28 RTC Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ALMIEN |Alarm Interrupt Enable Bit
* | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
* | | |0 = RTC Alarm interrupt Disabled.
* | | |1 = RTC Alarm interrupt Enabled.
* |[1] |TICKIEN |Time Tick Interrupt Enable Bit
* | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
* | | |0 = RTC Time Tick interrupt Disabled.
* | | |1 = RTC Time Tick interrupt Enabled.
* |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit
* | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
* | | |0 = Tamper 0 interrupt Disabled.
* | | |1 = Tamper 0 interrupt Enabled.
* @var RTC_T::INTSTS
* Offset: 0x2C RTC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ALMIF |RTC Alarm Interrupt Flag
* | | |0 = Alarm condition is not matched.
* | | |1 = Alarm condition is matched.
* | | |Note: Write 1 to clear this bit.
* |[1] |TICKIF |RTC Time Tick Interrupt Flag
* | | |0 = Tick condition does not occur.
* | | |1 = Tick condition occur.
* | | |Note: Write 1 to clear this bit.
* |[8] |TAMP0IF |Tamper 0 Interrupt Flag
* | | |0 = No Tamper 0 interrupt flag is generated.
* | | |1 = Tamper 0 interrupt flag is generated.
* | | |Note1: Write 1 to clear this bit.
* @var RTC_T::TICK
* Offset: 0x30 RTC Time Tick Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |TICK |Time Tick Register
* | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
* | | |000 = Time tick is 1 second.
* | | |001 = Time tick is 1/2 second.
* | | |010 = Time tick is 1/4 second.
* | | |011 = Time tick is 1/8 second.
* | | |100 = Time tick is 1/16 second.
* | | |101 = Time tick is 1/32 second.
* | | |110 = Time tick is 1/64 second.
* | | |111 = Time tick is 1/128 second.
* @var RTC_T::TAMSK
* Offset: 0x34 RTC Time Alarm Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
* |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
* |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
* |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
* |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
* |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
* @var RTC_T::CAMSK
* Offset: 0x38 RTC Calendar Alarm Mask Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
* |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
* |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
* |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
* |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
* |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
* @var RTC_T::SPRCTL
* Offset: 0x3C RTC Spare Functional Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPRCLRM |Spare Register Clear Mask Bit
* | | |0 = Spare register will be clear after TAMPER occur.
* | | |1 = Spare register will not be clear after TAMPER occur.
* |[2] |SPRRWEN |Spare Register Enable Bit
* | | |0 = Spare register is Disabled.
* | | |1 = Spare register is Enabled.
* | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed.
* |[5] |SPRCSTS |SPR Clear Flag
* | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR4 content is cleared when specify tamper event is detected.
* | | |0 = Spare register content is not cleared.
* | | |1 = Spare register content is cleared.
* | | |Writes 1 to clear this bit.
* | | |Note: This bit keep 1 when RTC_INTSTS[8] not equal zero.
* @var RTC_T::SPR
* Offset: 0x40~0x50 RTC Spare Register 0/1/2/3/4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SPARE |Spare Register
* | | |This field is used to store back-up information defined by user.
* | | |This field will be cleared by hardware automatically once a tamper pin event is detected.
* | | |Before storing back-up information in to RTC_SPRx register, user should check the register
* | | |read/write enable bit SPRRWEN (RTC_SPRCTL[2]) is enabled.
* @var RTC_T::LXTCTL
* Offset: 0x100 RTC 32KHz Oscillator Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:1] |GAIN |Oscillator Gain Option
* | | |User can select oscillator gain according to crystal external loading and operating temperature range.
* | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
* | | |000 = L0 mode.
* | | |001 = L1 mode.
* | | |010 = L2 mode.
* | | |011 = L3 mode.
* | | |100 = L4 mode(Only for VBAT domain).
* | | |101 = L5 mode(Only for VBAT domain).
* | | |110 = L6 mode(Only for VBAT domain).
* | | |111 = L7 mode(Only for VBAT domain).
* |[7] |C32KS |RTC Clock 32K Source Selection:
* | | |0 = Internal RTC clock is from 32K crystal .
* | | |1 = Internal RTC clock is from LIRC38K.
* |[13] |RTCLVDPD |RTC Low Voltage Detector Power Down (Only for VBAT domain)
* | | |0= RTC Low Voltage Detector active..
* | | |1= RTC Low Voltage Detector enter power down.
* |[14] |RTCPORPD |RTC Power on Reset Power Down (Only for VBAT domain)
* | | |0= RTC POR active 1sec after first power up.
* | | |1= RTC POR enter power down.
* @var RTC_T::GPIOCTL0
* Offset: 0x104 RTC GPIO Control 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |OPMODE0 |IO Operation Mode(Only for VBAT domain)
* | | |00 = PF.4 is input only mode.
* | | |01 = PF.4 is output push pull mode.
* | | |10 = PF.4 is open drain mode.
* | | |11 = PF.4 is quasi-bidirectional mode.
* |[2] |DOUT0 |IO Output Data(Only for VBAT domain)
* | | |0 = PF.4 output low.
* | | |1 = PF.4 output high.
* |[3] |CTLSEL0 |IO Pin State Backup Selection(Only for VBAT domain)
* | | |When low speed 32kHz oscillator is disabled, PF.4 pin(X32KO pin) can be used as GPIO function.
* | | |User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module
* | | |or VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.4 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.
* | | |1 = PF.4 pin I/O function is controlled by VBAT power domain.
* | | |PF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.
* | | |Note 1:CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0](RTC_INIT[0]) is 1.
* | | |NOte 2:The GPIO control feature is not supported when there is not any VBAT power domain.
* |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bits(Only for VBAT domain)
* | | |Determine PF.4 I/O pull-up or pull-down.
* | | |00 = PF.4 pull-up and pull-down disable.
* | | |01 = PF.4 pull-up enable.
* | | |10 = PF.4 pull-down enable.
* | | |11 = PF.4 pull-up and pull-down disable.
* | | |Note:Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up / pull-down control register only valid when OPMODE0 set as input tri-state
* | | |and open-drain mode.
* |[6] |SMTEN0 |Input Schmitt Trigger Enable Bit(Only for VBAT domain)
* | | |0 = PF.4 input schmitt trigger function Disabled.
* | | |1 = PF.4 input schmitt trigger function Enabled.
* |[9:8] |OPMODE1 |IO Operation Mode(Only for VBAT domain)
* | | |00 = PF.5 is input only mode.
* | | |01 = PF.5 is output push pull mode.
* | | |10 = PF.5 is open drain mode.
* | | |11 = PF.5 is quasi-bidirectional mode.
* |[10] |DOUT1 |IO Output Data(Only for VBAT domain)
* | | |0 = PF.5 output low.
* | | |1 = PF.5 output high.
* |[11] |CTLSEL1 |IO Pin State Backup Selection(Only for VBAT domain)
* | | |When low speed 32kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function.
* | | |User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module
* | | |or VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.5 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.
* | | |1 = PF.5 pin I/O function is controlled by VBAT power domain.
* | | |PF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.
* | | |Note 1:CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0](RTC_INIT[0]) is 1.
* | | |NOte 2:The GPIO control feature is not supported when there is not any VBAT power domain.
* |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bits(Only for VBAT domain)
* | | |Determine PF.5 I/O pull-up or pull-down.
* | | |00 = PF.5 pull-up and pull-down disable.
* | | |01 = PF.5 pull-up enable.
* | | |10 = PF.5 pull-down enable.
* | | |11 = PF.5 pull-up and pull-down disable.
* | | |Note:Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up / pull-down control register only valid when OPMODE1 set as input tri-state
* | | |and open-drain mode.
* |[14] |SMTEN1 |Input Schmitt Trigger Enable Bit(Only for VBAT domain)
* | | |0 = PF.5 input schmitt trigger function Disabled.
* | | |1 = PF.5 input schmitt trigger function Enabled.
* |[17:16] |OPMODE2 |IO Operation Mode(Only for VBAT domain)
* | | |00 = PF.6 is input only mode.
* | | |01 = PF.6 is output push pull mode.
* | | |10 = PF.6 is open drain mode.
* | | |11 = PF.6 is quasi-bidirectional mode.
* |[18] |DOUT2 |IO Output Data(Only for VBAT domain)
* | | |0 = PF.6 output low.
* | | |1 = PF.6 output high.
* |[19] |CTLSEL2 |IO Pin State Backup Selection(Only for VBAT domain)
* | | |When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function.
* | | |User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module
* | | |or VBAT power domain RTC_GPIOCTL0 control register.
* | | |0 = PF.6 pin I/O function is controlled by GPIO module.
* | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.
* | | |1 = PF.6 pin I/O function is controlled by VBAT power domain.
* | | |PF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.
* | | |Note 1:CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0](RTC_INIT[0]) is 1.
* | | |NOte 2:The GPIO control feature is not supported when there is not any VBAT power domain.
* |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bits(Only for VBAT domain)
* | | |Determine PF.6 I/O pull-up or pull-down.
* | | |00 = PF.6 pull-up and pull-down disable.
* | | |01 = PF.6 pull-up enable.
* | | |10 = PF.6 pull-down enable.
* | | |11 = PF.6 pull-up and pull-down disable.
* | | |Note:Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state
* | | |and open-drain mode and PF6 as tamper pin.
* |[22] |SMTEN2 |Input Schmitt Trigger Enable Bit(Only for VBAT domain)
* | | |0 = PF.6 input schmitt trigger function Disabled.
* | | |1 = PF.6 input schmitt trigger function Enabled.
* @var RTC_T::DSTCTL
* Offset: 0x110 RTC Daylight Saving Time Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADDHR |Add 1 Hour
* | | |0 = No effect.
* | | |1 = RTC hour digit has been added one hour for summer time change.
* |[1] |SUBHR |Subtract 1 Hour
* | | |0 = No effect.
* | | |1 = RTC hour digit has been subtracted one hour for winter time change.
* |[2] |DSBAK |Daylight Saving Back
* | | |0= Normal mode.
* | | |1= Daylight saving mode.
* @var RTC_T::TAMPCTL
* Offset: 0x120 RTC Tamper Pin Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8] |TAMP0EN |Tamper0 Detect Enable Bit
* | | |0 = Tamper 0 detect Disabled.
* | | |1 = Tamper 0 detect Enabled.
* | | |Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
* |[9] |TAMP0LV |Tamper 0 Level
* | | |This bit depend on level attribute of tamper pin for static tamper detection.
* | | |0 = Detect Rising detection, will trigger tamper status when RTC_TAMPCTL[11] = 1.
* | | |Detect voltage level should be low. High will trigger tamper status when RTC_TAMPCTL[11] = 0.
* | | |1 = Detect Falling detection, will trigger tamper status when RTC_TAMPCTL[11] = 1.
* | | |Detect voltage level shoulld be high. Low will trigger tamper status when RTC_TAMPCTL[11] = 0.
* |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
* | | |0 = Tamper 0 de-bounce Disabled.
* | | |1 = Tamper 0 de-bounce Enabled.
* | | |Note: In normal condition (25'C), it can deglitch 1~2 ns noise.
* |[11] |TAMP0TYPE |Tamper 0 Detect Type
* | | |0 = Tamper as edge detector.
* | | |1 = Tamper as Level detector.
* @var RTC_T::TAMPTIME
* Offset: 0x130 RTC Tamper Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9)
* |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5)
* |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9)
* |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5)
* |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9)
* |[21:20] |TENHR |10-hour Time Digit of TAMPER Time (0~2)
* | | |Note: 24-hour time scale only.
* @var RTC_T::TAMPCAL
* Offset: 0x134 RTC Tamper Calendar Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9)
* |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3)
* |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9)
* |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1)
* |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9)
* |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9)
*/
__IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
__I uint32_t RESERVE0[1];
__IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
__IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
__IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
__IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
__IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
__IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
__IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
__I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
__IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
__IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
__IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
__IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
__IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */
__IO uint32_t SPR[5]; /*!< [0x0040 ~ 0x0050] RTC Spare Register 0 ~ 4 */
__I uint32_t RESERVE1[43];
__IO uint32_t LXTCTL; /*!< [0x0100] RTC 32KHz Oscillator Control Register */
__IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */
__I uint32_t RESERVE2[2];
__IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */
__I uint32_t RESERVE3[3];
__IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */
__I uint32_t RESERVE4[3];
__I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */
__I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */
} RTC_T;
/**
@addtogroup RTC_CONST RTC Bit Field Definition
Constant Definitions for RTC Controller
@{ */
#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */
#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */
#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */
#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */
#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */
#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */
#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
#define RTC_SPRCTL_SPRCLRM_Pos (0) /*!< RTC_T::SPRCTL: SPRCLRM Position */
#define RTC_SPRCTL_SPRCLRM_Msk (0x1ul << RTC_SPRCTL_SPRCLRM_Pos) /*!< RTC_T::SPRCTL: SPRCLRM Mask */
#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */
#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */
#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */
#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */
#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */
#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */
#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */
#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */
#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */
#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */
#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
#define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */
#define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */
#define RTC_LXTCTL_RTCLVDPD_Pos (13) /*!< RTC_T::LXTCTL: RTCLVDPD Position */
#define RTC_LXTCTL_RTCLVDPD_Msk (0x1ul << RTC_LXTCTL_RTCLVDPD_Pos) /*!< RTC_T::LXTCTL: RTCLVDPD Mask */
#define RTC_LXTCTL_RTCPORPD_Pos (14) /*!< RTC_T::LXTCTL: RTCPORPD Position */
#define RTC_LXTCTL_RTCPORPD_Msk (0x1ul << RTC_LXTCTL_RTCPORPD_Pos) /*!< RTC_T::LXTCTL: RTCPORPD Mask */
#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */
#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */
#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */
#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */
#define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */
#define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */
#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */
#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */
#define RTC_GPIOCTL0_SMTEN0_Pos (6) /*!< RTC_T::GPIOCTL0: SMTEN0 Position */
#define RTC_GPIOCTL0_SMTEN0_Msk (0x1ul << RTC_GPIOCTL0_SMTEN0_Pos) /*!< RTC_T::GPIOCTL0: SMTEN0 Mask */
#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */
#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */
#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */
#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */
#define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */
#define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */
#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */
#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */
#define RTC_GPIOCTL0_SMTEN1_Pos (14) /*!< RTC_T::GPIOCTL0: SMTEN1 Position */
#define RTC_GPIOCTL0_SMTEN1_Msk (0x1ul << RTC_GPIOCTL0_SMTEN1_Pos) /*!< RTC_T::GPIOCTL0: SMTEN1 Mask */
#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */
#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */
#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */
#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */
#define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */
#define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */
#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */
#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */
#define RTC_GPIOCTL0_SMTEN2_Pos (22) /*!< RTC_T::GPIOCTL0: SMTEN2 Position */
#define RTC_GPIOCTL0_SMTEN2_Msk (0x1ul << RTC_GPIOCTL0_SMTEN2_Pos) /*!< RTC_T::GPIOCTL0: SMTEN2 Mask */
#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */
#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */
#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */
#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */
#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */
#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */
#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */
#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */
#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */
#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */
#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */
#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */
#define RTC_TAMPCTL_TAMP0TYPE_Pos (11) /*!< RTC_T::TAMPCTL: TAMP0TYPE Position */
#define RTC_TAMPCTL_TAMP0TYPE_Msk (0x1ul << RTC_TAMPCTL_TAMP0TYPE_Pos) /*!< RTC_T::TAMPCTL: TAMP0TYPE Mask */
#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */
#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */
#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */
#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */
#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */
#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */
#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */
#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */
#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */
#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */
#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */
#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */
#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */
#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */
#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */
#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */
#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */
#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */
#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */
#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */
#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */
#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */
#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */
#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */
/**@}*/ /* RTC_CONST */
/**@}*/ /* end of RTC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __RTC_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/sc_reg.h Normal file
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/**************************************************************************//**
* @file sc_reg.h
* @version V1.00
* @brief SC register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SC_REG_H__
#define __SC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SC Smart Card Host Interface Controller (SC)
Memory Mapped Structure for SC Controller
@{ */
typedef struct
{
/**
* @var SC_T::DAT
* Offset: 0x00 SC Receive/Transmit Holding Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DAT |Receive/Transmit Holding Buffer
* | | |Write Operation:
* | | |By writing data to DAT, the SC will send out an 8-bit data.
* | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
* | | |Read Operation:
* | | |By reading DAT, the SC will return an 8-bit received data.
* @var SC_T::CTL
* Offset: 0x04 SC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SCEN |SC Controller Enable Bit
* | | |Set this bit to 1 to enable SC operation. If this bit is cleared,
* | | |0 = SC will force all transition to IDLE state.
* | | |1 = SC controller is enabled and all function can work correctly.
* | | |Note: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
* |[1] |RXOFF |RX Transition Disable Control Bit
* | | |This bit is used for disable Rx transition function.
* | | |0 = The receiver Enabled.
* | | |1 = The receiver Disabled.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[2] |TXOFF |TX Transition Disable Control Bit
* | | |This bit is used for disable Tx transition function.
* | | |0 = The transceiver Enabled.
* | | |1 = The transceiver Disabled.
* |[3] |AUTOCEN |Auto Convention Enable Bit
* | | |This bit is used for enable auto convention function.
* | | |0 = Auto-convention Disabled.
* | | |1 = Auto-convention Enabled.
* | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F
* | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F
* | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
* | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
* |[5:4] |CONSEL |Convention Selection
* | | |00 = Direct convention.
* | | |01 = Reserved.
* | | |10 = Reserved.
* | | |11 = Inverse convention.
* | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
* |[7:6] |RXTRGLV |Rx Buffer Trigger Level
* | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
* | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
* | | |00 = Rx Buffer Trigger Level with 01 bytes.
* | | |01 = Rx Buffer Trigger Level with 02 bytes.
* | | |10 = Rx Buffer Trigger Level with 03 bytes.
* | | |11 = Reserved.
* |[12:8] |BGT |Block Guard Time (BGT)
* | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions
* | | |This field indicates the counter for the bit length of block guard time
* | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
* | | |Note: The real block guard time is BGT + 1.
* |[14:13] |TMRSEL |Timer Channel Selection
* | | |00 = All internal timer function Disabled.
* | | |11 = Internal 24 bit timer and two 8 bit timers Enabled
* | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
* | | |Other configurations are reserved
* |[15] |NSB |Stop Bit Length
* | | |This field indicates the length of stop bit.
* | | |0 = The stop bit length is 2 ETU.
* | | |1= The stop bit length is 1 ETU.
* | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
* | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
* |[18:16] |RXRTY |RX Error Retry Count Number
* | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
* | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when RXRTYEN enabled
* | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
* |[19] |RXRTYEN |RX Error Retry Enable Bit
* | | |This bit enables receiver retry function when parity error has occurred.
* | | |0 = RX error retry function Disabled.
* | | |1 = RX error retry function Enabled.
* | | |Note: User must fill in the RXRTY value before enabling this bit.
* |[22:20] |TXRTY |TX Error Retry Count Number
* | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
* | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
* | | |Note2: This field cannot be changed when TXRTYEN enabled
* | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
* |[23] |TXRTYEN |TX Error Retry Enable Bit
* | | |This bit enables transmitter retry function when parity error has occurred.
* | | |0 = TX error retry function Disabled.
* | | |1 = TX error retry function Enabled.
* |[25:24] |CDDBSEL |Card Detect De-bounce Selection
* | | |This field indicates the card detect de-bounce selection.
* | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks.
* | | |Other configurations are reserved.
* |[26] |CDLV |Card Detect Level Selection
* | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
* | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
* | | |Note: User must select card detect level before Smart Card controller enabled.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
* | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
* | | |1 = Last value is synchronizing.
* @var SC_T::ALTCTL
* Offset: 0x08 SC Alternate Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXRST |TX Software Reset
* | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the TX internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[1] |RXRST |Rx Software Reset
* | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
* | | |0 = No effect.
* | | |1 = Reset the Rx internal state machine and pointers.
* | | |Note: This bit will be auto cleared after reset is complete.
* |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by deactivation sequence.
* | | |0 = No effect.
* | | |1 = Deactivation sequence generator Enabled.
* | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[3] |ACTEN |Activation Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by activation sequence.
* | | |0 = No effect.
* | | |1 = Activation sequence generator Enabled.
* | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data
* | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
* |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
* | | |This bit enables SC controller to initiate the card by warm reset sequence.
* | | |0 = No effect.
* | | |1 = Warm reset sequence generator Enabled.
* | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
* | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
* | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
* | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
* |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
* | | |This bit enables Timer 0 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
* | | |This bit enables Timer 1 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
* | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
* | | |This bit enables Timer 2 to start counting
* | | |User can fill 0 to stop it and set 1 to reload and count
* | | |The counter unit is ETU base.
* | | |0 = Stops counting.
* | | |1 = Start counting.
* | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
* | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
* | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
* | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
* |[9:8] |INITSEL |Initial Timing Selection
* | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
* | | |The unit of initial timing is SC module clock.
* | | |Activation: refer to SC Activation Sequence in Figure 7.14-54.
* | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.14-5.
* | | |Deactivation: refer to Deactivation Sequence in Figure 7.14-56.
* | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
* |[11] |ADACEN |Auto Deactivation When Card Removal
* | | |This bit is used for enable hardware auto deactivation when smart card is removed.
* | | |0 = Auto deactivation Disabled.
* | | |1 = Auto deactivation Enabled.
* | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set
* | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
* |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
* | | |This bit enables the receiver block guard time function.
* | | |0 = Receiver block guard time function Disabled.
* | | |1 = Receiver block guard time function Enabled.
* |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer0.
* | | |0 = Timer0 is not active.
* | | |1 = Timer0 is active.
* | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
* |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer1.
* | | |0 = Timer1 is not active.
* | | |1 = Timer1 is active.
* | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
* |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only)
* | | |This bit indicates the timer counter status of timer2.
* | | |0 = Timer2 is not active.
* | | |1 = Timer2 is active.
* | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::EGT
* Offset: 0x0C SC Extra Guard Time Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |EGT |Extra Guard Time
* | | |This field indicates the extra guard time value.
* | | |Note: The extra guard time unit is ETU base.
* @var SC_T::RXTOUT
* Offset: 0x10 SC Receive Buffer Time-out Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |RFTM |SC Receiver FIFO Time-out Counter
* | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data
* | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.
* | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
* | | |Note2: Filling in all 0 to this field indicates to disable this function.
* @var SC_T::ETUCTL
* Offset: 0x14 SC Element Time Unit Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |ETURDIV |ETU Rate Divider
* | | |The field is used for ETU clock rate divider.
* | | |The real ETU is ETURDIV + 1.
* | | |Note: User can configure this field, but this field must be greater than 0x04.
* @var SC_T::INTEN
* Offset: 0x18 SC Interrupt Enable Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
* | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
* | | |0 = Receive data reach trigger level interrupt Disabled.
* | | |1 = Receive data reach trigger level interrupt Enabled.
* |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
* | | |This field is used to enable transmit buffer empty interrupt.
* | | |0 = Transmit buffer empty interrupt Disabled.
* | | |1 = Transmit buffer empty interrupt Enabled.
* |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
* | | |This field is used to enable transfer error interrupt
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt Disabled.
* | | |1 = Transfer error interrupt Enabled.
* |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
* | | |This field is used to enable Timer0 interrupt function.
* | | |0 = Timer0 interrupt Disabled.
* | | |1 = Timer0 interrupt Enabled.
* |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
* | | |This field is used to enable the Timer1 interrupt function.
* | | |0 = Timer1 interrupt Disabled.
* | | |1 = Timer1 interrupt Enabled.
* |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
* | | |This field is used to enable Timer2 interrupt function.
* | | |0 = Timer2 interrupt Disabled.
* | | |1 = Timer2 interrupt Enabled.
* |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
* | | |This field is used to enable block guard time interrupt in receive direction.
* | | |0 = Block guard time interrupt Disabled.
* | | |1 = Block guard time interrupt Enabled.
* | | |Note: This bit is valid only for receive direction block guard time.
* |[7] |CDIEN |Card Detect Interrupt Enable Bit
* | | |This field is used to enable card detect interrupt
* | | |The card detect status is CDPINSTS (SCn_STATUS[13]).
* | | |0 = Card detect interrupt Disabled.
* | | |1 = Card detect interrupt Enabled.
* |[8] |INITIEN |Initial End Interrupt Enable Bit
* | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
* | | |0 = Initial end interrupt Disabled.
* | | |1 = Initial end interrupt Enabled.
* |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit
* | | |This field is used to enable receiver buffer time-out interrupt.
* | | |0 = Receiver buffer time-out interrupt Disabled.
* | | |1 = Receiver buffer time-out interrupt Enabled.
* |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
* | | |This field is used to enable auto-convention error interrupt.
* | | |0 = Auto-convention error interrupt Disabled.
* | | |1 = Auto-convention error interrupt Enabled.
* @var SC_T::INTSTS
* Offset: 0x1C SC Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
* | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
* | | |0 = Number of receive buffer is less than RXTRGLV setting.
* | | |1 = Number of receive buffer data equals the RXTRGLV setting.
* | | |Note: This bit is read only
* | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
* |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
* | | |This field is used for transmit buffer empty interrupt status flag.
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* | | |Note: This bit is read only
* | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
* |[2] |TERRIF |Transfer Error Interrupt Status Flag
* | | |This field is used for transfer error interrupt status flag
* | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
* | | |0 = Transfer error interrupt did not occur.
* | | |1 = Transfer error interrupt occurred.
* | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[3] |TMR0IF |Timer0 Interrupt Status Flag
* | | |This field is used for Timer0 interrupt status flag.
* | | |0 = Timer0 interrupt did not occur.
* | | |1 = Timer0 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[4] |TMR1IF |Timer1 Interrupt Status Flag
* | | |This field is used for Timer1 interrupt status flag.
* | | |0 = Timer1 interrupt did not occur.
* | | |1 = Timer1 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[5] |TMR2IF |Timer2 Interrupt Status Flag
* | | |This field is used for Timer2 interrupt status flag.
* | | |0 = Timer2 interrupt did not occur.
* | | |1 = Timer2 interrupt occurred.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[6] |BGTIF |Block Guard Time Interrupt Status Flag
* | | |This field is used for indicate block guard time interrupt status flag in receive direction.
* | | |0 = Block guard time interrupt did not occur.
* | | |1 = Block guard time interrupt occurred.
* | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
* | | |Note2: This bit can be cleared by writing 1 to it.
* |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
* | | |This field is used for card detect interrupt status flag
* | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
* | | |0 = Card detect event did not occur.
* | | |1 = Card detect event occurred.
* | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
* |[8] |INITIF |Initial End Interrupt Status Flag
* | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
* | | |0 = Initial sequence is not complete.
* | | |1 = Initial sequence is completed.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only)
* | | |This field is used for indicate receive buffer time-out interrupt status flag.
* | | |0 = Receive buffer time-out interrupt did not occur.
* | | |1 = Receive buffer time-out interrupt occurred.
* | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
* |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag
* | | |This field indicates auto convention sequence error.
* | | |0 = Received TS at ATR state is 0x3B or 0x3F.
* | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
* | | |Note: This bit can be cleared by writing 1 to it.
* @var SC_T::STATUS
* Offset: 0x20 SC Transfer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXOV |Receive Overflow Error Status Flag
* | | |This bit is set when Rx buffer overflow.
* | | |0 = Rx buffer is not overflow.
* | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only)
* | | |This bit indicates Rx buffer empty or not.
* | | |0 = Rx buffer is not empty.
* | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
* |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only)
* | | |This bit indicates Rx buffer full or not.
* | | |0 = Rx buffer count is less than 4.
* | | |1 = Rx buffer count equals to 4.
* |[4] |PEF |Receiver Parity Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
* | | |0 = Receiver parity error flag did not occur.
* | | |1 = Receiver parity error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[5] |FEF |Receiver Frame Error Status Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = Receiver frame error flag did not occur.
* | | |1 = Receiver frame error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[6] |BEF |Receiver Break Error Status Flag
* | | |This bit is set to logic 1 whenever the received data input (Rx) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + "data bits" + "parity bit" + "stop bits").
* | | |0 = Receiver break error flag did not occur.
* | | |1 = Receiver break error flag occurred.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag
* | | |This bit is set when Tx buffer overflow.
* | | |0 = Tx buffer is not overflow.
* | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
* | | |Note: This bit can be cleared by writing 1 to it.
* |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
* | | |This bit indicates TX buffer empty or not.
* | | |0 = Tx buffer is not empty.
* | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register.
* | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
* |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
* | | |This bit indicates Tx buffer full or not.
* | | |0 = Tx buffer count is less than 4.
* | | |1 = Tx buffer count equals to 4.
* |[11] |CREMOVE |Card Removal Status of SCn_CD Pin
* | | |This bit is set whenever card has been removal.
* | | |0 = No effect.
* | | |1 = Card removed.
* | | |Note1: This bit can be cleared by writing "1" to it.
* | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
* |[12] |CINSERT |Card Insert Status of SCn_CD Pin
* | | |This bit is set whenever card has been inserted.
* | | |0 = No effect.
* | | |1 = Card insert.
* | | |Note1: This bit can be cleared by writing "1" to it.
* | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
* |[13] |CDPINSTS |Card Detect Pin Status (Read Only)
* | | |This bit is the pin status of SCn_CD.
* | | |0 = The SCn_CD pin state at low.
* | | |1 = The SCn_CD pin state at high.
* |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only)
* | | |This field indicates the Rx buffer pointer status
* | | |When SC controller receives one byte from external device, RXPOINT increases one
* | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
* |[21] |RXRERR |Receiver Retry Error
* | | |This bit is used for receiver error retry and set by hardware.
* | | |0 = No Rx retry transfer.
* | | |1 = Rx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
* | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[22] |RXOVERR |Receiver over Retry Error
* | | |This bit is used for receiver retry counts over than retry number limitation.
* | | |0 = Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1.
* | | |1 = Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
* |[23] |RXACT |Receiver in Active Status Flag (Read Only)
* | | |This bit indicates Rx transfer status.
* | | |0 = This bit is cleared automatically when Rx transfer is finished.
* | | |1 = This bit is set by hardware when Rx transfer is in active.
* |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only)
* | | |This field indicates the Tx buffer pointer status
* | | |When CPU writes data into SCn_DAT, TXPOINT increases one
* | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
* |[29] |TXRERR |Transmitter Retry Error
* | | |This bit is used for indicate transmitter error retry and set by hardware..
* | | |0 = No Tx retry transfer.
* | | |1 = Tx has any error and retries transfer.
* | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is a flag and cannot generate any interrupt to CPU.
* |[30] |TXOVERR |Transmitter over Retry Error
* | | |This bit is used for transmitter retry counts over than retry number limitation.
* | | |0 = Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1.
* | | |1 = Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[31] |TXACT |Transmit in Active Status Flag (Read Only)
* | | |This bit indicates Tx transmit status.
* | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed.
* | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted.
* @var SC_T::PINCTL
* Offset: 0x24 SC Pin Control State Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PWREN |SCn_PWR Pin Signal
* | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
* | | |Write this field to drive SCn_PWR pin
* | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
* | | |Read this field to get SCn_PWR signal status.
* | | |0 = SCn_PWR signal status is low.
* | | |1 = SCn_PWR signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[1] |RSTEN |SCn_RST Pin Signal
* | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
* | | |Write this field to drive SCn_RST pin.
* | | |0 = Drive SCn_RST pin to low.
* | | |1 = Drive SCn_RST pin to high.
* | | |Read this field to get SCn_RST signal status.
* | | |0 = SCn_RST signal status is low.
* | | |1 = SCn_RST signal status is high.
* | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[6] |CLKKEEP |SC Clock Enable Bit
* | | |0 = SC clock generation Disabled.
* | | |1 = SC clock always keeps free running.
* | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when operating in these modes.
* |[9] |SCDATA |SCn_DATA Pin Signal
* | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
* | | |0 = Drive SCn_DATA pin to low.
* | | |1 = Drive SCn_DATA pin to high.
* | | |Read this field to get SCn_DATA signal status.
* | | |0 = SCn_DATA signal status is low.
* | | |1 = SCn_DATA signal status is high.
* | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically
* | | |Thus, do not fill in this field when SC is in these modes.
* |[11] |PWRINV |SCn_PWR Pin Inverse
* | | |This bit is used for inverse the SCn_PWR pin.
* | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
* | | |PWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list,
* | | |00 = SCn_PWR pin is 0.
* | | |01 = SCn_PWR pin is 1.
* | | |10 = SCn_PWR pin is 1.
* | | |11 = SCn_PWR pin is 0.
* | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
* |[16] |DATASTS |SCn_DATA Pin Status (Read Only)
* | | |This bit is the pin status of SCn_DATA.
* | | |0 = The SCn_DATA pin status is low.
* | | |1 = The SCn_DATA pin status is high.
* |[17] |PWRSTS |SCn_PWR Pin Status (Read Only)
* | | |This bit is the pin status of SCn_PWR.
* | | |0 = SCn_PWR pin to low.
* | | |1 = SCn_PWR pin to high.
* |[18] |RSTSTS |SCn_RST Pin Status (Read Only)
* | | |This bit is the pin status of SCn_RST.
* | | |0 = SCn_RST pin is low.
* | | |1 = SCn_RST pin is high.
* |[30] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL0
* Offset: 0x28 SC Internal Timer0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer0 Counter Value
* | | |This field indicates the internal Timer0 counter values.
* | | |Note: Unit of Timer0 counter is ETU base.
* |[27:24] |OPMODE |Timer0 Operation Mode Selection
* | | |This field indicates the internal 24-bit Timer0 operation selection.
* | | |Refer to Table 7.14-3 for programming Timer0.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL1
* Offset: 0x2C SC Internal Timer1 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 1 Counter Value
* | | |This field indicates the internal Timer1 counter values.
* | | |Note: Unit of Timer1 counter is ETU base.
* |[27:24] |OPMODE |Timer 1 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer1 operation selection.
* | | |Refer to Table 7.14-3 for programming Timer1.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::TMRCTL2
* Offset: 0x30 SC Internal Timer2 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CNT |Timer 2 Counter Value
* | | |This field indicates the internal Timer2 counter values.
* | | |Note: Unit of Timer2 counter is ETU base.
* |[27:24] |OPMODE |Timer 2 Operation Mode Selection
* | | |This field indicates the internal 8-bit Timer2 operation selection
* | | |Refer to Table 7.14-3 for programming Timer2.
* |[31] |SYNC |SYNC Flag Indicator (Read Only)
* | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
* | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
* | | |1 = Last value is synchronizing.
* @var SC_T::UARTCTL
* Offset: 0x34 SC UART Mode Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |UARTEN |UART Mode Enable Bit
* | | |Sets this bit to enable UART mode function.
* | | |0 = Smart Card mode.
* | | |1 = UART mode.
* | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
* | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
* | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
* |[5:4] |WLS |Word Length Selection
* | | |This field is used for select UART data length.
* | | |00 = Word length is 8 bits.
* | | |01 = Word length is 7 bits.
* | | |10 = Word length is 6 bits.
* | | |11 = Word length is 5 bits.
* | | |Note: In smart card mode, this WLS must be 00.
* |[6] |PBOFF |Parity Bit Disable Bit
* | | |Sets this bit is used for disable parity check function.
* | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
* | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
* | | |Note: In smart card mode, this field must be 0 (default setting is with parity bit).
* |[7] |OPE |Odd Parity Enable Bit
* | | |This is used for odd/even parity selection.
* | | |0 = Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode.
* | | |1 = Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode.
* | | |Note: This bit has effect only when PBOFF bit is 0.
* @var SC_T::ACTCTL
* Offset: 0x4C SC Activation Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4:0] |T1EXT |T1 Extend Time of Hardware Activation
* | | |This field provide the configurable cycles to extend the activation time T1 period.
* | | |The cycle scaling factor is 2048.
* | | |Extend cycles = (filled value * 2048) cycles.
* | | |Refer to SC activation sequence in Figure 7.14-4.
* | | |For example,
* | | |SCLK = 4MHz, each cycle = 0.25us,.
* | | |Filled 20 to this field
* | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
* | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
*/
__IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */
__IO uint32_t CTL; /*!< [0x0004] SC Control Register */
__IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */
__IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */
__IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */
__IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */
__IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */
__IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */
__IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */
__IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */
__IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */
__IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */
__IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */
__IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */
__I uint32_t RESERVE0[5];
__IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */
__I uint32_t RESERVE1[1004];
} SC_T;
/**
@addtogroup SC_CONST SC Bit Field Definition
Constant Definitions for SC Controller
@{ */
#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */
#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */
#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */
#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */
#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */
#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */
#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */
#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */
#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */
#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */
#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */
#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */
#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */
#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */
#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */
#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */
#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */
#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */
#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */
#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */
#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */
#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */
#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */
#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */
#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */
#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */
#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */
#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */
#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */
#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */
#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */
#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */
#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */
#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */
#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */
#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */
#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */
#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */
#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */
#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */
#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */
#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */
#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */
#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */
#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */
#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */
#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */
/**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SC_REG_H__ */

838
board/Nuvoton_M251/STARTUP/Include/spi_reg.h Normal file
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@@ -0,0 +1,838 @@
/**************************************************************************//**
* @file spi_reg.h
* @version V1.00
* @brief SPI register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_REG_H__
#define __SPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup SPI Serial Peripheral Interface Controller (SPI)
Memory Mapped Structure for SPI Controller
@{ */
typedef struct
{
/**
* @var SPI_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SPIEN |SPI Transfer Control Enable Bit
* | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
* | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
* | | |0 = Transfer control Disabled.
* | | |1 = Transfer control Enabled.
* | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
* | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
* | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
* |[3] |CLKPOL |Clock Polarity
* | | |0 = SPI bus clock is idle low.
* | | |1 = SPI bus clock is idle high.
* |[7:4] |SUSPITV |Suspend Interval (Master Only)
* | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 u2026. 0.5 SPICLK clock cycle.
* | | |SUSPITV = 0x1 u2026. 1.5 SPICLK clock cycle.
* | | |u2026u2026
* | | |SUSPITV = 0xE u2026. 14.5 SPICLK clock cycle.
* | | |SUSPITV = 0xF u2026. 15.5 SPICLK clock cycle.
* |[12:8] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can up to 32 bits.
* | | |DWIDTH = 0x08 u2026. 8 bits.
* | | |DWIDTH = 0x09 u2026. 9 bits.
* | | |u2026u2026
* | | |DWIDTH = 0x1F u2026. 31 bits.
* | | |DWIDTH = 0x00 u2026. 32 bits.
* | | |Note: For SPI1, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode
* | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1.
* |[13] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
* |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit
* | | |This bit is used to select full-duplex or half-duplex for SPI transfer
* | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
* | | |0 = SPI operates in full-duplex transfer.
* | | |1 = SPI operates in half-duplex transfer.
* |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only)
* | | |This bit field is only available in Master mode
* | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
* | | |0 = Receive-only mode Disabled.
* | | |1 = Receive-only mode Enabled.
* |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in SPI0)
* | | |0 = 2-bit Transfer mode Disabled.
* | | |1 = 2-bit Transfer mode Enabled.
* | | |Note: When 2-bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
* | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Control
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte Reorder function Disabled.
* | | |1 = Byte Reorder function Enabled
* | | |A byte suspend interval will be inserted among each byte
* | | |The period of the byte suspend interval depends on the setting of SUSPITV.
* | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
* |[20] |DATDIR |Data Port Direction Control
* | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
* | | |0 = SPI data is input direction.
* | | |1 = SPI data is output direction.
* |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
* | | |0 = Dual I/O mode Disabled.
* | | |1 = Dual I/O mode Enabled.
* |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
* | | |0 = Quad I/O mode Disabled.
* | | |1 = Quad I/O mode Enabled.
* @var SPI_T::CLKDIV
* Offset: 0x04 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |DIVIDER |Clock Divider
* | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
* | | |The frequency is obtained according to the following equation.
* | | |where
* | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
* | | |Note: Not supported in I2S mode.
* @var SPI_T::SSCTL
* Offset: 0x08 SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit is cleared to 0,
* | | |0 = set the SPIx_SS line to inactive state.
* | | |1 = set the SPIx_SS line to active state.
* | | |If the AUTOSS bit is set to 1,
* | | |0 = Keep the SPIx_SS line at inactive state.
* | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
* | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |This bit defines the active polarity of slave selection signal (SPIx_SS).
* | | |0 = The slave selection signal SPIx_SS is active low.
* | | |1 = The slave selection signal SPIx_SS is active high.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = Automatic slave selection function Disabled
* | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
* | | |1 = Automatic slave selection function Enabled.
* |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in SPI0)
* | | |Slave 3-wire mode is only available in SPI0
* | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)
* | | |0 = Slave mode time-out interrupt Disabled.
* | | |1 = Slave mode time-out interrupt Enabled.
* |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in SPI0)
* | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
* | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
* |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
* | | |0 = Slave mode bit count error interrupt Disabled.
* | | |1 = Slave mode bit count error interrupt Enabled.
* |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
* | | |0 = Slave mode TX under run interrupt Disabled.
* | | |1 = Slave mode TX under run interrupt Enabled.
* |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
* | | |0 = Slave select active interrupt Disabled.
* | | |1 = Slave select active interrupt Enabled.
* |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |0 = Slave select inactive interrupt Disabled.
* | | |1 = Slave select inactive interrupt Enabled.
* |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in SPI0)
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var SPI_T::PDMACTL
* Offset: 0x0C SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
* | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
* |[1] |RXPDMAEN |Receive PDMA Enable Bit
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[2] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
* @var SPI_T::FIFOCTL
* Offset: 0x10 SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXRST |Receive Reset (Only for SPI)
* | | |0 = No effect.
* | | |1 = Reset receive FIFO pointer and receive circuit
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* |[1] |TXRST |Transmit Reset (Only for SPI)
* | | |0 = No effect.
* | | |1 = Reset transmit FIFO pointer and transmit circuit
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
* | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
* | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
* |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
* | | |0 = RX FIFO threshold interrupt Disabled.
* | | |1 = RX FIFO threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
* | | |0 = TX FIFO threshold interrupt Disabled.
* | | |1 = TX FIFO threshold interrupt Enabled.
* |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit
* | | |0 = Receive time-out interrupt Disabled.
* | | |1 = Receive time-out interrupt Enabled.
* |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = Receive FIFO overrun interrupt Disabled.
* | | |1 = Receive FIFO overrun interrupt Enabled.
* |[6] |TXUFPOL |TX Underflow Data Polarity
* | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
* | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
* | | |Note:
* | | |1
* | | |The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
* | | |2. This bit should be set as 0 in I2S mode.
* | | |3
* | | |When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
* | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
* |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
* | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
* | | |This bit is used to enable the TX underflow interrupt.
* | | |0 = Slave TX underflow interrupt Disabled.
* | | |1 = Slave TX underflow interrupt Enabled.
* |[8] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear receive FIFO pointer
* | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The RX shift register will not be cleared.
* |[9] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = No effect.
* | | |1 = Clear transmit FIFO pointer
* | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
* | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
* | | |Note: The TX shift register will not be cleared.
* |[26:24] |RXTH |Receive FIFO Threshold
* | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
* | | |For SPI1, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
* | | |For SPI1, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length
* @var SPI_T::STATUS
* Offset: 0x14 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSY |Busy Status (Read Only)
* | | |0 = SPI controller is in idle state.
* | | |1 = SPI controller is in busy state.
* | | |The following lists the bus busy conditions:
* | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
* | | |b
* | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
* | | |d
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[1] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[2] |SSACTIF |Slave Select Active Interrupt Flag
* | | |0 = Slave select active interrupt was cleared or not occurred.
* | | |1 = Slave select active interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
* | | |0 = Slave select inactive interrupt was cleared or not occurred.
* | | |1 = Slave select inactive interrupt event occurred.
* | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
* |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* | | |Note: This bit is only available in Slave mode
* | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in SPI0)
* | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started
* | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
* | | |0 = Slave time-out is not active.
* | | |1 = Slave time-out is active.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
* | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
* | | |0 = No Slave mode bit count error event.
* | | |1 = Slave mode bit count error event occurred.
* | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
* | | |This bit will be cleared by writing 1 to it.
* |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
* | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
* | | |0 = No Slave TX under run event.
* | | |1 = Slave TX under run event occurred.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |0 = No FIFO is overrun.
* | | |1 = Receive FIFO is overrun.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |SPIENSTS |SPI Enable Status (Read Only)
* | | |0 = SPI controller Disabled.
* | | |1 = SPI controller Enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* |[19] |TXUFIF |TX Underflow Interrupt Flag
* | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
* | | |0 = No effect.
* | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
* | | |Note 1: This bit will be cleared by writing 1 to it.
* | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* @var SPI_T::TX
* Offset: 0x20 SPI Data Transmit Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Data Transmit Register
* | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
* | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
* | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
* | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
* | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
* | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
* | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
* @var SPI_T::RX
* Offset: 0x30 SPI Data Receive Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Data Receive Register
* | | |There are 4-level FIFO buffers in this controller
* | | |The data receive register holds the data received from SPI data input pin
* | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register
* | | |This is a read only register.
* @var SPI_T::I2SCTL
* Offset: 0x60 I2S Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |I2SEN |I2S Controller Enable Bit
* | | |0 = Disabled I2S mode.
* | | |1 = Enabled I2S mode.
* | | |Note:
* | | |1. If enabling this bit, I2Sx_BCLK will start to output in Master mode.
* | | |2
* | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
* |[1] |TXEN |Transmit Enable Bit
* | | |0 = Data transmit Disabled.
* | | |1 = Data transmit Enabled.
* |[2] |RXEN |Receive Enable Bit
* | | |0 = Data receive Disabled.
* | | |1 = Data receive Enabled.
* |[3] |MUTE |Transmit Mute Enable Bit
* | | |0 = Transmit data is shifted from buffer.
* | | |1 = Transmit channel zero.
* |[5:4] |WDWIDTH |Word Width
* | | |00 = data size is 8-bit.
* | | |01 = data size is 16-bit.
* | | |10 = data size is 24-bit.
* | | |11 = data size is 32-bit.
* |[6] |MONO |Monaural Data
* | | |0 = Data is stereo format.
* | | |1 = Data is monaural format.
* |[7] |ORDER |Stereo Data Order in FIFO
* | | |0 = Left channel data at high byte.
* | | |1 = Left channel data at low byte.
* |[8] |SLAVE |Slave Mode
* | | |I2S can operate as master or slave
* | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip
* | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[15] |MCLKEN |Master Clock Enable Bit
* | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
* | | |0 = Master clock Disabled.
* | | |1 = Master clock Enabled.
* |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Right channel zero cross detection Disabled.
* | | |1 = Right channel zero cross detection Enabled.
* |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
* | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
* | | |This function is only available in transmit operation.
* | | |0 = Left channel zero cross detection Disabled.
* | | |1 = Left channel zero cross detection Enabled.
* |[23] |RXLCH |Receive Left Channel Enable Bit
* | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
* | | |0 = Receive right channel data in Mono mode.
* | | |1 = Receive left channel data in Mono mode.
* |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit
* | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* |[29:28] |FORMAT |Data Format Selection
* | | |00 = I2S data format.
* | | |01 = MSB justified data format.
* | | |10 = PCM mode A.
* | | |11 = PCM mode B.
* |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode
* | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs.
* | | |0 = Interrupt Disabled.
* | | |1 = Interrupt Enabled.
* @var SPI_T::I2SCLK
* Offset: 0x64 I2S Clock Divider Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |MCLKDIV |Master Clock Divider
* | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices
* | | |The frequency of master clock, fMCLK, is determined by the following expressions:
* | | |If MCLKDIV >= 1,.
* | | |If MCLKDIV = 0,.
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2
* | | |In general, the master clock rate is 256 times sampling clock rate.
* |[17:8] |BCLKDIV |Bit Clock Divider
* | | |The I2S controller will generate bit clock in Master mode
* | | |The clock frequency of bit clock , fBCLK, is determined by the following expression:
* | | |where
* | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
* | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by .
* | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
* @var SPI_T::I2SSTS
* Offset: 0x68 I2S Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[4] |RIGHT |Right Channel (Read Only)
* | | |This bit indicates the current transmit data is belong to which channel.
* | | |0 = Left channel.
* | | |1 = Right channel.
* |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not empty.
* | | |1 = Receive FIFO buffer is empty.
* |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Receive FIFO buffer is not full.
* | | |1 = Receive FIFO buffer is full.
* |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
* | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
* | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = No receive FIFO time-out event.
* | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
* | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[15] |I2SENSTS |I2S Enable Status (Read Only)
* | | |0 = The SPI/I2S control logic is disabled.
* | | |1 = The SPI/I2S control logic is enabled.
* | | |Note: The SPI peripheral clock is asynchronous with the system clock
* | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
* |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not empty.
* | | |1 = Transmit FIFO buffer is empty.
* |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmit FIFO buffer is not full.
* | | |1 = Transmit FIFO buffer is full.
* |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
* | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
* | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
* |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
* | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on right channel.
* | | |1 = Zero cross event occurred on right channel.
* |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
* | | |0 = No zero cross event occurred on left channel.
* | | |1 = Zero cross event occurred on left channel.
* |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode
* | | |0 = No bit clock loss event occurred.
* | | |1 = Bit clock loss event occurred.
* | | |This bit will be cleared by writing 1 to it.
* |[23] |TXRXRST |TX or RX Reset Status (Read Only)
* | | |0 = The reset function of TXRST or RXRST is done.
* | | |1 = Doing the reset function of TXRST or RXRST.
* | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
* | | |User can check the status of this bit to monitor the reset function is doing or done.
* |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */
__IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */
__IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */
__I uint32_t RESERVE0[2];
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
__I uint32_t RESERVE2[11];
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */
} SPI_T;
/**
@addtogroup SPI_CONST SPI Bit Field Definition
Constant Definitions for SPI Controller
@{ */
#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */
#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */
#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */
#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */
#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */
#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */
#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */
#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */
#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */
#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */
#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
/**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __SPI_REG_H__ */

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/**************************************************************************//**
* @file system_M251.h
* @version V0.10
* @brief System Setting Header File
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
****************************************************************************/
#ifndef __SYSTEM_M251_H__
#define __SYSTEM_M251_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
#define __LIRC (38400UL) /*!< Internal 38.4KHz RC Oscillator Frequency */
#define __MIRC (4032000UL) /*!< Internal 4.032M RC Oscillator Frequency */
#define __HIRC (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
#define __HSI (48000000UL) /*!< PLL default output is 48MHz */
#define __SYS_OSC_CLK ( ___HSI) /*!< Main oscillator frequency */
#define __SYSTEM_CLOCK (1UL*__HXT)
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the micro controller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
/**
* Set UART0 default multi function pin
*
* @param none
* @return none
*
* @brief The initialization of uart0 default multiple-function pin.
*/
extern void Uart0DefaultMPF(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_M251_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file timer_reg.h
* @version V1.00
* @brief TIMER register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TIMER_REG_H__
#define __TIMER_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup TIMER Timer Controller (TIMER)
Memory Mapped Structure for TIMER Controller
@{ */
typedef struct
{
/**
* @var TIMER_T::CTL
* Offset: 0x00 Timer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PSC |Prescale Counter
* | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
* | | |If this field is 0 (PSC = 0), then there is no scaling.
* | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
* |[15] |FUNCSEL |Function Selection
* | | |0 = Timer controller is used as timer function.
* | | |1 = Timer controller is used as PWM function.
* | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
* |[19] |INTRGEN |Inter-timer Trigger Mode Enable Bit
* | | |Setting this bit will enable the inter-timer trigger capture function.
* | | |The Timer0/2 will be in event counter mode and counting with external clock source or event
* | | |Also, Timer1/3 will be in trigger-counting mode of capture function.
* | | |0 = Inter-Timer Trigger Capture mode Disabled.
* | | |1 = Inter-Timer Trigger Capture mode Enabled.
* | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
* |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit
* | | |0 = The behavior selection in periodic mode is Disabled.
* | | |When user updates CMPDAT while timer is running in periodic mode,
* | | |CNT will be reset to default value.
* | | |1 = The behavior selection in periodic mode is Enabled.
* | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
* | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
* | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted.
* | | |If updated CMPDAT value < CNT, CNT will be reset to default value.
* |[21] |TGLPINSEL |Toggle-output Pin Select
* | | |0 = Toggle mode output to TMx (Timer Event Counter Pin).
* | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
* |[22] |CAPSRC |Capture Pin Source Selection
* | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
* | | |1 = Capture Function source is from internal ACMP output signal, internal clock (MIRC, LIRC, HIRC), or external clock (HXT, LXT).
* | | |Note: When CAPSRC = 1, User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source.
* |[23] |WKEN |Wake-up Function Enable Bit
* | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
* | | |0 = Wake-up function Disabled if timer interrupt signal generated.
* | | |1 = Wake-up function Enabled if timer interrupt signal generated.
* |[24] |EXTCNTEN |Event Counter Mode Enable Bit
* | | |This bit is for external counting pin function enabled.
* | | |0 = Event counter mode Disabled.
* | | |1 = Event counter mode Enabled.
* | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
* |[25] |ACTSTS |Timer Active Status Bit (Read Only)
* | | |This bit indicates the 24-bit up counter status.
* | | |0 = 24-bit up counter is not active.
* | | |1 = 24-bit up counter is active.
* | | |Note: This bit may active when CNT 0 transition to CNT 1.
* |[28:27] |OPMODE |Timer Counting Mode Select
* | | |00 = The timer controller is operated in One-shot mode.
* | | |01 = The timer controller is operated in Periodic mode.
* | | |10 = The timer controller is operated in Toggle-output mode.
* | | |11 = The timer controller is operated in Continuous Counting mode.
* |[29] |INTEN |Timer Interrupt Enable Bit
* | | |0 = Timer time-out interrupt Disabled.
* | | |1 = Timer time-out interrupt Enabled.
* | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
* |[30] |CNTEN |Timer Counting Enable Bit
* | | |0 = Stops/Suspends counting.
* | | |1 = Starts counting.
* | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
* | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
* | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
* | | |0 = ICE debug mode acknowledgement effects TIMER counting.
* | | |TIMER counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |TIMER counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var TIMER_T::CMP
* Offset: 0x04 Timer Comparator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CMPDAT |Timer Comparator Value
* | | |CMPDAT is a 24-bit compared value register
* | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
* | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
* | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
* | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field
* | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
* @var TIMER_T::INTSTS
* Offset: 0x08 Timer Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TIF |Timer Interrupt Flag
* | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
* | | |0 = No effect.
* | | |1 = CNT value matches the CMPDAT value.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |TWKF |Timer Wake-up Flag
* | | |This bit indicates the interrupt wake-up flag status of timer.
* | | |0 = Timer does not cause CPU wake-up.
* | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
* | | |Note: This bit is cleared by writing 1 to it.
* @var TIMER_T::CNT
* Offset: 0x0C Timer Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Timer Data Register
* | | |Read operation.
* | | |Read this register to get CNT value. For example:
* | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
* | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
* | | |Write operation.
* | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
* |[31] |RSTACT |Timer Data Register Reset Active (Read Only)
* | | |This bit indicates if the counter reset operation active.
* | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter
* | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress
* | | |Once the counter reset operation done, timer clear this bit to 0 automatically.
* | | |0 = Reset operation is done.
* | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress.
* @var TIMER_T::CAP
* Offset: 0x10 Timer Capture Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CAPDAT |Timer Capture Data Register
* | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
* @var TIMER_T::EXTCTL
* Offset: 0x14 Timer External Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTPHASE |Timer External Count Phase
* | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
* | | |0 = A falling edge of external counting pin will be counted.
* | | |1 = A rising edge of external counting pin will be counted.
* |[3] |CAPEN |Timer Capture Enable Bit
* | | |This bit enables the capture input function.
* | | |0 =Capture source Disabled.
* | | |1 =Capture source Enabled.
* | | |Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source.
* |[4] |CAPFUNCS |Capture Function Selection
* | | |0 = External Capture Mode Enabled.
* | | |1 = External Reset Mode Enabled.
* | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
* | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
* |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit
* | | |0 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled.
* | | |1 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled.
* | | |Note: CAPIEN is used to enable timer external interrupt
* | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
* | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
* |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit
* | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
* | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
* | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
* |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit
* | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
* | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
* | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
* |[10:8] |INTERCAPSEL|Internal Capture Source Select
* | | |000 = Capture Function source is from internal ACMP0 output signal.
* | | |001 = Capture Function source is from internal ACMP1 output signal.
* | | |010 = Capture Function source is from HXT.
* | | |011 = Capture Function source is from LXT.
* | | |100 = Capture Function source is from HIRC.
* | | |101 = Capture Function source is from LIRC.
* | | |110 = Capture Function source is from MIRC.
* | | |111 = Reserved.
* | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
* |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect
* | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
* | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
* | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
* | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.
* | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.
* | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
* | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
* | | |100, 101 = Reserved.
* | | |Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
* |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function
* | | |0 = Event Counter input source is from TMx (x= 0~3) pin.
* | | |1 = Event Counter input source is from USB internal SOF output signal.
* |[31:28] |CAPDIVSCL |Timer Capture Source Divider Scale
* | | |This bits indicate the divide scale for capture source divider
* | | |0000 = Capture source/1.
* | | |0001 = Capture source/2.
* | | |0010 = Capture source/4.
* | | |0011 = Capture source/8.
* | | |0100 = Capture source/16.
* | | |0101 = Capture source/32.
* | | |0110 = Capture source/64.
* | | |0111 = Capture source/128.
* | | |1000 = Capture source/256.
* | | |1001~1111 = Reserved.
* | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
* @var TIMER_T::EINTSTS
* Offset: 0x18 Timer External Interrupt Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPIF |Timer External Capture Interrupt Flag
* | | |This bit indicates the timer external capture interrupt flag status.
* | | |0 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur.
* | | |1 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred.
* | | |Note1: This bit is cleared by writing 1 to it.
* | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
* | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status
* | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
* @var TIMER_T::TRGCTL
* Offset: 0x1C Timer Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TRGSSEL |Trigger Source Select Bit
* | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
* | | |0 = Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.
* | | |1 = Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.
* |[1] |TRGPWM |Trigger PWM/BPWM Enable Bit
* | | |If this bit is set to 1, each timer time-out event or capture event can be as PWM/BPWM counter clock source.
* | | |0 = Timer interrupt trigger PWM/BPWM Disabled.
* | | |1 = Timer interrupt trigger PWM/BPWM Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM/BPWM counter clock source.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM/BPWM counter clock source.
* |[2] |TRGEADC |Trigger EADC Enable Bit
* | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
* | | |0 = Timer interrupt trigger EADC Disabled.
* | | |1 = Timer interrupt trigger EADC Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger ADC conversion.
* |[3] |TRGDAC |Trigger DAC Enable Bit
* | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
* | | |0 = Timer interrupt trigger DAC Disabled.
* | | |1 = Timer interrupt trigger DAC Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
* |[4] |TRGPDMA |Trigger PDMA Enable Bit
* | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
* | | |0 = Timer interrupt trigger PDMA Disabled.
* | | |1 = Timer interrupt trigger PDMA Enabled.
* | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
* | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
* @var TIMER_T::PWMCTL
* Offset: 0x40 Timer PWM Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTEN |PWM Counter Enable Bit
* | | |0 = PWM counter and clock prescale Stop Running.
* | | |1 = PWM counter and clock prescale Start Running.
* |[3] |CNTMODE |PWM Counter Mode
* | | |0 = Auto-reload mode.
* | | |1 = One-shot mode.
* |[12] |PWMINTWKEN|PWM Interrupt Wake-up Enable
* | | |If PWM interrupt occurs when chip is at power down mode, PWMINTWKEN can determine whether chip wake-up occurs or not.
* | | |0 = PWM interrupt wake-up disable.
* | | |1 = PWM interrupt wake-up enable.
* |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
* | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
* | | |0 = ICE debug mode counter halt disable.
* | | |1 = ICE debug mode counter halt enable.
* | | |Note: This bit is write protected. Refer toSYS_REGLCTL register.
* |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
* | | |0 = ICE debug mode acknowledgement effects PWM output.
* | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
* | | |1 = ICE debug mode acknowledgement disabled.
* | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not.
* | | |Note: This bit is write protected. Refer toSYS_REGLCTL register.
* @var TIMER_T::PWMCLKPSC
* Offset: 0x44 Timer PWM Counter Clock Pre-scale Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |CLKPSC |PWM Counter Clock Pre-scale
* | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)
* | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source.
* @var TIMER_T::PWMCNTCLR
* Offset: 0x48 Timer PWM Clear Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTCLR |Clear PWM Counter Control Bit
* | | |It is automatically cleared by hardware.
* | | |0 = No effect.
* | | |1 = Clear 16-bit PWM counter to 0x00000 in up count type.
* | | |Note: Timer peripheral clock source should be set as PCLK to ensure that this bit can automatically cleared by hardware.
* @var TIMER_T::PWMPERIOD
* Offset: 0x4C Timer PWM Period Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PERIOD |PWM Period Register
* | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
* | | |In up count type:
* | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
* @var TIMER_T::PWMCMPDAT
* Offset: 0x50 Timer PWM Comparator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMP |PWM Comparator Register
* | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC starting converting.
* @var TIMER_T::PWMCNT
* Offset: 0x54 Timer PWM Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CNT |PWM Counter Value Register (Read Only)
* | | |User can monitor CNT to know the current counter value in 16-bit period counter.
* @var TIMER_T::PWMPOLCTL
* Offset: 0x58 Timer PWM Pin Output Polar Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PINV |PWMx Output Pin Polar Control Bit
* | | |The bit is used to control polarity state of PWMx_OUT pin.
* | | |0 = PWMx_OUT pin polar inverse Disabled.
* | | |1 = PWMx_OUT polar inverse Enabled.
* | | |Note: Sets POSEL (TIMERx_PWMPOCTL[8]) to select Tx or Tx_EXT as PWMx output pin.
* @var TIMER_T::PWMPOCTL
* Offset: 0x5C Timer PWM Pin Output Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |POEN |PWMx Output Pin Enable Bit
* | | |0 = PWMx_OUT pin at tri-state mode.
* | | |1 = PWMx_OUT pin in output mode.
* | | |Note: Sets POSEL (TIMERx_PWMPOCTL[8]) to select Tx or Tx_EXT as PWMx output pin.
* |[8] |POSEL |PWM Output Pin Select
* | | |0 = PWMx_OUT pin is Tx.
* | | |1 = PWMx_OUT pin is Tx_EXT.
* @var TIMER_T::PWMINTEN0
* Offset: 0x60 Timer PWM Interrupt Enable Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |PIEN |PWM Period Point Interrupt Enable Bit
* | | |0 = Period point interrupt Disabled.
* | | |1 = Period point interrupt Enabled.
* |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit
* | | |0 = Compare up count interrupt Disabled.
* | | |1 = Compare up count interrupt Enabled.
* @var TIMER_T::PWMINTSTS0
* Offset: 0x64 Timer PWM Interrupt Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |PIF |PWM Period Point Interrupt Flag
* | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
* | | |Note: This bit is cleared by writing 1 to it.
* |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag
* | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
* | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type.
* | | |Note2: This bit is cleared by writing 1 to it.
* @var TIMER_T::PWMTRGCTL
* Offset: 0x68 Timer PWM Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion
* | | |00 = Trigger conversion at period point (PIF).
* | | |01 = Trigger conversion at compare up count point (CMPUIF).
* | | |10 = Trigger conversion at period or compare up count point (PIF or CMPUIF).
* | | |11 = Reserved.
* |[7] |PWMTRGEADC|PWM Counter Event Trigger EADC Conversion Enable Bit
* | | |0 = PWM counter event trigger EADC conversion Disabled.
* | | |1 = PWM counter event trigger EADC conversion Enabled.
* | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
* |[8] |PWMTRGDAC |PWM Counter Event Trigger DAC Conversion Enable Bit
* | | |If this bit is set to 1, PWM can trigger DAC conversion.
* | | |0 = PWM trigger DAC Disabled.
* | | |1 = PWM trigger DAC Enabled.
* | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
* |[9] |PWMTRGPDMA|PWM Counter Event Trigger PDMA Conversion Enable Bit
* | | |If this bit is set to 1, PWM can trigger PDMA conversion.
* | | |0 = PWM trigger PDMA Disabled.
* | | |1 = PWM trigger PDMA Enabled.
* | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
* @var TIMER_T::PWMSTATUS
* Offset: 0x6C Timer PWM Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag
* | | |0 = The PWM counter value never reached its maximum value 0xFFFF.
* | | |1 = The PWM counter value has reached its maximum value.
* | | |Note: This bit is cleared by writing 1 to it.
* |[8] |PWMINTWKF |PWM Interrupt Wake-up Flag
* | | |0 = PWM interrupt wake-up is not occurred.
* | | |1 = PWM interrupt wake-up has occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[16] |EADCTRGF |Trigger EADC Start Conversion Flag
* | | |0 = PWM counter event trigger EADC start conversion is not occurred.
* | | |1 = PWM counter event trigger EADC start conversion has occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[17] |DACTRGF |Trigger DAC Start Conversion Flag
* | | |0 = PWM counter event trigger DAC start conversion is not occurred.
* | | |1 = PWM counter event trigger DAC start conversion has occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[18] |PDMATRGF |Trigger PDMA Start Conversion Flag
* | | |0 = PWM counter event trigger PDMA start conversion is not occurred.
* | | |1 = PWM counter event trigger PDMA start conversion has occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var TIMER_T::PWMPBUF
* Offset: 0x70 Timer PWM Period Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |PBUF |PWM Period Buffer Register (Read Only)
* | | |Used as PERIOD active register.
* @var TIMER_T::PWMCMPBUF
* Offset: 0x74 Timer PWM Comparator Buffer Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only)
* | | |Used as CMP active register.
*/
__IO uint32_t CTL; /*!< [0x0000] Timer Control Register */
__IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */
__IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */
__IO uint32_t CNT; /*!< [0x000c] Timer Data Register */
__I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */
__IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */
__IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */
__IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */
__I uint32_t RESERVE0[8];
__IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */
__IO uint32_t PWMCLKPSC; /*!< [0x0044] Timer PWM Counter Clock Pre-scale Register */
__IO uint32_t PWMCNTCLR; /*!< [0x0048] Timer PWM Clear Counter Register */
__IO uint32_t PWMPERIOD; /*!< [0x004c] Timer PWM Period Register */
__IO uint32_t PWMCMPDAT; /*!< [0x0050] Timer PWM Comparator Register */
__I uint32_t PWMCNT; /*!< [0x0054] Timer PWM Counter Register */
__IO uint32_t PWMPOLCTL; /*!< [0x0058] Timer PWM Pin Output Polar Control Register */
__IO uint32_t PWMPOCTL; /*!< [0x005c] Timer PWM Pin Output Control Register */
__IO uint32_t PWMINTEN0; /*!< [0x0060] Timer PWM Interrupt Enable Register 0 */
__IO uint32_t PWMINTSTS0; /*!< [0x0064] Timer PWM Interrupt Status Register 0 */
__IO uint32_t PWMTRGCTL; /*!< [0x0068] Timer PWM Trigger Control Register */
__IO uint32_t PWMSTATUS; /*!< [0x006c] Timer PWM Status Register */
__I uint32_t PWMPBUF; /*!< [0x0070] Timer PWM Period Buffer Register */
__I uint32_t PWMCMPBUF; /*!< [0x0074] Timer PWM Comparator Buffer Register */
} TIMER_T;
/**
@addtogroup TIMER_CONST TIMER Bit Field Definition
Constant Definitions for TIMER Controller
@{ */
#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
#define TIMER_CTL_FUNCSEL_Pos (15) /*!< TIMER_T::CTL: FUNCSEL Position */
#define TIMER_CTL_FUNCSEL_Msk (0x1ul << TIMER_CTL_FUNCSEL_Pos) /*!< TIMER_T::CTL: FUNCSEL Mask */
#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */
#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */
#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */
#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */
#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */
#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */
#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */
#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */
#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */
#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
#define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */
#define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */
#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */
#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */
#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */
#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */
#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */
#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */
#define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */
#define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */
#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */
#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */
#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */
#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */
#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */
#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */
#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */
#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */
#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */
#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */
#define TIMER_PWMCTL_PWMINTWKEN_Pos (12) /*!< TIMER_T::PWMCTL: PWMINTWKEN Position */
#define TIMER_PWMCTL_PWMINTWKEN_Msk (0x1ul << TIMER_PWMCTL_PWMINTWKEN_Pos) /*!< TIMER_T::PWMCTL: PWMINTWKEN Mask */
#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */
#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */
#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */
#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */
#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */
#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xfful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */
#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */
#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */
#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */
#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */
#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */
#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */
#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */
#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */
#define TIMER_PWMPOLCTL_PINV_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV Position */
#define TIMER_PWMPOLCTL_PINV_Msk (0x1ul << TIMER_PWMPOLCTL_PINV_Pos) /*!< TIMER_T::PWMPOLCTL: PINV Mask */
#define TIMER_PWMPOCTL_POEN_Pos (0) /*!< TIMER_T::PWMPOCTL: POEN Position */
#define TIMER_PWMPOCTL_POEN_Msk (0x1ul << TIMER_PWMPOCTL_POEN_Pos) /*!< TIMER_T::PWMPOCTL: POEN Mask */
#define TIMER_PWMPOCTL_POSEL_Pos (8) /*!< TIMER_T::PWMPOCTL: POSEL Position */
#define TIMER_PWMPOCTL_POSEL_Msk (0x1ul << TIMER_PWMPOCTL_POSEL_Pos) /*!< TIMER_T::PWMPOCTL: POSEL Mask */
#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */
#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */
#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */
#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */
#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */
#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */
#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */
#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */
#define TIMER_PWMTRGCTL_TRGSEL_Pos (0) /*!< TIMER_T::PWMTRGCTL: TRGSEL Position */
#define TIMER_PWMTRGCTL_TRGSEL_Msk (0x3ul << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask */
#define TIMER_PWMTRGCTL_PWMTRGEADC_Pos (7) /*!< TIMER_T::PWMTRGCTL: PWMTRGEADC Position*/
#define TIMER_PWMTRGCTL_PWMTRGEADC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGEADC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGEADC Mask */
#define TIMER_PWMTRGCTL_PWMTRGDAC_Pos (8) /*!< TIMER_T::PWMTRGCTL: PWMTRGDAC Position */
#define TIMER_PWMTRGCTL_PWMTRGDAC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGDAC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGDAC Mask */
#define TIMER_PWMTRGCTL_PWMTRGPDMA_Pos (9) /*!< TIMER_T::PWMTRGCTL: PWMTRGPDMA Position*/
#define TIMER_PWMTRGCTL_PWMTRGPDMA_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGPDMA_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGPDMA Mask */
#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */
#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */
#define TIMER_PWMSTATUS_PWMINTWKF_Pos (8) /*!< TIMER_T::PWMSTATUS: PWMINTWKF Position */
#define TIMER_PWMSTATUS_PWMINTWKF_Msk (0x1ul << TIMER_PWMSTATUS_PWMINTWKF_Pos) /*!< TIMER_T::PWMSTATUS: PWMINTWKF Mask */
#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */
#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */
#define TIMER_PWMSTATUS_DACTRGF_Pos (17) /*!< TIMER_T::PWMSTATUS: DACTRGF Position */
#define TIMER_PWMSTATUS_DACTRGF_Msk (0x1ul << TIMER_PWMSTATUS_DACTRGF_Pos) /*!< TIMER_T::PWMSTATUS: DACTRGF Mask */
#define TIMER_PWMSTATUS_PDMATRGF_Pos (18) /*!< TIMER_T::PWMSTATUS: PDMATRGF Position */
#define TIMER_PWMSTATUS_PDMATRGF_Msk (0x1ul << TIMER_PWMSTATUS_PDMATRGF_Pos) /*!< TIMER_T::PWMSTATUS: PDMATRGF Mask */
#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */
#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */
#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */
#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */
/**@}*/ /* TIMER_CONST */
/**@}*/ /* end of TIMER register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __TIMER_REG_H__ */

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/**************************************************************************//**
* @file ui2c_reg.h
* @version V1.00
* @brief UI2C register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UI2C_REG_H__
#define __UI2C_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup UI2C I2C Mode of USCI Controller (UI2C)
Memory Mapped Structure for UI2C Controller
@{ */
typedef struct
{
/**
* @var UI2C_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var UI2C_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK = fDIV_CLK.
* | | |01 = fSAMP_CLK = fPROT_CLK.
* | | |10 = fSAMP_CLK = fSCLK.
* | | |11 = fSAMP_CLK = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UI2C_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits
* | | |And in I2C protocol, the length fixed as 8 bits.
* @var UI2C_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UI2C_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
* | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]).
* @var UI2C_T::DEVADDR0
* Offset: 0x44 USCI Device Address Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
* | | |Note 2: When software set 10'h000, the address can not be used.
* @var UI2C_T::DEVADDR1
* Offset: 0x48 USCI Device Address Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |DEVADDR |Device Address
* | | |In I2C protocol, this bit field contains the programmed slave address
* | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
* | | |Then the second address byte is also compared to DEVADDR[7:0].
* | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
* | | |Note 2: When software set 10'h000, the address can not be used.
* @var UI2C_T::ADDRMSK0
* Offset: 0x4C USCI Device Address Mask Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var UI2C_T::ADDRMSK1
* Offset: 0x50 USCI Device Address Mask Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |ADDRMSK |USCI Device Address Mask
* | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
* | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
* | | |USCI support multiple address recognition with two address mask register
* | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
* | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
* | | |Note: The wake-up function can not use address mask.
* @var UI2C_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* @var UI2C_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UI2C_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GCFUNC |General Call Function
* | | |0 = General Call Function Disabled.
* | | |1 = General Call Function Enabled.
* |[1] |AA |Assert Acknowledge Control
* | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
* | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
* |[2] |STO |I2C STOP Control
* | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
* | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (UI2C_PROTSTS.ERRIF = 1).
* |[3] |STA |I2C START Control
* | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
* |[4] |ADDR10EN |Address 10-bit Function Enable Bit
* | | |0 = Address match 10 bit function is disabled.
* | | |1 = Address match 10 bit function is enabled.
* |[5] |PTRG |I2C Protocol Trigger (Write Only)
* | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
* | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
* | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
* | | |1 = I2C's stretch active.
* |[8] |SCLOUTEN |SCL Output Enable Bit
* | | |This bit enables monitor pulling SCL to low
* | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
* | | |0 = SCL output will be forced high due to open drain mechanism.
* | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
* |[9] |MONEN |Monitor Mode Enable Bit
* | | |This bit enables monitor mode
* | | |In monitor mode the SDA output will be put in high impedance mode
* | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
* | | |0 = The monitor mode is disabled.
* | | |1 = The monitor mode is enabled.
* | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
* |[25:16] |TOCNT |Time-out Clock Cycle
* | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear
* | | |The time-out is enable when TOCNT bigger than 0.
* | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
* |[31] |PROTEN |I2C Protocol Enable Bit
* | | |0 = I2C Protocol disable.
* | | |1 = I2C Protocol enable.
* @var UI2C_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TOIEN |Time-out Interrupt Enable Control
* | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
* | | |0 = The time-out interrupt is disabled.
* | | |1 = The time-out interrupt is enabled.
* |[1] |STARIEN |Start Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a start condition is detected.
* | | |0 = The start condition interrupt is disabled.
* | | |1 = The start condition interrupt is enabled.
* |[2] |STORIEN |Stop Condition Received Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.
* | | |0 = The stop condition interrupt is disabled.
* | | |1 = The stop condition interrupt is enabled.
* |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
* | | |0 = The non - acknowledge interrupt is disabled.
* | | |1 = The non - acknowledge interrupt is enabled.
* |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
* | | |0 = The arbitration lost interrupt is disabled.
* | | |1 = The arbitration lost interrupt is enabled.
* |[5] |ERRIEN |Error Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
* | | |0 = The error interrupt is disabled.
* | | |1 = The error interrupt is enabled.
* |[6] |ACKIEN |Acknowledge Interrupt Enable Control
* | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
* | | |0 = The acknowledge interrupt is disabled.
* | | |1 = The acknowledge interrupt is enabled.
* @var UI2C_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5] |TOIF |Time-out Interrupt Flag
* | | |0 = A time-out interrupt status has not occurred.
* | | |1 = A time-out interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit
* |[6] |ONBUSY |On Bus Busy
* | | |Indicates that a communication is in progress on the bus
* | | |It is set by hardware when a START condition is detected
* | | |It is cleared by hardware when a STOP condition is detected
* | | |0 = The bus is IDLE (both SCLK and SDA High).
* | | |1 = The bus is busy.
* |[8] |STARIF |Start Condition Received Interrupt Flag
* | | |This bit indicates that a start condition or repeated start condition has been detected on master mode
* | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1.
* | | |0 = A start condition has not yet been detected.
* | | |1 = A start condition has been detected.
* | | |It is cleared by software writing one into this bit
* |[9] |STORIF |Stop Condition Received Interrupt Flag
* | | |This bit indicates that a stop condition has been detected on the I2C bus lines
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1.
* | | |0 = A stop condition has not yet been detected.
* | | |1 = A stop condition has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave RX mode.
* |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
* | | |This bit indicates that a non - acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1.
* | | |0 = A non - acknowledge has not been received.
* | | |1 = A non - acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
* | | |This bit indicates that an arbitration has been lost
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1.
* | | |0 = An arbitration has not been lost.
* | | |1 = An arbitration has been lost.
* | | |It is cleared by software writing one into this bit
* |[12] |ERRIF |Error Interrupt Flag
* | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
* | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1.
* | | |0 = An I2C error has not been detected.
* | | |1 = An I2C error has been detected.
* | | |It is cleared by software writing one into this bit
* | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode.
* |[13] |ACKIF |Acknowledge Received Interrupt Flag
* | | |This bit indicates that an acknowledge has been received in master mode
* | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1.
* | | |0 = An acknowledge has not been received.
* | | |1 = An acknowledge has been received.
* | | |It is cleared by software writing one into this bit
* |[14] |SLASEL |Slave Select Status
* | | |This bit indicates that this device has been selected as slave.
* | | |0 = The device is not selected as slave.
* | | |1 = The device is selected as slave.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[15] |SLAREAD |Slave Read Request Status
* | | |This bit indicates that a slave read request has been detected.
* | | |0 = A slave R/W bit is 1 has not been detected.
* | | |1 = A slave R/W bit is 1 has been detected.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
* |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
* | | |0 = The ACK bit cycle of address match frame isn't done.
* | | |1 = The ACK bit cycle of address match frame is done in power-down.
* | | |Note: This bit can't release when WKUPIF is set.
* |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
* | | |0 = Write command be record on the address match wakeup frame.
* | | |1 = Read command be record on the address match wakeup frame.
* |[18] |BUSHANG |Bus Hang-up
* | | |This bit indicates bus hang-up status
* | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
* | | |The hang-up counter will count to overflow and set this bit when SDA is low
* | | |The counter will be reset by falling edge of SCL signal.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is hang-up status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* |[19] |ERRARBLO |Error Arbitration Lost
* | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
* | | |The I2C can send start condition when ERRARBLO is set
* | | |Thus this bit doesn't be cared on slave mode.
* | | |0 = The bus is normal status for transmission.
* | | |1 = The bus is error arbitration lost status for transmission.
* | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
* @var UI2C_T::ADMAT
* Offset: 0x88 I2C Slave Match Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |ADMAT0 |USCI Address 0 Match Status Register
* | | |When address 0 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* |[1] |ADMAT1 |USCI Address 1 Match Status Register
* | | |When address 1 is matched, hardware will inform which address used
* | | |This bit will set to 1, and software can write 1 to clear this bit.
* @var UI2C_T::TMCTL
* Offset: 0x8C I2C Timing Configure Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |STCTL |Setup Time Configure Control Register
* | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
* | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
* |[24:16] |HTCTL |Hold Time Configure Control Register
* | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
* | | |transmission mode.
* | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__I uint32_t RESERVE0[1];
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
__I uint32_t RESERVE1[8];
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__I uint32_t RESERVE2[3];
__IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
__IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
__IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
__IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
__I uint32_t RESERVE3[8];
__IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
__IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
} UI2C_T;
/**
@addtogroup UI2C_CONST UI2C Bit Field Definition
Constant Definitions for UI2C Controller
@{ */
#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
/**@}*/ /* UI2C_CONST */
/**@}*/ /* end of UI2C register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __UI2C_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/usbd_reg.h Normal file
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/**************************************************************************//**
* @file usbd_reg.h
* @version V1.00
* @brief USBD register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USBD_REG_H__
#define __USBD_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup USBD USB Device Controller (USBD)
Memory Mapped Structure for USBD Controller
@{ */
typedef struct
{
/**
* @var USBD_EP_T::BUFSEG
* Offset: 0x000 Endpoint n Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |BUFSEG |Endpoint Buffer Segmentation
* | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
* | | |USBD_SRAM address + { BUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description.
* @var USBD_EP_T::MXPLD
* Offset: 0x004 Endpoint n Maximal Payload Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:0] |MXPLD |Maximal Payload
* | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
* | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
* | | |(1) When the register is written by CPU,
* | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
* | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
* | | |(2) When the register is read by CPU,
* | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
* | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
* | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
* @var USBD_EP_T::CFG
* Offset: 0x008 Endpoint n Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPNUM |Endpoint Number
* | | |These bits are used to define the endpoint number of the current endpoint
* |[4] |ISOCH |Isochronous Endpoint
* | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
* | | |0 = No Isochronous endpoint.
* | | |1 = Isochronous endpoint.
* |[6:5] |STATE |Endpoint STATE
* | | |00 = Endpoint is Disabled.
* | | |01 = Out endpoint.
* | | |10 = IN endpoint.
* | | |11 = Undefined.
* |[7] |DSQSYNC |Data Sequence Synchronization
* | | |0 = DATA0 PID.
* | | |1 = DATA1 PID.
* | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
* | | |hardware will toggle automatically in IN token base on the bit.
* |[9] |CSTALL |Clear STALL Response
* | | |0 = Disable the device to clear the STALL handshake in setup stage.
* | | |1 = Clear the device to response STALL handshake in setup stage.
* @var USBD_EP_T::CFGP
* Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CLRRDY |Clear Ready
* | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
* | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
* | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
* | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
* | | |This bit is write 1 only and is always 0 when it is read back.
* |[1] |SSTALL |Set STALL
* | | |0 = Disable the device to response STALL.
* | | |1 = Set the device to respond STALL automatically.
*/
__IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */
__IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */
__IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */
__IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */
} USBD_EP_T;
typedef struct
{
/**
* @var USBD_T::INTEN
* Offset: 0x00 USB Device Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIEN |Bus Event Interrupt Enable Bit
* | | |0 = BUS event interrupt Disabled.
* | | |1 = BUS event interrupt Enabled.
* |[1] |USBIEN |USB Event Interrupt Enable Bit
* | | |0 = USB event interrupt Disabled.
* | | |1 = USB event interrupt Enabled.
* |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
* | | |0 = VBUS detection Interrupt Disabled.
* | | |1 = VBUS detection Interrupt Enabled.
* |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
* | | |0 = No-event-wake-up Interrupt Disabled.
* | | |1 = No-event-wake-up Interrupt Enabled.
* |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
* | | |0 = SOF Interrupt Disabled.
* | | |1 = SOF Interrupt Enabled.
* |[8] |WKEN |Wake-up Function Enable Bit
* | | |0 = USB wake-up function Disabled.
* | | |1 = USB wake-up function Enabled.
* |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
* | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
* | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
* @var USBD_T::INTSTS
* Offset: 0x04 USB Device Interrupt Event Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |BUSIF |BUS Interrupt Status
* | | |The BUS event means that there is one of the suspense or the resume function in the bus.
* | | |0 = No BUS event occurred.
* | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
* |[1] |USBIF |USB Event Interrupt Status
* | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
* | | |0 = No USB event occurred.
* | | |1 = USB event occurred, check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
* |[2] |VBDETIF |VBUS Detection Interrupt Status
* | | |0 = There is not attached/detached event in the USB.
* | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
* |[3] |NEVWKIF |No-event-wake-up Interrupt Status
* | | |0 = NEVWK event does not occur.
* | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
* |[4] |SOFIF |Start of Frame Interrupt Status
* | | |0 = SOF event does not occur.
* | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
* |[16] |EPEVT0 |Endpoint 0's USB Event Status
* | | |0 = No event occurred in endpoint 0.
* | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
* |[17] |EPEVT1 |Endpoint 1's USB Event Status
* | | |0 = No event occurred in endpoint 1.
* | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
* |[18] |EPEVT2 |Endpoint 2's USB Event Status
* | | |0 = No event occurred in endpoint 2.
* | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
* |[19] |EPEVT3 |Endpoint 3's USB Event Status
* | | |0 = No event occurred in endpoint 3.
* | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
* |[20] |EPEVT4 |Endpoint 4's USB Event Status
* | | |0 = No event occurred in endpoint 4.
* | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
* |[21] |EPEVT5 |Endpoint 5's USB Event Status
* | | |0 = No event occurred in endpoint 5.
* | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
* |[22] |EPEVT6 |Endpoint 6's USB Event Status
* | | |0 = No event occurred in endpoint 6.
* | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
* |[23] |EPEVT7 |Endpoint 7's USB Event Status
* | | |0 = No event occurred in endpoint 7.
* | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
* |[24] |EPEVT8 |Endpoint 8's USB Event Status
* | | |0 = No event occurred in endpoint 8.
* | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
* |[25] |EPEVT9 |Endpoint 9's USB Event Status
* | | |0 = No event occurred in endpoint 9.
* | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
* |[26] |EPEVT10 |Endpoint 10's USB Event Status
* | | |0 = No event occurred in endpoint 10.
* | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
* |[27] |EPEVT11 |Endpoint 11's USB Event Status
* | | |0 = No event occurred in endpoint 11.
* | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
* |[31] |SETUP |Setup Event Status
* | | |0 = No Setup event.
* | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
* @var USBD_T::FADDR
* Offset: 0x08 USB Device Function Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6:0] |FADDR |USB Device Function Address
* @var USBD_T::EPSTS
* Offset: 0x0C USB Device Endpoint Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |OV |Overrun
* | | |It indicates that the received data is over the maximum payload number or not.
* | | |0 = No overrun.
* | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
* @var USBD_T::ATTR
* Offset: 0x10 USB Device Bus Status and Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |USBRST |USB Reset Status
* | | |0 = Bus no reset.
* | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
* | | |Note: This bit is read only.
* |[1] |SUSPEND |Suspend Status
* | | |0 = Bus no suspend.
* | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
* | | |Note: This bit is read only.
* |[2] |RESUME |Resume Status
* | | |0 = No bus resume.
* | | |1 = Resume from suspend.
* | | |Note: This bit is read only.
* |[3] |TOUT |Time-out Status
* | | |0 = No time-out.
* | | |1 = No Bus response more than 18 bits time (1 / 12MHz * 18 = 1.5 us).
* | | |Note: This bit is read only.
* |[4] |PHYEN |PHY Transceiver Function Enable Bit
* | | |0 = PHY transceiver function Disabled.
* | | |1 = PHY transceiver function Enabled.
* |[5] |RWAKEUP |Remote Wake-up
* | | |0 = Release the USB bus from K state.
* | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
* |[7] |USBEN |USB Controller Enable Bit
* | | |0 = USB Controller Disabled.
* | | |1 = USB Controller Enabled.
* |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
* | | |0 = Pull-up resistor in USB_D+ bus Disabled.
* | | |1 = Pull-up resistor in USB_D+ bus Active.
* |[9] |PWRDN |Power-down PHY Transceiver, Low Active
* | | |0 = Power-down related circuit of PHY transceiver.
* | | |1 = Turn-on related circuit of PHY transceiver.
* |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
* | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
* | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
* |[11] |LPMACK |LPM Token Acknowledge Enable Bit
* | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
* | | |0= the valid LPM Token will be NYET.
* | | |1= the valid LPM Token will be ACK.
* |[12] |L1SUSPEND |LPM L1 Suspend
* | | |0 = Bus no L1 state suspend.
* | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
* | | |Note: This bit is read only.
* |[13] |L1RESUME |LPM L1 Resume
* | | |0 = Bus no LPM L1 state resume.
* | | |1 = LPM L1 state Resume from LPM L1 state suspend.
* | | |Note: This bit is read only.
* @var USBD_T::VBUSDET
* Offset: 0x14 USB Device VBUS Detection Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VBUSDET |Device VBUS Detection
* | | |0 = Controller is not attached to the USB host.
* | | |1 = Controller is attached to the USB host.
* @var USBD_T::STBUFSEG
* Offset: 0x18 SETUP Token Buffer Segmentation Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
* | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
* | | |USBD_SRAM address + {STBUFSEG, 3'b000}
* | | |Where the USBD_SRAM address = USBD_BA+0x100h.
* | | |Note: It is used for SETUP token only.
* @var USBD_T::EPSTS0
* Offset: 0x20 USB Device Endpoint Status Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[03:00] |EPSTS0 |Endpoint 0 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[07:04] |EPSTS1 |Endpoint 1 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:08] |EPSTS2 |Endpoint 2 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS3 |Endpoint 3 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[19:16] |EPSTS4 |Endpoint 4 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[23:20] |EPSTS5 |Endpoint 5 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[27:24] |EPSTS6 |Endpoint 6 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[31:28] |EPSTS7 |Endpoint 7 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::EPSTS1
* Offset: 0x24 USB Device Endpoint Status Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |EPSTS8 |Endpoint 8 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[7:4] |EPSTS9 |Endpoint 9 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[11:8] |EPSTS10 |Endpoint 10 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* |[15:12] |EPSTS11 |Endpoint 11 Status
* | | |These bits are used to indicate the current status of this endpoint
* | | |0000 = In ACK.
* | | |0001 = In NAK.
* | | |0010 = Out Packet Data0 ACK.
* | | |0011 = Setup ACK.
* | | |0110 = Out Packet Data1 ACK.
* | | |0111 = Isochronous transfer end.
* @var USBD_T::LPMATTR
* Offset: 0x88 USB LPM Attribution Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[3:0] |LPMLINKSTS|LPM Link State
* | | |These bits contain the bLinkState received with last ACK LPM Token
* |[7:4] |LPMBESL |LPM Best Effort Service Latency
* | | |These bits contain the BESL value received with last ACK LPM Token
* |[8] |LPMRWAKUP |LPM Remote Wakeup
* | | |This bit contains the bRemoteWake value received with last ACK LPM Token
* @var USBD_T::FN
* Offset: 0x8C USB Frame number Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[10:0] |FN |Frame Number
* | | |These bits contain the 11-bits frame number in the last received SOF packet.
* @var USBD_T::SE0
* Offset: 0x90 USB Device Drive SE0 Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SE0 |Drive Single Ended Zero in USB Bus
* | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
* | | |0 = Normal operation.
* | | |1 = Force USB PHY transceiver to drive SE0.
*/
__IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
__IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
__IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
__I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
__IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
__I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
__IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
/* @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[1];
/* @endcond //HIDDEN_SYMBOLS */
__I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
__I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */
/* @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE1[24];
/* @endcond //HIDDEN_SYMBOLS */
__I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
__I uint32_t FN; /*!< [0x008c] USB Frame number Register */
__IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
/* @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE2[283];
/* @endcond //HIDDEN_SYMBOLS */
USBD_EP_T EP[12]; /*!< [0x0500~0x5BC] USB Device Endpoints(0~11) */
} USBD_T;
/**
@addtogroup USBD_CONST USBD Bit Field Definition
Constant Definitions for USBD Controller
@{ */
#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */
#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */
#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */
#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */
#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */
#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */
#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */
#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */
#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
#define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */
#define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */
#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */
#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */
#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */
#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */
#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */
#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */
#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */
#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */
#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */
#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */
#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */
#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */
#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */
#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */
#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */
#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */
#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */
#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */
#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
/**@}*/ /* USBD_CONST */
/**@}*/ /* end of USBD register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __USBD_REG_H__ */

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/**************************************************************************//**
* @file uspi_reg.h
* @version V1.00
* @brief USPI register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USPI_REG_H__
#define __USPI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup USPI SPI Mode of USCI Controller (USPI)
Memory Mapped Structure for USPI Controller
@{ */
typedef struct
{
/**
* @var USPI_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var USPI_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var USPI_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fDIV_CLK.
* | | |01 = fPROT_CLK.
* | | |10 = fSCLK.
* | | |11 = fREF_CLK.
* |[4] |TMCNTEN |Time Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Time measurement counter is Disabled.
* | | |1 = Time measurement counter is Enabled.
* |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
* | | |0 = Time measurement counter with fPROT_CLK.
* | | |1 = Time measurement counter with fDIV_CLK.
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
* @var USPI_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var USPI_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* | | |Note: In SPI protocol, we suggest this bit should be set as 0.
* @var USPI_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
* | | |0 = Data output level is not inverted.
* | | |1 = Data output level is inverted.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: The control signal has different definitions in different protocol
* | | |In SPI protocol, the control signal means slave select signal
* | | |In UART protocol, the control signal means RTS signal.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
* @var USPI_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission
* | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
* |[16] |PORTDIR |Port Direction Control
* | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
* | | |It is used to define the direction of the data port pin
* | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
* | | |0 = The data pin is configured as output mode.
* | | |1 = The data pin is configured as input mode.
* @var USPI_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* @var USPI_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit
* | | |0 = Transmit under-run interrupt Disabled.
* | | |1 = Transmit under-run interrupt Enabled.
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note1: It is cleared automatically after one PCLK cycle.
* | | |Note2: Write 1 to this bit will set the output data pin to zero if USPI_BUFCTL[5]=0.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* @var USPI_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status
* | | |This bit indicates that a receive buffer overrun event has been detected
* | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun event has not been detected.
* | | |1 = A receive buffer overrun event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty and available for the next transmission datum.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status
* | | |This bit indicates that a transmit buffer under-run event has been detected
* | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit
* | | |0 = A transmit buffer under-run event has not been detected.
* | | |1 = A transmit buffer under-run event has been detected.
* @var USPI_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* | | |Notice: The I2C is not supporting PDMA function.
* @var USPI_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[1] |WKADDREN |Wake-up Address Match Enable Bit
* | | |0 = The chip is woken up according data toggle.
* | | |1 = The chip is woken up according address match.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var USPI_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var USPI_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SLAVE |Slave Mode Selection
* | | |0 = Master mode.
* | | |1 = Slave mode.
* |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only)
* | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
* | | |0 = 4-wire bi-direction interface.
* | | |1 = 3-wire bi-direction interface.
* |[2] |SS |Slave Select Control (Master Only)
* | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state.
* | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
* | | |Note: In SPI protocol, the internal slave select signal is active high.
* |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only)
* | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
* | | |1 = Slave select signal will be generated automatically
* | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
* |[7:6] |SCLKMODE |Serial Bus Clock Mode
* | | |This bit field defines the SCLK idle status, data transmit, and data receive edge.
* | | |MODE0 = The idle state of SPI clock is low level
* | | |Data is transmitted with falling edge and received with rising edge.
* | | |MODE1 = The idle state of SPI clock is low level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE2 = The idle state of SPI clock is high level
* | | |Data is transmitted with rising edge and received with falling edge.
* | | |MODE3 = The idle state of SPI clock is high level
* | | |Data is transmitted with falling edge and received with rising edge.
* |[11:8] |SUSPITV |Suspend Interval (Master Only)
* | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
* | | |The default value is 0x3
* | | |The period of the suspend interval is obtained according to the following equation.
* | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
* | | |Example:
* | | |SUSPITV = 0x0 u2026 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 u2026 1.5 SPI_CLK clock cycle.
* | | |u2026u2026
* | | |SUSPITV = 0xE u2026 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF u2026 15.5 SPI_CLK clock cycle.
* |[14:12] |TSMSEL |Transmit Data Mode Selection
* | | |This bit field describes how receive and transmit data is shifted in and out.
* | | |TSMSEL = 000b: Full-duplex SPI.
* | | |TSMSEL = 100b: Half-duplex SPI.
* | | |Other values are reserved.
* | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
* |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only)
* | | |In Slave mode, this bit field is used for Slave time-out period
* | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
* | | |Writing 0x0 into this bit field will disable the Slave time-out function.
* | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
* |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave)
* | | |This bit defines the transmitting data level when no data is available for transferring.
* | | |0 = The output data level is 0 if TX under run event occurs.
* | | |1 = The output data level is 1 if TX under run event occurs.
* |[31] |PROTEN |SPI Protocol Enable Bit
* | | |0 = SPI Protocol Disabled.
* | | |1 = SPI Protocol Enabled.
* @var USPI_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
* | | |0 = Slave select inactive interrupt generation Disabled.
* | | |1 = Slave select inactive interrupt generation Enabled.
* |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control
* | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
* | | |0 = Slave select active interrupt generation Disabled.
* | | |1 = Slave select active interrupt generation Enabled.
* |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control
* | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
* | | |0 = The Slave time-out interrupt Disabled.
* | | |1 = The Slave time-out interrupt Enabled.
* |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control
* | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
* | | |Bit count error event occurs.
* | | |0 = The Slave mode bit count error interrupt Disabled.
* | | |1 = The Slave mode bit count error interrupt Enabled.
* @var USPI_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = Transmit start event does not occur.
* | | |1 = Transmit start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = Transmit end event does not occur.
* | | |1 = Transmit end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = Receive start event does not occur.
* | | |1 = Receive start event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = Receive end event does not occur.
* | | |1 = Receive end event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only)
* | | |0 = Slave time-out event does not occur.
* | | |1 = Slave time-out event occurs.
* | | |Note: It is cleared by software writes 1 to this bit
* |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only)
* | | |0 = Slave bit count error event does not occur.
* | | |1 = Slave bit count error event occurs.
* | | |Note: It is cleared by software writes 1 to this bit.
* |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to inactive
* | | |It is cleared by software writes 1 to this bit
* | | |0 = The slave select signal has not changed to inactive.
* | | |1 = The slave select signal has changed to inactive.
* | | |Note: The internal slave select signal is active high.
* |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only)
* | | |This bit indicates that the internal slave select signal has changed to active
* | | |It is cleared by software writes one to this bit
* | | |0 = The slave select signal has not changed to active.
* | | |1 = The slave select signal has changed to active.
* | | |Note: The internal slave select signal is active high.
* |[16] |SSLINE |Slave Select Line Bus Status (Read Only)
* | | |This bit is only available in Slave mode
* | | |It used to monitor the current status of the input slave select signal on the bus.
* | | |0 = The slave select line status is 0.
* | | |1 = The slave select line status is 1.
* |[17] |BUSY |Busy Status (Read Only)
* | | |0 = SPI is in idle state.
* | | |1 = SPI is in busy state.
* | | |The following listing are the bus busy conditions:
* | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
* | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
* | | |c
* | | |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
* | | |d
* | | |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
* |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only)
* | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
* | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
* | | |0 = Slave transmit under run event does not occur.
* | | |1 = Slave transmit under run event occurs.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
__I uint32_t RESERVE0[1];
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
__I uint32_t RESERVE1[3];
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
__I uint32_t RESERVE2[1];
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
__I uint32_t RESERVE3[4];
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
__I uint32_t RESERVE4[998];
} USPI_T;
/**
@addtogroup USPI_CONST USPI Bit Field Definition
Constant Definitions for USPI Controller
@{ */
#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */
#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */
#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */
#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */
#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */
#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */
#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */
#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */
#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */
#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */
#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */
#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */
#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */
#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */
#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */
#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */
#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */
#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */
#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */
#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */
#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */
#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */
#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */
#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */
#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */
#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */
#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */
#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */
#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */
#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */
#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */
#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */
#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */
#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */
#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */
#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */
#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */
#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */
#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */
#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */
#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */
#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */
#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */
#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */
#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */
#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */
#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */
#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */
#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */
#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */
#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */
#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */
#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */
#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */
#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */
#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */
#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */
#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */
#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */
#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */
#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */
#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */
#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */
#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */
#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */
#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */
#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */
#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */
#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */
#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */
#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */
#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */
#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */
#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */
#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */
#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */
#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */
#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */
#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */
#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */
#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */
#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */
#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */
#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */
#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */
#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */
#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */
#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */
#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */
#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */
#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */
#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */
#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */
#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */
#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */
#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */
#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */
#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */
#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */
#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */
#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */
#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */
#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */
#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */
#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */
#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */
#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */
#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */
#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */
#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */
#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */
#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */
#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */
#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */
#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */
#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */
#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */
#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */
#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */
#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */
#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */
#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */
#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */
#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */
#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */
#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */
#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */
#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */
#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */
#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */
#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */
#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */
#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */
#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */
#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */
#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */
/**@}*/ /* USPI_CONST */
/**@}*/ /* end of USPI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __USPI_REG_H__ */

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board/Nuvoton_M251/STARTUP/Include/uuart_reg.h Normal file
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/**************************************************************************//**
* @file uuart_reg.h
* @version V1.00
* @brief UUART register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UUART_REG_H__
#define __UUART_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup UUART UART Mode of USCI Controller (UUART)
Memory Mapped Structure for UUART Controller
@{ */
typedef struct
{
/**
* @var UUART_T::CTL
* Offset: 0x00 USCI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |FUNMODE |Function Mode
* | | |This bit field selects the protocol for this USCI controller
* | | |Selecting a protocol that is not available or a reserved combination disables the USCI
* | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
* | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
* | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
* | | |001 = The SPI protocol is selected.
* | | |010 = The UART protocol is selected.
* | | |100 = The I2C protocol is selected.
* | | |Note: Other bit combinations are reserved.
* @var UUART_T::INTEN
* Offset: 0x04 USCI Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit start event.
* | | |0 = The transmit start interrupt is disabled.
* | | |1 = The transmit start interrupt is enabled.
* |[2] |TXENDIEN |Transmit End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a transmit finish event.
* | | |0 = The transmit finish interrupt is disabled.
* | | |1 = The transmit finish interrupt is enabled.
* |[3] |RXSTIEN |Receive Start Interrupt Enable BIt
* | | |This bit enables the interrupt generation in case of a receive start event.
* | | |0 = The receive start interrupt is disabled.
* | | |1 = The receive start interrupt is enabled.
* |[4] |RXENDIEN |Receive End Interrupt Enable Bit
* | | |This bit enables the interrupt generation in case of a receive finish event.
* | | |0 = The receive end interrupt is disabled.
* | | |1 = The receive end interrupt is enabled.
* @var UUART_T::BRGEN
* Offset: 0x08 USCI Baud Rate Generator Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RCLKSEL |Reference Clock Source Selection
* | | |This bit selects the source signal of reference clock (fREF_CLK).
* | | |0 = Peripheral device clock fPCLK.
* | | |1 = Reserved.
* |[1] |PTCLKSEL |Protocol Clock Source Selection
* | | |This bit selects the source signal of protocol clock (fPROT_CLK).
* | | |0 = Reference clock fREF_CLK.
* | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
* |[3:2] |SPCLKSEL |Sample Clock Source Selection
* | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
* | | |00 = fSAMP_CLK = fDIV_CLK.
* | | |01 = fSAMP_CLK = fPROT_CLK.
* | | |10 = fSAMP_CLK = fSCLK.
* | | |11 = fSAMP_CLK = fREF_CLK.
* |[4] |TMCNTEN |Timing Measurement Counter Enable Bit
* | | |This bit enables the 10-bit timing measurement counter.
* | | |0 = Timing measurement counter is Disabled.
* | | |1 = Timing measurement counter is Enabled.
* |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection
* | | |0 = Timing measurement counter with fPROT_CLK.
* | | |1 = Timing measurement counter with fDIV_CLK.
* |[9:8] |PDSCNT |Pre-divider for Sample Counter
* | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
* | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
* |[14:10] |DSCNT |Denominator for Sample Counter
* | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
* | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
* | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
* |[25:16] |CLKDIV |Clock Divider
* | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
* | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled
* | | |The revised value is the average bit time between bit 5 and bit 6
* | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
* @var UUART_T::DATIN0
* Offset: 0x10 USCI Input Data Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Signal Synchronization Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* |[4:3] |EDGEDET |Input Signal Edge Detection Mode
* | | |This bit field selects which edge actives the trigger event of input data signal.
* | | |00 = The trigger event activation is disabled.
* | | |01 = A rising edge activates the trigger event of input data signal.
* | | |10 = A falling edge activates the trigger event of input data signal.
* | | |11 = Both edges activate the trigger event of input data signal.
* | | |Note: In UART function mode, it is suggested to set this bit field as 10.
* @var UUART_T::CTLIN0
* Offset: 0x20 USCI Input Control Signal Configuration Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* |[2] |ININV |Input Signal Inverse Selection
* | | |This bit defines the inverter enable of the input asynchronous signal.
* | | |0 = The un-synchronized input signal will not be inverted.
* | | |1 = The un-synchronized input signal will be inverted.
* @var UUART_T::CLKIN
* Offset: 0x28 USCI Input Clock Signal Configuration Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SYNCSEL |Input Synchronization Signal Selection
* | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
* | | |0 = The un-synchronized signal can be taken as input for the data shift unit.
* | | |1 = The synchronized signal can be taken as input for the data shift unit.
* @var UUART_T::LINECTL
* Offset: 0x2C USCI Line Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |LSB |LSB First Transmission Selection
* | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
* | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
* |[5] |DATOINV |Data Output Inverse Selection
* | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
* | | |0 = The value of USCIx_DAT1 is equal to the data shift register.
* | | |1 = The value of USCIx_DAT1 is the inversion of data shift register.
* |[7] |CTLOINV |Control Signal Output Inverse Selection
* | | |This bit defines the relation between the internal control signal and the output control signal.
* | | |0 = No effect.
* | | |1 = The control signal will be inverted before its output.
* | | |Note: In UART protocol, the control signal means nRTS signal.
* |[11:8] |DWIDTH |Word Length of Transmission
* | | |This bit field defines the data word length (amount of bits) for reception and transmission
* | | |The data word is always right-aligned in the data buffer
* | | |USCI support word length from 4 to 16 bits.
* | | |0x0: The data word contains 16 bits located at bit positions [15:0].
* | | |0x1: Reserved.
* | | |0x2: Reserved.
* | | |0x3: Reserved.
* | | |0x4: The data word contains 4 bits located at bit positions [3:0].
* | | |0x5: The data word contains 5 bits located at bit positions [4:0].
* | | |...
* | | |0xF: The data word contains 15 bits located at bit positions [14:0].
* | | |Note: In UART protocol, the length can be configured as 6~13 bits.
* @var UUART_T::TXDAT
* Offset: 0x30 USCI Transmit Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |TXDAT |Transmit Data
* | | |Software can use this bit field to write 16-bit transmit data for transmission.
* @var UUART_T::RXDAT
* Offset: 0x34 USCI Receive Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RXDAT |Received Data
* | | |This bit field monitors the received data which stored in receive data buffer.
* | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
* @var UUART_T::BUFCTL
* Offset: 0x38 USCI Transmit/Receive Buffer Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7] |TXCLR |Clear Transmit Buffer
* | | |0 = No effect.
* | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control
* | | |0 = Receive overrun interrupt Disabled.
* | | |1 = Receive overrun interrupt Enabled.
* |[15] |RXCLR |Clear Receive Buffer
* | | |0 = No effect.
* | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value)
* | | |Should only be used while the buffer is not taking part in data traffic.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[16] |TXRST |Transmit Reset
* | | |0 = No effect.
* | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
* | | |Note: It is cleared automatically after one PCLK cycle.
* |[17] |RXRST |Receive Reset
* | | |0 = No effect.
* | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
* | | |Note1: It is cleared automatically after one PCLK cycle.
* | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
* @var UUART_T::BUFSTS
* Offset: 0x3C USCI Transmit/Receive Buffer Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive Buffer Empty Indicator
* | | |0 = Receive buffer is not empty.
* | | |1 = Receive buffer is empty.
* |[1] |RXFULL |Receive Buffer Full Indicator
* | | |0 = Receive buffer is not full.
* | | |1 = Receive buffer is full.
* |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status
* | | |This bit indicates that a receive buffer overrun error event has been detected
* | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit.
* | | |0 = A receive buffer overrun error event has not been detected.
* | | |1 = A receive buffer overrun error event has been detected.
* |[8] |TXEMPTY |Transmit Buffer Empty Indicator
* | | |0 = Transmit buffer is not empty.
* | | |1 = Transmit buffer is empty.
* |[9] |TXFULL |Transmit Buffer Full Indicator
* | | |0 = Transmit buffer is not full.
* | | |1 = Transmit buffer is full.
* |[11] |TXUDRIF |Transmit Buffer Under-run Error Interrupt Status
* | | |This bit indicates that a transmit buffer under-run error event has been detected
* | | |If enabled by TXUDRIEN (UUART_BUFCTL[6]), the corresponding interrupt request is activated
* | | |It is cleared by software writes 1 to this bit
* | | |0 = A transmit buffer under-run error event has not been detected.
* | | |1 = A transmit buffer under-run error event has been detected.
* @var UUART_T::PDMACTL
* Offset: 0x40 USCI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |PDMARST |PDMA Reset
* | | |0 = No effect.
* | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
* |[1] |TXPDMAEN |PDMA Transmit Channel Available
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* |[2] |RXPDMAEN |PDMA Receive Channel Available
* | | |0 = Receive PDMA function Disabled.
* | | |1 = Receive PDMA function Enabled.
* |[3] |PDMAEN |PDMA Mode Enable Bit
* | | |0 = PDMA function Disabled.
* | | |1 = PDMA function Enabled.
* @var UUART_T::WKCTL
* Offset: 0x54 USCI Wake-up Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKEN |Wake-up Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* |[2] |PDBOPT |Power Down Blocking Option
* | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
* | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
* @var UUART_T::WKSTS
* Offset: 0x58 USCI Wake-up Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WKF |Wake-up Flag
* | | |When chip is woken up from Power-down mode, this bit is set to 1
* | | |Software can write 1 to clear this bit.
* @var UUART_T::PROTCTL
* Offset: 0x5C USCI Protocol Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |STOPB |Stop Bits
* | | |This bit defines the number of stop bits in an UART frame.
* | | |0 = The number of stop bits is 1.
* | | |1 = The number of stop bits is 2.
* |[1] |PARITYEN |Parity Enable Bit
* | | |This bit defines the parity bit is enabled in an UART frame.
* | | |0 = The parity bit Disabled.
* | | |1 = The parity bit Enabled.
* |[2] |EVENPARITY|Even Parity Enable Bit
* | | |0 = Odd number of logic 1 is transmitted and checked in each word.
* | | |1 = Even number of logic 1 is transmitted and checked in each word.
* | | |Note: This bit has effect only when PARITYEN is set.
* |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
* | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] =1), the UART will de-assert nRTS signal.
* | | |0 = nRTS auto-flow control Disabled.
* | | |1 = nRTS auto-flow control Enabled.
* | | |Note: This bit has effect only when the RTSAUDIREN is not set.
* |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
* | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
* | | |0 = nCTS auto-flow control Disabled.
* | | |1 = nCTS auto-flow control Enabled.
* |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit
* | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically.
* | | |0 = nRTS auto direction control Disabled.
* | | |1 = nRTS auto direction control Enabled.
* | | |Note 1: This bit is used for nRTS auto direction control for RS485.
* | | |Note 2: This bit has effect only when the RTSAUTOEN is not set.
* |[6] |ABREN |Auto-baud Rate Detect Enable Bit
* | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled.
* | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit
* | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
* |[9] |DATWKEN |Data Wake-up Mode Enable Bit
* | | |0 = Data wake-up mode Disabled.
* | | |1 = Data wake-up mode Enabled.
* |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit
* | | |0 = nCTS wake-up mode Disabled.
* | | |1 = nCTS wake-up mode Enabled.
* |[14:11] |WAKECNT |Wake-up Counter
* | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
* |[24:16] |BRDETITV |Baud Rate Detection Interval
* | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits
* | | |The order of the bus shall be 1 and 0 step by step (e.g
* | | |the input data pattern shall be 0x55)
* | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.
* | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV.
* |[26] |STICKEN |Stick Parity Enable Bit
* | | |0 = Stick parity Disabled.
* | | |1 = Stick parity Enabled.
* | | |Note: Refer to RS-485 Support section for detail information.
* |[29] |BCEN |Transmit Break Control Enable Bit
* | | |0 = Transmit Break Control Disabled.
* | | |1 = Transmit Break Control Enabled.
* | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0)
* | | |This bit acts only on TX line and has no effect on the transmitter logic.
* |[31] |PROTEN |UART Protocol Enable Bit
* | | |0 = UART Protocol Disabled.
* | | |1 = UART Protocol Enabled.
* @var UUART_T::PROTIEN
* Offset: 0x60 USCI Protocol Interrupt Enable Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
* | | |0 = Auto-baud rate interrupt Disabled.
* | | |1 = Auto-baud rate interrupt Enabled.
* |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
* | | |0 = Receive line status interrupt Disabled.
* | | |1 = Receive line status interrupt Enabled.
* | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
* @var UUART_T::PROTSTS
* Offset: 0x64 USCI Protocol Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |TXSTIF |Transmit Start Interrupt Flag
* | | |0 = A transmit start interrupt status has not occurred.
* | | |1 = A transmit start interrupt status has occurred.
* | | |Note 1: It is cleared by software writing one into this bit.
* | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer.
* |[2] |TXENDIF |Transmit End Interrupt Flag
* | | |0 = A transmit end interrupt status has not occurred.
* | | |1 = A transmit end interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[3] |RXSTIF |Receive Start Interrupt Flag
* | | |0 = A receive start interrupt status has not occurred.
* | | |1 = A receive start interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[4] |RXENDIF |Receive End Interrupt Flag
* | | |0 = A receive finish interrupt status has not occurred.
* | | |1 = A receive finish interrupt status has occurred.
* | | |Note: It is cleared by software writing one into this bit.
* |[5] |PARITYERR |Parity Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
* | | |0 = No parity error is generated.
* | | |1 = Parity error is generated.
* | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
* |[6] |FRMERR |Framing Error Flag
* | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
* | | |0 = No framing error is generated.
* | | |1 = Framing error is generated.
* | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
* |[7] |BREAK |Break Flag
* | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
* | | |0 = No Break is generated.
* | | |1 = Break is generated in the receiver bus.
* | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
* |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag
* | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data
* | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated
* | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
* | | |0 = Auto-baud rate detect function is not done.
* | | |1 = One Bit auto-baud rate detect function is done.
* | | |Note: This bit can be cleared by writing 1 to it.
* |[10] |RXBUSY |RX Bus Status Flag (Read Only)
* | | |This bit indicates the busy status of the receiver.
* | | |0 = The receiver is Idle.
* | | |1 = The receiver is BUSY.
* |[11] |ABERRSTS |Auto-baud Rate Error Status
* | | |This bit is set when auto-baud rate detection counter overrun
* | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.
* | | |0 = Auto-baud rate detect counter is not overrun.
* | | |1 = Auto-baud rate detect counter is overrun.
* | | |Note 1: This bit is set at the same time of ABRDETIF.
* | | |Note 2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS.
* |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
* | | |This bit used to indicate the current status of the internal synchronized nCTS signal.
* | | |0 = The internal synchronized nCTS is low.
* | | |1 = The internal synchronized nCTS is high.
* |[17] |CTSLV |nCTS Pin Status (Read Only)
* | | |This bit used to monitor the current status of nCTS pin input.
* | | |0 = nCTS pin input is low level voltage logic state.
* | | |1 = nCTS pin input is high level voltage logic state.
*/
__IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
__IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */
__IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
__I uint32_t RESERVE0[1];
__IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */
__I uint32_t RESERVE1[3];
__IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */
__I uint32_t RESERVE2[1];
__IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */
__IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
__O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
__I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
__IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */
__IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */
__IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */
__I uint32_t RESERVE3[4];
__IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
__IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
__IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
__IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
__IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
__I uint32_t RESERVE4[998];
} UUART_T;
/**
@addtogroup UUART_CONST UUART Bit Field Definition
Constant Definitions for UUART Controller
@{ */
#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */
#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */
#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */
#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */
#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */
#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */
#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */
#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */
#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */
#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */
#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */
#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */
#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */
#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */
#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */
#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */
#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */
#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */
#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */
#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */
#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */
#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */
#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */
#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */
#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */
#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */
#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */
#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */
#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */
#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */
#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */
#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */
#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */
#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */
#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */
#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */
#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */
#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */
#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */
#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */
#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */
#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */
#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */
#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */
#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */
#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */
#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */
#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */
#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */
#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */
#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */
#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */
#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */
#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */
#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */
#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */
#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */
#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */
#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */
#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */
#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */
#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */
#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */
#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */
#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */
#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */
#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */
#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */
#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */
#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */
#define UUART_BUFSTS_TXUDRIF_Pos (11) /*!< UUART_T::BUFSTS: TXUDRIF Position */
#define UUART_BUFSTS_TXUDRIF_Msk (0x1ul << UUART_BUFSTS_TXUDRIF_Pos) /*!< UUART_T::BUFSTS: TXUDRIF Mask */
#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */
#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */
#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */
#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */
#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */
#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */
#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */
#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */
#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */
#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */
#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */
#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */
#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */
#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */
#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */
#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */
#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */
#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */
#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */
#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */
#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */
#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */
#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */
#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */
#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */
#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */
#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */
#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */
#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */
#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */
#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */
#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */
#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */
#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */
#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */
#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */
#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */
#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */
#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */
#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */
#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */
#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */
#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */
#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */
#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */
#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */
#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */
#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */
#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */
#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */
#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */
#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */
#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */
#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */
#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */
#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */
#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */
#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */
#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */
#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */
#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */
#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */
#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */
#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */
#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */
#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */
#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */
#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */
#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */
#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */
/**@}*/ /* UUART_CONST */
/**@}*/ /* end of UUART register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __UUART_REG_H__ */

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/**************************************************************************//**
* @file wdt_reg.h
* @version V1.00
* @brief WDT register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_REG_H__
#define __WDT_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup WDT Watch Dog Timer Controller (WDT)
Memory Mapped Structure for WDT Controller
@{ */
typedef struct
{
/**
* @var WDT_T::CTL
* Offset: 0x00 WDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect)
* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
* | | |0 = WDT time-out reset function Disabled.
* | | |1 = WDT time-out reset function Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[2] |RSTF |WDT Time-out Reset Flag
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
* | | |0 = WDT time-out reset did not occur.
* | | |1 = WDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |IF |WDT Time-out Interrupt Flag
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
* | | |0 = WDT time-out interrupt did not occur.
* | | |1 = WDT time-out interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
* | | |This bit indicates the interrupt wake-up flag status of WDT
* | | |0 = WDT does not cause chip wake-up.
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This bit is cleared by writing 1 to it.
* |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect)
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
* | | |0 = WDT time-out interrupt Disabled.
* | | |1 = WDT time-out interrupt Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[7] |WDTEN |WDT Enable Bit (Write Protect)
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
* | | |1 = WDT Enabled.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
* | | |These four bits select the time-out interval period for the WDT.
* | | |0000 = 2^4 * WDT_CLK.
* | | |0001 = 2^6 * WDT_CLK.
* | | |0010 = 2^8 * WDT_CLK.
* | | |0011 = 2^10 * WDT_CLK.
* | | |0100 = 2^12 * WDT_CLK.
* | | |0101 = 2^14 * WDT_CLK.
* | | |0110 = 2^16 * WDT_CLK.
* | | |0111 = 2^18 * WDT_CLK.
* | | |1000 = 2^20 * WDT_CLK.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
* | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
* | | |0 = Set WDTEN bit is completed.
* | | |1 = Set WDTEN bit is synchronizing and not become active yet.
* | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
* | | |WDT up counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var WDT_T::ALTCTL
* Offset: 0x04 WDT Alternative Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
* @var WDT_T::RSTCNT
* Offset: 0x08 WDT Reset Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RSTCNT |WDT Reset Counter Register
* | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
* | | |Note1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
*/
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
} WDT_T;
/**
@addtogroup WDT_CONST WDT Bit Field Definition
Constant Definitions for WDT Controller
@{ */
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
/**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __WDT_REG_H__ */

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/**************************************************************************//**
* @file wwdt_reg.h
* @version V1.00
* @brief WWDT register definition header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_REG_H__
#define __WWDT_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup WWDT Window Watchdog Timer (WWDT)
Memory Mapped Structure for WWDT Controller
@{ */
typedef struct
{
/**
* @var WWDT_T::RLDCNT
* Offset: 0x00 WWDT Reload Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RLDCNT |WWDT Reload Counter Register
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16])
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
* @var WWDT_T::CTL
* Offset: 0x04 WWDT Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTEN |WWDT Enable Bit
* | | |0 = WWDT counter is stopped.
* | | |1 = WWDT counter starts counting.
* |[1] |INTEN |WWDT Interrupt Enable Bit
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
* | | |0 = WWDT counter compare match interrupt Disabled.
* | | |1 = WWDT counter compare match interrupt Enabled.
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
* |[21:16] |CMPDAT |WWDT Window Compare Register
* | | |Set this register to adjust the valid reload window.
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
* | | |WWDT down counter will be held while CPU is held by ICE.
* | | |1 = ICE debug mode acknowledgement Disabled.
* | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
* @var WWDT_T::STATUS
* Offset: 0x08 WWDT Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
* | | |0 = No effect.
* | | |1 = WWDT counter value matches CMPDAT.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
* | | |0 = WWDT time-out reset did not occur.
* | | |1 = WWDT time-out reset occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* @var WWDT_T::CNT
* Offset: 0x0C WWDT Counter Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |CNTDAT |WWDT Counter Value
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
*/
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
} WWDT_T;
/**
@addtogroup WWDT_CONST WWDT Bit Field Definition
Constant Definitions for WWDT Controller
@{ */
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
/**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __WWDT_REG_H__ */

412
board/Nuvoton_M251/STARTUP/startup_M251.s Normal file
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;/**************************************************************************//**
; * @file startup_M251.s
; * @version V0.10
; * @brief M251 Series Startup Source File
; *
; * @note
; * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Stack_Size
Stack_Size EQU 0x00000800
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Heap_Size
Heap_Size EQU 0x00000000
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
IMPORT SendChar_ToUART
IMPORT GetChar
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD SendChar_ToUART ; Addr: 0x10, sendchar in BL retarget.c
DCD GetChar ; Addr: 0x14, getchar in BL retarget.c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; maximum of 64 External Interrupts are possible
DCD BOD_IRQHandler ; 0
DCD IRCTRIM_IRQHandler ; 1
DCD PWRWU_IRQHandler ; 2
DCD DEFAULT_IRQHandler ; 3
DCD CLKFAIL_IRQHandler ; 4
DCD DEFAULT_IRQHandler ; 5
DCD RTC_IRQHandler ; 6
DCD TAMPER_IRQHandler ; 7
DCD WDT_IRQHandler ; 8
DCD WWDT_IRQHandler ; 9
DCD EINT0_IRQHandler ; 10
DCD EINT1_IRQHandler ; 11
DCD EINT2_IRQHandler ; 12
DCD EINT3_IRQHandler ; 13
DCD EINT4_IRQHandler ; 14
DCD EINT5_IRQHandler ; 15
DCD GPA_IRQHandler ; 16
DCD GPB_IRQHandler ; 17
DCD GPC_IRQHandler ; 18
DCD GPD_IRQHandler ; 19
DCD GPE_IRQHandler ; 20
DCD GPF_IRQHandler ; 21
DCD QSPI0_IRQHandler ; 22
DCD SPI0_IRQHandler ; 23
DCD BRAKE0_IRQHandler ; 24
DCD PWM0_P0_IRQHandler ; 25
DCD PWM0_P1_IRQHandler ; 26
DCD PWM0_P2_IRQHandler ; 27
DCD BRAKE1_IRQHandler ; 28
DCD PWM1_P0_IRQHandler ; 29
DCD PWM1_P1_IRQHandler ; 30
DCD PWM1_P2_IRQHandler ; 31
DCD TMR0_IRQHandler ; 32
DCD TMR1_IRQHandler ; 33
DCD TMR2_IRQHandler ; 34
DCD TMR3_IRQHandler ; 35
DCD UART0_IRQHandler ; 36
DCD UART1_IRQHandler ; 37
DCD I2C0_IRQHandler ; 38
DCD I2C1_IRQHandler ; 39
DCD PDMA_IRQHandler ; 40
DCD DAC_IRQHandler ; 41
DCD EADC_INT0_IRQHandler ; 42
DCD EADC_INT1_IRQHandler ; 43
DCD ACMP01_IRQHandler ; 44
DCD BPWM0_IRQHandler ; 45
DCD EADC_INT2_IRQHandler ; 46
DCD EADC_INT3_IRQHandler ; 47
DCD UART2_IRQHandler ; 48
DCD DEFAULT_IRQHandler ; 49
DCD USCI0_IRQHandler ; 50
DCD DEFAULT_IRQHandler ; 51
DCD USCI1_IRQHandler ; 52
DCD USBD_IRQHandler ; 53
DCD BPWM1_IRQHandler ; 54
DCD PSIO_IRQHandler ; 55
DCD DEFAULT_IRQHandler ; 56
DCD CRPT_IRQHandler ; 57
DCD SC0_IRQHandler ; 58
DCD DEFAULT_IRQHandler ; 59
DCD USCI2_IRQHandler ; 60
DCD DEFAULT_IRQHandler ; 61
DCD OPA_IRQHandler ; 62
DCD DEFAULT_IRQHandler ; 63
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Unlock Register
;IF :DEF: __ARM_FEATURE_CMSE
;IF __ARM_FEATURE_CMSE = 3
LDR R0, =0x40000100
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
; Init POR
LDR R2, =0x40000024
LDR R1, =0x5AA5
STR R1, [R2]
LDR R2, =0x400001EC
STR R1, [R2]
; Lock register
LDR R0, =0x40000100
MOVS R1, #0
STR R1, [R0]
;ENDIF
;ENDIF
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
IMPORT ProcessHardFault
EXPORT HardFault_Handler [WEAK]
MOV R0, LR
MRS R1, MSP
MRS R2, PSP
LDR R3, =ProcessHardFault
BLX R3
BX R0
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK] ; 0
EXPORT IRCTRIM_IRQHandler [WEAK] ; 1
EXPORT PWRWU_IRQHandler [WEAK] ; 2
;EXPORT 0 [WEAK] ; 3
EXPORT CLKFAIL_IRQHandler [WEAK] ; 4
;EXPORT 0 [WEAK] ; 5
EXPORT RTC_IRQHandler [WEAK] ; 6
EXPORT TAMPER_IRQHandler [WEAK] ; 7
EXPORT WDT_IRQHandler [WEAK] ; 8
EXPORT WWDT_IRQHandler [WEAK] ; 9
EXPORT EINT0_IRQHandler [WEAK] ; 10
EXPORT EINT1_IRQHandler [WEAK] ; 11
EXPORT EINT2_IRQHandler [WEAK] ; 12
EXPORT EINT3_IRQHandler [WEAK] ; 13
EXPORT EINT4_IRQHandler [WEAK] ; 14
EXPORT EINT5_IRQHandler [WEAK] ; 15
EXPORT GPA_IRQHandler [WEAK] ; 16
EXPORT GPB_IRQHandler [WEAK] ; 17
EXPORT GPC_IRQHandler [WEAK] ; 18
EXPORT GPD_IRQHandler [WEAK] ; 19
EXPORT GPE_IRQHandler [WEAK] ; 20
EXPORT GPF_IRQHandler [WEAK] ; 21
EXPORT QSPI0_IRQHandler [WEAK] ; 22
EXPORT SPI0_IRQHandler [WEAK] ; 23
EXPORT BRAKE0_IRQHandler [WEAK] ; 24
EXPORT PWM0_P0_IRQHandler [WEAK] ; 25
EXPORT PWM0_P1_IRQHandler [WEAK] ; 26
EXPORT PWM0_P2_IRQHandler [WEAK] ; 27
EXPORT BRAKE1_IRQHandler [WEAK] ; 28
EXPORT PWM1_P0_IRQHandler [WEAK] ; 29
EXPORT PWM1_P1_IRQHandler [WEAK] ; 30
EXPORT PWM1_P2_IRQHandler [WEAK] ; 31
EXPORT TMR0_IRQHandler [WEAK] ; 32
EXPORT TMR1_IRQHandler [WEAK] ; 33
EXPORT TMR2_IRQHandler [WEAK] ; 34
EXPORT TMR3_IRQHandler [WEAK] ; 35
EXPORT UART0_IRQHandler [WEAK] ; 36
EXPORT UART1_IRQHandler [WEAK] ; 37
EXPORT I2C0_IRQHandler [WEAK] ; 38
EXPORT I2C1_IRQHandler [WEAK] ; 39
EXPORT PDMA_IRQHandler [WEAK] ; 40
EXPORT DAC_IRQHandler [WEAK] ; 41
EXPORT EADC_INT0_IRQHandler [WEAK] ; 42
EXPORT EADC_INT1_IRQHandler [WEAK] ; 43
EXPORT ACMP01_IRQHandler [WEAK] ; 44
EXPORT BPWM0_IRQHandler [WEAK] ; 45
EXPORT EADC_INT2_IRQHandler [WEAK] ; 46
EXPORT EADC_INT3_IRQHandler [WEAK] ; 47
EXPORT UART2_IRQHandler [WEAK] ; 48
;EXPORT 0 [WEAK] ; 49
EXPORT USCI0_IRQHandler [WEAK] ; 50
;EXPORT 0 [WEAK] ; 51
EXPORT USCI1_IRQHandler [WEAK] ; 52
EXPORT USBD_IRQHandler [WEAK] ; 53
EXPORT BPWM1_IRQHandler [WEAK] ; 54
EXPORT PSIO_IRQHandler [WEAK] ; 55
;EXPORT 0 [WEAK] ; 56
EXPORT CRPT_IRQHandler [WEAK] ; 57
EXPORT SC0_IRQHandler [WEAK] ; 58
;EXPORT 0 [WEAK] ; 59
EXPORT USCI2_IRQHandler [WEAK] ; 60
;EXPORT 0 [WEAK] ; 61
EXPORT OPA_IRQHandler [WEAK] ; 62
;EXPORT 0 [WEAK] ; 63
EXPORT DEFAULT_IRQHandler [WEAK]
BOD_IRQHandler ; 0
IRCTRIM_IRQHandler ; 1
PWRWU_IRQHandler ; 2
;0 ; 3
CLKFAIL_IRQHandler ; 4
;0 ; 5
RTC_IRQHandler ; 6
TAMPER_IRQHandler ; 7
WDT_IRQHandler ; 8
WWDT_IRQHandler ; 9
EINT0_IRQHandler ; 10
EINT1_IRQHandler ; 11
EINT2_IRQHandler ; 12
EINT3_IRQHandler ; 13
EINT4_IRQHandler ; 14
EINT5_IRQHandler ; 15
GPA_IRQHandler ; 16
GPB_IRQHandler ; 17
GPC_IRQHandler ; 18
GPD_IRQHandler ; 19
GPE_IRQHandler ; 20
GPF_IRQHandler ; 21
QSPI0_IRQHandler ; 22
SPI0_IRQHandler ; 23
BRAKE0_IRQHandler ; 24
PWM0_P0_IRQHandler ; 25
PWM0_P1_IRQHandler ; 26
PWM0_P2_IRQHandler ; 27
BRAKE1_IRQHandler ; 28
PWM1_P0_IRQHandler ; 29
PWM1_P1_IRQHandler ; 30
PWM1_P2_IRQHandler ; 31
TMR0_IRQHandler ; 32
TMR1_IRQHandler ; 33
TMR2_IRQHandler ; 34
TMR3_IRQHandler ; 35
UART0_IRQHandler ; 36
UART1_IRQHandler ; 37
I2C0_IRQHandler ; 38
I2C1_IRQHandler ; 39
PDMA_IRQHandler ; 40
DAC_IRQHandler ; 41
EADC_INT0_IRQHandler ; 42
EADC_INT1_IRQHandler ; 43
ACMP01_IRQHandler ; 44
BPWM0_IRQHandler ; 45
EADC_INT2_IRQHandler ; 46
EADC_INT3_IRQHandler ; 47
UART2_IRQHandler ; 48
;0 ; 49
USCI0_IRQHandler ; 50
;0 ; 51
USCI1_IRQHandler ; 52
USBD_IRQHandler ; 53
BPWM1_IRQHandler ; 54
PSIO_IRQHandler ; 55
;0 ; 56
CRPT_IRQHandler ; 57
SC0_IRQHandler ; 58
;0 ; 59
USCI2_IRQHandler ; 60
;0 ; 61
OPA_IRQHandler ; 62
;0 ; 63
DEFAULT_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, =Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, =(Heap_Mem + Heap_Size)
LDR R3, =Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
SH_DoCommand PROC
EXPORT SH_DoCommand
IMPORT SH_Return
BKPT 0xAB ; Wait ICE or HardFault
LDR R3, =SH_Return
PUSH {R3 ,lr}
BLX R3 ; Call SH_Return. The return value is in R0
POP {R3 ,PC} ; Return value = R0
ENDP
__PC PROC
EXPORT __PC
MOV r0, lr
BLX lr
ALIGN
ENDP
END

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/**************************************************************************//**
* @file system_M251.c
* @version V0.10
* @brief System Setting Source File
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
****************************************************************************/
#include <arm_cmse.h>
#include <stdio.h>
#include <stdint.h>
#include "M251.h"
#include "tos.h" //include tos.h
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include "partition_M251.h"
#endif
extern void *__Vectors; /* see startup file */
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
const uint32_t gau32ClkSrcTbl[8] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __MIRC, 0UL, __HIRC};
/**
* @brief Update the Variable SystemCoreClock
*
* @param None
*
* @return None
*
* @details This function is used to update the variable SystemCoreClock
* and must be called whenever the core clock is changed.
*/
void SystemCoreClockUpdate(void)
{
uint32_t u32Freq, u32ClkSrc;
uint32_t u32HclkDiv;
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
/* Update PLL Clock */
PllClock = CLK_GetPLLClockFreq();
if (u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL)
{
/* Use the clock sources directly */
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
}
else
{
/* Use PLL clock */
u32Freq = PllClock;
}
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
/* Update System Core Clock */
SystemCoreClock = u32Freq / u32HclkDiv;
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
}
/**
* @brief System Initialization
*
* @param None
*
* @return None
*
* @details The necessary initialization of system. Global variables are forbidden here.
*/
void SystemInit(void)
{
/* Set access cycle for CPU @ 48MHz */
FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (3 << FMC_CYCCTL_CYCLE_Pos) | 0x100;
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
TZ_SAU_Setup();
SCU_Setup();
FMC_NSBA_Setup();
#endif
#ifdef INIT_SYSCLK_AT_BOOTING
#endif
}
#if USE_ASSERT
/**
* @brief Assert Error Message
*
* @param[in] file the source file name
* @param[in] line line number
*
* @return None
*
* @details The function prints the source file name and line number where
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
*/
void AssertError(uint8_t *file, uint32_t line)
{
printf("[%s] line %d : wrong parameters.\r\n", file, line);
/* Infinite loop */
while (1) ;
}
#endif
/**
* @brief Set UART0 Default MPF
*
* @param None
*
* @return None
*
* @details The initialization of uart0 default multi function pin.
*/
#if defined( __ICCARM__ )
__WEAK
#else
__attribute__((weak))
#endif
void Uart0DefaultMPF(void)
{
/* Set GPB multi-function pins for UART0 RXD and TXD */
// SYS->GPB_MFPH = (SYS->GPB_MFPH & ~SYS_GPB_MFPH_PB12MFP_Msk) | SYS_GPB_MFPH_PB12MFP_UART0_RXD;
// SYS->GPB_MFPH = (SYS->GPB_MFPH & ~SYS_GPB_MFPH_PB13MFP_Msk) | SYS_GPB_MFPH_PB13MFP_UART0_TXD;
SYS->GPA_MFPL = (SYS->GPA_MFPL & ~SYS_GPA_MFPL_PA0MFP_Msk) | SYS_GPA_MFPL_PA0MFP_UART0_RXD;
SYS->GPA_MFPL = (SYS->GPA_MFPL & ~SYS_GPA_MFPL_PA1MFP_Msk) | SYS_GPA_MFPL_PA1MFP_UART0_TXD;
}
//systick interrupt Handler function
void SysTick_Handler(void)
{
if (tos_knl_is_running())
{
tos_knl_irq_enter();
tos_tick_handler();
tos_knl_irq_leave();
}
}

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/**************************************************************************//**
* @file ACMP.h
* @version V1.00
* @brief M251 series ACMP Driver Header File
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __ACMP_H__
#define __ACMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* ACMP_CTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */
#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLKs filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLKs filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLKs filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLKs filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLKs filter count. \hideinitializer */
#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLKs filter count. \hideinitializer */
#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */
#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */
#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */
#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */
#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */
#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* ACMP_VREF constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ACMP_VREF_CRVSSEL_AVDD (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage AVDD as the CRV source voltage \hideinitializer */
#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */
/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define Macros and functions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief This macro is used to enable output inverse function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
* \hideinitializer
*/
#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
/**
* @brief This macro is used to disable output inverse function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
* \hideinitializer
*/
#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
/**
* @brief This macro is used to select ACMP negative input source
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Src is comparator negative input selection. Including:
* - \ref ACMP_CTL_NEGSEL_PIN
* - \ref ACMP_CTL_NEGSEL_CRV
* - \ref ACMP_CTL_NEGSEL_VBG
* - \ref ACMP_CTL_NEGSEL_DAC
* @return None
* @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
* \hideinitializer
*/
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
/**
* @brief This macro is used to enable hysteresis function and set hysteresis to 30mV
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
/**
* @brief This macro is used to disable hysteresis function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function.
* \hideinitializer
*/
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
/**
* @brief This macro is used to select hysteresis level
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32HysSel The hysteresis function option. Including:
* - \ref ACMP_CTL_HYSTERESIS_30MV
* - \ref ACMP_CTL_HYSTERESIS_20MV
* - \ref ACMP_CTL_HYSTERESIS_10MV
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
* \hideinitializer
* @return None
*/
#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))
/**
* @brief This macro is used to enable interrupt
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
* If wake-up function is enabled, the wake-up interrupt will be enabled as well.
* \hideinitializer
*/
#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
/**
* @brief This macro is used to disable interrupt
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
* \hideinitializer
*/
#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
/**
* @brief This macro is used to enable ACMP
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
* \hideinitializer
*/
#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
/**
* @brief This macro is used to disable ACMP
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
* \hideinitializer
*/
#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
/**
* @brief This macro is used to get ACMP output value
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return ACMP output value
* @details This macro will return the ACMP output value.
* \hideinitializer
*/
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
/**
* @brief This macro is used to get ACMP interrupt flag
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return ACMP interrupt occurred (1) or not (0)
* @details This macro will return the ACMP interrupt flag.
* \hideinitializer
*/
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
/**
* @brief This macro is used to clear ACMP interrupt flag
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
* \hideinitializer
*/
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
/**
* @brief This macro is used to clear ACMP wake-up interrupt flag
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
* \hideinitializer
*/
#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
/**
* @brief This macro is used to enable ACMP wake-up function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
* \hideinitializer
*/
#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
/**
* @brief This macro is used to disable ACMP wake-up function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
* \hideinitializer
*/
#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
/**
* @brief This macro is used to select ACMP positive input pin
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Pin Comparator positive pin selection. Including:
* - \ref ACMP_CTL_POSSEL_P0
* - \ref ACMP_CTL_POSSEL_P1
* - \ref ACMP_CTL_POSSEL_P2
* - \ref ACMP_CTL_POSSEL_P3
* @return None
* @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
* \hideinitializer
*/
#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
/**
* @brief This macro is used to enable ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
* \hideinitializer
*/
#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
/**
* @brief This macro is used to disable ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
* \hideinitializer
*/
#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
/**
* @brief This macro is used to set ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Cnt is comparator filter count setting.
* - \ref ACMP_CTL_FILTSEL_OFF
* - \ref ACMP_CTL_FILTSEL_1PCLK
* - \ref ACMP_CTL_FILTSEL_2PCLK
* - \ref ACMP_CTL_FILTSEL_4PCLK
* - \ref ACMP_CTL_FILTSEL_8PCLK
* - \ref ACMP_CTL_FILTSEL_16PCLK
* - \ref ACMP_CTL_FILTSEL_32PCLK
* - \ref ACMP_CTL_FILTSEL_64PCLK
* @return None
* @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
* \hideinitializer
*/
#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
/**
* @brief This macro is used to select comparator reference voltage
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32Level The comparator reference voltage setting.
* The formula is:
* comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
* The range of u32Level is 0 ~ 15.
* @return None
* @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
* \hideinitializer
*/
#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))
/**
* @brief This macro is used to select the source of CRV
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32Src is the source of CRV. Including:
* - \ref ACMP_VREF_CRVSSEL_AVDD
* - \ref ACMP_VREF_CRVSSEL_INTVREF
* @return None
* @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
* \hideinitializer
*/
#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
/**
* @brief This macro is used to select ACMP interrupt condition
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Cond Comparator interrupt condition selection. Including:
* - \ref ACMP_CTL_INTPOL_RF
* - \ref ACMP_CTL_INTPOL_R
* - \ref ACMP_CTL_INTPOL_F
* @return None
* @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
* \hideinitializer
*/
#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
/**
* @brief This macro is used to enable ACMP window latch mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
* When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
* block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
* WLATOUT, is frozen.
* \hideinitializer
*/
#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
/**
* @brief This macro is used to disable ACMP window latch mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
* \hideinitializer
*/
#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
/**
* @brief This macro is used to enable ACMP window compare mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
* When window compare mode is enabled, user can connect the specific analog voltage
* source to either the positive inputs of both comparators or the negative inputs of
* both comparators. The upper bound and lower bound of the designated range are
* determined by the voltages applied to the other inputs of both comparators. If the
* output of a comparator is low and the other comparator outputs high, which means two
* comparators implies the upper and lower bound. User can directly monitor a specific
* analog voltage source via ACMPWO (ACMP_STATUS[16]).
* \hideinitializer
*/
#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
/**
* @brief This macro is used to disable ACMP window compare mode
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
* \hideinitializer
*/
#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
/* Function prototype declaration */
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel);
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ACMP_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __ACMP_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/bpwm.h Normal file
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@@ -0,0 +1,376 @@
/******************************************************************************
* @file bpwm.h
* @version V0.10
* @brief M251 series BPWM driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __BPWM_H__
#define __BPWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup BPWM_Driver BPWM Driver
@{
*/
/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
@{
*/
#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */
#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask */
#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask */
#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask */
#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask */
#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask */
#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask */
/*---------------------------------------------------------------------------------------------------------*/
/* Counter Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */
#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */
#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
/*---------------------------------------------------------------------------------------------------------*/
/* Aligned Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */
#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */
/*---------------------------------------------------------------------------------------------------------*/
/* Output Level Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */
#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */
#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */
#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */
/*---------------------------------------------------------------------------------------------------------*/
/* Synchronous Start Function Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
#define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
#define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
#define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
/*---------------------------------------------------------------------------------------------------------*/
/* Trigger Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point */
#define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point */
#define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point */
#define BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point */
#define BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point */
#define BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point */
#define BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point */
/*---------------------------------------------------------------------------------------------------------*/
/* Capture Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition */
#define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition */
/*---------------------------------------------------------------------------------------------------------*/
/* Duty Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (BPWM_INTEN_CMPDIEN0_Msk) /*!< BPWM duty interrupt triggered if down count match comparator */
#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (BPWM_INTEN_CMPUIEN0_Msk) /*!< BPWM duty interrupt triggered if up down match comparator */
/*---------------------------------------------------------------------------------------------------------*/
/* Load Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_LOAD_MODE_IMMEDIATE (BPWM_CTL0_IMMLDEN0_Msk) /*!< BPWM immediately load mode */
#define BPWM_LOAD_MODE_CENTER (BPWM_CTL0_CTRLD0_Msk) /*!< BPWM center load mode */
/*---------------------------------------------------------------------------------------------------------*/
/* Clock Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK */
#define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow */
#define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow */
#define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow */
#define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow */
/*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
@{
*/
/**
* @brief Enable timer synchronous start counting function of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
* - \ref BPWM_SSCTL_SSRC_PWM0
* - \ref BPWM_SSCTL_SSRC_PWM1
* - \ref BPWM_SSCTL_SSRC_BPWM0
* - \ref BPWM_SSCTL_SSRC_BPWM1
* @return None
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
* @note All channels share channel 0's setting.
* \hideinitializer
*/
#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
/**
* @brief Disable timer synchronous start counting function of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
* @note All channels share channel 0's setting.
* \hideinitializer
*/
#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
/**
* @brief This macro enable BPWM counter synchronous start counting function.
* @param[in] bpwm The pointer of the specified BPWM module
* @return None
* @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
* To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
* \hideinitializer
*/
#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
/**
* @brief This macro enable output inverter of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* \hideinitializer
*/
#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
/**
* @brief This macro get captured rising data
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* \hideinitializer
*/
#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
/**
* @brief This macro get captured falling data
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* \hideinitializer
*/
#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
/**
* @brief This macro mask output logic to high or low
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32LevelMask Output logic to high or low
* @return None
* @details This macro is used to mask output logic to high or low of specified channel(s).
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
* \hideinitializer
*/
#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
{ \
(bpwm)->MSKEN = (u32ChannelMask); \
(bpwm)->MSK = (u32LevelMask); \
}
/**
* @brief This macro set the prescaler of all channels
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
* @return None
* \hideinitializer
*/
#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
/**
* @brief This macro get the prescaler of the selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5. This parameter is not used.
* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
* @details This macro is used to get the prescaler of specified channel.
* @note All channels share channel 0's setting.
* The clock of BPWM counter is divided by (u32Prescaler + 1).
* \hideinitializer
*/
#define BPWM_GET_PRESCALER(bpwm, u32ChannelNum) (bpwm)->CLKPSC
/**
* @brief This macro set the duty of the selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next BPWM period
* \hideinitializer
*/
#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
/**
* @brief This macro get the duty of the selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return Return the duty of specified channel. Valid values are between 0~0xFFFF
* @details This macro is used to get the duty of specified channel.
* \hideinitializer
*/
#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
/**
* @brief This macro set the period of all channels
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next BPWM period
* @note BPWM counter will stop if period length set to 0
* \hideinitializer
*/
#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
/**
* @brief This macro get the period of all channels
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return Return the period of specified channel.
* @details This macro is used to get the period of specified channel.
* \hideinitializer
*/
#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
/**
* @brief This macro set the BPWM aligned type
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @param[in] u32AlignedType BPWM aligned type, valid values are:
* - \ref BPWM_UP_COUNTER
* - \ref BPWM_DOWN_COUNTER
* - \ref BPWM_UP_DOWN_COUNTER
* @return None
* @note All channels share channel 0's setting.
* \hideinitializer
*/
#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
/**
* @brief Clear counter of channel 0
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This macro is used to clear counter of channel 0
* \hideinitializer
*/
#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
/**
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32ZeroLevel output level at zero point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
* - \ref BPWM_OUTPUT_NOTHING
* - \ref BPWM_OUTPUT_LOW
* - \ref BPWM_OUTPUT_HIGH
* - \ref BPWM_OUTPUT_TOGGLE
* @return None
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
* \hideinitializer
*/
#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
do{ \
uint32_t i; \
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) { \
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1UL))) | ((u32ZeroLevel) << (i << 1UL))); \
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))); \
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1UL))) | ((u32CmpUpLevel) << (i << 1UL))); \
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))); \
} \
} \
}while(0)
/*---------------------------------------------------------------------------------------------------------*/
/* Define BPWM functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group BPWM_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __BPWM_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

627
board/Nuvoton_M251/StdDriver/inc/clk.h Normal file
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@@ -0,0 +1,627 @@
/****************************************************************************
* @file clk.h
* @version V1.10
* @brief M251 series CLK driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CLK_H__
#define __CLK_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CLK_Driver CLK Driver
@{
*/
/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
@{
*/
#define FREQ_4MHZ 4000000UL
#define FREQ_8MHZ 8000000UL
#define FREQ_16MHZ 16000000UL
#define FREQ_25MHZ 25000000UL
#define FREQ_32MHZ 32000000UL
#define FREQ_48MHZ 48000000UL
#define FREQ_50MHZ 50000000UL
#define FREQ_64MHZ 64000000UL
#define FREQ_72MHZ 72000000UL
#define FREQ_96MHZ 96000000UL
#define FREQ_100MHZ 100000000UL
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL0 constant definitions. (Write-protection) */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external X'tal */
#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external X'tal 32.768KHz*/
#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output */
#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 10KHz RC clock */
#define CLK_CLKSEL0_HCLKSEL_MIRC (0x05UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock */
#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock */
#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external X'tal */
#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external X'tal 32.768KHz*/
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external X'tal/2 */
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as HCLK/2 */
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock/2 */
#define SysTick_CTRL_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
#define CLK_CLKSEL0_STCLKSEL_HCLK SysTick_CTRL_STCLKSEL_HCLK /*!< Setting SysTick clock source as HCLK (Backward compatible) */
#define CLK_CLKSEL0_USBDSEL_HIRC (0x00UL<<CLK_CLKSEL0_USBDSEL_Pos) /*!< Setting clock source as external X'tal */
#define CLK_CLKSEL0_USBDSEL_PLL (0x01UL<<CLK_CLKSEL0_USBDSEL_Pos) /*!< Setting clock source as external X'tal 32.768KHz*/
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external X'tal 32.768KHz*/
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */
#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WDT clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external X'tal */
#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external X'tal 32.768KHz */
#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK */
#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal 48MHz RC clock */
#define CLK_CLKSEL1_CLKOSEL_LIRC (0x4UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal 32.768KHz RC clock */
#define CLK_CLKSEL1_CLKOSEL_MIRC (0x5UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal 4.032MHz RC clock */
#define CLK_CLKSEL1_CLKOSEL_PLL (0x6UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as PLL */
#define CLK_CLKSEL1_CLKOSEL_SOF (0x7UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as USB SOF 1kHz */
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal */
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal 32.768KHz */
#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK */
#define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock */
#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal */
#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal 32.768KHz */
#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 0 clock source as PCLK */
#define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock */
#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal */
#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal 32.768KHz */
#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 0 clock source as PCLK */
#define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock */
#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal */
#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 0 clock source as external X'tal 32.768KHz */
#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 0 clock source as PCLK */
#define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock */
#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external X'tal */
#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external PLL */
#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external X'tal */
#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external internal 48MHz RC clock */
#define CLK_CLKSEL1_UART0SEL_PCLK0 (0x4UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external PCLK */
#define CLK_CLKSEL1_UART0SEL_LIRC (0x5UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as external internal 38.4KHz RC clock */
#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external X'tal */
#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external PLL */
#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external X'tal */
#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external internal 48MHz RC clock */
#define CLK_CLKSEL1_UART1SEL_PCLK1 (0x4UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external PCLK */
#define CLK_CLKSEL1_UART1SEL_LIRC (0x5UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as external internal 38.4KHz RC clock */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL2_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external X'tal */
#define CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK */
#define CLK_CLKSEL2_PWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external X'tal */
#define CLK_CLKSEL2_PWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK */
#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting SPI clock source as HXT */
#define CLK_CLKSEL2_QSPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting SPI clock source as PLL */
#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting SPI clock source as PCLK0 */
#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Setting SPI clock source as HIRC */
#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as HXT */
#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as PLL */
#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as PCLK0 */
#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI clock source as HIRC */
#define CLK_CLKSEL2_BPWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external X'tal */
#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK */
#define CLK_CLKSEL2_BPWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external X'tal */
#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK */
#define CLK_CLKSEL2_PSIOSEL_HXT (0x0UL<<CLK_CLKSEL2_PSIOSEL_Pos)
#define CLK_CLKSEL2_PSIOSEL_LXT (0x1UL<<CLK_CLKSEL2_PSIOSEL_Pos)
#define CLK_CLKSEL2_PSIOSEL_PCLK1 (0x2UL<<CLK_CLKSEL2_PSIOSEL_Pos)
#define CLK_CLKSEL2_PSIOSEL_PLL (0x3UL<<CLK_CLKSEL2_PSIOSEL_Pos)
#define CLK_CLKSEL2_PSIOSEL_LIRC (0x4UL<<CLK_CLKSEL2_PSIOSEL_Pos)
#define CLK_CLKSEL2_PSIOSEL_HIRC (0x7UL<<CLK_CLKSEL2_PSIOSEL_Pos)
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL3 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as external X'tal */
#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL */
#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK */
#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as internal 22.1184MHz RC clock */
#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external X'tal */
#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external PLL */
#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external X'tal */
#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external internal 48MHz RC clock */
#define CLK_CLKSEL3_UART2SEL_PCLK0 (0x4UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external PCLK */
#define CLK_CLKSEL3_UART2SEL_LIRC (0x5UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as external internal 38.4KHz RC clock */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV0 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 */
#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV Setting for USB clock divider. It could be 1~16, has to be 1 or even */
#define CLK_CLKDIV0_UART0(x) (((x)-1) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV Setting for UART clock divider. It could be 1~16 */
#define CLK_CLKDIV0_UART1(x) (((x)-1) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV Setting for UART clock divider. It could be 1~16 */
#define CLK_CLKDIV0_EADC(x) (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV Setting for EADC clock divider. It could be 1~256 */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV Setting for SC0 clock divider. It could be 1~256 */
#define CLK_CLKDIV1_PSIO(x) (((x)-1) << CLK_CLKDIV1_PSIODIV_Pos)/*!< CLKDIV Setting for PSIO clock divider. It could be 1~256 */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV4 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV4_UART2(x) (((x)-1) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV Setting for UART clock divider. It could be 1~16 */
/*---------------------------------------------------------------------------------------------------------*/
/* PCLKDIV constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL<<CLK_PCLKDIV_APB0DIV_Pos)
#define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL<<CLK_PCLKDIV_APB0DIV_Pos)
#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL<<CLK_PCLKDIV_APB0DIV_Pos)
#define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL<<CLK_PCLKDIV_APB0DIV_Pos)
#define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL<<CLK_PCLKDIV_APB0DIV_Pos)
#define CLK_PCLKDIV_APB0DIV_DIV32 (0x5UL<<CLK_PCLKDIV_APB0DIV_Pos)
#define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL<<CLK_PCLKDIV_APB1DIV_Pos)
#define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL<<CLK_PCLKDIV_APB1DIV_Pos)
#define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL<<CLK_PCLKDIV_APB1DIV_Pos)
#define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL<<CLK_PCLKDIV_APB1DIV_Pos)
#define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL<<CLK_PCLKDIV_APB1DIV_Pos)
#define CLK_PCLKDIV_APB1DIV_DIV32 (0x5UL<<CLK_PCLKDIV_APB1DIV_Pos)
/*---------------------------------------------------------------------------------------------------------*/
/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PLLCTL_PLLSRC_HXT (0x0ul << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is HXT. 4~12MHz < FIN < 24MHz */
#define CLK_PLLCTL_PLLSRC_HIRC_DIV4 (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is HIRC/4. 12 MHz< FIN < 12MHz */
#define CLK_PLLCTL_PLLSRC_MIRC (0x3ul << CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is MIRC. 4 MHz< FIN < 4MHz */
#define CLK_PLLCTL_NF(x) (x) /*!< x must be constant and 1 <= x <= 63. 64MHz < FIN*NF/NR < 100MHz. */
#define CLK_PLLCTL_NR(x) ((x)<<CLK_PLLCTL_INDIV_Pos) /*!< x must be constant and 1 <= x <= 15. 4MHz < FIN/NR < 8MHz */
#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
#define CLK_PLLCTL_16MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_4)
#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 48MHz PLL output with HXT(12MHz X'tal) */
#define CLK_PLLCTL_50MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(25) | CLK_PLLCTL_NO_2)
#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(12) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(20) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(25) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_16MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_4)
#define CLK_PLLCTL_48MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 48MHz PLL output with HIRC_DIV4(12MHz IRC) */
#define CLK_PLLCTL_50MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(25) | CLK_PLLCTL_NO_2)
#define CLK_PLLCTL_72MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(12) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_80MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(20) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_96MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_100MHz_HIRC_DIV4 (CLK_PLLCTL_PLLSRC_HIRC_DIV4 | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF(25) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_16MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_4)
#define CLK_PLLCTL_48MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(24) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 48MHz PLL output with MIRC(4MHz IRC) */
#define CLK_PLLCTL_50MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(25) | CLK_PLLCTL_NO_2)
#define CLK_PLLCTL_72MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(18) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_80MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(20) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_96MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(24) | CLK_PLLCTL_NO_1)
#define CLK_PLLCTL_100MHz_MIRC (CLK_PLLCTL_PLLSRC_MIRC | CLK_PLLCTL_NR(1) | CLK_PLLCTL_NF(25) | CLK_PLLCTL_NO_1)
/*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
#define MODULE_APBCLK(x) (((x) >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
#define MODULE_CLKSEL(x) (((x) >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index */
#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
#define MODULE_CLKDIV(x) (((x) >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 */
#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
#define NA MODULE_NoMsk /*!< Not Available */
#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4*/
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
//AHBCLK
#define PDMA_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMACKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */
#define CRC_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
#define EBI_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */
#define CRPT_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRYPTCKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */
#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_FMCIDLE_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */
//APBCLK0
#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module */
#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */
#define CLKO_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 4)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CLKO Module */
#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos)|\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module */
#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module */
#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module */
#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module */
#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(24)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART0 Module */
#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(28)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 12)) /*!< UART1 Module */
#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(24)|\
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< UART2 Module */
#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */
#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */
#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_QSPI0CKEN_Pos) |\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QSPI0 Module */
#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module */
#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */
#define EADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_EADCCKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< ADC Module */
#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP Module */
#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos)|\
MODULE_CLKSEL_ENC( 0)|MODULE_CLKSEL_Msk_ENC(1)|MODULE_CLKSEL_Pos_ENC(8)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBD Module */
//APBCLK1
#define PWM0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 0)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM0 Module */
#define PWM1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 1)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM1 Module */
#define DAC_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_DACCKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */
#define OPA_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_OPACKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< OPA Module */
#define USCI0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI0CKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */
#define USCI1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI1CKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */
#define USCI2_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI2CKEN_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI2 Module */
#define SC0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0CKEN_Pos)|\
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< SC0 Module */
#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM0CKEN_Pos)|\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 8)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */
#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM1CKEN_Pos)|\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 9)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */
#define PSIO_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PSIOCKEN_Pos)|\
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 28)|\
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 24)) /*!< PSIO Module */
/*---------------------------------------------------------------------------------------------------------*/
/* PDMSEL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PMUCTL_PDMSEL_PD (0x0UL<<CLK_PMUCTL_PDMSEL_Pos)
#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL<<CLK_PMUCTL_PDMSEL_Pos)
#define CLK_PMUCTL_PDMSEL_DPD (0x6UL<<CLK_PMUCTL_PDMSEL_Pos)
/*---------------------------------------------------------------------------------------------------------*/
/* WKTMRIS constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (~3.34 ms) */
#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (~6.67 ms) */
#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (~13.34 ms) */
#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (~26.67ms) */
#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (~106.67ms) */
#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (~213.34ms) */
#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (~426.67ms) */
#define CLK_PMUCTL_WKTMRIS_32768 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (~852.34ms) */
/*---------------------------------------------------------------------------------------------------------*/
/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_DPDWKPIN_0 (0x0UL) /*!< Wake-up pin0 (GPC.0) at Deep Power-down mode */
#define CLK_DPDWKPIN_1 (0x1UL) /*!< Wake-up pin1 (GPB.0) at Deep Power-down mode */
#define CLK_DPDWKPIN_2 (0x2UL) /*!< Wake-up pin2 (GPB.2) at Deep Power-down mode */
#define CLK_DPDWKPIN_3 (0x3UL) /*!< Wake-up pin3 (GPB.12) at Deep Power-down mode */
#define CLK_DPDWKPIN_4 (0x4UL) /*!< Wake-up pin4 (GPF.6) at Deep Power-down mode */
#define CLK_DPDWKPIN_RISING (0x1UL)
#define CLK_DPDWKPIN_FALLING (0x2UL)
#define CLK_DPDWKPIN_BOTHEDGE (0x3UL)
#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode */
#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode */
#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode */
#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode */
#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode */
#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode */
#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode */
#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode */
#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode */
#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode */
#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode */
#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode */
#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode */
#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode */
#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode */
#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode */
#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode */
#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode */
#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode */
#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode */
#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode */
#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode */
#define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN0_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode */
#define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode */
#define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode */
#define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode */
#define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode */
#define CLK_DISABLE_WKPINDB(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINDBEN_Msk) /*!< Disable Wake-up pin De-bounce function */
#define CLK_ENABLE_WKPINDB(void) (CLK->PMUCTL |= CLK_PMUCTL_WKPINDBEN_Msk) /*!< Enable Wake-up pin De-bounce function */
#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */
/**
* @brief Set Wake-up Timer Time-out Interval
*
* @param[in] u32Interval The de-bounce sampling cycle selection. It could be
* - \ref CLK_PMUCTL_WKTMRIS_128
* - \ref CLK_PMUCTL_WKTMRIS_256
* - \ref CLK_PMUCTL_WKTMRIS_512
* - \ref CLK_PMUCTL_WKTMRIS_1024
* - \ref CLK_PMUCTL_WKTMRIS_4096
* - \ref CLK_PMUCTL_WKTMRIS_8192
* - \ref CLK_PMUCTL_WKTMRIS_16384
* - \ref CLK_PMUCTL_WKTMRIS_32768
*
* @return None
*
* @details This function set Wake-up Timer Time-out Interval.
*
*
*/
#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
/*---------------------------------------------------------------------------------------------------------*/
/* static inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void CLK_SysTickDelay(uint32_t u32USec);
__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t u32USec);
/**
* @brief This function execute delay function.
* @param[in] u32USec Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
* 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
* @return None
* @details Use the SysTick to generate the delay time and the UNIT is in us.
* The SysTick clock source is from HCLK, i.e the same as system core clock.
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
*/
__STATIC_INLINE void CLK_SysTickDelay(uint32_t u32USec)
{
SysTick->LOAD = u32USec * CyclesPerUs;
SysTick->VAL = (0x0u);
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0u)
{
}
/* Disable SysTick counter */
SysTick->CTRL = 0u;
}
/**
* @brief This function execute long delay function.
* @param[in] u32USec Delay time.
* @return None
* @details Use the SysTick to generate the long delay time and the UNIT is in us.
* The SysTick clock source is from HCLK, i.e the same as system core clock.
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
*/
__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t u32USec)
{
uint32_t u32Delay;
/* It should <= 349525us for each delay loop */
u32Delay = 349525UL;
do
{
if (u32USec > u32Delay)
{
u32USec -= u32Delay;
}
else
{
u32Delay = u32USec;
u32USec = 0UL;
}
SysTick->LOAD = u32Delay * CyclesPerUs;
SysTick->VAL = (0x0UL);
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
{
}
/* Disable SysTick counter */
SysTick->CTRL = 0UL;
}
while (u32USec > 0UL);
}
void CLK_DisableCKO(void);
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
void CLK_PowerDown(void);
void CLK_Idle(void);
uint32_t CLK_GetHXTFreq(void);
uint32_t CLK_GetLXTFreq(void);
uint32_t CLK_GetPCLK0Freq(void);
uint32_t CLK_GetPCLK1Freq(void);
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetCPUFreq(void);
uint32_t CLK_GetPLLClockFreq(void);
void CLK_DisablePLL(void);
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
void CLK_EnableXtalRC(uint32_t u32ClkMask);
void CLK_DisableXtalRC(uint32_t u32ClkMask);
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
void CLK_DisableSysTick(void);
void CLK_SetPowerDownMode(uint32_t u32PDMode);
void CLK_EnableDPDWKPin(uint32_t u32Pin, uint32_t u32TriggerType);
void CLK_EnableDPDWKPin0(uint32_t u32TriggerType);
void CLK_EnableDPDWKPin1(uint32_t u32TriggerType);
void CLK_EnableDPDWKPin2(uint32_t u32TriggerType);
void CLK_EnableDPDWKPin3(uint32_t u32TriggerType);
void CLK_EnableDPDWKPin4(uint32_t u32TriggerType);
uint32_t CLK_GetPMUWKSrc(void);
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CLK_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __CLK_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file crc.h
* @version V0.10
* @brief M251 series Cyclic Redundancy Check(CRC) driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_H__
#define __CRC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* CRC Polynomial Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */
#define CRC_8 (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */
#define CRC_16 (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */
#define CRC_32 (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Checksum, Write data Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define CRC_CHECKSUM_COM (CRC_CTL_CHKSFMT_Msk) /*!<CRC Checksum Complement \hideinitializer */
#define CRC_CHECKSUM_RVS (CRC_CTL_CHKSREV_Msk) /*!<CRC Checksum Reverse \hideinitializer */
#define CRC_WDATA_COM (CRC_CTL_DATFMT_Msk) /*!<CRC Write Data Complement \hideinitializer */
#define CRC_WDATA_RVS (CRC_CTL_DATREV_Msk) /*!<CRC Write Data Reverse \hideinitializer */
/*---------------------------------------------------------------------------------------------------------------*/
/* CPU Write Data Length Constant Definitions */
/*---------------------------------------------------------------------------------------------------------------*/
#define CRC_CPU_WDATA_8 (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 8-bit \hideinitializer */
#define CRC_CPU_WDATA_16 (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 16-bit \hideinitializer */
#define CRC_CPU_WDATA_32 (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC CPU Write Data length is 32-bit \hideinitializer */
/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
@{
*/
/**
* @brief Set CRC Seed Value
*
* @param[in] u32Seed Seed value
*
* @return None
*
* @details This macro is used to set CRC seed value.
*
* @note User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
* to CRC controller.
*/
#define CRC_SET_SEED(u32Seed) do{ CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
/**
* @brief Get CRC Seed Value
*
* @param None
*
* @return CRC seed value
*
* @details This macro gets the current CRC seed value.
*/
#define CRC_GET_SEED() (CRC->SEED)
/**
* @brief CRC Write Data
*
* @param[in] u32Data Write data
*
* @return None
*
* @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
*/
#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
uint32_t CRC_GetChecksum(void);
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CRC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __CRC_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file crypto.h
* @version V1.10
* @brief Cryptographic Accelerator driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __CRYPTO_H__
#define __CRYPTO_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRYPTO_Driver CRYPTO Driver
@{
*/
/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
@{
*/
#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */
#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */
#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */
#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */
#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */
#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */
#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */
#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */
#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */
#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */
#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */
#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */
#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */
#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */
#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */
#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */
#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */
#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */
#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */
#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */
#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */
#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */
/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */
/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros
@{
*/
/*----------------------------------------------------------------------------------------------*/
/* Macros */
/*----------------------------------------------------------------------------------------------*/
/**
* @brief This macro enables PRNG interrupt.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
/**
* @brief This macro disables PRNG interrupt.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
/**
* @brief This macro gets PRNG interrupt flag.
* @param crpt Specified cripto module
* @return PRNG interrupt flag.
* \hideinitializer
*/
#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
/**
* @brief This macro clears PRNG interrupt flag.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
/**
* @brief This macro enables AES interrupt.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
/**
* @brief This macro disables AES interrupt.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
/**
* @brief This macro gets AES interrupt flag.
* @param crpt Specified cripto module
* @return AES interrupt flag.
* \hideinitializer
*/
#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
/**
* @brief This macro clears AES interrupt flag.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
/**
* @brief This macro enables AES key protection.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
/**
* @brief This macro disables AES key protection.
* @param crpt Specified cripto module
* @return None
* \hideinitializer
*/
#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_AES_CTL_KEYUNPRT_Pos)); \
((crpt)->AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)
/*@}*/ /* end of group CRYPTO_EXPORTED_MACROS */
/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Functions */
/*---------------------------------------------------------------------------------------------------------*/
void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
void PRNG_Start(CRPT_T *crpt);
void PRNG_Read(CRPT_T *crpt, uint32_t au32RandKey[]);
void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode);
void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]);
void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CRYPTO_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __CRYPTO_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file dac.h
* @version V0.10
* @brief M251 series DAC driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DAC_H__
#define __DAC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup DAC_Driver DAC Driver
@{
*/
/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* DAC_CTL Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. \hideinitializer */
#define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment \hideinitializer */
#define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger \hideinitializer */
#define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger \hideinitializer */
#define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger \hideinitializer */
#define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger \hideinitializer */
#define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger \hideinitializer */
#define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger \hideinitializer */
#define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger \hideinitializer */
#define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger \hideinitializer */
#define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger \hideinitializer */
#define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger \hideinitializer */
#define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable \hideinitializer */
#define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable \hideinitializer */
/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
@{
*/
/**
* @brief Start the D/A conversion.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
* \hideinitializer
*/
#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
/**
* @brief Enable DAC data left-aligned.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
* \hideinitializer
*/
#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
/**
* @brief Enable DAC data right-aligned.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
* \hideinitializer
*/
#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
/**
* @brief Enable output voltage buffer.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
* drive external loads directly without having to add an external operational amplifier.
* \hideinitializer
*/
#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
/**
* @brief Disable output voltage buffer.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details This macro is used to disable output voltage buffer.
* \hideinitializer
*/
#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
/**
* @brief Enable the interrupt.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @return None
* @details This macro is used to enable DAC interrupt.
* \hideinitializer
*/
#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
/**
* @brief Disable the interrupt.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @return None
* @details This macro is used to disable DAC interrupt.
* \hideinitializer
*/
#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
/**
* @brief Enable DMA under-run interrupt.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details This macro is used to enable DMA under-run interrupt.
* \hideinitializer
*/
#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
/**
* @brief Disable DMA under-run interrupt.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details This macro is used to disable DMA under-run interrupt.
* \hideinitializer
*/
#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
/**
* @brief Enable PDMA mode.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
* \hideinitializer
*/
#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
/**
* @brief Disable PDMA mode.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details This macro is used to disable DMA mode.
* \hideinitializer
*/
#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
/**
* @brief Write data for conversion.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
* @return None
* @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
* 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
* \hideinitializer
*/
#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
/**
* @brief Read DAC 12-bit holding data.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @return Return DAC 12-bit holding data.
* @details This macro is used to read DAC_DAT register.
* \hideinitializer
*/
#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
/**
* @brief Get the busy state of DAC.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @retval 0 Idle state.
* @retval 1 Busy state.
* @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
* \hideinitializer
*/
#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
/**
* @brief Get the interrupt flag.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @retval 0 DAC is in conversion state.
* @retval 1 DAC conversion finish.
* @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
* \hideinitializer
*/
#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
/**
* @brief Get the DMA under-run flag.
* @param[in] dac The pointer of the specified DAC module.
* @retval 0 No DMA under-run error condition occurred.
* @retval 1 DMA under-run error condition occurred.
* @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
* \hideinitializer
*/
#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
/**
* @brief This macro clear the interrupt status bit.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @return None
* @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
* \hideinitializer
*/
#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
/**
* @brief This macro clear the DMA under-run flag.
* @param[in] dac The pointer of the specified DAC module.
* @return None
* @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
* \hideinitializer
*/
#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
void DAC_Close(DAC_T *dac, uint32_t u32Ch);
uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group DAC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __DAC_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/eadc.h Normal file
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/****************************************************************************//**
* @file eadc.h
* @version V0.10
* @brief M251 series EADC driver header file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EADC_H__
#define __EADC_H__
/*---------------------------------------------------------------------------------------------------------*/
/* Include related headers */
/*---------------------------------------------------------------------------------------------------------*/
#include "M251.h"
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EADC_Driver EADC Driver
@{
*/
/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_SCTLn Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */
#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */
#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */
#define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */
#define EADC_FALLING_EDGE_TRIGGER ((1UL<<EADC_SCTL_TRGSEL_Pos) | EADC_SCTL_EXTFEN_Msk) /*!< STADC pin falling edge trigger */
#define EADC_RISING_EDGE_TRIGGER ((1UL<<EADC_SCTL_TRGSEL_Pos) | EADC_SCTL_EXTREN_Msk) /*!< STADC pin rising edge trigger */
#define EADC_FALLING_RISING_EDGE_TRIGGER ((1UL<<EADC_SCTL_TRGSEL_Pos) | EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk) /*!< STADC pin both falling and rising edge trigger */
#define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< EADC ADINT0 interrupt EOC pulse trigger */
#define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< EADC ADINT1 interrupt EOC pulse trigger */
#define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */
#define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */
#define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */
#define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */
#define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG0 trigger */
#define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG1 trigger */
#define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG2 trigger */
#define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG3 trigger */
#define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG4 trigger */
#define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG5 trigger */
#define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG0 trigger */
#define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG1 trigger */
#define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG2 trigger */
#define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG3 trigger */
#define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG4 trigger */
#define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG5 trigger */
#define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger */
#define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */
#define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_CMPn Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */
#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
#define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */
#define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */
#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */
#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_MnCTL1 Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_MCTL1_ACU_1 (0x0UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 1 time */
#define EADC_MCTL1_ACU_2 (0x1UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 2 times */
#define EADC_MCTL1_ACU_4 (0x2UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 4 times */
#define EADC_MCTL1_ACU_8 (0x3UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 8 times */
#define EADC_MCTL1_ACU_16 (0x4UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 16 times */
#define EADC_MCTL1_ACU_32 (0x5UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 32 times */
#define EADC_MCTL1_ACU_64 (0x6UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 64 times */
#define EADC_MCTL1_ACU_128 (0x7UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 128 times */
#define EADC_MCTL1_ACU_256 (0x8UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 256 times */
/*---------------------------------------------------------------------------------------------------------*/
/* EADC_PWRCTL Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EADC_PWRCTL_AUTOPDTHT_1 (0x0UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 1 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_2 (0x1UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 2 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_3 (0x2UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 3 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_4 (0x3UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 4 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_5 (0x4UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 5 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_6 (0x5UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 6 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_7 (0x6UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 7 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_8 (0x7UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 8 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_16 (0x8UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 16 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_32 (0x9UL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 32 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_64 (0xAUL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 64 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_128 (0xBUL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 128 EADC clock */
#define EADC_PWRCTL_AUTOPDTHT_256 (0xCUL<<EADC_PWRCTL_AUTOPDTHT_Pos) /*!< Auto Power Down Threshold Time 256 EADC clock */
/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* EADC Macro Definitions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief A/D Converter Control Circuits Reset.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details ADCRST bit (EADC_CTL[1]) remains 1 during EADC reset, when EADC reset end, the ADCRST bit is automatically cleared to 0.
*/
#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
/**
* @brief Enable PDMA transfer.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n=0~15) register,
* user can enable this bit to generate a PDMA data transfer request.
*/
#define EADC_ENABLE_PDMA(eadc, u32ModuleNum) (eadc)->PDMACTL |= (0x1 << u32ModuleNum)
/**
* @brief Disable PDMA transfer.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details This macro is used to disable PDMA transfer.
*/
#define EADC_DISABLE_PDMA(eadc, u32ModuleNum) (eadc)->PDMACTL &= ~(0x1 << u32ModuleNum)
/**
* @brief Set ADIFn at A/D start of conversion.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details The A/D converter generates ADIFn (EADC_STATUS2[n], n=0~3) at the start of conversion.
*/
#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((((eadc)->SCTL[(u32ModuleNum)])) |= EADC_SCTL_INTPOS_Msk)
/**
* @brief Set ADIFn at A/D end of conversion.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details The A/D converter generates ADIFn (EADC_STATUS2[n], n=0~3) at the end of conversion.
*/
#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((((eadc)->SCTL[(u32ModuleNum)])) &= (~EADC_SCTL_INTPOS_Msk))
/**
* @brief Enable the interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
* This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
* @return None
* @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n], n=0~3) upon the end of specific sample module A/D conversion.
* If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
*/
#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
/**
* @brief Disable the interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
* This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
* @return None
* @details Specific sample module A/D ADINT0 interrupt function disabled.
*/
#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= (~((u32Mask) << EADC_CTL_ADCIEN0_Pos)))
/**
* @brief Enable the sample module interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
* This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
* @return None
* @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
*/
#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((((eadc)->INTSRC[(u32IntSel)])) |= (u32ModuleMask))
/**
* @brief Disable the sample module interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
* This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
* @return None
* @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
*/
#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((((eadc)->INTSRC[(u32IntSel)])) &= (~(u32ModuleMask)))
/**
* @brief Start the A/D conversion.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
* This parameter decides which sample module will be converted, valid range are between 1~0x7FFFF.
* Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
* @return None
* @details After write EADC_SWTRG register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
*/
#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
/**
* @brief Cancel the conversion for sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
* This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
* Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
* @return None
* @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
*/
#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
/**
* @brief Get the conversion pending flag.
* @param[in] eadc The pointer of the specified EADC module.
* @return Return the conversion pending sample module.
* @details This STPFn (EADC_PENDSTS[n], n=0~18) bit remains 1 during pending state, when the respective EADC conversion is end,
* the STPFn (EADC_PENDSTS[n], n=0~18) bit is automatically cleared to 0.
*/
#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
/**
* @brief Get the conversion data of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
* @return Return the conversion data of the user-specified sample module.
* @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
*/
#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((((eadc)->DAT[(u32ModuleNum)])) & EADC_DAT_RESULT_Msk)
/**
* @brief Get the data overrun flag of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
* @return Return the data overrun flag of the user-specified sample module.
* @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
*/
#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
/**
* @brief Get the data valid flag of the user-specified sample module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
* @return Return the data valid flag of the user-specified sample module.
* @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data overrun status.
*/
#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
/**
* @brief Get the user-specified interrupt flags.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
* Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
* Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
* Or use combination of following pre-define mask:
* - \ref EADC_STATUS2_ADIF0_Msk : ADIF0 mask
* - \ref EADC_STATUS2_ADIF1_Msk : ADIF1 mask
* - \ref EADC_STATUS2_ADIF2_Msk : ADIF2 mask
* - \ref EADC_STATUS2_ADIF3_Msk : ADIF3 mask
* - \ref EADC_STATUS2_ADCMPF0_Msk : ADCMPF0 mask
* - \ref EADC_STATUS2_ADCMPF1_Msk : ADCMPF1 mask
* - \ref EADC_STATUS2_ADCMPF2_Msk : ADCMPF2 mask
* - \ref EADC_STATUS2_ADCMPF3_Msk : ADCMPF3 mask
* @return Return the user-specified interrupt flags.
* @details This macro is used to get the user-specified interrupt flags.
*/
#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
/**
* @brief Get the user-specified sample module overrun flags.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
* @return Return the user-specified sample module overrun flags.
* @details This macro is used to get the user-specified sample module overrun flags.
*/
#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
/**
* @brief Clear the selected interrupt status bits.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
* Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
* Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
* Or use combination of following pre-define mask:
* - \ref EADC_STATUS2_ADIF0_Msk : ADIF0 mask
* - \ref EADC_STATUS2_ADIF1_Msk : ADIF1 mask
* - \ref EADC_STATUS2_ADIF2_Msk : ADIF2 mask
* - \ref EADC_STATUS2_ADIF3_Msk : ADIF3 mask
* - \ref EADC_STATUS2_ADCMPF0_Msk : ADCMPF0 mask
* - \ref EADC_STATUS2_ADCMPF1_Msk : ADCMPF1 mask
* - \ref EADC_STATUS2_ADCMPF2_Msk : ADCMPF2 mask
* - \ref EADC_STATUS2_ADCMPF3_Msk : ADCMPF3 mask
* @return None
* @details This macro is used to clear clear the selected interrupt status bits.
*/
#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
/**
* @brief Clear the selected sample module overrun status bits.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
* Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
* @return None
* @details This macro is used to clear the selected sample module overrun status bits.
*/
#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
/**
* @brief Check all sample module A/D result data register overrun flags.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of sample module data register overrun flag is set to 1.
* @retval 1 Any one of sample module data register overrun flag is set to 1.
* @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16], n=0~18) is set to 1.
*/
#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
/**
* @brief Check all sample module A/D result data register valid flags.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of sample module data register valid flag is set to 1.
* @retval 1 Any one of sample module data register valid flag is set to 1.
* @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17], n=0~18) is set to 1.
*/
#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
/**
* @brief Check all A/D sample module start of conversion overrun flags.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of sample module event overrun flag is set to 1.
* @retval 1 Any one of sample module event overrun flag is set to 1.
* @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n], n=0~18) is set to 1.
*/
#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
/**
* @brief Check all A/D interrupt flag overrun bits.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 None of ADINT interrupt flag is overwritten to 1.
* @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
* @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[n+8], n=0~3) is overwritten to 1.
*/
#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
/**
* @brief Get the busy state of EADC.
* @param[in] eadc The pointer of the specified EADC module.
* @retval 0 Idle state.
* @retval 1 Busy state.
* @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
*/
#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
/**
* @brief Configure the comparator 0 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid values are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition is "greater than or equal to the compare value"
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
* @return None
* @details For example, EADC_ENABLE_CMP0(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
* Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
*/
#define EADC_ENABLE_CMP0(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[0] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\
EADC_CMP_ADCMPEN_Msk))
/**
* @brief Configure the comparator 1 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition s "greater than or equal to the compare value"
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
* @return None
* @details For example, EADC_ENABLE_CMP1(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
* Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
*/
#define EADC_ENABLE_CMP1(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[1] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\
EADC_CMP_ADCMPEN_Msk))
/**
* @brief Configure the comparator 2 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition is "greater than or equal to the compare value"
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
* @return None
* @details For example, EADC_ENABLE_CMP2(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
* Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
*/
#define EADC_ENABLE_CMP2(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[2] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\
EADC_CMP_ADCMPEN_Msk))
/**
* @brief Configure the comparator 3 and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
* @param[in] u32Condition specifies the compare condition. Valid values are:
* - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value"
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition is "greater than or equal to the compare value"
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
* @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
* @return None
* @details For example, EADC_ENABLE_CMP3(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10);
* Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
*/
#define EADC_ENABLE_CMP3(eadc,\
u32ModuleNum,\
u32Condition,\
u16CMPData,\
u32MatchCount) ((eadc)->CMP[3] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\
EADC_CMP_ADCMPEN_Msk))
/**
* @brief Enable the compare window mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid values are 0 and 2.
* @return None
* @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
* ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
*/
#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) |= EADC_CMP_CMPWEN_Msk)
/**
* @brief Disable the compare window mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid values are 0 and 2.
* @return None
* @details ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
* ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
*/
#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) &= (~EADC_CMP_CMPWEN_Msk))
/**
* @brief Enable the compare interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid values are from 0 to 3.
* @return None
* @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
* and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[n+4], n=0~3) will be asserted, in the meanwhile,
* if ADCMPIE (EADC_CMPn[1], n=0~3) is set to 1, a compare interrupt request is generated.
*/
#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) |= EADC_CMP_ADCMPIE_Msk)
/**
* @brief Disable the compare interrupt.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
* @return None
* @details This macro is used to disable the compare interrupt.
*/
#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) &= (~EADC_CMP_ADCMPIE_Msk))
/**
* @brief Disable comparator 0.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 0.
*/
#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] &= (~EADC_CMP_ADCMPEN_Msk))
/**
* @brief Disable comparator 1.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 1.
*/
#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] &= (~EADC_CMP_ADCMPEN_Msk))
/**
* @brief Disable comparator 2.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 2.
*/
#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] &= (~EADC_CMP_ADCMPEN_Msk))
/**
* @brief Disable comparator 3.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details This macro is used to disable comparator 3.
*/
#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] &= (~EADC_CMP_ADCMPEN_Msk))
/**
* @brief Enable conversion result left alignment.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details The 12-bit conversion result will be left aligned and stored in EADC_DATn[15:4] (n=0~15).
*/
#define EADC_ENABLE_LEFT_ALIGN(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) |= EADC_MCTL1_ALIGN_Msk)
/**
* @brief Disable conversion result left alignment.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details The 12-bit conversion result will be right aligned and stored in EADC_DATn[11:0] (n=0~15).
*/
#define EADC_DISABLE_LEFT_ALIGN(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_ALIGN_Msk))
/**
* @brief Enable average mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details Conversion results in data register will be averaged.
* @note This average mode needs to work with accumulated mode that configured by ACU (EADC_MnCTL1[7:4], n=0~15) bit field.
*/
#define EADC_ENABLE_AVG(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) |= EADC_MCTL1_AVG_Msk)
/**
* @brief Disable average mode.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @return None
* @details Conversion results in data register will not be averaged.
*/
#define EADC_DISABLE_AVG(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_AVG_Msk))
/**
* @brief Configure the Accumulation feature and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 15.
* @param[in] u16ACUNum specifies the number of accumulation, valid values are
* - \ref EADC_MCTL1_ACU_1 : 1 conversion result will be accumulated.
* - \ref EADC_MCTL1_ACU_2 : 2 conversion result will be accumulated.
* - \ref EADC_MCTL1_ACU_4 : 4 conversion result will be accumulated.
* - \ref EADC_MCTL1_ACU_8 : 8 conversion result will be accumulated.
* - \ref EADC_MCTL1_ACU_16 : 16 conversion result will be accumulated.
* - \ref EADC_MCTL1_ACU_32 : 32 conversion result will be accumulated. The result is right shift 1 bit to fit within the available 16-bit register size.
* - \ref EADC_MCTL1_ACU_64 : 64 conversion result will be accumulated. The result is right shift 2 bits to fit within the available 16-bit register size.
* - \ref EADC_MCTL1_ACU_128 : 128 conversion result will be accumulated. The result is right shift 3 bits to fit within the available 16-bit register size.
* - \ref EADC_MCTL1_ACU_256 : 256 conversion result will be accumulated. The result is right shift 4 bits to fit within the available 16-bit register size.
* @return None
* @details When accumulating more than 16 samples, the result will be too large to match the
* 16-bit RESULT register size (EADC_DATn[15:0]. To avoid overflow, the result is
* right shifted automatically to fit within the available 16-bit register size.
* The number of automatic right shifts is specified in parameter list above.
*
*/
#define EADC_ENABLE_ACU(eadc,\
u32ModuleNum,\
u16ACUNum) ((((eadc)->MCTL1[(u32ModuleNum)])) = (((((eadc)->MCTL1[(u32ModuleNum)])) & (~EADC_MCTL1_ACU_Msk)) |\
(u16ACUNum)))
/**
* @brief Disable the Accumulation feature.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 15.
* @return None
*/
#define EADC_DISABLE_ACU(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_ACU_Msk))
/**
* @brief Configure the Auto Power On/Off mode and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32PowerOffThreshold specifies the auto power off threshold time. Valid values are:
* - \ref EADC_PWRCTL_AUTOPDTHT_1 : Auto Power Off Threshold Time 1 EADC clock
* - \ref EADC_PWRCTL_AUTOPDTHT_2 : Auto Power Off Threshold Time 2 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_3 : Auto Power Off Threshold Time 3 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_4 : Auto Power Off Threshold Time 4 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_5 : Auto Power Off Threshold Time 5 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_6 : Auto Power Off Threshold Time 6 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_7 : Auto Power Off Threshold Time 7 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_8 : Auto Power Off Threshold Time 8 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_16 : Auto Power Off Threshold Time 16 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_32 : Auto Power Off Threshold Time 32 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_64 : Auto Power Off Threshold Time 64 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_128 : Auto Power Off Threshold Time 128 EADC clocks
* - \ref EADC_PWRCTL_AUTOPDTHT_256 : Auto Power Off Threshold Time 256 EADC clocks
* @param[in] u32PowerOnTime specifies the auto power on start-up time, valid range are between 0~0xFFF.
* @return None
* @details If the interval of time in idle state is longer than u32PowerOffThreshold, EADC will
* auto power off A/D converter analog circuit to reduce power consumption.
* EADC will automatically wakes-up when a conversion is started by software or hardware trigger.
* A start-up time is automatically inserted between the trigger event and the sampling time of the EADC.
* The start-up time = ((1/EADC_CLK) * u32PowerOnTime) and must be longer than 10us.
* @note The ADCEN bit (EADC_CTL[0]) will be set to 0 when EADC power off and set to 1 when EADC be wake-up.
*/
#define EADC_ENABLE_AUTOFF(eadc,\
u32PowerOffThreshold,\
u32PowerOnTime) ((eadc)->PWRCTL = ((u32PowerOffThreshold) |\
((u32PowerOnTime) << EADC_PWRCTL_STUPT_Pos) |\
EADC_PWRCTL_AUTOFF_Msk))
/**
* @brief Disable the Auto Power On/Off mode.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
*/
#define EADC_DISABLE_AUTOFF(eadc) ((eadc)->PWRCTL &= (~EADC_PWRCTL_AUTOFF_Msk))
/**
* @brief Configure the Offset Cancellation feature and enable it.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] i16OffsetCancel specifies the signed value of offset cancellation, valid values are -16 to 15.
* @return None
* @details When i16OffsetCancel is set to 0, the offset cancellation trim bits have no effect to A/D result.
*/
#define EADC_ENABLE_OFFSETCANCEL(eadc,\
i16OffsetCancel) {(eadc)->CTL |= EADC_CTL_CALEN_Msk;\
(eadc)->OFFSETCAL = (i16OffsetCancel & EADC_OFFSETCAL_OFFSETCANCEL_Msk);}
/**
* @brief Disable the Offset Cancellation feature.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
*/
#define EADC_DISABLE_OFFSETCANCEL(eadc) {(eadc)->OFFSETCAL = 0;\
(eadc)->CTL &= (~EADC_CTL_CALEN_Msk);}
/*---------------------------------------------------------------------------------------------------------*/
/* Define EADC functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
void EADC_Close(EADC_T *eadc);
void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel);
void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EADC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __EADC_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file ebi.h
* @version V0.10
* @brief M251 series EBI driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
****************************************************************************/
#ifndef __EBI_H__
#define __EBI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EBI_Driver EBI Driver
@{
*/
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */
#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */
#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */
#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI bank number */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */
#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */
#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI data bus width */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */
#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI CS Active Level */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */
#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Constants for EBI MCLK divider and Timing */
/*---------------------------------------------------------------------------------------------------------*/
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */
#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */
#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */
#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
/** @addtogroup M251_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @brief Read 8-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank0
*
* @param[in] u32Addr The data address on EBI bank0.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank0.
* \hideinitializer
*/
#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 8-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank1
*
* @param[in] u32Addr The data address on EBI bank1.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank1.
* \hideinitializer
*/
#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 8-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 8-bit Data
*
* @details This macro is used to read 8-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 8-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 8-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 16-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 16-bit Data
*
* @details This macro is used to read 16-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 16-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 16-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Read 32-bit data on EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
*
* @return 32-bit Data
*
* @details This macro is used to read 32-bit data from specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
/**
* @brief Write 32-bit data to EBI bank2
*
* @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written.
*
* @return None
*
* @details This macro is used to write 32-bit data to specify address on EBI bank2.
* \hideinitializer
*/
#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
/**
* @brief Enable EBI Write Buffer
*
* @param None
*
* @return None
*
* @details This macro is used to improve EBI write operation for EBI bank0 and bank1.
* \hideinitializer
*/
#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk);
/**
* @brief Disable EBI Write Buffer
*
* @param None
*
* @return None
*
* @details This macro is used to disable EBI write buffer function.
* \hideinitializer
*/
#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk);
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
void EBI_Close(uint32_t u32Bank);
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EBI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __EBI_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file fmc.h
* @version V3.0
* @brief M251 Series Flash Memory Controller(FMC) driver header file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __FMC_H__
#define __FMC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup FMC_Driver FMC Driver
@{
*/
/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Global constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define ISBEN 0
/*---------------------------------------------------------------------------------------------------------*/
/* Define Base Address */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
#define FMC_APROM_END 0x00040000UL /*!< APROM end address */
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address */
#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */
#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
#define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */
#define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 0x4UL) /*!< CONFIG 1 Address */
#define FMC_CONFIG2_ADDR (FMC_CONFIG_BASE + 0x8UL) /*!< CONFIG 2 Address */
#define FMC_XOMR0BASE_ADDR (FMC_XOM_BASE) /*!< XOMR 0 Base Address */
#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */
#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) */
#define FMC_FLASH_PAGE_SIZE 0x200UL /*!< Flash Page Size (512 Bytes) */
#define FMC_PAGE_ADDR_MASK 0xFFFFFE00UL /*!< Flash page address mask */
/*---------------------------------------------------------------------------------------------------------*/
/* ISPCTL constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_ISPCTL_BS_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */
#define FMC_ISPCTL_BS_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */
/*---------------------------------------------------------------------------------------------------------*/
/* ISPCMD constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */
#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */
#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */
#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */
#define FMC_ISPCMD_READ_PID 0x0CUL /*!< ISP Command: Read Device ID */
#define FMC_ISPCMD_CHECKSUM 0x0DUL /*!< ISP Command: Read Checksum */
#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */
#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */
#define FMC_ISPCMD_MULTI_PROG 0x27UL /*!< ISP Command: Flash Multi-Word Program */
#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification*/
#define FMC_ISPCMD_CAL_CHECKSUM 0x2DUL /*!< ISP Command: Run Check Calculation */
#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */
#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */
#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */
#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */
/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* FMC Macro Definitions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief Enable ISP Function
*
* @param None
*
* @return None
*
* @details This function will set ISPEN bit of ISPCTL control register to enable ISP function.
*
*/
#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */
/**
* @brief Disable ISP Function
*
* @param None
*
* @return None
*
* @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
*
*/
#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */
/**
* @brief Enable LDROM Update Function
*
* @param None
*
* @return None
*
* @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.
* User needs to set LDUEN bit before they can update LDROM.
*
*/
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */
/**
* @brief Disable LDROM Update Function
*
* @param None
*
* @return None
*
* @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
*
*/
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */
/**
* @brief Enable User Configuration Update Function
*
* @param None
*
* @return None
*
* @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
* User needs to set CFGUEN bit before they can update User Configuration area.
*
*/
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
/**
* @brief Disable User Configuration Update Function
*
* @param None
*
* @return None
*
* @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
*
*/
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
/**
* @brief Enable APROM Update Function
*
* @param None
*
* @return None
*
* @details This function will set APUEN bit of ISPCTL control register to enable APROM update function.
* User needs to set APUEN bit before they can update APROM in APROM boot mode.
*
*/
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */
/**
* @brief Disable APROM Update Function
*
* @param None
*
* @return None
*
* @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
*
*/
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */
/**
* @brief Next Booting Selection function
*
* @param[in] x Booting from APROM(0)/LDROM(1)
*
* @return None
*
* @details This function will set MCU next booting from LDROM/APROM.
*
* @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set.
*
*/
#define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */
/**
* @brief Get MCU Booting Status
*
* @param None
*
* @return None
*
* @details This function will get status of chip next booting from LDROM/APROM.
*
*/
#define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */
/**
* @brief Get ISP fail flag
*
* @param None
*
* @return None
*
* @details This function will get the status of ISP falil flag
*
*/
#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */
/**
* @brief Clear ISP fail flag
*
* @param None
*
* @return None
*
* @details This function will clear the status of ISP falil flag
*
*/
#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */
/**
* @brief Disable APROM update function
*
* @param None
*
* @return None
*
* @details Disable APROM update function will forbid APROM programming when boot form APROM.
* APROM update is default to be disable.
*
*/
#define FMC_DisableAPUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable AP update */
/**
* @brief Disable User Configuration update function
*
* @param None
*
* @return None
*
* @details Disable User Configuration update function will forbid User Configuration programming.
* User Configuration update is default to be disable.
*/
#define FMC_DisableConfigUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable config update */
/**
* @brief Disable LDROM update function
*
* @param None
*
* @return None
* @details Disable LDROM update function will forbid LDROM programming.
* LDROM update is default to be disable.
*/
#define FMC_DisableLDUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LD update */
/**
* @brief Enable APROM update function
*
* @param None
*
* @return None
*
* @details Enable APROM to be able to program when boot from APROM.
*
*/
#define FMC_EnableAPUpdate() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable AP update */
/**
* @brief Enable User Configuration update function
*
* @param None
*
* @return None
*
* @details Enable User Configuration to be able to program.
*
*/
#define FMC_EnableConfigUpdate() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable config update */
/**
* @brief Enable LDROM update function
*
* @param None
*
* @return None
*
* @details Enable LDROM to be able to program.
*
*/
#define FMC_EnableLDUpdate() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LD update */
/*---------------------------------------------------------------------------------------------------------*/
/* inline functions */
/*---------------------------------------------------------------------------------------------------------*/
static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index);
static __INLINE uint32_t FMC_ReadCID(void);
static __INLINE uint32_t FMC_ReadPID(void);
static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);
static __INLINE uint32_t FMC_ReadVBGCode(void);
static __INLINE uint32_t FMC_ReadVTEMPCode(void);
static __INLINE uint32_t FMC_ReadADCOffset(void);
static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
static __INLINE uint32_t FMC_GetVECMAP(void);
static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size);
static __INLINE void FMC_Write128(uint32_t u32Addr, uint32_t pu32Buf[]);
/**
* @brief Read Unique ID
*
* @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
*
* @return The 32-bit unique ID data of specified UID index.
*
* @details To read out 96-bit Unique ID.
*
*/
static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID;
FMC->ISPADDR = ((uint32_t)u8Index << 2u);
FMC->ISPDAT = 0u;
FMC->ISPTRG = 0x1u;
#if ISBEN
__ISB();
#endif
while (FMC->ISPTRG) {}
return FMC->ISPDAT;
}
/**
* @brief Read company ID
*
* @param None
*
* @return The company ID (32-bit)
*
* @details The company ID of Nuvoton is fixed to be 0xDA
*
*/
static __INLINE uint32_t FMC_ReadCID(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Read product ID
*
* @param None
*
* @return The product ID (32-bit)
*
* @details This function is used to read product ID.
*
*/
static __INLINE uint32_t FMC_ReadPID(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_PID; /* Set ISP Command Code */
FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief To read UCID
*
* @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
*
* @return The UCID of specified index
*
* @details This function is used to read unique chip ID (UCID).
*
*/
static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief To read bang-gap voltage code
*
* @param[in] None
*
* @return The bang-gap voltage code
*
* @details This function is used to read bang-gap voltage code
*
*/
static __INLINE uint32_t FMC_ReadVBGCode(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
FMC->ISPADDR = 0x70; /* The VBG is at offset 0x70 with word alignment. */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief To read the temperature sensor ADC code
*
* @param[in] None
*
* @return The temperature sensor ADC code
*
* @details This function is used to read temperature sensor ADC code
*
*/
static __INLINE uint32_t FMC_ReadVTEMPCode(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
FMC->ISPADDR = 0x74; /* The VTEMP code is at offset 0x74 with word alignment */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief To read the calibration value for ADC offset
*
* @param[in] None
*
* @return The calibration value for ADC offset
*
* @details This function is used to read the calibration value for ADC offset
*
*/
static __INLINE uint32_t FMC_ReadADCOffset(void)
{
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
FMC->ISPADDR = 0x78; /* The calibration value for ADC offset is at offset 0x78 with word alignment */
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
return FMC->ISPDAT;
}
/**
* @brief Set vector mapping address
*
* @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
*
* @return To set VECMAP to remap specified page address to 0x0.
*
* @details This function is used to set VECMAP to map specified page to vector page (0x0).
*
* @note
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
*
*/
static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
{
FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */
#if ISBEN
__ISB();
#endif /* To make sure ISP/CPU be Synchronized */
while (FMC->ISPTRG) {} /* Waiting for ISP Done */
}
/**
* @brief Get current vector mapping address.
*
* @param None
*
* @return The current vector mapping address.
*
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
*
* @note
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
*
*/
static __INLINE uint32_t FMC_GetVECMAP(void)
{
return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
}
/**
* @brief Get Flash Checksum
*
* @param[in] u32Addr Specific flash start address
* @param[in] i32Size Specific a size of Flash area
*
* @return A checksum value of a flash block.
*
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
*
*/
static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size)
{
FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
FMC->ISPADDR = u32Addr;
FMC->ISPDAT = (uint32_t)i32Size;
FMC->ISPTRG = 0x1u;
#if ISBEN
__ISB();
#endif
while (FMC->ISPTRG) {}
FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
FMC->ISPTRG = 0x1u;
while (FMC->ISPTRG) {}
return FMC->ISPDAT;
}
/**
* @brief Program Multi-Word data into specified address of flash
*
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
* @param[in] pu32Buf A data pointer is point to a data buffer start address;
*
* @return None
*
* @details To program multi-words data into Flash include APROM, LDROM, and CONFIG.
*
*/
static __INLINE void FMC_Write128(uint32_t u32Addr, uint32_t pu32Buf[])
{
uint32_t i, idx, u32OnProg;
int32_t err;
idx = 0u;
FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
FMC->ISPADDR = u32Addr;
do
{
err = 0;
u32OnProg = 1u;
FMC->MPDAT0 = pu32Buf[idx + 0u];
FMC->MPDAT1 = pu32Buf[idx + 1u];
FMC->MPDAT2 = pu32Buf[idx + 2u];
FMC->MPDAT3 = pu32Buf[idx + 3u];
FMC->ISPTRG = 0x1u;
idx += 4u;
for (i = idx; i < 128u / 4u; i += 4u) /* Max data length is 128 bytes (128/4 words)*/
{
__set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/
do
{
if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
{
__set_PRIMASK(0u);
FMC->ISPADDR = FMC->MPADDR & (~0xful);
idx = (FMC->ISPADDR - u32Addr) / 4u;
err = -1;
}
}
while ((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0));
if (err == 0)
{
/* Update new data for D0 */
FMC->MPDAT0 = pu32Buf[i];
FMC->MPDAT1 = pu32Buf[i + 1u];
do
{
if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
{
__set_PRIMASK(0u);
FMC->ISPADDR = FMC->MPADDR & (~0xful);
idx = (FMC->ISPADDR - u32Addr) / 4u;
err = -1;
}
}
while ((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0));
if (err == 0)
{
/* Update new data for D2*/
FMC->MPDAT2 = pu32Buf[i + 2u];
FMC->MPDAT3 = pu32Buf[i + 3u];
__set_PRIMASK(0u);
}
}
if (err < 0)
{
break;
}
}
if (err == 0)
{
u32OnProg = 0u;
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {}
}
}
while (u32OnProg);
}
void FMC_Open(void);
void FMC_Close(void);
int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count);
void FMC_SetBootSource(int32_t i32BootSrc);
int32_t FMC_GetBootSource(void);
uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
int32_t FMC_Is_XOM_Actived(uint32_t xom_num);
int32_t FMC_Erase_XOM(uint32_t xom_num);
int32_t FMC_Erase(uint32_t u32Addr);
int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page);
uint32_t FMC_Read(uint32_t u32Addr);
void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group FMC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __FMC_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/gpio.h Normal file
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/**************************************************************************//**
* @file crc.h
* @version V0.10
* @brief M251 series GPIO driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
@{
*/
#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port */
/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
Example 1:
PA0 = 1;
It is used to set GPIO PA.0 to high;
Example 2:
if (PA0)
PA0 = 0;
If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
*/
#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */
#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
#define PF14 GPIO_PIN_DATA(5, 14) /*!< Specify PF.14 Pin Data Input/Output */
/*---------------------------------------------------------------------------------------------------------*/
/* PMD Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO_INTTYPE Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Slew Rate Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for nornal Mode */
#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Pull-up And Pull-down Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */
#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */
#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO_DBCTL Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_DBCTL_ICLK_ON 0x003F0000UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 32k Hz */
#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
/**
* @brief Clear GPIO Pin Interrupt Flag
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Clear the interrupt status of specified GPIO pin.
*/
#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
/**
* @brief Disable Pin De-bounce Function
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Disable the interrupt de-bounce function of specified GPIO pin.
*/
#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
/**
* @brief Enable Pin De-bounce Function
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Enable the interrupt de-bounce function of specified GPIO pin.
*/
#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
/**
* @brief Disable I/O Digital Input Path
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Disable I/O digital input path of specified GPIO pin.
*/
#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
/**
* @brief Enable I/O Digital Input Path
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Enable I/O digital input path of specified GPIO pin.
*/
#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
/**
* @brief Disable I/O DOUT mask
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Disable I/O DOUT mask of specified GPIO pin.
*/
#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
/**
* @brief Enable I/O DOUT mask
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details Enable I/O DOUT mask of specified GPIO pin.
*/
#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
/**
* @brief Get GPIO Pin Interrupt Flag
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @retval 0 No interrupt at specified GPIO pin
* @retval 1 The specified GPIO pin generate an interrupt
*
* @details Get the interrupt status of specified GPIO pin.
*/
#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
/**
* @brief Set De-bounce Sampling Cycle Time
*
* @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
* @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
* - \ref GPIO_DBCTL_DBCLKSEL_1
* - \ref GPIO_DBCTL_DBCLKSEL_2
* - \ref GPIO_DBCTL_DBCLKSEL_4
* - \ref GPIO_DBCTL_DBCLKSEL_8
* - \ref GPIO_DBCTL_DBCLKSEL_16
* - \ref GPIO_DBCTL_DBCLKSEL_32
* - \ref GPIO_DBCTL_DBCLKSEL_64
* - \ref GPIO_DBCTL_DBCLKSEL_128
* - \ref GPIO_DBCTL_DBCLKSEL_256
* - \ref GPIO_DBCTL_DBCLKSEL_512
* - \ref GPIO_DBCTL_DBCLKSEL_1024
* - \ref GPIO_DBCTL_DBCLKSEL_2048
* - \ref GPIO_DBCTL_DBCLKSEL_4096
* - \ref GPIO_DBCTL_DBCLKSEL_8192
* - \ref GPIO_DBCTL_DBCLKSEL_16384
* - \ref GPIO_DBCTL_DBCLKSEL_32768
*
* @return None
*
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
* Example: GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
* It's meaning the debounce counter clock source is internal 38.4 KHz and sampling cycle selection is 4. \n
* Then the target de-bounce sampling cycle time is (4)*(1/(38.4*1000)) s = 1.04*0.0001 s = 104 us,
* and system will sampling interrupt input once per 104 us.
* Note: all GPIO ports use the same debounce source clock and de-bounce sampling cycle, but each port can close
* its clock source for power saving by setting ICLKONx bit to 0.
*/
#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = ((GPIO_DBCTL_ICLK_ON) | (u32ClkSrc) | (u32ClkSel) ))
/**
* @brief Set GPIO Interrupt Clock on bit
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
*
* @return None
*
* @details Set the I/O pins edge detection circuit always active after reset for specified port.
*/
#define GPIO_SET_DEBOUNCE_ICLKON(port) (GPIO->DBCTL |= ((0x1UL << ((((uint32_t)port - (uint32_t)GPIO_BASE) / 0x40) + 16))))
/**
* @brief Clear GPIO Interrupt Clock on bit
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
*
* @return None
*
* @details Set edge detection circuit active only if I/O pin edge interrupt enabled for specified port
*/
#define GPIO_CLR_DEBOUNCE_ICLKON(port) (GPIO->DBCTL &= ~((0x1UL << ((((uint32_t)port - (uint32_t)GPIO_BASE) / 0x40) + 16))))
/**
* @brief Get GPIO Port IN Data
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
*
* @return The specified port data
*
* @details Get the PIN register of specified GPIO port.
*/
#define GPIO_GET_IN_DATA(port) ((port)->PIN)
/**
* @brief Set GPIO Port OUT Data
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32Data GPIO port data.
*
* @return None
*
* @details Set the Data into specified GPIO port.
*/
#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
/**
* @brief Toggle Specified GPIO pin
*
* @param[in] u32Pin Pxy
*
* @return None
*
* @details Toggle the specified GPIO pint.
*/
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
/**
* @brief Enable External GPIO interrupt
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32Pin The pin of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_EnableEINT GPIO_EnableInt
/**
* @brief Disable External GPIO interrupt
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32Pin The pin of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_DisableEINT GPIO_DisableInt
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group GPIO_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/i2c.h Normal file
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/**************************************************************************//**
* @file I2C.h
* @version V0.10
* @brief M251 Series I2C Driver Header File
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup I2C_Driver I2C Driver
@{
*/
/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* I2C_CTL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */
#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */
#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */
#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */
#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit */
#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */
#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit */
#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit */
#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit */
/*---------------------------------------------------------------------------------------------------------*/
/* I2C GCMode constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */
#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* I2C SMBUS constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable */
#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable */
#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function */
#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function */
/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
@{
*/
/**
* @brief The macro is used to set I2C bus condition at One Time
*
* @param[in] i2c Specify I2C port
* @param[in] u8Ctrl A byte writes to I2C control register
*
* @return None
*
* @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
*/
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
/**
* @brief The macro is used to set START condition of I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Set the I2C bus START condition in I2C_CTL register.
*/
#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
/**
* @brief The macro is used to wait I2C bus status get ready
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
*/
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
/**
* @brief The macro is used to Read I2C Bus Data Register
*
* @param[in] i2c Specify I2C port
*
* @return A byte of I2C data register
*
* @details I2C controller read data from bus and save it in I2CDAT register.
*/
#define I2C_GET_DATA(i2c) ((i2c)->DAT)
/**
* @brief Write a Data to I2C Data Register
*
* @param[in] i2c Specify I2C port
* @param[in] u8Data A byte that writes to data register
*
* @return None
*
* @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
*/
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
/**
* @brief Get I2C Bus status code
*
* @param[in] i2c Specify I2C port
*
* @return I2C status code
*
* @details To get this status code to monitor I2C bus event.
*/
#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
/**
* @brief Get Time-out flag from I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @retval 0 I2C Bus time-out is not happened
* @retval 1 I2C Bus time-out is happened
*
* @details When I2C bus occurs time-out event, the time-out flag will be set.
*/
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
/**
* @brief To get wake-up flag from I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @retval 0 Chip is not woken-up from power-down mode
* @retval 1 Chip is woken-up from power-down mode
*
* @details I2C bus occurs wake-up event, wake-up flag will be set.
*/
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
/**
* @brief To clear wake-up flag
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details If wake-up flag is set, use this macro to clear it.
*/
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
/**
* @brief To get SMBus Status
*
* @param[in] i2c Specify I2C port
*
* @return SMBus status
*
* @details To get the Bus Management status of I2C_BUSSTS register
*
*/
#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
/**
* @brief Get SMBus CRC value
*
* @param[in] i2c Specify I2C port
*
* @return Packet error check byte value
*
* @details The CRC check value after a transmission or a reception by count by using CRC8
*
*/
#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
/**
* @brief Set SMBus Bytes number of Transmission or reception
*
* @param[in] i2c Specify I2C port
* @param[in] u32PktSize Transmit / Receive bytes
*
* @return None
*
* @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
*
*/
#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
/**
* @brief Enable SMBus Alert function
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
*
*/
#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
/**
* @brief Disable SMBus Alert pin function
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
*
*/
#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
/**
* @brief Set SMBus SUSCON pin is output mode
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
*
*
*/
#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
/**
* @brief Set SMBus SUSCON pin is input mode
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
*
*
*/
#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
/**
* @brief Set SMBus SUSCON pin output high state
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
*
*/
#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
/**
* @brief Set SMBus SUSCON pin output low state
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
*
*/
#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
/**
* @brief Enable SMBus Acknowledge control by manual
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
*
*/
#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
/**
* @brief Disable SMBus Acknowledge control by manual
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Disable acknowledge response control by user.
*
*/
#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
/**
* @brief Enable SMBus Acknowledge manual interrupt
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
*
*/
#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
/**
* @brief Disable SMBus Acknowledge manual interrupt
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
*
*/
#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
/**
* @brief Enable SMBus PEC clear at REPEAT START
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
*
*/
#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
/**
* @brief Disable SMBus PEC clear at Repeat START
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
*
*/
#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
/**
* @brief Enable RX PDMA function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
/**
* @brief Enable TX PDMA function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
/**
* @brief Disable TX PDMA transfer.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
/**
* @brief Enable PDMA stretch function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
* \hideinitializer
*/
#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
/**
* @brief Disable PDMA stretch function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details I2C will send STOP after PDMA transfers done automatically.
* \hideinitializer
*/
#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
/**
* @brief Reset PDMA function.
* @param[in] i2c The pointer of the specified I2C module.
* @return None.
* @details I2C PDMA engine will be reset after this function is called.
* \hideinitializer
*/
#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
/*---------------------------------------------------------------------------------------------------------*/
/* inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void I2C_STOP(I2C_T *i2c);
/**
* @brief The macro is used to set STOP condition of I2C Bus
*
* @param[in] i2c Specify I2C port
*
* @return None
*
* @details Set the I2C bus STOP condition in I2C_CTL register.
*/
__STATIC_INLINE void I2C_STOP(I2C_T *i2c)
{
(i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
while (i2c->CTL0 & I2C_CTL0_STO_Msk)
{
}
}
void I2C_ClearTimeoutFlag(I2C_T *i2c);
void I2C_Close(I2C_T *i2c);
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
void I2C_DisableInt(I2C_T *i2c);
void I2C_EnableInt(I2C_T *i2c);
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
uint32_t I2C_GetIntFlag(I2C_T *i2c);
uint32_t I2C_GetStatus(I2C_T *i2c);
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
uint8_t I2C_GetData(I2C_T *i2c);
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
void I2C_DisableTimeout(I2C_T *i2c);
void I2C_EnableWakeup(I2C_T *i2c);
void I2C_DisableWakeup(I2C_T *i2c);
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
void I2C_SMBusClose(I2C_T *i2c);
void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group I2C_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __I2C_H__ */

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/**************************************************************************//**
* @file opa.h
* @version V1.00
* @brief M251 series OPA driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __OPA_H__
#define __OPA_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup OPA_Driver OPA Driver
@{
*/
/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants
@{
*/
#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */
#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */
#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */
/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */
/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define OPA functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32RefVol);
/**
* @brief This macro is used to power on the OPA circuit
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will set OPENx (x=0) bit of OPA_CTL register to power on the OPA circuit.
* \hideinitializer
*/
#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
/**
* @brief This macro is used to power down the OPA circuit
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will clear OPENx (x=0) bit of OPA_CTL register to power down the OPA circuit.
* \hideinitializer
*/
#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum))))
/**
* @brief This macro is used to enable the OPA Schmitt trigger buffer
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will set OPDOENx (x=0) bit of OPA_CTL register to enable the OPA Schmitt trigger buffer.
* \hideinitializer
*/
#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum))))
/**
* @brief This macro is used to disable the OPA Schmitt trigger buffer
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will clear OPDOENx (x=0) bit of OPA_CTL register to disable the OPA Schmitt trigger buffer.
* \hideinitializer
*/
#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum))))
/**
* @brief This macro is used to enable OPA Schmitt trigger digital output interrupt
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will set OPDOIENx (x=0) bit of OPA_CTL register to enable the OPA Schmitt trigger digital output interrupt.
* \hideinitializer
*/
#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
/**
* @brief This macro is used to disable OPA Schmitt trigger digital output interrupt
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will clear OPDOIENx (x=0) bit of OPA_CTL register to disable the OPA Schmitt trigger digital output interrupt.
* \hideinitializer
*/
#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum))))
/**
* @brief This macro is used to get OPA digital output state
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return OPA digital output state
* @details This macro will return the OPA digital output value.
* \hideinitializer
*/
#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL)
/**
* @brief This macro is used to get OPA interrupt flag
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @retval 0 OPA interrupt does not occur.
* @retval 1 OPA interrupt occurs.
* @details This macro will return the OPA interrupt flag.
* \hideinitializer
*/
#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL)
/**
* @brief This macro is used to clear OPA interrupt flag
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @return None
* @details This macro will write 1 to OPDOIFx (x=0) bit of OPA_STATUS register to clear interrupt flag.
* \hideinitializer
*/
#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))
/**
* @brief This function is used to configure and start OPA calibration
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0.
* @param[in] u32ClockSel Select OPA calibration clock
* - \ref OPA_CALIBRATION_CLK_1K
* @param[in] u32RefVol Select OPA reference voltage
* - \ref OPA_CALIBRATION_RV_1_2_AVDD
* - \ref OPA_CALIBRATION_RV_H_L_VCM
* @retval 0 PMOS and NMOS calibration successfully.
* @retval -1 only PMOS calibration failed.
* @retval -2 only NMOS calibration failed.
* @retval -3 PMOS and NMOS calibration failed.
*/
__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32RefVol)
{
uint32_t u32CALResult;
int32_t i32Ret = 0L;
(opa)->CALCTL = (((opa)->CALCTL) & ~(0x30ul << (u32OpaNum << 1))) | (((u32ClockSel) << 4) << (u32OpaNum << 1));
(opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum));
(opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum));
while ((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))) {}
u32CALResult = ((opa)->CALST >> ((u32OpaNum) * 4U)) & (OPA_CALST_CALNS0_Msk | OPA_CALST_CALPS0_Msk);
if (u32CALResult == 0ul)
{
i32Ret = 0L;
}
else if (u32CALResult == OPA_CALST_CALNS0_Msk)
{
i32Ret = -2L;
}
else if (u32CALResult == OPA_CALST_CALPS0_Msk)
{
i32Ret = -1L;
}
else if (u32CALResult == (uint32_t)(OPA_CALST_CALNS0_Msk | OPA_CALST_CALPS0_Msk))
{
i32Ret = -3L;
}
else
{
}
return i32Ret;
}
/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group OPA_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __OPA_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file pdma.h
* @version V3.00
* @brief M251 series PDMA driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PDMA_H__
#define __PDMA_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup PDMA_Driver PDMA Driver
@{
*/
/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
@{
*/
#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Operation Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Data Width Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Address Attribute Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Burst Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Table Interrupt Disable Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */
#define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Peripheral Transfer Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_MEM 0UL /*!<DMA Connect to Memory \hideinitializer */
#define PDMA_UART0_TX 4UL /*!<DMA Connect to UART0_TX \hideinitializer */
#define PDMA_UART0_RX 5UL /*!<DMA Connect to UART0_RX \hideinitializer */
#define PDMA_UART1_TX 6UL /*!<DMA Connect to UART1_TX \hideinitializer */
#define PDMA_UART1_RX 7UL /*!<DMA Connect to UART1_RX \hideinitializer */
#define PDMA_UART2_TX 8UL /*!<DMA Connect to UART2_TX \hideinitializer */
#define PDMA_UART2_RX 9UL /*!<DMA Connect to UART2_RX \hideinitializer */
#define PDMA_USCI0_TX 16UL /*!<DMA Connect to USCI0_TX \hideinitializer */
#define PDMA_USCI0_RX 17UL /*!<DMA Connect to USCI0_RX \hideinitializer */
#define PDMA_USCI1_TX 18UL /*!<DMA Connect to USCI1_TX \hideinitializer */
#define PDMA_USCI1_RX 19UL /*!<DMA Connect to USCI1_RX \hideinitializer */
#define PDMA_QSPI0_TX 20UL /*!<DMA Connect to QSPI0_TX \hideinitializer */
#define PDMA_QSPI0_RX 21UL /*!<DMA Connect to QSPI0_RX \hideinitializer */
#define PDMA_SPI0_TX 22UL /*!<DMA Connect to SPI0_TX \hideinitializer */
#define PDMA_SPI0_RX 23UL /*!<DMA Connect to SPI0_RX \hideinitializer */
#define PDMA_PWM0_P1_RX 32UL /*!<DMA Connect to PWM0_P1 \hideinitializer */
#define PDMA_PWM0_P2_RX 33UL /*!<DMA Connect to PWM0_P2 \hideinitializer */
#define PDMA_PWM0_P3_RX 34UL /*!<DMA Connect to PWM0_P3 \hideinitializer */
#define PDMA_PWM1_P1_RX 35UL /*!<DMA Connect to PWM1_P1 \hideinitializer */
#define PDMA_PWM1_P2_RX 36UL /*!<DMA Connect to PWM1_P2 \hideinitializer */
#define PDMA_PWM1_P3_RX 37UL /*!<DMA Connect to PWM1_P3 \hideinitializer */
#define PDMA_I2C0_TX 38UL /*!<DMA Connect to I2C0_TX \hideinitializer */
#define PDMA_I2C0_RX 39UL /*!<DMA Connect to I2C0_RX \hideinitializer */
#define PDMA_I2C1_TX 40UL /*!<DMA Connect to I2C1_TX \hideinitializer */
#define PDMA_I2C1_RX 41UL /*!<DMA Connect to I2C1_RX \hideinitializer */
#define PDMA_TMR0 46UL /*!<DMA Connect to TMR0 \hideinitializer */
#define PDMA_TMR1 47UL /*!<DMA Connect to TMR1 \hideinitializer */
#define PDMA_TMR2 48UL /*!<DMA Connect to TMR2 \hideinitializer */
#define PDMA_TMR3 49UL /*!<DMA Connect to TMR3 \hideinitializer */
#define PDMA_EADC_RX 50UL /*!<DMA Connect to EADC_RX \hideinitializer */
#define PDMA_DAC0_TX 51UL /*!<DMA Connect to DAC0_TX \hideinitializer */
#define PDMA_PSIO_TX 66UL /*!<DMA Connect to PSIO_TX \hideinitializer */
#define PDMA_PSIO_RX 67UL /*!<DMA Connect to PSIO_RX \hideinitializer */
#define PDMA_USCI2_TX 68UL /*!<DMA Connect to USCI2_TX \hideinitializer */
#define PDMA_USCI2_RX 69UL /*!<DMA Connect to USCI2_RX \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */
#define PDMA_INT_TEMPTY 0x00000001UL /*!<Table Empty Interrupt \hideinitializer */
#define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */
/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
@{
*/
/**
* @brief Get PDMA Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details This macro gets the interrupt status.
* \hideinitializer
*/
#define PDMA_GET_INT_STATUS(pdma) ((uint32_t)(pdma->INTSTS))
/**
* @brief Get Transfer Done Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details Get the transfer done Interrupt status.
* \hideinitializer
*/
#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS))
/**
* @brief Clear Transfer Done Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask The channel mask
*
* @return None
*
* @details Clear the transfer done Interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask)))
/**
* @brief Get Target Abort Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details Get the target abort Interrupt status.
* \hideinitializer
*/
#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS))
/**
* @brief Clear Target Abort Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask The channel mask
*
* @return None
*
* @details Clear the target abort Interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask)))
/**
* @brief Get Alignment Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details Get Alignment Interrupt status.
* \hideinitializer
*/
#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN))
/**
* @brief Clear Alignment Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask The channel mask
*
* @return None
*
* @details Clear the Alignment Interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask)))
/**
* @brief Clear Timeout Interrupt Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details Clear the selected channel timeout interrupt status.
* \hideinitializer
*/
#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8))))
/**
* @brief Check Channel Status
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @retval 0 Idle state
* @retval 1 Busy state
*
* @details Check the selected channel is busy or not.
* \hideinitializer
*/
#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0)
/**
* @brief Set Source Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Addr The selected address
*
* @return None
*
* @details This macro set the selected channel source address.
* \hideinitializer
*/
#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr)))
/**
* @brief Set Destination Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Addr The selected address
*
* @return None
*
* @details This macro set the selected channel destination address.
* \hideinitializer
*/
#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr)))
/**
* @brief Set Transfer Count
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32TransCount Transfer Count
*
* @return None
*
* @details This macro set the selected channel transfer count.
* \hideinitializer
*/
#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
/**
* @brief Set Scatter-gather descriptor Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Addr The descriptor address
*
* @return None
*
* @details This macro set the selected channel scatter-gather descriptor address.
* \hideinitializer
*/
#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA)))
/**
* @brief Stop the channel
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details This macro stop the selected channel.
* \hideinitializer
*/
#define PDMA_STOP(pdma, u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch))))
/**
* @brief Pause the channel
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details This macro pause the selected channel.
* \hideinitializer
*/
#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch))))
/*---------------------------------------------------------------------------------------------------------*/
/* Define PDMA functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask);
void PDMA_Close(PDMA_T *pdma);
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask);
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask);
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch);
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount);
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group PDMA_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __PDMA_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/******************************************************************************
* @file pwm.h
* @version V0.10
* @brief M251 series PWM driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup PWM_Driver PWM Driver
@{
*/
/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
@{
*/
#define PWM_CHANNEL_NUM (6UL) /*!< PWM channel number */
#define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask */
#define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask */
#define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask */
#define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask */
#define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask */
#define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask */
/*---------------------------------------------------------------------------------------------------------*/
/* Counter Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_UP_COUNTER (0UL) /*!< Up counter type */
#define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */
#define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
/*---------------------------------------------------------------------------------------------------------*/
/* Aligned Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */
#define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */
/*---------------------------------------------------------------------------------------------------------*/
/* Output Level Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */
#define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */
#define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */
#define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */
/*---------------------------------------------------------------------------------------------------------*/
/* Synchronous Start Function Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_SSCTL_SSRC_PWM0 (0UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
#define PWM_SSCTL_SSRC_PWM1 (1UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
#define PWM_SSCTL_SSRC_BPWM0 (2UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
#define PWM_SSCTL_SSRC_BPWM1 (3UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
/*---------------------------------------------------------------------------------------------------------*/
/* Trigger Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger EADC while counter of even channel matches zero point */
#define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger EADC while counter of even channel matches period point */
#define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger EADC while counter of even channel matches zero or period point */
#define PWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< PWM trigger EADC while counter of even channel matches up count to comparator point */
#define PWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< PWM trigger EADC while counter of even channel matches down count to comparator point */
#define PWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< PWM trigger EADC while counter of odd channel matches up count to comparator point */
#define PWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< PWM trigger EADC while counter of odd channel matches down count to comparator point */
/*---------------------------------------------------------------------------------------------------------*/
/* Fail brake Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
#define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
#define PWM_FB_EDGE_BKP0 (PWM_BRKCTL_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
#define PWM_FB_EDGE_BKP1 (PWM_BRKCTL_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
#define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
#define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
#define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
#define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
#define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
#define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
#define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
#define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
#define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
#define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
#define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
#define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
/*---------------------------------------------------------------------------------------------------------*/
/* Capture Control Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */
#define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */
#define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */
#define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */
#define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */
/*---------------------------------------------------------------------------------------------------------*/
/* Duty Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */
#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */
/*---------------------------------------------------------------------------------------------------------*/
/* Load Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode */
#define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode */
/*---------------------------------------------------------------------------------------------------------*/
/* Noise Filter Clock Divide Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 */
#define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 */
#define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 */
#define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 */
#define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 */
#define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 */
#define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 */
#define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 */
/*---------------------------------------------------------------------------------------------------------*/
/* Clock Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK */
#define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow */
#define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow */
#define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow */
#define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow */
/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
@{
*/
/**
* @brief This macro enable complementary mode
* @param[in] pwm The pointer of the specified PWM module
* @return None
* @details This macro is used to enable complementary mode of PWM module.
* \hideinitializer
*/
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODE0_Msk | PWM_CTL1_OUTMODE2_Msk | PWM_CTL1_OUTMODE4_Msk)
/**
* @brief This macro disable complementary mode, and enable independent mode.
* @param[in] pwm The pointer of the specified PWM module
* @return None
* @details This macro is used to disable complementary mode of PWM module.
* \hideinitializer
*/
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODE0_Msk & ~PWM_CTL1_OUTMODE2_Msk & ~PWM_CTL1_OUTMODE4_Msk)
/**
* @brief Enable timer synchronous start counting function of specified channel(s)
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
* - \ref PWM_SSCTL_SSRC_PWM0
* - \ref PWM_SSCTL_SSRC_PWM1
* - \ref PWM_SSCTL_SSRC_BPWM0
* - \ref PWM_SSCTL_SSRC_BPWM1
* @return None
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
* @note Every two channels share the same setting.
* \hideinitializer
*/
#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask, u32SyncSrc) \
do{ \
uint32_t i;\
(pwm)->SSCTL = ((pwm)->SSCTL & ~PWM_SSCTL_SSRC_Msk) | (u32SyncSrc) ; \
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) \
(pwm)->SSCTL |= (1UL << ((i >> 1UL) << 1UL)); \
} \
}while(0)
/**
* @brief Disable timer synchronous start counting function of specified channel(s)
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
* @note Every two channels share the same setting.
* \hideinitializer
*/
#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
do{ \
uint32_t i;\
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) \
(pwm)->SSCTL &= ~(1UL << ((i >> 1UL) << 1UL)); \
} \
}while(0)
/**
* @brief This macro enable PWM counter synchronous start counting function.
* @param[in] pwm The pointer of the specified PWM module
* @return None
* @details This macro is used to make selected PWM0 and PWM1 channel(s) start counting at the same time.
* To configure synchronous start counting channel(s) by PWM_ENABLE_TIMER_SYNC() and PWM_DISABLE_TIMER_SYNC().
* \hideinitializer
*/
#define PWM_TRIGGER_SYNC_START(pwm) ((pwm)->SSTRG = PWM_SSTRG_CNTSEN_Msk)
/**
* @brief This macro enable output inverter of specified channel(s)
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* @details This macro is used to enable output inverter of specified channel(s).
* \hideinitializer
*/
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
/**
* @brief This macro get captured rising data
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @return None
* @details This macro is used to get captured rising data of specified channel.
* \hideinitializer
*/
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) ((pwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
/**
* @brief This macro get captured falling data
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @return None
* @details This macro is used to get captured falling data of specified channel.
* \hideinitializer
*/
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) ((pwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
/**
* @brief This macro mask output logic to high or low
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32LevelMask Output logic to high or low
* @return None
* @details This macro is used to mask output logic to high or low of specified channel(s).
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
* \hideinitializer
*/
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
do{ \
(pwm)->MSKEN = (u32ChannelMask); \
(pwm)->MSK = (u32LevelMask); \
}while(0)
/**
* @brief This macro set the prescaler of the selected channel
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
* @return None
* @details This macro is used to set the prescaler of specified channel.
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
* channel 1 will also be affected. The clock of PWM counter is divided by (u32Prescaler + 1).
* \hideinitializer
*/
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) ((pwm)->CLKPSC[(u32ChannelNum) >> 1UL] = (u32Prescaler))
/**
* @brief This macro get the prescaler of the selected channel
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
* @details This macro is used to get the prescaler of specified channel.
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
* The clock of PWM counter is divided by (u32Prescaler + 1).
* \hideinitializer
*/
#define PWM_GET_PRESCALER(pwm, u32ChannelNum) ((pwm)->CLKPSC[(u32ChannelNum) >> 1UL])
/**
* @brief This macro set the comparator of the selected channel
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set the comparator of specified channel.
* @note This new setting will take effect on next PWM period.
* \hideinitializer
*/
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
/**
* @brief This macro get the comparator of the selected channel
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
* @details This macro is used to get the comparator of specified channel.
* \hideinitializer
*/
#define PWM_GET_CMR(pwm, u32ChannelNum) ((pwm)->CMPDAT[(u32ChannelNum)])
/**
* @brief This macro set the period of the selected channel
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0, 2, 4. Every two channels share the same setting.
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
* @return None
* @details This macro is used to set the period of specified channel.
* @note This new setting will take effect on next PWM period.
* @note PWM counter will stop if period length set to 0.
* \hideinitializer
*/
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(((u32ChannelNum) >> 1UL) << 1UL)] = (u32CNR))
/**
* @brief This macro get the period of the selected channel
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @return Return the period of specified channel. Valid values are between 0~0xFFFF
* @details This macro is used to get the period of specified channel.
* \hideinitializer
*/
#define PWM_GET_CNR(pwm, u32ChannelNum) ((pwm)->PERIOD[(((u32ChannelNum) >> 1UL) << 1UL)])
/**
* @brief This macro set the PWM aligned type
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Every two channels share the same setting.
* @param[in] u32AlignedType PWM aligned type, valid values are:
* - \ref PWM_UP_COUNTER
* - \ref PWM_DOWN_COUNTER
* - \ref PWM_UP_DOWN_COUNTER
* @return None
* @details This macro is used to set the PWM aligned type of specified channel(s).
* \hideinitializer
*/
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
do{ \
uint32_t i; \
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) \
(pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << ((i >> 1UL) << 2UL))) | ((u32AlignedType) << ((i >> 1UL) << 2UL))); \
} \
}while(0)
/**
* @brief Clear counter of specified channel(s)
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Every two channels share the same setting.
* @return None
* @details This macro is used to clear counter of specified channel(s).
* \hideinitializer
*/
#define PWM_CLR_COUNTER(pwm, u32ChannelMask) \
do{ \
uint32_t i; \
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) \
((pwm)->CNTCLR |= (1UL << ((i >> 1UL) << 1UL))); \
} \
}while(0)
/**
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @param[in] u32ZeroLevel output level at zero point, valid values are:
* - \ref PWM_OUTPUT_NOTHING
* - \ref PWM_OUTPUT_LOW
* - \ref PWM_OUTPUT_HIGH
* - \ref PWM_OUTPUT_TOGGLE
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
* - \ref PWM_OUTPUT_NOTHING
* - \ref PWM_OUTPUT_LOW
* - \ref PWM_OUTPUT_HIGH
* - \ref PWM_OUTPUT_TOGGLE
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
* - \ref PWM_OUTPUT_NOTHING
* - \ref PWM_OUTPUT_LOW
* - \ref PWM_OUTPUT_HIGH
* - \ref PWM_OUTPUT_TOGGLE
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
* - \ref PWM_OUTPUT_NOTHING
* - \ref PWM_OUTPUT_LOW
* - \ref PWM_OUTPUT_HIGH
* - \ref PWM_OUTPUT_TOGGLE
* @return None
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
* \hideinitializer
*/
#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
do{ \
uint32_t i; \
for(i = 0UL; i < 6UL; i++) { \
if((u32ChannelMask) & (1UL << i)) { \
(pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (i << 1UL))) | ((u32ZeroLevel) << (i << 1UL))); \
(pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))); \
(pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (i << 1UL))) | ((u32CmpUpLevel) << (i << 1UL))); \
(pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))); \
} \
} \
}while(0)
/**
* @brief Trigger brake event from specified channel(s) by using sw trigger
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
* @param[in] u32BrakeType Type of brake trigger. It supports PWM_FB_EDGE and PWM_FB_LEVEL.
* - \ref PWM_FB_EDGE
* - \ref PWM_FB_LEVEL
* @return None
* @details This macro is used to trigger brake event from specified channel(s) by using sw trigger.
* \hideinitializer
*/
#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
/**
* @brief Set Dead zone clock source
* @param[in] pwm The pointer of the specified PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
* @return None
* @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
* @note The write-protection function should be disabled before using this function.
* \hideinitializer
*/
#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
(((pwm)->DTCTL[(u32ChannelNum) >> 1UL]) = ((pwm)->DTCTL[(u32ChannelNum) >> 1UL] & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
/*---------------------------------------------------------------------------------------------------------*/
/* Define PWM functions prototype */
/*---------------------------------------------------------------------------------------------------------*/
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group PWM_Driver */
/*@}*/ /* end of group Standard_Driver*/
#ifdef __cplusplus
}
#endif
#endif /* __PWM_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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@@ -0,0 +1,389 @@
/**************************************************************************//**
* @file qspi.h
* @version V0.10
* @brief M251 series QSPI driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __QSPI_H__
#define __QSPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup QSPI_Driver QSPI Driver
@{
*/
/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants
@{
*/
#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
#define QSPI_MASTER (0x0UL) /*!< Set as master \hideinitializer */
#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low \hideinitializer */
/* QSPI Interrupt Mask */
#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask \hideinitializer */
#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask \hideinitializer */
#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask \hideinitializer */
#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask \hideinitializer */
#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask \hideinitializer */
#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask \hideinitializer */
#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask \hideinitializer */
#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask \hideinitializer */
#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask \hideinitializer */
#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask \hideinitializer */
/* QSPI Status Mask */
#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask \hideinitializer */
#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask \hideinitializer */
#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask \hideinitializer */
#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask \hideinitializer */
#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask \hideinitializer */
#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask \hideinitializer */
#define QSPI_QSPIEN_STS_MASK (0x40UL) /*!< QSPIEN status mask \hideinitializer */
#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask \hideinitializer */
/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */
/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
@{
*/
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag.
* \hideinitializer
*/
#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk)
/**
* @brief Trigger RX PDMA function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk)
/**
* @brief Trigger TX PDMA function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable TX PDMA transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] qspi The pointer of the specified QSPI module.
* @return The count of available data in RX FIFO.
* @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO.
* \hideinitializer
*/
#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos)
/**
* @brief Get the RX FIFO empty flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 RX FIFO is not empty.
* @retval 1 RX FIFO is empty.
* @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag.
* \hideinitializer
*/
#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos)
/**
* @brief Get the TX FIFO empty flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 TX FIFO is not empty.
* @retval 1 TX FIFO is empty.
* @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag.
* \hideinitializer
*/
#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos)
/**
* @brief Get the TX FIFO full flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 TX FIFO is not full.
* @retval 1 TX FIFO is full.
* @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag.
* \hideinitializer
*/
#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos)
/**
* @brief Get the datum read from RX register.
* @param[in] qspi The pointer of the specified QSPI module.
* @return Data in RX register.
* @details Read QSPI_RX register to get the received datum.
* \hideinitializer
*/
#define QSPI_READ_RX(qspi) ((qspi)->RX)
/**
* @brief Write datum to TX register.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32TxData The datum which user attempt to transfer through QSPI bus.
* @return None.
* @details Write u32TxData to QSPI_TX register.
* \hideinitializer
*/
#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData))
/**
* @brief Set QSPIx_SS pin to high state.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Disable automatic slave selection function and set QSPIx_SS pin to high state.
* \hideinitializer
*/
#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))
/**
* @brief Set QSPIx_SS pin to low state.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Disable automatic slave selection function and set QSPIx_SS pin to low state.
* \hideinitializer
*/
#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk)
/**
* @brief Enable Byte Reorder function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]).
* \hideinitializer
*/
#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk)
/**
* @brief Disable Byte Reorder function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function.
* \hideinitializer
*/
#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk)
/**
* @brief Set the length of suspend interval.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
* @return None.
* @details Set the length of suspend interval according to u32SuspCycle.
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle).
* \hideinitializer
*/
#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos))
/**
* @brief Set the QSPI transfer sequence with LSB first.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first.
* \hideinitializer
*/
#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk)
/**
* @brief Set the QSPI transfer sequence with MSB first.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first.
* \hideinitializer
*/
#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk)
/**
* @brief Set the data width of a QSPI transaction.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Width The bit width of one transaction.
* @return None.
* @details The data width can be 8 ~ 32 bits.
* \hideinitializer
*/
#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos))
/**
* @brief Get the QSPI busy state.
* @param[in] qspi The pointer of the specified QSPI module.
* @retval 0 QSPI controller is not busy.
* @retval 1 QSPI controller is busy.
* @details This macro will return the busy state of QSPI controller.
* \hideinitializer
*/
#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos )
/**
* @brief Enable QSPI controller.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller.
* \hideinitializer
*/
#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk)
/**
* @brief Disable QSPI controller.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller.
* \hideinitializer
*/
#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk)
/**
* @brief Disable 2-bit Transfer mode.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode.
*/
#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk )
/**
* @brief Enable 2-bit Transfer mode.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode.
*/
#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk )
/**
* @brief Disable Slave 3-wire mode.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode.
*/
#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk )
/**
* @brief Enable Slave 3-wire mode.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None.
* @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode.
*/
#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk )
/**
* @brief Disable QSPI Dual IO function.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
/**
* @brief Enable Dual IO function and set QSPI Dual IO direction to input.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk )
/**
* @brief Enable Dual IO function and set QSPI Dual IO direction to output.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk )
/**
* @brief Disable QSPI Dual IO function.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
/**
* @brief Set QSPI Quad IO direction to input.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk )
/**
* @brief Set QSPI Quad IO direction to output.
* @param[in] qspi is the base address of QSPI module.
* @return none
* \hideinitializer
*/
#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk )
/* Function prototype declaration */
uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void QSPI_Close(QSPI_T *qspi);
void QSPI_ClearRxFIFO(QSPI_T *qspi);
void QSPI_ClearTxFIFO(QSPI_T *qspi);
void QSPI_DisableAutoSS(QSPI_T *qspi);
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
uint32_t QSPI_GetBusClock(QSPI_T *qspi);
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group QSPI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __QSPI_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file rtc.h
* @version V1.00
* @brief M251 series RTC driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __RTC_H__
#define __RTC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Initial Keyword Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Frequency Compensation Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_INTEGER_32752 (0x0ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32752HZ \hideinitializer */
#define RTC_INTEGER_32753 (0x1ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32753HZ \hideinitializer */
#define RTC_INTEGER_32754 (0x2ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32754HZ \hideinitializer */
#define RTC_INTEGER_32755 (0x3ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32755HZ \hideinitializer */
#define RTC_INTEGER_32756 (0x4ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32756HZ \hideinitializer */
#define RTC_INTEGER_32757 (0x5ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32757HZ \hideinitializer */
#define RTC_INTEGER_32758 (0x6ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32758HZ \hideinitializer */
#define RTC_INTEGER_32759 (0x7ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32759HZ \hideinitializer */
#define RTC_INTEGER_32760 (0x8ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32760HZ \hideinitializer */
#define RTC_INTEGER_32761 (0x9ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32761HZ \hideinitializer */
#define RTC_INTEGER_32762 (0xaul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32762HZ \hideinitializer */
#define RTC_INTEGER_32763 (0xbul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32763HZ \hideinitializer */
#define RTC_INTEGER_32764 (0xcul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32764HZ \hideinitializer */
#define RTC_INTEGER_32765 (0xdul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32765HZ \hideinitializer */
#define RTC_INTEGER_32766 (0xeul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32766HZ \hideinitializer */
#define RTC_INTEGER_32767 (0xful << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32767HZ \hideinitializer */
#define RTC_INTEGER_32768 (0x10ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32768HZ \hideinitializer */
#define RTC_INTEGER_32769 (0x11ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32769HZ \hideinitializer */
#define RTC_INTEGER_32770 (0x12ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32770HZ \hideinitializer */
#define RTC_INTEGER_32771 (0x13ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32771HZ \hideinitializer */
#define RTC_INTEGER_32772 (0x14ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32772HZ \hideinitializer */
#define RTC_INTEGER_32773 (0x15ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32773HZ \hideinitializer */
#define RTC_INTEGER_32774 (0x16ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32774HZ \hideinitializer */
#define RTC_INTEGER_32775 (0x17ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32775HZ \hideinitializer */
#define RTC_INTEGER_32776 (0x18ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32776HZ \hideinitializer */
#define RTC_INTEGER_32777 (0x19ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32777HZ \hideinitializer */
#define RTC_INTEGER_32778 (0x1aul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32778HZ \hideinitializer */
#define RTC_INTEGER_32779 (0x1bul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32779HZ \hideinitializer */
#define RTC_INTEGER_32780 (0x1cul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32780HZ \hideinitializer */
#define RTC_INTEGER_32781 (0x1dul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32781HZ \hideinitializer */
#define RTC_INTEGER_32782 (0x1eul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32782HZ \hideinitializer */
#define RTC_INTEGER_32783 (0x1ful << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32783HZ \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Time Attribute Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */
#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */
#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Tick Period Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */
#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */
#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */
#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */
#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */
#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */
#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */
#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Day of Week Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */
#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */
#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */
#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */
#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */
#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */
#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* RTC Miscellaneous Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */
#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */
#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */
#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */
#define MAX_TAMPER_PIN_NUM 1ul /*!< Tamper Pin number \hideinitializer */
#define RTC_TAMPER_HIGH_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is High \hideinitializer */
#define RTC_TAMPER_LOW_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is low \hideinitializer */
#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */
#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */
/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
@{
*/
/**
* @details RTC define Time Data Struct
*/
typedef struct
{
uint32_t u32Year; /*!< Year value */
uint32_t u32Month; /*!< Month value */
uint32_t u32Day; /*!< Day value */
uint32_t u32DayOfWeek; /*!< Day of week value */
uint32_t u32Hour; /*!< Hour value */
uint32_t u32Minute; /*!< Minute value */
uint32_t u32Second; /*!< Second value */
uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
} S_RTC_TIME_DATA_T;
/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
@{
*/
/**
* @brief Indicate is Leap Year or not
*
* @param None
*
* @retval 0 This year is not a leap year
* @retval 1 This year is a leap year
*
* @details According to current date, return this year is leap year or not.
* \hideinitializer
*/
#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
/**
* @brief Clear RTC Alarm Interrupt Flag
*
* @param None
*
* @return None
*
* @details This macro is used to clear RTC alarm interrupt flag.
* \hideinitializer
*/
#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
/**
* @brief Clear RTC Tick Interrupt Flag
*
* @param None
*
* @return None
*
* @details This macro is used to clear RTC tick interrupt flag.
* \hideinitializer
*/
#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
/**
* @brief Clear RTC Tamper Interrupt Flag
*
* @param u32TamperFlag Tamper interrupt flag. It consists of: \n
* - \ref RTC_INTSTS_TAMP0IF_Msk
*
* @return None
*
* @details This macro is used to clear RTC snooper pin interrupt flag.
* \hideinitializer
*/
#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag))
/**
* @brief Get RTC Alarm Interrupt Flag
*
* @param None
*
* @retval 0 RTC alarm interrupt did not occur
* @retval 1 RTC alarm interrupt occurred
*
* @details This macro indicates RTC alarm interrupt occurred or not.
* \hideinitializer
*/
#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
/**
* @brief Get RTC Time Tick Interrupt Flag
*
* @param None
*
* @retval 0 RTC time tick interrupt did not occur
* @retval 1 RTC time tick interrupt occurred
*
* @details This macro indicates RTC time tick interrupt occurred or not.
* \hideinitializer
*/
#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
/**
* @brief Get RTC Tamper Interrupt Flag
*
* @param None
*
* @retval 0 RTC snooper pin interrupt did not occur
* @retval 1 RTC snooper pin interrupt occurred
*
* @details This macro indicates RTC snooper pin interrupt occurred or not.
* \hideinitializer
*/
#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x0100))? 1:0)
/**
* @brief Get RTC TAMPER Interrupt Status
*
* @param None
*
* @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated
*
* @details This macro indicates RTC snooper pin interrupt occurred or not.
* \hideinitializer
*/
#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x0100)))
/**
* @brief Enable RTC Tick Wake-up Function
*
* @param None
*
* @return None
*
* @details This macro is used to enable RTC tick interrupt wake-up function.
* \hideinitializer
*/
#define RTC_ENABLE_TICK_WAKEUP() ((RTC->INTEN |= RTC_INTEN_TICKIEN_Msk))
/**
* @brief Disable RTC Tick Wake-up Function
*
* @param None
*
* @return None
*
* @details This macro is used to disable RTC tick interrupt wake-up function.
* \hideinitializer
*/
#define RTC_DISABLE_TICK_WAKEUP() ((RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk));
/**
* @brief Enable RTC Alarm Wake-up Function
*
* @param None
*
* @return None
*
* @details This macro is used to enable RTC Alarm interrupt wake-up function.
* \hideinitializer
*/
#define RTC_ENABLE_ALARM_WAKEUP() ((RTC->INTEN |= RTC_INTEN_ALMIEN_Msk))
/**
* @brief Disable RTC Alarm Wake-up Function
*
* @param None
*
* @return None
*
* @details This macro is used to disable RTC Alarm interrupt wake-up function.
* \hideinitializer
*/
#define RTC_DISABLE_ALARM_WAKEUP() ((RTC->INTEN &= ~RTC_INTEN_ALMIEN_Msk));
/**
* @brief Read Spare Register
*
* @param[in] u32RegNum The spare register number, 0~4.
*
* @return Spare register content
*
* @details Read the specify spare register content.
* @note The returned value is valid only when SPRRWEN(SPRCTL[2] RTC Spare Function control register) bit is set. \n
* And its controlled by RTC Spare Function control register(RTC_SPRCTL).
* \hideinitializer
*/
#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
/**
* @brief Write Spare Register
*
* @param[in] u32RegNum The spare register number, 0~4.
* @param[in] u32RegValue The spare register value.
*
* @return None
*
* @details Write specify data to spare register.
* @note This macro is effect only when SPRRWEN(SPRCTL[2] RTC Spare Function control register) bit is set. \n
* And its controlled by RTC Spare Function control register(RTC_SPRCTL).
* \hideinitializer
*/
#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
void RTC_Open(S_RTC_TIME_DATA_T *psPt);
void RTC_Close(void);
void RTC_32KCalibration(int32_t i32FrequencyX10000);
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *psPt);
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt);
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *psPt);
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt);
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
uint32_t RTC_GetDayOfWeek(void);
void RTC_SetTickPeriod(uint32_t u32TickSelection);
void RTC_EnableInt(uint32_t u32IntFlagMask);
void RTC_DisableInt(uint32_t u32IntFlagMask);
void RTC_EnableSpareAccess(void);
void RTC_DisableSpareRegister(void);
void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
void RTC_StaticTamperDisable(uint32_t u32TamperSelect);
/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group RTC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __RTC_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/sc.h Normal file
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/**************************************************************************//**
* @file sc.h
* @version V3.00
* @brief Smart Card(SC) driver header file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SC_H__
#define __SC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SC_Driver SC Driver
@{
*/
/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
@{
*/
#define SC_INTERFACE_NUM (1ul) /*!< Smartcard interface numbers \hideinitializer */
#define SC_PIN_STATE_HIGH (1ul) /*!< Smartcard pin status high \hideinitializer */
#define SC_PIN_STATE_LOW (0ul) /*!< Smartcard pin status low \hideinitializer */
#define SC_PIN_STATE_IGNORE (0xFFFFFFFFul) /*!< Ignore pin status \hideinitializer */
#define SC_CLK_ON (1ul) /*!< Smartcard clock on \hideinitializer */
#define SC_CLK_OFF (0ul) /*!< Smartcard clock off \hideinitializer */
#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 0, down count \hideinitializer */
#define SC_TMR_MODE_1 (1ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit \hideinitializer */
#define SC_TMR_MODE_2 (2ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit \hideinitializer */
#define SC_TMR_MODE_3 (3ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode \hideinitializer */
#define SC_TMR_MODE_4 (4ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout \hideinitializer */
#define SC_TMR_MODE_5 (5ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout \hideinitializer */
#define SC_TMR_MODE_6 (6ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout \hideinitializer */
#define SC_TMR_MODE_7 (7ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit \hideinitializer */
#define SC_TMR_MODE_8 (8ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 8, up count \hideinitializer */
#define SC_TMR_MODE_F (0xF << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit \hideinitializer */
/*@}*/ /* end of group SC_EXPORTED_CONSTANTS */
/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
@{
*/
/**
* @brief Enable Smartcard Interrupt
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Mask Interrupt mask to be enabled. A combination of
* - \ref SC_INTEN_ACERRIEN_Msk
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_INITIEN_Msk
* - \ref SC_INTEN_CDIEN_Msk
* - \ref SC_INTEN_BGTIEN_Msk
* - \ref SC_INTEN_TMR2IEN_Msk
* - \ref SC_INTEN_TMR1IEN_Msk
* - \ref SC_INTEN_TMR0IEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
*
* @return None
*
* @details The macro is used to enable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
* Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
* Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
* \hideinitializer
*/
#define SC_ENABLE_INT(psSC, u32Mask) ((psSC)->INTEN |= (u32Mask))
/**
* @brief Disable Smartcard Interrupt
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
* - \ref SC_INTEN_ACERRIEN_Msk
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_INITIEN_Msk
* - \ref SC_INTEN_CDIEN_Msk
* - \ref SC_INTEN_BGTIEN_Msk
* - \ref SC_INTEN_TMR2IEN_Msk
* - \ref SC_INTEN_TMR1IEN_Msk
* - \ref SC_INTEN_TMR0IEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
*
* @return None
*
* @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
* Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
* Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
* \hideinitializer
*/
#define SC_DISABLE_INT(psSC, u32Mask) ((psSC)->INTEN &= ~(u32Mask))
/**
* @brief Check Smartcard Interrupt Status Flag
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
* - \ref SC_INTSTS_ACERRIF_Msk
* - \ref SC_INTSTS_RXTOIF_Msk
* - \ref SC_INTSTS_INITIF_Msk
* - \ref SC_INTSTS_CDIF_Msk
* - \ref SC_INTSTS_BGTIF_Msk
* - \ref SC_INTSTS_TMR2IF_Msk
* - \ref SC_INTSTS_TMR1IF_Msk
* - \ref SC_INTSTS_TMR0IF_Msk
* - \ref SC_INTSTS_TERRIF_Msk
* - \ref SC_INTSTS_TBEIF_Msk
* - \ref SC_INTSTS_RDAIF_Msk
*
* @return None
*
* @details The macro is used to check Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
* Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
* Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
* \hideinitializer
*/
#define SC_CHECK_INTSTS(psSC, u32Mask) ((psSC)->INTSTS &= u32Mask)
/**
* @brief Clear Smartcard Interrupt Status Flag
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
* - \ref SC_INTSTS_ACERRIF_Msk
* - \ref SC_INTSTS_RXTOIF_Msk
* - \ref SC_INTSTS_INITIF_Msk
* - \ref SC_INTSTS_CDIF_Msk
* - \ref SC_INTSTS_BGTIF_Msk
* - \ref SC_INTSTS_TMR2IF_Msk
* - \ref SC_INTSTS_TMR1IF_Msk
* - \ref SC_INTSTS_TMR0IF_Msk
* - \ref SC_INTSTS_TERRIF_Msk
* - \ref SC_INTSTS_TBEIF_Msk
* - \ref SC_INTSTS_RDAIF_Msk
*
* @return None
*
* @details The macro is used to check Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
* Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
* Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
* \hideinitializer
*/
#define SC_CLEAR_INTSTS(psSC, u32Mask) ((psSC)->INTSTS = u32Mask)
/**
* @brief Set ETU Divider
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Mask ETU divider value
*
* @return None
*
* @details The macro is used to give ETU divider. Its value must be given more than 4.
* \hideinitializer
*/
#define SC_SET_ETUDIV(psSC, u32Mask) ((psSC)->ETUCTL = (((psSC)->ETUCTL&(~SC_ETUCTL_ETURDIV_Msk)) | (u32Mask <<SC_ETUCTL_ETURDIV_Pos)))
/**
* @brief Set Smartcard Power Pin State
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32State Set pin state of power pin, valid parameters are:
* - \ref SC_PIN_STATE_HIGH
* - \ref SC_PIN_STATE_LOW
*
* @return None
*
* @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level.
* \hideinitializer
*/
#define SC_SET_VCC_PIN(psSC, u32State) \
do {\
while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32State)\
(psSC)->PINCTL |= SC_PINCTL_PWREN_Msk;\
else\
(psSC)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
}while(0)
/**
* @brief Set Smartcard Clock Status
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32OnOff Set clock on or off for selected smartcard module, valid values are:
* - \ref SC_CLK_ON
* - \ref SC_CLK_OFF
*
* @return None
*
* @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.
* \hideinitializer
*/
#define SC_SET_CLK_PIN(psSC, u32OnOff)\
do {\
while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32OnOff)\
(psSC)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
else\
(psSC)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
}while(0)
/**
* @brief Set Smartcard I/O Pin State
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32State Set pin state of I/O pin, valid parameters are:
* - \ref SC_PIN_STATE_HIGH
* - \ref SC_PIN_STATE_LOW
*
* @return None
*
* @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low.
* \hideinitializer
*/
#define SC_SET_IO_PIN(psSC, u32State)\
do {\
while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32State)\
(psSC)->PINCTL |= SC_PINCTL_SCDATA_Msk;\
else\
(psSC)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\
}while(0)
/**
* @brief Set Smartcard Reset Pin State
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32State Set pin state of reset pin, valid parameters are:
* - \ref SC_PIN_STATE_HIGH
* - \ref SC_PIN_STATE_LOW
*
* @return None
*
* @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low.
* \hideinitializer
*/
#define SC_SET_RST_PIN(psSC, u32State)\
do {\
while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\
if(u32State)\
(psSC)->PINCTL |= SC_PINCTL_RSTEN_Msk;\
else\
(psSC)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\
}while(0)
/**
* @brief Read One Byte Data
*
* @param[in] psSC The pointer of smartcard module.
*
* @return One byte read from receive FIFO
*
* @details By reading DAT register, the SC will return an 8-bit received data.
* \hideinitializer
*/
#define SC_READ(psSC) ((char)((psSC)->DAT))
/**
* @brief Write One Byte Data
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u8Data Data to write to transmit FIFO.
*
* @return None
*
* @details By writing data to DAT register, the SC will send out an 8-bit data.
* \hideinitializer
*/
#define SC_WRITE(psSC, u8Data) ((psSC)->DAT = (u8Data))
/**
* @brief Set Smartcard Stop Bit Length
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Len Stop bit length, ether 1 or 2.
*
* @return None
*
* @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
* \hideinitializer
*/
#define SC_SET_STOP_BIT_LEN(psSC, u32Len) ((psSC)->CTL = ((psSC)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0))
/*---------------------------------------------------------------------------------------------------------*/
/* static inline functions */
/*---------------------------------------------------------------------------------------------------------*/
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void SC_SetTxRetry(SC_T *psSC, uint32_t u32Count);
__STATIC_INLINE void SC_SetRxRetry(SC_T *psSC, uint32_t u32Count);
/**
* @brief Set Tx Error Retry Count
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Count The number of Tx error retry count, between 0~8 and 0 means disable Tx error retry function.
*
* @return None
*
* @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count.
* @note Set error retry count to 0 will disable Tx error retry function.
*/
__STATIC_INLINE void SC_SetTxRetry(SC_T *psSC, uint32_t u32Count)
{
while ((psSC)->CTL & SC_CTL_SYNC_Msk) {}
/* Retry count must set while enable bit disabled, so disable it first */
(psSC)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
if ((u32Count) != 0UL)
{
while ((psSC)->CTL & SC_CTL_SYNC_Msk) {}
(psSC)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
}
}
/**
* @brief Set Rx Error Retry Count
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32Count The number of Rx error retry count, between 0~8 and 0 means disable Rx error retry function.
*
* @return None
*
* @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count.
* @note Set error retry count to 0 will disable Rx error retry function.
*/
__STATIC_INLINE void SC_SetRxRetry(SC_T *psSC, uint32_t u32Count)
{
while ((psSC)->CTL & SC_CTL_SYNC_Msk) {}
/* Retry count must set while enable bit disabled, so disable it first */
(psSC)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
if ((u32Count) != 0UL)
{
while ((psSC)->CTL & SC_CTL_SYNC_Msk) {}
(psSC)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
}
}
uint32_t SC_IsCardInserted(SC_T *psSC);
void SC_ClearFIFO(SC_T *psSC);
void SC_Close(SC_T *psSC);
void SC_Open(SC_T *psSC, uint32_t u32CardDet, uint32_t u32PWR);
void SC_ResetReader(SC_T *psSC);
void SC_SetBlockGuardTime(SC_T *psSC, uint32_t u32BGT);
void SC_SetCharGuardTime(SC_T *psSC, uint32_t u32CGT);
void SC_StopAllTimer(SC_T *psSC);
void SC_StartTimer(SC_T *psSC, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
void SC_StopTimer(SC_T *psSC, uint32_t u32TimerNum);
uint32_t SC_GetInterfaceClock(SC_T *psSC);
/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SC_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __SC_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file scuart.h
* @version V1.00
* @brief M251 Smartcard UART mode (SCUART) driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SCUART_H__
#define __SCUART_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SCUART_Driver SCUART Driver
@{
*/
/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
@{
*/
#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */
#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */
#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */
/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
@{
*/
/* TX Macros */
/**
* @brief Write Data to Tx data register
* @param[in] psSC The base address of smartcard module.
* @param[in] u8Data Data byte to transmit
* @return None
* \hideinitializer
*/
#define SCUART_WRITE(psSC, u8Data) ((psSC)->DAT = (u8Data))
/**
* @brief Get TX FIFO empty flag status from register
* @param[in] psSC The base address of smartcard module
* @return Transmit FIFO empty status
* @retval 0 Transmit FIFO is not empty
* @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
* \hideinitializer
*/
#define SCUART_GET_TX_EMPTY(psSC) ((psSC)->STATUS & SC_STATUS_TXEMPTY_Msk)
/**
* @brief Get TX FIFO full flag status from register
* @param[in] psSC The base address of smartcard module
* @return Transmit FIFO full status
* @retval 0 Transmit FIFO is not full
* @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
* \hideinitializer
*/
#define SCUART_GET_TX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_TXFULL_Msk)
/**
* @brief Wait specified smartcard port transmission complete
* @param[in] psSC The base address of smartcard module
* @return None
* @note This Macro blocks until transmit complete.
* \hideinitializer
*/
#define SCUART_WAIT_TX_EMPTY(psSC) while((psSC)->STATUS & SC_STATUS_TXACT_Msk)
/**
* @brief Check specified smartcard port transmit FIFO is full or not
* @param[in] psSC The base address of smartcard module
* @return Transmit FIFO full status
* @retval 0 Transmit FIFO is not full
* @retval 1 Transmit FIFO is full
* \hideinitializer
*/
#define SCUART_IS_TX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
/**
* @brief Check specified smartcard port transmission is over
* @param[in] psSC The base address of smartcard module
* @return Transmit complete status
* @retval 0 Transmit is not complete
* @retval 1 Transmit complete
* \hideinitializer
*/
#define SCUART_IS_TX_EMPTY(psSC) ((psSC)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
/**
* @brief Check specified Smartcard port Transmission Status
* @param[in] psSC The pointer of smartcard module.
* @retval 0 Transmit is completed
* @retval 1 Transmit is active
* @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.
* \hideinitializer
*/
#define SCUART_IS_TX_ACTIVE(psSC) (((psSC)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)
/* RX Macros */
/**
* @brief Read Rx data register
* @param[in] psSC The base address of smartcard module
* @return The oldest data byte in RX FIFO
* \hideinitializer
*/
#define SCUART_READ(psSC) ((psSC)->DAT)
/**
* @brief Get RX FIFO empty flag status from register
* @param[in] psSC The base address of smartcard module
* @return Receive FIFO empty status
* @retval 0 Receive FIFO is not empty
* @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
* \hideinitializer
*/
#define SCUART_GET_RX_EMPTY(psSC) ((psSC)->STATUS & SC_STATUS_RXEMPTY_Msk)
/**
* @brief Get RX FIFO full flag status from register
* @param[in] psSC The base address of smartcard module
* @return Receive FIFO full status
* @retval 0 Receive FIFO is not full
* @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
* \hideinitializer
*/
#define SCUART_GET_RX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_RXFULL_Msk)
/**
* @brief Check if receive data number in FIFO reach FIFO trigger level or not
* @param[in] psSC The base address of smartcard module
* @return Receive FIFO data status
* @retval 0 The number of bytes in receive FIFO is less than trigger level
* @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
* @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
* \hideinitializer
*/
#define SCUART_IS_RX_READY(psSC) ((psSC)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
/**
* @brief Check specified smartcard port receive FIFO is full or not
* @param[in] psSC The base address of smartcard module
* @return Receive FIFO full status
* @retval 0 Receive FIFO is not full
* @retval 1 Receive FIFO is full
* \hideinitializer
*/
#define SCUART_IS_RX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
/* Interrupt Macros */
/**
* @brief Enable specified interrupts
* @param[in] psSC The base address of smartcard module
* @param[in] u32Mask Interrupt masks to enable, a combination of following bits
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
* @return None
* \hideinitializer
*/
#define SCUART_ENABLE_INT(psSC, u32Mask) ((psSC)->INTEN |= (u32Mask))
/**
* @brief Disable specified interrupts
* @param[in] psSC The base address of smartcard module
* @param[in] u32Mask Interrupt masks to disable, a combination of following bits
* - \ref SC_INTEN_RXTOIEN_Msk
* - \ref SC_INTEN_TERRIEN_Msk
* - \ref SC_INTEN_TBEIEN_Msk
* - \ref SC_INTEN_RDAIEN_Msk
* @return None
* \hideinitializer
*/
#define SCUART_DISABLE_INT(psSC, u32Mask) ((psSC)->INTEN &= ~(u32Mask))
/**
* @brief Get specified interrupt flag/status
* @param[in] psSC The base address of smartcard module
* @param[in] u32Type Interrupt flag/status to check, could be one of following value
* - \ref SC_INTSTS_RXTOIF_Msk
* - \ref SC_INTSTS_TERRIF_Msk
* - \ref SC_INTSTS_TBEIF_Msk
* - \ref SC_INTSTS_RDAIF_Msk
* @return The status of specified interrupt
* @retval 0 Specified interrupt does not happened
* @retval 1 Specified interrupt happened
* \hideinitializer
*/
#define SCUART_GET_INT_FLAG(psSC, u32Type) ((psSC)->INTSTS & (u32Type) ? 1 : 0)
/**
* @brief Clear specified interrupt flag/status
* @param[in] psSC The base address of smartcard module
* @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
* - \ref SC_INTSTS_RXTOIF_Msk
* - \ref SC_INTSTS_TERRIF_Msk
* - \ref SC_INTSTS_TBEIF_Msk
* @return None
* \hideinitializer
*/
#define SCUART_CLR_INT_FLAG(psSC, u32Type) ((psSC)->INTSTS = (u32Type))
/**
* @brief Get receive error flag/status
* @param[in] psSC The base address of smartcard module
* @return Current receive error status, could one of following errors:
* @retval SC_STATUS_PEF_Msk Parity error
* @retval SC_STATUS_FEF_Msk Frame error
* @retval SC_STATUS_BEF_Msk Break error
* \hideinitializer
*/
#define SCUART_GET_ERR_FLAG(psSC) ((psSC)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
/**
* @brief Clear specified receive error flag/status
* @param[in] psSC The base address of smartcard module
* @param[in] u32Mask Receive error flag/status to clear, combination following values
* - \ref SC_STATUS_PEF_Msk
* - \ref SC_STATUS_FEF_Msk
* - \ref SC_STATUS_BEF_Msk
* @return None
* \hideinitializer
*/
#define SCUART_CLR_ERR_FLAG(psSC, u32Mask) ((psSC)->STATUS = (u32Mask))
void SCUART_Close(SC_T *psSC);
uint32_t SCUART_Open(SC_T *psSC, uint32_t u32baudrate);
uint32_t SCUART_Read(SC_T *psSC, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
uint32_t SCUART_SetLineConfig(SC_T *psSC, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
void SCUART_SetTimeoutCnt(SC_T *psSC, uint32_t u32TOC);
void SCUART_Write(SC_T *psSC, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SCUART_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __SCUART_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file spi.h
* @version V0.10
* @brief M251 series SPI driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_H__
#define __SPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SPI_Driver SPI Driver
@{
*/
/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
@{
*/
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
#define SPI_MASTER (0x0UL) /*!< Set as master \hideinitializer */
#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */
#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
#define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low \hideinitializer */
/* SPI Interrupt Mask */
#define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask \hideinitializer */
#define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask \hideinitializer */
#define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask \hideinitializer */
#define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask \hideinitializer */
#define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask \hideinitializer */
#define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask \hideinitializer */
#define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask \hideinitializer */
#define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask \hideinitializer */
#define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask \hideinitializer */
#define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask \hideinitializer */
/* SPI Status Mask */
#define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask \hideinitializer */
#define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask \hideinitializer */
#define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask \hideinitializer */
#define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask \hideinitializer */
#define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask \hideinitializer */
#define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask \hideinitializer */
#define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask \hideinitializer */
#define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask \hideinitializer */
/* I2S Data Width */
#define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
#define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
#define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
#define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
/* I2S Audio Format */
#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */
#define SPII2S_STEREO (0UL) /*!< Stereo channel \hideinitializer */
/* I2S Data Format */
#define SPII2S_FORMAT_I2S (0UL<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format \hideinitializer */
#define SPII2S_FORMAT_MSB (1UL<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format \hideinitializer */
#define SPII2S_FORMAT_PCMA (2UL<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format \hideinitializer */
#define SPII2S_FORMAT_PCMB (3UL<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format \hideinitializer */
/* I2S Operation mode */
#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
#define SPII2S_MODE_MASTER (0UL) /*!< As master mode \hideinitializer */
/* I2S TX FIFO Threshold */
#define SPII2S_FIFO_TX_LEVEL_WORD_0 (0UL) /*!< TX threshold is 0 word \hideinitializer */
#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
/* I2S RX FIFO Threshold */
#define SPII2S_FIFO_RX_LEVEL_WORD_1 (0UL) /*!< RX threshold is 1 word \hideinitializer */
#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
/* I2S Record Channel */
#define SPII2S_MONO_RIGHT (0UL) /*!< Record mono right channel \hideinitializer */
#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
/* I2S Channel */
#define SPII2S_RIGHT (0UL) /*!< Select right channel \hideinitializer */
#define SPII2S_LEFT (1UL) /*!< Select left channel \hideinitializer */
/* I2S Interrupt Mask */
#define SPII2S_FIFO_TXTH_INT_MASK (0x01UL) /*!< TX FIFO threshold interrupt mask \hideinitializer */
#define SPII2S_FIFO_RXTH_INT_MASK (0x02UL) /*!< RX FIFO threshold interrupt mask \hideinitializer */
#define SPII2S_FIFO_RXOV_INT_MASK (0x04UL) /*!< RX FIFO overrun interrupt mask \hideinitializer */
#define SPII2S_FIFO_RXTO_INT_MASK (0x08UL) /*!< RX FIFO time-out interrupt mask \hideinitializer */
#define SPII2S_TXUF_INT_MASK (0x10UL) /*!< TX FIFO underflow interrupt mask \hideinitializer */
#define SPII2S_RIGHT_ZC_INT_MASK (0x20UL) /*!< Right channel zero cross interrupt mask \hideinitializer */
#define SPII2S_LEFT_ZC_INT_MASK (0x40UL) /*!< Left channel zero cross interrupt mask \hideinitializer */
#define SPII2S_SLV_CLKERR_INT_MASK (0x80UL) /*!< Slave mode bit clock loss interrupt mask \hideinitializer */
/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
@{
*/
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
* \hideinitializer
*/
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
/**
* @brief Trigger RX PDMA function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
/**
* @brief Trigger TX PDMA function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable TX PDMA transfer.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] spi The pointer of the specified SPI module.
* @return The count of available data in RX FIFO.
* @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
* \hideinitializer
*/
#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
/**
* @brief Get the RX FIFO empty flag.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 RX FIFO is not empty.
* @retval 1 RX FIFO is empty.
* @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
* \hideinitializer
*/
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
/**
* @brief Get the TX FIFO empty flag.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 TX FIFO is not empty.
* @retval 1 TX FIFO is empty.
* @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
* \hideinitializer
*/
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
/**
* @brief Get the TX FIFO full flag.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 TX FIFO is not full.
* @retval 1 TX FIFO is full.
* @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
* \hideinitializer
*/
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
/**
* @brief Get the datum read from RX register.
* @param[in] spi The pointer of the specified SPI module.
* @return Data in RX register.
* @details Read SPI_RX register to get the received datum.
* \hideinitializer
*/
#define SPI_READ_RX(spi) ((spi)->RX)
/**
* @brief Write datum to TX register.
* @param[in] spi The pointer of the specified SPI module.
* @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
* @return None.
* @details Write u32TxData to SPI_TX register.
* \hideinitializer
*/
#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
/**
* @brief Set SPIx_SS pin to high state.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Disable automatic slave selection function and set SPIx_SS pin to high state.
* \hideinitializer
*/
#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
/**
* @brief Set SPIx_SS pin to low state.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Disable automatic slave selection function and set SPIx_SS pin to low state.
* \hideinitializer
*/
#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
/**
* @brief Enable Byte Reorder function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
* \hideinitializer
*/
#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
/**
* @brief Disable Byte Reorder function.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
* \hideinitializer
*/
#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
/**
* @brief Set the length of suspend interval.
* @param[in] spi The pointer of the specified SPI module.
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
* @return None.
* @details Set the length of suspend interval according to u32SuspCycle.
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
* \hideinitializer
*/
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
/**
* @brief Set the SPI transfer sequence with LSB first.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
* \hideinitializer
*/
#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
/**
* @brief Set the SPI transfer sequence with MSB first.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
* \hideinitializer
*/
#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
/**
* @brief Set the data width of a SPI transaction.
* @param[in] spi The pointer of the specified SPI module.
* @param[in] u32Width The bit width of one transaction.
* @return None.
* @details The data width can be 8 ~ 32 bits.
* \hideinitializer
*/
#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
/**
* @brief Get the SPI busy state.
* @param[in] spi The pointer of the specified SPI module.
* @retval 0 SPI controller is not busy.
* @retval 1 SPI controller is busy.
* @details This macro will return the busy state of SPI controller.
* \hideinitializer
*/
#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
/**
* @brief Enable SPI controller.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
* \hideinitializer
*/
#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
/**
* @brief Disable SPI controller.
* @param[in] spi The pointer of the specified SPI module.
* @return None.
* @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
* \hideinitializer
*/
#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
/**
* @brief Enable zero cross detection function.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
* - \ref SPII2S_RIGHT
* - \ref SPII2S_LEFT
* @return None
* @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
*/
__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
{
if (u32ChMask == SPII2S_RIGHT)
{
i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
}
else
{
i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
}
}
/**
* @brief Disable zero cross detection function.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
* - \ref SPII2S_RIGHT
* - \ref SPII2S_LEFT
* @return None
* @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
*/
__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
{
if (u32ChMask == SPII2S_RIGHT)
{
i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
}
else
{
i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
}
}
/**
* @brief Enable I2S TX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
* \hideinitializer
*/
#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Disable I2S TX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
* \hideinitializer
*/
#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Enable I2S RX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
* \hideinitializer
*/
#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable I2S RX DMA function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
* \hideinitializer
*/
#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Enable I2S TX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
* \hideinitializer
*/
#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
/**
* @brief Disable I2S TX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
* \hideinitializer
*/
#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
/**
* @brief Enable I2S RX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
* \hideinitializer
*/
#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
/**
* @brief Disable I2S RX function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
* \hideinitializer
*/
#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
/**
* @brief Enable TX Mute function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
* \hideinitializer
*/
#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
/**
* @brief Disable TX Mute function.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
* \hideinitializer
*/
#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
/**
* @brief Clear TX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
* \hideinitializer
*/
#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
/**
* @brief Clear RX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @return None
* @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
* \hideinitializer
*/
#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
/**
* @brief This function sets the recording source channel when mono mode is used.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Ch left or right channel. Valid values are:
* - \ref SPII2S_MONO_LEFT
* - \ref SPII2S_MONO_RIGHT
* @return None
* @details This function selects the recording source channel of monaural mode.
* \hideinitializer
*/
__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
{
u32Ch == SPII2S_MONO_LEFT ?
(i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
(i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
}
/**
* @brief Write data to I2S TX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Data The value written to TX FIFO.
* @return None
* @details This macro will write a value to TX FIFO.
* \hideinitializer
*/
#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
/**
* @brief Read RX FIFO.
* @param[in] i2s The pointer of the specified I2S module.
* @return The value read from RX FIFO.
* @details This function will return a value read from RX FIFO.
* \hideinitializer
*/
#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
/**
* @brief Get the interrupt flag.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Mask The mask value for all interrupt flags.
* @return The interrupt flags specified by the u32mask parameter.
* @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
* \hideinitializer
*/
#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
/**
* @brief Clear the interrupt flag.
* @param[in] i2s The pointer of the specified I2S module.
* @param[in] u32Mask The mask value for all interrupt flags.
* @return None
* @details This macro will clear the interrupt flags specified by the u32mask parameter.
* @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
* \hideinitializer
*/
#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
/**
* @brief Get transmit FIFO level
* @param[in] i2s The pointer of the specified I2S module.
* @return TX FIFO level
* @details This macro will return the number of available words in TX FIFO.
* \hideinitializer
*/
#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
/**
* @brief Get receive FIFO level
* @param[in] i2s The pointer of the specified I2S module.
* @return RX FIFO level
* @details This macro will return the number of available words in RX FIFO.
* \hideinitializer
*/
#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
/* Function prototype declaration */
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI_Close(SPI_T *spi);
void SPI_ClearRxFIFO(SPI_T *spi);
void SPI_ClearTxFIFO(SPI_T *spi);
void SPI_DisableAutoSS(SPI_T *spi);
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
uint32_t SPI_GetBusClock(SPI_T *spi);
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
void SPII2S_Close(SPI_T *i2s);
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
void SPII2S_DisableMCLK(SPI_T *i2s);
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SPI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file timer.h
* @version V0.10
* @brief M251 series Timer driver header file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup TIMER_Driver TIMER Driver
@{
*/
/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode */
#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */
#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode */
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode */
#define TIMER_TOUT_PIN_FROM_TX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx pin */
#define TIMER_TOUT_PIN_FROM_TX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx_EXT pin */
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value */
#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter */
#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection */
#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection */
#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event */
#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event */
#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge */
#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge */
#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge */
#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge */
/* For new Trigger Source Selection */
#define TIMER_TRGSEL_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos)
#define TIMER_TRGSEL_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos)
#define TIMER_TRG_TO_PWM (TIMER_TRGCTL_TRGPWM_Msk)
#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk)
#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk)
#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk)
/* Capture Sourdce Selection */
#define TIMER_CAPTURE_FROM_EXTERNAL (0UL << TIMER_CTL_CAPSRC_Pos)
#define TIMER_CAPTURE_FROM_INTERNAL (1UL << TIMER_CTL_CAPSRC_Pos)
/* Capture Sourdce Divider */
#define TIMER_CAPTURE_SRCDIV_1 (0UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_2 (1UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_4 (2UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_8 (3UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_16 (4UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_32 (5UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_64 (6UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_128 (7UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
#define TIMER_CAPTURE_SRCDIV_256 (8UL << TIMER_EXTCTL_CAPDIVSCL_Pos)
/* Internal Capture Sourdce Selection */
#define TIMER_INTER_CAPTURE_FROM_ACMP0 (0UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
#define TIMER_INTER_CAPTURE_FROM_ACMP1 (1UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
#define TIMER_INTER_CAPTURE_FROM_HXT (2UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
#define TIMER_INTER_CAPTURE_FROM_LXT (3UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
#define TIMER_INTER_CAPTURE_FROM_HIRC (4UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
#define TIMER_INTER_CAPTURE_FROM_LIRC (5UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
#define TIMER_INTER_CAPTURE_FROM_MIRC (6UL << TIMER_EXTCTL_INTERCAPSEL_Pos)
/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
@{
*/
/**
* @brief Set Timer Compared Value
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
*
* @return None
*
* @details This macro is used to set timer compared value to adjust timer time-out interval.
* @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
* 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
* But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
*/
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
/**
* @brief Set Timer Prescale Value
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
*
* @return None
*
* @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
* before it is fed into timer.
*/
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
/**
* @brief Check specify Timer Status
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Timer 24-bit up counter is inactive
* @retval 1 Timer 24-bit up counter is active
*
* @details This macro is used to check if specify Timer counter is inactive or active.
*/
#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
/**
* @brief Select Toggle-output Pin
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32ToutSel Toggle-output pin selection, valid values are:
* - \ref TIMER_TOUT_PIN_FROM_TX
* - \ref TIMER_TOUT_PIN_FROM_TX_EXT
*
* @return None
*
* @details This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin.
*/
#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void TIMER_Start(TIMER_T *timer);
__STATIC_INLINE void TIMER_Stop(TIMER_T *timer);
__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer);
__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer);
__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer);
__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer);
__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer);
__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer);
__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer);
__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer);
__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer);
__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer);
__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer);
__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer);
__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer);
__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer);
__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer);
__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer);
__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer);
__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer);
__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer);
__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer);
__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer);
/**
* @brief Start Timer Counting
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to start Timer counting.
*/
__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
{
timer->CTL |= TIMER_CTL_CNTEN_Msk;
}
/**
* @brief Stop Timer Counting
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to stop/suspend Timer counting.
*/
__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
}
/**
* @brief Enable Timer Interrupt Wake-up Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
* counter event interrupt or capture trigger interrupt.
* @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
*/
__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
{
timer->CTL |= TIMER_CTL_WKEN_Msk;
}
/**
* @brief Disable Timer Wake-up Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable the timer interrupt wake-up function.
*/
__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_WKEN_Msk;
}
/**
* @brief Start Timer Capture Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to start Timer capture function.
*/
__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk;
}
/**
* @brief Stop Timer Capture Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to stop Timer capture function.
*/
__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
}
/**
* @brief Enable Capture Pin De-bounce
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to enable the detect de-bounce function of capture pin.
*/
__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
}
/**
* @brief Disable Capture Pin De-bounce
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable the detect de-bounce function of capture pin.
*/
__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
}
/**
* @brief Enable Counter Pin De-bounce
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to enable the detect de-bounce function of counter pin.
*/
__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
}
/**
* @brief Disable Counter Pin De-bounce
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable the detect de-bounce function of counter pin.
*/
__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
}
/**
* @brief Enable Timer Time-out Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to enable the timer time-out interrupt function.
*/
__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
{
timer->CTL |= TIMER_CTL_INTEN_Msk;
}
/**
* @brief Disable Timer Time-out Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable the timer time-out interrupt function.
*/
__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_INTEN_Msk;
}
/**
* @brief Enable Capture Trigger Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to enable the timer capture trigger interrupt function.
*/
__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
}
/**
* @brief Disable Capture Trigger Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable the timer capture trigger interrupt function.
*/
__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
}
/**
* @brief Get Timer Time-out Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Timer time-out interrupt did not occur
* @retval 1 Timer time-out interrupt occurred
*
* @details This function indicates timer time-out interrupt occurred or not.
*/
__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
{
return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0);
}
/**
* @brief Clear Timer Time-out Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function clears timer time-out interrupt flag to 0.
*/
__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
{
timer->INTSTS = TIMER_INTSTS_TIF_Msk;
}
/**
* @brief Get Timer Capture Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Timer capture interrupt did not occur
* @retval 1 Timer capture interrupt occurred
*
* @details This function indicates timer capture trigger interrupt occurred or not.
*/
__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
{
return timer->EINTSTS;
}
/**
* @brief Clear Timer Capture Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function clears timer capture trigger interrupt flag to 0.
*/
__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
{
timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
}
/**
* @brief Get Timer Wake-up Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Timer does not cause CPU wake-up
* @retval 1 Timer interrupt event cause CPU wake-up
*
* @details This function indicates timer interrupt event has waked up system or not.
*/
__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
{
return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
}
/**
* @brief Clear Timer Wake-up Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function clears the timer wake-up system flag to 0.
*/
__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
{
timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
}
/**
* @brief Get Capture value
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return 24-bit Capture Value
*
* @details This function reports the current 24-bit timer capture value.
*/
__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
{
return timer->CAP;
}
/**
* @brief Get Counter value
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return 24-bit Counter Value
*
* @details This function reports the current 24-bit timer counter value.
*/
__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
{
return timer->CNT;
}
/**
* @brief Reset Counter
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to reset current counter value and internal prescale counter value.
*/
__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer)
{
timer->CNT = 0UL;
while ((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk)
{
;
}
}
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
void TIMER_Close(TIMER_T *timer);
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
void TIMER_CaptureSelect(TIMER_T *timer, uint32_t u32Src);
void TIMER_DisableCapture(TIMER_T *timer);
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
void TIMER_DisableEventCounter(TIMER_T *timer);
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt);
void TIMER_DisableFreqCounter(TIMER_T *timer);
/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group TIMER_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/timer_pwm.h Normal file
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/**************************************************************************//**
* @file timer_pwm.h
* @version V1.00
* @brief M251 series Timer PWM Controller(Timer PWM) driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TIMER_PWM_H__
#define __TIMER_PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
@{
*/
/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* TPWM Output Channel Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* TPWM Output Channel Selection Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TPWM_TOUT_PIN_FROM_TX (BIT0) /*!< Indicate PWMx output to Tx pins \hideinitializer */
#define TPWM_TOUT_PIN_FROM_TX_EXT (BIT8) /*!< Indicate PWMx output to Tx_ext pins \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* TPWM Counter Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */
#define TPWM_ONE_SHOT_MODE (1UL) /*!< One-shot mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* TPWM Output Level Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */
#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */
#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */
#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* TPWM Trigger ADC/DAC/PDMA Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TPWM_TRIGGER_AT_PERIOD_POINT (0UL) /*!< Timer PWM trigger EADC while counter period point event occurred \hideinitializer */
#define TPWM_TRIGGER_AT_COMPARE_POINT (1UL) /*!< Timer PWM trigger EADC while counter compare point event occurred \hideinitializer */
#define TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT (2UL) /*!< Timer PWM trigger EADC while counter period or compare point event occurred \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* TPWM Counter Clock Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define TPWM_CLKSRC_HXT (0UL) /*!< Timer PWM Clock source selects to HXT \hideinitializer \hideinitializer */
#define TPWM_CLKSRC_LXT (1UL) /*!< Timer PWM Clock source selects to LXT \hideinitializer \hideinitializer */
#define TPWM_CLKSRC_PCLK (2UL) /*!< Timer PWM Clock source selects to PCLK \hideinitializer \hideinitializer */
#define TPWM_CLKSRC_TX (3UL) /*!< Timer PWM Clock source selects to TX \hideinitializer \hideinitializer */
#define TPWM_CLKSRC_LIRC (5UL) /*!< Timer PWM Clock source selects to LIRC \hideinitializer \hideinitializer */
#define TPWM_CLKSRC_HIRC (7UL) /*!< Timer PWM Clock source selects to HIRC \hideinitializer \hideinitializer */
/*@}*/ /* end of group TIMER_PWM_EXPORTED_CONSTANTS */
/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
@{
*/
/**
* @brief Enable PWM Counter Mode
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to enable specified Timer channel as PWM counter mode, then timer counter mode is invalid.
* @note All registers about time counter function will be cleared to 0 and timer clock source will be changed to PCLKx automatically after executing this macro.
* \hideinitializer
*/
#define TPWM_ENABLE_PWM_MODE(timer) ((timer)->CTL |= TIMER_CTL_FUNCSEL_Msk)
/**
* @brief Disable PWM Counter Mode
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available.
* @note All registers about PWM counter function will be cleared to 0 after executing this macro.
* \hideinitializer
*/
#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->CTL &= ~TIMER_CTL_FUNCSEL_Msk)
/**
* @brief Start PWM Counter
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to enable PWM generator and start counter counting.
* \hideinitializer
*/
#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk)
/**
* @brief Stop PWM Counter
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to stop PWM counter after current period is completed.
* \hideinitializer
*/
#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0UL)
/**
* @brief Set Counter Clock Prescaler
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF.
*
* @return None
*
* @details This macro is used to set the prescaler of specified TIMER PWM.
* @note If prescaler is 0, then there is no scaling in counter clock source.
* \hideinitializer
*/
#define TPWM_SET_PRESCALER(timer, u32Prescaler) ((timer)->PWMCLKPSC = (u32Prescaler))
/**
* @brief Get Counter Clock Prescaler
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0])
*
* @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1).
* \hideinitializer
*/
#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC)
/**
* @brief Set Counter Period
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @param[in] u32Period Period of specified channel. Valid values are between 0x0~0xFFFF.
*
* @return None
*
* @details This macro is used to set the period of specified TIMER PWM.
* \hideinitializer
*/
#define TPWM_SET_PERIOD(timer, u32Period) ((timer)->PWMPERIOD = (u32Period))
/**
* @brief Get Counter Period
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0])
*
* @details This macro is used to get the period of specified TIMER PWM.
* \hideinitializer
*/
#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD)
/**
* @brief Set Comparator Value
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @param[in] u32Cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF.
*
* @return None
*
* @details This macro is used to set the comparator value of specified TIMER PWM.
* \hideinitializer
*/
#define TPWM_SET_CMPDAT(timer, u32Cmp) ((timer)->PWMCMPDAT = (u32Cmp))
/**
* @brief Get Comparator Value
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0])
*
* @details This macro is used to get the comparator value of specified TIMER PWM.
* \hideinitializer
*/
#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT)
/**
* @brief Clear Counter
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to clear counter of specified TIMER PWM.
* \hideinitializer
*/
#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk)
/**
* @brief Enable Output Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @param[in] u32Channel Enable specified channel output function. Valid values are:
* - \ref TPWM_CH0
*
* @return None
*
* @details This macro is used to enable output function of specified output pins.
* @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel.
* \hideinitializer
*/
#define TPWM_ENABLE_OUTPUT(timer, u32Channel) ((timer)->PWMPOCTL = (u32Channel))
/**
* @brief Select Toggle-output Pin
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32ToutSel Toggle-output pin selection, valid values are:
* - \ref TPWM_TOUT_PIN_FROM_TX
* - \ref TPWM_TOUT_PIN_FROM_TX_EXT
*
* @return None
*
* @details This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin.
*/
#define TPWM_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->PWMPOCTL = ((timer)->PWMPOCTL & ~TIMER_PWMPOCTL_POSEL_Msk) | (u32ToutSel))
/**
* @brief Set Output Inverse
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @param[in] u32Channel Set specified channel output is inversed or not. Valid values are:
* - \ref TPWM_CH0
*
* @return None
*
* @details This macro is used to enable output inverse of specified output pins.
* @note If u32ChMask parameter is 0, then output inverse function will be disabled.
* \hideinitializer
*/
#define TPWM_SET_OUTPUT_INVERSE(timer, u32Channel) ((timer)->PWMPOLCTL = (u32Channel))
/**
* @brief Enable Period Event Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to enable the period event interrupt function.
* \hideinitializer
*/
#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk)
/**
* @brief Disable Period Event Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to disable the period event interrupt function.
* \hideinitializer
*/
#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk)
/**
* @brief Get Period Event Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Period event interrupt did not occur
* @retval 1 Period event interrupt occurred
*
* @details This macro indicates period event occurred or not.
* \hideinitializer
*/
#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0)
/**
* @brief Clear Period Event Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro clears period event interrupt flag.
* \hideinitializer
*/
#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk)
/**
* @brief Enable Compare Up Event Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to enable the compare up event interrupt function.
* \hideinitializer
*/
#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk)
/**
* @brief Disable Compare Up Event Interrupt
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to disable the compare up event interrupt function.
* \hideinitializer
*/
#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk)
/**
* @brief Get Compare Up Event Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Compare up event interrupt did not occur
* @retval 1 Compare up event interrupt occurred
*
* @details This macro indicates compare up event occurred or not.
* \hideinitializer
*/
#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0)
/**
* @brief Clear Compare Up Event Interrupt Flag
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro clears compare up event interrupt flag.
* \hideinitializer
*/
#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk)
/**
* @brief Get Counter Reach Maximum Count Status
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Timer PWM counter never counts to maximum value
* @retval 1 Timer PWM counter counts to maximum value, 0xFFFF
*
* @details This macro indicates Timer PWM counter has count to 0xFFFF or not.
* \hideinitializer
*/
#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0)
/**
* @brief Clear Counter Reach Maximum Count Status
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro clears reach maximum count status.
* \hideinitializer
*/
#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk)
/**
* @brief Get Trigger ADC Status
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @retval 0 Trigger ADC start conversion is not occur
* @retval 1 Specified counter compare event has trigger ADC start conversion
*
* @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion.
* \hideinitializer
*/
#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0)
/**
* @brief Clear Trigger ADC Status
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This macro is used to clear PWM counter compare event trigger ADC status.
* \hideinitializer
*/
#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk)
uint32_t TPWM_GetModuleClock(TIMER_T *timer);
uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle);
void TPWM_EnableCounter(TIMER_T *timer);
void TPWM_DisableCounter(TIMER_T *timer);
void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition);
void TPWM_DisableTriggerADC(TIMER_T *timer);
void TPWM_EnableTriggerDAC(TIMER_T *timer, uint32_t u32Condition);
void TPWM_DisableTriggerDAC(TIMER_T *timer);
void TPWM_EnableTriggerPDMA(TIMER_T *timer, uint32_t u32Condition);
void TPWM_DisableTriggerPDMA(TIMER_T *timer);
void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode);
/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group TIMER_PWM_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_PWM_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/uart.h Normal file
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/****************************************************************************
* @file uart.h
* @version V1.00
* @brief M251 series UART driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup UART_Driver UART Driver
@{
*/
/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* UART FIFO size constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART0_FIFO_SIZE 16ul /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
#define UART1_FIFO_SIZE 16ul /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
#define UART2_FIFO_SIZE 16ul /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_FIFO constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FIFO_RFITL_1BYTE (0x0ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte \hideinitializer */
#define UART_FIFO_RFITL_4BYTES (0x1ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes \hideinitializer */
#define UART_FIFO_RFITL_8BYTES (0x2ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes \hideinitializer */
#define UART_FIFO_RFITL_14BYTES (0x3ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes \hideinitializer */
#define UART_FIFO_RTSTRGLV_1BYTE (0x0ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte \hideinitializer */
#define UART_FIFO_RTSTRGLV_4BYTES (0x1ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes \hideinitializer */
#define UART_FIFO_RTSTRGLV_8BYTES (0x2ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes \hideinitializer */
#define UART_FIFO_RTSTRGLV_14BYTES (0x3ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_LINE constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_WORD_LEN_5 (0ul) /*!< UART_LINE setting to set UART word length to 5 bits \hideinitializer */
#define UART_WORD_LEN_6 (1ul) /*!< UART_LINE setting to set UART word length to 6 bits \hideinitializer */
#define UART_WORD_LEN_7 (2ul) /*!< UART_LINE setting to set UART word length to 7 bits \hideinitializer */
#define UART_WORD_LEN_8 (3ul) /*!< UART_LINE setting to set UART word length to 8 bits \hideinitializer */
#define UART_PARITY_NONE (0x0ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity \hideinitializer */
#define UART_PARITY_ODD (0x1ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity \hideinitializer */
#define UART_PARITY_EVEN (0x3ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity \hideinitializer */
#define UART_PARITY_MARK (0x5ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' \hideinitializer */
#define UART_PARITY_SPACE (0x7ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' \hideinitializer */
#define UART_STOP_BIT_1 (0x0ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit \hideinitializer */
#define UART_STOP_BIT_1_5 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length \hideinitializer */
#define UART_STOP_BIT_2 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART RTS ACTIVE LEVEL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active \hideinitializer */
#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_IRDA constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_IRDA_TXEN (0x1ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode \hideinitializer */
#define UART_IRDA_RXEN (0x0ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_FUNCSEL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FUNCSEL_UART (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) \hideinitializer */
#define UART_FUNCSEL_LIN (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function \hideinitializer */
#define UART_FUNCSEL_IrDA (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function \hideinitializer */
#define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function \hideinitializer */
#define UART_FUNCSEL_SINGLE_WIRE (0x4ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set Single Wire Function \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_LINCTL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 \hideinitializer */
#define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 \hideinitializer */
#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field \hideinitializer */
#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field \hideinitializer */
#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field \hideinitializer */
#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UART BAUDRATE MODE constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_BAUD_MODE0 (0ul) /*!< Set UART Baudrate Mode is Mode0 \hideinitializer */
#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 \hideinitializer */
/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
@{
*/
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param[in] u32SrcFreq UART clock frequency
* @param[in] u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode0 divider
*
* @details This macro calculate UART baudrate mode0 divider.
* \hideinitializer
*/
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul)
/**
* @brief Calculate UART baudrate mode2 divider
*
* @param[in] u32SrcFreq UART clock frequency
* @param[in] u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode2 divider
*
* @details This macro calculate UART baudrate mode2 divider.
* \hideinitializer
*/
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
/**
* @brief Write UART data
*
* @param[in] uart The pointer of the specified UART module
* @param[in] u8Data Data byte to transmit.
*
* @return None
*
* @details This macro write Data to Tx data register.
* \hideinitializer
*/
#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
/**
* @brief Read UART data
*
* @param[in] uart The pointer of the specified UART module
*
* @return The oldest data byte in RX FIFO.
*
* @details This macro read Rx data register.
* \hideinitializer
*/
#define UART_READ(uart) ((uart)->DAT)
/**
* @brief Get Tx empty
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Tx FIFO is not empty
* @retval >=1 Tx FIFO is empty
*
* @details This macro get Transmitter FIFO empty register value.
* \hideinitializer
*/
#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
/**
* @brief Get Rx empty
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Rx FIFO is not empty
* @retval >=1 Rx FIFO is empty
*
* @details This macro get Receiver FIFO empty register value.
* \hideinitializer
*/
#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
/**
* @brief Check specified UART port transmission is over.
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Tx transmission is not over
* @retval 1 Tx transmission is over
*
* @details This macro return Transmitter Empty Flag register bit value.
* It indicates if specified UART port transmission is over nor not.
* \hideinitializer
*/
#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
/**
* @brief Wait specified UART port transmission is over
*
* @param[in] uart The pointer of the specified UART module
*
* @return None
*
* @details This macro wait specified UART port transmission is over.
* \hideinitializer
*/
#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
/**
* @brief Check RX is ready or not
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 The number of bytes in the RX FIFO is less than the RFITL
* @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
*
* @details This macro check receive data available interrupt flag is set or not.
* \hideinitializer
*/
#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
/**
* @brief Check TX FIFO is full or not
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 1 TX FIFO is full
* @retval 0 TX FIFO is not full
*
* @details This macro check TX FIFO is full or not.
* \hideinitializer
*/
#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
/**
* @brief Check RX FIFO is full or not
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 1 RX FIFO is full
* @retval 0 RX FIFO is not full
*
* @details This macro check RX FIFO is full or not.
* \hideinitializer
*/
#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
/**
* @brief Get Tx full register value
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Tx FIFO is not full.
* @retval >=1 Tx FIFO is full.
*
* @details This macro get Tx full register value.
* \hideinitializer
*/
#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
/**
* @brief Get Rx full register value
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Rx FIFO is not full.
* @retval >=1 Rx FIFO is full.
*
* @details This macro get Rx full register value.
* \hideinitializer
*/
#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
/**
* @brief Rx Idel Status register value
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Rx is busy.
* @retval 1 Rx is Idel(Default)
*
* @details This macro get Rx Idel Status register value.
* \hideinitializer
*/
#define UART_RX_IDEL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos)
/**
* @brief Enable specified UART interrupt
*
* @param[in] uart The pointer of the specified UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty interrupt
* - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
* - \ref UART_INTEN_SWBEIEN_Msk : Single-wire bit error detection interrupt
* - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
* - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
*
* @return None
*
* @details This macro enable specified UART interrupt.
* \hideinitializer
*/
#define UART_ENABLE_INT(uart, u32IntSel) ((uart)->INTEN |= (u32IntSel))
/**
* @brief Disable specified UART interrupt
*
* @param[in] uart The pointer of the specified UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty interrupt
* - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
* - \ref UART_INTEN_SWBEIEN_Msk : Single-wire bit error detection interrupt
* - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
* - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
*
* @return None
*
* @details This macro enable specified UART interrupt.
* \hideinitializer
*/
#define UART_DISABLE_INT(uart, u32IntSel) ((uart)->INTEN &= ~ (u32IntSel))
/**
* @brief Get specified interrupt flag/status
*
* @param[in] uart The pointer of the specified UART module
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator
* - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator
* - \ref UART_INTSTS_HWBUFEINT_Msk : In PDMA Mode, Buffer Error Interrupt Indicator
* - \ref UART_INTSTS_HWTOINT_Msk : In PDMA Mode, Time-out Interrupt Indicator
* - \ref UART_INTSTS_HWMODINT_Msk : In PDMA Mode, MODEM Status Interrupt Indicator
* - \ref UART_INTSTS_HWRLSINT_Msk : In PDMA Mode, Receive Line Status Interrupt Indicator
* - \ref UART_INTSTS_SWBEINT_Msk : In Single-wire Mode, Bit Error Detect Interrupt Indicator
* - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag
* - \ref UART_INTSTS_HWBUFEIF_Msk : In PDMA Mode, Buffer Error Interrupt Flag
* - \ref UART_INTSTS_HWTOIF_Msk : In PDMA Mode, Time-out Interrupt Flag
* - \ref UART_INTSTS_HWMODIF_Msk : In PDMA Mode, MODEM Interrupt Flag
* - \ref UART_INTSTS_HWRLSIF_Msk : In PDMA Mode, Receive Line Status Flag
* - \ref UART_INTSTS_SWBEIF_Msk : In Single-wire Mode, Bit Error Detection Interrupt Flag
* - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
* - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
* - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
* - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
* - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
* - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
* - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag
* - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
* - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
* - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
* - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
* - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
* - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
*
* @retval 0 The specified interrupt is not happened.
* 1 The specified interrupt is happened.
*
* @details This macro get specified interrupt flag or interrupt indicator status.
* \hideinitializer
*/
#define UART_GET_INT_FLAG(uart,u32IntTypeFlag) (((uart)->INTSTS & (u32IntTypeFlag))?1:0)
/**
* @brief Clear RS-485 Address Byte Detection Flag
*
* @param[in] uart The pointer of the specified UART module
*
* @return None
*
* @details This macro clear RS-485 address byte detection flag.
* \hideinitializer
*/
#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
/**
* @brief Get RS-485 Address Byte Detection Flag
*
* @param[in] uart The pointer of the specified UART module
*
* @retval 0 Receiver detects a data that is not an address bit.
* @retval 1 Receiver detects a data that is an address bit.
*
* @details This macro get RS-485 address byte detection flag.
* \hideinitializer
*/
#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart);
__STATIC_INLINE void UART_SET_RTS(UART_T *uart);
/**
* @brief Set RTS pin to low
*
* @param[in] uart The pointer of the specified UART module
*
* @return None
*
* @details This macro set RTS pin to low.
*/
__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart)
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart->MODEM &= ~UART_MODEM_RTS_Msk;
}
/**
* @brief Set RTS pin to high
*
* @param[in] uart The pointer of the specified UART module
*
* @return None
*
* @details This macro set RTS pin to high.
*/
__STATIC_INLINE void UART_SET_RTS(UART_T *uart)
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
}
void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag);
void UART_Close(UART_T *uart);
void UART_DisableFlowCtrl(UART_T *uart);
void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag);
void UART_EnableFlowCtrl(UART_T *uart);
void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag);
void UART_Open(UART_T *uart, uint32_t u32BaudRate);
uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
void UART_SetLine_Config(UART_T *uart, uint32_t u32BaudRate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC);
void UART_SelectIrDAMode(UART_T *uart, uint32_t u32BuadRate, uint32_t u32Direction);
void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr);
void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength);
uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
void UART_SelectSingleWireMode(UART_T *uart);
/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group UART_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /*__UART_H__*/
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/usbd.h Normal file
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/******************************************************************************
* @file usbd.h
* @version V0.10
* @brief M251 series USB driver header file
*
* @copyrightt (C) 2017 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __USBD_H__
#define __USBD_H__
#ifdef __cplusplus
extern "C"
{
#endif
/*!< Definition for enabling Link Power Management(LPM) function.
LPM related handler will raise after LPM event happen.
if bcdUSB >= 0x0201, USB version is equal or higher than 2.1,
OS(Windows) will issue "get BOS descriptor" request to check the support of LPM.
Notice:
If bcdUSB >= 0x0201, where USB version is equal or higher than 2.1,
WIN8 ~ WIN10 will fail to enumerate the device if device stalls the "get BOS descriptor" request.
WIN7 can still enumerate this device even though the "get BOS descriptor" request been stalled.
*/
//#define SUPPORT_LPM
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup USBD_Driver USBD Driver
@{
*/
/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs
@{
*/
typedef struct s_usbd_info
{
uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */
uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */
uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */
uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */
uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
} S_USBD_INFO_T; /*!< Device description structure */
extern const S_USBD_INFO_T gsInfo;
/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */
/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
@{
*/
#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */
#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */
#define EP0 0ul /*!< Endpoint 0 \hideinitializer */
#define EP1 1ul /*!< Endpoint 1 \hideinitializer */
#define EP2 2ul /*!< Endpoint 2 \hideinitializer */
#define EP3 3ul /*!< Endpoint 3 \hideinitializer */
#define EP4 4ul /*!< Endpoint 4 \hideinitializer */
#define EP5 5ul /*!< Endpoint 5 \hideinitializer */
#define EP6 6ul /*!< Endpoint 6 \hideinitializer */
#define EP7 7ul /*!< Endpoint 7 \hideinitializer */
#define EP8 8ul /*!< Endpoint 8 \hideinitializer */
#define EP9 9ul /*!< Endpoint 9 \hideinitializer */
#define EP10 10ul /*!< Endpoint 10 \hideinitializer */
#define EP11 11ul /*!< Endpoint 11 \hideinitializer */
/*!<USB Request Type */
#define REQ_STANDARD 0x00ul
#define REQ_CLASS 0x20ul
#define REQ_VENDOR 0x40ul
/*!<USB Standard Request */
#define GET_STATUS 0x00ul
#define CLEAR_FEATURE 0x01ul
#define SET_FEATURE 0x03ul
#define SET_ADDRESS 0x05ul
#define GET_DESCRIPTOR 0x06ul
#define SET_DESCRIPTOR 0x07ul
#define GET_CONFIGURATION 0x08ul
#define SET_CONFIGURATION 0x09ul
#define GET_INTERFACE 0x0Aul
#define SET_INTERFACE 0x0Bul
#define SYNC_FRAME 0x0Cul
/*!<USB Descriptor Type */
#define DESC_DEVICE 0x01ul
#define DESC_CONFIG 0x02ul
#define DESC_STRING 0x03ul
#define DESC_INTERFACE 0x04ul
#define DESC_ENDPOINT 0x05ul
#define DESC_QUALIFIER 0x06ul
#define DESC_OTHERSPEED 0x07ul
#define DESC_IFPOWER 0x08ul
#define DESC_OTG 0x09ul
#define DESC_BOS 0x0Ful
#define DESC_CAPABILITY 0x10ul
/*!<USB Device Capability Type */
#define CAP_WIRELESS 0x01ul
#define CAP_USB20_EXT 0x02ul
/*!<USB HID Descriptor Type */
#define DESC_HID 0x21ul
#define DESC_HID_RPT 0x22ul
/*!<USB Descriptor Length */
#define LEN_DEVICE 18ul
#define LEN_QUALIFIER 10ul
#define LEN_CONFIG 9ul
#define LEN_INTERFACE 9ul
#define LEN_ENDPOINT 7ul
#define LEN_OTG 5ul
#define LEN_BOS 5ul
#define LEN_HID 9ul
#define LEN_CCID 0x36ul
#define LEN_DEVCAP 7ul
/*!<USB Endpoint Type */
#define EP_ISO 0x01ul
#define EP_BULK 0x02ul
#define EP_INT 0x03ul
#define EP_INPUT 0x80ul
#define EP_OUTPUT 0x00ul
/*!<USB Feature Selector */
#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul
#define FEATURE_ENDPOINT_HALT 0x00ul
/******************************************************************************/
/* USB Specific Macros */
/******************************************************************************/
#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable */
#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 */
#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable */
#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On */
#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable */
#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable */
#define USBD_RWAKEUP USBD_ATTR_RWAKEUP_Msk /*!< Remote Wake Up Enable */
#define USBD_LPMACK USBD_ATTR_LPMACK_Msk /*!< LPM Enable */
#define USBD_BYTEM USBD_ATTR_BYTEM_Msk /*!< Byte Mode Enable */
#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt */
#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt */
#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt */
#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt */
#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status */
#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status */
#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status */
#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status */
#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event */
#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event */
#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event */
#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event */
#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event */
#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event */
#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event */
#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event */
#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event */
#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event */
#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event */
#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event */
#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event */
#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset */
#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend */
#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume */
#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout */
#define USBD_STATE_L1RESUME USBD_ATTR_L1RESUME_Msk /*!< USB Bus L1RESUME */
#define USBD_STATE_L1SUSPEND USBD_ATTR_L1SUSPEND_Msk /*!< USB BUS L1SUSPEND */
#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall */
#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */
#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable */
#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint */
#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint */
#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous */
/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */
/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
@{
*/
/**
* @brief Compare two input numbers and return maximum one.
*
* @param[in] a First number to be compared.
* @param[in] b Second number to be compared.
*
* @return Maximum value between a and b.
*
* @details If a > b, then return a. Otherwise, return b.
*/
#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b))
/**
* @brief Compare two input numbers and return minimum one
*
* @param[in] a First number to be compared
* @param[in] b Second number to be compared
*
* @return Minimum value between a and b
*
* @details If a < b, then return a. Otherwise, return b.
*/
#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b))
/**
* @brief Enable USB
*
* @param None
*
* @return None
*
* @details To set USB ATTR control register to enable USB and PHY.
*
*/
#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0))
/**
* @brief Disable USB
*
* @param None
*
* @return None
*
* @details To set USB ATTR control register to disable USB.
*
*/
#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
/**
* @brief Enable USB PHY
*
* @param None
*
* @return None
*
* @details To set USB ATTR control register to enable USB PHY.
*
*/
#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
/**
* @brief Disable USB PHY
*
* @param None
*
* @return None
*
* @details To set USB ATTR control register to disable USB PHY.
*
*/
#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
/**
* @brief Enable SE0. Force USB PHY transceiver to drive SE0.
*
* @param None
*
* @return None
*
* @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
*
*/
#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
/**
* @brief Disable SE0
*
* @param None
*
* @return None
*
* @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
*
*/
#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
/**
* @brief Set USB device address
*
* @param[in] addr The USB device address.
*
* @return None
*
* @details Write USB device address to USB_FADDR register.
*
*/
#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
/**
* @brief Get USB device address
*
* @param None
*
* @return USB device address
*
* @details Read USB_FADDR register to get USB device address.
*
*/
#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
/**
* @brief Enable USB interrupt function
*
* @param[in] intr The combination of the specified interrupt enable bits.
* Each bit corresponds to a interrupt enable bit.
* This parameter decides which interrupts will be enabled.
* (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
*
* @return None
*
* @details Enable USB related interrupt functions specified by intr parameter.
*
*/
#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
/**
* @brief Get interrupt status
*
* @param None
*
* @return The value of USB_INTSTS register
*
* @details Return all interrupt flags of USB_INTSTS register.
*
*/
#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
/**
* @brief Clear USB interrupt flag
*
* @param[in] flag The combination of the specified interrupt flags.
* Each bit corresponds to a interrupt source.
* This parameter decides which interrupt flags will be cleared.
* (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
*
* @return None
*
* @details Clear USB related interrupt flags specified by flag parameter.
*
*/
#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag))
/**
* @brief Get endpoint status
*
* @param None
*
* @return The value of USB_EPSTS register.
*
* @details Return all endpoint status.
*
*/
#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
/**
* @brief Get USB bus state
*
* @param None
*
* @return The value of USB_ATTR[3:0] and USB_ATTR[13:12].
* Bit 0 indicates USB bus reset status.
* Bit 1 indicates USB bus suspend status.
* Bit 2 indicates USB bus resume status.
* Bit 3 indicates USB bus time-out status.
* Bit 12 indicates USB bus LPM L1 suspend status.
* Bit 13 indicates USB bus LPM L1 resume status.
*
* @details Return USB_ATTR[3:0] and USB_ATTR[13:12] for USB bus events.
*
* \hideinitializer
*/
#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0x300f))
/**
* @brief Check cable connection state
*
* @param None
*
* @retval 0 USB cable is not attached.
* @retval 1 USB cable is attached.
*
* @details Check the connection state by FLDET bit of USB_FLDET register.
*
*/
#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
/**
* @brief Stop USB transaction of the specified endpoint ID
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @return None
*
* @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
*
*/
#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
/**
* @brief Set USB DATA1 PID for the specified endpoint ID
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @return None
*
* @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
* Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
*
*/
#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
/**
* @brief Set USB DATA0 PID for the specified endpoint ID
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @return None
*
* @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
* Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
*
*/
#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
/**
* @brief Set USB payload size (IN data)
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @param[in] size The transfer length.
*
* @return None
*
* @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
*
*/
#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
/**
* @brief Get USB payload size (OUT data)
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 endpoint ID. This parameter could be 0 ~ 11.
*
* @return The value of USB_MXPLDx register.
*
* @details Get the data length of OUT data transaction by reading USB_MXPLDx register.
*
*/
#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
/**
* @brief Configure endpoint
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @param[in] config The USB configuration.
*
* @return None
*
* @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.
*
*/
#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
/**
* @brief Set USB endpoint buffer
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @param[in] offset The SRAM offset.
*
* @return None
*
* @details This macro will set the SRAM offset for the specified endpoint ID.
*
*/
#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
/**
* @brief Get the offset of the specified USB endpoint buffer
*
@param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @return The offset of the specified endpoint buffer.
*
* @details This macro will return the SRAM offset of the specified endpoint ID.
*
*/
#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
/**
* @brief Set USB endpoint stall state
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @return None
*
* @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
*
*/
#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
/**
* @brief Clear USB endpoint stall state
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @return None
*
* @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
*/
#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
/**
* @brief Get USB endpoint stall state
*
* @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
*
* @retval 0 USB endpoint is not stalled.
* @retval Others USB endpoint is stalled.
*
* @details Get USB endpoint stall state of the specified endpoint ID.
*
*/
#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
/**
* @brief To support byte access between USB SRAM and system SRAM
*
* @param[in] dest Destination pointer.
*
* @param[in] src Source pointer.
*
* @param[in] size Byte count.
*
* @return None
*
* @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
*
*/
__STATIC_INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, uint32_t size)
{
while (size--) *dest++ = *src++;
}
/**
* @brief Set USB endpoint stall state
*
* @param[in] epnum USB endpoint number
*
* @return None
*
* @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.
*
*/
__STATIC_INLINE void USBD_SetStall(uint8_t epnum)
{
uint32_t u32CfgAddr;
uint32_t u32Cfg;
uint32_t i;
for (i = 0ul; i < USBD_MAX_EP; i++)
{
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
if ((u32Cfg & 0xful) == epnum)
{
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
break;
}
}
}
/**
* @brief Clear USB endpoint stall state
*
* @param[in] epnum USB endpoint number
*
* @return None
*
* @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
*/
__STATIC_INLINE void USBD_ClearStall(uint8_t epnum)
{
uint32_t u32CfgAddr;
uint32_t u32Cfg;
uint32_t i;
for (i = 0ul; i < USBD_MAX_EP; i++)
{
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
if ((u32Cfg & 0xful) == epnum)
{
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
break;
}
}
}
/**
* @brief Get USB endpoint stall state
*
* @param[in] epnum USB endpoint number
*
* @retval 0 USB endpoint is not stalled.
* @retval Others USB endpoint is stalled.
*
* @details Get USB endpoint stall state.
*
*/
__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)
{
uint32_t u32CfgAddr;
uint32_t u32Cfg;
uint32_t i;
for (i = 0ul; i < USBD_MAX_EP; i++)
{
u32CfgAddr = (uint32_t)(i << 4ul) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
if ((u32Cfg & 0xful) == epnum)
{
u32CfgAddr = (uint32_t)(i << 4ul) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
break;
}
}
return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
}
extern volatile uint8_t g_USBD_u8RemoteWakeupEn;
typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */
typedef void (*SET_INTERFACE_REQ)(void); /*!< Functional pointer type declaration for USB set interface request callback handler */
typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
/*--------------------------------------------------------------------*/
void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
void USBD_Start(void);
void USBD_GetSetupPacket(uint8_t *buf);
void USBD_ProcessSetupPacket(void);
void USBD_StandardRequest(void);
void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);
void USBD_CtrlIn(void);
void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
void USBD_CtrlOut(void);
void USBD_SwReset(void);
void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
void USBD_LockEpStall(uint32_t u32EpBitmap);
/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group USBD_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __USBD_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file usci_i2c.h
* @version V0.10
* @brief M251 series USCI I2C(UI2C) driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __USCI_I2C_H__
#define __USCI_I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
@{
*/
/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* USCI_I2C master event definitions */
/*---------------------------------------------------------------------------------------------------------*/
enum UI2C_MASTER_EVENT
{
MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */
MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */
MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */
MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */
MASTER_SEND_DATA, /*!< Master Send Data to Slave */
MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */
MASTER_READ_DATA, /*!< Master Get Data from Slave */
MASTER_STOP, /*!< Master send stop to Slave */
MASTER_SEND_START /*!< Master send start to Slave */
};
/*---------------------------------------------------------------------------------------------------------*/
/* USCI_I2C slave event definitions */
/*---------------------------------------------------------------------------------------------------------*/
enum UI2C_SLAVE_EVENT
{
SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */
SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */
SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */
SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */
SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */
SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */
SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */
};
/*---------------------------------------------------------------------------------------------------------*/
/* USCI_CTL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */
#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* USCI_I2C GCMode constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */
#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* USCI_I2C Wakeup Mode constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */
#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* USCI_I2C interrupt mask definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */
#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */
#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */
#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */
#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */
#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */
#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */
/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */
/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
@{
*/
/**
* @brief This macro sets the USCI_I2C protocol control register at one time
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
* @param[in] u8Ctrl Set the register value of USCI_I2C control register.
*
* @return None
*
* @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK.
* \hideinitializer
*/
#define UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl) ((psUI2C)->PROTCTL = ((psUI2C)->PROTCTL & ~0x2EU) | (u8Ctrl))
/**
* @brief This macro only set START bit to protocol control register of USCI_I2C module.
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return None
*
* @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register.
* \hideinitializer
*/
#define UI2C_START(psUI2C) ((psUI2C)->PROTCTL = ((psUI2C)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)
/**
* @brief This macro only set STOP bit to the control register of USCI_I2C module
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return None
*
* @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.
* \hideinitializer
*/
#define UI2C_STOP(psUI2C) ((psUI2C)->PROTCTL = ((psUI2C)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))
/**
* @brief This macro returns the data stored in data register of USCI_I2C module
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return Data
*
* @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus
* \hideinitializer
*/
#define UI2C_GET_DATA(psUI2C) ((psUI2C)->RXDAT)
/**
* @brief This macro writes the data to data register of USCI_I2C module
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
* @param[in] u8Data The data which will be written to data register of USCI_I2C module.
*
* @return None
*
* @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus
* \hideinitializer
*/
#define UI2C_SET_DATA(psUI2C, u8Data) ((psUI2C)->TXDAT = (u8Data))
/**
* @brief This macro returns time-out flag
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @retval 0 USCI_I2C bus time-out is not happened
* @retval 1 USCI_I2C bus time-out is happened
*
* @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.
* \hideinitializer
*/
#define UI2C_GET_TIMEOUT_FLAG(psUI2C) (((psUI2C)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)
/**
* @brief This macro returns wake-up flag
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @retval 0 Chip is not woken-up from power-down mode
* @retval 1 Chip is woken-up from power-down mode
*
* @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.
* \hideinitializer
*/
#define UI2C_GET_WAKEUP_FLAG(psUI2C) (((psUI2C)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)
/**
* @brief This macro is used to clear USCI_I2C wake-up flag
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return None
*
* @details If USCI_I2C wake-up flag is set, use this macro to clear it.
* \hideinitializer
*/
#define UI2C_CLR_WAKEUP_FLAG(psUI2C) ((psUI2C)->WKSTS = UI2C_WKSTS_WKF_Msk)
/**
* @brief This macro disables the USCI_I2C 10-bit address mode
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return None
*
* @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.
* \hideinitializer
*/
#define UI2C_DISABLE_10BIT_ADDR_MODE(psUI2C) ((psUI2C)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))
/**
* @brief This macro enables the 10-bit address mode
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return None
*
* @details To enable USCI_I2C 10-bit address match function.
* \hideinitializer
*/
#define UI2C_ENABLE_10BIT_ADDR_MODE(psUI2C) ((psUI2C)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)
/**
* @brief This macro gets USCI_I2C protocol interrupt flag or bus status
*
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
*
* @return A word data of USCI_I2C_PROTSTS register
*
* @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.
* \hideinitializer
*/
#define UI2C_GET_PROT_STATUS(psUI2C) ((psUI2C)->PROTSTS)
/**
* @brief This macro clears specified protocol interrupt flag
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref UI2C_PROTSTS_ACKIF_Msk
* - \ref UI2C_PROTSTS_ERRIF_Msk
* - \ref UI2C_PROTSTS_ARBLOIF_Msk
* - \ref UI2C_PROTSTS_NACKIF_Msk
* - \ref UI2C_PROTSTS_STORIF_Msk
* - \ref UI2C_PROTSTS_STARIF_Msk
* - \ref UI2C_PROTSTS_TOIF_Msk
* @return None
*
* @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.
* \hideinitializer
*/
#define UI2C_CLR_PROT_INT_FLAG(psUI2C,u32IntTypeFlag) ((psUI2C)->PROTSTS = (u32IntTypeFlag))
/**
* @brief This macro enables specified protocol interrupt
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref UI2C_PROTIEN_ACKIEN_Msk
* - \ref UI2C_PROTIEN_ERRIEN_Msk
* - \ref UI2C_PROTIEN_ARBLOIEN_Msk
* - \ref UI2C_PROTIEN_NACKIEN_Msk
* - \ref UI2C_PROTIEN_STORIEN_Msk
* - \ref UI2C_PROTIEN_STARIEN_Msk
* - \ref UI2C_PROTIEN_TOIEN_Msk
* @return None
*
* @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function.
* \hideinitializer
*/
#define UI2C_ENABLE_PROT_INT(psUI2C, u32IntSel) ((psUI2C)->PROTIEN |= (u32IntSel))
/**
* @brief This macro disables specified protocol interrupt
* @param[in] psUI2C The pointer of the specified USCI_I2C module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref UI2C_PROTIEN_ACKIEN_Msk
* - \ref UI2C_PROTIEN_ERRIEN_Msk
* - \ref UI2C_PROTIEN_ARBLOIEN_Msk
* - \ref UI2C_PROTIEN_NACKIEN_Msk
* - \ref UI2C_PROTIEN_STORIEN_Msk
* - \ref UI2C_PROTIEN_STARIEN_Msk
* - \ref UI2C_PROTIEN_TOIEN_Msk
* @return None
*
* @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function.
* \hideinitializer
*/
#define UI2C_DISABLE_PROT_INT(psUI2C, u32IntSel) ((psUI2C)->PROTIEN &= ~ (u32IntSel))
uint32_t UI2C_Open(UI2C_T *psUI2C, uint32_t u32BusClock);
void UI2C_Close(UI2C_T *psUI2C);
void UI2C_ClearTimeoutFlag(UI2C_T *psUI2C);
void UI2C_Trigger(UI2C_T *psUI2C, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);
void UI2C_DisableInt(UI2C_T *psUI2C, uint32_t u32Mask);
void UI2C_EnableInt(UI2C_T *psUI2C, uint32_t u32Mask);
uint32_t UI2C_GetBusClockFreq(UI2C_T *psUI2C);
uint32_t UI2C_SetBusClockFreq(UI2C_T *psUI2C, uint32_t u32BusClock);
uint32_t UI2C_GetIntFlag(UI2C_T *psUI2C, uint32_t u32Mask);
void UI2C_ClearIntFlag(UI2C_T *psUI2C, uint32_t u32Mask);
uint32_t UI2C_GetData(UI2C_T *psUI2C);
void UI2C_SetData(UI2C_T *psUI2C, uint8_t u8Data);
void UI2C_SetSlaveAddr(UI2C_T *psUI2C, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
void UI2C_SetSlaveAddrMask(UI2C_T *psUI2C, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
void UI2C_EnableTimeout(UI2C_T *psUI2C, uint32_t u32TimeoutCnt);
void UI2C_DisableTimeout(UI2C_T *psUI2C);
void UI2C_EnableWakeup(UI2C_T *psUI2C, uint8_t u8WakeupMode);
void UI2C_DisableWakeup(UI2C_T *psUI2C);
uint8_t UI2C_WriteByte(UI2C_T *psUI2C, uint8_t u8SlaveAddr, const uint8_t u8Data);
uint32_t UI2C_WriteMultiBytes(UI2C_T *psUI2C, uint8_t u8SlaveAddr, const uint8_t *pu8Data, uint32_t u32WLen);
uint8_t UI2C_WriteByteOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t u8Data);
uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t *pu8Data, uint32_t u32WLen);
uint8_t UI2C_WriteByteTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t u8Data);
uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t *pu8Data, uint32_t u32WLen);
uint8_t UI2C_ReadByte(UI2C_T *psUI2C, uint8_t u8SlaveAddr);
uint32_t UI2C_ReadMultiBytes(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t *pu8RData, uint32_t u32RLen);
uint8_t UI2C_ReadByteOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *pu8RData, uint32_t u32RLen);
uint8_t UI2C_ReadByteTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *pu8RData, uint32_t u32RLen);
/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group USCI_I2C_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __USCI_I2C_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/****************************************************************************//**
* @file usci_spi.h
* @version V0.10
* @brief M251 series USCI_SPI driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USCI_SPI_H__
#define __USCI_SPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
@{
*/
/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants
@{
*/
#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */
#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */
#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */
#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */
#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */
#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */
#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */
#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */
/* USCI_SPI Interrupt Mask */
#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */
#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */
#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */
#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */
#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */
#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */
#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */
#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */
#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */
#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */
/* USCI_SPI Status Mask */
#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */
#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */
#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */
#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */
#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */
#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */
/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */
/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
@{
*/
/**
* @brief Disable slave 3-wire mode.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None
* \hideinitializer
*/
#define USPI_DISABLE_3WIRE_MODE(psUSPI) ( (psUSPI)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )
/**
* @brief Enable slave 3-wire mode.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None
* \hideinitializer
*/
#define USPI_ENABLE_3WIRE_MODE(psUSPI) ( (psUSPI)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )
/**
* @brief Get the Rx buffer empty flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return Rx buffer flag
* @retval 0: Rx buffer is not empty
* @retval 1: Rx buffer is empty
* \hideinitializer
*/
#define USPI_GET_RX_EMPTY_FLAG(psUSPI) ( ((psUSPI)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )
/**
* @brief Get the Tx buffer empty flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return Tx buffer flag
* @retval 0: Tx buffer is not empty
* @retval 1: Tx buffer is empty
* \hideinitializer
*/
#define USPI_GET_TX_EMPTY_FLAG(psUSPI) ( ((psUSPI)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )
/**
* @brief Get the Tx buffer full flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return Tx buffer flag
* @retval 0: Tx buffer is not full
* @retval 1: Tx buffer is full
* \hideinitializer
*/
#define USPI_GET_TX_FULL_FLAG(psUSPI) ( ((psUSPI)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )
/**
* @brief Get the datum read from RX register.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return data in Rx register
* \hideinitializer
*/
#define USPI_READ_RX(psUSPI) ((psUSPI)->RXDAT)
/**
* @brief Write datum to TX register.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus.
* @return None
* \hideinitializer
*/
#define USPI_WRITE_TX(psUSPI, u32TxData) ( (psUSPI)->TXDAT = (u32TxData) )
/**
* @brief Set USCI_SPI_SS pin to high state.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None.
* @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.
* \hideinitializer
*/
#define USPI_SET_SS_HIGH(psUSPI) \
do{ \
(psUSPI)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
(psUSPI)->PROTCTL = ((psUSPI)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \
}while(0)
/**
* @brief Set USCI_SPI_SS pin to low state.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None.
* @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.
* \hideinitializer
*/
#define USPI_SET_SS_LOW(psUSPI) \
do{ \
(psUSPI)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
(psUSPI)->PROTCTL = (((psUSPI)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
}while(0)
/**
* @brief Set the length of suspend interval.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32SuspCycle Decide the length of suspend interval.
* @return None
* \hideinitializer
*/
#define USPI_SET_SUSPEND_CYCLE(psUSPI, u32SuspCycle) ( (psUSPI)->PROTCTL = ((psUSPI)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) )
/**
* @brief Set the USCI_SPI transfer sequence with LSB first.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None
* \hideinitializer
*/
#define USPI_SET_LSB_FIRST(psUSPI) ( (psUSPI)->LINECTL |= USPI_LINECTL_LSB_Msk )
/**
* @brief Set the USCI_SPI transfer sequence with MSB first.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None
* \hideinitializer
*/
#define USPI_SET_MSB_FIRST(psUSPI) ( (psUSPI)->LINECTL &= ~USPI_LINECTL_LSB_Msk )
/**
* @brief Set the data width of a USCI_SPI transaction.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32Width The data width
* @return None
* \hideinitializer
*/
#define USPI_SET_DATA_WIDTH(psUSPI,u32Width) \
do{ \
if((u32Width) == 16ul){ \
(psUSPI)->LINECTL = ((psUSPI)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \
}else { \
(psUSPI)->LINECTL = ((psUSPI)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \
} \
}while(0)
/**
* @brief Get the USCI_SPI busy state.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return USCI_SPI busy status
* @retval 0: USCI_SPI module is not busy
* @retval 1: USCI_SPI module is busy
* \hideinitializer
*/
#define USPI_IS_BUSY(psUSPI) ( ((psUSPI)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )
/**
* @brief Get the USCI_SPI wakeup flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return Wakeup status.
* @retval 0 Flag is not set.
* @retval 1 Flag is set.
* \hideinitializer
*/
#define USPI_GET_WAKEUP_FLAG(psUSPI) ( ((psUSPI)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0)
/**
* @brief Clear the USCI_SPI wakeup flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None
* \hideinitializer
*/
#define USPI_CLR_WAKEUP_FLAG(psUSPI) ( (psUSPI)->WKSTS |= USPI_WKSTS_WKF_Msk)
/**
* @brief Get protocol interrupt flag/status.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return The interrupt flag/status of protocol status register.
* \hideinitializer
*/
#define USPI_GET_PROT_STATUS(psUSPI) ( (psUSPI)->PROTSTS)
/**
* @brief Clear specified protocol interrupt flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref USPI_PROTSTS_SSACTIF_Msk
* - \ref USPI_PROTSTS_SSINAIF_Msk
* - \ref USPI_PROTSTS_SLVBEIF_Msk
* - \ref USPI_PROTSTS_SLVTOIF_Msk
* - \ref USPI_PROTSTS_RXENDIF_Msk
* - \ref USPI_PROTSTS_RXSTIF_Msk
* - \ref USPI_PROTSTS_TXENDIF_Msk
* - \ref USPI_PROTSTS_TXSTIF_Msk
* @return None
* \hideinitializer
*/
#define USPI_CLR_PROT_INT_FLAG(psUSPI,u32IntTypeFlag) ( (psUSPI)->PROTSTS = (u32IntTypeFlag))
/**
* @brief Get buffer interrupt flag/status.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return The interrupt flag/status of buffer status register.
* \hideinitializer
*/
#define USPI_GET_BUF_STATUS(psUSPI) ( (psUSPI)->BUFSTS)
/**
* @brief Clear specified buffer interrupt flag.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref USPI_BUFSTS_TXUDRIF_Msk
* - \ref USPI_BUFSTS_RXOVIF_Msk
* @return None
* \hideinitializer
*/
#define USPI_CLR_BUF_INT_FLAG(psUSPI,u32IntTypeFlag) ( (psUSPI)->BUFSTS = (u32IntTypeFlag))
/**
* @brief Enable specified protocol interrupt.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref USPI_PROTIEN_SLVBEIEN_Msk
* - \ref USPI_PROTIEN_SLVTOIEN_Msk
* - \ref USPI_PROTIEN_SSACTIEN_Msk
* - \ref USPI_PROTIEN_SSINAIEN_Msk
* @return None
* \hideinitializer
*/
#define USPI_ENABLE_PROT_INT(psUSPI, u32IntSel) ((psUSPI)->PROTIEN |= (u32IntSel))
/**
* @brief Disable specified protocol interrupt.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref USPI_PROTIEN_SLVBEIEN_Msk
* - \ref USPI_PROTIEN_SLVTOIEN_Msk
* - \ref USPI_PROTIEN_SSACTIEN_Msk
* - \ref USPI_PROTIEN_SSINAIEN_Msk
* @return None
* \hideinitializer
*/
#define USPI_DISABLE_PROT_INT(psUSPI, u32IntSel) ((psUSPI)->PROTIEN &= ~ (u32IntSel))
/**
* @brief Enable specified buffer interrupt.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref USPI_BUFCTL_RXOVIEN_Msk
* - \ref USPI_BUFCTL_TXUDRIEN_Msk
* @return None
* \hideinitializer
*/
#define USPI_ENABLE_BUF_INT(psUSPI, u32IntSel) ((psUSPI)->BUFCTL |= (u32IntSel))
/**
* @brief Disable specified buffer interrupt.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref USPI_BUFCTL_RXOVIEN_Msk
* - \ref USPI_BUFCTL_TXUDRIEN_Msk
* @return None
* \hideinitializer
*/
#define USPI_DISABLE_BUF_INT(psUSPI, u32IntSel) ((psUSPI)->BUFCTL &= ~ (u32IntSel))
/**
* @brief Enable specified transfer interrupt.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref USPI_INTEN_RXENDIEN_Msk
* - \ref USPI_INTEN_RXSTIEN_Msk
* - \ref USPI_INTEN_TXENDIEN_Msk
* - \ref USPI_INTEN_TXSTIEN_Msk
* @return None
* \hideinitializer
*/
#define USPI_ENABLE_TRANS_INT(psUSPI, u32IntSel) ((psUSPI)->INTEN |= (u32IntSel))
/**
* @brief Disable specified transfer interrupt.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @param[in] u32IntSel Interrupt Type, should be
* - \ref USPI_INTEN_RXENDIEN_Msk
* - \ref USPI_INTEN_RXSTIEN_Msk
* - \ref USPI_INTEN_TXENDIEN_Msk
* - \ref USPI_INTEN_TXSTIEN_Msk
* @return None
* \hideinitializer
*/
#define USPI_DISABLE_TRANS_INT(psUSPI, u32IntSel) ((psUSPI)->INTEN &= ~ (u32IntSel))
/**
* @brief Trigger RX PDMA function.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None.
* @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define USPI_TRIGGER_RX_PDMA(psUSPI) ((psUSPI)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
/**
* @brief Trigger TX PDMA function.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None.
* @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define USPI_TRIGGER_TX_PDMA(psUSPI) ((psUSPI)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None.
* @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define USPI_DISABLE_RX_PDMA(psUSPI) ( (psUSPI)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable TX PDMA transfer.
* @param[in] psUSPI The pointer of the specified USCI_SPI module.
* @return None.
* @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define USPI_DISABLE_TX_PDMA(psUSPI) ( (psUSPI)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
uint32_t USPI_Open(USPI_T *psUSPI, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void USPI_Close(USPI_T *psUSPI);
void USPI_ClearRxBuf(USPI_T *psUSPI);
void USPI_ClearTxBuf(USPI_T *psUSPI);
void USPI_DisableAutoSS(USPI_T *psUSPI);
void USPI_EnableAutoSS(USPI_T *psUSPI, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t USPI_SetBusClock(USPI_T *psUSPI, uint32_t u32BusClock);
uint32_t USPI_GetBusClock(USPI_T *psUSPI);
void USPI_EnableInt(USPI_T *psUSPI, uint32_t u32Mask);
void USPI_DisableInt(USPI_T *psUSPI, uint32_t u32Mask);
uint32_t USPI_GetIntFlag(USPI_T *psUSPI, uint32_t u32Mask);
void USPI_ClearIntFlag(USPI_T *psUSPI, uint32_t u32Mask);
uint32_t USPI_GetStatus(USPI_T *psUSPI, uint32_t u32Mask);
void USPI_EnableWakeup(USPI_T *psUSPI);
void USPI_DisableWakeup(USPI_T *psUSPI);
/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group USCI_SPI_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __USCI_SPI_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/inc/usci_uart.h Normal file
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@@ -0,0 +1,490 @@
/**************************************************************************//**
* @file usci_uart.h
* @version V0.10
* @brief M251 series USCI UART (UUART) driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __USCI_UART_H__
#define __USCI_UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup USCI_UART_Driver USCI_UART Driver
@{
*/
/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* UUART_LINECTL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */
#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */
#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */
#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* UUART_PROTCTL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */
#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */
#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */
#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */
#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* USCI UART interrupt mask definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */
#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */
#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */
#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */
#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */
#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */
#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */
/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */
/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
@{
*/
/**
* @brief Write USCI_UART data
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u8Data Data byte to transmit.
*
* @return None
*
* @details This macro write Data to Tx data register.
* \hideinitializer
*/
#define UUART_WRITE(psUUART, u8Data) ((psUUART)->TXDAT = (u8Data))
/**
* @brief Read USCI_UART data
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @return The oldest data byte in RX buffer.
*
* @details This macro read Rx data register.
* \hideinitializer
*/
#define UUART_READ(psUUART) ((psUUART)->RXDAT)
/**
* @brief Get Tx empty
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Tx buffer is not empty
* @retval >=1 Tx buffer is empty
*
* @details This macro get Transmitter buffer empty register value.
* \hideinitializer
*/
#define UUART_GET_TX_EMPTY(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)
/**
* @brief Get Rx empty
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Rx buffer is not empty
* @retval >=1 Rx buffer is empty
*
* @details This macro get Receiver buffer empty register value.
* \hideinitializer
*/
#define UUART_GET_RX_EMPTY(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)
/**
* @brief Check specified usci_uart port transmission is over.
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Tx transmission is not over
* @retval 1 Tx transmission is over
*
* @details This macro return Transmitter Empty Flag register bit value. \n
* It indicates if specified usci_uart port transmission is over nor not.
* \hideinitializer
*/
#define UUART_IS_TX_EMPTY(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)
/**
* @brief Check specified usci_uart port receiver is empty.
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Rx receiver is not empty
* @retval 1 Rx receiver is empty
*
* @details This macro return Receive Empty Flag register bit value. \n
* It indicates if specified usci_uart port receiver is empty nor not.
* \hideinitializer
*/
#define UUART_IS_RX_EMPTY(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)
/**
* @brief Wait specified usci_uart port transmission is over
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @return None
*
* @details This macro wait specified usci_uart port transmission is over.
* \hideinitializer
*/
#define UUART_WAIT_TX_EMPTY(psUUART) while(!((((psUUART)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))
/**
* @brief Check TX buffer is full or not
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 1 TX buffer is full
* @retval 0 TX buffer is not full
*
* @details This macro check TX buffer is full or not.
* \hideinitializer
*/
#define UUART_IS_TX_FULL(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)
/**
* @brief Check RX buffer is full or not
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 1 RX buffer is full
* @retval 0 RX buffer is not full
*
* @details This macro check RX buffer is full or not.
* \hideinitializer
*/
#define UUART_IS_RX_FULL(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)
/**
* @brief Get Tx full register value
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Tx buffer is not full.
* @retval >=1 Tx buffer is full.
*
* @details This macro get Tx full register value.
* \hideinitializer
*/
#define UUART_GET_TX_FULL(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)
/**
* @brief Get Rx full register value
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Rx buffer is not full.
* @retval >=1 Rx buffer is full.
*
* @details This macro get Rx full register value.
* \hideinitializer
*/
#define UUART_GET_RX_FULL(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)
/**
* @brief Enable specified USCI_UART protocol interrupt
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
*
* @return None
*
* @details This macro enable specified USCI_UART protocol interrupt.
* \hideinitializer
*/
#define UUART_ENABLE_PROT_INT(psUUART, u32IntSel) ((psUUART)->PROTIEN |= (u32IntSel))
/**
* @brief Disable specified USCI_UART protocol interrupt
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
*
* @return None
*
* @details This macro disable specified USCI_UART protocol interrupt.
* \hideinitializer
*/
#define UUART_DISABLE_PROT_INT(psUUART, u32IntSel) ((psUUART)->PROTIEN &= ~(u32IntSel))
/**
* @brief Enable specified USCI_UART buffer interrupt
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
*
* @return None
*
* @details This macro enable specified USCI_UART buffer interrupt.
* \hideinitializer
*/
#define UUART_ENABLE_BUF_INT(psUUART, u32IntSel) ((psUUART)->BUFCTL |= (u32IntSel))
/**
* @brief Disable specified USCI_UART buffer interrupt
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
*
* @return None
*
* @details This macro disable specified USCI_UART buffer interrupt.
* \hideinitializer
*/
#define UUART_DISABLE_BUF_INT(psUUART, u32IntSel) ((psUUART)->BUFCTL &= ~ (u32IntSel))
/**
* @brief Enable specified USCI_UART transfer interrupt
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
* - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
* - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
* - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
*
* @return None
*
* @details This macro enable specified USCI_UART transfer interrupt.
* \hideinitializer
*/
#define UUART_ENABLE_TRANS_INT(psUUART, u32IntSel) ((psUUART)->INTEN |= (u32IntSel))
/**
* @brief Disable specified USCI_UART transfer interrupt
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntSel Interrupt type select
* - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
* - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
* - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
* - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
*
* @return None
*
* @details This macro disable specified USCI_UART transfer interrupt.
* \hideinitializer
*/
#define UUART_DISABLE_TRANS_INT(psUUART, u32IntSel) ((psUUART)->INTEN &= ~(u32IntSel))
/**
* @brief Get protocol interrupt flag/status
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @return The interrupt flag/status of protocol status register.
*
* @details This macro get protocol status register value.
* \hideinitializer
*/
#define UUART_GET_PROT_STATUS(psUUART) ((psUUART)->PROTSTS)
/**
* @brief Clear specified protocol interrupt flag
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator
* - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag
* - \ref UUART_PROTSTS_BREAK_Msk : Break Flag
* - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag
* - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag
* - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag
* - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag
* - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag
* - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag
*
* @return None
*
* @details This macro clear specified protocol interrupt flag.
* \hideinitializer
*/
#define UUART_CLR_PROT_INT_FLAG(psUUART,u32IntTypeFlag) ((psUUART)->PROTSTS = (u32IntTypeFlag))
/**
* @brief Get transmit/receive buffer interrupt flag/status
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @return The interrupt flag/status of buffer status register.
*
* @details This macro get buffer status register value.
* \hideinitializer
*/
#define UUART_GET_BUF_STATUS(psUUART) ((psUUART)->BUFSTS)
/**
* @brief Clear specified buffer interrupt flag
*
* @param[in] psUUART The pointer of the specified USCI_UART module
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator
*
* @return None
*
* @details This macro clear specified buffer interrupt flag.
* \hideinitializer
*/
#define UUART_CLR_BUF_INT_FLAG(psUUART,u32IntTypeFlag) ((psUUART)->BUFSTS = (u32IntTypeFlag))
/**
* @brief Get wakeup flag
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @retval 0 Chip did not wake up from power-down mode.
* @retval 1 Chip waked up from power-down mode.
*
* @details This macro get wakeup flag.
* \hideinitializer
*/
#define UUART_GET_WAKEUP_FLAG(psUUART) ((psUUART)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )
/**
* @brief Clear wakeup flag
*
* @param[in] psUUART The pointer of the specified USCI_UART module
*
* @return None
*
* @details This macro clear wakeup flag.
* \hideinitializer
*/
#define UUART_CLR_WAKEUP_FLAG(psUUART) ((psUUART)->WKSTS = UUART_WKSTS_WKF_Msk)
/**
* @brief Trigger RX PDMA function.
*
* @param[in] psUUART The pointer of the specified USCI_UART module.
*
* @return None.
*
* @details Set RXPDMAEN bit of UUART_PDMACTL register to enable RX PDMA transfer function.
* \hideinitializer
*/
#define UUART_TRIGGER_RX_PDMA(psUUART) ((psUUART)->PDMACTL |= UUART_PDMACTL_RXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk)
/**
* @brief Trigger TX PDMA function.
*
* @param[in] psUUART The pointer of the specified USCI_UART module.
*
* @return None.
*
* @details Set TXPDMAEN bit of UUART_PDMACTL register to enable TX PDMA transfer function.
* \hideinitializer
*/
#define UUART_TRIGGER_TX_PDMA(psUUART) ((psUUART)->PDMACTL |= UUART_PDMACTL_TXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk)
/**
* @brief Disable RX PDMA transfer.
*
* @param[in] psUUART The pointer of the specified USCI_UART module.
*
* @return None.
*
* @details Clear RXPDMAEN bit of UUART_PDMACTL register to disable RX PDMA transfer function.
* \hideinitializer
*/
#define UUART_DISABLE_RX_PDMA(psUUART) ( (psUUART)->PDMACTL &= ~UUART_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Disable TX PDMA transfer.
*
* @param[in] psUUART The pointer of the specified USCI_UART module.
*
* @return None.
*
* @details Clear TXPDMAEN bit of UUART_PDMACTL register to disable TX PDMA transfer function.
* \hideinitializer
*/
#define UUART_DISABLE_TX_PDMA(psUUART) ( (psUUART)->PDMACTL &= ~UUART_PDMACTL_TXPDMAEN_Msk )
void UUART_ClearIntFlag(UUART_T *psUUART, uint32_t u32Mask);
uint32_t UUART_GetIntFlag(UUART_T *psUUART, uint32_t u32Mask);
void UUART_Close(UUART_T *psUUART);
void UUART_DisableInt(UUART_T *psUUART, uint32_t u32Mask);
void UUART_EnableInt(UUART_T *psUUART, uint32_t u32Mask);
uint32_t UUART_Open(UUART_T *psUUART, uint32_t u32Baudrate);
uint32_t UUART_Read(UUART_T *psUUART, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
uint32_t UUART_SetLine_Config(UUART_T *psUUART, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
uint32_t UUART_Write(UUART_T *psUUART, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
void UUART_EnableWakeup(UUART_T *psUUART, uint32_t u32WakeupMode);
void UUART_DisableWakeup(UUART_T *psUUART);
void UUART_EnableFlowCtrl(UUART_T *psUUART);
void UUART_DisableFlowCtrl(UUART_T *psUUART);
/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group USCI_UART_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __USCI_UART_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file wdt.h
* @version V0.10
* @brief M251 series WDT driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_H__
#define __WDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup WDT_Driver WDT Driver
@{
*/
/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* WDT Time-out Interval Period Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
#define WDT_TIMEOUT_2POW20 (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks */
/*---------------------------------------------------------------------------------------------------------*/
/* WDT Reset Delay Period Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
/*---------------------------------------------------------------------------------------------------------*/
/* WDT Free Reset Counter Keyword Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WDT_FREE_RESET_COUNTER_KEY (0x00005AA5) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter */
/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
@{
*/
/**
* @brief Clear WDT Reset System Flag
*
* @param None
*
* @return None
*
* @details This macro clears WDT time-out reset system flag.
*
* \hideinitializer
*/
#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
/**
* @brief Clear WDT Time-out Interrupt Flag
*
* @param None
*
* @return None
*
* @details This macro clears WDT time-out interrupt flag.
*
* \hideinitializer
*/
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
/**
* @brief Clear WDT Wake-up Flag
*
* @param None
*
* @return None
*
* @details This macro clears WDT time-out wake-up system flag.
*
* \hideinitializer
*/
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
/**
* @brief Get WDT Time-out Reset Flag
*
* @param None
*
* @retval 0 WDT time-out reset system did not occur
* @retval 1 WDT time-out reset system occurred
*
* @details This macro indicates system has been reset by WDT time-out reset or not.
*
* \hideinitializer
*/
#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
/**
* @brief Get WDT Time-out Interrupt Flag
*
* @param None
*
* @retval 0 WDT time-out interrupt did not occur
* @retval 1 WDT time-out interrupt occurred
*
* @details This macro indicates WDT time-out interrupt occurred or not.
*
* \hideinitializer
*/
#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
/**
* @brief Get WDT Time-out Wake-up Flag
*
* @param None
*
* @retval 0 WDT time-out interrupt does not cause CPU wake-up
* @retval 1 WDT time-out interrupt event cause CPU wake-up
*
* @details This macro indicates WDT time-out interrupt event has waked up system or not.
*
* \hideinitializer
*/
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
/**
* @brief Reset WDT Counter
*
* @param None
*
* @return None
*
* @details This macro is used to reset the internal 18-bit WDT up counter value.
* @note If WDT is activated and time-out reset system function is enabled also, user should \n
* reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
* reset system before the WDT time-out reset delay period expires.
*
* \hideinitializer
*/
#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_FREE_RESET_COUNTER_KEY)
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void WDT_Close(void);
__STATIC_INLINE void WDT_EnableInt(void);
__STATIC_INLINE void WDT_DisableInt(void);
/**
* @brief Stop WDT Counting
*
* @param None
*
* @return None
*
* @details This function will stop WDT counting and disable WDT module.
*/
__STATIC_INLINE void WDT_Close(void)
{
WDT->CTL = 0UL;
return;
}
/**
* @brief Enable WDT Time-out Interrupt
*
* @param None
*
* @return None
*
* @details This function will enable the WDT time-out interrupt function.
*/
__STATIC_INLINE void WDT_EnableInt(void)
{
WDT->CTL |= WDT_CTL_INTEN_Msk;
return;
}
/**
* @brief Disable WDT Time-out Interrupt
*
* @param None
*
* @return None
*
* @details This function will disable the WDT time-out interrupt function.
*/
__STATIC_INLINE void WDT_DisableInt(void)
{
/* Do not touch another write 1 clear bits */
WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
return;
}
void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group WDT_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __WDT_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file wwdt.h
* @version V0.10
* @brief M251 series WWDT driver header file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_H__
#define __WWDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* WWDT Prescale Period Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
/*---------------------------------------------------------------------------------------------------------*/
/* WWDT Reload Counter Keyword Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter */
/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
@{
*/
/**
* @brief Clear WWDT Reset System Flag
*
* @param None
*
* @return None
*
* @details This macro is used to clear WWDT time-out reset system flag.
*
* \hideinitializer
*/
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
/**
* @brief Clear WWDT Compared Match Interrupt Flag
*
* @param None
*
* @return None
*
* @details This macro is used to clear WWDT compared match interrupt flag.
*
* \hideinitializer
*/
#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
/**
* @brief Get WWDT Reset System Flag
*
* @param None
*
* @retval 0 WWDT time-out reset system did not occur
* @retval 1 WWDT time-out reset system occurred
*
* @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
*
* \hideinitializer
*/
#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
/**
* @brief Get WWDT Compared Match Interrupt Flag
*
* @param None
*
* @retval 0 WWDT compare match interrupt did not occur
* @retval 1 WWDT compare match interrupt occurred
*
* @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
*
* \hideinitializer
*/
#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
/**
* @brief Get WWDT Counter
*
* @param None
*
* @return WWDT Counter Value
*
* @details This macro reflects the current WWDT counter value.
*
* \hideinitializer
*/
#define WWDT_GET_COUNTER() (WWDT->CNT)
/**
* @brief Reload WWDT Counter
*
* @param None
*
* @return None
*
* @details This macro is used to reload the WWDT counter value to 0x3F.
* @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
* between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
* WWDT reset signal will generate immediately to reset system.
*
* \hideinitializer
*/
#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group WWDT_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __WWDT_H__ */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file acmp.c
* @version V1.00
* @brief M251 series Analog Comparator(ACMP) driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief Configure the specified ACMP module
*
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum Comparator number.
* @param[in] u32NegSrc Comparator negative input selection. Including:
* - \ref ACMP_CTL_NEGSEL_PIN
* - \ref ACMP_CTL_NEGSEL_CRV
* - \ref ACMP_CTL_NEGSEL_VBG
* - \ref ACMP_CTL_NEGSEL_DAC
* @param[in] u32HysSel The hysteresis function option. Including:
* - \ref ACMP_CTL_HYSTERESIS_30MV
* - \ref ACMP_CTL_HYSTERESIS_20MV
* - \ref ACMP_CTL_HYSTERESIS_10MV
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
*
* @return None
*
* @details Configure hysteresis function, select the source of negative input and enable analog comparator.
*/
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)
{
acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);
}
/**
* @brief Close analog comparator
*
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum Comparator number.
*
* @return None
*
* @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
*/
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
{
acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
}
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group ACMP_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file bpwm.c
* @version V0.10
* @brief M251 series BPWM driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup BPWM_Driver BPWM Driver
@{
*/
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
@{
*/
/**
* @brief Configure BPWM capture and get the nearest unit time.
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32UnitTimeNsec The unit time of counter
* @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
* @return The nearest unit time in nano second.
* @details This function is used to Configure BPWM capture and get the nearest unit time.
*/
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
{
uint32_t u32Src;
uint32_t u32BPWMClockSrc;
uint32_t u32NearestUnitTimeNsec;
uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL;
uint8_t u8BreakLoop = 0UL;
if (bpwm == BPWM0)
{
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
}
else /* (bpwm == BPWM1) */
{
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
}
if (u32Src == 0UL)
{
//clock source is from PLL clock
u32BPWMClockSrc = CLK_GetPLLClockFreq();
}
else
{
//clock source is from PCLK
SystemCoreClockUpdate();
if (bpwm == BPWM0)
{
u32BPWMClockSrc = CLK_GetPCLK0Freq();
}
else /* (bpwm == BPWM1) */
{
u32BPWMClockSrc = CLK_GetPCLK1Freq();
}
}
u32BPWMClockSrc /= 1000UL;
for (u16Prescale = 1UL; u16Prescale <= 0x1000UL; u16Prescale++)
{
u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32BPWMClockSrc;
if (u32NearestUnitTimeNsec < u32UnitTimeNsec)
{
if (u16Prescale == 0x1000UL)
{
/* limit to the maximum unit time(nano second) */
u8BreakLoop = 1UL;
}
if (!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32BPWMClockSrc))))
{
u8BreakLoop = 1UL;
}
}
else
{
u8BreakLoop = 1UL;
}
if (u8BreakLoop)
{
break;
}
}
// convert to real register value
u16Prescale = u16Prescale - 1UL;
// all channels share a prescaler
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale);
// set BPWM to down count type(edge aligned)
(bpwm)->CTL1 = BPWM_DOWN_COUNTER;
BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
return (u32NearestUnitTimeNsec);
}
/**
* @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(down countertype) auto-reload mode
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @return Nearest frequency clock in nano second
* @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect
* existing frequency of other channel.
*/
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
{
uint32_t u32Src;
uint32_t u32BPWMClockSrc;
uint32_t i;
uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL;
if (bpwm == BPWM0)
{
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
}
else /* (bpwm == BPWM1) */
{
u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
}
if (u32Src == 0UL)
{
//clock source is from PLL clock
u32BPWMClockSrc = CLK_GetPLLClockFreq();
}
else
{
//clock source is from PCLK
SystemCoreClockUpdate();
if (bpwm == BPWM0)
{
u32BPWMClockSrc = CLK_GetPCLK0Freq();
}
else /* (bpwm == BPWM1) */
{
u32BPWMClockSrc = CLK_GetPCLK1Freq();
}
}
for (u16Prescale = 1UL; u16Prescale < 0xFFFUL; u16Prescale++) //prescale could be 0~0xFFF
{
i = (u32BPWMClockSrc / u32Frequency) / u16Prescale;
// If target value is larger than CNR, need to use a larger prescaler
if (i <= (0x10000UL))
{
u16CNR = (uint16_t)i;
break;
}
}
// Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
i = u32BPWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR);
// convert to real register value
u16Prescale = u16Prescale - 1UL;
// all channels share a prescaler
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale);
// set BPWM to down count type
(bpwm)->CTL1 = BPWM_DOWN_COUNTER;
u16CNR = u16CNR - 1UL;
BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
if (u32DutyCycle)
{
if (u32DutyCycle >= 100UL)
BPWM_SET_CMR(bpwm, u32ChannelNum, u16CNR);
else
BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL);
(bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
(bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + BPWM_WGCTL0_PRDPCTL0_Pos));
(bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL));
(bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + BPWM_WGCTL1_CMPDCTL0_Pos));
}
else
{
BPWM_SET_CMR(bpwm, u32ChannelNum, 0UL);
(bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
(bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + BPWM_WGCTL0_ZPCTL0_Pos));
(bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL));
(bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + BPWM_WGCTL1_CMPDCTL0_Pos));
}
return (i);
}
/**
* @brief Start BPWM module
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This function is used to start BPWM module.
* @note All channels share one counter.
*/
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
}
/**
* @brief Stop BPWM module
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This function is used to stop BPWM module.
* @note All channels share one period.
*/
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->PERIOD = 0UL;
}
/**
* @brief Stop BPWM generation immediately by clear channel enable bit
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
* @return None
* @details This function is used to stop BPWM generation immediately by clear channel enable bit.
* @note All channels share one counter.
*/
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
}
/**
* @brief Enable selected channel to trigger ADC
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
* - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT
* - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT
* - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
* - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT
* - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT
* - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT
* - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT
* @return None
* @details This function is used to enable selected channel to trigger ADC
*/
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
{
if (u32ChannelNum < 4UL)
{
(bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3UL));
(bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3UL));
}
else
{
(bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3UL));
(bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3UL));
}
}
/**
* @brief Disable selected channel to trigger ADC
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* @details This function is used to disable selected channel to trigger ADC
*/
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
if (u32ChannelNum < 4UL)
{
(bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3UL));
}
else
{
(bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3UL));
}
}
/**
* @brief Clear selected channel trigger ADC flag
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32Condition This parameter is not used
* @return None
* @details This function is used to clear selected channel trigger ADC flag
*/
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
{
(bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);
}
/**
* @brief Get selected channel trigger ADC flag
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @retval 0 The specified channel trigger ADC to start of conversion flag is not set
* @retval 1 The specified channel trigger ADC to start of conversion flag is set
* @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel
*/
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);
}
/**
* @brief Enable capture of selected channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
* Bit 0 is channel 0, bit 1 is channel 1...
* @return None
* @details This function is used to enable capture of selected channel(s)
*/
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->CAPINEN |= u32ChannelMask;
(bpwm)->CAPCTL |= u32ChannelMask;
}
/**
* @brief Disable capture of selected channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
* Bit 0 is channel 0, bit 1 is channel 1...
* @return None
* @details This function is used to disable capture of selected channel(s)
*/
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->CAPINEN &= ~u32ChannelMask;
(bpwm)->CAPCTL &= ~u32ChannelMask;
}
/**
* @brief Enables BPWM output generation of selected channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
* @return None
* @details This function is used to enables BPWM output generation of selected channel(s)
*/
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->POEN |= u32ChannelMask;
}
/**
* @brief Disables BPWM output generation of selected channel(s)
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
* @return None
* @details This function is used to disables BPWM output generation of selected channel(s)
*/
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
{
(bpwm)->POEN &= ~u32ChannelMask;
}
/**
* @brief Enable capture interrupt of selected channel.
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32Edge Rising or falling edge to latch counter.
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
* @return None
* @details This function is used to enable capture interrupt of selected channel.
*/
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
{
(bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
}
/**
* @brief Disable capture interrupt of selected channel.
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32Edge Rising or falling edge to latch counter.
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
* @return None
* @details This function is used to disable capture interrupt of selected channel.
*/
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
{
(bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
}
/**
* @brief Clear capture interrupt of selected channel.
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32Edge Rising or falling edge to latch counter.
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
* @return None
* @details This function is used to clear capture interrupt of selected channel.
*/
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
{
(bpwm)->CAPIF = (u32Edge << u32ChannelNum);
}
/**
* @brief Get capture interrupt of selected channel.
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @retval 0 No capture interrupt
* @retval 1 Rising edge latch interrupt
* @retval 2 Falling edge latch interrupt
* @retval 3 Rising and falling latch interrupt
* @details This function is used to get capture interrupt of selected channel.
*/
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1UL) | \
(((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL));
}
/**
* @brief Enable duty interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32IntDutyType Duty interrupt type, could be either
* - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
* - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
* @return None
* @details This function is used to enable duty interrupt of selected channel.
*/
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
{
(bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
}
/**
* @brief Disable duty interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* @details This function is used to disable duty interrupt of selected channel
*/
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
}
/**
* @brief Clear duty interrupt flag of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return None
* @details This function is used to clear duty interrupt flag of selected channel
*/
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum;
}
/**
* @brief Get duty interrupt flag of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @return Duty interrupt flag of specified channel
* @retval 0 Duty interrupt did not occur
* @retval 1 Duty interrupt occurred
* @details This function is used to get duty interrupt flag of selected channel
*/
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
}
/**
* @brief Enable period interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
* @return None
* @details This function is used to enable period interrupt of selected channel.
* @note All channels share channel 0's setting.
*/
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
{
(bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
}
/**
* @brief Disable period interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* @details This function is used to disable period interrupt of selected channel.
* @note All channels share channel 0's setting.
*/
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
}
/**
* @brief Clear period interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* @details This function is used to clear period interrupt of selected channel
* @note All channels share channel 0's setting.
*/
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
}
/**
* @brief Get period interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return Period interrupt flag of specified channel
* @retval 0 Period interrupt did not occur
* @retval 1 Period interrupt occurred
* @details This function is used to get period interrupt of selected channel
* @note All channels share channel 0's setting.
*/
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);
}
/**
* @brief Enable zero interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* @details This function is used to enable zero interrupt of selected channel.
* @note All channels share channel 0's setting.
*/
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
}
/**
* @brief Disable zero interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* @details This function is used to disable zero interrupt of selected channel.
* @note All channels share channel 0's setting.
*/
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
}
/**
* @brief Clear zero interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* @details This function is used to clear zero interrupt of selected channel.
* @note All channels share channel 0's setting.
*/
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
}
/**
* @brief Get zero interrupt of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return zero interrupt flag of specified channel
* @retval 0 zero interrupt did not occur
* @retval 1 zero interrupt occurred
* @details This function is used to get zero interrupt of selected channel.
* @note All channels share channel 0's setting.
*/
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);
}
/**
* @brief Enable load mode of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32LoadMode BPWM counter loading mode.
* - \ref BPWM_LOAD_MODE_IMMEDIATE
* - \ref BPWM_LOAD_MODE_CENTER
* @return None
* @details This function is used to enable load mode of selected channel.
*/
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
{
(bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
}
/**
* @brief Disable load mode of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
* @param[in] u32LoadMode BPWM counter loading mode.
* - \ref BPWM_LOAD_MODE_IMMEDIATE
* - \ref BPWM_LOAD_MODE_CENTER
* @return None
* @details This function is used to disable load mode of selected channel.
*/
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
{
(bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
}
/**
* @brief Set BPWM clock source
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @param[in] u32ClkSrcSel BPWM external clock source.
* - \ref BPWM_CLKSRC_BPWM_CLK
* - \ref BPWM_CLKSRC_TIMER0
* - \ref BPWM_CLKSRC_TIMER1
* - \ref BPWM_CLKSRC_TIMER2
* - \ref BPWM_CLKSRC_TIMER3
* @return None
* @details This function is used to set BPWM clock source.
* @note All channels share channel 0's setting.
*/
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
{
(bpwm)->CLKSRC = (u32ClkSrcSel);
}
/**
* @brief Get the time-base counter reached its maximum value flag of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return Count to max interrupt flag of specified channel
* @retval 0 Count to max interrupt did not occur
* @retval 1 Count to max interrupt occurred
* @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
* @note All channels share channel 0's setting.
*/
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);
}
/**
* @brief Clear the time-base counter reached its maximum value flag of selected channel
* @param[in] bpwm The pointer of the specified BPWM module
* - BPWM0 : BPWM Group 0
* - BPWM1 : BPWM Group 1
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
* @return None
* @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
* @note All channels share channel 0's setting.
*/
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
{
(bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
}
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group BPWM_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/src/crc.c Normal file
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/**************************************************************************//**
* @file crc.c
* @version V0.10
* @brief M251 CRC driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRC_Driver CRC Driver
@{
*/
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
@{
*/
/**
* @brief CRC Open
*
* @param[in] u32Mode CRC operation polynomial mode. Valid values are:
* - \ref CRC_CCITT
* - \ref CRC_8
* - \ref CRC_16
* - \ref CRC_32
* @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
* - \ref CRC_CHECKSUM_COM
* - \ref CRC_CHECKSUM_RVS
* - \ref CRC_WDATA_COM
* - \ref CRC_WDATA_RVS
* @param[in] u32Seed Seed value.
* @param[in] u32DataLen CPU Write Data Length. Valid values are:
* - \ref CRC_CPU_WDATA_8
* - \ref CRC_CPU_WDATA_16
* - \ref CRC_CPU_WDATA_32
*
* @return None
*
* @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
* After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
*/
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
{
CRC->SEED = u32Seed;
CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
/* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */
CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
}
/**
* @brief Get CRC Checksum
*
* @param[in] None
*
* @return Checksum Result
*
* @details This function gets the CRC checksum result by current CRC polynomial mode.
*/
uint32_t CRC_GetChecksum(void)
{
uint32_t ret;
switch (CRC->CTL & CRC_CTL_CRCMODE_Msk)
{
case CRC_CCITT:
case CRC_16:
ret = (CRC->CHECKSUM & 0xFFFFU);
break;
case CRC_32:
ret = (CRC->CHECKSUM);
break;
case CRC_8:
ret = (CRC->CHECKSUM & 0xFFU);
break;
default:
ret = 0U;
break;
}
return ret;
}
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CRC_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file crypto.c
* @version V1.10
* @brief Cryptographic Accelerator driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include <stdio.h>
#include <string.h>
#include "NuMicro.h"
#define ENABLE_DEBUG 0
#if ENABLE_DEBUG
#define CRPT_DBGMSG printf
#else
#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */
#endif
#if defined(__ICCARM__)
#pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup CRYPTO_Driver CRYPTO Driver
@{
*/
/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
@{
*/
/* // @cond HIDDEN_SYMBOLS */
static uint32_t g_AES_au32CTL[1];
/* // @endcond HIDDEN_SYMBOLS */
/**
* @brief Open PRNG function
* @param[in] crpt Reference to Crypto module.
* @param[in] u32KeySize is PRNG key size, including:
* - \ref PRNG_KEY_SIZE_64
* - \ref PRNG_KEY_SIZE_128
* - \ref PRNG_KEY_SIZE_192
* - \ref PRNG_KEY_SIZE_256
* @param[in] u32SeedReload is PRNG seed reload or not, including:
* - \ref PRNG_SEED_CONT
* - \ref PRNG_SEED_RELOAD
* @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.
* @return None
*/
void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)
{
if (u32SeedReload)
{
crpt->PRNG_SEED = u32Seed;
}
crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
(u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
}
/**
* @brief Start to generate one PRNG key.
* @param[in] crpt Reference to Crypto module.
* @return None
*/
void PRNG_Start(CRPT_T *crpt)
{
crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;
}
/**
* @brief Read the PRNG key.
* @param[in] crpt Reference to Crypto module.
* @param[out] au32RandKey The key buffer to store newly generated PRNG key.
* @return None
*/
void PRNG_Read(CRPT_T *crpt, uint32_t au32RandKey[])
{
uint32_t u32Idx, u32Wcnt;
u32Wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U;
for (u32Idx = 0U; u32Idx < u32Wcnt; u32Idx++)
{
au32RandKey[u32Idx] = crpt->PRNG_KEY[u32Idx];
}
crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk;
}
/**
* @brief Open AES encrypt/decrypt function.
* @param[in] crpt Reference to Crypto module.
* @param[in] u32Channel AES channel. Must be 0.
* @param[in] u32EncDec 1: AES encode; 0: AES decode
* @param[in] u32OpMode AES operation mode, including:
* - \ref AES_MODE_ECB
* - \ref AES_MODE_CBC
* - \ref AES_MODE_CFB
* - \ref AES_MODE_OFB
* - \ref AES_MODE_CTR
* - \ref AES_MODE_CBC_CS1
* - \ref AES_MODE_CBC_CS2
* - \ref AES_MODE_CBC_CS3
* @param[in] u32KeySize is AES key size, including:
* - \ref AES_KEY_SIZE_128
* - \ref AES_KEY_SIZE_192
* - \ref AES_KEY_SIZE_256
* @param[in] u32SwapType is AES input/output data swap control, including:
* - \ref AES_NO_SWAP
* - \ref AES_OUT_SWAP
* - \ref AES_IN_SWAP
* - \ref AES_IN_OUT_SWAP
* @return None
*/
void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec,
uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)
{
crpt->AES_CTL = (u32EncDec << CRPT_AES_CTL_ENCRYPTO_Pos) |
(u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |
(u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |
(u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);
g_AES_au32CTL[u32Channel] = crpt->AES_CTL;
}
/**
* @brief Start AES encrypt/decrypt
* @param[in] crpt Reference to Crypto module.
* @param[in] u32Channel AES channel. Must be 0.
* @param[in] u32DMAMode AES DMA control, including:
* - \ref CRYPTO_DMA_FIRST Do first encrypt/decrypt in DMA cascade.
* - \ref CRYPTO_DMA_ONE_SHOT Do one shot encrypt/decrypt with DMA.
* - \ref CRYPTO_DMA_CONTINUE Do continuous encrypt/decrypt in DMA cascade.
* - \ref CRYPTO_DMA_LAST Do last encrypt/decrypt in DMA cascade.
* @return None
*/
void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode)
{
crpt->AES_CTL = g_AES_au32CTL[u32Channel];
crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);
}
/**
* @brief Set AES keys
* @param[in] crpt Reference to Crypto module.
* @param[in] u32Channel AES channel. Must be 0.
* @param[in] au32Keys An word array contains AES keys.
* @param[in] u32KeySize is AES key size, including:
* - \ref AES_KEY_SIZE_128
* - \ref AES_KEY_SIZE_192
* - \ref AES_KEY_SIZE_256
* @return None
*/
void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
{
uint32_t u32Idx, u32Wcnt, u32KeyRegAddr;
u32KeyRegAddr = (uint32_t)&crpt->AES_KEY[0] + (u32Channel * 0x3CUL);
u32Wcnt = 4UL + u32KeySize * 2UL;
for (u32Idx = 0U; u32Idx < u32Wcnt; u32Idx++)
{
outpw(u32KeyRegAddr, au32Keys[u32Idx]);
u32KeyRegAddr += 4UL;
}
}
/**
* @brief Set AES initial vectors
* @param[in] crpt Reference to Crypto module.
* @param[in] u32Channel AES channel. Must be 0.
* @param[in] au32IV A four entry word array contains AES initial vectors.
* @return None
*/
void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[])
{
uint32_t u32Idx, u32KeyRegAddr;
u32KeyRegAddr = (uint32_t)&crpt->AES_IV[0] + (u32Channel * 0x3CUL);
for (u32Idx = 0U; u32Idx < 4U; u32Idx++)
{
outpw(u32KeyRegAddr, au32IV[u32Idx]);
u32KeyRegAddr += 4UL;
}
}
/**
* @brief Set AES DMA transfer configuration.
* @param[in] crpt Reference to Crypto module.
* @param[in] u32Channel AES channel. Must be 0.
* @param[in] u32SrcAddr AES DMA source address
* @param[in] u32DstAddr AES DMA destination address
* @param[in] u32TransCnt AES DMA transfer byte count
* @return None
*/
void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr,
uint32_t u32DstAddr, uint32_t u32TransCnt)
{
uint32_t u32RegAddr;
u32RegAddr = (uint32_t)&crpt->AES_SADDR + (u32Channel * 0x3CUL);
outpw(u32RegAddr, u32SrcAddr);
u32RegAddr = (uint32_t)&crpt->AES_DADDR + (u32Channel * 0x3CUL);
outpw(u32RegAddr, u32DstAddr);
u32RegAddr = (uint32_t)&crpt->AES_CNT + (u32Channel * 0x3CUL);
outpw(u32RegAddr, u32TransCnt);
}
/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CRYPTO_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file dac.c
* @version V0.10
* @brief M251 series DAC driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup DAC_Driver DAC Driver
@{
*/
/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
@{
*/
/**
* @brief This function make DAC module be ready to convert.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @param[in] u32TrgSrc Decides the trigger source. Valid values are:
* - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger
* - \ref DAC_SOFTWARE_TRIGGER :Software trigger
* - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger
* - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger
* - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger
* - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger
* - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger
* - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger
* - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger
* - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger
* @return None
* @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
* When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
* When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
* external STDAC pin, or timer event.
*/
void DAC_Open(DAC_T *dac,
uint32_t u32Ch,
uint32_t u32TrgSrc)
{
dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
}
/**
* @brief Disable DAC analog power.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Ch Not used in M251 DAC.
* @return None
* @details Disable DAC analog power for saving power consumption.
*/
void DAC_Close(DAC_T *dac, uint32_t u32Ch)
{
dac->CTL &= (~DAC_CTL_DACEN_Msk);
}
/**
* @brief Set delay time for DAC to become stable.
* @param[in] dac The pointer of the specified DAC module.
* @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.
* @return Real DAC conversion settling time (micro second).
* @details For example, DAC controller clock speed is 50MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x32.
* @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
*/
uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
{
dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);
return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());
}
/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group DAC_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file eadc.c
* @version V0.10
* @brief M251 series EADC driver source file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EADC_Driver EADC Driver
@{
*/
/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
@{
*/
/**
* @brief This function make EADC_module be ready to convert.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32InputMode Decides the input mode. M251 don't support this feature.
* - \ref NULL :Always NULL.
* @return None
* @details This function is used to set analog input mode and enable A/D Converter.
* Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
* @note
*/
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
{
eadc->CTL |= EADC_CTL_ADCEN_Msk;
/* Wait for EADC start up completely and ready for conversion */
while ((eadc->PWRCTL & EADC_PWRCTL_READY_Msk) == 0);
}
/**
* @brief Disable EADC_module.
* @param[in] eadc The pointer of the specified EADC module.
* @return None
* @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
*/
void EADC_Close(EADC_T *eadc)
{
eadc->CTL &= (~EADC_CTL_ADCEN_Msk);
}
/**
* @brief Configure the sample control logic module.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
* @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
* - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
* - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
* - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
* - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
* - \ref EADC_ADINT0_TRIGGER : EADC ADINT0 interrupt EOC pulse trigger
* - \ref EADC_ADINT1_TRIGGER : EADC ADINT1 interrupt EOC pulse trigger
* - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
* - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
* - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
* - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
* - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger
* - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger
* - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger
* - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger
* - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger
* - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger
* - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger
* - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger
* - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger
* - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger
* - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger
* - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger
* - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger
* @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
* @return None
* @details Each of EADC control logic modules 0~15 which is configurable for EADC converter channel EADC_CH0~15 and trigger source.
* Sample module 16~18 is fixed for EADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
*/
void EADC_ConfigSampleModule(EADC_T *eadc, \
uint32_t u32ModuleNum, \
uint32_t u32TriggerSrc, \
uint32_t u32Channel)
{
((eadc->SCTL[u32ModuleNum])) &= (~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk));
((eadc->SCTL[u32ModuleNum])) |= (u32TriggerSrc | u32Channel);
}
/**
* @brief Set trigger delay time.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid values are from 0 to 15.
* @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~255.
* @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is EADC_CLK/1
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is EADC_CLK/2
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is EADC_CLK/4
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is EADC_CLK/16
* @return None
* @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
* Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
*/
void EADC_SetTriggerDelayTime(EADC_T *eadc, \
uint32_t u32ModuleNum, \
uint32_t u32TriggerDelayTime, \
uint32_t u32DelayClockDivider)
{
((eadc->SCTL[u32ModuleNum])) &= (~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk));
((eadc->SCTL[u32ModuleNum])) |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
}
/**
* @brief Set EADC extend sample time.
* @param[in] eadc The pointer of the specified EADC module.
* @param[in] u32ModuleNum Decides the sample module number, valid values are from 0 to 18.
* @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 EADC clock. Valid value are from 0 to 255.
* @return None
* @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough
* if the analog channel has heavy loading to cause fully charge time is longer.
* User can extend A/D sampling time after trigger source is coming to get enough sampling time.
*/
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
{
if (u32ModuleNum < 16)
{
((eadc->SCTL[u32ModuleNum])) &= (~EADC_SCTL_EXTSMPT_Msk);
((eadc->SCTL[u32ModuleNum])) |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
}
else
{
((eadc->SCTL0[u32ModuleNum - 16])) &= (~EADC_SCTL0_EXTSMPT_Msk);
((eadc->SCTL0[u32ModuleNum - 16])) |= (u32ExtendSampleTime << EADC_SCTL0_EXTSMPT_Pos);
}
}
/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EADC_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file ebi.c
* @version V0.10
* @brief M251 series EBI driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup EBI_Driver EBI Driver
@{
*/
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
@{
*/
/**
* @brief Initialize EBI for specify Bank
*
* @param[in] u32Bank Bank number for EBI. Valid values are:
* - \ref EBI_BANK0
* - \ref EBI_BANK1
* - \ref EBI_BANK2
* @param[in] u32DataWidth Data bus width. Valid values are:
* - \ref EBI_BUSWIDTH_8BIT
* - \ref EBI_BUSWIDTH_16BIT
* @param[in] u32TimingClass Default timing configuration. Valid values are:
* - \ref EBI_TIMING_FASTEST
* - \ref EBI_TIMING_VERYFAST
* - \ref EBI_TIMING_FAST
* - \ref EBI_TIMING_NORMAL
* - \ref EBI_TIMING_SLOW
* - \ref EBI_TIMING_VERYSLOW
* - \ref EBI_TIMING_SLOWEST
* @param[in] u32BusMode Set EBI bus operate mode. Valid values are:
* - \ref EBI_OPMODE_NORMAL
* - \ref EBI_OPMODE_CACCESS
* @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
* - \ref EBI_CS_ACTIVE_HIGH
* - \ref EBI_CS_ACTIVE_LOW
*
* @return None
*
* @details This function is used to open specify EBI bank with different bus width, timing setting and \n
* active level of CS pin to access EBI device.
* @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
*/
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
{
uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0);
volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1);
if (u32DataWidth == EBI_BUSWIDTH_8BIT)
{
*pu32EBICTL &= ~EBI_CTL_DW16_Msk;
}
else
{
*pu32EBICTL |= EBI_CTL_DW16_Msk;
}
*pu32EBICTL |= u32BusMode;
switch (u32TimingClass)
{
case EBI_TIMING_FASTEST:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
*pu32EBITCTL = 0x0U;
break;
case EBI_TIMING_VERYFAST:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
(0x3U << EBI_CTL_TALE_Pos) ;
*pu32EBITCTL = 0x03003318U;
break;
case EBI_TIMING_FAST:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
*pu32EBITCTL = 0x0U;
break;
case EBI_TIMING_NORMAL:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
(0x3U << EBI_CTL_TALE_Pos) ;
*pu32EBITCTL = 0x03003318U;
break;
case EBI_TIMING_SLOW:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
(0x7U << EBI_CTL_TALE_Pos) ;
*pu32EBITCTL = 0x07007738U;
break;
case EBI_TIMING_VERYSLOW:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
(0x7U << EBI_CTL_TALE_Pos) ;
*pu32EBITCTL = 0x07007738U;
break;
case EBI_TIMING_SLOWEST:
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
(EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
(0x7U << EBI_CTL_TALE_Pos) ;
*pu32EBITCTL = 0x07007738U;
break;
default:
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
break;
}
}
/**
* @brief Disable EBI on specify Bank
*
* @param[in] u32Bank Bank number for EBI. Valid values are:
* - \ref EBI_BANK0
* - \ref EBI_BANK1
* - \ref EBI_BANK2
*
* @return None
*
* @details This function is used to close specify EBI function.
*/
void EBI_Close(uint32_t u32Bank)
{
uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U;
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index);
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
}
/**
* @brief Set EBI Bus Timing for specify Bank
*
* @param[in] u32Bank Bank number for EBI. Valid values are:
* - \ref EBI_BANK0
* - \ref EBI_BANK1
* - \ref EBI_BANK2
* @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
* @param[in] u32MclkDiv Divider for MCLK. Valid values are:
* - \ref EBI_MCLKDIV_1
* - \ref EBI_MCLKDIV_2
* - \ref EBI_MCLKDIV_4
* - \ref EBI_MCLKDIV_8
* - \ref EBI_MCLKDIV_16
* - \ref EBI_MCLKDIV_32
* - \ref EBI_MCLKDIV_64
* - \ref EBI_MCLKDIV_128
*
* @return None
*
* @details This function is used to configure specify EBI bus timing for access EBI device.
*/
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
{
uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0);
volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1);
*pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
*pu32EBITCTL = u32TimingConfig;
}
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group EBI_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file fmc.c
* @version V3.00
* @brief M251 Series Flash Memory Controller(FMC) driver source file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include <stdio.h>
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup FMC_Driver FMC Driver
@{
*/
/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
@{
*/
/**
* @brief Set boot source from LDROM or APROM after next software reset
*
* @param[in] i32BootSrc
* 1: Boot from LDROM
* 0: Boot from APROM
*
* @return None
*
* @details This function is used to switch APROM boot or LDROM boot. User need to call
* FMC_SetBootSource to select boot source first, then use CPU reset or
* System Reset Request to reset system.
*
*/
void FMC_SetBootSource(int32_t i32BootSrc)
{
if (i32BootSrc)
{
FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
}
else
{
FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
}
}
/**
* @brief Disable ISP Functions
*
* @param None
*
* @return None
*
* @details This function will clear ISPEN bit of ISPCON to disable ISP function
*
*/
void FMC_Close(void)
{
FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
}
/**
* @brief Get the current boot source
*
* @param None
*
* @retval 0 This chip is currently booting from APROM
* @retval 1 This chip is currently booting from LDROM
*
* @note This function only show the boot source.
* User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
*/
int32_t FMC_GetBootSource(void)
{
int32_t ret = 0;
if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
{
ret = 1;
}
return ret;
}
/**
* @brief Enable FMC ISP function
*
* @param None
*
* @return None
*
* @details ISPEN bit of ISPCON must be set before we can use ISP commands.
* Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.
*
* @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.
*
*/
void FMC_Open(void)
{
FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
}
/**
* @brief Read the User Configuration words.
*
* @param[out] u32Config The word buffer to store the User Configuration data.
* @param[in] u32Count The word count to be read.
*
* @retval 0 Success
* @retval -1 Failed
*
* @details This function is used to read the settings of user configuration.
* if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.
* if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.
*/
int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)
{
uint32_t i;
for (i = 0u; i < u32Count; i++)
{
u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4u);
}
return 0;
}
/**
* @brief Write User Configuration
*
* @param[in] u32Config The word buffer to store the User Configuration data.
* @param[in] u32Count The word count to program to User Configuration.
*
* @retval 0 Success
* @retval -1 Failed
*
* @details User must enable User Configuration update before writing it.
* User must erase User Configuration before writing it.
* User Configuration is also be page erase. User needs to backup necessary data
* before erase User Configuration.
*/
int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
{
int32_t ret = 0;
uint32_t i;
for (i = 0u; i < u32Count; i++)
{
FMC_Write(FMC_CONFIG_BASE + i * 4u, u32Config[i]);
if (FMC_Read(FMC_CONFIG_BASE + i * 4u) != u32Config[i])
{
ret = 1;
}
}
return ret;
}
/**
* @brief Run CRC32 checksum calculation and get result.
*
* @param[in] u32addr Starting flash address. It must be a page aligned address.
* @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
*
* @return Success or not.
* @retval 0 Success.
* @retval 0xFFFFFFFF Invalid parameter.
*
* details Run ISP checksum command to calculate specify area
*/
uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
{
uint32_t ret;
if ((u32addr % 512UL) || (u32count % 512UL))
{
ret = 0xFFFFFFFF;
}
else
{
FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
FMC->ISPADDR = u32addr;
FMC->ISPDAT = u32count;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
FMC->ISPADDR = u32addr;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
ret = FMC->ISPDAT;
}
return ret;
}
/**
* @brief Run flash all one verification and get result.
*
* @param[in] u32addr Starting flash address. It must be a page aligned address.
* @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
*
* @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF.
* @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF.
* @retval READ_ALLONE_CMD_FAIL Unexpected error occurred.
*
* @details Run ISP check all one command to check specify area is all one or not.
*/
uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
{
uint32_t ret = READ_ALLONE_CMD_FAIL;
FMC->ISPSTS = 0x80UL; /* clear check all one bit */
FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1;
FMC->ISPADDR = u32addr;
FMC->ISPDAT = u32count;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
do
{
FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;
FMC->ISPADDR = u32addr;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
}
while (FMC->ISPDAT == 0UL);
if (FMC->ISPDAT == READ_ALLONE_YES)
{
ret = FMC->ISPDAT;
}
if (FMC->ISPDAT == READ_ALLONE_NOT)
{
ret = FMC->ISPDAT;
}
return ret;
}
/**
* @brief Check the XOM is actived or not.
*
* @param[in] xom_num The XOM number. The value will always be 0 in M251 series.
*
* @retval 1 XOM is actived.
* @retval 0 XOM is not actived.
* @retval -2 Invalid XOM number.
*
* @details To get specify XOM active status
*/
int32_t FMC_Is_XOM_Actived(uint32_t xom_num)
{
uint32_t u32act;
int32_t ret = 0;
if (xom_num >= 1UL)
{
ret = -2;
}
if (ret >= 0)
{
u32act = (((FMC->XOMSTS) & 0xful) & (1ul << xom_num)) >> xom_num;
ret = (int32_t)u32act;
}
return ret;
}
/**
* @brief Config XOM Region
* @param[in] xom_num The XOM number. The value will always be 0 in M251 series.
* @param[in] xom_base The XOM region base address.
* @param[in] xom_page The XOM page number of region size.
*
* @retval 0 Success
* @retval 1 XOM is has already actived.
* @retval -1 Program failed.
* @retval -2 Invalid XOM number.
*
* @details Program XOM base address and XOM size(page)
*/
int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page)
{
int32_t ret = 0;
if (xom_num >= 1UL)
{
ret = -2;
}
if (ret == 0)
{
ret = FMC_Is_XOM_Actived(xom_num);
}
if (ret == 0)
{
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u);
FMC->ISPDAT = xom_base;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
{
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
ret = -1;
}
}
if (ret == 0)
{
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u + 0x04u);
FMC->ISPDAT = xom_page;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
{
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
ret = -1;
}
}
if (ret == 0)
{
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u + 0x08u);
FMC->ISPDAT = 0u;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
{
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
ret = -1;
}
}
return ret;
}
/**
* @brief Execute Erase XOM Region
*
* @param[in] xom_num The XOM number. The value will always be 0 in M251 series.
*
* @return XOM erase success or not.
* @retval 0 Success
* @retval -1 Erase failed
* @retval -2 Invalid XOM number.
*
* @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM.
*/
int32_t FMC_Erase_XOM(uint32_t xom_num)
{
uint32_t u32Addr;
int32_t i32Active, err = 0;
if (xom_num >= 1UL)
{
err = -2;
}
i32Active = FMC_Is_XOM_Actived(xom_num);
if (i32Active)
{
u32Addr = FMC->XOMR0STS0;
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
FMC->ISPADDR = u32Addr;
FMC->ISPDAT = 0x55aa03u;
FMC->ISPTRG = 0x1u;
#if ISBEN
__ISB();
#endif
while (FMC->ISPTRG) {}
/* Check ISPFF flag to know whether erase OK or fail. */
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
{
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
err = -1;
}
}
else
{
err = -1;
}
return err;
}
/**
* @brief Flash page erase
*
* @param[in] u32Addr Flash address including APROM, LDROM, Data Flash, and CONFIG
*
* @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
* The page size is 512 bytes.
*
* @retval 0 Success
* @retval -1 Erase failed
*
*/
int32_t FMC_Erase(uint32_t u32Addr)
{
int32_t ret = 0;
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
FMC->ISPADDR = u32Addr;
FMC->ISPTRG = 0x1u;
#if ISBEN
__ISB();
#endif
while (FMC->ISPTRG) {}
/* Check ISPFF flag to know whether erase OK or fail. */
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
{
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
ret = -1;
}
return ret;
}
/**
* @brief Read 32-bit Data from specified address of flash
*
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
*
* @return The data of specified address
*
* @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
*
*/
uint32_t FMC_Read(uint32_t u32Addr)
{
FMC->ISPCMD = FMC_ISPCMD_READ;
FMC->ISPADDR = u32Addr;
FMC->ISPDAT = 0u;
FMC->ISPTRG = 0x1u;
#if ISBEN
__ISB();
#endif
while (FMC->ISPTRG) {}
return FMC->ISPDAT;
}
/**
* @brief Program 32-bit data into specified address of flash
*
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
* @param[in] u32Data 32-bit Data to program
*
* @return None
*
* @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
* The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
*
*/
void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
{
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = u32Addr;
FMC->ISPDAT = u32Data;
FMC->ISPTRG = 0x1u;
#if ISBEN
__ISB();
#endif
while (FMC->ISPTRG) {}
}
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group FMC_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file gpio.c
* @version V0.10
* @brief M251 GPIO driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
@{
*/
/**
* @brief Set GPIO operation mode
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
* @param[in] u32Mode Operation mode. It could be \n
* GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
*
* @return None
*
* @details This function is used to set specified GPIO operation mode.
*/
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{
uint32_t i;
for (i = 0ul; i < GPIO_PIN_MAX; i++)
{
if (u32PinMask & (1ul << i))
{
port->MODE = (port->MODE & ~(0x3ul << (i << 1ul))) | (u32Mode << (i << 1ul));
}
}
}
/**
* @brief Enable GPIO interrupt
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32Pin The pin of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
{
port->INTTYPE |= (((u32IntAttribs >> 24UL) & 0xFFUL) << u32Pin);
port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
}
/**
* @brief Disable GPIO interrupt
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32Pin The pin of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
{
/* Configure interrupt mode of specified pin */
port->INTTYPE &= ~(1UL << u32Pin);
/* Disable interrupt function of specified pin */
port->INTEN &= ~((0x00010001UL) << u32Pin);
}
/**
* @brief Set GPIO slew rate control
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
* @param[in] u32Mode Slew rate mode. It could be
* - \ref GPIO_SLEWCTL_NORMAL (minimum 16 MHz at 2.7V)
* - \ref GPIO_SLEWCTL_HIGH (minimum 25 MHz at 2.7V)
*
* @return None
*
* @details This function is used to set specified GPIO operation mode.
*/
void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{
uint32_t i;
for (i = 0ul; i < GPIO_PIN_MAX; i++)
{
if (u32PinMask & (1ul << i))
{
port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1ul))) | (u32Mode << (i << 1ul));
}
}
}
/**
* @brief Set GPIO Pull-up and Pull-down control
*
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, or PF.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
* It could be BIT0 ~ BIT15 for PA, PB, and PE.
* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC.
* It could be BIT0 ~ BIT13, and BIT15 for PD.
* It could be BIT0 ~ BIT7 for PF.
* @param[in] u32Mode The pin mode of specified GPIO pin. It could be
* - \ref GPIO_PUSEL_DISABLE
* - \ref GPIO_PUSEL_PULL_UP
* - \ref GPIO_PUSEL_PULL_DOWN
*
* @return None
*
* @details Set the pin mode of specified GPIO pin.
*/
void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{
uint32_t i;
for (i = 0ul; i < GPIO_PIN_MAX; i++)
{
if (u32PinMask & (1ul << i))
{
port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1ul))) | (u32Mode << (i << 1ul));
}
}
}
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group GPIO_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file pdma.c
* @version V1.00
* @brief M251 series PDMA driver source file
*
* @note
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "M251.h"
static uint8_t u8ChSelect[PDMA_CH_MAX];
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup PDMA_Driver PDMA Driver
@{
*/
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
@{
*/
/**
* @brief PDMA Open
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask Channel enable bits.
*
* @return None
*
* @details This function enable the PDMA channels.
*/
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
{
uint32_t i;
for (i = 0UL; i < PDMA_CH_MAX; i++)
{
if ((1 << i) & u32Mask)
{
pdma->DSCT[i].CTL = 0UL;
u8ChSelect[i] = PDMA_MEM;
}
}
pdma->CHCTL |= u32Mask;
}
/**
* @brief PDMA Close
*
* @param[in] pdma The pointer of the specified PDMA module
*
* @return None
*
* @details This function disable all PDMA channels.
*/
void PDMA_Close(PDMA_T *pdma)
{
pdma->CHCTL = 0UL;
}
/**
* @brief Set PDMA Transfer Count
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Width Data width. Valid values are
* - \ref PDMA_WIDTH_8
* - \ref PDMA_WIDTH_16
* - \ref PDMA_WIDTH_32
* @param[in] u32TransCount Transfer count
*
* @return None
*
* @details This function set the selected channel data width and transfer count.
*/
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
{
pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
}
/**
* @brief Set PDMA Stride Mode
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32DestLen Destination stride count
* @param[in] u32SrcLen Source stride count
* @param[in] u32TransCount Transfer count
*
* @return None
*
* @details This function set the selected stride mode.
*/
void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
{
pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDE_EN_Msk;
pdma->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen;
pdma->STRIDE[u32Ch].STC = u32TransCount;
}
/**
* @brief Set PDMA Transfer Address
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32SrcAddr Source address
* @param[in] u32SrcCtrl Source control attribute. Valid values are
* - \ref PDMA_SAR_INC
* - \ref PDMA_SAR_FIX
* @param[in] u32DstAddr Destination address
* @param[in] u32DstCtrl Destination control attribute. Valid values are
* - \ref PDMA_DAR_INC
* - \ref PDMA_DAR_FIX
*
* @return None
*
* @details This function set the selected channel source/destination address and attribute.
*/
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
{
pdma->DSCT[u32Ch].SA = u32SrcAddr;
pdma->DSCT[u32Ch].DA = u32DstAddr;
pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
}
/**
* @brief Set PDMA Transfer Mode
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Peripheral The selected peripheral. Valid values are
* - \ref PDMA_MEM
* - \ref PDMA_UART0_TX
* - \ref PDMA_UART0_RX
* - \ref PDMA_UART1_TX
* - \ref PDMA_UART1_RX
* - \ref PDMA_UART2_TX
* - \ref PDMA_UART2_RX
* - \ref PDMA_USCI0_TX
* - \ref PDMA_USCI0_RX
* - \ref PDMA_USCI1_TX
* - \ref PDMA_USCI1_RX
* - \ref PDMA_QSPI0_TX
* - \ref PDMA_QSPI0_RX
* - \ref PDMA_SPI0_TX
* - \ref PDMA_SPI0_RX
* - \ref PDMA_PWM0_P1_RX
* - \ref PDMA_PWM0_P2_RX
* - \ref PDMA_PWM0_P3_RX
* - \ref PDMA_PWM1_P1_RX
* - \ref PDMA_PWM1_P2_RX
* - \ref PDMA_PWM1_P3_RX
* - \ref PDMA_I2C0_TX
* - \ref PDMA_I2C0_RX
* - \ref PDMA_I2C1_TX
* - \ref PDMA_I2C1_RX
* - \ref PDMA_TMR0
* - \ref PDMA_TMR1
* - \ref PDMA_TMR2
* - \ref PDMA_TMR3
* - \ref PDMA_EADC_RX
* - \ref PDMA_DAC0_TX
* - \ref PDMA_PSIO_TX
* - \ref PDMA_PSIO_RX
* - \ref PDMA_USCI2_TX
* - \ref PDMA_USCI2_RX
* @param[in] u32ScatterEn Scatter-gather mode enable
* @param[in] u32DescAddr Scatter-gather descriptor address
*
* @return None
*
* @details This function set the selected channel transfer mode. Include peripheral setting.
*/
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
{
u8ChSelect[u32Ch] = u32Peripheral;
switch (u32Ch)
{
case 0ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
break;
case 1ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
break;
case 2ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
break;
case 3ul:
pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
break;
case 4ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
break;
case 5ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
break;
case 6ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
break;
case 7ul:
pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
break;
default:
break;
}
if (u32ScatterEn)
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
pdma->DSCT[u32Ch].NEXT = u32DescAddr - (pdma->SCATBA);
}
else
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
}
}
/**
* @brief Set PDMA Burst Type and Size
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32BurstType Burst mode or single mode. Valid values are
* - \ref PDMA_REQ_SINGLE
* - \ref PDMA_REQ_BURST
* @param[in] u32BurstSize Set the size of burst mode. Valid values are
* - \ref PDMA_BURST_128
* - \ref PDMA_BURST_64
* - \ref PDMA_BURST_32
* - \ref PDMA_BURST_16
* - \ref PDMA_BURST_8
* - \ref PDMA_BURST_4
* - \ref PDMA_BURST_2
* - \ref PDMA_BURST_1
*
* @return None
*
* @details This function set the selected channel burst type and size.
*/
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
{
pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
}
/**
* @brief Enable timeout function
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask Channel enable bits.
*
* @return None
*
* @details This function enable timeout function of the selected channel(s).
*/
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)
{
pdma->TOUTEN |= u32Mask;
}
/**
* @brief Disable timeout function
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Mask Channel enable bits.
*
* @return None
*
* @details This function disable timeout function of the selected channel(s).
*/
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
{
pdma->TOUTEN &= ~u32Mask;
}
/**
* @brief Set PDMA Timeout Count
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32OnOff Enable/disable time out function
* @param[in] u32TimeOutCnt Timeout count
*
* @return None
*
* @details This function set the timeout count.
* @note M251 only supported channel 0/1.
*/
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
{
switch (u32Ch)
{
case 0ul:
pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
break;
case 1ul:
pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
break;
default:
break;
}
if (u32OnOff)
pdma->TOUTEN |= (1 << u32Ch);
else
pdma->TOUTEN &= ~(1 << u32Ch);
}
/**
* @brief Trigger PDMA
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
*
* @return None
*
* @details This function trigger the selected channel.
*/
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
{
if (u8ChSelect[u32Ch] == PDMA_MEM)
{
pdma->SWREQ = (1ul << u32Ch);
}
else {}
}
/**
* @brief Enable Interrupt
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Mask The Interrupt Type. Valid values are
* - \ref PDMA_INT_TRANS_DONE
* - \ref PDMA_INT_TEMPTY
* - \ref PDMA_INT_TIMEOUT
*
* @return None
*
* @details This function enable the selected channel interrupt.
*/
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
{
switch (u32Mask)
{
case PDMA_INT_TRANS_DONE:
pdma->INTEN |= (1ul << u32Ch);
break;
case PDMA_INT_TEMPTY:
pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
break;
case PDMA_INT_TIMEOUT:
pdma->TOUTIEN |= (1ul << u32Ch);
break;
default:
break;
}
}
/**
* @brief Disable Interrupt
*
* @param[in] pdma The pointer of the specified PDMA module
* @param[in] u32Ch The selected channel
* @param[in] u32Mask The Interrupt Type. Valid values are
* - \ref PDMA_INT_TRANS_DONE
* - \ref PDMA_INT_TEMPTY
* - \ref PDMA_INT_TIMEOUT
*
* @return None
*
* @details This function disable the selected channel interrupt.
*/
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
{
switch (u32Mask)
{
case PDMA_INT_TRANS_DONE:
pdma->INTEN &= ~(1ul << u32Ch);
break;
case PDMA_INT_TEMPTY:
pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
break;
case PDMA_INT_TIMEOUT:
pdma->TOUTIEN &= ~(1ul << u32Ch);
break;
default:
break;
}
}
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group PDMA_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file qspi.c
* @version V0.10
* @brief M251 series QSPI driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup QSPI_Driver QSPI Driver
@{
*/
/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
@{
*/
/**
* @brief This function make QSPI module be ready to transfer.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER)
* @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3)
* @param[in] u32DataWidth Decides the data width of a QSPI transaction.
* @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
* @return Actual frequency of QSPI peripheral clock.
* @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
* slave selection function is disabled.
* In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0.
* The actual clock rate may be different from the target QSPI clock rate.
* For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the
* actual QSPI clock rate will be 6MHz.
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
* @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
* @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
* @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate.
*/
uint32_t QSPI_Open(QSPI_T *qspi,
uint32_t u32MasterSlave,
uint32_t u32QSPIMode,
uint32_t u32DataWidth,
uint32_t u32BusClock)
{
uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32RetValue = 0UL;
if (u32DataWidth == 32UL)
{
u32DataWidth = 0UL;
}
/* Get system clock frequency */
u32HCLKFreq = CLK_GetHCLKFreq();
if (u32MasterSlave == QSPI_MASTER)
{
/* Default setting: slave selection signal is active low; disable automatic slave selection function. */
qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
if (u32BusClock >= u32HCLKFreq)
{
/* Select PCLK as the clock source of QSPI */
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
}
/* Check clock source of QSPI */
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
{
/* Clock source is PCLK0 */
u32ClkSrc = CLK_GetPCLK0Freq();
}
else
{
u32ClkSrc = __HIRC; /* Clock source is HIRC */
}
if (u32BusClock >= u32HCLKFreq)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0UL;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if (u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0UL;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if (u32BusClock == 0UL)
{
/* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
}
else
{
u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
if (u32Div > 0x1FFUL)
{
u32Div = 0x1FFUL;
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
}
else
{
qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (u32Div + 1UL));
}
}
}
else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */
{
/* Default setting: slave selection signal is low level active. */
qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
/* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk;
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0UL;
/* Select PCLK as the clock source of QSPI */
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
/* Return slave peripheral clock rate */
u32RetValue = CLK_GetPCLK0Freq();
}
return u32RetValue;
}
/**
* @brief Disable QSPI controller.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None
* @details This function will reset QSPI controller.
*/
void QSPI_Close(QSPI_T *qspi)
{
/* Reset QSPI */
SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk;
SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk;
}
/**
* @brief Clear RX FIFO buffer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None
* @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1.
*/
void QSPI_ClearRxFIFO(QSPI_T *qspi)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk;
}
/**
* @brief Clear TX FIFO buffer.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None
* @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1.
* @note The TX shift register will not be cleared.
*/
void QSPI_ClearTxFIFO(QSPI_T *qspi)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk;
}
/**
* @brief Disable the automatic slave selection function.
* @param[in] qspi The pointer of the specified QSPI module.
* @return None
* @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
*/
void QSPI_DisableAutoSS(QSPI_T *qspi)
{
qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk);
}
/**
* @brief Enable the automatic slave selection function.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS)
* @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW)
* @return None
* @details This function will enable the automatic slave selection function. Only available in Master mode.
* The slave selection pin and the active level will be set in this function.
*/
void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
{
qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk);
}
/**
* @brief Set the QSPI bus clock.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz.
* @return Actual frequency of QSPI bus clock.
* @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate.
* For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock
* rate will be 6 MHz.
* @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
* @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
* @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
*/
uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
{
uint32_t u32ClkSrc, u32HCLKFreq;
uint32_t u32Div, u32RetValue;
/* Get system clock frequency */
u32HCLKFreq = CLK_GetHCLKFreq();
if (u32BusClock >= u32HCLKFreq)
{
/* Select PCLK as the clock source of QSPI */
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
}
/* Check clock source of SPI */
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
{
/* Clock source is PCLK0 */
u32ClkSrc = CLK_GetPCLK0Freq();
}
else
{
u32ClkSrc = __HIRC; /* Clock source is HIRC */
}
if (u32BusClock >= u32HCLKFreq)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0UL;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if (u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
qspi->CLKDIV = 0UL;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if (u32BusClock == 0UL)
{
/* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
}
else
{
u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
if (u32Div > 0x1FFUL)
{
u32Div = 0x1FFUL;
qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
}
else
{
qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (u32Div + 1UL));
}
}
return u32RetValue;
}
/**
* @brief Configure FIFO threshold setting.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
* @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
* @return None
* @details Set TX FIFO threshold and RX FIFO threshold configurations.
*/
void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
{
qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) |
(u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) |
(u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos);
}
/**
* @brief Get the actual frequency of QSPI bus clock. Only available in Master mode.
* @param[in] qspi The pointer of the specified QSPI module.
* @return Actual QSPI bus clock frequency in Hz.
* @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode.
*/
uint32_t QSPI_GetBusClock(QSPI_T *qspi)
{
uint32_t u32Div;
uint32_t u32ClkSrc;
/* Get DIVIDER setting */
u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
/* Check clock source of QSPI */
if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
{
/* Clock source is PCLK0 */
u32ClkSrc = CLK_GetPCLK0Freq();
}
else
{
u32ClkSrc = __HIRC; /* Clock source is HIRC */
}
/* Return QSPI bus clock rate */
return (u32ClkSrc / (u32Div + 1UL));
}
/**
* @brief Enable interrupt function.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Mask The combination of all related interrupt enable bits.
* Each bit corresponds to a interrupt enable bit.
* This parameter decides which interrupts will be enabled. It is combination of:
* - \ref QSPI_UNIT_INT_MASK
* - \ref QSPI_SSACT_INT_MASK
* - \ref QSPI_SSINACT_INT_MASK
* - \ref QSPI_SLVUR_INT_MASK
* - \ref QSPI_SLVBE_INT_MASK
* - \ref QSPI_SLVTO_INT_MASK
* - \ref QSPI_TXUF_INT_MASK
* - \ref QSPI_FIFO_TXTH_INT_MASK
* - \ref QSPI_FIFO_RXTH_INT_MASK
* - \ref QSPI_FIFO_RXOV_INT_MASK
* - \ref QSPI_FIFO_RXTO_INT_MASK
*
* @return None
* @details Enable QSPI related interrupts specified by u32Mask parameter.
*/
void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
{
/* Enable unit transfer interrupt flag */
if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
{
qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
}
/* Enable slave selection signal active interrupt flag */
if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
}
/* Enable slave selection signal inactive interrupt flag */
if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
}
/* Enable slave TX under run interrupt flag */
if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
}
/* Enable slave bit count error interrupt flag */
if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
}
/* Enable slave mode time-out interrupt flag */
if ((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
{
qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk;
}
/* Enable slave TX underflow interrupt flag */
if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
}
/* Enable TX threshold interrupt flag */
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
}
/* Enable RX threshold interrupt flag */
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
}
/* Enable RX overrun interrupt flag */
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
}
/* Enable RX time-out interrupt flag */
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
{
qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
}
}
/**
* @brief Disable interrupt function.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Mask The combination of all related interrupt enable bits.
* Each bit corresponds to a interrupt bit.
* This parameter decides which interrupts will be disabled. It is combination of:
* - \ref QSPI_UNIT_INT_MASK
* - \ref QSPI_SSACT_INT_MASK
* - \ref QSPI_SSINACT_INT_MASK
* - \ref QSPI_SLVUR_INT_MASK
* - \ref QSPI_SLVBE_INT_MASK
* - \ref QSPI_SLVTO_INT_MASK
* - \ref QSPI_TXUF_INT_MASK
* - \ref QSPI_FIFO_TXTH_INT_MASK
* - \ref QSPI_FIFO_RXTH_INT_MASK
* - \ref QSPI_FIFO_RXOV_INT_MASK
* - \ref QSPI_FIFO_RXTO_INT_MASK
*
* @return None
* @details Disable QSPI related interrupts specified by u32Mask parameter.
*/
void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
{
/* Disable unit transfer interrupt flag */
if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
{
qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
}
/* Disable slave selection signal active interrupt flag */
if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
}
/* Disable slave selection signal inactive interrupt flag */
if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
}
/* Disable slave TX under run interrupt flag */
if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
}
/* Disable slave bit count error interrupt flag */
if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
}
/* Disable slave mode time-out interrupt flag */
if ((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
{
qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk;
}
/* Disable slave TX underflow interrupt flag */
if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
}
/* Disable TX threshold interrupt flag */
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
}
/* Disable RX threshold interrupt flag */
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
}
/* Disable RX overrun interrupt flag */
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
}
/* Disable RX time-out interrupt flag */
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
{
qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
}
}
/**
* @brief Get interrupt flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Mask The combination of all related interrupt sources.
* Each bit corresponds to a interrupt source.
* This parameter decides which interrupt flags will be read. It is combination of:
* - \ref QSPI_UNIT_INT_MASK
* - \ref QSPI_SSACT_INT_MASK
* - \ref QSPI_SSINACT_INT_MASK
* - \ref QSPI_SLVUR_INT_MASK
* - \ref QSPI_SLVBE_INT_MASK
* - \ref QSPI_SLVTO_INT_MASK
* - \ref QSPI_TXUF_INT_MASK
* - \ref QSPI_FIFO_TXTH_INT_MASK
* - \ref QSPI_FIFO_RXTH_INT_MASK
* - \ref QSPI_FIFO_RXOV_INT_MASK
* - \ref QSPI_FIFO_RXTO_INT_MASK
*
* @return Interrupt flags of selected sources.
* @details Get QSPI related interrupt flags specified by u32Mask parameter.
*/
uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
{
uint32_t u32IntFlag = 0U, u32TmpVal;
u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk;
/* Check unit transfer interrupt flag */
if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_UNIT_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk;
/* Check slave selection signal active interrupt flag */
if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SSACT_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk;
/* Check slave selection signal inactive interrupt flag */
if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SSINACT_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk;
/* Check slave TX under run interrupt flag */
if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SLVUR_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk;
/* Check slave bit count error interrupt flag */
if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SLVBE_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVTOIF_Msk;
/* Check slave mode time-out interrupt flag */
if ((u32Mask & QSPI_SLVTO_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_SLVTO_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk;
/* Check slave TX underflow interrupt flag */
if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_TXUF_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk;
/* Check TX threshold interrupt flag */
if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk;
/* Check RX threshold interrupt flag */
if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk;
/* Check RX overrun interrupt flag */
if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
}
u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk;
/* Check RX time-out interrupt flag */
if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal))
{
u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
}
return u32IntFlag;
}
/**
* @brief Clear interrupt flag.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Mask The combination of all related interrupt sources.
* Each bit corresponds to a interrupt source.
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
* - \ref QSPI_UNIT_INT_MASK
* - \ref QSPI_SSACT_INT_MASK
* - \ref QSPI_SSINACT_INT_MASK
* - \ref QSPI_SLVUR_INT_MASK
* - \ref QSPI_SLVBE_INT_MASK
* - \ref QSPI_SLVTO_INT_MASK
* - \ref QSPI_TXUF_INT_MASK
* - \ref QSPI_FIFO_RXOV_INT_MASK
* - \ref QSPI_FIFO_RXTO_INT_MASK
*
* @return None
* @details Clear QSPI related interrupt flags specified by u32Mask parameter.
*/
void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
{
if (u32Mask & QSPI_UNIT_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
}
if (u32Mask & QSPI_SSACT_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
}
if (u32Mask & QSPI_SSINACT_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
}
if (u32Mask & QSPI_SLVUR_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
}
if (u32Mask & QSPI_SLVBE_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
}
if (u32Mask & QSPI_SLVTO_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */
}
if (u32Mask & QSPI_TXUF_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
}
if (u32Mask & QSPI_FIFO_RXOV_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
}
if (u32Mask & QSPI_FIFO_RXTO_INT_MASK)
{
qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
}
}
/**
* @brief Get QSPI status.
* @param[in] qspi The pointer of the specified QSPI module.
* @param[in] u32Mask The combination of all related sources.
* Each bit corresponds to a source.
* This parameter decides which flags will be read. It is combination of:
* - \ref QSPI_BUSY_MASK
* - \ref QSPI_RX_EMPTY_MASK
* - \ref QSPI_RX_FULL_MASK
* - \ref QSPI_TX_EMPTY_MASK
* - \ref QSPI_TX_FULL_MASK
* - \ref QSPI_TXRX_RESET_MASK
* - \ref QSPI_QSPIEN_STS_MASK
* - \ref QSPI_SSLINE_STS_MASK
*
* @return Flags of selected sources.
* @details Get QSPI related status specified by u32Mask parameter.
*/
uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
{
uint32_t u32Flag = 0UL, u32TmpValue;
u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk;
/* Check busy status */
if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_BUSY_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk;
/* Check RX empty flag */
if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_RX_EMPTY_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk;
/* Check RX full flag */
if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_RX_FULL_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk;
/* Check TX empty flag */
if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_TX_EMPTY_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk;
/* Check TX full flag */
if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_TX_FULL_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk;
/* Check TX/RX reset flag */
if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_TXRX_RESET_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk;
/* Check QSPIEN flag */
if ((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_QSPIEN_STS_MASK;
}
u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk;
/* Check QSPIx_SS line status */
if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue))
{
u32Flag |= QSPI_SSLINE_STS_MASK;
}
return u32Flag;
}
/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group QSPI_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

628
board/Nuvoton_M251/StdDriver/src/retarget.c Normal file
View File

@@ -0,0 +1,628 @@
/**************************************************************************//**
* @file retarget.c
* @version V0.10
* @brief M251 series serial driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
****************************************************************************/
#include <stdio.h>
#include "NuMicro.h"
#if defined (__ICCARM__)
#pragma diag_suppress=Pm150
#endif
#if defined ( __CC_ARM )
#if (__ARMCC_VERSION < 400000)
#else
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
#pragma import _printf_widthprec
#endif
#endif
# define DEBUG_PORT UART0
# define BUF_SIZE 512
/*---------------------------------------------------------------------------------------------------------*/
/* Global variables */
/*---------------------------------------------------------------------------------------------------------*/
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
#if (__ARMCC_VERSION < 6040000)
struct __FILE
{
int handle; /* Add whatever you need here */
};
#endif
#endif
FILE __stdout;
FILE __stdin;
#if defined (__ARMCC_VERSION) || defined (__ICCARM__)
extern int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0);
#if defined( __ICCARM__ )
__WEAK
#else
__attribute__((weak))
#endif
uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp);
#endif
int kbhit(void);
int IsDebugFifoEmpty(void);
void _ttywrch(int ch);
int fputc(int ch, FILE *stream);
#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION)
#if !defined (OS_USE_SEMIHOSTING)
int _read(int fd, char *ptr, int len);
#endif
int _write(int fd, char *ptr, int len);
#endif
#if defined (__ARMCC_VERSION) || defined (__ICCARM__)
int fgetc(FILE *stream);
int ferror(FILE *stream);
#endif
char GetChar(void);
void SendChar_ToUART(int ch);
void SendChar(int ch);
static volatile int32_t g_ICE_Conneced = 1;
enum { r0, r1, r2, r3, r12, lr, pc, psr};
/**
* @brief Helper function to dump register while hard fault occurred
* @param[in] stack pointer points to the dumped registers in SRAM
* @return None
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
*/
static void DumpStack(uint32_t stack[])
{
printf("r0 =0x%x\n", stack[r0]);
printf("r1 =0x%x\n", stack[r1]);
printf("r2 =0x%x\n", stack[r2]);
printf("r3 =0x%x\n", stack[r3]);
printf("r12=0x%x\n", stack[r12]);
printf("lr =0x%x\n", stack[lr]);
printf("pc =0x%x\n", stack[pc]);
printf("psr=0x%x\n", stack[psr]);
}
#if defined(DEBUG_ENABLE_SEMIHOST)
/* The static buffer is used to speed up the semihost */
static char g_buf[16];
static char g_buf_len = 0;
/**
*
* @brief The function to process semihosted command
* @param[in] n32In_R0 : semihost register 0
* @param[in] n32In_R1 : semihost register 1
* @param[out] pn32Out_R0: semihost register 0
* @retval 0: No ICE debug
* @retval 1: ICE debug
*
*/
int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
{
if (g_ICE_Conneced)
{
if (pn32Out_R0)
*pn32Out_R0 = n32In_R0;
return 1;
}
return 0;
}
#else // defined(DEBUG_ENABLE_SEMIHOST)
#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION)
/**
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
*
* @param None
*
* @returns None
*
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
*
*/
void HardFault_Handler(void)
{
asm("MOV R0, LR \n"
"MRS R1, MSP \n"
"MRS R2, PSP \n"
"LDR R3, =ProcessHardFault \n"
"BLX R3 \n"
"BX R0 \n"
);
}
#else
int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0);
int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
{
return 0;
}
#endif
#endif /* defined(DEBUG_ENABLE_SEMIHOST) */
#if defined( __ICCARM__ )
__WEAK
#else
__attribute__((weak))
#endif
uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp)
{
uint32_t *sp;
uint32_t inst;
/* It is casued by hardfault. Just process the hard fault */
/* TODO: Implement your hardfault handle code here */
/* Check the used stack */
// if(lr & 0x40UL) // M251 has no TrustZone.
{
/* Secure stack used */
if (lr & 4UL)
{
sp = (uint32_t *)psp;
}
else
{
sp = (uint32_t *)msp;
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
else
{
/* Non-secure stack used */
if (lr & 4)
sp = (uint32_t *)__TZ_get_PSP_NS();
else
sp = (uint32_t *)__TZ_get_MSP_NS();
}
#endif
/* Get the instruction caused the hardfault */
inst = M16(sp[6]);
if (inst == 0xBEAB)
{
/*
If the instruction is 0xBEAB, it means it is caused by BKPT without ICE connected.
We still return for output/input message to UART.
*/
g_ICE_Conneced = 0; // Set a flag for ICE offline
sp[6] += 2; // Return to next instruction
return lr; // Keep lr in R0
}
printf(" HardFault!\n\n");
DumpStack(sp);
/* Or *sp to remove compiler warning */
while (1U | *sp) {}
return lr;
}
/**
* @brief Routine to send a char
*
* @param[in] ch A character data writes to debug port
*
* @returns Send value from UART debug port
*
* @details Send a target char to UART debug port .
*/
#ifndef NONBLOCK_PRINTF
void SendChar_ToUART(int ch)
{
while (DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {}
DEBUG_PORT->DAT = (uint32_t)ch;
if ((char)ch == '\n')
{
while (DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {}
DEBUG_PORT->DAT = '\r';
}
}
#else
/* Non-block implement of send char */
void SendChar_ToUART(int ch)
{
static uint8_t u8Buf[BUF_SIZE] = {0};
static int32_t i32Head = 0;
static int32_t i32Tail = 0;
int32_t i32Tmp;
/* Only flush the data in buffer to UART when ch == 0 */
if (ch)
{
// Push char
i32Tmp = i32Head + 1;
if (i32Tmp > BUF_SIZE) i32Tmp = 0;
if (i32Tmp != i32Tail)
{
u8Buf[i32Head] = ch;
i32Head = i32Tmp;
}
if (ch == '\n')
{
i32Tmp = i32Head + 1;
if (i32Tmp > BUF_SIZE) i32Tmp = 0;
if (i32Tmp != i32Tail)
{
u8Buf[i32Head] = '\r';
i32Head = i32Tmp;
}
}
}
else
{
if (i32Tail == i32Head)
return;
}
// Pop char
do
{
i32Tmp = i32Tail + 1;
if (i32Tmp > BUF_SIZE) i32Tmp = 0;
if ((DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk) == 0)
{
DEBUG_PORT->DATA = u8Buf[i32Tail];
i32Tail = i32Tmp;
}
else
break; // FIFO full
} while (i32Tail != i32Head);
}
#endif /* else for NONBLOCK_PRINTF */
/**
* @brief Routine to send a char
*
* @param[in] ch : A character data writes to debug port
*
* @returns Send value from UART debug port or semihost
*
* @details Send a target char to UART debug port or semihost.
*/
#if !defined( __ICCARM__ )
#define __WEAK __attribute__((weak))
#endif
__WEAK void SendChar(int ch)
{
#if defined(DEBUG_ENABLE_SEMIHOST)
g_buf[g_buf_len++] = ch;
g_buf[g_buf_len] = '\0';
if (g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
{
/* Send the char */
if (g_ICE_Conneced)
{
if (SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
{
g_buf_len = 0;
return;
}
}
else
{
#if (DEBUG_ENABLE_SEMIHOST == 1) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=1
int i;
for (i = 0; i < g_buf_len; i++)
SendChar_ToUART(g_buf[i]);
#endif
g_buf_len = 0;
}
}
#else
#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION)
char *ch0;
*ch0 = (char)ch;
_write(0, ch0, 1);
#else
SendChar_ToUART(ch);
#endif /* ( __GNUC__ ) */
#endif /* DEBUG_ENABLE_SEMIHOST */
}
/**
* @brief Routine to get a char
*
* @param None
*
* @returns Get value from UART debug port or semihost
*
* @details Wait UART debug port or semihost to input a char.
*/
char GetChar(void)
{
#ifdef DEBUG_ENABLE_SEMIHOST
if(g_ICE_Conneced)
{
#if defined (__ICCARM__)
int nRet;
while (SH_DoCommand(0x7, 0, &nRet) != 0)
{
if (nRet != 0)
return (char)nRet;
}
#else
int nRet, nRet1;
while (SH_DoCommand(0x101, 0, &nRet) != 0)
{
if (nRet != 0)
{
SH_DoCommand(0x07, 0, &nRet);
return (char)nRet;
}
}
#endif
}
else
{
#if (DEBUG_ENABLE_SEMIHOST == 1) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=1
/* Use debug port when ICE is not connected at semihost mode */
while (!g_ICE_Conneced)
{
if ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U)
{
return ((char)DEBUG_PORT->DAT);
}
}
#endif
}
return (0);
#else
while (1)
{
if ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U)
{
return ((char)DEBUG_PORT->DAT);
}
}
#endif
}
/**
* @brief Check any char input from UART
*
* @param None
*
* @retval 1: No any char input
* @retval 0: Have some char input
*
* @details Check UART RSR RX EMPTY or not to determine if any char input from UART
*/
int kbhit(void)
{
return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U);
}
/**
* @brief Check if debug message finished
*
* @param None
*
* @retval 1: Message is finished
* @retval 0: Message is transmitting.
*
* @details Check if message finished (FIFO empty of debug port)
*/
int IsDebugFifoEmpty(void)
{
return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0U);
}
/**
* @brief C library retargetting
*
* @param[in] ch Write a character data
*
* @returns None
*
* @details Check if message finished (FIFO empty of debug port)
*/
void _ttywrch(int ch)
{
SendChar(ch);
return;
}
/**
* @brief Write character to stream
*
* @param[in] ch Character to be written. The character is passed as its int promotion.
* @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
*
* @returns If there are no errors, the same character that has been written is returned.
* If an error occurs, EOF is returned and the error indicator is set (see ferror).
*
* @details Writes a character to the stream and advances the position indicator.\n
* The character is written at the current position of the stream as indicated \n
* by the internal position indicator, which is then advanced one character.
*
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
*
*
*/
int fputc(int ch, FILE *stream)
{
SendChar(ch);
return ch;
}
#if defined ( __GNUC__ ) && !defined (__ARMCC_VERSION)
#if defined (OS_USE_SEMIHOSTING)
#else
int _write(int fd, char *ptr, int len)
{
int i = len;
while (i--)
{
while (DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
DEBUG_PORT->DAT = *ptr++;
if (*ptr == '\n')
{
while (DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
DEBUG_PORT->DAT = '\r';
}
}
return len;
}
int _read(int fd, char *ptr, int len)
{
while ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) != 0);
*ptr = DEBUG_PORT->DAT;
return 1;
}
#endif
#else
/**
* @brief Get character from UART debug port or semihosting input
*
* @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
*
* @returns The character read from UART debug port or semihosting
*
* @details For get message from debug port or semihosting.
*
*/
int fgetc(FILE *stream)
{
return ((int)GetChar());
}
/**
* @brief Check error indicator
*
* @param[in] stream Pointer to a FILE object that identifies the stream.
*
* @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
* Otherwise, it returns a zero value.
*
* @details Checks if the error indicator associated with stream is set, returning a value different
* from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
*
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
*
*/
int ferror(FILE *stream)
{
return EOF;
}
#endif
#ifdef DEBUG_ENABLE_SEMIHOST
#ifdef __ICCARM__
void __exit(int return_code)
{
/* Check if link with ICE */
if (SH_DoCommand(0x18, 0x20026, NULL) == 0)
{
/* Make sure all message is print out */
while (IsDebugFifoEmpty() == 0);
}
label:
goto label; /* Endless loop */
}
#else
void _sys_exit(int return_code)
{
/* Check if link with ICE */
if (SH_DoCommand(0x18, 0x20026, NULL) == 0)
{
/* Make sure all message is print out */
while (IsDebugFifoEmpty() == 0);
}
label:
goto label; /* Endless loop */
}
#endif
#endif

893
board/Nuvoton_M251/StdDriver/src/rtc.c Normal file
View File

@@ -0,0 +1,893 @@
/****************************************************************************
* @file rtc.c
* @version V1.00
* @brief M251 series CLK driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @cond HIDDEN_SYMBOLS */
/*---------------------------------------------------------------------------------------------------------*/
/* Macro, type and constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define RTC_GLOBALS
/*---------------------------------------------------------------------------------------------------------*/
/* Global file scope (static) variables */
/*---------------------------------------------------------------------------------------------------------*/
static volatile uint32_t g_u32HiYear, g_u32LoYear, g_u32HiMonth, g_u32LoMonth, g_u32HiDay, g_u32LoDay;
static volatile uint32_t g_u32HiHour, g_u32LoHour, g_u32HiMin, g_u32LoMin, g_u32HiSec, g_u32LoSec;
/** @endcond HIDDEN_SYMBOLS */
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup RTC_Driver RTC Driver
@{
*/
/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
@{
*/
/**
* @brief Initialize RTC module and start counting
*
* @param[in] psPt Specify the time property and current date and time. It includes: \n
* u32Year: Year value, range between 2000 ~ 2099. \n
* u32Month: Month value, range between 1 ~ 12. \n
* u32Day: Day value, range between 1 ~ 31. \n
* u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
* RTC_SATURDAY] \n
* u32Hour: Hour value, range between 0 ~ 23. \n
* u32Minute: Minute value, range between 0 ~ 59. \n
* u32Second: Second value, range between 0 ~ 59. \n
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
* u8AmPm: [RTC_AM / RTC_PM] \n
*
* @return None
*
* @details This function is used to: \n
* 1. Write initial key to let RTC start count. \n
* 2. Input parameter indicates start date/time. \n
* 3. User has to make sure that parameters of RTC date/time are reasonable. \n
* @note Null pointer for using default starting date/time.
*/
void RTC_Open(S_RTC_TIME_DATA_T *psPt)
{
RTC->INIT = RTC_INIT_KEY;
if (RTC->INIT != RTC_INIT_ACTIVE_Msk)
{
RTC->INIT = RTC_INIT_KEY;
while (RTC->INIT != RTC_INIT_ACTIVE_Msk)
{
}
}
if (psPt == 0)
{
/* No RTC date/time data */
}
else
{
/* Set RTC date and time */
RTC_SetDateAndTime(psPt);
}
}
/**
* @brief Disable RTC Clock
*
* @param None
*
* @return None
*
* @details This API will disable RTC peripheral clock and stops RTC counting.
*/
void RTC_Close(void)
{
CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
}
/**
* @brief Set Frequency Compensation Data
*
* @param[in] i32FrequencyX10000 Specify the RTC clock X 10000, ex: 327736512 means 32773.6512.
*
* @return None
*
*/
void RTC_32KCalibration(int32_t i32FrequencyX10000)
{
/*
Frequency counter measurement : 32773.6512 Hz
*/
uint32_t u32Index;
uint32_t u32Compensate;
/* 327736512 %10000 = 6512 */
u32Compensate = (uint32_t)(i32FrequencyX10000 % 10000);
/*Fraction Part: (6512 X 64)/10000 = 41.6768(0x2A) => RTC_FREQADJ[5:0]=0x2A*/
u32Compensate = ((u32Compensate * 64) / 10000);
u32Compensate &= 0x3F;
/*
Formula for 32K compensation is
FREQADJ = 0~0x00001F00 (Frequency range : 32752Hz ~ 32783Hz)
*/
if (i32FrequencyX10000 >= (uint32_t)327840000)
{
u32Compensate = 0x1F3F;
}
else if (i32FrequencyX10000 < (uint32_t)327520000)
{
u32Compensate = 0x0;
}
else
{
/* Integer Part: 32773 => RTC_FREQADJ[12:8] = 0x15 */
for (u32Index = 0; u32Index < 0x20 ; u32Index++)
{
if ((i32FrequencyX10000 >= 327520000 + (u32Index * 10000)) && (i32FrequencyX10000 < 327520000 + ((u32Index + 1) * 10000)))
{
u32Compensate += (u32Index << RTC_FREQADJ_INTEGER_Pos);
break;
}
}
}
RTC->FREQADJ = (uint32_t)u32Compensate;
}
/**
* @brief Get Current RTC Date and Time
*
* @param[out] psPt The returned pointer is specified the current RTC value. It includes: \n
* u32Year: Year value \n
* u32Month: Month value \n
* u32Day: Day value \n
* u32DayOfWeek: Day of week \n
* u32Hour: Hour value \n
* u32Minute: Minute value \n
* u32Second: Second value \n
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
* u8AmPm: [RTC_AM / RTC_PM] \n
*
* @return None
*
* @details This API is used to get the current RTC date and time value.
*/
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *psPt)
{
uint32_t u32Tmp;
psPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
psPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
/* Get [Date digit] data */
g_u32HiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
g_u32LoYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
g_u32HiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
g_u32LoMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
g_u32HiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
g_u32LoDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
/* Get [Time digit] data */
g_u32HiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
g_u32LoHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
g_u32HiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
g_u32LoMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
g_u32HiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
g_u32LoSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
/* Compute to 20XX year */
u32Tmp = (g_u32HiYear * 10ul);
u32Tmp += g_u32LoYear;
psPt->u32Year = u32Tmp + RTC_YEAR2000;
/* Compute 0~12 month */
u32Tmp = (g_u32HiMonth * 10ul);
psPt->u32Month = u32Tmp + g_u32LoMonth;
/* Compute 0~31 day */
u32Tmp = (g_u32HiDay * 10ul);
psPt->u32Day = u32Tmp + g_u32LoDay;
/* Compute 12/24 hour */
if (psPt->u32TimeScale == RTC_CLOCK_12)
{
u32Tmp = (g_u32HiHour * 10ul);
u32Tmp += g_u32LoHour;
psPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
if (psPt->u32Hour >= 21ul)
{
psPt->u32AmPm = RTC_PM;
psPt->u32Hour -= 20ul;
}
else
{
psPt->u32AmPm = RTC_AM;
}
u32Tmp = (g_u32HiMin * 10ul);
u32Tmp += g_u32LoMin;
psPt->u32Minute = u32Tmp;
u32Tmp = (g_u32HiSec * 10ul);
u32Tmp += g_u32LoSec;
psPt->u32Second = u32Tmp;
}
else
{
u32Tmp = (g_u32HiHour * 10ul);
u32Tmp += g_u32LoHour;
psPt->u32Hour = u32Tmp;
u32Tmp = (g_u32HiMin * 10ul);
u32Tmp += g_u32LoMin;
psPt->u32Minute = u32Tmp;
u32Tmp = (g_u32HiSec * 10ul);
u32Tmp += g_u32LoSec;
psPt->u32Second = u32Tmp;
}
}
/**
* @brief Get RTC Alarm Date and Time
*
* @param[out] psPt The returned pointer is specified the RTC alarm value. It includes: \n
* u32Year: Year value \n
* u32Month: Month value \n
* u32Day: Day value \n
* u32DayOfWeek: Day of week \n
* u32Hour: Hour value \n
* u32Minute: Minute value \n
* u32Second: Second value \n
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
* u8AmPm: [RTC_AM / RTC_PM] \n
*
* @return None
*
* @details This API is used to get the RTC alarm date and time setting.
*/
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt)
{
uint32_t u32Tmp;
psPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
psPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
/* Get alarm [Date digit] data */
g_u32HiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
g_u32LoYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
g_u32HiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
g_u32LoMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
g_u32HiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
g_u32LoDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
/* Get alarm [Time digit] data */
g_u32HiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
g_u32LoHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
g_u32HiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
g_u32LoMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
g_u32HiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
g_u32LoSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
/* Compute to 20XX year */
u32Tmp = (g_u32HiYear * 10ul);
u32Tmp += g_u32LoYear;
psPt->u32Year = u32Tmp + RTC_YEAR2000;
/* Compute 0~12 month */
u32Tmp = (g_u32HiMonth * 10ul);
psPt->u32Month = u32Tmp + g_u32LoMonth;
/* Compute 0~31 day */
u32Tmp = (g_u32HiDay * 10ul);
psPt->u32Day = u32Tmp + g_u32LoDay;
/* Compute 12/24 hour */
if (psPt->u32TimeScale == RTC_CLOCK_12)
{
u32Tmp = (g_u32HiHour * 10ul);
u32Tmp += g_u32LoHour;
psPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
if (psPt->u32Hour >= 21ul)
{
psPt->u32AmPm = RTC_PM;
psPt->u32Hour -= 20ul;
}
else
{
psPt->u32AmPm = RTC_AM;
}
u32Tmp = (g_u32HiMin * 10ul);
u32Tmp += g_u32LoMin;
psPt->u32Minute = u32Tmp;
u32Tmp = (g_u32HiSec * 10ul);
u32Tmp += g_u32LoSec;
psPt->u32Second = u32Tmp;
}
else
{
u32Tmp = (g_u32HiHour * 10ul);
u32Tmp += g_u32LoHour;
psPt->u32Hour = u32Tmp;
u32Tmp = (g_u32HiMin * 10ul);
u32Tmp += g_u32LoMin;
psPt->u32Minute = u32Tmp;
u32Tmp = (g_u32HiSec * 10ul);
u32Tmp += g_u32LoSec;
psPt->u32Second = u32Tmp;
}
}
/**
* @brief Update Current RTC Date and Time
*
* @param[in] psPt Specify the time property and current date and time. It includes: \n
* u32Year: Year value, range between 2000 ~ 2099. \n
* u32Month: Month value, range between 1 ~ 12. \n
* u32Day: Day value, range between 1 ~ 31. \n
* u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
* RTC_SATURDAY] \n
* u32Hour: Hour value, range between 0 ~ 23. \n
* u32Minute: Minute value, range between 0 ~ 59. \n
* u32Second: Second value, range between 0 ~ 59. \n
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
* u8AmPm: [RTC_AM / RTC_PM] \n
*
* @return None
*
* @details This API is used to update current date and time to RTC.
*/
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *psPt)
{
uint32_t u32RegCAL, u32RegTIME;
if (psPt == 0ul)
{
/* No RTC date/time data */
}
else
{
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
if (psPt->u32TimeScale == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
/*-------------------------------------------------------------------------------------------------*/
/* Important, range of 12-hour PM mode is 21 up to 32 */
/*-------------------------------------------------------------------------------------------------*/
if (psPt->u32AmPm == RTC_PM)
{
psPt->u32Hour += 20ul;
}
}
else
{
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
}
/* Set Day of the Week */
RTC->WEEKDAY = psPt->u32DayOfWeek;
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC Current Date and Time */
/*-----------------------------------------------------------------------------------------------------*/
u32RegCAL = ((psPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
u32RegCAL |= (((psPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
u32RegCAL |= ((psPt->u32Month / 10ul) << 12);
u32RegCAL |= ((psPt->u32Month % 10ul) << 8);
u32RegCAL |= ((psPt->u32Day / 10ul) << 4);
u32RegCAL |= (psPt->u32Day % 10ul);
u32RegTIME = ((psPt->u32Hour / 10ul) << 20);
u32RegTIME |= ((psPt->u32Hour % 10ul) << 16);
u32RegTIME |= ((psPt->u32Minute / 10ul) << 12);
u32RegTIME |= ((psPt->u32Minute % 10ul) << 8);
u32RegTIME |= ((psPt->u32Second / 10ul) << 4);
u32RegTIME |= (psPt->u32Second % 10ul);
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC Calender and Time Loading */
/*-----------------------------------------------------------------------------------------------------*/
RTC->CAL = (uint32_t)u32RegCAL;
RTC->TIME = (uint32_t)u32RegTIME;
}
}
/**
* @brief Update RTC Alarm Date and Time
*
* @param[in] psPt Specify the time property and alarm date and time. It includes: \n
* u32Year: Year value, range between 2000 ~ 2099. \n
* u32Month: Month value, range between 1 ~ 12. \n
* u32Day: Day value, range between 1 ~ 31. \n
* u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
* RTC_SATURDAY] \n
* u32Hour: Hour value, range between 0 ~ 23. \n
* u32Minute: Minute value, range between 0 ~ 59. \n
* u32Second: Second value, range between 0 ~ 59. \n
* u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
* u8AmPm: [RTC_AM / RTC_PM] \n
*
* @return None
*
* @details This API is used to update alarm date and time setting to RTC.
*/
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt)
{
uint32_t u32RegCALM, u32RegTALM;
if (psPt == 0)
{
/* No RTC date/time data */
}
else
{
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
if (psPt->u32TimeScale == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
/*-------------------------------------------------------------------------------------------------*/
/* Important, range of 12-hour PM mode is 21 up to 32 */
/*-------------------------------------------------------------------------------------------------*/
if (psPt->u32AmPm == RTC_PM)
{
psPt->u32Hour += 20ul;
}
}
else
{
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
}
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC Alarm Date and Time */
/*-----------------------------------------------------------------------------------------------------*/
u32RegCALM = ((psPt->u32Year - RTC_YEAR2000) / 10ul) << 20;
u32RegCALM |= (((psPt->u32Year - RTC_YEAR2000) % 10ul) << 16);
u32RegCALM |= ((psPt->u32Month / 10ul) << 12);
u32RegCALM |= ((psPt->u32Month % 10ul) << 8);
u32RegCALM |= ((psPt->u32Day / 10ul) << 4);
u32RegCALM |= (psPt->u32Day % 10ul);
u32RegTALM = ((psPt->u32Hour / 10ul) << 20);
u32RegTALM |= ((psPt->u32Hour % 10ul) << 16);
u32RegTALM |= ((psPt->u32Minute / 10ul) << 12);
u32RegTALM |= ((psPt->u32Minute % 10ul) << 8);
u32RegTALM |= ((psPt->u32Second / 10ul) << 4);
u32RegTALM |= (psPt->u32Second % 10ul);
RTC->CALM = (uint32_t)u32RegCALM;
RTC->TALM = (uint32_t)u32RegTALM;
}
}
/**
* @brief Update RTC Current Date
*
* @param[in] u32Year The year calendar digit of current RTC setting.
* @param[in] u32Month The month calendar digit of current RTC setting.
* @param[in] u32Day The day calendar digit of current RTC setting.
* @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
* RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
* RTC_SATURDAY]
*
* @return None
*
* @details This API is used to update current date to RTC.
*/
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
{
uint32_t u32RegCAL;
u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
u32RegCAL |= ((u32Month / 10ul) << 12);
u32RegCAL |= ((u32Month % 10ul) << 8);
u32RegCAL |= ((u32Day / 10ul) << 4);
u32RegCAL |= (u32Day % 10ul);
/* Set Day of the Week */
RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
/* Set RTC Calender Loading */
RTC->CAL = (uint32_t)u32RegCAL;
}
/**
* @brief Update RTC Current Time
*
* @param[in] u32Hour The hour time digit of current RTC setting.
* @param[in] u32Minute The minute time digit of current RTC setting.
* @param[in] u32Second The second time digit of current RTC setting.
* @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
* @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
*
* @return None
*
* @details This API is used to update current time to RTC.
*/
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
{
uint32_t u32RegTIME;
/* Important, range of 12-hour PM mode is 21 up to 32 */
if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
{
u32Hour += 20ul;
}
u32RegTIME = ((u32Hour / 10ul) << 20);
u32RegTIME |= ((u32Hour % 10ul) << 16);
u32RegTIME |= ((u32Minute / 10ul) << 12);
u32RegTIME |= ((u32Minute % 10ul) << 8);
u32RegTIME |= ((u32Second / 10ul) << 4);
u32RegTIME |= (u32Second % 10ul);
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
if (u32TimeMode == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
}
else
{
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
}
RTC->TIME = (uint32_t)u32RegTIME;
}
/**
* @brief Update RTC Alarm Date
*
* @param[in] u32Year The year calendar digit of RTC alarm setting.
* @param[in] u32Month The month calendar digit of RTC alarm setting.
* @param[in] u32Day The day calendar digit of RTC alarm setting.
*
* @return None
*
* @details This API is used to update alarm date setting to RTC.
*/
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
{
uint32_t u32RegCALM;
u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20;
u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16);
u32RegCALM |= ((u32Month / 10ul) << 12);
u32RegCALM |= ((u32Month % 10ul) << 8);
u32RegCALM |= ((u32Day / 10ul) << 4);
u32RegCALM |= (u32Day % 10ul);
/* Set RTC Alarm Date */
RTC->CALM = (uint32_t)u32RegCALM;
}
/**
* @brief Update RTC Alarm Time
*
* @param[in] u32Hour The hour time digit of RTC alarm setting.
* @param[in] u32Minute The minute time digit of RTC alarm setting.
* @param[in] u32Second The second time digit of RTC alarm setting.
* @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
* @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
*
* @return None
*
* @details This API is used to update alarm time setting to RTC.
*/
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
{
uint32_t u32RegTALM;
/* Important, range of 12-hour PM mode is 21 up to 32 */
if ((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM))
{
u32Hour += 20ul;
}
u32RegTALM = ((u32Hour / 10ul) << 20);
u32RegTALM |= ((u32Hour % 10ul) << 16);
u32RegTALM |= ((u32Minute / 10ul) << 12);
u32RegTALM |= ((u32Minute % 10ul) << 8);
u32RegTALM |= ((u32Second / 10ul) << 4);
u32RegTALM |= (u32Second % 10ul);
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
if (u32TimeMode == (uint32_t)RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
}
else
{
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
}
/* Set RTC Alarm Time */
RTC->TALM = (uint32_t)u32RegTALM;
}
/**
* @brief Set RTC Alarm Date Mask Function
*
* @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled.
* @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled.
* @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled.
* @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled.
* @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled.
* @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled.
*
* @return None
*
* @details This API is used to enable or disable RTC alarm date mask function.
*/
void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk)
{
RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) |
((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) |
((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) |
((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) |
((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) |
((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos);
}
/**
* @brief Set RTC Alarm Time Mask Function
*
* @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled.
* @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled.
* @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled.
* @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled.
* @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled.
* @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled.
*
* @return None
*
* @details This API is used to enable or disable RTC alarm time mask function.
*/
void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk)
{
RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) |
((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) |
((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) |
((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) |
((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) |
((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos);
}
/**
* @brief Get Day of the Week
*
* @param None
*
* @retval 0 Sunday
* @retval 1 Monday
* @retval 2 Tuesday
* @retval 3 Wednesday
* @retval 4 Thursday
* @retval 5 Friday
* @retval 6 Saturday
*
* @details This API is used to get day of the week of current RTC date.
*/
uint32_t RTC_GetDayOfWeek(void)
{
return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
}
/**
* @brief Set RTC Tick Period Time
*
* @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n
* It consists of:
* - \ref RTC_TICK_1_SEC : Time tick is 1 second
* - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second
* - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second
* - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second
* - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second
* - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second
* - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second
* - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
*
* @return None
*
* @details This API is used to set RTC tick period time for each tick interrupt.
*/
void RTC_SetTickPeriod(uint32_t u32TickSelection)
{
RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
}
/**
* @brief Enable RTC Interrupt
*
* @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
* - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
* - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
* - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
*
* @return None
*
* @details This API is used to enable the specify RTC interrupt function.
*/
void RTC_EnableInt(uint32_t u32IntFlagMask)
{
RTC->INTEN |= u32IntFlagMask;
}
/**
* @brief Disable RTC Interrupt
*
* @param[in] u32IntFlagMask Specify the interrupt source. It consists of:
* - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt
* - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt
* - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
*
* @return None
*
* @details This API is used to disable the specify RTC interrupt function.
*/
void RTC_DisableInt(uint32_t u32IntFlagMask)
{
RTC->INTEN &= ~u32IntFlagMask;
RTC->INTSTS = u32IntFlagMask;
}
/**
* @brief Enable Spare Registers Access
*
* @param None
*
* @return None
*
* @details This API is used to enable the spare registers 0~4 can be accessed.
*/
void RTC_EnableSpareAccess(void)
{
RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
}
/**
* @brief Disable Spare Register
*
* @param None
*
* @return None
*
* @details This API is used to disable the spare register 0~4 cannot be accessed.
*/
void RTC_DisableSpareRegister(void)
{
RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
}
/**
* @brief Static Tamper Detect
*
* @param[in] u32TamperSelect Tamper pin select. Possible options are
* - \ref RTC_TAMPER0_SELECT
*
* @param[in] u32DetecLevel Tamper pin detection level select. Possible options are
* - \ref RTC_TAMPER_HIGH_LEVEL_DETECT
* - \ref RTC_TAMPER_LOW_LEVEL_DETECT
*
* @param[in] u32DebounceEn Tamper pin de-bounce enable
* - \ref RTC_TAMPER_DEBOUNCE_ENABLE
* - \ref RTC_TAMPER_DEBOUNCE_DISABLE
*
* @return None
*
* @details This API is used to enable the tamper pin detect function with specify trigger condition.
*/
void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)
{
uint32_t u32Loop;
uint32_t u32Reg;
uint32_t u32TmpReg;
u32Reg = RTC->TAMPCTL;
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
(u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos));
for (u32Loop = 0ul; u32Loop < MAX_TAMPER_PIN_NUM; u32Loop++)
{
if (u32TamperSelect & (0x1ul << u32Loop))
{
u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (u32Loop * 4ul));
u32Reg |= (u32TmpReg << (u32Loop * 4ul));
}
}
RTC->TAMPCTL = u32Reg;
}
/**
* @brief Static Tamper Disable
*
* @param[in] u32TamperSelect Tamper pin select. Possible options are
* - \ref RTC_TAMPER0_SELECT
*
* @return None
*
* @details This API is used to disable the static tamper pin detect.
*/
void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
{
uint32_t u32Loop;
uint32_t u32Reg;
uint32_t u32TmpReg;
u32Reg = RTC->TAMPCTL;
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
for (u32Loop = 0ul; u32Loop < MAX_TAMPER_PIN_NUM; u32Loop++)
{
if (u32TamperSelect & (0x1ul << u32Loop))
{
u32Reg &= ~(u32TmpReg << (u32Loop * 4ul));
}
}
RTC->TAMPCTL = u32Reg;
}
/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group RTC_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

463
board/Nuvoton_M251/StdDriver/src/sc.c Normal file
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@@ -0,0 +1,463 @@
/**************************************************************************//**
* @file sc.c
* @version V3.00
* @brief Smart Card(SC) driver source file
*
* @note
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
/** @cond HIDDEN_SYMBOLS */
static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL};
/** @endcond HIDDEN_SYMBOLS */
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SC_Driver SC Driver
@{
*/
/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
@{
*/
/**
* @brief Check Smartcard Slot Status
*
* @param[in] psSC The pointer of smartcard module.
*
* @retval TRUE Card insert
* @retval FALSE Card remove
*
* @details This function is used to check if specified smartcard slot is presented.
*/
uint32_t SC_IsCardInserted(SC_T *psSC)
{
uint32_t ret;
/* put conditions into two variable to remove IAR compilation warning */
uint32_t cond1 = ((psSC->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
uint32_t cond2 = ((psSC->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
if ((psSC == SC0) && (u32CardStateIgnore[0] == 1UL))
{
ret = (uint32_t)TRUE;
}
else if (cond1 != cond2)
{
ret = (uint32_t)FALSE;
}
else
{
ret = (uint32_t)TRUE;
}
return ret;
}
/*
* @brief Reset the Tx/Rx FIFO
*
* @param[in] psSC The pointer of smartcard module.
*
* @return None
*
* @details This function reset both transmit and receive FIFO of specified smartcard module.
*/
void SC_ClearFIFO(SC_T *psSC)
{
while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk)
{
;
}
psSC->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
}
/**
* @brief Disable specified Smartcard
*
* @param[in] psSC The pointer of smartcard module.
*
* @return None
*
* @details SC will force all transition to IDLE state.
*/
void SC_Close(SC_T *psSC)
{
psSC->INTEN = 0UL;
while (psSC->PINCTL & SC_PINCTL_SYNC_Msk)
{
;
}
psSC->PINCTL = 0UL;
psSC->ALTCTL = 0UL;
while (psSC->CTL & SC_CTL_SYNC_Msk)
{
;
}
psSC->CTL = 0UL;
}
/**
* @brief Initialized Smartcard
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32CardDet Card detect polarity, select the SC_CD pin state which indicates card insert. Could be:
* -\ref SC_PIN_STATE_HIGH
* -\ref SC_PIN_STATE_LOW
* -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.
* @param[in] u32PWR Power on polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be:
* -\ref SC_PIN_STATE_HIGH
* -\ref SC_PIN_STATE_LOW
*
* @return None
*
* @details Initialization process configures smartcard and enables engine clock.
*/
void SC_Open(SC_T *psSC, uint32_t u32CardDet, uint32_t u32PWR)
{
uint32_t u32Reg = 0UL, u32Intf;
if (psSC == SC0)
{
u32Intf = 0UL;
}
else
{
u32Intf = 2UL;
}
if (u32CardDet != SC_PIN_STATE_IGNORE)
{
u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk;
u32CardStateIgnore[u32Intf] = 0UL;
}
else
{
u32CardStateIgnore[u32Intf] = 1UL;
}
psSC->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk;
while (psSC->CTL & SC_CTL_SYNC_Msk)
{
;
}
psSC->CTL = SC_CTL_SCEN_Msk | u32Reg;
}
/**
* @brief Reset specified Smartcard
*
* @param[in] psSC The pointer of smartcard module.
*
* @return None
*
* @details Reset the Tx/Rx FIFO, clock and initial default parameter.
*/
void SC_ResetReader(SC_T *psSC)
{
uint32_t u32Intf;
if (psSC == SC0)
{
u32Intf = 0UL;
}
else
{
u32Intf = 2UL;
}
/* Reset FIFO, enable auto de-activation while card removal */
psSC->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
/* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */
while (psSC->CTL & SC_CTL_SYNC_Msk)
{
;
}
psSC->CTL &= ~(SC_CTL_RXTRGLV_Msk |
SC_CTL_CDDBSEL_Msk |
SC_CTL_TXRTY_Msk |
SC_CTL_TXRTYEN_Msk |
SC_CTL_RXRTY_Msk |
SC_CTL_RXRTYEN_Msk);
while (psSC->CTL & SC_CTL_SYNC_Msk)
{
;
}
/* Enable auto convention, and all three smartcard internal timers */
psSC->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
/* Disable Rx timeout */
psSC->RXTOUT = 0UL;
/* 372 clocks per ETU by default */
psSC->ETUCTL = 371UL;
/* Enable necessary interrupt for smartcard operation */
if (u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */
{
psSC->INTEN = (SC_INTEN_RDAIEN_Msk |
SC_INTEN_TERRIEN_Msk |
SC_INTEN_TMR0IEN_Msk |
SC_INTEN_TMR1IEN_Msk |
SC_INTEN_TMR2IEN_Msk |
SC_INTEN_BGTIEN_Msk |
SC_INTEN_ACERRIEN_Msk);
}
else
{
psSC->INTEN = (SC_INTEN_RDAIEN_Msk |
SC_INTEN_TERRIEN_Msk |
SC_INTEN_TMR0IEN_Msk |
SC_INTEN_TMR1IEN_Msk |
SC_INTEN_TMR2IEN_Msk |
SC_INTEN_BGTIEN_Msk |
SC_INTEN_ACERRIEN_Msk |
SC_INTEN_CDIEN_Msk);
}
return;
}
/**
* @brief Set Block Guard Time
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32.
*
* @return None
*
* @details This function is used to configure block guard time (BGT) of specified smartcard module.
*/
void SC_SetBlockGuardTime(SC_T *psSC, uint32_t u32BGT)
{
psSC->CTL = (psSC->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos);
}
/**
* @brief Set Character Guard Time
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267.
*
* @return None
*
* @details This function is used to configure character guard time (CGT) of specified smartcard module.
* @note Before using this API, user should set the correct stop bit length first.
*/
void SC_SetCharGuardTime(SC_T *psSC, uint32_t u32CGT)
{
/* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */
u32CGT -= psSC->CTL & SC_CTL_NSB_Msk ? 11UL : 12UL;
psSC->EGT = u32CGT;
}
/**
* @brief Stop all Timer Counting
*
* @param[in] psSC The pointer of smartcard module.
*
* @return None
*
* @details This function stop all smartcard timer of specified smartcard module.
* @note This function stop the timers within smartcard module, \b not timer module.
*/
void SC_StopAllTimer(SC_T *psSC)
{
while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk)
{
;
}
psSC->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
}
/**
* @brief Configure and Start specified Timer
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32TimerNum Specify time channel to start. Valid values are 0, 1, 2.
* @param[in] u32Mode Timer operating mode, valid values are:
* - \ref SC_TMR_MODE_0
* - \ref SC_TMR_MODE_1
* - \ref SC_TMR_MODE_2
* - \ref SC_TMR_MODE_3
* - \ref SC_TMR_MODE_4
* - \ref SC_TMR_MODE_5
* - \ref SC_TMR_MODE_6
* - \ref SC_TMR_MODE_7
* - \ref SC_TMR_MODE_8
* - \ref SC_TMR_MODE_F
* @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs.
* For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.
*
* @return None
*
* @details Enable Timer starting, counter will count when condition match.
* @note This function start the timer within smartcard module, \b not timer module.
* @note Depend on the timer operating mode, timer may not start counting immediately.
*/
void SC_StartTimer(SC_T *psSC, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
{
uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL));
/* before to set CNTEN0/1/2 of reg. ALTCTL, SCEN bit must be enabled */
if (u32TimerNum <= 2)
{
while (psSC->CTL & SC_CTL_SYNC_Msk) {};
psSC->CTL |= SC_CTL_TMRSEL_Msk | SC_CTL_SCEN_Msk;
while (psSC->CTL & SC_CTL_SYNC_Msk) {};
while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk) {};
}
switch (u32TimerNum)
{
case 0UL:
while (psSC->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) {};
psSC->TMRCTL0 = reg;
psSC->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
break;
case 1UL:
while (psSC->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) {};
psSC->TMRCTL1 = reg;
psSC->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
break;
case 2UL:
while (psSC->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) {};
psSC->TMRCTL2 = reg;
psSC->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
break;
default:
break;
}
}
/**
* @brief Stop specified Timer Counting
*
* @param[in] psSC The pointer of smartcard module.
* @param[in] u32TimerNum Specify timer channel to stop. Valid values are 0, 1, 2.
*
* @return None
*
* @details This function stop a smartcard timer of specified smartcard module.
* @note This function stop the timer within smartcard module, \b not timer module.
*/
void SC_StopTimer(SC_T *psSC, uint32_t u32TimerNum)
{
while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk) {}
if (u32TimerNum == 0UL) /* timer 0 */
{
psSC->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
}
else if (u32TimerNum == 1UL) /* timer 1 */
{
psSC->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
}
else /* timer 2 */
{
psSC->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
}
}
/**
* @brief Get specified Smartcard Clock Frequency
*
* @param[in] psSC The pointer of smartcard module.
*
* @return Smartcard frequency in kHZ
*
* @details This function is used to get specified smartcard module clock frequency in kHz.
*/
uint32_t SC_GetInterfaceClock(SC_T *psSC)
{
uint32_t u32ClkSrc, u32Num, u32Clk = __HIRC, u32Div;
/* Get smartcard module clock source and divider */
if (psSC == SC0)
{
u32Num = 0UL;
u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);
u32Div = CLK_GetModuleClockDivider(SC0_MODULE);
// u32ClkSrc = __HXT;
// u32Div = SC0->ETUCTL&SC_ETUCTL_ETURDIV_Msk;
}
else
{
u32Clk = 0UL;
}
if (u32Clk == 0UL)
{
; /* Invalid sc port */
}
else
{
/* Get smartcard module clock */
if (u32ClkSrc == 0UL)
{
u32Clk = __HXT;
}
else if (u32ClkSrc == 1UL)
{
u32Clk = CLK_GetPLLClockFreq();
}
else if (u32ClkSrc == 2UL)
{
if (u32Num == 1UL)
{
u32Clk = CLK_GetPCLK1Freq();
}
else
{
u32Clk = CLK_GetPCLK0Freq();
}
}
else
{
u32Clk = __HIRC;
}
u32Clk /= (u32Div + 1UL) * 1000UL;
}
return u32Clk;
}
/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SC_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file scuart.c
* @brief M251 Smartcard UART mode (SCUART) driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
static uint32_t SCUART_GetClock(SC_T *sc);
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SCUART_Driver SCUART Driver
@{
*/
/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
@{
*/
/**
* @brief The function is used to disable smartcard interface UART mode.
* @param sc The base address of smartcard module.
* @return None
*/
void SCUART_Close(SC_T *sc)
{
sc->INTEN = 0UL;
sc->UARTCTL = 0UL;
sc->CTL = 0UL;
}
/** @cond HIDDEN_SYMBOLS */
/**
* @brief This function returns module clock of specified SC interface
* @param[in] sc The base address of smartcard module.
* @return Module clock of specified SC interface
*/
static uint32_t SCUART_GetClock(SC_T *sc)
{
uint32_t u32ClkSrc, u32Num, u32Clk;
if (sc == SC0)
{
u32Num = 0UL;
}
else
{
u32Num = 2UL;
}
u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
/* Get smartcard module clock */
if (u32ClkSrc == 0UL)
{
u32Clk = __HXT;
}
else if (u32ClkSrc == 1UL)
{
u32Clk = CLK_GetPLLClockFreq();
}
else if (u32ClkSrc == 2UL)
{
if (u32Num == 1UL)
{
u32Clk = CLK_GetPCLK1Freq();
}
else
{
u32Clk = CLK_GetPCLK0Freq();
}
}
else
{
u32Clk = __HIRC;
}
u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL);
return u32Clk;
}
/** @endcond HIDDEN_SYMBOLS */
/**
* @brief This function use to enable smartcard module UART mode and set baudrate.
* @param[in] sc The base address of smartcard module.
* @param[in] u32baudrate Target baudrate of smartcard module.
* @return Actual baudrate of smartcard mode
* @details This function configures character width to 8 bits, 1 stop bit, and no parity.
* And can use \ref SCUART_SetLineConfig function to update these settings
* The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
* by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
* register. Since the baudrate divider is 12-bit wide and must be larger than 4,
* (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
* 4096. Otherwise this function cannot configure SCUART to work with target baudrate.
*/
uint32_t SCUART_Open(SC_T *sc, uint32_t u32baudrate)
{
uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
/* Calculate divider for target baudrate */
u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL;
/* Enable smartcard interface and stop bit = 1 */
sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk;
/* Enable UART mode, disable parity and 8 bit per character */
sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk;
sc->ETUCTL = u32Div;
return (u32Clk / (u32Div + 1UL));
}
/**
* @brief The function is used to read Rx data from RX FIFO.
* @param[in] sc The base address of smartcard module.
* @param[in] pu8RxBuf The buffer to store receive the data
* @param[in] u32ReadBytes Target number of characters to receive
* @return Actual character number reads to buffer
* @note This function does not block and return immediately if there's no data available
*/
uint32_t SCUART_Read(SC_T *sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
{
uint32_t u32Count;
for (u32Count = 0UL; u32Count < u32ReadBytes; u32Count++)
{
if (SCUART_GET_RX_EMPTY(sc)) /* no data available */
{
break;
}
pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */
}
return u32Count;
}
/**
* @brief This function use to configure smartcard UART mode line setting.
* @param[in] sc The base address of smartcard module.
* @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
* @param[in] u32DataWidth The data length, could be
* - \ref SCUART_CHAR_LEN_5
* - \ref SCUART_CHAR_LEN_6
* - \ref SCUART_CHAR_LEN_7
* - \ref SCUART_CHAR_LEN_8
* @param[in] u32Parity The parity setting, could be
* - \ref SCUART_PARITY_NONE
* - \ref SCUART_PARITY_ODD
* - \ref SCUART_PARITY_EVEN
* @param[in] u32StopBits The stop bit length, could be
* - \ref SCUART_STOP_BIT_1
* - \ref SCUART_STOP_BIT_2
* @return Actual baudrate of smartcard
* @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
* by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
* register. Since the baudrate divider is 12-bit wide and must be larger than 4,
* (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
* 4096. Otherwise this function cannot configure SCUART to work with target baudrate.
*/
uint32_t SCUART_SetLineConfig(SC_T *sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
{
uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
if (u32Baudrate == 0UL) /* keep original baudrate setting */
{
u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
}
else
{
/* Calculate divider for target baudrate */
u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL;
sc->ETUCTL = u32Div;
}
/* Set stop bit */
sc->CTL = u32StopBits | SC_CTL_SCEN_Msk;
/* Set character width and parity */
sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk;
return (u32Clk / (u32Div + 1UL));
}
/**
* @brief This function use to set receive timeout count.
* @param[in] sc The base address of smartcard module.
* @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
* set this value to 0 will disable timeout counter
* @return None
* @details The time-out counter resets and starts counting whenever the RX buffer received a
* new data word. Once the counter decrease to 1 and no new data is received or CPU
* does not read any data from FIFO, a receiver time-out interrupt will be generated.
*/
void SCUART_SetTimeoutCnt(SC_T *sc, uint32_t u32TOC)
{
sc->RXTOUT = u32TOC;
}
/**
* @brief This function is to write data into transmit FIFO to send data out.
* @param[in] sc The base address of smartcard module.
* @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
* @param[in] u32WriteBytes Number of data to send.
* @return None
* @note This function blocks until all data write into FIFO
*/
void SCUART_Write(SC_T *sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
{
uint32_t u32Count;
for (u32Count = 0UL; u32Count != u32WriteBytes; u32Count++)
{
/* Wait 'til FIFO not full */
while (SCUART_GET_TX_FULL(sc))
{
;
}
/* Write 1 byte to FIFO */
sc->DAT = pu8TxBuf[u32Count];
}
}
/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SCUART_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/****************************************************************************
* @file sys.c
* @version V1.10
* @brief M251 series SYS driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SYS_Driver SYS Driver
@{
*/
/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
@{
*/
/**
* @brief Clear reset source
* @param[in] u32Src is system reset source. Including :
* - \ref SYS_RSTSTS_VBATLVRF_Msk
* - \ref SYS_RSTSTS_CPULKRF_Msk
* - \ref SYS_RSTSTS_CPURF_Msk
* - \ref SYS_RSTSTS_PMURF_Msk
* - \ref SYS_RSTSTS_SYSRF_Msk
* - \ref SYS_RSTSTS_BODRF_Msk
* - \ref SYS_RSTSTS_LVRF_Msk
* - \ref SYS_RSTSTS_WDTRF_Msk
* - \ref SYS_RSTSTS_PINRF_Msk
* - \ref SYS_RSTSTS_PORF_Msk
* @return None
* @details This function clear the selected system reset source.
*/
void SYS_ClearResetSrc(uint32_t u32Src)
{
SYS->RSTSTS |= u32Src;
}
/**
* @brief Get Brown-out detector output status
* @param None
* @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0.
* @retval 1 System voltage is lower than BOD_VL setting.
* @details This function get Brown-out detector output status.
*/
uint32_t SYS_GetBODStatus(void)
{
return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
}
/**
* @brief Get reset status register value
* @param None
* @return Reset source
* @details This function get the system reset status register value.
*/
uint32_t SYS_GetResetSrc(void)
{
return (SYS->RSTSTS);
}
/**
* @brief Check if register is locked nor not
* @param None
* @retval 0 Write-protection function is disabled.
* 1 Write-protection function is enabled.
* @details This function check register write-protection bit setting.
*/
uint32_t SYS_IsRegLocked(void)
{
return !(SYS->REGLCTL & 0x1UL);
}
/**
* @brief Get product ID
* @param None
* @return Product ID
* @details This function get product ID.
*/
uint32_t SYS_ReadPDID(void)
{
return SYS->PDID;
}
/**
* @brief Reset chip with chip reset
* @param None
* @return None
* @details This function reset chip with chip reset.
* The register write-protection function should be disabled before using this function.
*/
void SYS_ResetChip(void)
{
SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
}
/**
* @brief Reset chip with CPU reset
* @param None
* @return None
* @details This function reset CPU with CPU reset.
* The register write-protection function should be disabled before using this function.
*/
void SYS_ResetCPU(void)
{
SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
}
/**
* @brief Reset selected module
* @param[in] u32ModuleIndex is module index. Including :
* - \ref PDMA_RST
* - \ref EBI_RST
* - \ref CRC_RST
* - \ref CRPT_RST
* - \ref GPIO_RST
* - \ref TMR0_RST
* - \ref TMR1_RST
* - \ref TMR2_RST
* - \ref TMR3_RST
* - \ref ACMP01_RST
* - \ref I2C0_RST
* - \ref I2C1_RST
* - \ref QSPI0_RST
* - \ref SPI0_RST
* - \ref UART0_RST
* - \ref UART1_RST
* - \ref UART2_RST
* - \ref USBD_RST
* - \ref EADC_RST
* - \ref SC0_RST
* - \ref USCI0_RST
* - \ref USCI1_RST
* - \ref USCI2_RST
* - \ref DAC_RST
* - \ref PWM0_RST
* - \ref PWM1_RST
* - \ref BPWM0_RST
* - \ref BPWM1_RST
* - \ref OPA_RST
* - \ref PSIO_RST
* @return None
* @details This function reset selected module.
*/
void SYS_ResetModule(uint32_t u32ModuleIndex)
{
/* Generate reset signal to the corresponding module */
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24UL)) |= 1UL << (u32ModuleIndex & 0x00ffffffUL);
/* Release corresponding module from reset state */
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24UL)) &= ~(1UL << (u32ModuleIndex & 0x00ffffffUL));
}
/**
* @brief Enable and configure Brown-out detector function
* @param[in] i32Mode is reset or interrupt mode. Including :
* - \ref SYS_BODCTL_BOD_RST_EN
* - \ref SYS_BODCTL_BOD_INTERRUPT_EN
* @param[in] u32BODLevel is Brown-out voltage level. Including :
* - \ref SYS_BODCTL_BODVL_4_4V
* - \ref SYS_BODCTL_BODVL_3_7V
* - \ref SYS_BODCTL_BODVL_3_0V
* - \ref SYS_BODCTL_BODVL_2_7V
* - \ref SYS_BODCTL_BODVL_2_4V
* - \ref SYS_BODCTL_BODVL_2_0V
* - \ref SYS_BODCTL_BODVL_1_8V
* @return None
* @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
* The register write-protection function should be disabled before using this function.
*/
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
{
/* Enable Brown-out Detector function */
SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
/* Enable Brown-out interrupt or reset function */
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
/* Select Brown-out Detector threshold voltage */
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
}
/**
* @brief Disable Brown-out detector function
* @param None
* @return None
* @details This function disable Brown-out detector function.
* The register write-protection function should be disabled before using this function.
*/
void SYS_DisableBOD(void)
{
SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
}
/**
* @brief Set Power Level
* @param[in] u32PowerLevel is power level setting. Including :
* - \ref SYS_PLCTL_PLSEL_PL0
* - \ref SYS_PLCTL_PLSEL_PL2
* @return None
* @details This function select power level.
* The register write-protection function should be disabled before using this function.
*/
void SYS_SetPowerLevel(uint32_t u32PowerLevel)
{
/* Set power voltage level */
SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel);
}
/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SYS_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file timer.c
* @version V3.00
* @brief M251 series Timer Controller(Timer) driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup TIMER_Driver TIMER Driver
@{
*/
/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
@{
*/
/**
* @brief Open Timer with Operate Mode and Frequency
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Mode Operation mode. Possible options are
* - \ref TIMER_ONESHOT_MODE
* - \ref TIMER_PERIODIC_MODE
* - \ref TIMER_TOGGLE_MODE
* - \ref TIMER_CONTINUOUS_MODE
* @param[in] u32Freq Target working frequency
*
* @return Real timer working frequency
*
* @details This API is used to configure timer to operate in specified mode and frequency.
* If timer cannot work in target frequency, a closest frequency will be chose and returned.
* @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
* \ref TIMER_Start macro or program registers directly.
*/
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
{
uint32_t u32Clk = TIMER_GetModuleClock(timer);
uint32_t u32Cmpr = 0UL, u32Prescale = 0UL;
// Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0.
if (u32Freq > (u32Clk / 2UL))
{
u32Cmpr = 2UL;
}
else
{
if (u32Clk > 64000000UL)
{
u32Prescale = 7UL; // real prescaler value is 8
u32Clk >>= 3;
}
else if (u32Clk > 32000000UL)
{
u32Prescale = 3UL; // real prescaler value is 4
u32Clk >>= 2;
}
else if (u32Clk > 16000000UL)
{
u32Prescale = 1UL; // real prescaler value is 2
u32Clk >>= 1;
}
u32Cmpr = u32Clk / u32Freq;
}
timer->CTL = u32Mode | u32Prescale;
timer->CMP = u32Cmpr;
return (u32Clk / (u32Cmpr * (u32Prescale + 1UL)));
}
/**
* @brief Stop Timer Counting
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This API stops timer counting and disable all timer interrupt function.
*/
void TIMER_Close(TIMER_T *timer)
{
timer->CTL = 0UL;
timer->EXTCTL = 0UL;
}
/**
* @brief Create a specify Delay Time
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
*
* @return None
*
* @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
* @note This API overwrites the register setting of the timer used to count the delay time.
* @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
*/
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
{
uint32_t u32Clk = TIMER_GetModuleClock(timer);
uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32Clk) + 1UL;
uint32_t u32Cmpr, u32NsecPerTick;
// Clear current timer configuration/
timer->CTL = 0UL;
timer->EXTCTL = 0UL;
if (u32Clk <= 1000000UL) // min delay is 1000 us if timer clock source is <= 1 MHz
{
if (u32Usec < 1000UL)
u32Usec = 1000UL;
if (u32Usec > 1000000UL)
u32Usec = 1000000UL;
}
else
{
if (u32Usec < 100UL)
u32Usec = 100UL;
if (u32Usec > 1000000UL)
u32Usec = 1000000UL;
}
if (u32Clk <= 1000000UL)
{
u32Prescale = 0UL;
u32NsecPerTick = 1000000000UL / u32Clk;
u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
}
else
{
if (u32Clk > 64000000UL)
{
u32Prescale = 7UL; // real prescaler value is 8
u32Clk >>= 3;
}
else if (u32Clk > 32000000UL)
{
u32Prescale = 3UL; // real prescaler value is 4
u32Clk >>= 2;
}
else if (u32Clk > 16000000UL)
{
u32Prescale = 1UL; // real prescaler value is 2
u32Clk >>= 1;
}
if (u32Usec < 250UL)
{
u32Cmpr = (u32Usec * u32Clk) / 1000000UL;
}
else
{
u32NsecPerTick = 1000000000UL / u32Clk;
u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
}
}
timer->CMP = u32Cmpr;
timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
// When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
// And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
for (; u32Delay > 0UL; u32Delay--)
{
__NOP();
}
while (timer->CTL & TIMER_CTL_ACTSTS_Msk)
{
}
}
/**
* @brief Enable Timer Capture Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32CapMode Timer capture mode. Could be
* - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
* - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
* @param[in] u32Edge Timer capture trigger edge. Possible values are
* - \ref TIMER_CAPTURE_EVENT_FALLING
* - \ref TIMER_CAPTURE_EVENT_RISING
* - \ref TIMER_CAPTURE_EVENT_FALLING_RISING
* - \ref TIMER_CAPTURE_EVENT_RISING_FALLING
* - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD
* - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD
*
* @return None
*
* @details This API is used to enable timer capture function with specify capture trigger edge \n
* to get current counter value or reset counter value to 0.
* @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
*/
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
{
timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
}
/**
* @brief Select Timer Capture Source
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Src Timer capture source. Possible values are
* - \ref TIMER_CAPTURE_FROM_EXTERNAL
* - \ref TIMER_CAPTURE_FROM_INTERNAL
*
* @return None
*
* @details This API is used to select timer capture source from Tx_EXT or internal singal.
*/
void TIMER_CaptureSelect(TIMER_T *timer, uint32_t u32Src)
{
timer->CTL = (timer->CTL & (~TIMER_CTL_CAPSRC_Msk)) | u32Src;
}
/**
* @brief Disable Timer Capture Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This API is used to disable the timer capture function.
*/
void TIMER_DisableCapture(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
}
/**
* @brief Set Timer Trigger Source
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Src Timer source from timeout or capture event
*
* @return None
*
* @details This macro is used to set timer trigger source
*/
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
{
timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src;
}
/**
* @brief Set Timer Trigger Target
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Mask Timer trigger target to PWM/BPWM/DAC/EADC/PDMA
*
* @return None
*
* @details This macro is used to set timer trigger target
*/
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
{
timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask;
}
/**
* @brief Enable Timer Counter Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Edge Detection edge of counter pin. Could be ether
* - \ref TIMER_COUNTER_EVENT_FALLING, or
* - \ref TIMER_COUNTER_EVENT_RISING
*
* @return None
*
* @details This function is used to enable the timer counter function with specify detection edge.
* @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
* @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
*/
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
{
timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
}
/**
* @brief Disable Timer Counter Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This API is used to disable the timer event counter function.
*/
void TIMER_DisableEventCounter(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
}
/**
* @brief Enable Timer Frequency Counter Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32DropCount This parameter has no effect in this BSP
* @param[in] u32Timeout This parameter has no effect in this BSP
* @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE
*
* @return None
*
* @details This function is used to enable the Timer frequency counter function for
* calculate input event frequency. After enable this function, a pair of timers,
* TIMER0 and TIMER1, or TIMER2 and TIMER3 will be configured for this function.
* The mode used to calculate input event frequency is mentioned as
* "Inter Timer Trigger Mode" in Technical Reference Manual.
*/
void TIMER_EnableFreqCounter(TIMER_T *timer,
uint32_t u32DropCount,
uint32_t u32Timeout,
uint32_t u32EnableInt)
{
TIMER_T *ptimerTmp; /* store the timer base to configure compare value */
if (timer == TIMER0)
{
ptimerTmp = TIMER1;
}
else if (timer == TIMER2)
{
ptimerTmp = TIMER3;
}
else
{
ptimerTmp = 0UL ;
}
if (ptimerTmp != 0UL)
{
ptimerTmp->CMP = 0xFFFFFFUL;
ptimerTmp->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL;
timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
}
}
/**
* @brief Disable Timer Frequency Counter Function
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @brief This function is used to disable the Timer frequency counter function.
*/
void TIMER_DisableFreqCounter(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
}
/**
* @brief Get Timer Clock Frequency
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return Timer clock frequency
*
* @details This API is used to get the timer clock frequency.
* @note This API cannot return correct clock rate if timer source is from external clock input.
*/
uint32_t TIMER_GetModuleClock(TIMER_T *timer)
{
uint32_t u32Src;
const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC};
if (timer == TIMER0)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
else if (timer == TIMER1)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
else if (timer == TIMER2)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
else // Timer 3
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
if (u32Src == 2UL)
{
return (SystemCoreClock);
}
return (au32Clk[u32Src]);
}
/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group TIMER_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file timer.c
* @version V3.00
* @brief Timer PWM Controller(Timer PWM) driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
@{
*/
/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
@{
*/
/**
* @brief Get PWM Clock Frequency
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return PWM clock frequency
*
* @details This API is used to get the timer clock frequency.
* @note This API cannot return correct clock rate if timer source is from external clock input.
*/
uint32_t TPWM_GetModuleClock(TIMER_T *timer)
{
uint32_t u32Src;
const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC};
if (timer == TIMER0)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
else if (timer == TIMER1)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
else if (timer == TIMER2)
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
else // Timer 3
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
if (u32Src == 2UL)
{
return (SystemCoreClock);
}
return (au32Clk[u32Src]);
}
/**
* @brief Configure PWM Output Frequency and Duty Cycle
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Frequency Target generator frequency.
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%...
*
* @return Nearest frequency clock in nano second
*
* @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode.
* @note This API is only available if Timer PWM counter clock source is from TMRx_CLK.
*/
uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle)
{
uint32_t u32PWMClockFreq, u32TargetFreq;
uint32_t u32Prescaler = 0x100UL, u32Period, u32CMP;
u32PWMClockFreq = TPWM_GetModuleClock(timer);
/* Calculate u8PERIOD and u8PSC */
for (u32Prescaler = 1; u32Prescaler <= 0x100UL; u32Prescaler++)
{
u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency;
/* If target u32Period is larger than 0x10000, need to use a larger prescaler */
if (u32Period > 0x10000UL)
continue;
break;
}
/* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */
u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period;
/* Set PWM to auto-reload mode */
timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos);
/* Convert to real register value */
TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL));
TPWM_SET_PERIOD(timer, (u32Period - 1UL));
if (u32DutyCycle)
{
u32CMP = (u32DutyCycle * u32Period) / 100UL;
}
else
{
u32CMP = 0UL;
}
TPWM_SET_CMPDAT(timer, u32CMP);
return (u32TargetFreq);
}
/**
* @brief Enable PWM Counter
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to enable PWM generator and start counter counting.
*/
void TPWM_EnableCounter(TIMER_T *timer)
{
timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk;
}
/**
* @brief Disable PWM Generator
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit.
*/
void TPWM_DisableCounter(TIMER_T *timer)
{
timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk;
}
/**
* @brief Enable Trigger ADC
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions:
* - \ref TPWM_TRIGGER_AT_PERIOD_POINT
* - \ref TPWM_TRIGGER_AT_COMPARE_POINT
* - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT
* @return None
*
* @details This function is used to enable specified counter compare event to trigger ADC.
*/
void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition)
{
timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGSEL_Msk;
timer->PWMTRGCTL |= TIMER_PWMTRGCTL_PWMTRGEADC_Msk | (u32Condition << TIMER_PWMTRGCTL_TRGSEL_Pos);
}
/**
* @brief Disable Trigger ADC
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable counter compare event to trigger ADC.
*/
void TPWM_DisableTriggerADC(TIMER_T *timer)
{
timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_PWMTRGEADC_Msk;
}
/**
* @brief Enable Trigger DAC
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Condition The condition to trigger DAC. It could be one of following conditions:
* - \ref TPWM_TRIGGER_AT_PERIOD_POINT
* - \ref TPWM_TRIGGER_AT_COMPARE_POINT
* - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT
* @return None
*
* @details This function is used to enable specified counter compare event to trigger ADC.
*/
void TPWM_EnableTriggerDAC(TIMER_T *timer, uint32_t u32Condition)
{
timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGSEL_Msk;
timer->PWMTRGCTL |= TIMER_PWMTRGCTL_PWMTRGDAC_Msk | (u32Condition << TIMER_PWMTRGCTL_TRGSEL_Pos);
}
/**
* @brief Disable Trigger DAC
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable counter compare event to trigger ADC.
*/
void TPWM_DisableTriggerDAC(TIMER_T *timer)
{
timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_PWMTRGDAC_Msk;
}
/**
* @brief Enable Trigger PDMA
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
* @param[in] u32Condition The condition to trigger PDMA. It could be one of following conditions:
* - \ref TPWM_TRIGGER_AT_PERIOD_POINT
* - \ref TPWM_TRIGGER_AT_COMPARE_POINT
* - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT
* @return None
*
* @details This function is used to enable specified counter compare event to trigger ADC.
*/
void TPWM_EnableTriggerPDMA(TIMER_T *timer, uint32_t u32Condition)
{
timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGSEL_Msk;
timer->PWMTRGCTL |= TIMER_PWMTRGCTL_PWMTRGPDMA_Msk | (u32Condition << TIMER_PWMTRGCTL_TRGSEL_Pos);
}
/**
* @brief Disable Trigger PDMA
*
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
*
* @return None
*
* @details This function is used to disable counter compare event to trigger ADC.
*/
void TPWM_DisableTriggerPDMA(TIMER_T *timer)
{
timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_PWMTRGPDMA_Msk;
}
/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group TIMER_PWM_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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/****************************************************************************
* @file uart.c
* @version V1.00
* @brief M251 series UART driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup UART_Driver UART Driver
@{
*/
/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
@{
*/
/**
* @brief Clear UART specified interrupt flag
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32InterruptFlag The specified interrupt of UART module.
* - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt
* - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
* - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
*
* @return None
*
* @details The function is used to clear UART specified interrupt flag.
*/
void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag)
{
if (u32InterruptFlag & UART_INTSTS_SWBEINT_Msk) /* Clear Bit Error Detection Interrupt */
{
uart->FIFOSTS = UART_INTSTS_SWBEIF_Msk;
}
if (u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
{
uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk;
uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
}
if (u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
{
uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
}
if (u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
{
uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
}
if (u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */
{
uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk |
UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |
UART_WKSTS_TOUTWKF_Msk;
}
if (u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
{
uart->INTSTS = UART_INTSTS_LINIF_Msk;
uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |
UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;
}
}
/**
* @brief Disable UART interrupt
*
* @param[in] uart The pointer of the specified UART module.
*
* @return None
*
* @details The function is used to disable UART interrupt.
*/
void UART_Close(UART_T *uart)
{
uart->INTEN = 0ul;
}
/**
* @brief Disable UART auto flow control function
*
* @param[in] uart The pointer of the specified UART module.
*
* @return None
*
* @details The function is used to disable UART auto flow control.
*/
void UART_DisableFlowCtrl(UART_T *uart)
{
uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
}
/**
* @brief Disable UART specified interrupt
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32InterruptFlag The specified interrupt of UART module.
* - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
* - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
*
* @return None
*
* @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
*/
void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag)
{
/* Disable UART specified interrupt */
UART_DISABLE_INT(uart, u32InterruptFlag);
}
/**
* @brief Enable UART auto flow control function
*
* @param[in] uart The pointer of the specified UART module.
*
* @return None
*
* @details The function is used to Enable UART auto flow control.
*/
void UART_EnableFlowCtrl(UART_T *uart)
{
/* Set RTS pin output is low level active */
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
/* Set CTS pin input is low level active */
uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
/* Set RTS and CTS auto flow control enable */
uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
}
/**
* @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32InterruptFlag The specified interrupt of UART module:
* - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
* - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
*
* @return None
*
* @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
*/
void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag)
{
/* Enable UART specified interrupt */
UART_ENABLE_INT(uart, u32InterruptFlag);
}
/**
* @brief Open and set UART function
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32BaudRate The baud rate of UART module.
*
* @return None
*
* @details This function use to enable UART function and set baud-rate.
*/
void UART_Open(UART_T *uart, uint32_t u32BaudRate)
{
uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
uint32_t au32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC};
uint32_t u32Baud_Div = 0ul;
if (uart == (UART_T *)UART0)
{
/* Get UART clock source selection */
u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
}
else if (uart == (UART_T *)UART1)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
}
else if (uart == (UART_T *)UART2)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
}
else {}
/* Select UART function */
uart->FUNCSEL = UART_FUNCSEL_UART;
/* Set UART line configuration */
uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
/* Set UART Rx and RTS trigger level */
uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
/* Get PLL clock frequency if UART clock source selection is PLL */
if (u32UartClkSrcSel == 1ul)
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
}
/* Get PCLK clock frequency if UART clock source selection is PCLK */
if (u32UartClkSrcSel == 4ul)
{
/* UART Port as UART0 or UART1 */
if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2))
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq();
}
else /* UART Port as UART1*/
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq();
}
}
/* Set UART baud rate */
if (u32BaudRate != 0ul)
{
u32Baud_Div = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate);
if (u32Baud_Div > 0xFFFFul)
{
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate));
}
else
{
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
}
}
}
/**
* @brief Read UART data
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
* @param[in] u32ReadBytes The the read bytes number of data.
*
* @return u32Count Receive byte count
*
* @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
*/
uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
{
uint32_t u32Count, u32DelayNum;
uint32_t u32Exit = 0ul;
for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
{
u32DelayNum = 0ul;
while (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
{
u32DelayNum++;
if (u32DelayNum >= 0x40000000ul)
{
u32Exit = 1ul;
break;
}
else
{
}
}
if (u32Exit == 1ul)
{
break;
}
else
{
pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */
}
}
return u32Count;
}
/**
* @brief Set UART line configuration
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32BaudRate The register value of baudrate of UART module.
* If u32BaudRate = 0, UART baudrate will not change.
* @param[in] u32DataWidth The data length of UART module.
* - \ref UART_WORD_LEN_5
* - \ref UART_WORD_LEN_6
* - \ref UART_WORD_LEN_7
* - \ref UART_WORD_LEN_8
* @param[in] u32Parity The parity setting (none/odd/even/mark/space) of UART module.
* - \ref UART_PARITY_NONE
* - \ref UART_PARITY_ODD
* - \ref UART_PARITY_EVEN
* - \ref UART_PARITY_MARK
* - \ref UART_PARITY_SPACE
* @param[in] u32StopBits The stop bit length (1/1.5/2 bit) of UART module.
* - \ref UART_STOP_BIT_1
* - \ref UART_STOP_BIT_1_5
* - \ref UART_STOP_BIT_2
*
* @return None
*
* @details This function use to config UART line setting.
*/
void UART_SetLine_Config(UART_T *uart, uint32_t u32BaudRate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
{
uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
uint32_t au32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0, __LIRC};
uint32_t u32Baud_Div = 0ul;
if (uart == (UART_T *)UART0)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
}
else if (uart == (UART_T *)UART1)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
}
else if (uart == (UART_T *)UART2)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
}
else {}
/* Get PLL clock frequency if UART clock source selection is PLL */
if (u32UartClkSrcSel == 1ul)
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
}
/* Get PCLK clock frequency if UART clock source selection is PCLK */
if (u32UartClkSrcSel == 4ul)
{
if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2))
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq();
}
else /* UART Port as UART1*/
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq();
}
}
/* Set UART baud rate */
if (u32BaudRate != 0ul)
{
u32Baud_Div = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate);
if (u32Baud_Div > 0xFFFFul)
{
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate));
}
else
{
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
}
}
/* Set UART line configuration */
uart->LINE = u32DataWidth | u32Parity | u32StopBits;
}
/**
* @brief Set Rx timeout count
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32TOC Rx timeout counter.
*
* @return None
*
* @details This function use to set Rx timeout count.
*/
void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC)
{
/* Set time-out interrupt comparator */
uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
/* Set time-out counter enable */
uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
}
/**
* @brief Select and configure IrDA function
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32BuadRate The baud rate of UART module.
* @param[in] u32Direction The direction of UART module in IrDA mode:
* - \ref UART_IRDA_TXEN
* - \ref UART_IRDA_RXEN
*
* @return None
*
* @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
*/
void UART_SelectIrDAMode(UART_T *uart, uint32_t u32BuadRate, uint32_t u32Direction)
{
uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
uint32_t au32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC};
uint32_t u32Baud_Div;
/* Select IrDA function mode */
uart->FUNCSEL = UART_FUNCSEL_IrDA;
if (uart == UART0)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
}
else if (uart == UART1)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
}
else if (uart == UART2)
{
/* Get UART clock source selection */
u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos;
/* Get UART clock divider number */
u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos;
}
else
{
}
/* Get PLL clock frequency if UART clock source selection is PLL */
if (u32UartClkSrcSel == 1ul)
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
}
/* Get PCLK clock frequency if UART clock source selection is PCLK */
if (u32UartClkSrcSel == 4ul)
{
if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2))
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq();
}
else /* UART Port as UART1*/
{
au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq();
}
}
/* Set UART IrDA baud rate in mode 0 */
if (u32BuadRate != 0ul)
{
u32Baud_Div = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BuadRate);
if (u32Baud_Div < 0xFFFFul)
{
uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
}
else
{
}
}
/* Configure IrDA relative settings */
if (u32Direction == UART_IRDA_RXEN)
{
uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/
uart->IRDA &= ~UART_IRDA_TXEN_Msk;
}
else
{
uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/
uart->IRDA |= UART_IRDA_TXEN_Msk;
}
}
/**
* @brief Select and configure RS485 function
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32Mode The operation mode(NMM/AUD/AAD).
* - \ref UART_ALTCTL_RS485NMM_Msk
* - \ref UART_ALTCTL_RS485AUD_Msk
* - \ref UART_ALTCTL_RS485AAD_Msk
* @param[in] u32Addr The RS485 address.
*
* @return None
*
* @details The function is used to set RS485 relative setting.
*/
void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr)
{
/* Select UART RS485 function mode */
uart->FUNCSEL = UART_FUNCSEL_RS485;
/* Set RS585 configuration */
uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
}
/**
* @brief Select and configure LIN function
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] u32Mode The LIN direction :
* - \ref UART_ALTCTL_LINTXEN_Msk
* - \ref UART_ALTCTL_LINRXEN_Msk
* @param[in] u32BreakLength The break field length.
*
* @return None
*
* @details The function is used to set LIN relative setting.
*/
void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength)
{
/* Select LIN function mode */
uart->FUNCSEL = UART_FUNCSEL_LIN;
/* Select LIN function setting : Tx enable, Rx enable and break field length */
uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
}
/**
* @brief Write UART data
*
* @param[in] uart The pointer of the specified UART module.
* @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
* @param[out] u32WriteBytes The byte number of data.
*
* @return u32Count transfer byte count
*
* @details The function is to write data into TX buffer to transmit data by UART.
*/
uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
{
uint32_t u32Count, u32DelayNum;
uint32_t u32Exit = 0ul;
for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
{
u32DelayNum = 0ul;
while ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0ul) /* Wait Tx empty and Time-out manner */
{
u32DelayNum++;
if (u32DelayNum >= 0x40000000ul)
{
u32Exit = 1ul;
break;
}
else
{
}
}
if (u32Exit == 1ul)
{
break;
}
else
{
uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
}
}
return u32Count;
}
/**
* @brief Select Single Wire mode function
*
* @param[in] uart The pointer of the specified UART module.
*
* @return None
*
* @details The function is used to select Single Wire mode.
*/
void UART_SelectSingleWireMode(UART_T *uart)
{
/* Select UART SingleWire function mode */
uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE);
}
/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group UART_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/src/usbd.c Normal file
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@@ -0,0 +1,784 @@
/**************************************************************************//**
* @file usbd.c
* @version V0.10
* @brief M251 series USBD driver source file
*
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include <string.h>
#include "NuMicro.h"
#if 0
#define DBG_PRINTF printf
#else
#define DBG_PRINTF(...)
#endif
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup USBD_Driver USBD Driver
@{
*/
/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
@{
*/
/* Global variables for Control Pipe */
uint8_t g_USBD_au8SetupPacket[8] = {0u}; /*!< Setup packet buffer */
volatile uint8_t g_USBD_u8RemoteWakeupEn = 0u; /*!< Remote wake up function enable flag */
/**
* @cond HIDDEN_SYMBOLS
*/
static volatile uint8_t *s_USBD_pu8CtrlInPointer = 0ul;
static volatile uint8_t *s_USBD_pu8CtrlOutPointer = 0ul;
static volatile uint32_t s_USBD_u32CtrlInSize = 0ul;
static volatile uint32_t s_USBD_u32CtrlOutSize = 0ul;
static volatile uint32_t s_USBD_u32CtrlOutSizeLimit = 0ul;
static volatile uint32_t s_USBD_u32UsbAddr = 0ul;
static volatile uint32_t s_USBD_u32UsbConfig = 0ul;
static volatile uint32_t s_USBD_u32CtrlMaxPktSize = 8ul;
static volatile uint32_t s_USBD_u32UsbAltInterface = 0ul;
static volatile uint8_t s_USBD_u8CtrlInZeroFlag = 0ul;
/**
* @endcond
*/
const S_USBD_INFO_T *g_USBD_sINFO; /*!< A pointer for USB information structure */
VENDOR_REQ g_USBD_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */
CLASS_REQ g_USBD_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */
SET_INTERFACE_REQ g_USBD_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */
SET_CONFIG_CB g_USBD_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */
uint32_t g_USBD_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */
/**
* @brief This function makes USBD module to be ready to use
*
* @param[in] param The structure of USBD information.
* @param[in] pfnClassReq USB Class request callback function.
* @param[in] pfnSetInterface USB Set Interface request callback function.
*
* @return None
*
* @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
*/
void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
{
g_USBD_sINFO = param;
g_USBD_pfnClassRequest = pfnClassReq;
g_USBD_pfnSetInterface = pfnSetInterface;
/* get EP0 maximum packet size */
s_USBD_u32CtrlMaxPktSize = g_USBD_sINFO->gu8DevDesc[7];
/* Initial USB engine */
#ifdef SUPPORT_LPM
USBD->ATTR = 0x7D0UL | USBD_LPMACK;
#else
USBD->ATTR = 0x7D0UL;
#endif
/* Force SE0 */
USBD_SET_SE0();
}
/**
* @brief This function makes USB host to recognize the device
*
* @param None
*
* @return None
*
* @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
*/
void USBD_Start(void)
{
/* Disable software-disconnect function */
USBD_CLR_SE0();
/* Clear USB-related interrupts before enable interrupt */
USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
/* Enable USB-related interrupts. */
USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
}
/**
* @brief Get the received SETUP packet
*
* @param[in] buf A buffer pointer used to store 8-byte SETUP packet.
*
* @return None
*
* @details Store SETUP packet to a user-specified buffer.
*
*/
void USBD_GetSetupPacket(uint8_t *buf)
{
USBD_MemCopy(buf, g_USBD_au8SetupPacket, 8ul);
}
/**
* @brief Process SETUP packet
*
* @param None
*
* @return None
*
* @details Parse SETUP packet and perform the corresponding action.
*
*/
void USBD_ProcessSetupPacket(void)
{
/* Get SETUP packet from USB buffer */
USBD_MemCopy(g_USBD_au8SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul);
/* Check the request type */
switch (g_USBD_au8SetupPacket[0] & 0x60ul)
{
case REQ_STANDARD: /* Standard */
{
USBD_StandardRequest();
break;
}
case REQ_CLASS: /* Class */
{
if (g_USBD_pfnClassRequest != NULL)
{
g_USBD_pfnClassRequest();
}
break;
}
case REQ_VENDOR: /* Vendor */
{
if (g_USBD_pfnVendorRequest != NULL)
{
g_USBD_pfnVendorRequest();
}
break;
}
default: /* reserved */
{
/* Setup error, stall the device */
USBD_SET_EP_STALL(EP0);
USBD_SET_EP_STALL(EP1);
break;
}
}
}
/**
* @brief Process GetDescriptor request
*
* @param None
*
* @return None
*
* @details Parse GetDescriptor request and perform the corresponding action.
*
*/
void USBD_GetDescriptor(void)
{
uint32_t u32Len;
u32Len = 0ul;
u32Len = g_USBD_au8SetupPacket[7];
u32Len <<= 8ul;
u32Len += g_USBD_au8SetupPacket[6];
switch (g_USBD_au8SetupPacket[3])
{
/* Get Device Descriptor */
case DESC_DEVICE:
{
u32Len = USBD_Minimum(u32Len, LEN_DEVICE);
DBG_PRINTF("Get device desc, %d\n", u32Len);
USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8DevDesc, u32Len);
break;
}
/* Get Configuration Descriptor */
case DESC_CONFIG:
{
uint32_t u32TotalLen;
DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen);
u32TotalLen = g_USBD_sINFO->gu8ConfigDesc[3];
u32TotalLen = g_USBD_sINFO->gu8ConfigDesc[2] + (u32TotalLen << 8U);
DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen);
u32Len = USBD_Minimum(u32Len, u32TotalLen);
DBG_PRINTF("Minimum len %d\n", u32Len);
USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8ConfigDesc, u32Len);
break;
}
/* Get BOS Descriptor */
case DESC_BOS:
{
uint32_t u32TotalLen;
u32TotalLen = g_USBD_sINFO->gu8BosDesc[3];
u32TotalLen = g_USBD_sINFO->gu8BosDesc[2] + (u32TotalLen << 8ul);
DBG_PRINTF("Get BOS desc len %d, acture len %d\n", u32Len, u32TotalLen);
u32Len = USBD_Minimum(u32Len, u32TotalLen);
DBG_PRINTF("Minimum len %d\n", u32Len);
USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8BosDesc, u32Len);
break;
}
/* Get HID Descriptor */
case DESC_HID:
{
/* CV3.0 HID Class Descriptor Test,
Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */
u32Len = USBD_Minimum(u32Len, LEN_HID);
DBG_PRINTF("Get HID desc, %d\n", u32Len);
u32ConfigDescOffset = g_USBD_sINFO->gu32ConfigHidDescIdx[g_USBD_au8SetupPacket[4]];
USBD_PrepareCtrlIn((uint8_t *)&g_USBD_sINFO->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
break;
}
/* Get Report Descriptor */
case DESC_HID_RPT:
{
DBG_PRINTF("Get HID report, %d\n", u32Len);
u32Len = USBD_Minimum(u32Len, g_USBD_sINFO->gu32HidReportSize[g_USBD_au8SetupPacket[4]]);
USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8HidReportDesc[g_USBD_au8SetupPacket[4]], u32Len);
break;
}
/* Get String Descriptor */
case DESC_STRING:
{
/* Get String Descriptor */
if (g_USBD_au8SetupPacket[2] < 4ul)
{
u32Len = USBD_Minimum(u32Len, g_USBD_sINFO->gu8StringDesc[g_USBD_au8SetupPacket[2]][0]);
DBG_PRINTF("Get string desc %d\n", u32Len);
USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8StringDesc[g_USBD_au8SetupPacket[2]], u32Len);
break;
}
else
{
/* Not support. Reply STALL. */
USBD_SET_EP_STALL(EP0);
USBD_SET_EP_STALL(EP1);
DBG_PRINTF("Unsupported string desc (%d). Stall ctrl pipe.\n", g_USBD_au8SetupPacket[2]);
break;
}
}
default:
/* Not support. Reply STALL. */
USBD_SET_EP_STALL(EP0);
USBD_SET_EP_STALL(EP1);
DBG_PRINTF("Unsupported get desc type. stall ctrl pipe\n");
break;
}
}
/**
* @brief Process standard request
*
* @param None
*
* @return None
*
* @details Parse standard request and perform the corresponding action.
*
*/
void USBD_StandardRequest(void)
{
DBG_PRINTF("USBD_StandardRequest\n");
/* clear global variables for new request */
s_USBD_pu8CtrlInPointer = 0ul;
s_USBD_u32CtrlInSize = 0ul;
if (g_USBD_au8SetupPacket[0] & 0x80ul) /* request data transfer direction */
{
/* Device to host */
switch (g_USBD_au8SetupPacket[1])
{
case GET_CONFIGURATION:
{
/* Return current configuration setting */
/* Data stage */
M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)s_USBD_u32UsbConfig;
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 1ul);
/* Status stage */
USBD_PrepareCtrlOut(0, 0ul);
DBG_PRINTF("Get configuration\n");
break;
}
case GET_DESCRIPTOR:
{
USBD_GetDescriptor();
USBD_PrepareCtrlOut(0, 0ul); /* For status stage */
break;
}
case GET_INTERFACE:
{
/* Return current interface setting */
/* Data stage */
M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)s_USBD_u32UsbAltInterface;
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 1ul);
/* Status stage */
USBD_PrepareCtrlOut(0, 0ul);
DBG_PRINTF("Get interface\n");
break;
}
case GET_STATUS:
{
/* Device */
if (g_USBD_au8SetupPacket[0] == 0x80ul)
{
uint8_t u8Tmp;
u8Tmp = (uint8_t)0ul;
if (g_USBD_sINFO->gu8ConfigDesc[7] & 0x40ul) u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered. */
if (g_USBD_sINFO->gu8ConfigDesc[7] & 0x20) u8Tmp |= (uint8_t)(g_USBD_u8RemoteWakeupEn << 1ul); /* Remote wake up */
M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp;
}
/* Interface */
else if (g_USBD_au8SetupPacket[0] == 0x81ul)
M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)0ul;
/* Endpoint */
else if (g_USBD_au8SetupPacket[0] == 0x82ul)
{
uint8_t ep = (uint8_t)g_USBD_au8SetupPacket[4] & 0xFul;
M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul);
}
M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = (uint8_t)0ul;
/* Data stage */
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 2ul);
/* Status stage */
USBD_PrepareCtrlOut(0, 0ul);
DBG_PRINTF("Get status\n");
break;
}
default:
{
/* Setup error, stall the device */
USBD_SET_EP_STALL(EP0);
USBD_SET_EP_STALL(EP1);
DBG_PRINTF("Unknown request. stall ctrl pipe.\n");
break;
}
}
}
else
{
/* Host to device */
switch (g_USBD_au8SetupPacket[1])
{
case CLEAR_FEATURE:
{
if (g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT)
{
uint32_t epNum, i;
/* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
a flag: g_USBD_u32EpStallLock is added to support it */
epNum = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFul);
for (i = 0ul; i < USBD_MAX_EP; i++)
{
if (((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_USBD_u32EpStallLock & (1ul << i)) == 0ul))
{
USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
DBG_PRINTF("Clr stall ep%d %x\n", i, USBD->EP[i].CFGP);
}
}
}
else if (g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
g_USBD_u8RemoteWakeupEn = (uint8_t)0;
/* Status stage */
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
DBG_PRINTF("Clear feature op %d\n", g_USBD_au8SetupPacket[2]);
break;
}
case SET_ADDRESS:
{
s_USBD_u32UsbAddr = g_USBD_au8SetupPacket[2];
DBG_PRINTF("Set addr to %d\n", s_USBD_u32UsbAddr);
/* DATA IN for end of setup */
/* Status Stage */
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
break;
}
case SET_CONFIGURATION:
{
s_USBD_u32UsbConfig = g_USBD_au8SetupPacket[2];
if (g_USBD_pfnSetConfigCallback)
g_USBD_pfnSetConfigCallback();
/* Status stage */
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
DBG_PRINTF("Set config to %d\n", s_USBD_u32UsbConfig);
break;
}
case SET_FEATURE:
{
if (g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT)
{
USBD_SetStall((uint8_t)(g_USBD_au8SetupPacket[4] & 0xFul));
DBG_PRINTF("Set feature. stall ep %d\n", g_USBD_au8SetupPacket[4] & 0xFul);
}
else if (g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
{
g_USBD_u8RemoteWakeupEn = (uint8_t)1ul;
DBG_PRINTF("Set feature. enable remote wakeup\n");
}
/* Status stage */
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
break;
}
case SET_INTERFACE:
{
s_USBD_u32UsbAltInterface = g_USBD_au8SetupPacket[2];
if (g_USBD_pfnSetInterface != NULL)
g_USBD_pfnSetInterface();
/* Status stage */
USBD_SET_DATA1(EP0);
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
DBG_PRINTF("Set interface to %d\n", s_USBD_u32UsbAltInterface);
break;
}
default:
{
/* Setup error, stall the device */
USBD_SET_EP_STALL(EP0);
USBD_SET_EP_STALL(EP1);
DBG_PRINTF("Unsupported request. stall ctrl pipe.\n");
break;
}
}
}
}
/**
* @brief Prepare the first Control IN pipe
*
* @param[in] pu8Buf The pointer of data sent to USB host.
* @param[in] u32Size The IN transfer size.
*
* @return None
*
* @details Prepare data for Control IN transfer.
*
*/
void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
{
DBG_PRINTF("Prepare Ctrl In %d\n", u32Size);
if (u32Size > s_USBD_u32CtrlMaxPktSize)
{
// Data size > MXPLD
s_USBD_pu8CtrlInPointer = pu8Buf + s_USBD_u32CtrlMaxPktSize;
s_USBD_u32CtrlInSize = u32Size - s_USBD_u32CtrlMaxPktSize;
USBD_SET_DATA1(EP0);
USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, s_USBD_u32CtrlMaxPktSize);
USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize);
}
else
{
// Data size <= MXPLD
s_USBD_pu8CtrlInPointer = 0ul;
s_USBD_u32CtrlInSize = 0ul;
if (u32Size == s_USBD_u32CtrlMaxPktSize)
{
s_USBD_u8CtrlInZeroFlag = (uint8_t)1ul;
}
USBD_SET_DATA1(EP0);
USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size);
USBD_SET_PAYLOAD_LEN(EP0, u32Size);
}
}
/**
* @brief Repeat Control IN pipe
*
* @param None
*
* @return None
*
* @details This function processes the remained data of Control IN transfer.
*
*/
void USBD_CtrlIn(void)
{
DBG_PRINTF("Ctrl In Ack. residue %d\n", s_USBD_u32CtrlInSize);
if (s_USBD_u32CtrlInSize)
{
// Process remained data
if (s_USBD_u32CtrlInSize > s_USBD_u32CtrlMaxPktSize)
{
// Data size > MXPLD
USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlMaxPktSize);
USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize);
s_USBD_pu8CtrlInPointer += s_USBD_u32CtrlMaxPktSize;
s_USBD_u32CtrlInSize -= s_USBD_u32CtrlMaxPktSize;
}
else
{
// Data size <= MXPLD
USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlInSize);
USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlInSize);
if (s_USBD_u32CtrlInSize == s_USBD_u32CtrlMaxPktSize)
{
s_USBD_u8CtrlInZeroFlag = (uint8_t)1ul;
}
s_USBD_pu8CtrlInPointer = 0ul;
s_USBD_u32CtrlInSize = 0ul;
}
}
else // No more data for IN token
{
// In ACK for Set address
if ((g_USBD_au8SetupPacket[0] == REQ_STANDARD) && (g_USBD_au8SetupPacket[1] == SET_ADDRESS))
{
if ((USBD_GET_ADDR() != s_USBD_u32UsbAddr) && (USBD_GET_ADDR() == 0ul))
{
USBD_SET_ADDR(s_USBD_u32UsbAddr);
}
}
/* For the case of data size is integral times maximum packet size */
if (s_USBD_u8CtrlInZeroFlag)
{
USBD_SET_PAYLOAD_LEN(EP0, 0ul);
s_USBD_u8CtrlInZeroFlag = (uint8_t)0ul;
}
DBG_PRINTF("Ctrl In done.\n");
}
}
/**
* @brief Prepare the first Control OUT pipe
*
* @param[in] pu8Buf The pointer of data received from USB host.
* @param[in] u32Size The OUT transfer size.
*
* @return None
*
* @details This function is used to prepare the first Control OUT transfer.
*
*/
void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
{
s_USBD_pu8CtrlOutPointer = pu8Buf;
s_USBD_u32CtrlOutSize = 0ul;
s_USBD_u32CtrlOutSizeLimit = u32Size;
USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize);
}
/**
* @brief Repeat Control OUT pipe
*
* @param None
*
* @return None
*
* @details This function processes the successive Control OUT transfer.
*
*/
void USBD_CtrlOut(void)
{
uint32_t u32Size;
DBG_PRINTF("Ctrl Out Ack %d\n", s_USBD_u32CtrlOutSize);
if (s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit)
{
u32Size = USBD_GET_PAYLOAD_LEN(EP1);
USBD_MemCopy((uint8_t *)s_USBD_pu8CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size);
s_USBD_pu8CtrlOutPointer += u32Size;
s_USBD_u32CtrlOutSize += u32Size;
if (s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit)
USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize);
}
}
/**
* @brief Reset software flags
*
* @param None
*
* @return None
*
* @details This function resets all variables for protocol and resets USB device address to 0.
*
*/
void USBD_SwReset(void)
{
uint32_t i;
// Reset all variables for protocol
s_USBD_pu8CtrlInPointer = 0ul;
s_USBD_u32CtrlInSize = 0ul;
s_USBD_pu8CtrlOutPointer = 0ul;
s_USBD_u32CtrlOutSize = 0ul;
s_USBD_u32CtrlOutSizeLimit = 0ul;
g_USBD_u32EpStallLock = 0ul;
memset(g_USBD_au8SetupPacket, 0, 8ul);
/* Reset PID DATA0 */
for (i = 0ul; i < USBD_MAX_EP; i++)
USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
// Reset USB device address
USBD_SET_ADDR(0ul);
}
/**
* @brief USBD Set Vendor Request
*
* @param[in] pfnVendorReq Vendor Request Callback Function
*
* @return None
*
* @details This function is used to set USBD vendor request callback function
*/
void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
{
g_USBD_pfnVendorRequest = pfnVendorReq;
}
/**
* @brief The callback function which called when get SET CONFIGURATION request
*
* @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request
*
* @return None
*
* @details This function is used to set the callback function which will be called at SET CONFIGURATION request.
*/
void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
{
g_USBD_pfnSetConfigCallback = pfnSetConfigCallback;
}
/**
* @brief EP stall lock function to avoid stall clear by USB SET FEATURE request.
*
* @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked
*
* @return None
*
* @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request.
* If ep stall locked, user needs to reset USB device or re-configure device to clear it.
*/
void USBD_LockEpStall(uint32_t u32EpBitmap)
{
g_USBD_u32EpStallLock = u32EpBitmap;
}
/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group USBD_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

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board/Nuvoton_M251/StdDriver/src/usci_i2c.c Normal file
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