244 lines
11 KiB
C
244 lines
11 KiB
C
/*
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* The Clear BSD License
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_common.h"
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#include "fsl_debug_console.h"
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#include "board.h"
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#include "tos_k.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* Get debug console frequency. */
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uint32_t BOARD_DebugConsoleSrcFreq(void)
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{
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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{
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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else
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{
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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return freq;
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}
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void SysTick_Handler(void)
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{
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if (tos_knl_is_running())
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{
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tos_knl_irq_enter();
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tos_tick_handler();
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tos_knl_irq_leave();
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}
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}
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/* Initialize debug console. */
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void BOARD_InitDebugConsole(void)
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{
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uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
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DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
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}
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/* MPU configuration. */
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void BOARD_ConfigMPU(void)
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{
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
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SCB_DisableICache();
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}
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
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SCB_DisableDCache();
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
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* API in core_cm7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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* Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner noncache
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* 1 1 0 0 Normal shareable outer and inner noncache
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* 1 0 1 1 Normal not shareable outer and inner write back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
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*/
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/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 2 setting */
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Setting Memory with Normal type, not shareable, outer/inner write back. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
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#else
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/* Setting Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
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#endif
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/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
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MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
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/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
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/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
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/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
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* accessed by cache can be put here */
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/* Memory with Normal type, not shareable, non-cacheable */
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MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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#if defined(USE_RAM_VECTOR_TABLE)
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/* <20><><EFBFBD><EFBFBD>SDRAM<41>汾<EFBFBD><E6B1BE><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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CopyAndUseRAMVectorTable();
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#endif
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}
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#if defined(USE_RAM_VECTOR_TABLE)
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/**
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* @brief <20><><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>ݵ<EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD><C3B8>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* @note <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>nor_sdram_code<64>汾<EFBFBD>ij<EFBFBD><C4B3><EFBFBD><EFBFBD><EFBFBD>оƬ<D0BE>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>
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ʹ<><CAB9>SDRAM<41><4D><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϲ<D0B6><CFB2><EFBFBD>ʱCPU<50><55><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>FLASH
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* @retval <20><>
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*/
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void CopyAndUseRAMVectorTable(void)
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{
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/* <20><><EFBFBD>ݲ<EFBFBD>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>ƽ̨<C6BD>ķ<EFBFBD>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>õ<EFBFBD>VECTOR_TABLE <20><> VECTOR_RAM<41>ĵ<EFBFBD>ַ*/
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#if defined(__CC_ARM)
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/* ROM<4F><4D>RAM<41>е<EFBFBD><D0B5>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>MDK<44><4B>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFB7A8> */
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extern uint32_t Image$$VECTOR_ROM$$Base[];
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extern uint32_t Image$$VECTOR_RAM$$Base[];
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/* SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>VECTOR_RAMռ<4D>õĿռ<C4BF> */
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extern uint32_t Image$$ER_m_ram_text$$Base[];
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#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
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#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
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#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$ER_m_ram_text$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
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#elif defined(__ICCARM__)
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/* ROM<4F><4D>RAM<41>е<EFBFBD><D0B5>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD>С<EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD>ַ<EFBFBD><D6B7>IAR<41><52>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFB7A8> */
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extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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#elif defined(__GNUC__)
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/* <20><>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>GCC<43><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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extern uint32_t __VECTOR_TABLE[];
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extern uint32_t __VECTOR_RAM[];
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extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
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uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
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#endif /* defined(__CC_ARM) */
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uint32_t n;
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uint32_t irqMaskValue;
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irqMaskValue = DisableGlobalIRQ();
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if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
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{
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/* <20><><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM */
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for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
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{
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__VECTOR_RAM[n] = __VECTOR_TABLE[n];
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}
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/* <20><><EFBFBD><EFBFBD>Cortex-M<>ں˵<DABA>VTOR<4F>Ĵ<EFBFBD><C4B4><EFBFBD>ָ<EFBFBD><D6B8>RAM<41>汾<EFBFBD><E6B1BE><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>VTOR<4F>Ĵ<EFBFBD><C4B4><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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*/
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SCB->VTOR = (uint32_t)__VECTOR_RAM;
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}
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EnableGlobalIRQ(irqMaskValue);
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
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exception return operation might vector to incorrect interrupt */
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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#endif
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