add NXP Imx RT1052 support
add NXP RT1052 support
This commit is contained in:
supowang
50
board/FIRE_NXP_IMXRT1052/BSP/Inc/board.h
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50
board/FIRE_NXP_IMXRT1052/BSP/Inc/board.h
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@@ -0,0 +1,50 @@
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#include "clock_config.h"
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#include "fsl_common.h"
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#include "fsl_gpio.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief The board name */
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#define BOARD_NAME "YH i.MX RT1052 Board"
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/* <20><><EFBFBD>Դ<EFBFBD><D4B4>ڶ<EFBFBD><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ */
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#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
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#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
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#define BOARD_DEBUG_UART_INSTANCE 1U
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#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
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#define BOARD_UART_IRQ LPUART1_IRQn
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#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
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#ifndef BOARD_DEBUG_UART_BAUDRATE
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#define BOARD_DEBUG_UART_BAUDRATE (115200U)
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#endif /* BOARD_DEBUG_UART_BAUDRATE */
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/*! @brief FLASH<53>ռ<EFBFBD><D5BC><EFBFBD>С */
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#define BOARD_FLASH_SIZE (0x2000000U)
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus */
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/*******************************************************************************
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* API
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******************************************************************************/
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uint32_t BOARD_DebugConsoleSrcFreq(void);
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void BOARD_InitDebugConsole(void);
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void BOARD_ConfigMPU(void);
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void CopyAndUseRAMVectorTable(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus */
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#endif /* _BOARD_H_ */
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136
board/FIRE_NXP_IMXRT1052/BSP/Inc/bsp_led.h
Normal file
136
board/FIRE_NXP_IMXRT1052/BSP/Inc/bsp_led.h
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@@ -0,0 +1,136 @@
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#ifndef __BSP_LED_H
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#define __BSP_LED_H
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#include "fsl_common.h"
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/*********************************************************
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* LED GPIO<49>˿ڡ<CBBF><DAA1><EFBFBD><EFBFBD>źż<C5BA>IOMUXC<58><43><EFBFBD>ú궨<C3BA><EAB6A8>
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*********************************************************/
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#define CORE_BOARD_LED_GPIO GPIO1
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#define CORE_BOARD_LED_GPIO_PIN (9U)
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#define CORE_BOARD_LED_IOMUXC IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
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#define RGB_RED_LED_GPIO GPIO1
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#define RGB_RED_LED_GPIO_PIN (24U)
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#define RGB_RED_LED_IOMUXC IOMUXC_GPIO_AD_B1_08_GPIO1_IO24
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#define RGB_GREEN_LED_GPIO GPIO1
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#define RGB_GREEN_LED_GPIO_PIN (25U)
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#define RGB_GREEN_LED_IOMUXC IOMUXC_GPIO_AD_B1_09_GPIO1_IO25
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#define RGB_BLUE_LED_GPIO GPIO1
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#define RGB_BLUE_LED_GPIO_PIN (10U)
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#define RGB_BLUE_LED_IOMUXC IOMUXC_GPIO_AD_B0_10_GPIO1_IO10
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#define LED_DELAY_COUNT 70000000
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/** <20><><EFBFBD><EFBFBD>LED<45><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĺ꣬
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* LED<45>͵<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ON=0<><30>OFF=1
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* <20><>LED<45>ߵ<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD>Ѻ<EFBFBD><D1BA><EFBFBD><EFBFBD>ó<EFBFBD>ON=1 <20><>OFF=0 <20><><EFBFBD><EFBFBD>
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*/
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#define ON 1
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#define OFF 0
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/* ʹ<>ñ<EFBFBD><EFBFBD>Ĺ̼<C4B9><CCBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO
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ʹ<>÷<EFBFBD><C3B7><EFBFBD><EFBFBD><EFBFBD>CORE_BOARD_LED(ON); */
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#define CORE_BOARD_LED(a) if (a) \
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GPIO_PinWrite(CORE_BOARD_LED_GPIO, CORE_BOARD_LED_GPIO_PIN, 0U);\
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else \
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GPIO_PinWrite(CORE_BOARD_LED_GPIO, CORE_BOARD_LED_GPIO_PIN, 1U);
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#define RGB_RED_LED(a) if (a) \
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GPIO_PinWrite(RGB_RED_LED_GPIO, RGB_RED_LED_GPIO_PIN, 0U);\
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else \
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GPIO_PinWrite(RGB_RED_LED_GPIO, RGB_RED_LED_GPIO_PIN, 1U);
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#define RGB_GREEN_LED(a) if (a) \
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GPIO_PinWrite(RGB_RGB_GREEN_LED_GPIO, RGB_RGB_GREEN_LED_GPIO_PIN, 0U);\
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else \
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GPIO_PinWrite(RGB_GREEN_LED_GPIO, RGB_GREEN_LED_GPIO_PIN, 1U);
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#define RGB_BLUE_LED(a) if (a) \
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GPIO_PinWrite(RGB_BLUE_LED_GPIO, RGB_BLUE_LED_GPIO_PIN, 0U);\
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else \
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GPIO_PinWrite(RGB_BLUE_LED_GPIO, RGB_BLUE_LED_GPIO_PIN, 1U);
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/* ֱ<>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO */
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#define digitalHi(p,i) {p->DR |= (1U << i);} //<2F><><EFBFBD><EFBFBD>Ϊ<EFBFBD>ߵ<EFBFBD>ƽ
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#define digitalLo(p,i) {p->DR &= ~(1U << i);} //<2F><><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ
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#define digitalToggle(p,i) {p->DR ^= (1U<<i);} //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת״̬
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IO<49>ĺ<EFBFBD> */
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#define CORE_BOARD_LED_TOGGLE digitalToggle(CORE_BOARD_LED_GPIO,CORE_BOARD_LED_GPIO_PIN)
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#define CORE_BOARD_LED_OFF digitalHi(CORE_BOARD_LED_GPIO,CORE_BOARD_LED_GPIO_PIN)
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#define CORE_BOARD_LED_ON digitalLo(CORE_BOARD_LED_GPIO,CORE_BOARD_LED_GPIO_PIN)
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#define RGB_RED_LED_TOGGLE digitalToggle(RGB_RED_LED_GPIO,RGB_RED_LED_GPIO_PIN)
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#define RGB_RED_LED_OFF digitalHi(RGB_RED_LED_GPIO,RGB_RED_LED_GPIO_PIN)
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#define RGB_RED_LED_ON digitalLo(RGB_RED_LED_GPIO,RGB_RED_LED_GPIO_PIN)
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#define RGB_GREEN_LED_TOGGLE digitalToggle(RGB_GREEN_LED_GPIO,RGB_GREEN_LED_GPIO_PIN)
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#define RGB_GREEN_LED_OFF digitalHi(RGB_GREEN_LED_GPIO,RGB_GREEN_LED_GPIO_PIN)
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#define RGB_GREEN_LED_ON digitalLo(RGB_GREEN_LED_GPIO,RGB_GREEN_LED_GPIO_PIN)
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#define RGB_BLUE_LED_TOGGLE digitalToggle(RGB_BLUE_LED_GPIO,RGB_BLUE_LED_GPIO_PIN)
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#define RGB_BLUE_LED_OFF digitalHi(RGB_BLUE_LED_GPIO,RGB_BLUE_LED_GPIO_PIN)
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#define RGB_BLUE_LED_ON digitalLo(RGB_BLUE_LED_GPIO,RGB_BLUE_LED_GPIO_PIN)
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɫ<EFBFBD><C9AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DFBC>÷<EFBFBD>ʹ<EFBFBD><CAB9>PWM<57>ɻ<EFBFBD><C9BB><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD>ɫ,<2C><>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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//<2F><>
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#define RGB_LED_COLOR_RED \
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RGB_RED_LED_ON;\
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RGB_GREEN_LED_OFF;\
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RGB_BLUE_LED_OFF
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//<2F><>
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#define RGB_LED_COLOR_GREEN \
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RGB_RED_LED_OFF;\
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RGB_GREEN_LED_ON;\
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RGB_BLUE_LED_OFF
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//<2F><>
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#define RGB_LED_COLOR_BLUE \
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RGB_RED_LED_OFF;\
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RGB_GREEN_LED_OFF;\
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RGB_BLUE_LED_ON
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//<2F><>(<28><>+<2B><>)
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#define RGB_LED_COLOR_YELLOW \
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RGB_RED_LED_ON;\
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RGB_GREEN_LED_ON;\
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RGB_BLUE_LED_OFF
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//<2F><>(<28><>+<2B><>)
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#define RGB_LED_COLOR_PURPLE \
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RGB_RED_LED_ON;\
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RGB_GREEN_LED_OFF;\
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RGB_BLUE_LED_ON
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//<2F><>(<28><>+<2B><>)
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#define RGB_LED_COLOR_CYAN \
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RGB_RED_LED_OFF;\
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RGB_GREEN_LED_ON;\
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RGB_BLUE_LED_ON
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//<2F><>(<28><>+<2B><>+<2B><>)
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#define RGB_LED_COLOR_WHITE \
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RGB_RED_LED_ON;\
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RGB_GREEN_LED_ON;\
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RGB_BLUE_LED_ON
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//<2F><>(ȫ<><C8AB><EFBFBD>ر<EFBFBD>)
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#define RGB_LED_COLOR_OFF \
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RGB_RED_LED_OFF;\
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RGB_GREEN_LED_OFF;\
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RGB_BLUE_LED_OFF
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/*******************************************************************************
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* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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******************************************************************************/
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void LED_GPIO_Config(void);
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#endif /* __BSP_LED_H */
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98
board/FIRE_NXP_IMXRT1052/BSP/Inc/clock_config.h
Normal file
98
board/FIRE_NXP_IMXRT1052/BSP/Inc/clock_config.h
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@@ -0,0 +1,98 @@
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/*
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* The Clear BSD License
|
||||
* Copyright 2017 NXP
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* All rights reserved.
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||||
*
|
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* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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|
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/*!
|
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* @brief This function executes default configuration of clocks.
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*
|
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*/
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void BOARD_InitBootClocks(void);
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#if defined(__cplusplus)
|
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}
|
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#endif /* __cplusplus*/
|
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|
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockRUN configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
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/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
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*/
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extern const clock_arm_pll_config_t g_armPllConfig_BOARD_BootClockRUN;
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/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
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*/
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extern const clock_usb_pll_config_t g_usb1PllConfig_BOARD_BootClockRUN;
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/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
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*/
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extern const clock_sys_pll_config_t g_sysPllConfig_BOARD_BootClockRUN;
|
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|
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/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
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******************************************************************************/
|
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#if defined(__cplusplus)
|
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extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
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/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
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void BOARD_BootClockRUN(void);
|
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|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
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#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __EVKBIMXRT1050_DCD_SDRAM_INIT__
|
||||
#define __EVKBIMXRT1050_DCD_SDRAM_INIT__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*************************************
|
||||
* DCD Data
|
||||
*************************************/
|
||||
#define DCD_TAG_HEADER (0xD2)
|
||||
#define DCD_TAG_HEADER_SHIFT (24)
|
||||
#define DCD_VERSION (0x40)
|
||||
#define DCD_ARRAY_SIZE 1
|
||||
|
||||
#endif /* __EVKBIMXRT1050_DCD_SDRAM_INIT__ */
|
||||
@@ -0,0 +1,296 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this
|
||||
* list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __EVKBIMXRT1050_HYPER_CONFIG__
|
||||
#define __EVKBIMXRT1050_HYPER_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
//!@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKBIMXRT1050_HYPER_CONFIG__ */
|
||||
131
board/FIRE_NXP_IMXRT1052/BSP/Inc/fsl_flexspi_nor_boot.h
Normal file
131
board/FIRE_NXP_IMXRT1052/BSP/Inc/fsl_flexspi_nor_boot.h
Normal file
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __FLEXSPI_NOR_BOOT_H__
|
||||
#define __FLEXSPI_NOR_BOOT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "board.h"
|
||||
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
typedef struct _ivt_ {
|
||||
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
|
||||
* (see @ref data)
|
||||
*/
|
||||
uint32_t hdr;
|
||||
/** Absolute address of the first instruction to execute from the
|
||||
* image
|
||||
*/
|
||||
uint32_t entry;
|
||||
/** Reserved in this version of HAB: should be NULL. */
|
||||
uint32_t reserved1;
|
||||
/** Absolute address of the image DCD: may be NULL. */
|
||||
uint32_t dcd;
|
||||
/** Absolute address of the Boot Data: may be NULL, but not interpreted
|
||||
* any further by HAB
|
||||
*/
|
||||
uint32_t boot_data;
|
||||
/** Absolute address of the IVT.*/
|
||||
uint32_t self;
|
||||
/** Absolute address of the image CSF.*/
|
||||
uint32_t csf;
|
||||
/** Reserved in this version of HAB: should be zero. */
|
||||
uint32_t reserved2;
|
||||
} ivt;
|
||||
|
||||
#define IVT_MAJOR_VERSION 0x4
|
||||
#define IVT_MAJOR_VERSION_SHIFT 0x4
|
||||
#define IVT_MAJOR_VERSION_MASK 0xF
|
||||
#define IVT_MINOR_VERSION 0x1
|
||||
#define IVT_MINOR_VERSION_SHIFT 0x0
|
||||
#define IVT_MINOR_VERSION_MASK 0xF
|
||||
|
||||
#define IVT_VERSION(major, minor) \
|
||||
((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
|
||||
(((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
|
||||
|
||||
/* IVT header */
|
||||
#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */
|
||||
#define IVT_SIZE 0x2000
|
||||
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
|
||||
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
|
||||
|
||||
/* Set resume entry */
|
||||
#if defined(__CC_ARM)
|
||||
extern uint32_t __Vectors[];
|
||||
extern uint32_t Image$$RW_m_config_text$$Base[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
|
||||
#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base)
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __Vectors[];
|
||||
extern uint32_t __boot_hdr_start__[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
|
||||
#define FLASH_BASE ((uint32_t)__boot_hdr_start__)
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t m_boot_hdr_conf_start[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
|
||||
#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start)
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __FLASH_BASE[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
|
||||
#define FLASH_BASE ((uint32_t)__FLASH_BASE)
|
||||
#endif
|
||||
|
||||
#define DCD_ADDRESS dcd_data
|
||||
#define BOOT_DATA_ADDRESS &boot_data
|
||||
#define CSF_ADDRESS 0
|
||||
#define IVT_RSVD (uint32_t)(0x00000000)
|
||||
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
typedef struct _boot_data_ {
|
||||
uint32_t start; /* boot start location */
|
||||
uint32_t size; /* size */
|
||||
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
|
||||
uint32_t placeholder; /* placehoder to make even 0x10 size */
|
||||
}BOOT_DATA_T;
|
||||
|
||||
#define FLASH_SIZE BOARD_FLASH_SIZE
|
||||
#define PLUGIN_FLAG (uint32_t)0
|
||||
|
||||
/* External Variables */
|
||||
const BOOT_DATA_T boot_data;
|
||||
extern const uint8_t dcd_data[];
|
||||
|
||||
#endif /* __FLEXSPI_NOR_BOOT_H__ */
|
||||
|
||||
72
board/FIRE_NXP_IMXRT1052/BSP/Inc/pad_config.h
Normal file
72
board/FIRE_NXP_IMXRT1052/BSP/Inc/pad_config.h
Normal file
@@ -0,0 +1,72 @@
|
||||
/**
|
||||
******************************************************************
|
||||
* @file pad_config.h
|
||||
* @author fire
|
||||
* @version V1.0
|
||||
* @date 2018-xx-xx
|
||||
* @brief IOMUXC PAD属性配置使用的功能宏定义
|
||||
******************************************************************
|
||||
* @attention
|
||||
*
|
||||
* 实验平台:野火 i.MXRT1052开发板
|
||||
* 论坛 :http://www.firebbs.cn
|
||||
* 淘宝 :https://fire-stm32.taobao.com
|
||||
*
|
||||
******************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __PAD_CONFIG_H
|
||||
#define __PAD_CONFIG_H
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/* SRE 压摆率选择 */
|
||||
#define SRE_0_SLOW_SLEW_RATE IOMUXC_SW_PAD_CTL_PAD_SRE(0)
|
||||
#define SRE_1_FAST_SLEW_RATE IOMUXC_SW_PAD_CTL_PAD_SRE(1)
|
||||
|
||||
/* 驱动能力配置，配置阻值的大小 */
|
||||
#define DSE_0_OUTPUT_DRIVER_DISABLED IOMUXC_SW_PAD_CTL_PAD_DSE(0)
|
||||
/* R0 260 Ohm @ 3.3V, 150Ohm@1.8V, 240 Ohm for DDR */
|
||||
#define DSE_1_R0_1 IOMUXC_SW_PAD_CTL_PAD_DSE(1)
|
||||
/* R0/2 */
|
||||
#define DSE_2_R0_2 IOMUXC_SW_PAD_CTL_PAD_DSE(2)
|
||||
/* R0/3 */
|
||||
#define DSE_3_R0_3 IOMUXC_SW_PAD_CTL_PAD_DSE(3)
|
||||
/* R0/4 */
|
||||
#define DSE_4_R0_4 IOMUXC_SW_PAD_CTL_PAD_DSE(4)
|
||||
/* R0/5 */
|
||||
#define DSE_5_R0_5 IOMUXC_SW_PAD_CTL_PAD_DSE(5)
|
||||
/* R0/6 */
|
||||
#define DSE_6_R0_6 IOMUXC_SW_PAD_CTL_PAD_DSE(6)
|
||||
/* R0/7 */
|
||||
#define DSE_7_R0_7 IOMUXC_SW_PAD_CTL_PAD_DSE(7)
|
||||
|
||||
/* SPEED 带宽配置 */
|
||||
#define SPEED_0_LOW_50MHz IOMUXC_SW_PAD_CTL_PAD_SPEED(0)
|
||||
#define SPEED_1_MEDIUM_100MHz IOMUXC_SW_PAD_CTL_PAD_SPEED(1)
|
||||
#define SPEED_2_MEDIUM_100MHz IOMUXC_SW_PAD_CTL_PAD_SPEED(2)
|
||||
#define SPEED_3_MAX_200MHz IOMUXC_SW_PAD_CTL_PAD_SPEED(3)
|
||||
|
||||
/* ODE 是否使用开漏模式 */
|
||||
#define ODE_0_OPEN_DRAIN_DISABLED IOMUXC_SW_PAD_CTL_PAD_ODE(0)
|
||||
#define ODE_1_OPEN_DRAIN_ENABLED IOMUXC_SW_PAD_CTL_PAD_ODE(1)
|
||||
|
||||
/* PKE 是否使能保持器或上下拉功能 */
|
||||
#define PKE_0_PULL_KEEPER_DISABLED IOMUXC_SW_PAD_CTL_PAD_PKE(0)
|
||||
#define PKE_1_PULL_KEEPER_ENABLED IOMUXC_SW_PAD_CTL_PAD_PKE(1)
|
||||
|
||||
/* PUE 选择使用保持器还是上下拉 */
|
||||
#define PUE_0_KEEPER_SELECTED IOMUXC_SW_PAD_CTL_PAD_PUE(0)
|
||||
#define PUE_1_PULL_SELECTED IOMUXC_SW_PAD_CTL_PAD_PUE(1)
|
||||
|
||||
/* PUS 上下拉配置 */
|
||||
#define PUS_0_100K_OHM_PULL_DOWN IOMUXC_SW_PAD_CTL_PAD_PUS(0)
|
||||
#define PUS_1_47K_OHM_PULL_UP IOMUXC_SW_PAD_CTL_PAD_PUS(1)
|
||||
#define PUS_2_100K_OHM_PULL_UP IOMUXC_SW_PAD_CTL_PAD_PUS(2)
|
||||
#define PUS_3_22K_OHM_PULL_UP IOMUXC_SW_PAD_CTL_PAD_PUS(3)
|
||||
|
||||
/* HYS 滞后功能 */
|
||||
#define HYS_0_HYSTERESIS_DISABLED IOMUXC_SW_PAD_CTL_PAD_HYS(0)
|
||||
#define HYS_1_HYSTERESIS_ENABLED IOMUXC_SW_PAD_CTL_PAD_HYS(1)
|
||||
|
||||
#endif /* __PAD_CONFIG_H */
|
||||
21
board/FIRE_NXP_IMXRT1052/BSP/Inc/peripherals.h
Normal file
21
board/FIRE_NXP_IMXRT1052/BSP/Inc/peripherals.h
Normal file
@@ -0,0 +1,21 @@
|
||||
#ifndef _PERIPHERALS_H_
|
||||
#define _PERIPHERALS_H_
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /*_cplusplus. */
|
||||
/*******************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD_InitConfigMPU function
|
||||
******************************************************************************/
|
||||
void BOARD_ConfigMPU(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /*_cplusplus. */
|
||||
|
||||
#endif /* _PERIPHERALS_H_ */
|
||||
76
board/FIRE_NXP_IMXRT1052/BSP/Inc/pin_mux.h
Normal file
76
board/FIRE_NXP_IMXRT1052/BSP/Inc/pin_mux.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
243
board/FIRE_NXP_IMXRT1052/BSP/Src/board.c
Normal file
243
board/FIRE_NXP_IMXRT1052/BSP/Src/board.c
Normal file
@@ -0,0 +1,243 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#include "tos_k.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/* Get debug console frequency. */
|
||||
uint32_t BOARD_DebugConsoleSrcFreq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
/* To make it simple, we assume default PLL and divider settings, and the only variable
|
||||
from application is use PLL3 source or OSC source */
|
||||
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
|
||||
{
|
||||
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
if (tos_knl_is_running())
|
||||
{
|
||||
tos_knl_irq_enter();
|
||||
tos_tick_handler();
|
||||
tos_knl_irq_leave();
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize debug console. */
|
||||
void BOARD_InitDebugConsole(void)
|
||||
{
|
||||
uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
|
||||
|
||||
DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
|
||||
}
|
||||
|
||||
/* MPU configuration. */
|
||||
void BOARD_ConfigMPU(void)
|
||||
{
|
||||
/* Disable I cache and D cache */
|
||||
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
|
||||
SCB_DisableICache();
|
||||
}
|
||||
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/* Disable MPU */
|
||||
ARM_MPU_Disable();
|
||||
|
||||
/* MPU configure:
|
||||
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
|
||||
* API in core_cm7.h.
|
||||
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled.
|
||||
* param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* Use MACROS defined in core_cm7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
|
||||
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
|
||||
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
|
||||
* 0 x 0 0 Strongly Ordered shareable
|
||||
* 0 x 0 1 Device shareable
|
||||
* 0 0 1 0 Normal not shareable Outer and inner write through no write allocate
|
||||
* 0 0 1 1 Normal not shareable Outer and inner write back no write allocate
|
||||
* 0 1 1 0 Normal shareable Outer and inner write through no write allocate
|
||||
* 0 1 1 1 Normal shareable Outer and inner write back no write allocate
|
||||
* 1 0 0 0 Normal not shareable outer and inner noncache
|
||||
* 1 1 0 0 Normal shareable outer and inner noncache
|
||||
* 1 0 1 1 Normal not shareable outer and inner write back write/read acllocate
|
||||
* 1 1 1 1 Normal shareable outer and inner write back write/read acllocate
|
||||
* 2 x 0 0 Device not shareable
|
||||
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy.
|
||||
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
|
||||
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
|
||||
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in core_cm7.h.
|
||||
*/
|
||||
|
||||
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
|
||||
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 2 setting */
|
||||
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||||
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
#else
|
||||
/* Setting Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||||
#endif
|
||||
|
||||
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
|
||||
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||||
|
||||
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||||
|
||||
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||||
|
||||
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||||
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||||
|
||||
/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
|
||||
* accessed by cache can be put here */
|
||||
/* Memory with Normal type, not shareable, non-cacheable */
|
||||
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
|
||||
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
|
||||
|
||||
/* Enable MPU */
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
|
||||
|
||||
/* Enable I cache and D cache */
|
||||
SCB_EnableDCache();
|
||||
SCB_EnableICache();
|
||||
|
||||
#if defined(USE_RAM_VECTOR_TABLE)
|
||||
/* <20><><EFBFBD><EFBFBD>SDRAM<41>汾<EFBFBD><E6B1BE><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
CopyAndUseRAMVectorTable();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(USE_RAM_VECTOR_TABLE)
|
||||
/**
|
||||
* @brief <20><><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>ݵ<EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD><C3B8>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* @note <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>nor_sdram_code<64>汾<EFBFBD>ij<EFBFBD><C4B3><EFBFBD><EFBFBD><EFBFBD>оƬ<D0BE>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD>
|
||||
ʹ<><CAB9>SDRAM<41><4D><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϲ<D0B6><CFB2><EFBFBD>ʱCPU<50><55><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>FLASH
|
||||
* @retval <20><>
|
||||
*/
|
||||
void CopyAndUseRAMVectorTable(void)
|
||||
{
|
||||
/* <20><><EFBFBD>ݲ<EFBFBD>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>ƽ̨<C6BD>ķ<EFBFBD>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>õ<EFBFBD>VECTOR_TABLE <20><> VECTOR_RAM<41>ĵ<EFBFBD>ַ*/
|
||||
#if defined(__CC_ARM)
|
||||
/* ROM<4F><4D>RAM<41>е<EFBFBD><D0B5>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>MDK<44><4B>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFB7A8> */
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
/* SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><C4BB><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD>VECTOR_RAMռ<4D>õĿռ<C4BF> */
|
||||
extern uint32_t Image$$ER_m_ram_text$$Base[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$ER_m_ram_text$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
/* ROM<4F><4D>RAM<41>е<EFBFBD><D0B5>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD>С<EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD>ַ<EFBFBD><D6B7>IAR<41><52>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFB7A8> */
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
/* <20><>δ<EFBFBD><CEB4><EFBFBD><EFBFBD>GCC<43><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) */
|
||||
uint32_t n;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* <20><><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ROM<4F><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* <20><><EFBFBD><EFBFBD>Cortex-M<>ں˵<DABA>VTOR<4F>Ĵ<EFBFBD><C4B4><EFBFBD>ָ<EFBFBD><D6B8>RAM<41>汾<EFBFBD><E6B1BE><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>VTOR<4F>Ĵ<EFBFBD><C4B4><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
*/
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
124
board/FIRE_NXP_IMXRT1052/BSP/Src/bsp_led.c
Normal file
124
board/FIRE_NXP_IMXRT1052/BSP/Src/bsp_led.c
Normal file
@@ -0,0 +1,124 @@
|
||||
/**
|
||||
******************************************************************
|
||||
* @file bsp_led.c
|
||||
* @author fire
|
||||
* @version V1.1
|
||||
* @date 2018-xx-xx
|
||||
* @brief ledӦ<64>ú<EFBFBD><C3BA><EFBFBD><EFBFBD>ӿ<EFBFBD>
|
||||
******************************************************************
|
||||
* @attention
|
||||
*
|
||||
* ʵ<><CAB5>ƽ̨:Ұ<><D2B0> i.MXRT1052<35><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* <20><>̳ :http://www.firebbs.cn
|
||||
* <20>Ա<EFBFBD> :https://fire-stm32.taobao.com
|
||||
*
|
||||
******************************************************************
|
||||
*/
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
#include "pad_config.h"
|
||||
#include "bsp_led.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* <20><>
|
||||
******************************************************************************/
|
||||
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ž<EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>PAD<41><44><EFBFBD><EFBFBD> */
|
||||
#define LED_PAD_CONFIG_DATA (SRE_0_SLOW_SLEW_RATE| \
|
||||
DSE_6_R0_6| \
|
||||
SPEED_2_MEDIUM_100MHz| \
|
||||
ODE_0_OPEN_DRAIN_DISABLED| \
|
||||
PKE_0_PULL_KEEPER_DISABLED| \
|
||||
PUE_0_KEEPER_SELECTED| \
|
||||
PUS_0_100K_OHM_PULL_DOWN| \
|
||||
HYS_0_HYSTERESIS_DISABLED)
|
||||
/* <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> : */
|
||||
/* ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF>: R0/6
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> : medium(100MHz)
|
||||
<20><>©<EFBFBD><C2A9><EFBFBD><EFBFBD>: <20>ر<EFBFBD>
|
||||
<20><>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20>ر<EFBFBD>
|
||||
<20><>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹرգ<D8B1><D5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>
|
||||
<20><><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>: 100Kŷķ<C5B7><C4B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹرգ<D8B1><D5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>
|
||||
<20>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: <20>ر<EFBFBD> */
|
||||
|
||||
/*******************************************************************************
|
||||
* <20><><EFBFBD><EFBFBD>
|
||||
******************************************************************************/
|
||||
static void LED_IOMUXC_MUX_Config(void);
|
||||
static void LED_IOMUXC_PAD_Config(void);
|
||||
static void LED_GPIO_Mode_Config(void);
|
||||
|
||||
/**
|
||||
* @brief <20><>ʼ<EFBFBD><CABC>LED<45><44><EFBFBD><EFBFBD>IOMUXC<58><43>MUX<55><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* @param <20><>
|
||||
* @retval <20><>
|
||||
*/
|
||||
static void LED_IOMUXC_MUX_Config(void)
|
||||
{
|
||||
/* <20><><EFBFBD>İ<EFBFBD><C4B0><EFBFBD>LED<45><44> */
|
||||
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŵĸ<C5B5><C4B8><EFBFBD>ģʽΪGPIO<49><4F><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>SION<4F><4E><EFBFBD><EFBFBD> */
|
||||
IOMUXC_SetPinMux(CORE_BOARD_LED_IOMUXC, 0U);
|
||||
|
||||
/* RGB LED<45>ƣ<EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>IOMUXC MUX<55><58><EFBFBD><EFBFBD> */
|
||||
IOMUXC_SetPinMux(RGB_RED_LED_IOMUXC, 0U);
|
||||
IOMUXC_SetPinMux(RGB_BLUE_LED_IOMUXC, 0U);
|
||||
IOMUXC_SetPinMux(RGB_GREEN_LED_IOMUXC, 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief <20><>ʼ<EFBFBD><CABC>LED<45><44><EFBFBD><EFBFBD>IOMUXC<58><43>MUX<55><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* @param <20><>
|
||||
* @retval <20><>
|
||||
*/
|
||||
static void LED_IOMUXC_PAD_Config(void)
|
||||
{
|
||||
/* <20><><EFBFBD>İ<EFBFBD><C4B0><EFBFBD>LED<45><44> */
|
||||
IOMUXC_SetPinConfig(CORE_BOARD_LED_IOMUXC, LED_PAD_CONFIG_DATA);
|
||||
|
||||
/* RGB LED<45>ƣ<EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>IOMUXC PAD<41><44><EFBFBD><EFBFBD> */
|
||||
IOMUXC_SetPinConfig(RGB_RED_LED_IOMUXC, LED_PAD_CONFIG_DATA);
|
||||
IOMUXC_SetPinConfig(RGB_GREEN_LED_IOMUXC, LED_PAD_CONFIG_DATA);
|
||||
IOMUXC_SetPinConfig(RGB_BLUE_LED_IOMUXC, LED_PAD_CONFIG_DATA);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief <20><>ʼ<EFBFBD><CABC>LED<45><44><EFBFBD>ص<EFBFBD>GPIOģʽ
|
||||
* @param <20><>
|
||||
* @retval <20><>
|
||||
*/
|
||||
static void LED_GPIO_Mode_Config(void)
|
||||
{
|
||||
/* <20><><EFBFBD><EFBFBD>gpio<69><6F>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ýṹ<C3BD><E1B9B9> */
|
||||
gpio_pin_config_t led_config;
|
||||
|
||||
/** <20><><EFBFBD>İ<EFBFBD><C4B0><EFBFBD>LED<45>ƣ<EFBFBD>GPIO<49><4F><EFBFBD><EFBFBD> **/
|
||||
led_config.direction = kGPIO_DigitalOutput; //<2F><><EFBFBD><EFBFBD>ģʽ
|
||||
led_config.outputLogic = 1; //Ĭ<>ϸߵ<CFB8>ƽ
|
||||
led_config.interruptMode = kGPIO_NoIntmode; //<2F><>ʹ<EFBFBD><CAB9><EFBFBD>ж<EFBFBD>
|
||||
|
||||
/* <20><>ʼ<EFBFBD><CABC> LED GPIO. */
|
||||
GPIO_PinInit(CORE_BOARD_LED_GPIO, CORE_BOARD_LED_GPIO_PIN, &led_config);
|
||||
|
||||
/* ʹ<><CAB9>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>LED config<69><67><EFBFBD><EFBFBD>RGB LED<45><44> */
|
||||
GPIO_PinInit(RGB_RED_LED_GPIO, RGB_RED_LED_GPIO_PIN, &led_config);
|
||||
GPIO_PinInit(RGB_GREEN_LED_GPIO, RGB_GREEN_LED_GPIO_PIN, &led_config);
|
||||
GPIO_PinInit(RGB_BLUE_LED_GPIO, RGB_BLUE_LED_GPIO_PIN, &led_config);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LED<45><44>IO
|
||||
* @param <20><>
|
||||
* @retval <20><>
|
||||
*/
|
||||
void LED_GPIO_Config(void)
|
||||
{
|
||||
/* <20><>ʼ<EFBFBD><CABC>GPIO<49><4F><EFBFBD>á<EFBFBD><C3A1><EFBFBD><EFBFBD>ԡ<EFBFBD>ģʽ */
|
||||
LED_IOMUXC_MUX_Config();
|
||||
LED_IOMUXC_PAD_Config();
|
||||
LED_GPIO_Mode_Config();
|
||||
}
|
||||
|
||||
|
||||
/*********************************************END OF FILE**********************/
|
||||
307
board/FIRE_NXP_IMXRT1052/BSP/Src/clock_config.c
Normal file
307
board/FIRE_NXP_IMXRT1052/BSP/Src/clock_config.c
Normal file
@@ -0,0 +1,307 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
|
||||
*
|
||||
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
|
||||
*
|
||||
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
|
||||
*
|
||||
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
|
||||
*
|
||||
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
|
||||
*
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v4.0
|
||||
processor: MIMXRT1052xxxxx
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: i_mx_1_0
|
||||
processor_version: 0.0.0
|
||||
board: IMXRT1050-EVKB
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
|
||||
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
|
||||
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
|
||||
- {id: CLK_1M.outFreq, value: 1 MHz}
|
||||
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
|
||||
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
|
||||
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
|
||||
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 37.5 MHz}
|
||||
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
|
||||
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
|
||||
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
|
||||
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
|
||||
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
|
||||
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
|
||||
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
|
||||
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
|
||||
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
settings:
|
||||
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
|
||||
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
|
||||
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
|
||||
- {id: CCM.SEMC_PODF.scale, value: '8'}
|
||||
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
|
||||
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
|
||||
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
|
||||
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
|
||||
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
|
||||
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
|
||||
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
|
||||
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
|
||||
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
|
||||
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
|
||||
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
|
||||
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
|
||||
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
|
||||
- {id: CCM_ANALOG.PLL4.div, value: '47'}
|
||||
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
|
||||
- {id: CCM_ANALOG.PLL5.div, value: '40'}
|
||||
- {id: CCM_ANALOG.PLL5.num, value: '0'}
|
||||
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
|
||||
sources:
|
||||
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
|
||||
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */
|
||||
};
|
||||
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
|
||||
.numerator = 0, /* 30 bit numerator of fractional loop divider */
|
||||
.denominator = 1, /* 30 bit denominator of fractional loop divider */
|
||||
};
|
||||
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
|
||||
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Init RTC OSC clock frequency. */
|
||||
CLOCK_SetRtcXtalFreq(32768U);
|
||||
/* Set XTAL 24MHz clock frequency. */
|
||||
CLOCK_SetXtalFreq(24000000U);
|
||||
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
|
||||
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz. */
|
||||
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
|
||||
/* Waiting for DCDC_STS_DC_OK bit is asserted */
|
||||
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
|
||||
{
|
||||
}
|
||||
/* Init ARM PLL. */
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||
/* Init System PLL. */
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||||
#endif
|
||||
/* Init Usb1 PLL. */
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||||
#endif
|
||||
/* Enbale Audio PLL output. */
|
||||
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||||
/* Enbale Video PLL output. */
|
||||
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||||
/* Enable ENET PLL output. */
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
/* Set periph clock2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||||
/* Set PERIPH_CLK2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
|
||||
/* Set periph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||||
/* Set AHB_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
|
||||
/* Set IPG_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
|
||||
/* Set ARM_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
|
||||
/* Set preperiph clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||||
/* Set PERCLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
|
||||
/* Set per clock source. */
|
||||
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||||
/* Set Usdhc1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
|
||||
/* Set USDHC1_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
|
||||
/* Set Usdhc2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
|
||||
/* Set USDHC2_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
|
||||
#ifndef SKIP_SYSCLK_INIT
|
||||
/* Set Semc alt clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
|
||||
/* Set Semc clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SemcMux, 1);
|
||||
/* Set SEMC_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
|
||||
#endif
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||||
/* Set Flexspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
|
||||
/* Set FLEXSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
|
||||
#endif
|
||||
/* Set Csi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CsiMux, 0);
|
||||
/* Set CSI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
|
||||
/* Set Lpspi clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||||
/* Set LPSPI_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||||
/* Set Trace clock source. */
|
||||
CLOCK_SetMux(kCLOCK_TraceMux, 2);
|
||||
/* Set TRACE_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
|
||||
/* Set Sai1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||||
/* Set SAI1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||||
/* Set SAI1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||||
/* Set Sai2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||||
/* Set SAI2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||||
/* Set SAI2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||||
/* Set Sai3 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||||
/* Set SAI3_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||||
/* Set SAI3_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||||
/* Set Lpi2c clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||||
/* Set LPI2C_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||||
/* Set Can clock source. */
|
||||
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||||
/* Set CAN_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||||
/* Set Uart clock source. */
|
||||
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||||
/* Set UART_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||||
/* Set Lcdif pre clock source. */
|
||||
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||||
/* Set LCDIF_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
|
||||
/* Set LCDIF_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
|
||||
/* Set Spdif clock source. */
|
||||
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||||
/* Set SPDIF0_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||||
/* Set SPDIF0_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||||
/* Set Flexio1 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||||
/* Set FLEXIO1_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||||
/* Set FLEXIO1_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||||
/* Set Flexio2 clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||||
/* Set FLEXIO2_CLK_PRED. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||||
/* Set FLEXIO2_CLK_PODF. */
|
||||
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||||
/* Set Pll3 sw clock source. */
|
||||
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||||
/* Set lvds1 clock source. */
|
||||
CCM_ANALOG->MISC1 =
|
||||
(CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
1127
board/FIRE_NXP_IMXRT1052/BSP/Src/fire_imxrt1052_sdram_ini_dcd.c
Normal file
1127
board/FIRE_NXP_IMXRT1052/BSP/Src/fire_imxrt1052_sdram_ini_dcd.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fire_imxrt1052_spiflash_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t spiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,/*<2A><>־<EFBFBD><D6BE>FCFB*/
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,/*<2A>汾<EFBFBD><E6B1BE>V1.4.0*/
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,/*<2A>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
.csHoldTime = 3u, /*<2A><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>*/
|
||||
.csSetupTime = 3u,/*<2A><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>*/
|
||||
.columnAddressWidth = 0u,/*<2A>е<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>*/
|
||||
.deviceModeCfgEnable = 1u,/*<2A>豸ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>*/
|
||||
.deviceModeType = 1u,/*Quad ʹ<><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
.deviceModeSeq.seqNum = 1u,/*LUT<55><54><EFBFBD>к<EFBFBD>*/
|
||||
.deviceModeSeq.seqId = 4u, /*LUT<55><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
.deviceModeArg = 0x000200,/*<2A><><EFBFBD><EFBFBD> QE=1<><31>S9<53><39>*/
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>Ϊnor flash*/
|
||||
.sflashPadType = kSerialFlash_4Pads,/*<2A>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ4*/
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,/*flash ʱ<><CAB1>*/
|
||||
.sflashA1Size = 32u * 1024u * 1024u, /*flash <20><>С32MBytes*/
|
||||
//.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
/*<2A><><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EEA3A8><EFBFBD>ߣ<EFBFBD>*/
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
|
||||
|
||||
/*<2A><>״̬<D7B4><CCAC><EFBFBD><EFBFBD>*/
|
||||
[1*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
/*дʹ<D0B4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
[3*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
[5*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x04),
|
||||
/*ҳ<><D2B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EEA3A8><EFBFBD>ߣ<EFBFBD>*/
|
||||
[9*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[9*4+1] = FLEXSPI_LUT_SEQ(WRITE_SDR,FLEXSPI_4PAD , 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
/*<2A><>Ƭ<EFBFBD><C6AC><EFBFBD><EFBFBD>*/
|
||||
[11*4] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xc7, STOP, FLEXSPI_1PAD, 0),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,/*ҳ<><D2B3>СΪ256<35>ֽ<EFBFBD>*/
|
||||
.sectorSize = 4u * 1024u,/*<2A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>СΪ4k<34>ֽ<EFBFBD>*/
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
72
board/FIRE_NXP_IMXRT1052/BSP/Src/fsl_flexspi_nor_boot.c
Normal file
72
board/FIRE_NXP_IMXRT1052/BSP/Src/fsl_flexspi_nor_boot.c
Normal file
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_flexspi_nor_boot.h"
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.ivt")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location=".boot_hdr.ivt"
|
||||
#endif
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
const ivt image_vector_table = {
|
||||
IVT_HEADER, /* IVT ͷ<><CDB7> */
|
||||
IMAGE_ENTRY_ADDRESS, /* <20>̼<EFBFBD><CCBC><EFBFBD><EFBFBD>ڵ<EFBFBD>ַ */
|
||||
IVT_RSVD, /* <20><><EFBFBD><EFBFBD> */
|
||||
(uint32_t)DCD_ADDRESS, /* DCD<43><44><EFBFBD>ݴ洢<DDB4>ĵ<EFBFBD>ַ */
|
||||
(uint32_t)BOOT_DATA_ADDRESS, /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽṹ<DDBD>洢<EFBFBD>ĵ<EFBFBD>ַ */
|
||||
(uint32_t)&image_vector_table, /* IVT<56><54><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>Ĵ洢<C4B4><E6B4A2>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>Ե<EFBFBD>ַ<EFBFBD><D6B7> */
|
||||
(uint32_t)CSF_ADDRESS, /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>洢<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
IVT_RSVD /* <20><><EFBFBD><EFBFBD> */
|
||||
};
|
||||
|
||||
#if defined(__CC_ARM) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.boot_data")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location=".boot_hdr.boot_data"
|
||||
#endif
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
const BOOT_DATA_T boot_data = {
|
||||
FLASH_BASE, /* <20>̼<EFBFBD><CCBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>flash<73><68><EFBFBD><EFBFBD>ַ */
|
||||
FLASH_SIZE, /* flash<73><68>С */
|
||||
PLUGIN_FLAG, /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
|
||||
0xFFFFFFFF /* <20>գ<EFBFBD><D5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
83
board/FIRE_NXP_IMXRT1052/BSP/Src/main.c
Normal file
83
board/FIRE_NXP_IMXRT1052/BSP/Src/main.c
Normal file
@@ -0,0 +1,83 @@
|
||||
#include "fsl_debug_console.h"
|
||||
#include "board.h"
|
||||
#include "pin_mux.h"
|
||||
#include "clock_config.h"
|
||||
#include "bsp_led.h"
|
||||
#include "cmsis_os.h"
|
||||
|
||||
|
||||
#define TASK1_STK_SIZE 512
|
||||
void task1(void *arg);
|
||||
osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE);
|
||||
|
||||
#define TASK2_STK_SIZE 512
|
||||
void task2(void *arg);
|
||||
osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE);
|
||||
|
||||
|
||||
void task1(void *arg)
|
||||
{
|
||||
int count = 0;
|
||||
while(1)
|
||||
{
|
||||
PRINTF("********This is Task 1, count is %d \r\n",count++);
|
||||
/* LED<45><44> */
|
||||
CORE_BOARD_LED_ON;
|
||||
|
||||
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɫ */
|
||||
RGB_LED_COLOR_RED;
|
||||
osDelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void task2(void *arg)
|
||||
{
|
||||
int count = 0;
|
||||
while(1)
|
||||
{
|
||||
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɫ */
|
||||
RGB_LED_COLOR_GREEN;
|
||||
PRINTF("++++++++This is Task 2, count is %d \r\n",count++);
|
||||
osDelay(2000);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
* @param <20><>
|
||||
* @retval <20><>
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/* <20><>ʼ<EFBFBD><CABC><EFBFBD>ڴ汣<DAB4><E6B1A3><EFBFBD><EFBFBD>Ԫ */
|
||||
BOARD_ConfigMPU();
|
||||
/* <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
||||
BOARD_InitPins();
|
||||
/* <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1> */
|
||||
BOARD_BootClockRUN();
|
||||
/* <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD> */
|
||||
BOARD_InitDebugConsole();
|
||||
/* <20><>ӡϵͳʱ<CDB3><CAB1> */
|
||||
PRINTF("\r\n");
|
||||
PRINTF("*****<2A><>ӭʹ<D3AD><CAB9>i.MX RT1052 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*****\r\n");
|
||||
PRINTF("CPU: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_CpuClk));
|
||||
PRINTF("AHB: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_AhbClk));
|
||||
PRINTF("SEMC: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SemcClk));
|
||||
PRINTF("SYSPLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllClk));
|
||||
PRINTF("SYSPLLPFD0: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
|
||||
PRINTF("SYSPLLPFD1: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
|
||||
PRINTF("SYSPLLPFD2: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
|
||||
PRINTF("SYSPLLPFD3: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
|
||||
|
||||
PRINTF("GPIO<EFBFBD><EFBFBD><EFBFBD><EFBFBD>-ʹ<>ù̼<C3B9><CCBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>LED\r\n");
|
||||
|
||||
/* <20><>ʼ<EFBFBD><CABC>LED<45><44><EFBFBD><EFBFBD> */
|
||||
LED_GPIO_Config();
|
||||
printf("Welcome to TencentOS tiny\r\n");
|
||||
osKernelInitialize(); // TencentOS Tiny kernel initialize
|
||||
osThreadCreate(osThread(task1), NULL); // Create task1
|
||||
osThreadCreate(osThread(task2), NULL); // Create task2
|
||||
osKernelStart(); // Start TencentOS Tiny
|
||||
}
|
||||
/****************************END OF FILE**********************/
|
||||
17
board/FIRE_NXP_IMXRT1052/BSP/Src/peripherals.c
Normal file
17
board/FIRE_NXP_IMXRT1052/BSP/Src/peripherals.c
Normal file
@@ -0,0 +1,17 @@
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Peripherals v1.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Included files
|
||||
******************************************************************************/
|
||||
#include "peripherals.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* BOARD_InitBootPeripherals function
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootPeripherals(void)
|
||||
{
|
||||
BOARD_ConfigMPU();
|
||||
}
|
||||
111
board/FIRE_NXP_IMXRT1052/BSP/Src/pin_mux.c
Normal file
111
board/FIRE_NXP_IMXRT1052/BSP/Src/pin_mux.c
Normal file
@@ -0,0 +1,111 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v4.0
|
||||
processor: MIMXRT1052xxxxx
|
||||
package_id: MIMXRT1052DVL6B
|
||||
mcu_data: i_mx_1_0
|
||||
processor_version: 0.0.0
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
|
||||
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
|
||||
0x10B0u); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: R0/6
|
||||
Speed Field: medium(100MHz)
|
||||
Open Drain Enable Field: Open Drain Disabled
|
||||
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||
Pull / Keep Select Field: Keeper
|
||||
Pull Up / Down Config. Field: 100K Ohm Pull Down
|
||||
Hyst. Enable Field: Hysteresis Disabled */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
6972
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/JLinkLog.txt
Normal file
6972
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/JLinkLog.txt
Normal file
File diff suppressed because it is too large
Load Diff
39
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/JLinkSettings.ini
Normal file
39
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/JLinkSettings.ini
Normal file
@@ -0,0 +1,39 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
MonModeVTableAddr = 0xFFFFFFFF
|
||||
MonModeDebug = 0
|
||||
MaxNumAPs = 0
|
||||
LowPowerHandlingMode = 0
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 0
|
||||
Device="ARM7"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
@@ -0,0 +1,117 @@
|
||||
#! armcc -E
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b180131
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x01FFDC00
|
||||
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00020000
|
||||
|
||||
#define m_data2_start 0x20200000
|
||||
#define m_data2_size 0x00040000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
LR_m_rom_config m_flash_config_start m_flash_config_size { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_rom_ivt m_ivt_start m_ivt_size { ; load region size_region
|
||||
RW_m_ivt_text m_ivt_start m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
}
|
||||
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_size { ; load region size_region
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (RESET,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (NonCacheable.init)
|
||||
* (NonCacheable)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
}
|
||||
885
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/TencentOS_tiny.uvoptx
Normal file
885
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/TencentOS_tiny.uvoptx
Normal file
@@ -0,0 +1,885 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>TencentOS_tiny</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>8</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>4</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>.\evkbimxrt1050_flexspi_nor.ini</tIfile>
|
||||
<pMon>Segger\JL2CM3.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>-U260106173 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_QuadSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1052DVL6B$arm\MIMXRT105x_QuadSPI_4KB_SEC.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052DVL6B$arm\MIMXRT105x_HYPER_256KB_SEC.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Fire CMSIS-DAP" -UHS-00000000 -O1007 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0iMXRT1052_W25Q256JV_RAW_By_Fire -FS060000000 -FL02000000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>1</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>USER</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\board.c</PathWithFileName>
|
||||
<FilenameWithoutPath>board.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\bsp_led.c</PathWithFileName>
|
||||
<FilenameWithoutPath>bsp_led.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\clock_config.c</PathWithFileName>
|
||||
<FilenameWithoutPath>clock_config.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\fire_imxrt1052_sdram_ini_dcd.c</PathWithFileName>
|
||||
<FilenameWithoutPath>fire_imxrt1052_sdram_ini_dcd.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\fire_imxrt1052_spiflash_config.c</PathWithFileName>
|
||||
<FilenameWithoutPath>fire_imxrt1052_spiflash_config.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\fsl_flexspi_nor_boot.c</PathWithFileName>
|
||||
<FilenameWithoutPath>fsl_flexspi_nor_boot.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\peripherals.c</PathWithFileName>
|
||||
<FilenameWithoutPath>peripherals.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>9</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\BSP\Src\pin_mux.c</PathWithFileName>
|
||||
<FilenameWithoutPath>pin_mux.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>10</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\system_MIMXRT1052.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_MIMXRT1052.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>startup</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>11</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\startup_MIMXRT1052.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_MIMXRT1052.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>drivers</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
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<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>44</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_sched.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_sched.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>45</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_sem.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_sem.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>46</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_sys.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_sys.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>47</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_task.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_task.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>48</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_tick.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_tick.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>49</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_time.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_time.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>7</GroupNumber>
|
||||
<FileNumber>50</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\kernel\core\tos_timer.c</PathWithFileName>
|
||||
<FilenameWithoutPath>tos_timer.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>tos/cmsis</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>8</GroupNumber>
|
||||
<FileNumber>51</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\osal\cmsis_os\cmsis_os.c</PathWithFileName>
|
||||
<FilenameWithoutPath>cmsis_os.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
690
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/TencentOS_tiny.uvprojx
Normal file
690
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/TencentOS_tiny.uvprojx
Normal file
@@ -0,0 +1,690 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>TencentOS_tiny</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MIMXRT1052DVL6B</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>NXP.MIMXRT1052_DFP.12.0.0</PackID>
|
||||
<PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) XRAM(0x20200000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll></FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:MIMXRT1052DVL6B$fsl_device_registers.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:MIMXRT1052DVL6B$MIMXRT1052.xml</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\object\</OutputDirectory>
|
||||
<OutputName>TencentOS_tiny</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2></Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M7"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>1</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>3</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>0</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>--library_interface=armcc
|
||||
--library_type=standardlib
|
||||
--diag_suppress=66,1296,186,1,47,177,223,1295</MiscControls>
|
||||
<Define>CPU_MIMXRT1052DVL6B,XIP_EXTERNAL_FLASH=1, XIP_BOOT_HEADER_ENABLE =1,XIP_BOOT_HEADER_DCD_ENABLE =1,PRINTF_FLOAT_ENABLE=1, SCANF_FLOAT_ENABLE=1, PRINTF_ADVANCED_ENABLE=1, SCANF_ADVANCED_ENABLE=1</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\CMSIS\Include;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\log;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\io;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\xip;..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052;..\..\BSP\Inc;..\..\TOS_CONFIG;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>__STARTUP_INITIALIZE_NONCACHEDATA</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\MIMXRT1052xxxxx_nor_txt_ram.scf</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--keep=*(.boot_hdr.conf)
|
||||
--keep=*(.boot_hdr.ivt)</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings>6314</DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>USER</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>board.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\board.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>bsp_led.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\bsp_led.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>clock_config.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\clock_config.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fire_imxrt1052_sdram_ini_dcd.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\fire_imxrt1052_sdram_ini_dcd.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fire_imxrt1052_spiflash_config.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\fire_imxrt1052_spiflash_config.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_flexspi_nor_boot.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\fsl_flexspi_nor_boot.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>peripherals.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\peripherals.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>pin_mux.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\pin_mux.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_MIMXRT1052.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\system_MIMXRT1052.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>startup</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_MIMXRT1052.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>.\startup_MIMXRT1052.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>drivers</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_clock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_clock.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_common.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_common.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_lpuart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\drivers\fsl_lpuart.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>utilities</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>fsl_io.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\io\fsl_io.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_log.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\log\fsl_log.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_str.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\str\fsl_str.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_assert.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_assert.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_debug_console.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_debug_console.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_notifier.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_notifier.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_sbrk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_sbrk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>fsl_shell.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nxp\MIMXRT1052\utilities\fsl_shell.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/arch</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_cpu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_s.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_binary_heap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_char_fifo.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_completion.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_countdownlatch.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_event.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_global.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_global.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmblk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mmblk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmheap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mutex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_pend.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_ring_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_robin.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_robin.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sched.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sched.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sys.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_task.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_task.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_tick.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_tick.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_time.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_time.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/cmsis</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>cmsis_os.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\osal\cmsis_os\cmsis_os.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
1051
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/startup_MIMXRT1052.s
Normal file
1051
board/FIRE_NXP_IMXRT1052/KEIL/hello_world/startup_MIMXRT1052.s
Normal file
File diff suppressed because it is too large
Load Diff
55
board/FIRE_NXP_IMXRT1052/TOS_CONFIG/tos_config.h
Normal file
55
board/FIRE_NXP_IMXRT1052/TOS_CONFIG/tos_config.h
Normal file
@@ -0,0 +1,55 @@
|
||||
#ifndef _TOS_CONFIG_H_
|
||||
#define _TOS_CONFIG_H_
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#define TOS_CFG_TASK_PRIO_MAX 10u
|
||||
|
||||
#define TOS_CFG_ROUND_ROBIN_EN 0u
|
||||
|
||||
#define TOS_CFG_OBJECT_VERIFY_EN 1u
|
||||
|
||||
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 1u
|
||||
|
||||
#define TOS_CFG_EVENT_EN 1u
|
||||
|
||||
#define TOS_CFG_MMBLK_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x1000
|
||||
|
||||
#define TOS_CFG_MUTEX_EN 1u
|
||||
|
||||
#define TOS_CFG_MESSAGE_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_MAIL_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u
|
||||
|
||||
#define TOS_CFG_TIMER_EN 1u
|
||||
|
||||
#define TOS_CFG_PWR_MGR_EN 0u
|
||||
|
||||
#define TOS_CFG_TICKLESS_EN 0u
|
||||
|
||||
#define TOS_CFG_SEM_EN 1u
|
||||
|
||||
#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u
|
||||
|
||||
#define TOS_CFG_FAULT_BACKTRACE_EN 0u
|
||||
|
||||
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
|
||||
|
||||
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
|
||||
|
||||
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
|
||||
|
||||
#define TOS_CFG_TIMER_AS_PROC 1u
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,321 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_CAN.h"
|
||||
|
||||
#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) // CAN driver version
|
||||
|
||||
// Driver Version
|
||||
static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION };
|
||||
|
||||
// Driver Capabilities
|
||||
static const ARM_CAN_CAPABILITIES can_driver_capabilities = {
|
||||
32U, // Number of CAN Objects available
|
||||
1U, // Supports reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.
|
||||
0U, // Does not support CAN with Flexible Data-rate mode (CAN_FD)
|
||||
0U, // Does not support restricted operation mode
|
||||
1U, // Supports bus monitoring mode
|
||||
1U, // Supports internal loopback mode
|
||||
1U, // Supports external loopback mode
|
||||
};
|
||||
|
||||
// Object Capabilities
|
||||
static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = {
|
||||
1U, // Object supports transmission
|
||||
1U, // Object supports reception
|
||||
0U, // Object does not support RTR reception and automatic Data transmission
|
||||
0U, // Object does not support RTR transmission and automatic Data reception
|
||||
1U, // Object allows assignment of multiple filters to it
|
||||
1U, // Object supports exact identifier filtering
|
||||
0U, // Object does not support range identifier filtering
|
||||
1U, // Object supports mask identifier filtering
|
||||
3U // Object can buffer 3 messages
|
||||
};
|
||||
|
||||
static uint8_t can_driver_powered = 0U;
|
||||
static uint8_t can_driver_initialized = 0U;
|
||||
static ARM_CAN_SignalUnitEvent_t CAN_SignalUnitEvent = NULL;
|
||||
static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent = NULL;
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
static ARM_DRIVER_VERSION CAN_GetVersion (void) {
|
||||
// Return driver version
|
||||
return can_driver_version;
|
||||
}
|
||||
|
||||
static ARM_CAN_CAPABILITIES CAN_GetCapabilities (void) {
|
||||
// Return driver capabilities
|
||||
return can_driver_capabilities;
|
||||
}
|
||||
|
||||
static int32_t CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event,
|
||||
ARM_CAN_SignalObjectEvent_t cb_object_event) {
|
||||
|
||||
if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; }
|
||||
|
||||
CAN_SignalUnitEvent = cb_unit_event;
|
||||
CAN_SignalObjectEvent = cb_object_event;
|
||||
|
||||
// Add code for pin, memory, RTX objects initialization
|
||||
// ..
|
||||
|
||||
can_driver_initialized = 1U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_Uninitialize (void) {
|
||||
|
||||
// Add code for pin, memory, RTX objects de-initialization
|
||||
// ..
|
||||
|
||||
can_driver_initialized = 0U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_PowerControl (ARM_POWER_STATE state) {
|
||||
switch (state) {
|
||||
case ARM_POWER_OFF:
|
||||
can_driver_powered = 0U;
|
||||
// Add code to disable interrupts and put peripheral into reset mode,
|
||||
// and if possible disable clock
|
||||
// ..
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; }
|
||||
if (can_driver_powered != 0U) { return ARM_DRIVER_OK; }
|
||||
|
||||
// Add code to enable clocks, reset variables enable interrupts
|
||||
// and put peripheral into operational
|
||||
// ..
|
||||
|
||||
can_driver_powered = 1U;
|
||||
break;
|
||||
|
||||
default:
|
||||
// Other states are not supported
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
uint32_t CAN_GetClock (void) {
|
||||
|
||||
// Add code to return peripheral clock frequency
|
||||
// ..
|
||||
}
|
||||
|
||||
static int32_t CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
// Add code to setup peripheral parameters to generate specified bitrate
|
||||
// with specified bit segments
|
||||
// ..
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_SetMode (ARM_CAN_MODE mode) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (mode) {
|
||||
case ARM_CAN_MODE_INITIALIZATION:
|
||||
// Add code to put peripheral into initialization mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_NORMAL:
|
||||
// Add code to put peripheral into normal operation mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_RESTRICTED:
|
||||
// Add code to put peripheral into restricted operation mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_MONITOR:
|
||||
// Add code to put peripheral into bus monitoring mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_LOOPBACK_INTERNAL:
|
||||
// Add code to put peripheral into internal loopback mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_LOOPBACK_EXTERNAL:
|
||||
// Add code to put peripheral into external loopback mode
|
||||
// ..
|
||||
break;
|
||||
default:
|
||||
// Handle unknown mode code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
ARM_CAN_OBJ_CAPABILITIES CAN_ObjectGetCapabilities (uint32_t obj_idx) {
|
||||
// Return object capabilities
|
||||
return can_object_capabilities;
|
||||
}
|
||||
|
||||
static int32_t CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (operation) {
|
||||
case ARM_CAN_FILTER_ID_EXACT_ADD:
|
||||
// Add code to setup peripheral to receive messages with specified exact ID
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_MASKABLE_ADD:
|
||||
// Add code to setup peripheral to receive messages with specified maskable ID
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_RANGE_ADD:
|
||||
// Add code to setup peripheral to receive messages within specified range of IDs
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_EXACT_REMOVE:
|
||||
// Add code to remove specified exact ID from being received by peripheral
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:
|
||||
// Add code to remove specified maskable ID from being received by peripheral
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_RANGE_REMOVE:
|
||||
// Add code to remove specified range of IDs from being received by peripheral
|
||||
break;
|
||||
default:
|
||||
// Handle unknown operation code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (obj_cfg) {
|
||||
case ARM_CAN_OBJ_INACTIVE:
|
||||
// Deactivate object
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_RX_RTR_TX_DATA:
|
||||
// Setup object to automatically return data when RTR with it's ID is received
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_TX_RTR_RX_DATA:
|
||||
// Setup object to send RTR and receive data response
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_TX:
|
||||
// Setup object to be used for sending messages
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_RX:
|
||||
// Setup object to be used for receiving messages
|
||||
// ..
|
||||
break;
|
||||
default:
|
||||
// Handle unknown object configuration code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
// Add code to send requested message
|
||||
// ..
|
||||
|
||||
return ((int32_t)size);
|
||||
}
|
||||
|
||||
static int32_t CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
// Add code to read previously received message
|
||||
// (reception was started when object was configured for reception)
|
||||
// ..
|
||||
|
||||
return ((int32_t)size);
|
||||
}
|
||||
|
||||
static int32_t CAN_Control (uint32_t control, uint32_t arg) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (control & ARM_CAN_CONTROL_Msk) {
|
||||
case ARM_CAN_ABORT_MESSAGE_SEND:
|
||||
// Add code to abort message pending to be sent
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_SET_FD_MODE:
|
||||
// Add code to enable Flexible Data-rate mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_SET_TRANSCEIVER_DELAY:
|
||||
// Add code to set transceiver delay
|
||||
// ..
|
||||
break;
|
||||
default:
|
||||
// Handle unknown control code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static ARM_CAN_STATUS CAN_GetStatus (void) {
|
||||
|
||||
// Add code to return device bus and error status
|
||||
// ..
|
||||
}
|
||||
|
||||
|
||||
// IRQ handlers
|
||||
// Add interrupt routines to handle transmission, reception, error and status interrupts
|
||||
// ..
|
||||
|
||||
// CAN driver functions structure
|
||||
|
||||
ARM_DRIVER_CAN Driver_CAN = {
|
||||
CAN_GetVersion,
|
||||
CAN_GetCapabilities,
|
||||
CAN_Initialize,
|
||||
CAN_Uninitialize,
|
||||
CAN_PowerControl,
|
||||
CAN_GetClock,
|
||||
CAN_SetBitrate,
|
||||
CAN_SetMode,
|
||||
CAN_ObjectGetCapabilities,
|
||||
CAN_ObjectSetFilter,
|
||||
CAN_ObjectConfigure,
|
||||
CAN_MessageSend,
|
||||
CAN_MessageRead,
|
||||
CAN_Control,
|
||||
CAN_GetStatus
|
||||
};
|
||||
|
||||
@@ -0,0 +1,228 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_ETH_MAC.h"
|
||||
|
||||
#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_ETH_MAC_API_VERSION,
|
||||
ARM_ETH_MAC_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = {
|
||||
0, /* 1 = IPv4 header checksum verified on receive */
|
||||
0, /* 1 = IPv6 checksum verification supported on receive */
|
||||
0, /* 1 = UDP payload checksum verified on receive */
|
||||
0, /* 1 = TCP payload checksum verified on receive */
|
||||
0, /* 1 = ICMP payload checksum verified on receive */
|
||||
0, /* 1 = IPv4 header checksum generated on transmit */
|
||||
0, /* 1 = IPv6 checksum generation supported on transmit */
|
||||
0, /* 1 = UDP payload checksum generated on transmit */
|
||||
0, /* 1 = TCP payload checksum generated on transmit */
|
||||
0, /* 1 = ICMP payload checksum generated on transmit */
|
||||
0, /* Ethernet Media Interface type */
|
||||
0, /* 1 = driver provides initial valid MAC address */
|
||||
0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated */
|
||||
0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated */
|
||||
0, /* 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated */
|
||||
0 /* 1 = Precision Timer supported */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_ETH_MAC_GetRxFrameSize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control)
|
||||
{
|
||||
case ARM_ETH_MAC_CONFIGURE:
|
||||
|
||||
switch (arg & ARM_ETH_MAC_SPEED_Msk)
|
||||
{
|
||||
case ARM_ETH_MAC_SPEED_10M:
|
||||
break;
|
||||
case ARM_ETH_SPEED_100M:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
|
||||
{
|
||||
case ARM_ETH_MAC_DUPLEX_FULL:
|
||||
break;
|
||||
}
|
||||
|
||||
if (arg & ARM_ETH_MAC_LOOPBACK)
|
||||
{
|
||||
}
|
||||
|
||||
if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||
|
||||
(arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST))
|
||||
{
|
||||
}
|
||||
|
||||
if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST)
|
||||
{
|
||||
}
|
||||
|
||||
if (arg & ARM_ETH_MAC_ADDRESS_ALL)
|
||||
{
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_CONTROL_TX:
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_CONTROL_RX:
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_FLUSH:
|
||||
if (arg & ARM_ETH_MAC_FLUSH_RX)
|
||||
{
|
||||
}
|
||||
if (arg & ARM_ETH_MAC_FLUSH_TX)
|
||||
{
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_SLEEP:
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_VLAN_FILTER:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_ETH_MAC_SignalEvent(uint32_t event)
|
||||
{
|
||||
}
|
||||
|
||||
// End ETH MAC Interface
|
||||
|
||||
ARM_DRIVER_ETH_MAC Driver_ETH_MAC =
|
||||
{
|
||||
ARM_ETH_MAC_GetVersion,
|
||||
ARM_ETH_MAC_GetCapabilities,
|
||||
ARM_ETH_MAC_Initialize,
|
||||
ARM_ETH_MAC_Uninitialize,
|
||||
ARM_ETH_MAC_PowerControl,
|
||||
ARM_ETH_MAC_GetMacAddress,
|
||||
ARM_ETH_MAC_SetMacAddress,
|
||||
ARM_ETH_MAC_SetAddressFilter,
|
||||
ARM_ETH_MAC_SendFrame,
|
||||
ARM_ETH_MAC_ReadFrame,
|
||||
ARM_ETH_MAC_GetRxFrameSize,
|
||||
ARM_ETH_MAC_GetRxFrameTime,
|
||||
ARM_ETH_MAC_GetTxFrameTime,
|
||||
ARM_ETH_MAC_ControlTimer,
|
||||
ARM_ETH_MAC_Control,
|
||||
ARM_ETH_MAC_PHY_Read,
|
||||
ARM_ETH_MAC_PHY_Write
|
||||
};
|
||||
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_ETH_PHY.h"
|
||||
|
||||
#define ARM_ETH_PHY_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_ETH_PHY_API_VERSION,
|
||||
ARM_ETH_PHY_DRV_VERSION
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_SetInterface(uint32_t interface)
|
||||
{
|
||||
switch (interface)
|
||||
{
|
||||
case ARM_ETH_INTERFACE_MII:
|
||||
break;
|
||||
case ARM_ETH_INTERFACE_RMII:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_SetMode(uint32_t mode)
|
||||
{
|
||||
switch (mode & ARM_ETH_PHY_SPEED_Msk)
|
||||
{
|
||||
case ARM_ETH_PHY_SPEED_10M:
|
||||
break;
|
||||
case ARM_ETH_PHY_SPEED_100M:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
switch (mode & ARM_ETH_PHY_DUPLEX_Msk)
|
||||
{
|
||||
case ARM_ETH_PHY_DUPLEX_HALF:
|
||||
break;
|
||||
case ARM_ETH_PHY_DUPLEX_FULL:
|
||||
break;
|
||||
}
|
||||
|
||||
if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE)
|
||||
{
|
||||
}
|
||||
|
||||
if (mode & ARM_ETH_PHY_LOOPBACK)
|
||||
{
|
||||
}
|
||||
|
||||
if (mode & ARM_ETH_PHY_ISOLATE)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM) =
|
||||
{
|
||||
ARM_ETH_PHY_GetVersion,
|
||||
ARM_ETH_PHY_Initialize,
|
||||
ARM_ETH_PHY_Uninitialize,
|
||||
ARM_ETH_PHY_PowerControl,
|
||||
ARM_ETH_PHY_SetInterface,
|
||||
ARM_ETH_PHY_SetMode,
|
||||
ARM_ETH_PHY_GetLinkState,
|
||||
ARM_ETH_PHY_GetLinkInfo,
|
||||
};
|
||||
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_Flash.h"
|
||||
|
||||
#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Sector Information */
|
||||
#ifdef FLASH_SECTORS
|
||||
static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = {
|
||||
FLASH_SECTORS
|
||||
};
|
||||
#else
|
||||
#define FLASH_SECTOR_INFO NULL
|
||||
#endif
|
||||
|
||||
/* Flash Information */
|
||||
static ARM_FLASH_INFO FlashInfo = {
|
||||
0, /* FLASH_SECTOR_INFO */
|
||||
0, /* FLASH_SECTOR_COUNT */
|
||||
0, /* FLASH_SECTOR_SIZE */
|
||||
0, /* FLASH_PAGE_SIZE */
|
||||
0, /* FLASH_PROGRAM_UNIT */
|
||||
0 /* FLASH_ERASED_VALUE */
|
||||
};
|
||||
|
||||
/* Flash Status */
|
||||
static ARM_FLASH_STATUS FlashStatus;
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_FLASH_API_VERSION,
|
||||
ARM_FLASH_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
|
||||
0, /* event_ready */
|
||||
0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
|
||||
0 /* erase_chip */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_EraseSector(uint32_t addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_EraseChip(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_Flash_SignalEvent(uint32_t event)
|
||||
{
|
||||
}
|
||||
// End Flash Interface
|
||||
|
||||
ARM_DRIVER_FLASH Driver_FLASH = {
|
||||
ARM_Flash_GetVersion,
|
||||
ARM_Flash_GetCapabilities,
|
||||
ARM_Flash_Initialize,
|
||||
ARM_Flash_Uninitialize,
|
||||
ARM_Flash_PowerControl,
|
||||
ARM_Flash_ReadData,
|
||||
ARM_Flash_ProgramData,
|
||||
ARM_Flash_EraseSector,
|
||||
ARM_Flash_EraseChip,
|
||||
ARM_Flash_GetStatus,
|
||||
ARM_Flash_GetInfo
|
||||
};
|
||||
@@ -0,0 +1,148 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_I2C.h"
|
||||
|
||||
#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_I2C_API_VERSION,
|
||||
ARM_I2C_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_I2C_CAPABILITIES DriverCapabilities = {
|
||||
0 /* supports 10-bit addressing */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_GetDataCount(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control)
|
||||
{
|
||||
case ARM_I2C_OWN_ADDRESS:
|
||||
break;
|
||||
|
||||
case ARM_I2C_BUS_SPEED:
|
||||
switch (arg)
|
||||
{
|
||||
case ARM_I2C_BUS_SPEED_STANDARD:
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_FAST:
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_FAST_PLUS:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_I2C_BUS_CLEAR:
|
||||
break;
|
||||
|
||||
case ARM_I2C_ABORT_TRANSFER:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
ARM_I2C_STATUS ARM_I2C_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_I2C_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End I2C Interface
|
||||
|
||||
ARM_DRIVER_I2C Driver_I2C = {
|
||||
ARM_I2C_GetVersion,
|
||||
ARM_I2C_GetCapabilities,
|
||||
ARM_I2C_Initialize,
|
||||
ARM_I2C_Uninitialize,
|
||||
ARM_I2C_PowerControl,
|
||||
ARM_I2C_MasterTransmit,
|
||||
ARM_I2C_MasterReceive,
|
||||
ARM_I2C_SlaveTransmit,
|
||||
ARM_I2C_SlaveReceive,
|
||||
ARM_I2C_GetDataCount,
|
||||
ARM_I2C_Control,
|
||||
ARM_I2C_GetStatus
|
||||
};
|
||||
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_MCI.h"
|
||||
|
||||
#define ARM_MCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_MCI_API_VERSION,
|
||||
ARM_MCI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_MCI_CAPABILITIES DriverCapabilities = {
|
||||
0, /* cd_state */
|
||||
0, /* cd_event */
|
||||
0, /* vdd */
|
||||
0, /* vdd_1v8 */
|
||||
0, /* vccq */
|
||||
0, /* vccq_1v8 */
|
||||
0, /* vccq_1v2 */
|
||||
1, /* data_width_4 */
|
||||
1, /* data_width_8 */
|
||||
0, /* data_width_4_ddr */
|
||||
0, /* data_width_8_ddr */
|
||||
0, /* high_speed */
|
||||
0, /* uhs_signaling */
|
||||
0, /* uhs_tuning */
|
||||
0, /* uhs_sdr50 */
|
||||
0, /* uhs_sdr104 */
|
||||
0, /* uhs_ddr50 */
|
||||
0, /* uhs_driver_type_a */
|
||||
0, /* uhs_driver_type_c */
|
||||
0, /* uhs_driver_type_d */
|
||||
1, /* sdio_interrupt */
|
||||
1, /* read_wait */
|
||||
0, /* suspend_resume */
|
||||
0, /* mmc_interrupt */
|
||||
0, /* mmc_boot */
|
||||
0, /* ccs */
|
||||
0 /* ccs_timeout */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_MCI_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_CardPower(uint32_t voltage)
|
||||
{
|
||||
switch (voltage & ARM_MCI_POWER_VDD_Msk)
|
||||
{
|
||||
case ARM_MCI_POWER_VDD_OFF:
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
case ARM_MCI_POWER_VDD_3V3:
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_ReadCD(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_ReadWP(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_SetupTransfer(uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_AbortTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control)
|
||||
{
|
||||
case ARM_MCI_BUS_SPEED:
|
||||
break;
|
||||
|
||||
case ARM_MCI_BUS_SPEED_MODE:
|
||||
break;
|
||||
|
||||
case ARM_MCI_BUS_CMD_MODE:
|
||||
/* Implement external pull-up control to support MMC cards in open-drain mode */
|
||||
/* Default mode is push-pull and is configured in Driver_MCI0.Initialize() */
|
||||
if (arg == ARM_MCI_BUS_CMD_PUSH_PULL)
|
||||
{
|
||||
/* Configure external circuit to work in push-pull mode */
|
||||
}
|
||||
else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN)
|
||||
{
|
||||
/* Configure external circuit to work in open-drain mode */
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_MCI_BUS_DATA_WIDTH:
|
||||
switch (arg)
|
||||
{
|
||||
case ARM_MCI_BUS_DATA_WIDTH_1:
|
||||
break;
|
||||
case ARM_MCI_BUS_DATA_WIDTH_4:
|
||||
break;
|
||||
case ARM_MCI_BUS_DATA_WIDTH_8:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_MCI_CONTROL_RESET:
|
||||
break;
|
||||
|
||||
case ARM_MCI_CONTROL_CLOCK_IDLE:
|
||||
break;
|
||||
|
||||
case ARM_MCI_DATA_TIMEOUT:
|
||||
break;
|
||||
|
||||
case ARM_MCI_MONITOR_SDIO_INTERRUPT:
|
||||
break;
|
||||
|
||||
case ARM_MCI_CONTROL_READ_WAIT:
|
||||
break;
|
||||
|
||||
case ARM_MCI_DRIVER_STRENGTH:
|
||||
default: return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
ARM_MCI_STATUS ARM_MCI_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_MCI_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End MCI Interface
|
||||
|
||||
ARM_DRIVER_MCI Driver_MCI = {
|
||||
ARM_MCI_GetVersion,
|
||||
ARM_MCI_GetCapabilities,
|
||||
ARM_MCI_Initialize,
|
||||
ARM_MCI_Uninitialize,
|
||||
ARM_MCI_PowerControl,
|
||||
ARM_MCI_CardPower,
|
||||
ARM_MCI_ReadCD,
|
||||
ARM_MCI_ReadWP,
|
||||
ARM_MCI_SendCommand,
|
||||
ARM_MCI_SetupTransfer,
|
||||
ARM_MCI_AbortTransfer,
|
||||
ARM_MCI_Control,
|
||||
ARM_MCI_GetStatus
|
||||
};
|
||||
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_SAI.h"
|
||||
|
||||
#define ARM_SAI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_SAI_API_VERSION,
|
||||
ARM_SAI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_SAI_CAPABILITIES DriverCapabilities = {
|
||||
1, /* supports asynchronous Transmit/Receive */
|
||||
0, /* supports synchronous Transmit/Receive */
|
||||
0, /* supports user defined Protocol */
|
||||
1, /* supports I2S Protocol */
|
||||
0, /* supports MSB/LSB justified Protocol */
|
||||
0, /* supports PCM short/long frame Protocol */
|
||||
0, /* supports AC'97 Protocol */
|
||||
0, /* supports Mono mode */
|
||||
0, /* supports Companding */
|
||||
0, /* supports MCLK (Master Clock) pin */
|
||||
0 /* supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Uninitialize (void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Send (const void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Receive (void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_SAI_GetTxCount (void)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_SAI_GetRxCount (void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_SAI_STATUS ARM_SAI_GetStatus (void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_SAI_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End SAI Interface
|
||||
|
||||
ARM_DRIVER_SAI Driver_SAI = {
|
||||
ARM_SAI_GetVersion,
|
||||
ARM_SAI_GetCapabilities,
|
||||
ARM_SAI_Initialize,
|
||||
ARM_SAI_Uninitialize,
|
||||
ARM_SAI_PowerControl,
|
||||
ARM_SAI_Send,
|
||||
ARM_SAI_Receive,
|
||||
ARM_SAI_GetTxCount,
|
||||
ARM_SAI_GetRxCount,
|
||||
ARM_SAI_Control,
|
||||
ARM_SAI_GetStatus
|
||||
};
|
||||
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_SPI.h"
|
||||
|
||||
#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_SPI_API_VERSION,
|
||||
ARM_SPI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_SPI_CAPABILITIES DriverCapabilities = {
|
||||
1, /* Simplex Mode (Master and Slave) */
|
||||
1, /* TI Synchronous Serial Interface */
|
||||
1, /* Microwire Interface */
|
||||
0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_SPI_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_Send(const void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_Receive(void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_SPI_GetDataCount(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SPI_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control & ARM_SPI_CONTROL_Msk)
|
||||
{
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
|
||||
case ARM_SPI_MODE_INACTIVE: // SPI Inactive
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
case ARM_SPI_MODE_MASTER: // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
|
||||
break;
|
||||
|
||||
case ARM_SPI_MODE_SLAVE: // SPI Slave (Output on MISO, Input on MOSI)
|
||||
break;
|
||||
|
||||
case ARM_SPI_MODE_MASTER_SIMPLEX: // SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
|
||||
case ARM_SPI_MODE_SLAVE_SIMPLEX: // SPI Slave (Output/Input on MISO)
|
||||
return ARM_SPI_ERROR_MODE;
|
||||
|
||||
case ARM_SPI_SET_BUS_SPEED: // Set Bus Speed in bps; arg = value
|
||||
break;
|
||||
|
||||
case ARM_SPI_GET_BUS_SPEED: // Get Bus Speed in bps
|
||||
break;
|
||||
|
||||
case ARM_SPI_SET_DEFAULT_TX_VALUE: // Set default Transmit value; arg = value
|
||||
break;
|
||||
|
||||
case ARM_SPI_CONTROL_SS: // Control Slave Select; arg = 0:inactive, 1:active
|
||||
break;
|
||||
|
||||
case ARM_SPI_ABORT_TRANSFER: // Abort current data transfer
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ARM_SPI_STATUS ARM_SPI_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_SPI_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End SPI Interface
|
||||
|
||||
ARM_DRIVER_SPI Driver_SPI = {
|
||||
ARM_SPI_GetVersion,
|
||||
ARM_SPI_GetCapabilities,
|
||||
ARM_SPI_Initialize,
|
||||
ARM_SPI_Uninitialize,
|
||||
ARM_SPI_PowerControl,
|
||||
ARM_SPI_Send,
|
||||
ARM_SPI_Receive,
|
||||
ARM_SPI_Transfer,
|
||||
ARM_SPI_GetDataCount,
|
||||
ARM_SPI_Control,
|
||||
ARM_SPI_GetStatus
|
||||
};
|
||||
@@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#include "Driver_Storage.h"
|
||||
|
||||
#define ARM_STORAGE_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_STORAGE_API_VERSION,
|
||||
ARM_STORAGE_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_STORAGE_CAPABILITIES DriverCapabilities = {
|
||||
1, /* Asynchronous Mode */
|
||||
1, /* Supports EraseAll operation */
|
||||
0 /* Reserved */
|
||||
};
|
||||
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_Storage_GetVersion (void) {
|
||||
}
|
||||
|
||||
ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_Uninitialize (void) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_EraseAll (void) {
|
||||
}
|
||||
|
||||
ARM_STORAGE_STATUS ARM_Storage_GetStatus (void) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info) {
|
||||
}
|
||||
|
||||
uint32_t ARM_Storage_ResolveAddress(uint64_t addr) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block) {
|
||||
}
|
||||
|
||||
int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block) {
|
||||
}
|
||||
// End Storage Interface
|
||||
|
||||
ARM_DRIVER_STORAGE Driver_STORAGE = {
|
||||
ARM_Storage_GetVersion,
|
||||
ARM_Storage_GetCapabilities,
|
||||
ARM_Storage_Initialize,
|
||||
ARM_Storage_Uninitialize,
|
||||
ARM_Storage_PowerControl,
|
||||
ARM_Storage_ReadData,
|
||||
ARM_Storage_ProgramData,
|
||||
ARM_Storage_Erase,
|
||||
ARM_Storage_EraseAll,
|
||||
ARM_Storage_GetStatus,
|
||||
ARM_Storage_GetInfo,
|
||||
ARM_Storage_ResolveAddress,
|
||||
ARM_Storage_GetNextBlock,
|
||||
ARM_Storage_GetBlock
|
||||
};
|
||||
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_USART.h"
|
||||
|
||||
#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_USART_API_VERSION,
|
||||
ARM_USART_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_USART_CAPABILITIES DriverCapabilities = {
|
||||
1, /* supports UART (Asynchronous) mode */
|
||||
0, /* supports Synchronous Master mode */
|
||||
0, /* supports Synchronous Slave mode */
|
||||
0, /* supports UART Single-wire mode */
|
||||
0, /* supports UART IrDA mode */
|
||||
0, /* supports UART Smart Card mode */
|
||||
0, /* Smart Card Clock generator available */
|
||||
0, /* RTS Flow Control available */
|
||||
0, /* CTS Flow Control available */
|
||||
0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */
|
||||
0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */
|
||||
0, /* RTS Line: 0=not available, 1=available */
|
||||
0, /* CTS Line: 0=not available, 1=available */
|
||||
0, /* DTR Line: 0=not available, 1=available */
|
||||
0, /* DSR Line: 0=not available, 1=available */
|
||||
0, /* DCD Line: 0=not available, 1=available */
|
||||
0, /* RI Line: 0=not available, 1=available */
|
||||
0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */
|
||||
0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */
|
||||
0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */
|
||||
0 /* Signal RI change event: \ref ARM_USART_EVENT_RI */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_USART_Send(const void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_Receive(void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_USART_GetTxCount(void)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_USART_GetRxCount(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USART_STATUS ARM_USART_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_USART_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End USART Interface
|
||||
|
||||
ARM_DRIVER_USART Driver_USART = {
|
||||
ARM_USART_GetVersion,
|
||||
ARM_USART_GetCapabilities,
|
||||
ARM_USART_Initialize,
|
||||
ARM_USART_Uninitialize,
|
||||
ARM_USART_PowerControl,
|
||||
ARM_USART_Send,
|
||||
ARM_USART_Receive,
|
||||
ARM_USART_Transfer,
|
||||
ARM_USART_GetTxCount,
|
||||
ARM_USART_GetRxCount,
|
||||
ARM_USART_Control,
|
||||
ARM_USART_GetStatus,
|
||||
ARM_USART_SetModemControl,
|
||||
ARM_USART_GetModemStatus
|
||||
};
|
||||
@@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_USBD.h"
|
||||
|
||||
#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION usbd_driver_version = {
|
||||
ARM_USBD_API_VERSION,
|
||||
ARM_USBD_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
|
||||
0, /* vbus_detection */
|
||||
0, /* event_vbus_on */
|
||||
0 /* event_vbus_off */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_USBD_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event,
|
||||
ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_DeviceConnect(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_DeviceDisconnect(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USBD_STATE ARM_USBD_DeviceGetState(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_DeviceRemoteWakeup(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_EndpointConfigure(uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_max_packet_size)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr)
|
||||
{
|
||||
}
|
||||
|
||||
uint16_t ARM_USBD_GetFrameNumber(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_USBD_SignalDeviceEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End USBD Interface
|
||||
|
||||
ARM_DRIVER_USBD Driver_USBD =
|
||||
{
|
||||
ARM_USBD_GetVersion,
|
||||
ARM_USBD_GetCapabilities,
|
||||
ARM_USBD_Initialize,
|
||||
ARM_USBD_Uninitialize,
|
||||
ARM_USBD_PowerControl,
|
||||
ARM_USBD_DeviceConnect,
|
||||
ARM_USBD_DeviceDisconnect,
|
||||
ARM_USBD_DeviceGetState,
|
||||
ARM_USBD_DeviceRemoteWakeup,
|
||||
ARM_USBD_DeviceSetAddress,
|
||||
ARM_USBD_ReadSetupPacket,
|
||||
ARM_USBD_EndpointConfigure,
|
||||
ARM_USBD_EndpointUnconfigure,
|
||||
ARM_USBD_EndpointStall,
|
||||
ARM_USBD_EndpointTransfer,
|
||||
ARM_USBD_EndpointTransferGetResult,
|
||||
ARM_USBD_EndpointTransferAbort,
|
||||
ARM_USBD_GetFrameNumber
|
||||
};
|
||||
@@ -0,0 +1,225 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_USBH.h"
|
||||
|
||||
/* USB Host Driver */
|
||||
|
||||
#define ARM_USBH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION usbh_driver_version = {
|
||||
ARM_USBH_API_VERSION,
|
||||
ARM_USBH_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_USBH_CAPABILITIES usbd_driver_capabilities = {
|
||||
0x0001, /* Root HUB available Ports Mask */
|
||||
0, /* Automatic SPLIT packet handling */
|
||||
0, /* Signal Connect event */
|
||||
0, /* Signal Disconnect event */
|
||||
0 /* Signal Overcurrent event */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_USBH_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event,
|
||||
ARM_USBH_SignalEndpointEvent_t cb_endpoint_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_PortReset(uint8_t port)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_PortSuspend(uint8_t port)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_PortResume(uint8_t port)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USBH_EP_HANDLE ARM_USBH_EndpointCreate(uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t hub_addr,
|
||||
uint8_t hub_port,
|
||||
uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_max_packet_size,
|
||||
uint8_t ep_interval)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_EndpointModify(ARM_USBH_EP_HANDLE ep_hndl,
|
||||
uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t hub_addr,
|
||||
uint8_t hub_port,
|
||||
uint16_t ep_max_packet_size)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_EndpointDelete(ARM_USBH_EP_HANDLE ep_hndl)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_EndpointReset(ARM_USBH_EP_HANDLE ep_hndl)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_EndpointTransfer(ARM_USBH_EP_HANDLE ep_hndl,
|
||||
uint32_t packet,
|
||||
uint8_t *data,
|
||||
uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_USBH_EndpointTransferGetResult(ARM_USBH_EP_HANDLE ep_hndl)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_EndpointTransferAbort(ARM_USBH_EP_HANDLE ep_hndl)
|
||||
{
|
||||
}
|
||||
|
||||
uint16_t ARM_USBH_GetFrameNumber(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
void ARM_USBH_SignalEndpointEvent(ARM_USBH_EP_HANDLE ep_hndl, uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
/* USB Host HCI (OHCI/EHCI) Driver */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION usbh_hci_driver_version = {
|
||||
ARM_USBH_API_VERSION,
|
||||
ARM_USBH_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_USBH_HCI_CAPABILITIES usbh_hci_driver_capabilities = {
|
||||
0x0001 /* Root HUB available Ports Mask */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_HCI_Initialize(ARM_USBH_HCI_Interrupt_t cb_interrupt)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_HCI_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_HCI_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_USBH_HCI_PortVbusOnOff(uint8_t port, bool vbus)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_USBH_HCI_Interrupt(void)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End USBH Interface
|
||||
|
||||
ARM_DRIVER_USBH_HCI Driver_USBH_HCI = {
|
||||
ARM_USBH_HCI_GetVersion,
|
||||
ARM_USBH_HCI_GetCapabilities,
|
||||
ARM_USBH_HCI_Initialize,
|
||||
ARM_USBH_HCI_Uninitialize,
|
||||
ARM_USBH_HCI_PowerControl,
|
||||
ARM_USBH_HCI_PortVbusOnOff
|
||||
};
|
||||
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V1.1
|
||||
*
|
||||
* Project: CAN (Controller Area Network) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 1.1
|
||||
* ARM_CAN_STATUS made volatile
|
||||
* Version 1.0
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_CAN_H_
|
||||
#define DRIVER_CAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1) /* API version */
|
||||
|
||||
|
||||
/****** CAN Bitrate selection codes *****/
|
||||
typedef enum _ARM_CAN_BITRATE_SELECT {
|
||||
ARM_CAN_BITRATE_NOMINAL, ///< Select nominal (flexible data-rate arbitration) bitrate
|
||||
ARM_CAN_BITRATE_FD_DATA ///< Select flexible data-rate data bitrate
|
||||
} ARM_CAN_BITRATE_SELECT;
|
||||
|
||||
/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/
|
||||
#define ARM_CAN_BIT_PROP_SEG_Pos 0UL ///< bits 7..0
|
||||
#define ARM_CAN_BIT_PROP_SEG_Msk (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)
|
||||
#define ARM_CAN_BIT_PROP_SEG(x) (((x) << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)
|
||||
|
||||
/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/
|
||||
#define ARM_CAN_BIT_PHASE_SEG1_Pos 8UL ///< bits 15..8
|
||||
#define ARM_CAN_BIT_PHASE_SEG1_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)
|
||||
#define ARM_CAN_BIT_PHASE_SEG1(x) (((x) << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)
|
||||
|
||||
/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/
|
||||
#define ARM_CAN_BIT_PHASE_SEG2_Pos 16UL ///< bits 23..16
|
||||
#define ARM_CAN_BIT_PHASE_SEG2_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)
|
||||
#define ARM_CAN_BIT_PHASE_SEG2(x) (((x) << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)
|
||||
|
||||
/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/
|
||||
#define ARM_CAN_BIT_SJW_Pos 24UL ///< bits 28..24
|
||||
#define ARM_CAN_BIT_SJW_Msk (0x1FUL << ARM_CAN_BIT_SJW_Pos)
|
||||
#define ARM_CAN_BIT_SJW(x) (((x) << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)
|
||||
|
||||
/****** CAN Mode codes *****/
|
||||
typedef enum _ARM_CAN_MODE {
|
||||
ARM_CAN_MODE_INITIALIZATION, ///< Initialization mode
|
||||
ARM_CAN_MODE_NORMAL, ///< Normal operation mode
|
||||
ARM_CAN_MODE_RESTRICTED, ///< Restricted operation mode
|
||||
ARM_CAN_MODE_MONITOR, ///< Bus monitoring mode
|
||||
ARM_CAN_MODE_LOOPBACK_INTERNAL, ///< Loopback internal mode
|
||||
ARM_CAN_MODE_LOOPBACK_EXTERNAL ///< Loopback external mode
|
||||
} ARM_CAN_MODE;
|
||||
|
||||
/****** CAN Filter Operation codes *****/
|
||||
typedef enum _ARM_CAN_FILTER_OPERATION {
|
||||
ARM_CAN_FILTER_ID_EXACT_ADD, ///< Add exact id filter
|
||||
ARM_CAN_FILTER_ID_EXACT_REMOVE, ///< Remove exact id filter
|
||||
ARM_CAN_FILTER_ID_RANGE_ADD, ///< Add range id filter
|
||||
ARM_CAN_FILTER_ID_RANGE_REMOVE, ///< Remove range id filter
|
||||
ARM_CAN_FILTER_ID_MASKABLE_ADD, ///< Add maskable id filter
|
||||
ARM_CAN_FILTER_ID_MASKABLE_REMOVE ///< Remove maskable id filter
|
||||
} ARM_CAN_FILTER_OPERATION;
|
||||
|
||||
/****** CAN Object Configuration codes *****/
|
||||
typedef enum _ARM_CAN_OBJ_CONFIG {
|
||||
ARM_CAN_OBJ_INACTIVE, ///< CAN object inactive
|
||||
ARM_CAN_OBJ_TX, ///< CAN transmit object
|
||||
ARM_CAN_OBJ_RX, ///< CAN receive object
|
||||
ARM_CAN_OBJ_RX_RTR_TX_DATA, ///< CAN object that on RTR reception automatically transmits Data Frame
|
||||
ARM_CAN_OBJ_TX_RTR_RX_DATA ///< CAN object that transmits RTR and automatically receives Data Frame
|
||||
} ARM_CAN_OBJ_CONFIG;
|
||||
|
||||
/**
|
||||
\brief CAN Object Capabilities
|
||||
*/
|
||||
typedef struct _ARM_CAN_OBJ_CAPABILITIES {
|
||||
uint32_t tx : 1; ///< Object supports transmission
|
||||
uint32_t rx : 1; ///< Object supports reception
|
||||
uint32_t rx_rtr_tx_data : 1; ///< Object supports RTR reception and automatic Data Frame transmission
|
||||
uint32_t tx_rtr_rx_data : 1; ///< Object supports RTR transmission and automatic Data Frame reception
|
||||
uint32_t multiple_filters : 1; ///< Object allows assignment of multiple filters to it
|
||||
uint32_t exact_filtering : 1; ///< Object supports exact identifier filtering
|
||||
uint32_t range_filtering : 1; ///< Object supports range identifier filtering
|
||||
uint32_t mask_filtering : 1; ///< Object supports mask identifier filtering
|
||||
uint32_t message_depth : 8; ///< Number of messages buffers (FIFO) for that object
|
||||
uint32_t reserved : 16; ///< Reserved (must be zero)
|
||||
} ARM_CAN_OBJ_CAPABILITIES;
|
||||
|
||||
/****** CAN Control Function Operation codes *****/
|
||||
#define ARM_CAN_CONTROL_Pos 0UL
|
||||
#define ARM_CAN_CONTROL_Msk (0xFFUL << ARM_CAN_CONTROL_Pos)
|
||||
#define ARM_CAN_SET_FD_MODE (1UL << ARM_CAN_CONTROL_Pos) ///< Set FD operation mode; arg: 0 = disable, 1 = enable
|
||||
#define ARM_CAN_ABORT_MESSAGE_SEND (2UL << ARM_CAN_CONTROL_Pos) ///< Abort sending of CAN message; arg = object
|
||||
#define ARM_CAN_CONTROL_RETRANSMISSION (3UL << ARM_CAN_CONTROL_Pos) ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)
|
||||
#define ARM_CAN_SET_TRANSCEIVER_DELAY (4UL << ARM_CAN_CONTROL_Pos) ///< Set transceiver delay; arg = delay in time quanta
|
||||
|
||||
/****** CAN ID Frame Format codes *****/
|
||||
#define ARM_CAN_ID_IDE_Pos 31UL
|
||||
#define ARM_CAN_ID_IDE_Msk (1UL << ARM_CAN_ID_IDE_Pos)
|
||||
|
||||
/****** CAN Identifier encoding *****/
|
||||
#define ARM_CAN_STANDARD_ID(id) (id & 0x000007FFUL) ///< CAN identifier in standard format (11-bits)
|
||||
#define ARM_CAN_EXTENDED_ID(id) ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)
|
||||
|
||||
/**
|
||||
\brief CAN Message Information
|
||||
*/
|
||||
typedef struct _ARM_CAN_MSG_INFO {
|
||||
uint32_t id; ///< CAN identifier with frame format specifier (bit 31)
|
||||
uint32_t rtr : 1; ///< Remote transmission request frame
|
||||
uint32_t edl : 1; ///< Flexible data-rate format extended data length
|
||||
uint32_t brs : 1; ///< Flexible data-rate format with bitrate switch
|
||||
uint32_t esi : 1; ///< Flexible data-rate format error state indicator
|
||||
uint32_t dlc : 4; ///< Data length code
|
||||
uint32_t reserved : 24;
|
||||
} ARM_CAN_MSG_INFO;
|
||||
|
||||
/****** CAN specific error code *****/
|
||||
#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Bitrate selection not supported
|
||||
#define ARM_CAN_INVALID_BITRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Requested bitrate not supported
|
||||
#define ARM_CAN_INVALID_BIT_PROP_SEG (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Propagation segment value not supported
|
||||
#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Phase segment 1 value not supported
|
||||
#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Phase segment 2 value not supported
|
||||
#define ARM_CAN_INVALID_BIT_SJW (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< SJW value not supported
|
||||
#define ARM_CAN_NO_MESSAGE_AVAILABLE (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Message is not available
|
||||
|
||||
/****** CAN Status codes *****/
|
||||
#define ARM_CAN_UNIT_STATE_INACTIVE (0U) ///< Unit state: Not active on bus (initialize or error bus off)
|
||||
#define ARM_CAN_UNIT_STATE_ACTIVE (1U) ///< Unit state: Active on bus (can generate active error frame)
|
||||
#define ARM_CAN_UNIT_STATE_PASSIVE (2U) ///< Unit state: Error passive (can not generate active error frame)
|
||||
#define ARM_CAN_LEC_NO_ERROR (0U) ///< Last error code: No error
|
||||
#define ARM_CAN_LEC_BIT_ERROR (1U) ///< Last error code: Bit error
|
||||
#define ARM_CAN_LEC_STUFF_ERROR (2U) ///< Last error code: Bit stuffing error
|
||||
#define ARM_CAN_LEC_CRC_ERROR (3U) ///< Last error code: CRC error
|
||||
#define ARM_CAN_LEC_FORM_ERROR (4U) ///< Last error code: Illegal fixed-form bit
|
||||
#define ARM_CAN_LEC_ACK_ERROR (5U) ///< Last error code: Acknowledgment error
|
||||
|
||||
/**
|
||||
\brief CAN Status
|
||||
*/
|
||||
typedef volatile struct _ARM_CAN_STATUS {
|
||||
uint32_t unit_state : 4; ///< Unit bus state
|
||||
uint32_t last_error_code : 4; ///< Last error code
|
||||
uint32_t tx_error_count : 8; ///< Transmitter error count
|
||||
uint32_t rx_error_count : 8; ///< Receiver error count
|
||||
uint32_t reserved : 8;
|
||||
} ARM_CAN_STATUS;
|
||||
|
||||
|
||||
/****** CAN Unit Event *****/
|
||||
#define ARM_CAN_EVENT_UNIT_ACTIVE (1U) ///< Unit entered Error Active state
|
||||
#define ARM_CAN_EVENT_UNIT_WARNING (2U) ///< Unit entered Error Warning state (one or both error counters >= 96)
|
||||
#define ARM_CAN_EVENT_UNIT_PASSIVE (3U) ///< Unit entered Error Passive state
|
||||
#define ARM_CAN_EVENT_UNIT_BUS_OFF (4U) ///< Unit entered bus off state
|
||||
|
||||
/****** CAN Send/Receive Event *****/
|
||||
#define ARM_CAN_EVENT_SEND_COMPLETE (1UL << 0) ///< Send complete
|
||||
#define ARM_CAN_EVENT_RECEIVE (1UL << 1) ///< Message received
|
||||
#define ARM_CAN_EVENT_RECEIVE_OVERRUN (1UL << 2) ///< Received message overrun
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_CAN_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event,
|
||||
ARM_CAN_SignalObjectEvent_t cb_object_event)
|
||||
\brief Initialize CAN interface and register signal (callback) functions.
|
||||
\param[in] cb_unit_event Pointer to \ref ARM_CAN_SignalUnitEvent callback function
|
||||
\param[in] cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_Uninitialize (void)
|
||||
\brief De-initialize CAN interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control CAN interface power.
|
||||
\param[in] state Power state
|
||||
- \ref ARM_POWER_OFF : power off: no operation possible
|
||||
- \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events
|
||||
- \ref ARM_POWER_FULL : power on: full operation at maximum performance
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_CAN_GetClock (void)
|
||||
\brief Retrieve CAN base clock frequency.
|
||||
\return base clock frequency
|
||||
|
||||
\fn int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)
|
||||
\brief Set bitrate for CAN interface.
|
||||
\param[in] select Bitrate selection
|
||||
- \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
|
||||
- \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
|
||||
\param[in] bitrate Bitrate
|
||||
\param[in] bit_segments Bit segments settings
|
||||
- \ref ARM_CAN_BIT_PROP_SEG(x) : number of time quanta for propagation time segment
|
||||
- \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1
|
||||
- \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2
|
||||
- \ref ARM_CAN_BIT_SJW(x) : number of time quanta for (re-)synchronization jump width
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)
|
||||
\brief Set operating mode for CAN interface.
|
||||
\param[in] mode Operating mode
|
||||
- \ref ARM_CAN_MODE_INITIALIZATION : initialization mode
|
||||
- \ref ARM_CAN_MODE_NORMAL : normal operation mode
|
||||
- \ref ARM_CAN_MODE_RESTRICTED : restricted operation mode
|
||||
- \ref ARM_CAN_MODE_MONITOR : bus monitoring mode
|
||||
- \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
|
||||
- \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)
|
||||
\brief Retrieve capabilities of an object.
|
||||
\param[in] obj_idx Object index
|
||||
\return \ref ARM_CAN_OBJ_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)
|
||||
\brief Add or remove filter for message reception.
|
||||
\param[in] obj_idx Object index of object that filter should be or is assigned to
|
||||
\param[in] operation Operation on filter
|
||||
- \ref ARM_CAN_FILTER_ID_EXACT_ADD : add exact id filter
|
||||
- \ref ARM_CAN_FILTER_ID_EXACT_REMOVE : remove exact id filter
|
||||
- \ref ARM_CAN_FILTER_ID_RANGE_ADD : add range id filter
|
||||
- \ref ARM_CAN_FILTER_ID_RANGE_REMOVE : remove range id filter
|
||||
- \ref ARM_CAN_FILTER_ID_MASKABLE_ADD : add maskable id filter
|
||||
- \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
|
||||
\param[in] id ID or start of ID range (depending on filter type)
|
||||
\param[in] arg Mask or end of ID range (depending on filter type)
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)
|
||||
\brief Configure object.
|
||||
\param[in] obj_idx Object index
|
||||
\param[in] obj_cfg Object configuration state
|
||||
- \ref ARM_CAN_OBJ_INACTIVE : deactivate object
|
||||
- \ref ARM_CAN_OBJ_RX : configure object for reception
|
||||
- \ref ARM_CAN_OBJ_TX : configure object for transmission
|
||||
- \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
|
||||
- \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)
|
||||
\brief Send message on CAN bus.
|
||||
\param[in] obj_idx Object index
|
||||
\param[in] msg_info Pointer to CAN message information
|
||||
\param[in] data Pointer to data buffer
|
||||
\param[in] size Number of data bytes to send
|
||||
\return value >= 0 number of data bytes accepted to send
|
||||
\return value < 0 \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)
|
||||
\brief Read message received on CAN bus.
|
||||
\param[in] obj_idx Object index
|
||||
\param[out] msg_info Pointer to read CAN message information
|
||||
\param[out] data Pointer to data buffer for read data
|
||||
\param[in] size Maximum number of data bytes to read
|
||||
\return value >= 0 number of data bytes read
|
||||
\return value < 0 \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control CAN interface.
|
||||
\param[in] control Operation
|
||||
- \ref ARM_CAN_SET_FD_MODE : set FD operation mode
|
||||
- \ref ARM_CAN_ABORT_MESSAGE_SEND : abort sending of CAN message
|
||||
- \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
|
||||
- \ref ARM_CAN_SET_TRANSCEIVER_DELAY : set transceiver delay
|
||||
\param[in] arg Argument of operation
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_CAN_STATUS ARM_CAN_GetStatus (void)
|
||||
\brief Get CAN status.
|
||||
\return CAN status \ref ARM_CAN_STATUS
|
||||
|
||||
\fn void ARM_CAN_SignalUnitEvent (uint32_t event)
|
||||
\brief Signal CAN unit event.
|
||||
\param[in] event \ref CAN_unit_events
|
||||
\return none
|
||||
|
||||
\fn void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)
|
||||
\brief Signal CAN object event.
|
||||
\param[in] obj_idx Object index
|
||||
\param[in] event \ref CAN_events
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_CAN_SignalUnitEvent_t) (uint32_t event); ///< Pointer to \ref ARM_CAN_SignalUnitEvent : Signal CAN Unit Event.
|
||||
typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief CAN Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_CAN_CAPABILITIES {
|
||||
uint32_t num_objects : 8; ///< Number of \ref can_objects available
|
||||
uint32_t reentrant_operation : 1; ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control
|
||||
uint32_t fd_mode : 1; ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control)
|
||||
uint32_t restricted_mode : 1; ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t monitor_mode : 1; ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t internal_loopback : 1; ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t external_loopback : 1; ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t reserved : 18; ///< Reserved (must be zero)
|
||||
} ARM_CAN_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the CAN Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_CAN {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_CAN_GetVersion : Get driver version.
|
||||
ARM_CAN_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_CAN_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_CAN_SignalUnitEvent_t cb_unit_event,
|
||||
ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_CAN_Uninitialize : De-initialize CAN interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_CAN_PowerControl : Control CAN interface power.
|
||||
uint32_t (*GetClock) (void); ///< Pointer to \ref ARM_CAN_GetClock : Retrieve CAN base clock frequency.
|
||||
int32_t (*SetBitrate) (ARM_CAN_BITRATE_SELECT select,
|
||||
uint32_t bitrate,
|
||||
uint32_t bit_segments); ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.
|
||||
int32_t (*SetMode) (ARM_CAN_MODE mode); ///< Pointer to \ref ARM_CAN_SetMode : Set operating mode for CAN interface.
|
||||
ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.
|
||||
int32_t (*ObjectSetFilter) (uint32_t obj_idx,
|
||||
ARM_CAN_FILTER_OPERATION operation,
|
||||
uint32_t id,
|
||||
uint32_t arg); ///< Pointer to \ref ARM_CAN_ObjectSetFilter : Add or remove filter for message reception.
|
||||
int32_t (*ObjectConfigure) (uint32_t obj_idx,
|
||||
ARM_CAN_OBJ_CONFIG obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure : Configure object.
|
||||
int32_t (*MessageSend) (uint32_t obj_idx,
|
||||
ARM_CAN_MSG_INFO *msg_info,
|
||||
const uint8_t *data,
|
||||
uint8_t size); ///< Pointer to \ref ARM_CAN_MessageSend : Send message on CAN bus.
|
||||
int32_t (*MessageRead) (uint32_t obj_idx,
|
||||
ARM_CAN_MSG_INFO *msg_info,
|
||||
uint8_t *data,
|
||||
uint8_t size); ///< Pointer to \ref ARM_CAN_MessageRead : Read message received on CAN bus.
|
||||
int32_t (*Control) (uint32_t control,
|
||||
uint32_t arg); ///< Pointer to \ref ARM_CAN_Control : Control CAN interface.
|
||||
ARM_CAN_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_CAN_GetStatus : Get CAN status.
|
||||
} const ARM_DRIVER_CAN;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CAN_H_ */
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.0
|
||||
*
|
||||
* Project: Common Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.0
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Added General return codes definitions
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_COMMON_H_
|
||||
#define DRIVER_COMMON_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
|
||||
|
||||
/**
|
||||
\brief Driver Version
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_VERSION {
|
||||
uint16_t api; ///< API version
|
||||
uint16_t drv; ///< Driver version
|
||||
} ARM_DRIVER_VERSION;
|
||||
|
||||
/* General return codes */
|
||||
#define ARM_DRIVER_OK 0 ///< Operation succeeded
|
||||
#define ARM_DRIVER_ERROR -1 ///< Unspecified error
|
||||
#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
|
||||
#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
|
||||
#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
|
||||
#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
|
||||
#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
|
||||
|
||||
/**
|
||||
\brief General power states
|
||||
*/
|
||||
typedef enum _ARM_POWER_STATE {
|
||||
ARM_POWER_OFF, ///< Power off: no operation possible
|
||||
ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
|
||||
ARM_POWER_FULL ///< Power on: full operation at maximum performance
|
||||
} ARM_POWER_STATE;
|
||||
|
||||
#endif /* DRIVER_COMMON_H_ */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.1
|
||||
*
|
||||
* Project: Ethernet PHY and MAC Driver common definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.1
|
||||
* ARM_ETH_LINK_INFO made volatile
|
||||
* Version 2.0
|
||||
* Removed ARM_ETH_STATUS enumerator
|
||||
* Removed ARM_ETH_MODE enumerator
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ETH_H_
|
||||
#define DRIVER_ETH_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
/**
|
||||
\brief Ethernet Media Interface type
|
||||
*/
|
||||
#define ARM_ETH_INTERFACE_MII (0) ///< Media Independent Interface (MII)
|
||||
#define ARM_ETH_INTERFACE_RMII (1) ///< Reduced Media Independent Interface (RMII)
|
||||
#define ARM_ETH_INTERFACE_SMII (2) ///< Serial Media Independent Interface (SMII)
|
||||
|
||||
/**
|
||||
\brief Ethernet link speed
|
||||
*/
|
||||
#define ARM_ETH_SPEED_10M (0) ///< 10 Mbps link speed
|
||||
#define ARM_ETH_SPEED_100M (1) ///< 100 Mbps link speed
|
||||
#define ARM_ETH_SPEED_1G (2) ///< 1 Gpbs link speed
|
||||
|
||||
/**
|
||||
\brief Ethernet duplex mode
|
||||
*/
|
||||
#define ARM_ETH_DUPLEX_HALF (0) ///< Half duplex link
|
||||
#define ARM_ETH_DUPLEX_FULL (1) ///< Full duplex link
|
||||
|
||||
/**
|
||||
\brief Ethernet link state
|
||||
*/
|
||||
typedef enum _ARM_ETH_LINK_STATE {
|
||||
ARM_ETH_LINK_DOWN, ///< Link is down
|
||||
ARM_ETH_LINK_UP ///< Link is up
|
||||
} ARM_ETH_LINK_STATE;
|
||||
|
||||
/**
|
||||
\brief Ethernet link information
|
||||
*/
|
||||
typedef volatile struct _ARM_ETH_LINK_INFO {
|
||||
uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
|
||||
uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full
|
||||
uint32_t reserved : 29;
|
||||
} ARM_ETH_LINK_INFO;
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Address
|
||||
*/
|
||||
typedef struct _ARM_ETH_MAC_ADDR {
|
||||
uint8_t b[6]; ///< MAC Address (6 bytes), MSB first
|
||||
} ARM_ETH_MAC_ADDR;
|
||||
|
||||
#endif /* DRIVER_ETH_H_ */
|
||||
@@ -0,0 +1,308 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.1
|
||||
*
|
||||
* Project: Ethernet MAC (Media Access Control) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.1
|
||||
* Added ARM_ETH_MAC_SLEEP Control
|
||||
* Version 2.0
|
||||
* Changed MAC Address handling:
|
||||
* moved from ARM_ETH_MAC_Initialize
|
||||
* to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
|
||||
* Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
|
||||
* Extended ARM_ETH_MAC_SendFrame function with flags
|
||||
* Added ARM_ETH_MAC_Control function:
|
||||
* more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
|
||||
* replaces ARM_ETH_MAC_SetMode
|
||||
* replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
|
||||
* Added optional event on transmitted frame
|
||||
* Added support for PTP (Precision Time Protocol) through new functions:
|
||||
* ARM_ETH_MAC_ControlTimer
|
||||
* ARM_ETH_MAC_GetRxFrameTime
|
||||
* ARM_ETH_MAC_GetTxFrameTime
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Changed return values of some functions to int32_t
|
||||
* Version 1.10
|
||||
* Name space prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Renamed capabilities items for checksum offload
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ETH_MAC_H_
|
||||
#define DRIVER_ETH_MAC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_ETH.h"
|
||||
|
||||
#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_ETH_MAC_(n) Driver_ETH_MAC##n
|
||||
#define ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
|
||||
|
||||
|
||||
/****** Ethernet MAC Control Codes *****/
|
||||
|
||||
#define ARM_ETH_MAC_CONFIGURE (0x01) ///< Configure MAC; arg = configuration
|
||||
#define ARM_ETH_MAC_CONTROL_TX (0x02) ///< Transmitter; arg: 0=disabled (default), 1=enabled
|
||||
#define ARM_ETH_MAC_CONTROL_RX (0x03) ///< Receiver; arg: 0=disabled (default), 1=enabled
|
||||
#define ARM_ETH_MAC_FLUSH (0x04) ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
|
||||
#define ARM_ETH_MAC_SLEEP (0x05) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
|
||||
#define ARM_ETH_MAC_VLAN_FILTER (0x06) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
|
||||
|
||||
/*----- Ethernet MAC Configuration -----*/
|
||||
#define ARM_ETH_MAC_SPEED_Pos 0
|
||||
#define ARM_ETH_MAC_SPEED_Msk (3UL << ARM_ETH_MAC_SPEED_Pos)
|
||||
#define ARM_ETH_MAC_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed
|
||||
#define ARM_ETH_MAC_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed
|
||||
#define ARM_ETH_MAC_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed
|
||||
#define ARM_ETH_MAC_DUPLEX_Pos 2
|
||||
#define ARM_ETH_MAC_DUPLEX_Msk (1UL << ARM_ETH_MAC_DUPLEX_Pos)
|
||||
#define ARM_ETH_MAC_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
|
||||
#define ARM_ETH_MAC_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
|
||||
#define ARM_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode
|
||||
#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload
|
||||
#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload
|
||||
#define ARM_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address
|
||||
#define ARM_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address
|
||||
#define ARM_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode)
|
||||
|
||||
/*----- Ethernet MAC Flush Flags -----*/
|
||||
#define ARM_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer
|
||||
#define ARM_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer
|
||||
|
||||
/*----- Ethernet MAC VLAN Filter Flag -----*/
|
||||
#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
|
||||
|
||||
|
||||
/****** Ethernet MAC Frame Transmit Flags *****/
|
||||
#define ARM_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment
|
||||
#define ARM_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted
|
||||
#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp
|
||||
|
||||
|
||||
/****** Ethernet MAC Timer Control Codes *****/
|
||||
#define ARM_ETH_MAC_TIMER_GET_TIME (0x01) ///< Get current time
|
||||
#define ARM_ETH_MAC_TIMER_SET_TIME (0x02) ///< Set new time
|
||||
#define ARM_ETH_MAC_TIMER_INC_TIME (0x03) ///< Increment current time
|
||||
#define ARM_ETH_MAC_TIMER_DEC_TIME (0x04) ///< Decrement current time
|
||||
#define ARM_ETH_MAC_TIMER_SET_ALARM (0x05) ///< Set alarm time
|
||||
#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK (0x06) ///< Adjust clock frequency; time->ns: correction factor * 2^31
|
||||
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Time
|
||||
*/
|
||||
typedef struct _ARM_ETH_MAC_TIME {
|
||||
uint32_t ns; ///< Nano seconds
|
||||
uint32_t sec; ///< Seconds
|
||||
} ARM_ETH_MAC_TIME;
|
||||
|
||||
|
||||
/****** Ethernet MAC Event *****/
|
||||
#define ARM_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received
|
||||
#define ARM_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted
|
||||
#define ARM_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet)
|
||||
#define ARM_ETH_MAC_EVENT_TIMER_ALARM (1UL << 3) ///< Timer Alarm
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_ETH_MAC_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
|
||||
\brief Initialize Ethernet MAC Device.
|
||||
\param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_Uninitialize (void)
|
||||
\brief De-initialize Ethernet MAC Device.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control Ethernet MAC Device Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
\brief Get Ethernet MAC Address.
|
||||
\param[in] ptr_addr Pointer to address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
\brief Set Ethernet MAC Address.
|
||||
\param[in] ptr_addr Pointer to address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
|
||||
uint32_t num_addr)
|
||||
\brief Configure Address Filter.
|
||||
\param[in] ptr_addr Pointer to addresses
|
||||
\param[in] num_addr Number of addresses to configure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
|
||||
\brief Send Ethernet frame.
|
||||
\param[in] frame Pointer to frame buffer with data to send
|
||||
\param[in] len Frame buffer length in bytes
|
||||
\param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
|
||||
\brief Read data of received Ethernet frame.
|
||||
\param[in] frame Pointer to frame buffer for data to read into
|
||||
\param[in] len Frame buffer length in bytes
|
||||
\return number of data bytes read or execution status
|
||||
- value >= 0: number of data bytes read
|
||||
- value < 0: error occurred, value is execution status as defined with \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
|
||||
\brief Get size of received Ethernet frame.
|
||||
\return number of bytes in received frame
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
|
||||
\brief Get time of received Ethernet frame.
|
||||
\param[in] time Pointer to time structure for data to read into
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
|
||||
\brief Get time of transmitted Ethernet frame.
|
||||
\param[in] time Pointer to time structure for data to read into
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control Ethernet Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
|
||||
\brief Control Precision Timer.
|
||||
\param[in] control Operation
|
||||
\param[in] time Pointer to time structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
|
||||
\brief Read Ethernet PHY Register through Management Interface.
|
||||
\param[in] phy_addr 5-bit device address
|
||||
\param[in] reg_addr 5-bit register address
|
||||
\param[out] data Pointer where the result is written to
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
|
||||
\brief Write Ethernet PHY Register through Management Interface.
|
||||
\param[in] phy_addr 5-bit device address
|
||||
\param[in] reg_addr 5-bit register address
|
||||
\param[in] data 16-bit data to write
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_ETH_MAC_SignalEvent (uint32_t event)
|
||||
\brief Callback function that signals a Ethernet Event.
|
||||
\param[in] event event notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Capabilities
|
||||
*/
|
||||
typedef struct _ARM_ETH_MAC_CAPABILITIES {
|
||||
uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive
|
||||
uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive
|
||||
uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive
|
||||
uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive
|
||||
uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive
|
||||
uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit
|
||||
uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit
|
||||
uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit
|
||||
uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit
|
||||
uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit
|
||||
uint32_t media_interface : 2; ///< Ethernet Media Interface type
|
||||
uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address
|
||||
uint32_t event_rx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
|
||||
uint32_t event_tx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
|
||||
uint32_t event_wakeup : 1; ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
|
||||
uint32_t precision_timer : 1; ///< 1 = Precision Timer supported
|
||||
uint32_t reserved : 15; ///< Reserved (must be zero)
|
||||
} ARM_ETH_MAC_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the Ethernet MAC Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_ETH_MAC {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
|
||||
ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_ETH_MAC_SignalEvent_t cb_event); ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
|
||||
int32_t (*GetMacAddress) ( ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
|
||||
int32_t (*SetMacAddress) (const ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
|
||||
int32_t (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
|
||||
int32_t (*SendFrame) (const uint8_t *frame, uint32_t len, uint32_t flags); ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
|
||||
int32_t (*ReadFrame) ( uint8_t *frame, uint32_t len); ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
|
||||
uint32_t (*GetRxFrameSize) (void); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
|
||||
int32_t (*GetRxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
|
||||
int32_t (*GetTxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
|
||||
int32_t (*ControlTimer) (uint32_t control, ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
|
||||
int32_t (*PHY_Read) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
|
||||
int32_t (*PHY_Write) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
|
||||
} const ARM_DRIVER_ETH_MAC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_ETH_MAC_H_ */
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.1
|
||||
*
|
||||
* Project: Ethernet PHY (Physical Transceiver) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.1
|
||||
* ARM_ETH_LINK_INFO made volatile
|
||||
* Version 2.0
|
||||
* changed parameter "mode" in function ARM_ETH_PHY_SetMode
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Changed return values of some functions to int32_t
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ETH_PHY_H_
|
||||
#define DRIVER_ETH_PHY_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_ETH.h"
|
||||
|
||||
#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_ETH_PHY_(n) Driver_ETH_PHY##n
|
||||
#define ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
|
||||
|
||||
|
||||
/****** Ethernet PHY Mode *****/
|
||||
#define ARM_ETH_PHY_SPEED_Pos 0
|
||||
#define ARM_ETH_PHY_SPEED_Msk (3UL << ARM_ETH_PHY_SPEED_Pos)
|
||||
#define ARM_ETH_PHY_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed
|
||||
#define ARM_ETH_PHY_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed
|
||||
#define ARM_ETH_PHY_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed
|
||||
#define ARM_ETH_PHY_DUPLEX_Pos 2
|
||||
#define ARM_ETH_PHY_DUPLEX_Msk (1UL << ARM_ETH_PHY_DUPLEX_Pos)
|
||||
#define ARM_ETH_PHY_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
|
||||
#define ARM_ETH_PHY_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
|
||||
#define ARM_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode
|
||||
#define ARM_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode
|
||||
#define ARM_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read,
|
||||
ARM_ETH_PHY_Write_t fn_write)
|
||||
\brief Initialize Ethernet PHY Device.
|
||||
\param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read
|
||||
\param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_Uninitialize (void)
|
||||
\brief De-initialize Ethernet PHY Device.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control Ethernet PHY Device Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
|
||||
\brief Set Ethernet Media Interface.
|
||||
\param[in] interface Media Interface type
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
|
||||
\brief Set Ethernet PHY Device Operation mode.
|
||||
\param[in] mode Operation Mode
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
|
||||
\brief Get Ethernet PHY Device Link state.
|
||||
\return current link status \ref ARM_ETH_LINK_STATE
|
||||
*/
|
||||
/**
|
||||
\fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
|
||||
\brief Get Ethernet PHY Device Link information.
|
||||
\return current link parameters \ref ARM_ETH_LINK_INFO
|
||||
*/
|
||||
|
||||
|
||||
typedef int32_t (*ARM_ETH_PHY_Read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
|
||||
typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the Ethernet PHY Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_ETH_PHY {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
|
||||
int32_t (*Initialize) (ARM_ETH_PHY_Read_t fn_read,
|
||||
ARM_ETH_PHY_Write_t fn_write); ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
|
||||
int32_t (*SetInterface) (uint32_t interface); ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
|
||||
int32_t (*SetMode) (uint32_t mode); ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
|
||||
ARM_ETH_LINK_STATE (*GetLinkState) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
|
||||
ARM_ETH_LINK_INFO (*GetLinkInfo) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
|
||||
} const ARM_DRIVER_ETH_PHY;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_ETH_PHY_H_ */
|
||||
@@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.1
|
||||
*
|
||||
* Project: Flash Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.1
|
||||
* ARM_FLASH_STATUS made volatile
|
||||
* Version 2.0
|
||||
* Renamed driver NOR -> Flash (more generic)
|
||||
* Non-blocking operation
|
||||
* Added Events, Status and Capabilities
|
||||
* Linked Flash information (GetInfo)
|
||||
* Version 1.11
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_FLASH_H_
|
||||
#define DRIVER_FLASH_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,1) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_Flash_(n) Driver_Flash##n
|
||||
#define ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
|
||||
|
||||
|
||||
#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
|
||||
|
||||
/**
|
||||
\brief Flash Sector information
|
||||
*/
|
||||
typedef struct _ARM_FLASH_SECTOR {
|
||||
uint32_t start; ///< Sector Start address
|
||||
uint32_t end; ///< Sector End address (start+size-1)
|
||||
} const ARM_FLASH_SECTOR;
|
||||
|
||||
/**
|
||||
\brief Flash information
|
||||
*/
|
||||
typedef struct _ARM_FLASH_INFO {
|
||||
ARM_FLASH_SECTOR *sector_info; ///< Sector layout information (NULL=Uniform sectors)
|
||||
uint32_t sector_count; ///< Number of sectors
|
||||
uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used)
|
||||
uint32_t page_size; ///< Optimal programming page size in bytes
|
||||
uint32_t program_unit; ///< Smallest programmable unit in bytes
|
||||
uint8_t erased_value; ///< Contents of erased memory (usually 0xFF)
|
||||
} const ARM_FLASH_INFO;
|
||||
|
||||
|
||||
/**
|
||||
\brief Flash Status
|
||||
*/
|
||||
typedef volatile struct _ARM_FLASH_STATUS {
|
||||
uint32_t busy : 1; ///< Flash busy flag
|
||||
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
|
||||
uint32_t reserved : 30;
|
||||
} ARM_FLASH_STATUS;
|
||||
|
||||
|
||||
/****** Flash Event *****/
|
||||
#define ARM_FLASH_EVENT_READY (1UL << 0) ///< Flash Ready
|
||||
#define ARM_FLASH_EVENT_ERROR (1UL << 1) ///< Read/Program/Erase Error
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_FLASH_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
|
||||
\brief Initialize the Flash Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_Flash_SignalEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_Uninitialize (void)
|
||||
\brief De-initialize the Flash Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control the Flash interface power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
|
||||
\brief Read data from Flash.
|
||||
\param[in] addr Data address.
|
||||
\param[out] data Pointer to a buffer storing the data read from Flash.
|
||||
\param[in] cnt Number of data items to read.
|
||||
\return number of data items read or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
|
||||
\brief Program data to Flash.
|
||||
\param[in] addr Data address.
|
||||
\param[in] data Pointer to a buffer containing the data to be programmed to Flash.
|
||||
\param[in] cnt Number of data items to program.
|
||||
\return number of data items programmed or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_EraseSector (uint32_t addr)
|
||||
\brief Erase Flash Sector.
|
||||
\param[in] addr Sector address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_EraseChip (void)
|
||||
\brief Erase complete Flash.
|
||||
Optional function for faster full chip erase.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
|
||||
\brief Get Flash status.
|
||||
\return Flash status \ref ARM_FLASH_STATUS
|
||||
*/
|
||||
/**
|
||||
\fn ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
|
||||
\brief Get Flash information.
|
||||
\return Pointer to Flash information \ref ARM_FLASH_INFO
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_Flash_SignalEvent (uint32_t event)
|
||||
\brief Signal Flash event.
|
||||
\param[in] event Event notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief Flash Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_FLASH_CAPABILITIES {
|
||||
uint32_t event_ready : 1; ///< Signal Flash Ready event
|
||||
uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
|
||||
uint32_t erase_chip : 1; ///< Supports EraseChip operation
|
||||
uint32_t reserved : 28; ///< Reserved (must be zero)
|
||||
} ARM_FLASH_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the Flash Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_FLASH {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
|
||||
ARM_FLASH_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_Flash_SignalEvent_t cb_event); ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
|
||||
int32_t (*ReadData) (uint32_t addr, void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
|
||||
int32_t (*ProgramData) (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
|
||||
int32_t (*EraseSector) (uint32_t addr); ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
|
||||
int32_t (*EraseChip) (void); ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
|
||||
ARM_FLASH_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
|
||||
ARM_FLASH_INFO * (*GetInfo) (void); ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
|
||||
} const ARM_DRIVER_FLASH;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_FLASH_H_ */
|
||||
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.3
|
||||
*
|
||||
* Project: I2C (Inter-Integrated Circuit) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.3
|
||||
* ARM_I2C_STATUS made volatile
|
||||
* Version 2.2
|
||||
* Removed function ARM_I2C_MasterTransfer in order to simplify drivers
|
||||
* and added back parameter "xfer_pending" to functions
|
||||
* ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
|
||||
* Version 2.1
|
||||
* Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
|
||||
* from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
|
||||
* Added function ARM_I2C_GetDataCount
|
||||
* Removed flag "address_nack" from ARM_I2C_STATUS
|
||||
* Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
|
||||
* with event ARM_I2C_EVENT_TRANSFER_DONE
|
||||
* Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
|
||||
* Removed parameter "arg" from function ARM_I2C_SignalEvent
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* Added:
|
||||
* Slave Mode
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_I2C_H_
|
||||
#define DRIVER_I2C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
|
||||
|
||||
|
||||
/****** I2C Control Codes *****/
|
||||
|
||||
#define ARM_I2C_OWN_ADDRESS (0x01) ///< Set Own Slave Address; arg = address
|
||||
#define ARM_I2C_BUS_SPEED (0x02) ///< Set Bus Speed; arg = speed
|
||||
#define ARM_I2C_BUS_CLEAR (0x03) ///< Execute Bus clear: send nine clock pulses
|
||||
#define ARM_I2C_ABORT_TRANSFER (0x04) ///< Abort Master/Slave Transmit/Receive
|
||||
|
||||
/*----- I2C Bus Speed -----*/
|
||||
#define ARM_I2C_BUS_SPEED_STANDARD (0x01) ///< Standard Speed (100kHz)
|
||||
#define ARM_I2C_BUS_SPEED_FAST (0x02) ///< Fast Speed (400kHz)
|
||||
#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03) ///< Fast+ Speed ( 1MHz)
|
||||
#define ARM_I2C_BUS_SPEED_HIGH (0x04) ///< High Speed (3.4MHz)
|
||||
|
||||
|
||||
/****** I2C Address Flags *****/
|
||||
|
||||
#define ARM_I2C_ADDRESS_10BIT (0x0400) ///< 10-bit address flag
|
||||
#define ARM_I2C_ADDRESS_GC (0x8000) ///< General Call flag
|
||||
|
||||
|
||||
/**
|
||||
\brief I2C Status
|
||||
*/
|
||||
typedef volatile struct _ARM_I2C_STATUS {
|
||||
uint32_t busy : 1; ///< Busy flag
|
||||
uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master
|
||||
uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver
|
||||
uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation)
|
||||
uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation)
|
||||
uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation)
|
||||
uint32_t reserved : 26;
|
||||
} ARM_I2C_STATUS;
|
||||
|
||||
|
||||
/****** I2C Event *****/
|
||||
#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished
|
||||
#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer
|
||||
#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Slave Transmit operation requested
|
||||
#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Slave Receive operation requested
|
||||
#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave
|
||||
#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< General Call indication
|
||||
#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration
|
||||
#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position)
|
||||
#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_I2C_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
|
||||
\brief Initialize I2C Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_Uninitialize (void)
|
||||
\brief De-initialize I2C Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control I2C Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
\brief Start transmitting data as I2C Master.
|
||||
\param[in] addr Slave address (7-bit or 10-bit)
|
||||
\param[in] data Pointer to buffer with data to transmit to I2C Slave
|
||||
\param[in] num Number of data bytes to transmit
|
||||
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
\brief Start receiving data as I2C Master.
|
||||
\param[in] addr Slave address (7-bit or 10-bit)
|
||||
\param[out] data Pointer to buffer for data to receive from I2C Slave
|
||||
\param[in] num Number of data bytes to receive
|
||||
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
|
||||
\brief Start transmitting data as I2C Slave.
|
||||
\param[in] data Pointer to buffer with data to transmit to I2C Master
|
||||
\param[in] num Number of data bytes to transmit
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
|
||||
\brief Start receiving data as I2C Slave.
|
||||
\param[out] data Pointer to buffer for data to receive from I2C Master
|
||||
\param[in] num Number of data bytes to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_GetDataCount (void)
|
||||
\brief Get transferred data count.
|
||||
\return number of data bytes transferred; -1 when Slave is not addressed by Master
|
||||
|
||||
\fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control I2C Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_I2C_STATUS ARM_I2C_GetStatus (void)
|
||||
\brief Get I2C status.
|
||||
\return I2C status \ref ARM_I2C_STATUS
|
||||
|
||||
\fn void ARM_I2C_SignalEvent (uint32_t event)
|
||||
\brief Signal I2C Events.
|
||||
\param[in] event \ref I2C_events notification mask
|
||||
*/
|
||||
|
||||
typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief I2C Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_I2C_CAPABILITIES {
|
||||
uint32_t address_10_bit : 1; ///< supports 10-bit addressing
|
||||
uint32_t reserved : 31; ///< Reserved (must be zero)
|
||||
} ARM_I2C_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the I2C Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_I2C {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
|
||||
ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
|
||||
int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
|
||||
int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
|
||||
int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
|
||||
int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
|
||||
int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
|
||||
ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
|
||||
} const ARM_DRIVER_I2C;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_I2C_H_ */
|
||||
@@ -0,0 +1,360 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.3
|
||||
*
|
||||
* Project: MCI (Memory Card Interface) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.3
|
||||
* ARM_MCI_STATUS made volatile
|
||||
* Version 2.2
|
||||
* Added timeout and error flags to ARM_MCI_STATUS
|
||||
* Added support for controlling optional RST_n pin (eMMC)
|
||||
* Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
|
||||
* Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
|
||||
* Version 2.1
|
||||
* Decoupled SPI mode from MCI driver
|
||||
* Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
|
||||
* Version 2.0
|
||||
* Added support for:
|
||||
* SD UHS-I (Ultra High Speed)
|
||||
* SD I/O Interrupt
|
||||
* Read Wait (SD I/O)
|
||||
* Suspend/Resume (SD I/O)
|
||||
* MMC Interrupt
|
||||
* MMC Boot
|
||||
* Stream Data transfer (MMC)
|
||||
* VCCQ Power Supply Control (eMMC)
|
||||
* Command Completion Signal (CCS) for CE-ATA
|
||||
* Added ARM_MCI_Control function
|
||||
* Added ARM_MCI_GetStatus function
|
||||
* Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
|
||||
* (replaced by ARM_MCI_Control)
|
||||
* Changed ARM_MCI_CardPower function (voltage parameter)
|
||||
* Changed ARM_MCI_SendCommnad function (flags parameter)
|
||||
* Changed ARM_MCI_SetupTransfer function (mode parameter)
|
||||
* Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Changed return values of some functions to int32_t
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_MCI_H_
|
||||
#define DRIVER_MCI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
|
||||
|
||||
|
||||
/****** MCI Send Command Flags *****/
|
||||
#define ARM_MCI_RESPONSE_Pos 0
|
||||
#define ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos)
|
||||
#define ARM_MCI_RESPONSE_NONE (0UL << ARM_MCI_RESPONSE_Pos) ///< No response expected (default)
|
||||
#define ARM_MCI_RESPONSE_SHORT (1UL << ARM_MCI_RESPONSE_Pos) ///< Short response (48-bit)
|
||||
#define ARM_MCI_RESPONSE_SHORT_BUSY (2UL << ARM_MCI_RESPONSE_Pos) ///< Short response with busy signal (48-bit)
|
||||
#define ARM_MCI_RESPONSE_LONG (3UL << ARM_MCI_RESPONSE_Pos) ///< Long response (136-bit)
|
||||
|
||||
#define ARM_MCI_RESPONSE_INDEX (1UL << 2) ///< Check command index in response
|
||||
#define ARM_MCI_RESPONSE_CRC (1UL << 3) ///< Check CRC in response
|
||||
|
||||
#define ARM_MCI_WAIT_BUSY (1UL << 4) ///< Wait until busy before sending the command
|
||||
|
||||
#define ARM_MCI_TRANSFER_DATA (1UL << 5) ///< Activate Data transfer
|
||||
|
||||
#define ARM_MCI_CARD_INITIALIZE (1UL << 6) ///< Execute Memory Card initialization sequence
|
||||
|
||||
#define ARM_MCI_INTERRUPT_COMMAND (1UL << 7) ///< Send Interrupt command (CMD40 - MMC only)
|
||||
#define ARM_MCI_INTERRUPT_RESPONSE (1UL << 8) ///< Send Interrupt response (CMD40 - MMC only)
|
||||
|
||||
#define ARM_MCI_BOOT_OPERATION (1UL << 9) ///< Execute Boot operation (MMC only)
|
||||
#define ARM_MCI_BOOT_ALTERNATIVE (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
|
||||
#define ARM_MCI_BOOT_ACK (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
|
||||
|
||||
#define ARM_MCI_CCSD (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
|
||||
#define ARM_MCI_CCS (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
|
||||
|
||||
|
||||
/****** MCI Setup Transfer Mode *****/
|
||||
#define ARM_MCI_TRANSFER_READ (0UL << 0) ///< Data Read Transfer (from MCI)
|
||||
#define ARM_MCI_TRANSFER_WRITE (1UL << 0) ///< Data Write Transfer (to MCI)
|
||||
#define ARM_MCI_TRANSFER_BLOCK (0UL << 1) ///< Block Data transfer (default)
|
||||
#define ARM_MCI_TRANSFER_STREAM (1UL << 1) ///< Stream Data transfer (MMC only)
|
||||
|
||||
|
||||
/****** MCI Control Codes *****/
|
||||
#define ARM_MCI_BUS_SPEED (0x01) ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
|
||||
#define ARM_MCI_BUS_SPEED_MODE (0x02) ///< Set Bus Speed Mode as specified with arg
|
||||
#define ARM_MCI_BUS_CMD_MODE (0x03) ///< Set CMD Line Mode as specified with arg
|
||||
#define ARM_MCI_BUS_DATA_WIDTH (0x04) ///< Set Bus Data Width as specified with arg
|
||||
#define ARM_MCI_DRIVER_STRENGTH (0x05) ///< Set SD UHS-I Driver Strength as specified with arg
|
||||
#define ARM_MCI_CONTROL_RESET (0x06) ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active
|
||||
#define ARM_MCI_CONTROL_CLOCK_IDLE (0x07) ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
|
||||
#define ARM_MCI_UHS_TUNING_OPERATION (0x08) ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
|
||||
#define ARM_MCI_UHS_TUNING_RESULT (0x09) ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
|
||||
#define ARM_MCI_DATA_TIMEOUT (0x0A) ///< Set Data timeout; arg = timeout in bus cycles
|
||||
#define ARM_MCI_CSS_TIMEOUT (0x0B) ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
|
||||
#define ARM_MCI_MONITOR_SDIO_INTERRUPT (0x0C) ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
|
||||
#define ARM_MCI_CONTROL_READ_WAIT (0x0D) ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
|
||||
#define ARM_MCI_SUSPEND_TRANSFER (0x0E) ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
|
||||
#define ARM_MCI_RESUME_TRANSFER (0x0F) ///< Resume Data transfer (SD I/O)
|
||||
|
||||
/*----- MCI Bus Speed Mode -----*/
|
||||
#define ARM_MCI_BUS_DEFAULT_SPEED (0x00) ///< SD/MMC: Default Speed mode up to 25/26MHz
|
||||
#define ARM_MCI_BUS_HIGH_SPEED (0x01) ///< SD/MMC: High Speed mode up to 50/52MHz
|
||||
#define ARM_MCI_BUS_UHS_SDR12 (0x02) ///< SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
|
||||
#define ARM_MCI_BUS_UHS_SDR25 (0x03) ///< SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
|
||||
#define ARM_MCI_BUS_UHS_SDR50 (0x04) ///< SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
|
||||
#define ARM_MCI_BUS_UHS_SDR104 (0x05) ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
|
||||
#define ARM_MCI_BUS_UHS_DDR50 (0x06) ///< SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
|
||||
|
||||
/*----- MCI CMD Line Mode -----*/
|
||||
#define ARM_MCI_BUS_CMD_PUSH_PULL (0x00) ///< Push-Pull CMD line (default)
|
||||
#define ARM_MCI_BUS_CMD_OPEN_DRAIN (0x01) ///< Open Drain CMD line (MMC only)
|
||||
|
||||
/*----- MCI Bus Data Width -----*/
|
||||
#define ARM_MCI_BUS_DATA_WIDTH_1 (0x00) ///< Bus data width: 1 bit (default)
|
||||
#define ARM_MCI_BUS_DATA_WIDTH_4 (0x01) ///< Bus data width: 4 bits
|
||||
#define ARM_MCI_BUS_DATA_WIDTH_8 (0x02) ///< Bus data width: 8 bits
|
||||
#define ARM_MCI_BUS_DATA_WIDTH_4_DDR (0x03) ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
|
||||
#define ARM_MCI_BUS_DATA_WIDTH_8_DDR (0x04) ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
|
||||
|
||||
/*----- MCI Driver Strength -----*/
|
||||
#define ARM_MCI_DRIVER_TYPE_A (0x01) ///< SD UHS-I Driver Type A
|
||||
#define ARM_MCI_DRIVER_TYPE_B (0x00) ///< SD UHS-I Driver Type B (default)
|
||||
#define ARM_MCI_DRIVER_TYPE_C (0x02) ///< SD UHS-I Driver Type C
|
||||
#define ARM_MCI_DRIVER_TYPE_D (0x03) ///< SD UHS-I Driver Type D
|
||||
|
||||
|
||||
/****** MCI Card Power *****/
|
||||
#define ARM_MCI_POWER_VDD_Pos 0
|
||||
#define ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos)
|
||||
#define ARM_MCI_POWER_VDD_OFF (0x01UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) turned off
|
||||
#define ARM_MCI_POWER_VDD_3V3 (0x02UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 3.3V
|
||||
#define ARM_MCI_POWER_VDD_1V8 (0x03UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 1.8V
|
||||
#define ARM_MCI_POWER_VCCQ_Pos 4
|
||||
#define ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
|
||||
#define ARM_MCI_POWER_VCCQ_OFF (0x01UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ turned off
|
||||
#define ARM_MCI_POWER_VCCQ_3V3 (0x02UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 3.3V
|
||||
#define ARM_MCI_POWER_VCCQ_1V8 (0x03UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.8V
|
||||
#define ARM_MCI_POWER_VCCQ_1V2 (0x04UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.2V
|
||||
|
||||
|
||||
/**
|
||||
\brief MCI Status
|
||||
*/
|
||||
typedef volatile struct _ARM_MCI_STATUS {
|
||||
uint32_t command_active : 1; ///< Command active flag
|
||||
uint32_t command_timeout : 1; ///< Command timeout flag (cleared on start of next command)
|
||||
uint32_t command_error : 1; ///< Command error flag (cleared on start of next command)
|
||||
uint32_t transfer_active : 1; ///< Transfer active flag
|
||||
uint32_t transfer_timeout : 1; ///< Transfer timeout flag (cleared on start of next command)
|
||||
uint32_t transfer_error : 1; ///< Transfer error flag (cleared on start of next command)
|
||||
uint32_t sdio_interrupt : 1; ///< SD I/O Interrupt flag (cleared on start of monitoring)
|
||||
uint32_t ccs : 1; ///< CCS flag (cleared on start of next command)
|
||||
uint32_t reserved : 24;
|
||||
} ARM_MCI_STATUS;
|
||||
|
||||
|
||||
/****** MCI Card Event *****/
|
||||
#define ARM_MCI_EVENT_CARD_INSERTED (1UL << 0) ///< Memory Card inserted
|
||||
#define ARM_MCI_EVENT_CARD_REMOVED (1UL << 1) ///< Memory Card removed
|
||||
#define ARM_MCI_EVENT_COMMAND_COMPLETE (1UL << 2) ///< Command completed
|
||||
#define ARM_MCI_EVENT_COMMAND_TIMEOUT (1UL << 3) ///< Command timeout
|
||||
#define ARM_MCI_EVENT_COMMAND_ERROR (1UL << 4) ///< Command response error (CRC error or invalid response)
|
||||
#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5) ///< Data transfer completed
|
||||
#define ARM_MCI_EVENT_TRANSFER_TIMEOUT (1UL << 6) ///< Data transfer timeout
|
||||
#define ARM_MCI_EVENT_TRANSFER_ERROR (1UL << 7) ///< Data transfer CRC failed
|
||||
#define ARM_MCI_EVENT_SDIO_INTERRUPT (1UL << 8) ///< SD I/O Interrupt
|
||||
#define ARM_MCI_EVENT_CCS (1UL << 9) ///< Command Completion Signal (CCS)
|
||||
#define ARM_MCI_EVENT_CCS_TIMEOUT (1UL << 10) ///< Command Completion Signal (CCS) Timeout
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_MCI_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
|
||||
\brief Initialize the Memory Card Interface
|
||||
\param[in] cb_event Pointer to \ref ARM_MCI_SignalEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_Uninitialize (void)
|
||||
\brief De-initialize Memory Card Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control Memory Card Interface Power.
|
||||
\param[in] state Power state \ref ARM_POWER_STATE
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_CardPower (uint32_t voltage)
|
||||
\brief Set Memory Card Power supply voltage.
|
||||
\param[in] voltage Memory Card Power supply voltage
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_ReadCD (void)
|
||||
\brief Read Card Detect (CD) state.
|
||||
\return 1:card detected, 0:card not detected, or error
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_ReadWP (void)
|
||||
\brief Read Write Protect (WP) state.
|
||||
\return 1:write protected, 0:not write protected, or error
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_SendCommand (uint32_t cmd,
|
||||
uint32_t arg,
|
||||
uint32_t flags,
|
||||
uint32_t *response)
|
||||
\brief Send Command to card and get the response.
|
||||
\param[in] cmd Memory Card command
|
||||
\param[in] arg Command argument
|
||||
\param[in] flags Command flags
|
||||
\param[out] response Pointer to buffer for response
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_SetupTransfer (uint8_t *data,
|
||||
uint32_t block_count,
|
||||
uint32_t block_size,
|
||||
uint32_t mode)
|
||||
\brief Setup read or write transfer operation.
|
||||
\param[in,out] data Pointer to data block(s) to be written or read
|
||||
\param[in] block_count Number of blocks
|
||||
\param[in] block_size Size of a block in bytes
|
||||
\param[in] mode Transfer mode
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_AbortTransfer (void)
|
||||
\brief Abort current read/write data transfer.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control MCI Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_MCI_STATUS ARM_MCI_GetStatus (void)
|
||||
\brief Get MCI status.
|
||||
\return MCI status \ref ARM_MCI_STATUS
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_MCI_SignalEvent (uint32_t event)
|
||||
\brief Callback function that signals a MCI Card Event.
|
||||
\param[in] event \ref mci_event_gr
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief MCI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_MCI_CAPABILITIES {
|
||||
uint32_t cd_state : 1; ///< Card Detect State available
|
||||
uint32_t cd_event : 1; ///< Signal Card Detect change event
|
||||
uint32_t wp_state : 1; ///< Write Protect State available
|
||||
uint32_t vdd : 1; ///< Supports VDD Card Power Supply Control
|
||||
uint32_t vdd_1v8 : 1; ///< Supports 1.8 VDD Card Power Supply
|
||||
uint32_t vccq : 1; ///< Supports VCCQ Card Power Supply Control (eMMC)
|
||||
uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
|
||||
uint32_t vccq_1v2 : 1; ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
|
||||
uint32_t data_width_4 : 1; ///< Supports 4-bit data
|
||||
uint32_t data_width_8 : 1; ///< Supports 8-bit data
|
||||
uint32_t data_width_4_ddr : 1; ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
|
||||
uint32_t data_width_8_ddr : 1; ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
|
||||
uint32_t high_speed : 1; ///< Supports SD/MMC High Speed Mode
|
||||
uint32_t uhs_signaling : 1; ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling
|
||||
uint32_t uhs_tuning : 1; ///< Supports SD UHS-I tuning
|
||||
uint32_t uhs_sdr50 : 1; ///< Supports SD UHS-I SDR50 (Single Data Rate) up to 50MB/s
|
||||
uint32_t uhs_sdr104 : 1; ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
|
||||
uint32_t uhs_ddr50 : 1; ///< Supports SD UHS-I DDR50 (Dual Data Rate) up to 50MB/s
|
||||
uint32_t uhs_driver_type_a : 1; ///< Supports SD UHS-I Driver Type A
|
||||
uint32_t uhs_driver_type_c : 1; ///< Supports SD UHS-I Driver Type C
|
||||
uint32_t uhs_driver_type_d : 1; ///< Supports SD UHS-I Driver Type D
|
||||
uint32_t sdio_interrupt : 1; ///< Supports SD I/O Interrupt
|
||||
uint32_t read_wait : 1; ///< Supports Read Wait (SD I/O)
|
||||
uint32_t suspend_resume : 1; ///< Supports Suspend/Resume (SD I/O)
|
||||
uint32_t mmc_interrupt : 1; ///< Supports MMC Interrupt
|
||||
uint32_t mmc_boot : 1; ///< Supports MMC Boot
|
||||
uint32_t rst_n : 1; ///< Supports RST_n Pin Control (eMMC)
|
||||
uint32_t ccs : 1; ///< Supports Command Completion Signal (CCS) for CE-ATA
|
||||
uint32_t ccs_timeout : 1; ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
|
||||
uint32_t reserved : 3; ///< Reserved (must be zero)
|
||||
} ARM_MCI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the MCI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_MCI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
|
||||
ARM_MCI_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
|
||||
int32_t (*CardPower) (uint32_t voltage); ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
|
||||
int32_t (*ReadCD) (void); ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
|
||||
int32_t (*ReadWP) (void); ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
|
||||
int32_t (*SendCommand) (uint32_t cmd,
|
||||
uint32_t arg,
|
||||
uint32_t flags,
|
||||
uint32_t *response); ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
|
||||
int32_t (*SetupTransfer) (uint8_t *data,
|
||||
uint32_t block_count,
|
||||
uint32_t block_size,
|
||||
uint32_t mode); ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
|
||||
int32_t (*AbortTransfer) (void); ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
|
||||
ARM_MCI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
|
||||
} const ARM_DRIVER_MCI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_MCI_H_ */
|
||||
@@ -0,0 +1,413 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: NAND Flash Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* ARM_NAND_STATUS made volatile
|
||||
* Version 2.1
|
||||
* Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (command agnostic)
|
||||
* Added support for:
|
||||
* NV-DDR & NV-DDR2 Interface (ONFI specification)
|
||||
* VCC, VCCQ and VPP Power Supply Control
|
||||
* WP (Write Protect) Control
|
||||
* Version 1.11
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_NAND_H_
|
||||
#define DRIVER_NAND_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
|
||||
|
||||
|
||||
/****** NAND Device Power *****/
|
||||
#define ARM_NAND_POWER_VCC_Pos 0
|
||||
#define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos)
|
||||
#define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off
|
||||
#define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V
|
||||
#define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V
|
||||
#define ARM_NAND_POWER_VCCQ_Pos 3
|
||||
#define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
|
||||
#define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
|
||||
#define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
|
||||
#define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
|
||||
#define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off
|
||||
#define ARM_NAND_POWER_VPP_ON (1Ul << 7) ///< VPP on
|
||||
|
||||
|
||||
/****** NAND Control Codes *****/
|
||||
#define ARM_NAND_BUS_MODE (0x01) ///< Set Bus Mode as specified with arg
|
||||
#define ARM_NAND_BUS_DATA_WIDTH (0x02) ///< Set Bus Data Width as specified with arg
|
||||
#define ARM_NAND_DRIVER_STRENGTH (0x03) ///< Set Driver Strength as specified with arg
|
||||
#define ARM_NAND_DEVICE_READY_EVENT (0x04) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled
|
||||
#define ARM_NAND_DRIVER_READY_EVENT (0x05) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled
|
||||
|
||||
/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
|
||||
#define ARM_NAND_BUS_INTERFACE_Pos 4
|
||||
#define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
|
||||
#define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default)
|
||||
#define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate)
|
||||
#define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate)
|
||||
#define ARM_NAND_BUS_TIMING_MODE_Pos 0
|
||||
#define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
|
||||
#define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default)
|
||||
#define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1
|
||||
#define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2
|
||||
#define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3
|
||||
#define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable)
|
||||
#define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable)
|
||||
#define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only)
|
||||
#define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only)
|
||||
#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8
|
||||
#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
|
||||
#define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
|
||||
#define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
|
||||
#define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
|
||||
#define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
|
||||
#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12
|
||||
#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
|
||||
#define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
|
||||
#define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
|
||||
#define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
|
||||
#define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
|
||||
#define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference
|
||||
#define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal
|
||||
#define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal
|
||||
|
||||
/*----- NAND Data Bus Width -----*/
|
||||
#define ARM_NAND_BUS_DATA_WIDTH_8 (0x00) ///< Bus Data Width: 8 bit (default)
|
||||
#define ARM_NAND_BUS_DATA_WIDTH_16 (0x01) ///< Bus Data Width: 16 bit
|
||||
|
||||
/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
|
||||
#define ARM_NAND_DRIVER_STRENGTH_18 (0x00) ///< Driver Strength 2.0x = 18 Ohms
|
||||
#define ARM_NAND_DRIVER_STRENGTH_25 (0x01) ///< Driver Strength 1.4x = 25 Ohms
|
||||
#define ARM_NAND_DRIVER_STRENGTH_35 (0x02) ///< Driver Strength 1.0x = 35 Ohms (default)
|
||||
#define ARM_NAND_DRIVER_STRENGTH_50 (0x03) ///< Driver Strength 0.7x = 50 Ohms
|
||||
|
||||
|
||||
/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
|
||||
#define ARM_NAND_ECC_INDEX_Pos 0
|
||||
#define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
|
||||
#define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC
|
||||
#define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC
|
||||
#define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC
|
||||
|
||||
/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
|
||||
#define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
|
||||
|
||||
/****** NAND Sequence Execution Code *****/
|
||||
#define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1
|
||||
#define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1
|
||||
#define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2
|
||||
#define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1
|
||||
#define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2
|
||||
#define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3
|
||||
#define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address
|
||||
#define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data
|
||||
#define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2
|
||||
#define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy
|
||||
#define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data
|
||||
#define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3
|
||||
#define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
|
||||
|
||||
/*----- NAND Sequence Execution Code: Command -----*/
|
||||
#define ARM_NAND_CODE_CMD1_Pos 0
|
||||
#define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
|
||||
#define ARM_NAND_CODE_CMD2_Pos 8
|
||||
#define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
|
||||
#define ARM_NAND_CODE_CMD3_Pos 16
|
||||
#define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
|
||||
|
||||
/*----- NAND Sequence Execution Code: Column Address -----*/
|
||||
#define ARM_NAND_CODE_ADDR_COL1_Pos 0
|
||||
#define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
|
||||
#define ARM_NAND_CODE_ADDR_COL2_Pos 8
|
||||
#define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
|
||||
|
||||
/*----- NAND Sequence Execution Code: Row Address -----*/
|
||||
#define ARM_NAND_CODE_ADDR_ROW1_Pos 0
|
||||
#define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
|
||||
#define ARM_NAND_CODE_ADDR_ROW2_Pos 8
|
||||
#define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
|
||||
#define ARM_NAND_CODE_ADDR_ROW3_Pos 16
|
||||
#define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
|
||||
|
||||
|
||||
/****** NAND specific error codes *****/
|
||||
#define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed
|
||||
|
||||
|
||||
/**
|
||||
\brief NAND ECC (Error Correction Code) Information
|
||||
*/
|
||||
typedef struct _ARM_NAND_ECC_INFO {
|
||||
uint32_t type : 2; ///< Type: 1=ECC0 over Data, 2=ECC0 over Data+Spare, 3=ECC0 over Data and ECC1 over Spare
|
||||
uint32_t page_layout : 1; ///< Page layout: 0=|Data0|Spare0|...|DataN-1|SpareN-1|, 1=|Data0|...|DataN-1|Spare0|...|SpareN-1|
|
||||
uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count
|
||||
uint32_t page_size : 4; ///< Virtual Page size (Data+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448
|
||||
uint32_t reserved : 14; ///< Reserved (must be zero)
|
||||
uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size)
|
||||
uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated
|
||||
uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up)
|
||||
uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare area)
|
||||
} ARM_NAND_ECC_INFO;
|
||||
|
||||
|
||||
/**
|
||||
\brief NAND Status
|
||||
*/
|
||||
typedef volatile struct _ARM_NAND_STATUS {
|
||||
uint32_t busy : 1; ///< Driver busy flag
|
||||
uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
|
||||
uint32_t reserved : 30;
|
||||
} ARM_NAND_STATUS;
|
||||
|
||||
|
||||
/****** NAND Event *****/
|
||||
#define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge
|
||||
#define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready
|
||||
#define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done
|
||||
#define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_NAND_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
|
||||
\brief Initialize the NAND Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_Uninitialize (void)
|
||||
\brief De-initialize the NAND Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control the NAND interface power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_DevicePower (uint32_t voltage)
|
||||
\brief Set device power supply voltage.
|
||||
\param[in] voltage NAND Device supply voltage
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
|
||||
\brief Control WPn (Write Protect).
|
||||
\param[in] dev_num Device number
|
||||
\param[in] enable
|
||||
- \b false Write Protect off
|
||||
- \b true Write Protect on
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
|
||||
\brief Control CEn (Chip Enable).
|
||||
\param[in] dev_num Device number
|
||||
\param[in] enable
|
||||
- \b false Chip Enable off
|
||||
- \b true Chip Enable on
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
|
||||
\brief Get Device Busy pin state.
|
||||
\param[in] dev_num Device number
|
||||
\return 1=busy, 0=not busy, or error
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
|
||||
\brief Send command to NAND device.
|
||||
\param[in] dev_num Device number
|
||||
\param[in] cmd Command
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
|
||||
\brief Send address to NAND device.
|
||||
\param[in] dev_num Device number
|
||||
\param[in] addr Address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
|
||||
\brief Read data from NAND device.
|
||||
\param[in] dev_num Device number
|
||||
\param[out] data Pointer to buffer for data to read from NAND device
|
||||
\param[in] cnt Number of data items to read
|
||||
\param[in] mode Operation mode
|
||||
\return number of data items read or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
|
||||
\brief Write data to NAND device.
|
||||
\param[in] dev_num Device number
|
||||
\param[out] data Pointer to buffer with data to write to NAND device
|
||||
\param[in] cnt Number of data items to write
|
||||
\param[in] mode Operation mode
|
||||
\return number of data items written or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
|
||||
uint32_t addr_col, uint32_t addr_row,
|
||||
void *data, uint32_t data_cnt,
|
||||
uint8_t *status, uint32_t *count)
|
||||
\brief Execute sequence of operations.
|
||||
\param[in] dev_num Device number
|
||||
\param[in] code Sequence code
|
||||
\param[in] cmd Command(s)
|
||||
\param[in] addr_col Column address
|
||||
\param[in] addr_row Row address
|
||||
\param[in,out] data Pointer to data to be written or read
|
||||
\param[in] data_cnt Number of data items in one iteration
|
||||
\param[out] status Pointer to status read
|
||||
\param[in,out] count Number of iterations
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
|
||||
\brief Abort sequence execution.
|
||||
\param[in] dev_num Device number
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
|
||||
\brief Control NAND Interface.
|
||||
\param[in] dev_num Device number
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
|
||||
\brief Get NAND status.
|
||||
\param[in] dev_num Device number
|
||||
\return NAND status \ref ARM_NAND_STATUS
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
|
||||
\brief Inquire about available ECC.
|
||||
\param[in] index Device number
|
||||
\param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
|
||||
\brief Signal NAND event.
|
||||
\param[in] dev_num Device number
|
||||
\param[in] event Event notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief NAND Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_NAND_CAPABILITIES {
|
||||
uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge)
|
||||
uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
|
||||
uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
|
||||
uint32_t vcc : 1; ///< Supports VCC Power Supply Control
|
||||
uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply
|
||||
uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control
|
||||
uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply
|
||||
uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control
|
||||
uint32_t wp : 1; ///< Supports WPn (Write Protect) Control
|
||||
uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1
|
||||
uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control
|
||||
uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring
|
||||
uint32_t data_width_16 : 1; ///< Supports 16-bit data
|
||||
uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI)
|
||||
uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI)
|
||||
uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI)
|
||||
uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI)
|
||||
uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
|
||||
uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms
|
||||
uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms
|
||||
uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms
|
||||
uint32_t reserved : 2; ///< Reserved (must be zero)
|
||||
} ARM_NAND_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the NAND Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_NAND {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
|
||||
ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
|
||||
int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
|
||||
int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
|
||||
int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
|
||||
int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
|
||||
int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
|
||||
int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
|
||||
int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
|
||||
int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
|
||||
int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
|
||||
uint32_t addr_col, uint32_t addr_row,
|
||||
void *data, uint32_t data_cnt,
|
||||
uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
|
||||
int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution.
|
||||
int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
|
||||
ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
|
||||
int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC.
|
||||
} const ARM_DRIVER_NAND;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_NAND_H_ */
|
||||
@@ -0,0 +1,308 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V1.1
|
||||
*
|
||||
* Project: SAI (Serial Audio Interface) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 1.1
|
||||
* ARM_SAI_STATUS made volatile
|
||||
* Version 1.0
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SAI_H_
|
||||
#define DRIVER_SAI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1) /* API version */
|
||||
|
||||
|
||||
/****** SAI Control Codes *****/
|
||||
|
||||
#define ARM_SAI_CONTROL_Msk (0xFFU)
|
||||
#define ARM_SAI_CONFIGURE_TX (0x01U) ///< Configure Transmitter; arg1 and arg2 provide additional configuration
|
||||
#define ARM_SAI_CONFIGURE_RX (0x02U) ///< Configure Receiver; arg1 and arg2 provide additional configuration
|
||||
#define ARM_SAI_CONTROL_TX (0x03U) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute
|
||||
#define ARM_SAI_CONTROL_RX (0x04U) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable
|
||||
#define ARM_SAI_MASK_SLOTS_TX (0x05U) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
|
||||
#define ARM_SAI_MASK_SLOTS_RX (0x06U) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
|
||||
#define ARM_SAI_ABORT_SEND (0x07U) ///< Abort \ref ARM_SAI_Send
|
||||
#define ARM_SAI_ABORT_RECEIVE (0x08U) ///< Abort \ref ARM_SAI_Receive
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Mode -----*/
|
||||
#define ARM_SAI_MODE_Pos 8
|
||||
#define ARM_SAI_MODE_Msk (1U << ARM_SAI_MODE_Pos)
|
||||
#define ARM_SAI_MODE_MASTER (1U << ARM_SAI_MODE_Pos) ///< Master Mode
|
||||
#define ARM_SAI_MODE_SLAVE (0U << ARM_SAI_MODE_Pos) ///< Slave Mode (default)
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/
|
||||
#define ARM_SAI_SYNCHRONIZATION_Pos 9
|
||||
#define ARM_SAI_SYNCHRONIZATION_Msk (1U << ARM_SAI_SYNCHRONIZATION_Pos)
|
||||
#define ARM_SAI_ASYNCHRONOUS (0U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default)
|
||||
#define ARM_SAI_SYNCHRONOUS (1U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/
|
||||
#define ARM_SAI_PROTOCOL_Pos 10
|
||||
#define ARM_SAI_PROTOCOL_Msk (7U << ARM_SAI_PROTOCOL_Pos)
|
||||
#define ARM_SAI_PROTOCOL_USER (0U << ARM_SAI_PROTOCOL_Pos) ///< User defined (default)
|
||||
#define ARM_SAI_PROTOCOL_I2S (1U << ARM_SAI_PROTOCOL_Pos) ///< I2S
|
||||
#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2U << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified
|
||||
#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3U << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified
|
||||
#define ARM_SAI_PROTOCOL_PCM_SHORT (4U << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame
|
||||
#define ARM_SAI_PROTOCOL_PCM_LONG (5U << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame
|
||||
#define ARM_SAI_PROTOCOL_AC97 (6U << ARM_SAI_PROTOCOL_Pos) ///< AC'97
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/
|
||||
#define ARM_SAI_DATA_SIZE_Pos 13
|
||||
#define ARM_SAI_DATA_SIZE_Msk (0x1FU << ARM_SAI_DATA_SIZE_Pos)
|
||||
#define ARM_SAI_DATA_SIZE(n) ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32)
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/
|
||||
#define ARM_SAI_BIT_ORDER_Pos 18
|
||||
#define ARM_SAI_BIT_ORDER_Msk (1U << ARM_SAI_BIT_ORDER_Pos)
|
||||
#define ARM_SAI_MSB_FIRST (0U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default)
|
||||
#define ARM_SAI_LSB_FIRST (1U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/
|
||||
#define ARM_SAI_MONO_MODE (1U << 19) ///< Mono Mode (only for I2S, MSB/LSB justified)
|
||||
|
||||
/*----- SAI Control Codes:Configuration Parameters: Companding -----*/
|
||||
#define ARM_SAI_COMPANDING_Pos 20
|
||||
#define ARM_SAI_COMPANDING_Msk (3U << ARM_SAI_COMPANDING_Pos)
|
||||
#define ARM_SAI_COMPANDING_NONE (0U << ARM_SAI_COMPANDING_Pos) ///< No compading (default)
|
||||
#define ARM_SAI_COMPANDING_A_LAW (2U << ARM_SAI_COMPANDING_Pos) ///< A-Law companding
|
||||
#define ARM_SAI_COMPANDING_U_LAW (3U << ARM_SAI_COMPANDING_Pos) ///< u-Law companding
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/
|
||||
#define ARM_SAI_CLOCK_POLARITY_Pos 23
|
||||
#define ARM_SAI_CLOCK_POLARITY_Msk (1U << ARM_SAI_CLOCK_POLARITY_Pos)
|
||||
#define ARM_SAI_CLOCK_POLARITY_0 (0U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default)
|
||||
#define ARM_SAI_CLOCK_POLARITY_1 (1U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/
|
||||
#define ARM_SAI_MCLK_PIN_Pos 24
|
||||
#define ARM_SAI_MCLK_PIN_Msk (3U << ARM_SAI_MCLK_PIN_Pos)
|
||||
#define ARM_SAI_MCLK_PIN_INACTIVE (0U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default)
|
||||
#define ARM_SAI_MCLK_PIN_OUTPUT (1U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only)
|
||||
#define ARM_SAI_MCLK_PIN_INPUT (2U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only)
|
||||
|
||||
|
||||
/****** SAI Configuration (arg1) *****/
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Length -----*/
|
||||
#define ARM_SAI_FRAME_LENGTH_Pos 0
|
||||
#define ARM_SAI_FRAME_LENGTH_Msk (0x3FFU << ARM_SAI_FRAME_LENGTH_Pos)
|
||||
#define ARM_SAI_FRAME_LENGTH(n) ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Sync Width -----*/
|
||||
#define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10
|
||||
#define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFU << ARM_SAI_FRAME_SYNC_WIDTH_Pos)
|
||||
#define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos)
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Sync Early -----*/
|
||||
#define ARM_SAI_FRAME_SYNC_EARLY (1U << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Slot Count -----*/
|
||||
#define ARM_SAI_SLOT_COUNT_Pos 20
|
||||
#define ARM_SAI_SLOT_COUNT_Msk (0x1FU << ARM_SAI_SLOT_COUNT_Pos)
|
||||
#define ARM_SAI_SLOT_COUNT(n) ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Slot Size -----*/
|
||||
#define ARM_SAI_SLOT_SIZE_Pos 25
|
||||
#define ARM_SAI_SLOT_SIZE_Msk (3U << ARM_SAI_SLOT_SIZE_Pos)
|
||||
#define ARM_SAI_SLOT_SIZE_DEFAULT (0U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default)
|
||||
#define ARM_SAI_SLOT_SIZE_16 (1U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise)
|
||||
#define ARM_SAI_SLOT_SIZE_32 (3U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Slot Offset -----*/
|
||||
#define ARM_SAI_SLOT_OFFSET_Pos 27
|
||||
#define ARM_SAI_SLOT_OFFSET_Msk (0x1FU << ARM_SAI_SLOT_OFFSET_Pos)
|
||||
#define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)
|
||||
|
||||
/****** SAI Configuration (arg2) *****/
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/
|
||||
#define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFU) ///< Audio frequency mask
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/
|
||||
#define ARM_SAI_MCLK_PRESCALER_Pos 20
|
||||
#define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos)
|
||||
#define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)
|
||||
|
||||
|
||||
/****** SAI specific error codes *****/
|
||||
#define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported
|
||||
#define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported
|
||||
#define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported
|
||||
#define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported
|
||||
#define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported
|
||||
#define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported
|
||||
#define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported
|
||||
#define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported
|
||||
#define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported
|
||||
#define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported
|
||||
#define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported
|
||||
#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported
|
||||
#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported
|
||||
#define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported
|
||||
#define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported
|
||||
#define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported
|
||||
#define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported
|
||||
|
||||
|
||||
/**
|
||||
\brief SAI Status
|
||||
*/
|
||||
typedef volatile struct _ARM_SAI_STATUS {
|
||||
uint32_t tx_busy : 1; ///< Transmitter busy flag
|
||||
uint32_t rx_busy : 1; ///< Receiver busy flag
|
||||
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
|
||||
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
|
||||
uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation)
|
||||
uint32_t reserved : 27;
|
||||
} ARM_SAI_STATUS;
|
||||
|
||||
|
||||
/****** SAI Event *****/
|
||||
#define ARM_SAI_EVENT_SEND_COMPLETE (1U << 0) ///< Send completed
|
||||
#define ARM_SAI_EVENT_RECEIVE_COMPLETE (1U << 1) ///< Receive completed
|
||||
#define ARM_SAI_EVENT_TX_UNDERFLOW (1U << 2) ///< Transmit data not available
|
||||
#define ARM_SAI_EVENT_RX_OVERFLOW (1U << 3) ///< Receive data overflow
|
||||
#define ARM_SAI_EVENT_FRAME_ERROR (1U << 4) ///< Sync Frame error in Slave mode (optional)
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_SAI_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
|
||||
\brief Initialize SAI Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_Uninitialize (void)
|
||||
\brief De-initialize SAI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control SAI Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to SAI transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to SAI transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from SAI receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from SAI receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_SAI_GetTxCount (void)
|
||||
\brief Get transmitted data count.
|
||||
\return number of data items transmitted
|
||||
|
||||
\fn uint32_t ARM_SAI_GetRxCount (void)
|
||||
\brief Get received data count.
|
||||
\return number of data items received
|
||||
|
||||
\fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
|
||||
\brief Control SAI Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg1 Argument 1 of operation (optional)
|
||||
\param[in] arg2 Argument 2 of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref sai_execution_status
|
||||
|
||||
\fn ARM_SAI_STATUS ARM_SAI_GetStatus (void)
|
||||
\brief Get SAI status.
|
||||
\return SAI status \ref ARM_SAI_STATUS
|
||||
|
||||
\fn void ARM_SAI_SignalEvent (uint32_t event)
|
||||
\brief Signal SAI Events.
|
||||
\param[in] event \ref SAI_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief SAI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_SAI_CAPABILITIES {
|
||||
uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive
|
||||
uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive
|
||||
uint32_t protocol_user : 1; ///< supports user defined Protocol
|
||||
uint32_t protocol_i2s : 1; ///< supports I2S Protocol
|
||||
uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol
|
||||
uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol
|
||||
uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol
|
||||
uint32_t mono_mode : 1; ///< supports Mono mode
|
||||
uint32_t companding : 1; ///< supports Companding
|
||||
uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin
|
||||
uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
|
||||
uint32_t reserved : 21; ///< Reserved (must be zero)
|
||||
} ARM_SAI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the SAI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_SAI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version.
|
||||
ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface.
|
||||
uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count.
|
||||
uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface.
|
||||
ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status.
|
||||
} const ARM_DRIVER_SAI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_SAI_H_ */
|
||||
@@ -0,0 +1,247 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: SPI (Serial Peripheral Interface) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* ARM_SPI_STATUS made volatile
|
||||
* Version 2.1
|
||||
* Renamed status flag "tx_rx_busy" to "busy"
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* Added:
|
||||
* Slave Mode
|
||||
* Half-duplex Modes
|
||||
* Configurable number of data bits
|
||||
* Support for TI Mode and Microwire
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Added "send_done_event" to Capabilities
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SPI_H_
|
||||
#define DRIVER_SPI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
|
||||
|
||||
|
||||
/****** SPI Control Codes *****/
|
||||
|
||||
#define ARM_SPI_CONTROL_Pos 0
|
||||
#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos)
|
||||
|
||||
/*----- SPI Control Codes: Mode -----*/
|
||||
#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive
|
||||
#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
|
||||
#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI)
|
||||
#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
|
||||
#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO)
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
|
||||
#define ARM_SPI_FRAME_FORMAT_Pos 8
|
||||
#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos)
|
||||
#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default)
|
||||
#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1
|
||||
#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0
|
||||
#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1
|
||||
#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format
|
||||
#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Microwire Frame Format
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
|
||||
#define ARM_SPI_DATA_BITS_Pos 12
|
||||
#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos)
|
||||
#define ARM_SPI_DATA_BITS(n) (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
|
||||
#define ARM_SPI_BIT_ORDER_Pos 18
|
||||
#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos)
|
||||
#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default)
|
||||
#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
|
||||
#define ARM_SPI_SS_MASTER_MODE_Pos 19
|
||||
#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
|
||||
#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
|
||||
#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
|
||||
#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
|
||||
#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
|
||||
#define ARM_SPI_SS_SLAVE_MODE_Pos 21
|
||||
#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
|
||||
#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default)
|
||||
#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled
|
||||
|
||||
|
||||
/*----- SPI Control Codes: Miscellaneous Controls -----*/
|
||||
#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value
|
||||
#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps
|
||||
#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value
|
||||
#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active
|
||||
#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer
|
||||
|
||||
|
||||
/****** SPI Slave Select Signal definitions *****/
|
||||
#define ARM_SPI_SS_INACTIVE 0 ///< SPI Slave Select Signal Inactive
|
||||
#define ARM_SPI_SS_ACTIVE 1 ///< SPI Slave Select Signal Active
|
||||
|
||||
|
||||
/****** SPI specific error codes *****/
|
||||
#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
|
||||
#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported
|
||||
#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
|
||||
#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported
|
||||
#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported
|
||||
|
||||
|
||||
/**
|
||||
\brief SPI Status
|
||||
*/
|
||||
typedef volatile struct _ARM_SPI_STATUS {
|
||||
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
|
||||
uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
|
||||
uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation)
|
||||
uint32_t reserved : 29;
|
||||
} ARM_SPI_STATUS;
|
||||
|
||||
|
||||
/****** SPI Event *****/
|
||||
#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed
|
||||
#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow
|
||||
#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master)
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_SPI_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
|
||||
\brief Initialize SPI Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Uninitialize (void)
|
||||
\brief De-initialize SPI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control SPI Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to SPI transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to SPI transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from SPI receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from SPI receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Transfer (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num)
|
||||
\brief Start sending/receiving data to/from SPI transmitter/receiver.
|
||||
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
|
||||
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
|
||||
\param[in] num Number of data items to transfer
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_SPI_GetDataCount (void)
|
||||
\brief Get transferred data count.
|
||||
\return number of data items transferred
|
||||
|
||||
\fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control SPI Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref spi_execution_status
|
||||
|
||||
\fn ARM_SPI_STATUS ARM_SPI_GetStatus (void)
|
||||
\brief Get SPI status.
|
||||
\return SPI status \ref ARM_SPI_STATUS
|
||||
|
||||
\fn void ARM_SPI_SignalEvent (uint32_t event)
|
||||
\brief Signal SPI Events.
|
||||
\param[in] event \ref SPI_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief SPI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_SPI_CAPABILITIES {
|
||||
uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave)
|
||||
uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface
|
||||
uint32_t microwire : 1; ///< supports Microwire Interface
|
||||
uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
|
||||
uint32_t reserved : 28; ///< Reserved (must be zero)
|
||||
} ARM_SPI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the SPI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_SPI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
|
||||
ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
|
||||
int32_t (*Transfer) (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
|
||||
uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
|
||||
ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
|
||||
} const ARM_DRIVER_SPI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_SPI_H_ */
|
||||
@@ -0,0 +1,341 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.3
|
||||
*
|
||||
* Project: USART (Universal Synchronous Asynchronous Receiver Transmitter)
|
||||
* Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.3
|
||||
* ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
|
||||
* Version 2.2
|
||||
* Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
|
||||
* Version 2.1
|
||||
* Removed optional argument parameter from Signal Event
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* renamed driver UART -> USART (Asynchronous & Synchronous)
|
||||
* Added modes:
|
||||
* Synchronous
|
||||
* Single-wire
|
||||
* IrDA
|
||||
* Smart Card
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Added events:
|
||||
* ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT
|
||||
* ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
|
||||
* Added functions: SetTxThreshold, SetRxThreshold
|
||||
* Added "rx_timeout_event" to capabilities
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_USART_H_
|
||||
#define DRIVER_USART_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
|
||||
|
||||
|
||||
/****** USART Control Codes *****/
|
||||
|
||||
#define ARM_USART_CONTROL_Pos 0
|
||||
#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos)
|
||||
|
||||
/*----- USART Control Codes: Mode -----*/
|
||||
#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate
|
||||
#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate
|
||||
#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal)
|
||||
#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate
|
||||
#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate
|
||||
#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
|
||||
#define ARM_USART_DATA_BITS_Pos 8
|
||||
#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos)
|
||||
#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits
|
||||
#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit
|
||||
#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits
|
||||
#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default)
|
||||
#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Parity -----*/
|
||||
#define ARM_USART_PARITY_Pos 12
|
||||
#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos)
|
||||
#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default)
|
||||
#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity
|
||||
#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
|
||||
#define ARM_USART_STOP_BITS_Pos 14
|
||||
#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos)
|
||||
#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default)
|
||||
#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits
|
||||
#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits
|
||||
#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
|
||||
#define ARM_USART_FLOW_CONTROL_Pos 16
|
||||
#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos)
|
||||
#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
|
||||
#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
|
||||
#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
|
||||
#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
|
||||
#define ARM_USART_CPOL_Pos 18
|
||||
#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos)
|
||||
#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default)
|
||||
#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
|
||||
#define ARM_USART_CPHA_Pos 19
|
||||
#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos)
|
||||
#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default)
|
||||
#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1
|
||||
|
||||
|
||||
/*----- USART Control Codes: Miscellaneous Controls -----*/
|
||||
#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value
|
||||
#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
|
||||
#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods
|
||||
#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
|
||||
#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send
|
||||
#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive
|
||||
#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer
|
||||
|
||||
|
||||
|
||||
/****** USART specific error codes *****/
|
||||
#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
|
||||
#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported
|
||||
#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
|
||||
#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported
|
||||
#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported
|
||||
#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported
|
||||
#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported
|
||||
#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported
|
||||
|
||||
|
||||
/**
|
||||
\brief USART Status
|
||||
*/
|
||||
typedef volatile struct _ARM_USART_STATUS {
|
||||
uint32_t tx_busy : 1; ///< Transmitter busy flag
|
||||
uint32_t rx_busy : 1; ///< Receiver busy flag
|
||||
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
|
||||
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
|
||||
uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
|
||||
uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
|
||||
uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
|
||||
uint32_t reserved : 25;
|
||||
} ARM_USART_STATUS;
|
||||
|
||||
/**
|
||||
\brief USART Modem Control
|
||||
*/
|
||||
typedef enum _ARM_USART_MODEM_CONTROL {
|
||||
ARM_USART_RTS_CLEAR, ///< Deactivate RTS
|
||||
ARM_USART_RTS_SET, ///< Activate RTS
|
||||
ARM_USART_DTR_CLEAR, ///< Deactivate DTR
|
||||
ARM_USART_DTR_SET ///< Activate DTR
|
||||
} ARM_USART_MODEM_CONTROL;
|
||||
|
||||
/**
|
||||
\brief USART Modem Status
|
||||
*/
|
||||
typedef volatile struct _ARM_USART_MODEM_STATUS {
|
||||
uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
|
||||
uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
|
||||
uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
|
||||
uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
|
||||
uint32_t reserved : 28;
|
||||
} ARM_USART_MODEM_STATUS;
|
||||
|
||||
|
||||
/****** USART Event *****/
|
||||
#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data
|
||||
#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
|
||||
#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed
|
||||
#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional)
|
||||
#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave)
|
||||
#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow
|
||||
#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional)
|
||||
#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive
|
||||
#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive
|
||||
#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive
|
||||
#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional)
|
||||
#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional)
|
||||
#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional)
|
||||
#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional)
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
|
||||
\brief Get driver capabilities
|
||||
\return \ref ARM_USART_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
|
||||
\brief Initialize USART Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_USART_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Uninitialize (void)
|
||||
\brief De-initialize USART Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control USART Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to USART transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to USART transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from USART receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from USART receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Transfer (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num)
|
||||
\brief Start sending/receiving data to/from USART transmitter/receiver.
|
||||
\param[in] data_out Pointer to buffer with data to send to USART transmitter
|
||||
\param[out] data_in Pointer to buffer for data to receive from USART receiver
|
||||
\param[in] num Number of data items to transfer
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_USART_GetTxCount (void)
|
||||
\brief Get transmitted data count.
|
||||
\return number of data items transmitted
|
||||
|
||||
\fn uint32_t ARM_USART_GetRxCount (void)
|
||||
\brief Get received data count.
|
||||
\return number of data items received
|
||||
|
||||
\fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control USART Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref usart_execution_status
|
||||
|
||||
\fn ARM_USART_STATUS ARM_USART_GetStatus (void)
|
||||
\brief Get USART status.
|
||||
\return USART status \ref ARM_USART_STATUS
|
||||
|
||||
\fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
|
||||
\brief Set USART Modem Control line state.
|
||||
\param[in] control \ref ARM_USART_MODEM_CONTROL
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
|
||||
\brief Get USART Modem Status lines state.
|
||||
\return modem status \ref ARM_USART_MODEM_STATUS
|
||||
|
||||
\fn void ARM_USART_SignalEvent (uint32_t event)
|
||||
\brief Signal USART Events.
|
||||
\param[in] event \ref USART_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief USART Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_USART_CAPABILITIES {
|
||||
uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
|
||||
uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
|
||||
uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
|
||||
uint32_t single_wire : 1; ///< supports UART Single-wire mode
|
||||
uint32_t irda : 1; ///< supports UART IrDA mode
|
||||
uint32_t smart_card : 1; ///< supports UART Smart Card mode
|
||||
uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
|
||||
uint32_t flow_control_rts : 1; ///< RTS Flow Control available
|
||||
uint32_t flow_control_cts : 1; ///< CTS Flow Control available
|
||||
uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
|
||||
uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
|
||||
uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
|
||||
uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
|
||||
uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
|
||||
uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
|
||||
uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
|
||||
uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
|
||||
uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
|
||||
uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
|
||||
uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
|
||||
uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI
|
||||
uint32_t reserved : 11; ///< Reserved (must be zero)
|
||||
} ARM_USART_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the USART Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_USART {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
|
||||
ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
|
||||
int32_t (*Transfer) (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
|
||||
uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
|
||||
uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
|
||||
ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
|
||||
int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
|
||||
ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
|
||||
} const ARM_DRIVER_USART;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_USART_H_ */
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.0
|
||||
*
|
||||
* Project: USB Driver common definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.0
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Added PID Types
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_USB_H_
|
||||
#define DRIVER_USB_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
/* USB Role */
|
||||
#define ARM_USB_ROLE_NONE (0)
|
||||
#define ARM_USB_ROLE_HOST (1)
|
||||
#define ARM_USB_ROLE_DEVICE (2)
|
||||
|
||||
/* USB Pins */
|
||||
#define ARM_USB_PIN_DP (1 << 0) ///< USB D+ pin
|
||||
#define ARM_USB_PIN_DM (1 << 1) ///< USB D- pin
|
||||
#define ARM_USB_PIN_VBUS (1 << 2) ///< USB VBUS pin
|
||||
#define ARM_USB_PIN_OC (1 << 3) ///< USB OverCurrent pin
|
||||
#define ARM_USB_PIN_ID (1 << 4) ///< USB ID pin
|
||||
|
||||
/* USB Speed */
|
||||
#define ARM_USB_SPEED_LOW (0) ///< Low-speed USB
|
||||
#define ARM_USB_SPEED_FULL (1) ///< Full-speed USB
|
||||
#define ARM_USB_SPEED_HIGH (2) ///< High-speed USB
|
||||
|
||||
/* USB PID Types */
|
||||
#define ARM_USB_PID_OUT (1)
|
||||
#define ARM_USB_PID_IN (9)
|
||||
#define ARM_USB_PID_SOF (5)
|
||||
#define ARM_USB_PID_SETUP (13)
|
||||
#define ARM_USB_PID_DATA0 (3)
|
||||
#define ARM_USB_PID_DATA1 (11)
|
||||
#define ARM_USB_PID_DATA2 (7)
|
||||
#define ARM_USB_PID_MDATA (15)
|
||||
#define ARM_USB_PID_ACK (2)
|
||||
#define ARM_USB_PID_NAK (10)
|
||||
#define ARM_USB_PID_STALL (14)
|
||||
#define ARM_USB_PID_NYET (6)
|
||||
#define ARM_USB_PID_PRE (12)
|
||||
#define ARM_USB_PID_ERR (12)
|
||||
#define ARM_USB_PID_SPLIT (8)
|
||||
#define ARM_USB_PID_PING (4)
|
||||
#define ARM_USB_PID_RESERVED (0)
|
||||
|
||||
/* USB Endpoint Address (bEndpointAddress) */
|
||||
#define ARM_USB_ENDPOINT_NUMBER_MASK (0x0F)
|
||||
#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80)
|
||||
|
||||
/* USB Endpoint Type */
|
||||
#define ARM_USB_ENDPOINT_CONTROL (0) ///< Control Endpoint
|
||||
#define ARM_USB_ENDPOINT_ISOCHRONOUS (1) ///< Isochronous Endpoint
|
||||
#define ARM_USB_ENDPOINT_BULK (2) ///< Bulk Endpoint
|
||||
#define ARM_USB_ENDPOINT_INTERRUPT (3) ///< Interrupt Endpoint
|
||||
|
||||
/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */
|
||||
#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK (0x07FF)
|
||||
#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK (0x1800)
|
||||
#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1 (0x0000)
|
||||
#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2 (0x0800)
|
||||
#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3 (0x1000)
|
||||
|
||||
#endif /* DRIVER_USB_H_ */
|
||||
@@ -0,0 +1,273 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: USB Device Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* ARM_USBD_STATE made volatile
|
||||
* Version 2.1
|
||||
* Added ARM_USBD_ReadSetupPacket function
|
||||
* Version 2.0
|
||||
* Removed ARM_USBD_DeviceConfigure function
|
||||
* Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function
|
||||
* Removed ARM_USBD_EndpointReadStart function
|
||||
* Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer
|
||||
* Added ARM_USBD_EndpointTransferGetResult function
|
||||
* Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Changed return values of some functions to int32_t
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_USBD_H_
|
||||
#define DRIVER_USBD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_USB.h"
|
||||
|
||||
#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
|
||||
|
||||
|
||||
/**
|
||||
\brief USB Device State
|
||||
*/
|
||||
typedef volatile struct _ARM_USBD_STATE {
|
||||
uint32_t vbus : 1; ///< USB Device VBUS flag
|
||||
uint32_t speed : 2; ///< USB Device speed setting (ARM_USB_SPEED_xxx)
|
||||
uint32_t active : 1; ///< USB Device active flag
|
||||
uint32_t reserved : 28;
|
||||
} ARM_USBD_STATE;
|
||||
|
||||
|
||||
/****** USB Device Event *****/
|
||||
#define ARM_USBD_EVENT_VBUS_ON (1UL << 0) ///< USB Device VBUS On
|
||||
#define ARM_USBD_EVENT_VBUS_OFF (1UL << 1) ///< USB Device VBUS Off
|
||||
#define ARM_USBD_EVENT_RESET (1UL << 2) ///< USB Reset occurred
|
||||
#define ARM_USBD_EVENT_HIGH_SPEED (1UL << 3) ///< USB switch to High Speed occurred
|
||||
#define ARM_USBD_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred
|
||||
#define ARM_USBD_EVENT_RESUME (1UL << 5) ///< USB Resume occurred
|
||||
|
||||
/****** USB Endpoint Event *****/
|
||||
#define ARM_USBD_EVENT_SETUP (1UL << 0) ///< SETUP Packet
|
||||
#define ARM_USBD_EVENT_OUT (1UL << 1) ///< OUT Packet(s)
|
||||
#define ARM_USBD_EVENT_IN (1UL << 2) ///< IN Packet(s)
|
||||
|
||||
|
||||
#ifndef __DOXYGEN_MW__ // exclude from middleware documentation
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_USBD_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event,
|
||||
ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
|
||||
\brief Initialize USB Device Interface.
|
||||
\param[in] cb_device_event Pointer to \ref ARM_USBD_SignalDeviceEvent
|
||||
\param[in] cb_endpoint_event Pointer to \ref ARM_USBD_SignalEndpointEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_Uninitialize (void)
|
||||
\brief De-initialize USB Device Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control USB Device Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_DeviceConnect (void)
|
||||
\brief Connect USB Device.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_DeviceDisconnect (void)
|
||||
\brief Disconnect USB Device.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_USBD_STATE ARM_USBD_DeviceGetState (void)
|
||||
\brief Get current USB Device State.
|
||||
\return Device State \ref ARM_USBD_STATE
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_DeviceRemoteWakeup (void)
|
||||
\brief Trigger USB Remote Wakeup.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)
|
||||
\brief Set USB Device Address.
|
||||
\param[in] dev_addr Device Address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)
|
||||
\brief Read setup packet received over Control Endpoint.
|
||||
\param[out] setup Pointer to buffer for setup packet
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_EndpointConfigure (uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_max_packet_size)
|
||||
\brief Configure USB Endpoint.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx)
|
||||
\param[in] ep_max_packet_size Endpoint Maximum Packet Size
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)
|
||||
\brief Unconfigure USB Endpoint.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)
|
||||
\brief Set/Clear Stall for USB Endpoint.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\param[in] stall Operation
|
||||
- \b false Clear
|
||||
- \b true Set
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
|
||||
\brief Read data from or Write data to USB Endpoint.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\param[out] data Pointer to buffer for data to read or with data to write
|
||||
\param[in] num Number of data bytes to transfer
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)
|
||||
\brief Get result of USB Endpoint transfer.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\return number of successfully transferred data bytes
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)
|
||||
\brief Abort current USB Endpoint transfer.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn uint16_t ARM_USBD_GetFrameNumber (void)
|
||||
\brief Get current USB Frame Number.
|
||||
\return Frame Number
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_USBD_SignalDeviceEvent (uint32_t event)
|
||||
\brief Signal USB Device Event.
|
||||
\param[in] event \ref USBD_dev_events
|
||||
\return none
|
||||
*/
|
||||
/**
|
||||
\fn void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)
|
||||
\brief Signal USB Endpoint Event.
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\param[in] event \ref USBD_ep_events
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_USBD_SignalDeviceEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.
|
||||
typedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event); ///< Pointer to \ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief USB Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_USBD_CAPABILITIES {
|
||||
uint32_t vbus_detection : 1; ///< VBUS detection
|
||||
uint32_t event_vbus_on : 1; ///< Signal VBUS On event
|
||||
uint32_t event_vbus_off : 1; ///< Signal VBUS Off event
|
||||
uint32_t reserved : 29; ///< Reserved (must be zero)
|
||||
} ARM_USBD_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the USB Device Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_USBD {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBD_GetVersion : Get driver version.
|
||||
ARM_USBD_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBD_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_USBD_SignalDeviceEvent_t cb_device_event,
|
||||
ARM_USBD_SignalEndpointEvent_t cb_endpoint_event); ///< Pointer to \ref ARM_USBD_Initialize : Initialize USB Device Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBD_PowerControl : Control USB Device Interface Power.
|
||||
int32_t (*DeviceConnect) (void); ///< Pointer to \ref ARM_USBD_DeviceConnect : Connect USB Device.
|
||||
int32_t (*DeviceDisconnect) (void); ///< Pointer to \ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.
|
||||
ARM_USBD_STATE (*DeviceGetState) (void); ///< Pointer to \ref ARM_USBD_DeviceGetState : Get current USB Device State.
|
||||
int32_t (*DeviceRemoteWakeup) (void); ///< Pointer to \ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.
|
||||
int32_t (*DeviceSetAddress) (uint8_t dev_addr); ///< Pointer to \ref ARM_USBD_DeviceSetAddress : Set USB Device Address.
|
||||
int32_t (*ReadSetupPacket) (uint8_t *setup); ///< Pointer to \ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.
|
||||
int32_t (*EndpointConfigure) (uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.
|
||||
int32_t (*EndpointUnconfigure) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.
|
||||
int32_t (*EndpointStall) (uint8_t ep_addr, bool stall); ///< Pointer to \ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.
|
||||
int32_t (*EndpointTransfer) (uint8_t ep_addr, uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.
|
||||
uint32_t (*EndpointTransferGetResult) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.
|
||||
int32_t (*EndpointTransferAbort) (uint8_t ep_addr); ///< Pointer to \ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.
|
||||
uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.
|
||||
} const ARM_DRIVER_USBD;
|
||||
|
||||
#endif /* __DOXYGEN_MW__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_USBD_H_ */
|
||||
@@ -0,0 +1,417 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: USB Host Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* ARM_USBH_PORT_STATE made volatile
|
||||
* Version 2.1
|
||||
* Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE
|
||||
* Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...
|
||||
* Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent
|
||||
* Version 2.0
|
||||
* Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff
|
||||
* Changed function ARM_USBH_EndpointCreate parameters
|
||||
* Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify
|
||||
* Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset
|
||||
* Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer
|
||||
* Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort
|
||||
* Added function ARM_USBH_EndpointTransferGetResult
|
||||
* Added function ARM_USBH_GetFrameNumber
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.20
|
||||
* Added API for OHCI/EHCI Host Controller Interface (HCI)
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_USBH_H_
|
||||
#define DRIVER_USBH_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_USB.h"
|
||||
|
||||
#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
|
||||
|
||||
|
||||
/**
|
||||
\brief USB Host Port State
|
||||
*/
|
||||
typedef volatile struct _ARM_USBH_PORT_STATE {
|
||||
uint32_t connected : 1; ///< USB Host Port connected flag
|
||||
uint32_t overcurrent : 1; ///< USB Host Port overcurrent flag
|
||||
uint32_t speed : 2; ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)
|
||||
uint32_t reserved : 28;
|
||||
} ARM_USBH_PORT_STATE;
|
||||
|
||||
/**
|
||||
\brief USB Host Pipe Handle
|
||||
*/
|
||||
typedef uint32_t ARM_USBH_PIPE_HANDLE;
|
||||
#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE /* Legacy name */
|
||||
|
||||
|
||||
/****** USB Host Packet Information *****/
|
||||
#define ARM_USBH_PACKET_TOKEN_Pos 0
|
||||
#define ARM_USBH_PACKET_TOKEN_Msk (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)
|
||||
#define ARM_USBH_PACKET_SETUP (0x01UL << ARM_USBH_PACKET_TOKEN_Pos) ///< SETUP Packet
|
||||
#define ARM_USBH_PACKET_OUT (0x02UL << ARM_USBH_PACKET_TOKEN_Pos) ///< OUT Packet
|
||||
#define ARM_USBH_PACKET_IN (0x03UL << ARM_USBH_PACKET_TOKEN_Pos) ///< IN Packet
|
||||
#define ARM_USBH_PACKET_PING (0x04UL << ARM_USBH_PACKET_TOKEN_Pos) ///< PING Packet
|
||||
|
||||
#define ARM_USBH_PACKET_DATA_Pos 4
|
||||
#define ARM_USBH_PACKET_DATA_Msk (0x0FUL << ARM_USBH_PACKET_DATA_Pos)
|
||||
#define ARM_USBH_PACKET_DATA0 (0x01UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA0 PID
|
||||
#define ARM_USBH_PACKET_DATA1 (0x02UL << ARM_USBH_PACKET_DATA_Pos) ///< DATA1 PID
|
||||
|
||||
#define ARM_USBH_PACKET_SPLIT_Pos 8
|
||||
#define ARM_USBH_PACKET_SPLIT_Msk (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)
|
||||
#define ARM_USBH_PACKET_SSPLIT (0x08UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet
|
||||
#define ARM_USBH_PACKET_SSPLIT_S (0x09UL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data Start
|
||||
#define ARM_USBH_PACKET_SSPLIT_E (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data End
|
||||
#define ARM_USBH_PACKET_SSPLIT_S_E (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos) ///< SSPLIT Packet: Data All
|
||||
#define ARM_USBH_PACKET_CSPLIT (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos) ///< CSPLIT Packet
|
||||
|
||||
#define ARM_USBH_PACKET_PRE (1UL << 12) ///< PRE Token
|
||||
|
||||
|
||||
/****** USB Host Port Event *****/
|
||||
#define ARM_USBH_EVENT_CONNECT (1UL << 0) ///< USB Device Connected to Port
|
||||
#define ARM_USBH_EVENT_DISCONNECT (1UL << 1) ///< USB Device Disconnected from Port
|
||||
#define ARM_USBH_EVENT_OVERCURRENT (1UL << 2) ///< USB Device caused Overcurrent
|
||||
#define ARM_USBH_EVENT_RESET (1UL << 3) ///< USB Reset completed
|
||||
#define ARM_USBH_EVENT_SUSPEND (1UL << 4) ///< USB Suspend occurred
|
||||
#define ARM_USBH_EVENT_RESUME (1UL << 5) ///< USB Resume occurred
|
||||
#define ARM_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) ///< USB Device activated Remote Wakeup
|
||||
|
||||
/****** USB Host Pipe Event *****/
|
||||
#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Transfer completed
|
||||
#define ARM_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) ///< NAK Handshake received
|
||||
#define ARM_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) ///< NYET Handshake received
|
||||
#define ARM_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) ///< MDATA Handshake received
|
||||
#define ARM_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) ///< STALL Handshake received
|
||||
#define ARM_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) ///< ERR Handshake received
|
||||
#define ARM_USBH_EVENT_BUS_ERROR (1UL << 6) ///< Bus Error detected
|
||||
|
||||
|
||||
#ifndef __DOXYGEN_MW__ // exclude from middleware documentation
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_USBH_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,
|
||||
ARM_USBH_SignalPipeEvent_t cb_pipe_event)
|
||||
\brief Initialize USB Host Interface.
|
||||
\param[in] cb_port_event Pointer to \ref ARM_USBH_SignalPortEvent
|
||||
\param[in] cb_pipe_event Pointer to \ref ARM_USBH_SignalPipeEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_Uninitialize (void)
|
||||
\brief De-initialize USB Host Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control USB Host Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)
|
||||
\brief Root HUB Port VBUS on/off.
|
||||
\param[in] port Root HUB Port Number
|
||||
\param[in] vbus
|
||||
- \b false VBUS off
|
||||
- \b true VBUS on
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PortReset (uint8_t port)
|
||||
\brief Do Root HUB Port Reset.
|
||||
\param[in] port Root HUB Port Number
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PortSuspend (uint8_t port)
|
||||
\brief Suspend Root HUB Port (stop generating SOFs).
|
||||
\param[in] port Root HUB Port Number
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PortResume (uint8_t port)
|
||||
\brief Resume Root HUB Port (start generating SOFs).
|
||||
\param[in] port Root HUB Port Number
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)
|
||||
\brief Get current Root HUB Port State.
|
||||
\param[in] port Root HUB Port Number
|
||||
\return Port State \ref ARM_USBH_PORT_STATE
|
||||
*/
|
||||
/**
|
||||
\fn ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t hub_addr,
|
||||
uint8_t hub_port,
|
||||
uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_max_packet_size,
|
||||
uint8_t ep_interval)
|
||||
\brief Create Pipe in System.
|
||||
\param[in] dev_addr Device Address
|
||||
\param[in] dev_speed Device Speed
|
||||
\param[in] hub_addr Hub Address
|
||||
\param[in] hub_port Hub Port
|
||||
\param[in] ep_addr Endpoint Address
|
||||
- ep_addr.0..3: Address
|
||||
- ep_addr.7: Direction
|
||||
\param[in] ep_type Endpoint Type (ARM_USB_ENDPOINT_xxx)
|
||||
\param[in] ep_max_packet_size Endpoint Maximum Packet Size
|
||||
\param[in] ep_interval Endpoint Polling Interval
|
||||
\return Pipe Handle \ref ARM_USBH_PIPE_HANDLE
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,
|
||||
uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t hub_addr,
|
||||
uint8_t hub_port,
|
||||
uint16_t ep_max_packet_size)
|
||||
\brief Modify Pipe in System.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\param[in] dev_addr Device Address
|
||||
\param[in] dev_speed Device Speed
|
||||
\param[in] hub_addr Hub Address
|
||||
\param[in] hub_port Hub Port
|
||||
\param[in] ep_max_packet_size Endpoint Maximum Packet Size
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)
|
||||
\brief Delete Pipe from System.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)
|
||||
\brief Reset Pipe.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,
|
||||
uint32_t packet,
|
||||
uint8_t *data,
|
||||
uint32_t num)
|
||||
\brief Transfer packets through USB Pipe.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\param[in] packet Packet information
|
||||
\param[in] data Pointer to buffer with data to send or for data to receive
|
||||
\param[in] num Number of data bytes to transfer
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)
|
||||
\brief Get result of USB Pipe transfer.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\return number of successfully transferred data bytes
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)
|
||||
\brief Abort current USB Pipe transfer.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn uint16_t ARM_USBH_GetFrameNumber (void)
|
||||
\brief Get current USB Frame Number.
|
||||
\return Frame Number
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)
|
||||
\brief Signal Root HUB Port Event.
|
||||
\param[in] port Root HUB Port Number
|
||||
\param[in] event \ref USBH_port_events
|
||||
\return none
|
||||
*/
|
||||
/**
|
||||
\fn void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)
|
||||
\brief Signal Pipe Event.
|
||||
\param[in] pipe_hndl Pipe Handle
|
||||
\param[in] event \ref USBH_pipe_events
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.
|
||||
typedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); ///< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.
|
||||
#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t /* Legacy name */
|
||||
|
||||
|
||||
/**
|
||||
\brief USB Host Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_USBH_CAPABILITIES {
|
||||
uint32_t port_mask : 15; ///< Root HUB available Ports Mask
|
||||
uint32_t auto_split : 1; ///< Automatic SPLIT packet handling
|
||||
uint32_t event_connect : 1; ///< Signal Connect event
|
||||
uint32_t event_disconnect : 1; ///< Signal Disconnect event
|
||||
uint32_t event_overcurrent : 1; ///< Signal Overcurrent event
|
||||
uint32_t reserved : 13; ///< Reserved (must be zero)
|
||||
} ARM_USBH_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of USB Host Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_USBH {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_GetVersion : Get driver version.
|
||||
ARM_USBH_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_USBH_SignalPortEvent_t cb_port_event,
|
||||
ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power.
|
||||
int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.
|
||||
int32_t (*PortReset) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset.
|
||||
int32_t (*PortSuspend) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).
|
||||
int32_t (*PortResume) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).
|
||||
ARM_USBH_PORT_STATE (*PortGetState) (uint8_t port); ///< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State.
|
||||
ARM_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t hub_addr,
|
||||
uint8_t hub_port,
|
||||
uint8_t ep_addr,
|
||||
uint8_t ep_type,
|
||||
uint16_t ep_max_packet_size,
|
||||
uint8_t ep_interval); ///< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System.
|
||||
int32_t (*PipeModify) (ARM_USBH_PIPE_HANDLE pipe_hndl,
|
||||
uint8_t dev_addr,
|
||||
uint8_t dev_speed,
|
||||
uint8_t hub_addr,
|
||||
uint8_t hub_port,
|
||||
uint16_t ep_max_packet_size); ///< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System.
|
||||
int32_t (*PipeDelete) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System.
|
||||
int32_t (*PipeReset) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe.
|
||||
int32_t (*PipeTransfer) (ARM_USBH_PIPE_HANDLE pipe_hndl,
|
||||
uint32_t packet,
|
||||
uint8_t *data,
|
||||
uint32_t num); ///< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.
|
||||
uint32_t (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.
|
||||
int32_t (*PipeTransferAbort) (ARM_USBH_PIPE_HANDLE pipe_hndl); ///< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.
|
||||
uint16_t (*GetFrameNumber) (void); ///< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.
|
||||
} const ARM_DRIVER_USBH;
|
||||
|
||||
|
||||
// HCI (OHCI/EHCI)
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)
|
||||
\brief Get USB Host HCI (OHCI/EHCI) driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_USBH_HCI_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
|
||||
\brief Initialize USB Host HCI (OHCI/EHCI) Interface.
|
||||
\param[in] cb_interrupt Pointer to Interrupt Handler Routine
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_HCI_Uninitialize (void)
|
||||
\brief De-initialize USB Host HCI (OHCI/EHCI) Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control USB Host HCI (OHCI/EHCI) Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
|
||||
\brief USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
|
||||
\param[in] port Root HUB Port Number
|
||||
\param[in] vbus
|
||||
- \b false VBUS off
|
||||
- \b true VBUS on
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_USBH_HCI_Interrupt (void)
|
||||
\brief USB Host HCI Interrupt Handler.
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_USBH_HCI_Interrupt_t) (void); ///< Pointer to Interrupt Handler Routine.
|
||||
|
||||
|
||||
/**
|
||||
\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_USBH_HCI_CAPABILITIES {
|
||||
uint32_t port_mask : 15; ///< Root HUB available Ports Mask
|
||||
uint32_t reserved : 17; ///< Reserved (must be zero)
|
||||
} ARM_USBH_HCI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of USB Host HCI (OHCI/EHCI) Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_USBH_HCI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.
|
||||
ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.
|
||||
int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); ///< Pointer to \ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
|
||||
} const ARM_DRIVER_USBH_HCI;
|
||||
|
||||
#endif /* __DOXYGEN_MW__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_USBH_H_ */
|
||||
@@ -0,0 +1,121 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
7201
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/arm_math.h
Normal file
7201
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/arm_math.h
Normal file
File diff suppressed because it is too large
Load Diff
814
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/cmsis_armcc.h
Normal file
814
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/cmsis_armcc.h
Normal file
@@ -0,0 +1,814 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (ARM compiler V5) header file
|
||||
* @version V5.0.2
|
||||
* @date 13. February 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in integer value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in two unsigned short values.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value
|
||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1802
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/cmsis_armclang.h
Normal file
1802
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,353 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.2
|
||||
* @date 13. February 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* ARM Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* ARM Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
|
||||
#ifndef __ARM_ARCH_6M__
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
#elif (__CORE__ == __ARM7M__)
|
||||
#ifndef __ARM_ARCH_7M__
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#elif (__CORE__ == __ARM7EM__)
|
||||
#ifndef __ARM_ARCH_7EM__
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __noreturn
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __root
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
__packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
// Workaround for missing __CLZ intrinsic in
|
||||
// various versions of the IAR compilers.
|
||||
// __IAR_FEATURE_CLZ__ should be defined by
|
||||
// the compiler that supports __CLZ internally.
|
||||
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
|
||||
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0u) { return 32u; }
|
||||
|
||||
uint32_t count = 0;
|
||||
uint32_t mask = 0x80000000;
|
||||
|
||||
while ((data & mask) == 0)
|
||||
{
|
||||
count += 1u;
|
||||
mask = mask >> 1u;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TI ARM Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
1979
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/cmsis_gcc.h
Normal file
1979
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
1878
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_armv8mbl.h
Normal file
1878
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_armv8mbl.h
Normal file
File diff suppressed because it is too large
Load Diff
2902
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_armv8mml.h
Normal file
2902
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_armv8mml.h
Normal file
File diff suppressed because it is too large
Load Diff
888
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm0.h
Normal file
888
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm0.h
Normal file
@@ -0,0 +1,888 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
|
||||
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1021
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm0plus.h
Normal file
1021
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
1878
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm23.h
Normal file
1878
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1928
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm3.h
Normal file
1928
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
2898
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm33.h
Normal file
2898
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
2113
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm4.h
Normal file
2113
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2655
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm7.h
Normal file
2655
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
1016
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_sc000.h
Normal file
1016
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_sc000.h
Normal file
File diff suppressed because it is too large
Load Diff
1903
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_sc300.h
Normal file
1903
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/core_sc300.h
Normal file
File diff suppressed because it is too large
Load Diff
182
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/mpu_armv7.h
Normal file
182
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/Include/mpu_armv7.h
Normal file
@@ -0,0 +1,182 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for ARMv7 MPU
|
||||
* @version V5.0.2
|
||||
* @date 09. June 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0u
|
||||
#define ARM_MPU_AP_PRIV 1u
|
||||
#define ARM_MPU_AP_URO 2u
|
||||
#define ARM_MPU_AP_FULL 3u
|
||||
#define ARM_MPU_AP_PRO 5u
|
||||
#define ARM_MPU_AP_RO 6u
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
|
||||
|
||||
/**
|
||||
* MPU Region Attribut and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct _ARM_MPU_Region_t {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable()
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0u;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0u; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 21. September 2016
|
||||
* $Revision: V1.0
|
||||
*
|
||||
* Project: TrustZone for ARMv8-M
|
||||
* Title: Context Management for ARMv8-M TrustZone
|
||||
*
|
||||
* Version 1.0
|
||||
* Initial Release
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
201
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/LICENSE.txt
Normal file
201
platform/vendor_bsp/nxp/MIMXRT1052/CMSIS/LICENSE.txt
Normal file
@@ -0,0 +1,201 @@
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
the copyright owner that is granting the License.
|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
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|
||||
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|
||||
"control" means (i) the power, direct or indirect, to cause the
|
||||
direction or management of such entity, whether by contract or
|
||||
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|
||||
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|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
||||
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|
||||
|
||||
"Source" form shall mean the preferred form for making modifications,
|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or
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||||
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|
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||||
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||||
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END OF TERMS AND CONDITIONS
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|
||||
APPENDIX: How to apply the Apache License to your work.
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||||
|
||||
To apply the Apache License to your work, attach the following
|
||||
boilerplate notice, with the fields enclosed by brackets "{}"
|
||||
replaced with your own identifying information. (Don't include
|
||||
the brackets!) The text should be enclosed in the appropriate
|
||||
comment syntax for the file format. We also recommend that a
|
||||
file or class name and description of purpose be included on the
|
||||
same "printed page" as the copyright notice for easier
|
||||
identification within third-party archives.
|
||||
|
||||
Copyright {yyyy} {name of copyright owner}
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
29861
platform/vendor_bsp/nxp/MIMXRT1052/MIMXRT1052.h
Normal file
29861
platform/vendor_bsp/nxp/MIMXRT1052/MIMXRT1052.h
Normal file
File diff suppressed because it is too large
Load Diff
194800
platform/vendor_bsp/nxp/MIMXRT1052/MIMXRT1052.xml
Normal file
194800
platform/vendor_bsp/nxp/MIMXRT1052/MIMXRT1052.xml
Normal file
File diff suppressed because it is too large
Load Diff
592
platform/vendor_bsp/nxp/MIMXRT1052/MIMXRT1052_features.h
Normal file
592
platform/vendor_bsp/nxp/MIMXRT1052/MIMXRT1052_features.h
Normal file
@@ -0,0 +1,592 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b180312
|
||||
**
|
||||
** Abstract:
|
||||
** Chip specific module features.
|
||||
**
|
||||
** The Clear BSD License
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without
|
||||
** modification, are permitted (subject to the limitations in the
|
||||
** disclaimer below) provided that the following conditions are met:
|
||||
**
|
||||
** * Redistributions of source code must retain the above copyright
|
||||
** notice, this list of conditions and the following disclaimer.
|
||||
**
|
||||
** * Redistributions in binary form must reproduce the above copyright
|
||||
** notice, this list of conditions and the following disclaimer in the
|
||||
** documentation and/or other materials provided with the distribution.
|
||||
**
|
||||
** * Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from
|
||||
** this software without specific prior written permission.
|
||||
**
|
||||
** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
|
||||
** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
|
||||
** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 0.1 (2017-01-10)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#ifndef _MIMXRT1052_FEATURES_H_
|
||||
#define _MIMXRT1052_FEATURES_H_
|
||||
|
||||
/* SOC module features */
|
||||
|
||||
/* @brief ADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC_COUNT (2)
|
||||
/* @brief AIPSTZ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
|
||||
/* @brief AOI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AOI_COUNT (2)
|
||||
/* @brief CCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_COUNT (1)
|
||||
/* @brief CCM_ANALOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
|
||||
/* @brief CMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CMP_COUNT (4)
|
||||
/* @brief CSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CSI_COUNT (1)
|
||||
/* @brief DCDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCDC_COUNT (1)
|
||||
/* @brief DCP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCP_COUNT (1)
|
||||
/* @brief DMAMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
|
||||
/* @brief EDMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EDMA_COUNT (1)
|
||||
/* @brief ENC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ENC_COUNT (4)
|
||||
/* @brief ENET availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ENET_COUNT (1)
|
||||
/* @brief EWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EWM_COUNT (1)
|
||||
/* @brief FLEXCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
|
||||
/* @brief FLEXIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
|
||||
/* @brief FLEXRAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
|
||||
/* @brief FLEXSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
|
||||
/* @brief GPC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPC_COUNT (1)
|
||||
/* @brief GPT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPT_COUNT (2)
|
||||
/* @brief I2S availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_I2S_COUNT (3)
|
||||
/* @brief IGPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
|
||||
/* @brief IOMUXC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
|
||||
/* @brief IOMUXC_GPR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
|
||||
/* @brief IOMUXC_SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
|
||||
/* @brief KPP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_KPP_COUNT (1)
|
||||
/* @brief LCDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
|
||||
/* @brief LPI2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
|
||||
/* @brief LPSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
|
||||
/* @brief LPUART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPUART_COUNT (8)
|
||||
/* @brief OCOTP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
|
||||
/* @brief PIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PIT_COUNT (1)
|
||||
/* @brief PMU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PMU_COUNT (1)
|
||||
/* @brief PWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PWM_COUNT (4)
|
||||
/* @brief PXP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PXP_COUNT (1)
|
||||
/* @brief ROMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
|
||||
/* @brief SEMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
|
||||
/* @brief SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
|
||||
/* @brief SPDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
|
||||
/* @brief SRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SRC_COUNT (1)
|
||||
/* @brief TEMPMON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
|
||||
/* @brief TMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TMR_COUNT (4)
|
||||
/* @brief TRNG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
|
||||
/* @brief TSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSC_COUNT (1)
|
||||
/* @brief USBHS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
|
||||
/* @brief USBNC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
|
||||
/* @brief USBPHY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
|
||||
/* @brief USDHC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
|
||||
/* @brief WDOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
|
||||
/* @brief XBARA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
|
||||
/* @brief XBARB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
|
||||
/* @brief XTALOSC24M availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
|
||||
|
||||
/* ADC module features */
|
||||
|
||||
/* @brief Remove Hardware Trigger feature. */
|
||||
#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
|
||||
/* @brief Remove ALT Clock selection feature. */
|
||||
#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
|
||||
|
||||
/* ADC_ETC module features */
|
||||
|
||||
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
|
||||
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
|
||||
|
||||
/* AOI module features */
|
||||
|
||||
/* @brief Maximum value of input mux. */
|
||||
#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
|
||||
/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
|
||||
#define FSL_FEATURE_AOI_EVENT_COUNT (4)
|
||||
|
||||
/* FLEXCAN module features */
|
||||
|
||||
/* @brief Message buffer size */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
|
||||
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
|
||||
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
|
||||
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
|
||||
/* @brief Has extended bit timing register (register CBT). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
|
||||
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
|
||||
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
|
||||
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
|
||||
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
|
||||
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
|
||||
/* @brief Has extra MB interrupt or common one. */
|
||||
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
|
||||
|
||||
/* CMP module features */
|
||||
|
||||
/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
|
||||
#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
|
||||
/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
|
||||
#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
|
||||
/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
|
||||
#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
|
||||
/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
|
||||
#define FSL_FEATURE_CMP_HAS_DMA (1)
|
||||
/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
|
||||
#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
|
||||
/* @brief Has DAC Test function in CMP (register DACTEST). */
|
||||
#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
|
||||
|
||||
/* EDMA module features */
|
||||
|
||||
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
|
||||
/* @brief Total number of DMA channels on all modules. */
|
||||
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
|
||||
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
|
||||
/* @brief Has DMA_Error interrupt vector. */
|
||||
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
|
||||
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
|
||||
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
|
||||
|
||||
/* DMAMUX module features */
|
||||
|
||||
/* @brief Number of DMA channels (related to number of register CHCFGn). */
|
||||
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
|
||||
/* @brief Total number of DMA channels on all modules. */
|
||||
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
|
||||
/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
|
||||
#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
|
||||
/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
|
||||
#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
|
||||
|
||||
/* ENET module features */
|
||||
|
||||
/* @brief Support Interrupt Coalesce */
|
||||
#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
|
||||
/* @brief Queue Size. */
|
||||
#define FSL_FEATURE_ENET_QUEUE (1)
|
||||
/* @brief Has AVB Support. */
|
||||
#define FSL_FEATURE_ENET_HAS_AVB (0)
|
||||
/* @brief Has Timer Pulse Width control. */
|
||||
#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
|
||||
/* @brief Has Extend MDIO Support. */
|
||||
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
|
||||
/* @brief Has Additional 1588 Timer Channel Interrupt. */
|
||||
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
|
||||
|
||||
/* FLEXRAM module features */
|
||||
|
||||
/* @brief Bank size */
|
||||
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
|
||||
/* @brief Total Bank numbers */
|
||||
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
|
||||
|
||||
/* FLEXSPI module features */
|
||||
|
||||
/* @brief FlexSPI AHB buffer count */
|
||||
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
|
||||
/* @brief FlexSPI has no data learn. */
|
||||
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
|
||||
|
||||
/* GPC module features */
|
||||
|
||||
/* @brief Has DVFS0 Change Request. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0)
|
||||
/* @brief Has GPC interrupt/event masking. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0)
|
||||
/* @brief Has L2 cache power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0)
|
||||
/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1)
|
||||
/* @brief Has VADC power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0)
|
||||
/* @brief Has Display power control. */
|
||||
#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0)
|
||||
/* @brief Supports IRQ 0-31. */
|
||||
#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
|
||||
|
||||
/* IGPIO module features */
|
||||
|
||||
/* @brief Has data register set DR_SET. */
|
||||
#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
|
||||
/* @brief Has data register clear DR_CLEAR. */
|
||||
#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
|
||||
/* @brief Has data register toggle DR_TOGGLE. */
|
||||
#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
|
||||
|
||||
/* LCDIF module features */
|
||||
|
||||
/* @brief LCDIF does not support alpha support. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
|
||||
/* @brief LCDIF does not support output reset pin to LCD panel. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
|
||||
/* @brief LCDIF supports LUT. */
|
||||
#define FSL_FEATURE_LCDIF_HAS_LUT (1)
|
||||
|
||||
/* LPI2C module features */
|
||||
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
||||
|
||||
/* LPSPI module features */
|
||||
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
|
||||
/* LPUART module features */
|
||||
|
||||
/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
|
||||
/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
|
||||
/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_HAS_FIFO (1)
|
||||
/* @brief Has 32-bit register MODIR */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODIR (1)
|
||||
/* @brief Hardware flow control (RTS, CTS) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
|
||||
/* @brief Infrared (modulation) is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
|
||||
/* @brief 2 bits long stop bit is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
|
||||
/* @brief If 10-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
|
||||
/* @brief If 7-bit mode is supported. */
|
||||
#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
|
||||
/* @brief Baud rate fine adjustment is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
|
||||
/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
|
||||
/* @brief Baud rate oversampling is available. */
|
||||
#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
|
||||
/* @brief Peripheral type. */
|
||||
#define FSL_FEATURE_LPUART_IS_SCI (1)
|
||||
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
||||
#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
|
||||
/* @brief Maximal data width without parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
|
||||
/* @brief Maximal data width with parity bit. */
|
||||
#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
|
||||
/* @brief Supports two match addresses to filter incoming frames. */
|
||||
#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
|
||||
/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
|
||||
/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
|
||||
#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
|
||||
/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
|
||||
#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
|
||||
/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has improved smart card (ISO7816 protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
|
||||
/* @brief Has local operation network (CEA709.1-B protocol) support. */
|
||||
#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
|
||||
/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
|
||||
#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
|
||||
/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
|
||||
/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
|
||||
#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
|
||||
/* @brief Has separate DMA RX and TX requests. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
|
||||
/* @brief Has separate RX and TX interrupts. */
|
||||
#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
|
||||
/* @brief Has LPAURT_PARAM. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PARAM (1)
|
||||
/* @brief Has LPUART_VERID. */
|
||||
#define FSL_FEATURE_LPUART_HAS_VERID (1)
|
||||
/* @brief Has LPUART_GLOBAL. */
|
||||
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
|
||||
/* @brief Has LPUART_PINCFG. */
|
||||
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
|
||||
|
||||
/* interrupt module features */
|
||||
|
||||
/* @brief Lowest interrupt request number. */
|
||||
#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
|
||||
/* @brief Highest interrupt request number. */
|
||||
#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
|
||||
|
||||
/* OCOTP module features */
|
||||
|
||||
/* No feature definitions */
|
||||
|
||||
/* PIT module features */
|
||||
|
||||
/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
|
||||
#define FSL_FEATURE_PIT_TIMER_COUNT (4)
|
||||
/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
|
||||
#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
|
||||
/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
|
||||
#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
|
||||
/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
|
||||
#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
|
||||
/* @brief Has timer enable control. */
|
||||
#define FSL_FEATURE_PIT_HAS_MDIS (1)
|
||||
|
||||
/* PMU module features */
|
||||
|
||||
/* @brief PMU supports lower power control. */
|
||||
#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0)
|
||||
|
||||
/* PWM module features */
|
||||
|
||||
/* @brief Number of each EflexPWM module channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
|
||||
/* @brief Number of EflexPWM module A channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
|
||||
/* @brief Number of EflexPWM module B channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
|
||||
/* @brief Number of EflexPWM module X channels (outputs). */
|
||||
#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module compare channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module reload channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
|
||||
/* @brief Number of each EflexPWM module capture channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of each EflexPWM module reload error channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of each EflexPWM module fault channels interrupts. */
|
||||
#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
|
||||
/* @brief Number of submodules in each EflexPWM module. */
|
||||
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
|
||||
|
||||
/* PXP module features */
|
||||
|
||||
/* @brief PXP module has dither engine. */
|
||||
#define FSL_FEATURE_PXP_HAS_DITHER (0)
|
||||
/* @brief PXP module supports repeat run */
|
||||
#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
|
||||
/* @brief PXP doesn't have CSC */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
|
||||
/* @brief PXP doesn't have LUT */
|
||||
#define FSL_FEATURE_PXP_HAS_NO_LUT (1)
|
||||
|
||||
/* RTWDOG module features */
|
||||
|
||||
/* @brief Watchdog is available. */
|
||||
#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
|
||||
/* @brief RTWDOG_CNT can be 32-bit written. */
|
||||
#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
|
||||
|
||||
/* SAI module features */
|
||||
|
||||
/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
|
||||
#define FSL_FEATURE_SAI_FIFO_COUNT (32)
|
||||
/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
|
||||
#define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
|
||||
/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
|
||||
#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
|
||||
/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
|
||||
/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
|
||||
/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
|
||||
#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
|
||||
/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
|
||||
#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
|
||||
/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
|
||||
#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
|
||||
/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
|
||||
#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
|
||||
/* @brief Interrupt source number */
|
||||
#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
|
||||
/* @brief Has register of MCR. */
|
||||
#define FSL_FEATURE_SAI_HAS_MCR (0)
|
||||
/* @brief Has register of MDR */
|
||||
#define FSL_FEATURE_SAI_HAS_MDR (0)
|
||||
|
||||
/* SNVS module features */
|
||||
|
||||
/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
|
||||
#define FSL_FEATURE_SNVS_HAS_SRTC (1)
|
||||
|
||||
/* SRC module features */
|
||||
|
||||
/* @brief There is MASK_WDOG3_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1)
|
||||
/* @brief There is MIX_RST_STRCH bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0)
|
||||
/* @brief There is DBG_RST_MSK_PG bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1)
|
||||
/* @brief There is WDOG3_RST_OPTN bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0)
|
||||
/* @brief There is CORES_DBG_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0)
|
||||
/* @brief There is MTSR bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0)
|
||||
/* @brief There is CORE0_DBG_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1)
|
||||
/* @brief There is CORE0_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
|
||||
/* @brief There is LOCKUP_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
|
||||
/* @brief There is SWRC bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
|
||||
/* @brief There is EIM_RST bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0)
|
||||
/* @brief There is LUEN bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0)
|
||||
/* @brief There is no WRBC bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1)
|
||||
/* @brief There is no WRE bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1)
|
||||
/* @brief There is SISR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SISR (0)
|
||||
/* @brief There is RESET_OUT bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
|
||||
/* @brief There is WDOG3_RST_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
|
||||
/* @brief There is SW bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
|
||||
/* @brief There is IPP_USER_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1)
|
||||
/* @brief There is SNVS bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0)
|
||||
/* @brief There is CSU_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1)
|
||||
/* @brief There is LOCKUP bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0)
|
||||
/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1)
|
||||
/* @brief There is POR bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_POR (0)
|
||||
/* @brief There is IPP_RESET_B bit in SRSR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1)
|
||||
/* @brief There is no WBI bit in SCR register. */
|
||||
#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1)
|
||||
|
||||
/* SCB module features */
|
||||
|
||||
/* @brief L1 ICACHE line size in byte. */
|
||||
#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
|
||||
/* @brief L1 DCACHE line size in byte. */
|
||||
#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
|
||||
|
||||
/* TRNG module features */
|
||||
|
||||
/* @brief TRNG has no TRNG_ACC bitfield. */
|
||||
#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
|
||||
|
||||
/* USBHS module features */
|
||||
|
||||
/* @brief EHCI module instance count */
|
||||
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
|
||||
/* @brief Number of endpoints supported */
|
||||
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
|
||||
|
||||
/* USDHC module features */
|
||||
|
||||
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
||||
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
|
||||
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
||||
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
||||
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
|
||||
|
||||
/* XBARA module features */
|
||||
|
||||
/* @brief DMA_CH_MUX_REQ_30. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
|
||||
/* @brief DMA_CH_MUX_REQ_31. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
|
||||
/* @brief DMA_CH_MUX_REQ_94. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
|
||||
/* @brief DMA_CH_MUX_REQ_95. */
|
||||
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
|
||||
|
||||
#endif /* _MIMXRT1052_FEATURES_H_ */
|
||||
|
||||
2055
platform/vendor_bsp/nxp/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c
Normal file
2055
platform/vendor_bsp/nxp/MIMXRT1052/cmsis_drivers/fsl_lpi2c_cmsis.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_LPI2C_CMSIS_H_
|
||||
#define _FSL_LPI2C_CMSIS_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "Driver_I2C.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "fsl_lpi2c.h"
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
|
||||
#include "fsl_lpi2c_dma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_lpi2c_edma.h"
|
||||
#endif
|
||||
|
||||
#if defined(LPI2C0)
|
||||
extern ARM_DRIVER_I2C Driver_I2C0;
|
||||
#endif /* LPI2C0 */
|
||||
|
||||
#if defined(LPI2C1)
|
||||
extern ARM_DRIVER_I2C Driver_I2C1;
|
||||
#endif /* LPI2C1 */
|
||||
|
||||
#if defined(LPI2C2)
|
||||
extern ARM_DRIVER_I2C Driver_I2C2;
|
||||
#endif /* LPI2C2 */
|
||||
|
||||
#if defined(LPI2C3)
|
||||
extern ARM_DRIVER_I2C Driver_I2C3;
|
||||
#endif /* LPI2C3 */
|
||||
|
||||
#if defined(LPI2C4)
|
||||
extern ARM_DRIVER_I2C Driver_I2C4;
|
||||
#endif /* LPI2C4 */
|
||||
|
||||
#if defined(LPI2C5)
|
||||
extern ARM_DRIVER_I2C Driver_I2C5;
|
||||
#endif /* LPI2C5*/
|
||||
|
||||
#if defined(LPI2C6)
|
||||
extern ARM_DRIVER_I2C Driver_I2C6;
|
||||
#endif /* LPI2C6 */
|
||||
|
||||
/* I2C Driver state flags */
|
||||
#define I2C_FLAG_UNINIT (0)
|
||||
#define I2C_FLAG_INIT (1 << 0)
|
||||
#define I2C_FLAG_POWER (1 << 1)
|
||||
|
||||
#endif /* _FSL_LPI2C_CMSIS_H_ */
|
||||
2177
platform/vendor_bsp/nxp/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.c
Normal file
2177
platform/vendor_bsp/nxp/MIMXRT1052/cmsis_drivers/fsl_lpspi_cmsis.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_LPSPI_CMSISI_H_
|
||||
#define _FSL_LPSPI_CMSISI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "Driver_SPI.h"
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_lpspi_edma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
|
||||
#if defined(LPSPI0)
|
||||
extern ARM_DRIVER_SPI Driver_SPI0;
|
||||
#endif /* LPSPI0 */
|
||||
|
||||
#if defined(LPSPI1)
|
||||
extern ARM_DRIVER_SPI Driver_SPI1;
|
||||
#endif /* LPSPI1 */
|
||||
|
||||
#if defined(LPSPI2)
|
||||
extern ARM_DRIVER_SPI Driver_SPI2;
|
||||
#endif /* LPSPI2 */
|
||||
|
||||
#if defined(LPSPI3)
|
||||
extern ARM_DRIVER_SPI Driver_SPI3;
|
||||
#endif /* LPSPI3 */
|
||||
|
||||
#if defined(LPSPI4)
|
||||
extern ARM_DRIVER_SPI Driver_SPI4;
|
||||
#endif /* LPSPI4 */
|
||||
|
||||
#if defined(LPSPI5)
|
||||
extern ARM_DRIVER_SPI Driver_SPI5;
|
||||
#endif /* LPSPI5 */
|
||||
|
||||
/* SPI Driver state flags */
|
||||
#define SPI_FLAG_UNINIT (0)
|
||||
#define SPI_FLAG_INIT (1 << 0)
|
||||
#define SPI_FLAG_POWER (1 << 1)
|
||||
#define SPI_FLAG_CONFIGURED (1 << 2)
|
||||
|
||||
#endif
|
||||
3303
platform/vendor_bsp/nxp/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.c
Normal file
3303
platform/vendor_bsp/nxp/MIMXRT1052/cmsis_drivers/fsl_lpuart_cmsis.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
|
||||
* Copyright 2016-2017 NXP. Not a Contribution.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FSL_LPUART_CMSIS_H_
|
||||
#define _FSL_LPUART_CMSIS_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "Driver_USART.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "fsl_lpuart.h"
|
||||
#if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT)
|
||||
#include "fsl_dmamux.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
|
||||
#include "fsl_lpuart_dma.h"
|
||||
#endif
|
||||
#if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && FSL_FEATURE_SOC_EDMA_COUNT)
|
||||
#include "fsl_lpuart_edma.h"
|
||||
#endif
|
||||
|
||||
#if defined(LPUART0)
|
||||
extern ARM_DRIVER_USART Driver_USART0;
|
||||
#endif /* LPUART0 */
|
||||
|
||||
#if defined(LPUART1)
|
||||
extern ARM_DRIVER_USART Driver_USART1;
|
||||
#endif /* LPUART1 */
|
||||
|
||||
#if defined(LPUART2)
|
||||
extern ARM_DRIVER_USART Driver_USART2;
|
||||
#endif /* LPUART2 */
|
||||
|
||||
#if defined(LPUART3)
|
||||
extern ARM_DRIVER_USART Driver_USART3;
|
||||
#endif /* LPUART3 */
|
||||
|
||||
#if defined(LPUART4)
|
||||
extern ARM_DRIVER_USART Driver_USART4;
|
||||
#endif /* LPUART4 */
|
||||
|
||||
#if defined(LPUART5)
|
||||
extern ARM_DRIVER_USART Driver_USART5;
|
||||
#endif /* LPUART5 */
|
||||
|
||||
#if defined(LPUART6)
|
||||
extern ARM_DRIVER_USART Driver_USART6;
|
||||
#endif /* LPUART6 */
|
||||
|
||||
#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 3)
|
||||
|
||||
extern ARM_DRIVER_USART Driver_USART3;
|
||||
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 4)
|
||||
|
||||
extern ARM_DRIVER_USART Driver_USART4;
|
||||
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_SOC_LPUART_COUNT == 1) && (FSL_FEATURE_SOC_UART_COUNT == 5)
|
||||
extern ARM_DRIVER_USART Driver_USART5;
|
||||
|
||||
#endif
|
||||
|
||||
/* USART Driver state flags */
|
||||
#define USART_FLAG_UNINIT (0)
|
||||
#define USART_FLAG_INIT (1 << 0)
|
||||
#define USART_FLAG_POWER (1 << 1)
|
||||
#define USART_FLAG_CONFIGURED (1 << 2)
|
||||
|
||||
#endif /* _FSL_LPUART_CMSIS_H_ */
|
||||
300
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc.c
Normal file
300
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc.c
Normal file
@@ -0,0 +1,300 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_adc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address
|
||||
*/
|
||||
static uint32_t ADC_GetInstance(ADC_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to ADC bases for each instance. */
|
||||
static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
|
||||
|
||||
/*! @brief Pointers to ADC clocks for each instance. */
|
||||
static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t ADC_GetInstance(ADC_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
|
||||
{
|
||||
if (s_adcBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_adcBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void ADC_Init(ADC_Type *base, const adc_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
/* Enable the clock. */
|
||||
CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
|
||||
/* ADCx_CFG */
|
||||
tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */
|
||||
tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) |
|
||||
ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution);
|
||||
if (config->enableOverWrite)
|
||||
{
|
||||
tmp32 |= ADC_CFG_OVWREN_MASK;
|
||||
}
|
||||
if (config->enableLongSample)
|
||||
{
|
||||
tmp32 |= ADC_CFG_ADLSMP_MASK;
|
||||
}
|
||||
if (config->enableLowPower)
|
||||
{
|
||||
tmp32 |= ADC_CFG_ADLPC_MASK;
|
||||
}
|
||||
if (config->enableHighSpeed)
|
||||
{
|
||||
tmp32 |= ADC_CFG_ADHSC_MASK;
|
||||
}
|
||||
base->CFG = tmp32;
|
||||
|
||||
/* ADCx_GC */
|
||||
tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK);
|
||||
if (config->enableContinuousConversion)
|
||||
{
|
||||
tmp32 |= ADC_GC_ADCO_MASK;
|
||||
}
|
||||
if (config->enableAsynchronousClockOutput)
|
||||
{
|
||||
tmp32 |= ADC_GC_ADACKEN_MASK;
|
||||
}
|
||||
base->GC = tmp32;
|
||||
}
|
||||
|
||||
void ADC_Deinit(ADC_Type *base)
|
||||
{
|
||||
/* Disable the clock. */
|
||||
CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
|
||||
}
|
||||
|
||||
void ADC_GetDefaultConfig(adc_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
config->enableAsynchronousClockOutput = true;
|
||||
config->enableOverWrite = false;
|
||||
config->enableContinuousConversion = false;
|
||||
config->enableHighSpeed = false;
|
||||
config->enableLowPower = false;
|
||||
config->enableLongSample = false;
|
||||
config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
|
||||
config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
|
||||
config->clockSource = kADC_ClockSourceAD;
|
||||
config->clockDriver = kADC_ClockDriver1;
|
||||
config->resolution = kADC_Resolution12Bit;
|
||||
}
|
||||
|
||||
void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
assert(channelGroup < ADC_HC_COUNT);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = ADC_HC_ADCH(config->channelNumber);
|
||||
if (config->enableInterruptOnConversionCompleted)
|
||||
{
|
||||
tmp32 |= ADC_HC_AIEN_MASK;
|
||||
}
|
||||
base->HC[channelGroup] = tmp32;
|
||||
}
|
||||
|
||||
/*
|
||||
*To complete calibration, the user must follow the below procedure:
|
||||
* 1. Configure ADC_CFG with actual operating values for maximum accuracy.
|
||||
* 2. Configure the ADC_GC values along with CAL bit.
|
||||
* 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC.
|
||||
* 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status.
|
||||
*/
|
||||
status_t ADC_DoAutoCalibration(ADC_Type *base)
|
||||
{
|
||||
status_t status = kStatus_Success;
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
|
||||
bool bHWTrigger = false;
|
||||
|
||||
/* The calibration would be failed when in hardwar mode.
|
||||
* Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
|
||||
if (0U != (ADC_CFG_ADTRG_MASK & base->CFG))
|
||||
{
|
||||
bHWTrigger = true;
|
||||
ADC_EnableHardwareTrigger(base, false);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear the CALF and launch the calibration. */
|
||||
base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */
|
||||
base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */
|
||||
|
||||
/* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */
|
||||
while (0U != (base->GC & ADC_GC_CAL_MASK))
|
||||
{
|
||||
/* Check the CALF when the calibration is active. */
|
||||
if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag))
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */
|
||||
if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */
|
||||
{
|
||||
status = kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Clear conversion done flag. */
|
||||
ADC_GetChannelConversionValue(base, 0U);
|
||||
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
|
||||
/* Restore original trigger mode. */
|
||||
if (true == bHWTrigger)
|
||||
{
|
||||
ADC_EnableHardwareTrigger(base, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = ADC_OFS_OFS(config->offsetValue);
|
||||
if (config->enableSigned)
|
||||
{
|
||||
tmp32 |= ADC_OFS_SIGN_MASK;
|
||||
}
|
||||
base->OFS = tmp32;
|
||||
}
|
||||
|
||||
void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config)
|
||||
{
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK);
|
||||
if (NULL == config) /* Pass "NULL" to disable the feature. */
|
||||
{
|
||||
base->GC = tmp32;
|
||||
return;
|
||||
}
|
||||
/* Enable the feature. */
|
||||
tmp32 |= ADC_GC_ACFE_MASK;
|
||||
|
||||
/* Select the hardware compare working mode. */
|
||||
switch (config->hardwareCompareMode)
|
||||
{
|
||||
case kADC_HardwareCompareMode0:
|
||||
break;
|
||||
case kADC_HardwareCompareMode1:
|
||||
tmp32 |= ADC_GC_ACFGT_MASK;
|
||||
break;
|
||||
case kADC_HardwareCompareMode2:
|
||||
tmp32 |= ADC_GC_ACREN_MASK;
|
||||
break;
|
||||
case kADC_HardwareCompareMode3:
|
||||
tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
base->GC = tmp32;
|
||||
|
||||
/* Load the compare values. */
|
||||
tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2);
|
||||
base->CV = tmp32;
|
||||
}
|
||||
|
||||
void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode)
|
||||
{
|
||||
uint32_t tmp32;
|
||||
|
||||
if (mode == kADC_HardwareAverageDiasable)
|
||||
{
|
||||
base->GC &= ~ADC_GC_AVGE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK;
|
||||
tmp32 |= ADC_CFG_AVGS(mode);
|
||||
base->CFG = tmp32;
|
||||
base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */
|
||||
}
|
||||
}
|
||||
|
||||
void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
|
||||
{
|
||||
uint32_t tmp32 = 0;
|
||||
|
||||
if (0U != (mask & kADC_CalibrationFailedFlag))
|
||||
{
|
||||
tmp32 |= ADC_GS_CALF_MASK;
|
||||
}
|
||||
if (0U != (mask & kADC_ConversionActiveFlag))
|
||||
{
|
||||
tmp32 |= ADC_GS_ADACT_MASK;
|
||||
}
|
||||
base->GS = tmp32;
|
||||
}
|
||||
446
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc.h
Normal file
446
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc.h
Normal file
@@ -0,0 +1,446 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ADC_H_
|
||||
#define _FSL_ADC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup adc_12b1msps_sar
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief ADC driver version */
|
||||
#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
|
||||
/*!
|
||||
* @brief Converter's status flags.
|
||||
*/
|
||||
typedef enum _adc_status_flags
|
||||
{
|
||||
kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */
|
||||
kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */
|
||||
kADC_AsynchronousWakeupInterruptFlag =
|
||||
ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */
|
||||
} adc_status_flags_t;
|
||||
|
||||
/*!
|
||||
* @brief Reference voltage source.
|
||||
*/
|
||||
typedef enum _adc_reference_voltage_source
|
||||
{
|
||||
kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */
|
||||
} adc_reference_voltage_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Sample time duration.
|
||||
*/
|
||||
typedef enum _adc_sample_period_mode
|
||||
{
|
||||
/* This group of enumeration is for internal use which is related to register setting. */
|
||||
kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */
|
||||
kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */
|
||||
kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */
|
||||
kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */
|
||||
/* This group of enumeration is for a public user. */
|
||||
/* For long sample mode. */
|
||||
kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */
|
||||
kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */
|
||||
kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */
|
||||
kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */
|
||||
/* For short sample mode. */
|
||||
kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */
|
||||
kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */
|
||||
kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */
|
||||
kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */
|
||||
} adc_sample_period_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Clock source.
|
||||
*/
|
||||
typedef enum _adc_clock_source
|
||||
{
|
||||
kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */
|
||||
kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE)
|
||||
kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */
|
||||
#endif
|
||||
kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */
|
||||
} adc_clock_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Clock divider for the converter.
|
||||
*/
|
||||
typedef enum _adc_clock_drvier
|
||||
{
|
||||
kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */
|
||||
kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */
|
||||
kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */
|
||||
kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */
|
||||
} adc_clock_driver_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter's resolution.
|
||||
*/
|
||||
typedef enum _adc_resolution
|
||||
{
|
||||
kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */
|
||||
kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */
|
||||
kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */
|
||||
} adc_resolution_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter hardware compare mode.
|
||||
*/
|
||||
typedef enum _adc_hardware_compare_mode
|
||||
{
|
||||
kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */
|
||||
kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */
|
||||
kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or
|
||||
the result is Greater than value2.
|
||||
Value1 > Value2, compare true if the result is less than value1 And the
|
||||
result is greater than value2*/
|
||||
kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal
|
||||
to value1 And the result is less than or equal to value2.
|
||||
Value1 > Value2, compare true if the result is greater than or equal to
|
||||
value1 Or the result is less than or equal to value2. */
|
||||
} adc_hardware_compare_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter hardware average mode.
|
||||
*/
|
||||
typedef enum _adc_hardware_average_mode
|
||||
{
|
||||
kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */
|
||||
kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */
|
||||
kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */
|
||||
kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */
|
||||
kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */
|
||||
} adc_hardware_average_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter configuration.
|
||||
*/
|
||||
typedef struct _adc_config
|
||||
{
|
||||
bool enableOverWrite; /*!< Enable the overwriting. */
|
||||
bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */
|
||||
bool enableHighSpeed; /*!< Enable the high-speed mode. */
|
||||
bool enableLowPower; /*!< Enable the low power mode. */
|
||||
bool enableLongSample; /*!< Enable the long sample mode. */
|
||||
bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */
|
||||
adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
|
||||
adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */
|
||||
adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */
|
||||
adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */
|
||||
adc_resolution_t resolution; /*!< Select the ADC resolution mode. */
|
||||
} adc_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Converter Offset configuration.
|
||||
*/
|
||||
typedef struct _adc_offest_config
|
||||
{
|
||||
bool enableSigned; /*!< if false,The offset value is added with the raw result.
|
||||
if true,The offset value is subtracted from the raw converted value. */
|
||||
uint32_t offsetValue; /*!< User configurable offset value(0-4095). */
|
||||
} adc_offest_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC hardware compare configuration.
|
||||
*
|
||||
* In kADC_HardwareCompareMode0, compare true if the result is less than the value1.
|
||||
* In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1.
|
||||
* In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is
|
||||
* Greater than value2.
|
||||
* Value1 > Value2, compare true if the result is less than value1 And the result is
|
||||
* Greater than value2.
|
||||
* In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the
|
||||
* result is less than or equal to value2.
|
||||
* Value1 > Value2, compare true if the result is greater than or equal to value1 Or the
|
||||
* result is less than or equal to value2.
|
||||
*/
|
||||
typedef struct _adc_hardware_compare_config
|
||||
{
|
||||
adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode.
|
||||
See "adc_hardware_compare_mode_t". */
|
||||
uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */
|
||||
uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */
|
||||
} adc_hardware_compare_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC channel conversion configuration.
|
||||
*/
|
||||
typedef struct _adc_channel_config
|
||||
{
|
||||
uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31.
|
||||
See channel connection information for each chip in Reference
|
||||
Manual document. */
|
||||
bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
|
||||
} adc_channel_config_t;
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize the ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to "adc_config_t" structure.
|
||||
*/
|
||||
void ADC_Init(ADC_Type *base, const adc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*/
|
||||
void ADC_Deinit(ADC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available pre-defined settings for the converter's configuration.
|
||||
*
|
||||
* This function initializes the converter configuration structure with available settings. The default values are:
|
||||
* @code
|
||||
* config->enableAsynchronousClockOutput = true;
|
||||
* config->enableOverWrite = false;
|
||||
* config->enableContinuousConversion = false;
|
||||
* config->enableHighSpeed = false;
|
||||
* config->enableLowPower = false;
|
||||
* config->enableLongSample = false;
|
||||
* config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0;
|
||||
* config->samplePeriodMode = kADC_SamplePeriod2or12Clocks;
|
||||
* config->clockSource = kADC_ClockSourceAD;
|
||||
* config->clockDriver = kADC_ClockDriver1;
|
||||
* config->resolution = kADC_Resolution12Bit;
|
||||
* @endcode
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void ADC_GetDefaultConfig(adc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures the conversion channel.
|
||||
*
|
||||
* This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
|
||||
* configures the channel while the external trigger source helps to trigger the conversion.
|
||||
*
|
||||
* Note that the "Channel Group" has a detailed description.
|
||||
* To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
|
||||
* group of status and control registers, one for each conversion. The channel group parameter indicates which group of
|
||||
* registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B
|
||||
* registers. The
|
||||
* channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of
|
||||
* the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and
|
||||
* hardware
|
||||
* trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for
|
||||
* use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual
|
||||
* about the
|
||||
* number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used
|
||||
* for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
|
||||
* Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
|
||||
* vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
|
||||
* conversion aborts the current conversion.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelGroup Channel group index.
|
||||
* @param config Pointer to the "adc_channel_config_t" structure for the conversion channel.
|
||||
*/
|
||||
void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gets the conversion value.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelGroup Channel group index.
|
||||
*
|
||||
* @return Conversion value.
|
||||
*/
|
||||
static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)
|
||||
{
|
||||
assert(channelGroup < ADC_R_COUNT);
|
||||
|
||||
return base->R[channelGroup];
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the status flags of channel.
|
||||
*
|
||||
* A conversion is completed when the result of the conversion is transferred into the data
|
||||
* result registers. (provided the compare function & hardware averaging is disabled), this is
|
||||
* indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only,
|
||||
* if the last of the selected number of conversions is complete. If the compare function is
|
||||
* enabled, COCOn sets and conversion result data is transferred only if the compare
|
||||
* condition is true. If both hardware averaging and compare functions are enabled, then
|
||||
* COCOn sets only if the last of the selected number of conversions is complete and the
|
||||
* compare condition is true.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelGroup Channel group index.
|
||||
*
|
||||
* @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1.
|
||||
*/
|
||||
static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
|
||||
{
|
||||
assert(channelGroup < ADC_HC_COUNT);
|
||||
|
||||
/* If flag is set,return 1,otherwise, return 0. */
|
||||
return (((base->HS) & (1U << channelGroup)) >> channelGroup);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Automates the hardware calibration.
|
||||
*
|
||||
* This auto calibration helps to adjust the plus/minus side gain automatically.
|
||||
* Execute the calibration before using the converter. Note that the software trigger should be used
|
||||
* during calibration.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*
|
||||
* @return Execution status.
|
||||
* @retval kStatus_Success Calibration is done successfully.
|
||||
* @retval kStatus_Fail Calibration has failed.
|
||||
*/
|
||||
status_t ADC_DoAutoCalibration(ADC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Set user defined offset.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to "adc_offest_config_t" structure.
|
||||
*/
|
||||
void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Enables generating the DMA trigger when the conversion is complete.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
|
||||
*/
|
||||
static inline void ADC_EnableDMA(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->GC |= ADC_GC_DMAEN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->GC &= ~ADC_GC_DMAEN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables the hardware trigger mode.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode.
|
||||
*/
|
||||
#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
|
||||
static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CFG |= ADC_CFG_ADTRG_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CFG &= ~ADC_CFG_ADTRG_MASK;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Configures the hardware compare mode.
|
||||
*
|
||||
* The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the
|
||||
* result
|
||||
* in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate
|
||||
* reference
|
||||
* manual for more information.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param Pointer to "adc_hardware_compare_config_t" structure.
|
||||
*
|
||||
*/
|
||||
void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures the hardware average mode.
|
||||
*
|
||||
* The hardware average mode provides a way to process the conversion result automatically by using hardware. The
|
||||
* multiple
|
||||
* conversion results are accumulated and averaged internally making them easier to read.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t".
|
||||
*/
|
||||
void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode);
|
||||
|
||||
/*!
|
||||
* @brief Gets the converter's status flags.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*
|
||||
* @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t".
|
||||
*/
|
||||
static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
|
||||
{
|
||||
return base->GS;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the converter's status falgs.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mask Mask value for the cleared flags. See "adc_status_flags_t".
|
||||
*/
|
||||
void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_ADC_H_ */
|
||||
365
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc_etc.c
Normal file
365
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc_etc.c
Normal file
@@ -0,0 +1,365 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_adc_etc.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.adc_etc"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
#if defined(ADC_ETC_CLOCKS)
|
||||
/*!
|
||||
* @brief Get instance number for ADC_ETC module.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address
|
||||
*/
|
||||
static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to ADC_ETC bases for each instance. */
|
||||
static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS;
|
||||
|
||||
/*! @brief Pointers to ADC_ETC clocks for each instance. */
|
||||
static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base)
|
||||
{
|
||||
uint32_t instance = 0U;
|
||||
uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0]));
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < adcetcArrayCount; instance++)
|
||||
{
|
||||
if (s_adcetcBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return instance;
|
||||
}
|
||||
#endif /* ADC_ETC_CLOCKS */
|
||||
|
||||
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
#if defined(ADC_ETC_CLOCKS)
|
||||
/* Open clock gate. */
|
||||
CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
|
||||
#endif /* ADC_ETC_CLOCKS */
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Disable software reset. */
|
||||
ADC_ETC_DoSoftwareReset(base, false);
|
||||
|
||||
/* Set ADC_ETC_CTRL register. */
|
||||
tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
|
||||
ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
|
||||
ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
| ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
;
|
||||
if (config->enableTSCBypass)
|
||||
{
|
||||
tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
|
||||
}
|
||||
if (config->enableTSC0Trigger)
|
||||
{
|
||||
tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK;
|
||||
}
|
||||
if (config->enableTSC1Trigger)
|
||||
{
|
||||
tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK;
|
||||
}
|
||||
base->CTRL = tmp32;
|
||||
}
|
||||
|
||||
void ADC_ETC_Deinit(ADC_ETC_Type *base)
|
||||
{
|
||||
/* Do software reset to clear all logical. */
|
||||
ADC_ETC_DoSoftwareReset(base, true);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
#if defined(ADC_ETC_CLOCKS)
|
||||
/* Close clock gate. */
|
||||
CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]);
|
||||
#endif /* ADC_ETC_CLOCKS */
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
|
||||
{
|
||||
config->enableTSCBypass = true;
|
||||
config->enableTSC0Trigger = false;
|
||||
config->enableTSC1Trigger = false;
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
config->TSC0triggerPriority = 0U;
|
||||
config->TSC1triggerPriority = 0U;
|
||||
config->clockPreDivider = 0U;
|
||||
config->XBARtriggerMask = 0U;
|
||||
}
|
||||
|
||||
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||||
assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
/* Set ADC_ETC_TRGn_CTRL register. */
|
||||
tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) |
|
||||
ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority);
|
||||
if (config->enableSyncMode)
|
||||
{
|
||||
tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK;
|
||||
}
|
||||
if (config->enableSWTriggerMode)
|
||||
{
|
||||
tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK;
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CTRL = tmp32;
|
||||
|
||||
/* Set ADC_ETC_TRGn_COUNTER register. */
|
||||
tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) |
|
||||
ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay);
|
||||
base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32;
|
||||
}
|
||||
|
||||
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
|
||||
uint32_t triggerGroup,
|
||||
uint32_t chainGroup,
|
||||
const adc_etc_trigger_chain_config_t *config)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||||
|
||||
uint32_t tmp;
|
||||
uint32_t tmp32;
|
||||
uint8_t mRemainder = chainGroup % 2U;
|
||||
|
||||
/* Set ADC_ETC_TRIGn_CHAINm register. */
|
||||
tmp = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable);
|
||||
if (config->enableB2BMode)
|
||||
{
|
||||
tmp |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK;
|
||||
}
|
||||
switch (chainGroup / 2U)
|
||||
{
|
||||
case 0U: /* Configurate trigger chain0 and chain 1. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0;
|
||||
if (mRemainder == 0U) /* Chain 0. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 1. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmp32;
|
||||
break;
|
||||
case 1U: /* Configurate trigger chain2 and chain 3. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2;
|
||||
if (mRemainder == 0U) /* Chain 2. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 3. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmp32;
|
||||
break;
|
||||
case 2U: /* Configurate trigger chain4 and chain 5. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4;
|
||||
if (mRemainder == 0U) /* Chain 4. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 5. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmp32;
|
||||
break;
|
||||
case 3U: /* Configurate trigger chain6 and chain 7. */
|
||||
tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6;
|
||||
if (mRemainder == 0U) /* Chain 6. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK);
|
||||
tmp32 |= tmp;
|
||||
}
|
||||
else /* Chain 7. */
|
||||
{
|
||||
tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK |
|
||||
ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK);
|
||||
tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT);
|
||||
}
|
||||
base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmp32;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex)
|
||||
{
|
||||
uint32_t tmp32 = 0U;
|
||||
|
||||
if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex)) != 0U)
|
||||
{
|
||||
tmp32 |= kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in fsl_adc_etc.h
|
||||
file. */
|
||||
}
|
||||
return tmp32;
|
||||
}
|
||||
|
||||
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask)
|
||||
{
|
||||
if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */
|
||||
{
|
||||
base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex);
|
||||
}
|
||||
if (0U != (mask & kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */
|
||||
{
|
||||
base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex);
|
||||
}
|
||||
if (0U != (mask & kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */
|
||||
{
|
||||
base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex);
|
||||
}
|
||||
if (0U != (mask & kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */
|
||||
{
|
||||
base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT);
|
||||
|
||||
uint32_t mADCResult;
|
||||
uint8_t mRemainder = chainGroup % 2U;
|
||||
|
||||
switch (chainGroup / 2U)
|
||||
{
|
||||
case 0U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT;
|
||||
}
|
||||
break;
|
||||
case 1U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT;
|
||||
}
|
||||
break;
|
||||
case 2U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT;
|
||||
}
|
||||
break;
|
||||
case 3U:
|
||||
if (0U == mRemainder)
|
||||
{
|
||||
mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6);
|
||||
}
|
||||
else
|
||||
{
|
||||
mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return 0U;
|
||||
}
|
||||
return mADCResult;
|
||||
}
|
||||
342
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc_etc.h
Normal file
342
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_adc_etc.h
Normal file
@@ -0,0 +1,342 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_ADC_ETC_H_
|
||||
#define _FSL_ADC_ETC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup adc_etc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief ADC_ETC driver version */
|
||||
#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*! @brief The mask of status flags cleared by writing 1. */
|
||||
#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC customized status flags mask.
|
||||
*/
|
||||
enum _adc_etc_status_flag_mask
|
||||
{
|
||||
kADC_ETC_Done0StatusFlagMask = 1U,
|
||||
kADC_ETC_Done1StatusFlagMask = 2U,
|
||||
kADC_ETC_Done2StatusFlagMask = 4U,
|
||||
kADC_ETC_ErrorStatusFlagMask = 8U,
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief External triggers sources.
|
||||
*/
|
||||
typedef enum _adc_etc_external_trigger_source
|
||||
{
|
||||
/* External XBAR sources. Support HW or SW mode. */
|
||||
kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */
|
||||
kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */
|
||||
kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */
|
||||
kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */
|
||||
kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */
|
||||
kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */
|
||||
kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */
|
||||
kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */
|
||||
/* External TSC sources. Only support HW mode. */
|
||||
kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */
|
||||
kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */
|
||||
} adc_etc_external_trigger_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Interrupt enable/disable mask.
|
||||
*/
|
||||
typedef enum _adc_etc_interrupt_enable
|
||||
{
|
||||
kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
|
||||
kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
|
||||
kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
|
||||
kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
|
||||
} adc_etc_interrupt_enable_t;
|
||||
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
/*!
|
||||
* @brief DMA mode selection.
|
||||
*/
|
||||
typedef enum _adc_etc_dma_mode_selection
|
||||
{
|
||||
kADC_ETC_TrigDMAWithLatchedSignal = 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
|
||||
kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
|
||||
} adc_etc_dma_mode_selection_t;
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC configuration.
|
||||
*/
|
||||
typedef struct _adc_etc_config
|
||||
{
|
||||
bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
|
||||
Otherwise TSC would trigger ADC through ADC_ETC. */
|
||||
bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
|
||||
bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
|
||||
#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
|
||||
adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
|
||||
#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
|
||||
uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
|
||||
uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
|
||||
uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
|
||||
Clock would be divided by (clockPreDivider+1). */
|
||||
uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
|
||||
trigger7:0x80
|
||||
For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
|
||||
enabled. */
|
||||
} adc_etc_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC trigger chain configuration.
|
||||
*/
|
||||
typedef struct _adc_etc_trigger_chain_config
|
||||
{
|
||||
bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
|
||||
wait until interval delay is reached. */
|
||||
uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */
|
||||
uint32_t ADCChannelSelect; /* Select ADC sample channel. */
|
||||
adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */
|
||||
} adc_etc_trigger_chain_config_t;
|
||||
|
||||
/*!
|
||||
* @brief ADC_ETC trigger configuration.
|
||||
*/
|
||||
typedef struct _adc_etc_trigger_config
|
||||
{
|
||||
bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
|
||||
In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */
|
||||
bool enableSWTriggerMode; /* Enable the sofware trigger mode. */
|
||||
uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */
|
||||
uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */
|
||||
uint32_t sampleIntervalDelay; /* Set sampling interval delay. */
|
||||
uint32_t initialDelay; /* Set trigger initial delay. */
|
||||
} adc_etc_trigger_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize the ADC_ETC module.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param config Pointer to "adc_etc_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-Initialize the ADC_ETC module.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
*/
|
||||
void ADC_ETC_Deinit(ADC_ETC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
|
||||
* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
|
||||
* @code
|
||||
* config->enableTSCBypass = true;
|
||||
* config->enableTSC0Trigger = false;
|
||||
* config->enableTSC1Trigger = false;
|
||||
* config->TSC0triggerPriority = 0U;
|
||||
* config->TSC1triggerPriority = 0U;
|
||||
* config->clockPreDivider = 0U;
|
||||
* config->XBARtriggerMask = 0U;
|
||||
* @endCode
|
||||
*
|
||||
* @param config Pointer to "adc_etc_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Set the external XBAR trigger configuration.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index.
|
||||
* @param config Pointer to "adc_etc_trigger_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Set the external XBAR trigger chain configuration.
|
||||
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
|
||||
* configurated.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
* @param chainGroup Trigger chain group index. Available number is 0~7.
|
||||
* @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
|
||||
*/
|
||||
void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
|
||||
uint32_t triggerGroup,
|
||||
uint32_t chainGroup,
|
||||
const adc_etc_trigger_chain_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gets the interrupt status flags of external XBAR and TSC triggers.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param sourceIndex trigger source index.
|
||||
*
|
||||
* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
|
||||
*/
|
||||
uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
|
||||
|
||||
/*!
|
||||
* @brief Clears the ADC_ETC's interrupt status falgs.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param sourceIndex trigger source index.
|
||||
* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
|
||||
*/
|
||||
void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
|
||||
adc_etc_external_trigger_source_t sourceIndex,
|
||||
uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Enable the DMA corresponding to each trigger source.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
*/
|
||||
static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||||
{
|
||||
/* Avoid clearing status flags at the same time. */
|
||||
base->DMA_CTRL =
|
||||
(base->DMA_CTRL | (ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the DMA corresponding to each trigger sources.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
*/
|
||||
static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||||
{
|
||||
/* Avoid clearing status flags at the same time. */
|
||||
base->DMA_CTRL =
|
||||
(base->DMA_CTRL & ~(ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get the DMA request status falgs. Only external XBAR sources support DMA request.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
|
||||
* trigger7:0x80.
|
||||
*/
|
||||
static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)
|
||||
{
|
||||
return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
|
||||
* trigger7:0x80.
|
||||
*/
|
||||
static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief When enable ,all logical will be reset.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param enable Enable/Disable the software reset.
|
||||
*/
|
||||
static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Do software trigger corresponding to each XBAR trigger sources.
|
||||
* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
|
||||
* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
|
||||
* can only work in hardware trigger mode.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
*/
|
||||
static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||||
{
|
||||
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||||
|
||||
base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get ADC conversion result from external XBAR sources.
|
||||
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
|
||||
* return Trigger0 source's chain1 conversion result.
|
||||
*
|
||||
* @param base ADC_ETC peripheral base address.
|
||||
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||||
* @param chainGroup Trigger chain group index. Available number is 0~7.
|
||||
* @return ADC conversion result value.
|
||||
*/
|
||||
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_ADC_ETC_H_ */
|
||||
60
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aipstz.c
Normal file
60
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aipstz.c
Normal file
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_aipstz.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig)
|
||||
{
|
||||
uint32_t mask = ((uint32_t)master >> 8) - 1;
|
||||
uint32_t shift = (uint32_t)master & 0xFF;
|
||||
base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift);
|
||||
}
|
||||
|
||||
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl)
|
||||
{
|
||||
volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16));
|
||||
uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1;
|
||||
uint32_t shift = (uint32_t)peripheral & 0xFF;
|
||||
|
||||
*reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift);
|
||||
}
|
||||
|
||||
|
||||
155
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aipstz.h
Normal file
155
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aipstz.h
Normal file
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_AIPSTZ_H_
|
||||
#define _FSL_AIPSTZ_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup aipstz
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of AIPSTZ privilege configuration.*/
|
||||
typedef enum _aipstz_master_privilege_level {
|
||||
kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
|
||||
kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
|
||||
kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
|
||||
kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
|
||||
} aipstz_master_privilege_level_t;
|
||||
|
||||
/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
|
||||
typedef enum _aipstz_master {
|
||||
kAIPSTZ_Master0 = (0x400U | 28U),
|
||||
kAIPSTZ_Master1 = (0x400U | 24U),
|
||||
kAIPSTZ_Master2 = (0x400U | 20U),
|
||||
kAIPSTZ_Master3 = (0x400U | 16U),
|
||||
kAIPSTZ_Master5 = (0x400U | 8U)
|
||||
} aipstz_master_t;
|
||||
|
||||
/*! @brief List of AIPSTZ peripheral access control configuration.*/
|
||||
typedef enum _aipstz_peripheral_access_control {
|
||||
kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
|
||||
kAIPSTZ_PeripheralWriteProtected = (1U < 1),
|
||||
kAIPSTZ_PeripheralRequireSupervisor = (1U < 2),
|
||||
kAIPSTZ_PeripheralAllowBufferedWrite = (1U < 2)
|
||||
} aipstz_peripheral_access_control_t;
|
||||
|
||||
/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/
|
||||
typedef enum _aipstz_peripheral {
|
||||
kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
|
||||
kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
|
||||
kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
|
||||
kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
|
||||
kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
|
||||
kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
|
||||
kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
|
||||
kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
|
||||
kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
|
||||
} aipstz_peripheral_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configure the privilege level for master.
|
||||
*
|
||||
* @param base AIPSTZ peripheral base pointer
|
||||
* @param master Masters for AIPSTZ.
|
||||
* @param privilegeConfig Configuration is ORed from @aipstz_master_privilege_level_t.
|
||||
*/
|
||||
void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig);
|
||||
|
||||
/*!
|
||||
* @brief Configure the access for peripheral.
|
||||
*
|
||||
* @param base AIPSTZ peripheral base pointer
|
||||
* @param master Peripheral for AIPSTZ.
|
||||
* @param accessControl Configuration is ORed from @aipstz_peripheral_access_control_t.
|
||||
*/
|
||||
void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_AIPSTZ_H_ */
|
||||
151
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aoi.c
Normal file
151
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aoi.c
Normal file
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "fsl_aoi.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to aoi bases for each instance. */
|
||||
static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to aoi clocks for each instance. */
|
||||
static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for AOI module.
|
||||
*
|
||||
* @param base AOI peripheral base address
|
||||
*
|
||||
* @return The AOI instance
|
||||
*/
|
||||
static uint32_t AOI_GetInstance(AOI_Type *base);
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t AOI_GetInstance(AOI_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++)
|
||||
{
|
||||
if (s_aoiBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_aoiBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void AOI_Init(AOI_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the clock gate from clock manager. */
|
||||
CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void AOI_Deinit(AOI_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the clock gate from clock manager */
|
||||
CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config)
|
||||
{
|
||||
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
|
||||
assert(config != NULL);
|
||||
|
||||
uint16_t value = 0;
|
||||
/* Read BFCRT01 register at event index. */
|
||||
value = base->BFCRT[event].BFCRT01;
|
||||
|
||||
config->PT0AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT);
|
||||
config->PT0BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT);
|
||||
config->PT0CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT);
|
||||
config->PT0DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT);
|
||||
|
||||
config->PT1AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT);
|
||||
config->PT1BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT);
|
||||
config->PT1CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT);
|
||||
config->PT1DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT);
|
||||
|
||||
/* Read BFCRT23 register at event index. */
|
||||
value = 0;
|
||||
value = base->BFCRT[event].BFCRT23;
|
||||
|
||||
config->PT2AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT);
|
||||
config->PT2BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT);
|
||||
config->PT2CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT);
|
||||
config->PT2DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT);
|
||||
|
||||
config->PT3AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT);
|
||||
config->PT3BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT);
|
||||
config->PT3CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT);
|
||||
config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT);
|
||||
}
|
||||
|
||||
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig)
|
||||
{
|
||||
assert(eventConfig != NULL);
|
||||
assert(event < FSL_FEATURE_AOI_EVENT_COUNT);
|
||||
|
||||
uint16_t value = 0;
|
||||
/* Calculate value to configure product term 0, 1 */
|
||||
value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) |
|
||||
AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) |
|
||||
AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) |
|
||||
AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC);
|
||||
/* Write value to register */
|
||||
base->BFCRT[event].BFCRT01 = value;
|
||||
|
||||
/* Reset and calculate value to configure product term 2, 3 */
|
||||
value = 0;
|
||||
value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) |
|
||||
AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) |
|
||||
AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) |
|
||||
AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC);
|
||||
/* Write value to register */
|
||||
base->BFCRT[event].BFCRT23 = value;
|
||||
}
|
||||
213
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aoi.h
Normal file
213
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_aoi.h
Normal file
@@ -0,0 +1,213 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_AOI_H_
|
||||
#define _FSL_AOI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup aoi
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#ifndef AOI
|
||||
#define AOI AOI0 /*!< AOI peripheral address */
|
||||
#endif
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief AOI input configurations.
|
||||
*
|
||||
* The selection item represents the Boolean evaluations.
|
||||
*/
|
||||
typedef enum _aoi_input_config
|
||||
{
|
||||
kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */
|
||||
kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */
|
||||
kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */
|
||||
kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */
|
||||
} aoi_input_config_t;
|
||||
|
||||
/*!
|
||||
* @brief AOI event indexes, where an event is the collection of the four product
|
||||
* terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D).
|
||||
*/
|
||||
typedef enum _aoi_event
|
||||
{
|
||||
kAOI_Event0 = 0x0U, /*!< Event 0 index */
|
||||
kAOI_Event1 = 0x1U, /*!< Event 1 index */
|
||||
kAOI_Event2 = 0x2U, /*!< Event 2 index */
|
||||
kAOI_Event3 = 0x3U /*!< Event 3 index */
|
||||
} aoi_event_t;
|
||||
|
||||
/*!
|
||||
* @brief AOI event configuration structure
|
||||
*
|
||||
* Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make
|
||||
* whole event configuration.
|
||||
*/
|
||||
typedef struct _aoi_event_config
|
||||
{
|
||||
aoi_input_config_t PT0AC; /*!< Product term 0 input A */
|
||||
aoi_input_config_t PT0BC; /*!< Product term 0 input B */
|
||||
aoi_input_config_t PT0CC; /*!< Product term 0 input C */
|
||||
aoi_input_config_t PT0DC; /*!< Product term 0 input D */
|
||||
aoi_input_config_t PT1AC; /*!< Product term 1 input A */
|
||||
aoi_input_config_t PT1BC; /*!< Product term 1 input B */
|
||||
aoi_input_config_t PT1CC; /*!< Product term 1 input C */
|
||||
aoi_input_config_t PT1DC; /*!< Product term 1 input D */
|
||||
aoi_input_config_t PT2AC; /*!< Product term 2 input A */
|
||||
aoi_input_config_t PT2BC; /*!< Product term 2 input B */
|
||||
aoi_input_config_t PT2CC; /*!< Product term 2 input C */
|
||||
aoi_input_config_t PT2DC; /*!< Product term 2 input D */
|
||||
aoi_input_config_t PT3AC; /*!< Product term 3 input A */
|
||||
aoi_input_config_t PT3BC; /*!< Product term 3 input B */
|
||||
aoi_input_config_t PT3CC; /*!< Product term 3 input C */
|
||||
aoi_input_config_t PT3DC; /*!< Product term 3 input D */
|
||||
} aoi_event_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @name AOI Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes an AOI instance for operation.
|
||||
*
|
||||
* This function un-gates the AOI clock.
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Init(AOI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes an AOI instance for operation.
|
||||
*
|
||||
* This function shutdowns AOI module.
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
*/
|
||||
void AOI_Deinit(AOI_Type *base);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @name AOI Get Set Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the Boolean evaluation associated.
|
||||
*
|
||||
* This function returns the Boolean evaluation associated.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct);
|
||||
@endcode
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
* @param event Index of the event which will be set of type aoi_event_t.
|
||||
* @param config Selected input configuration .
|
||||
*/
|
||||
void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures an AOI event.
|
||||
*
|
||||
* This function configures an AOI event according
|
||||
* to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D)
|
||||
* of all product terms (0, 1, 2, and 3) of a desired event.
|
||||
*
|
||||
* Example:
|
||||
@code
|
||||
aoi_event_config_t demoEventLogicStruct;
|
||||
|
||||
demoEventLogicStruct.PT0AC = kAOI_InvInputSignal;
|
||||
demoEventLogicStruct.PT0BC = kAOI_InputSignal;
|
||||
demoEventLogicStruct.PT0CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT0DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT1AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT1BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT1DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT2AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT2BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT2DC = kAOI_LogicOne;
|
||||
|
||||
demoEventLogicStruct.PT3AC = kAOI_LogicZero;
|
||||
demoEventLogicStruct.PT3BC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3CC = kAOI_LogicOne;
|
||||
demoEventLogicStruct.PT3DC = kAOI_LogicOne;
|
||||
|
||||
AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct);
|
||||
@endcode
|
||||
*
|
||||
* @param base AOI peripheral address.
|
||||
* @param event Event which will be configured of type aoi_event_t.
|
||||
* @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for
|
||||
* filling out the members of this structure and passing the pointer to this function.
|
||||
*/
|
||||
void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*!* @} */
|
||||
|
||||
#endif /* _FSL_AOI_H_*/
|
||||
238
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_bee.c
Normal file
238
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_bee.c
Normal file
@@ -0,0 +1,238 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_bee.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static void aligned_memcpy(void *dst, const void *src, size_t size)
|
||||
{
|
||||
register uint32_t *to32 = (uint32_t *)(uintptr_t)dst;
|
||||
register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src;
|
||||
|
||||
while (size >= sizeof(uint32_t))
|
||||
{
|
||||
*to32 = *from32;
|
||||
size -= sizeof(uint32_t);
|
||||
to32++;
|
||||
from32++;
|
||||
}
|
||||
}
|
||||
|
||||
void BEE_Init(BEE_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_EnableClock(kCLOCK_Bee);
|
||||
#endif
|
||||
|
||||
base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK;
|
||||
}
|
||||
|
||||
void BEE_Deinit(BEE_Type *base)
|
||||
{
|
||||
base->CTRL &=
|
||||
~(BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK | BEE_CTRL_KEY_VALID_MASK);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_DisableClock(kCLOCK_Bee);
|
||||
#endif
|
||||
}
|
||||
|
||||
void BEE_GetDefaultConfig(bee_region_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
config->mode = kBEE_AesEcbMode;
|
||||
config->regionBot = 0U;
|
||||
config->regionTop = 0U;
|
||||
config->addrOffset = 0xF0000000U;
|
||||
config->regionEn = kBEE_RegionDisabled;
|
||||
}
|
||||
|
||||
status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config)
|
||||
{
|
||||
IOMUXC_GPR_Type *iomuxc = IOMUXC_GPR;
|
||||
bool reenable = false;
|
||||
|
||||
/* Wait until BEE is in idle state */
|
||||
while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
|
||||
{
|
||||
}
|
||||
|
||||
/* Disable BEE before region configuration in case it is enabled. */
|
||||
if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1)
|
||||
{
|
||||
BEE_Disable(base);
|
||||
reenable = true;
|
||||
}
|
||||
|
||||
if (region == kBEE_Region0)
|
||||
{
|
||||
/* Region 0 config */
|
||||
iomuxc->GPR18 = config->regionBot;
|
||||
iomuxc->GPR19 = config->regionTop;
|
||||
|
||||
base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R0(config->mode);
|
||||
base->ADDR_OFFSET0 = BEE_ADDR_OFFSET0_ADDR_OFFSET0(config->addrOffset);
|
||||
}
|
||||
|
||||
else if (region == kBEE_Region1)
|
||||
{
|
||||
/* Region 1 config */
|
||||
iomuxc->GPR20 = config->regionBot;
|
||||
iomuxc->GPR21 = config->regionTop;
|
||||
|
||||
base->CTRL |= BEE_CTRL_CTRL_AES_MODE_R1(config->mode);
|
||||
base->ADDR_OFFSET1 = BEE_ADDR_OFFSET1_ADDR_OFFSET0(config->addrOffset);
|
||||
base->REGION1_BOT = BEE_REGION1_BOT_REGION1_BOT(config->regionBot);
|
||||
base->REGION1_TOP = BEE_REGION1_TOP_REGION1_TOP(config->regionTop);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Enable/disable region if desired */
|
||||
if (config->regionEn == kBEE_RegionEnabled)
|
||||
{
|
||||
iomuxc->GPR11 |= IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region);
|
||||
}
|
||||
else
|
||||
{
|
||||
iomuxc->GPR11 &= ~IOMUXC_GPR_GPR11_BEE_DE_RX_EN(1 << region);
|
||||
}
|
||||
|
||||
/* Reenable BEE if it was enabled before. */
|
||||
if (reenable)
|
||||
{
|
||||
BEE_Enable(base);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t BEE_SetRegionKey(
|
||||
BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize)
|
||||
{
|
||||
bool reenable = false;
|
||||
|
||||
/* Key must be 32-bit aligned */
|
||||
if (((uintptr_t)key & 0x3u) || (keySize != 16))
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Wait until BEE is in idle state */
|
||||
while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag))
|
||||
{
|
||||
}
|
||||
|
||||
/* Disable BEE before region configuration in case it is enabled. */
|
||||
if ((base->CTRL >> BEE_CTRL_BEE_ENABLE_SHIFT) & 1)
|
||||
{
|
||||
BEE_Disable(base);
|
||||
reenable = true;
|
||||
}
|
||||
|
||||
if (region == kBEE_Region0)
|
||||
{
|
||||
base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK;
|
||||
|
||||
if (nonce)
|
||||
{
|
||||
if (nonceSize != 16)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize);
|
||||
}
|
||||
}
|
||||
|
||||
else if (region == kBEE_Region1)
|
||||
{
|
||||
base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK;
|
||||
|
||||
if (nonce)
|
||||
{
|
||||
if (nonceSize != 16)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize);
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Try to load key. If BEE key selection fuse is programmed to use OTMP key on this device, this operation should
|
||||
* fail. */
|
||||
aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize);
|
||||
if (memcmp((uint32_t *)&base->AES_KEY0_W0, key, keySize) != 0)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Reenable BEE if it was enabled before. */
|
||||
if (reenable)
|
||||
{
|
||||
BEE_Enable(base);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
uint32_t BEE_GetStatusFlags(BEE_Type *base)
|
||||
{
|
||||
return base->STATUS;
|
||||
}
|
||||
|
||||
void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask)
|
||||
{
|
||||
/* w1c */
|
||||
base->STATUS |= mask;
|
||||
}
|
||||
228
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_bee.h
Normal file
228
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_bee.h
Normal file
@@ -0,0 +1,228 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_BEE_H_
|
||||
#define _FSL_BEE_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief BEE driver version. Version 2.0.0.
|
||||
*
|
||||
* Current version: 2.0.0
|
||||
*
|
||||
* Change log:
|
||||
* - Version 2.0.0
|
||||
* - Initial version
|
||||
*/
|
||||
#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
typedef enum _bee_aes_mode
|
||||
{
|
||||
kBEE_AesEcbMode = 0U, /*!< AES ECB Mode */
|
||||
kBEE_AesCtrMode = 1U /*!< AES CTR Mode */
|
||||
} bee_aes_mode_t;
|
||||
|
||||
typedef enum _bee_region
|
||||
{
|
||||
kBEE_Region0 = 0U, /*!< BEE region 0 */
|
||||
kBEE_Region1 = 1U /*!< BEE region 1 */
|
||||
} bee_region_t;
|
||||
|
||||
typedef enum _bee_region_enable
|
||||
{
|
||||
kBEE_RegionDisabled = 0U, /*!< BEE region disabled */
|
||||
kBEE_RegionEnabled = 1U /*!< BEE region enabled */
|
||||
} bee_region_enable_t;
|
||||
|
||||
typedef enum _bee_status_flags
|
||||
{
|
||||
kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */
|
||||
kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */
|
||||
kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */
|
||||
kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */
|
||||
kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */
|
||||
kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */
|
||||
kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */
|
||||
} bee_status_flags_t;
|
||||
|
||||
/*! @brief BEE region configuration structure. */
|
||||
typedef struct _bee_region_config
|
||||
{
|
||||
bee_aes_mode_t mode; /*!< AES mode used for encryption/decryption */
|
||||
uint32_t regionBot; /*!< Region bottom address */
|
||||
uint32_t regionTop; /*!< Region top address */
|
||||
uint32_t addrOffset; /*!< Region address offset */
|
||||
bee_region_enable_t regionEn; /*!< Region enable/disable */
|
||||
} bee_region_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Resets BEE module to factory default values.
|
||||
*
|
||||
* This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
*/
|
||||
void BEE_Init(BEE_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Resets BEE module, clears keys for both regions and disables clock to the BEE.
|
||||
*
|
||||
* This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both
|
||||
* regions are cleared.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
*/
|
||||
void BEE_Deinit(BEE_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enables BEE decryption.
|
||||
*
|
||||
* This function enables decryption using BEE.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
*/
|
||||
static inline void BEE_Enable(BEE_Type *base)
|
||||
{
|
||||
base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables BEE decryption.
|
||||
*
|
||||
* This function disables decryption using BEE.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
*/
|
||||
static inline void BEE_Disable(BEE_Type *base)
|
||||
{
|
||||
base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_KEY_VALID_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Loads default values to the BEE region configuration structure.
|
||||
*
|
||||
* Loads default values to the BEE region configuration structure. The default values are as follows:
|
||||
* @code
|
||||
* config->mode = kBEE_AesCbcMode;
|
||||
* config->regionBot = 0U;
|
||||
* config->regionTop = 0U;
|
||||
* config->addrOffset = 0xF0000000U;
|
||||
* config->regionEn = kBEE_RegionDisabled;
|
||||
* @endcode
|
||||
*
|
||||
* @param config Configuration structure for BEE region.
|
||||
*/
|
||||
void BEE_GetDefaultConfig(bee_region_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Sets BEE region configuration.
|
||||
*
|
||||
* This function sets BEE region settings accorging to given configuration structure.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
* @param region Selection of the BEE region to be configured.
|
||||
* @param config Configuration structure for BEE region.
|
||||
*/
|
||||
status_t BEE_SetRegionConfig(BEE_Type *base, bee_region_t region, const bee_region_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Loads the AES key and nonce for selected region into BEE key registers.
|
||||
*
|
||||
* This function loads given AES key and nonce(only AES CTR mode) to BEE register for the given region.
|
||||
*
|
||||
* Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers.
|
||||
* Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
* @param region Selection of the BEE region to be configured.
|
||||
* @param key AES key.
|
||||
* @param keySize Size of AES key.
|
||||
* @param nonce AES nonce.
|
||||
* @param nonceSize Size of AES nonce.
|
||||
*/
|
||||
status_t BEE_SetRegionKey(
|
||||
BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize, const uint8_t *nonce, size_t nonceSize);
|
||||
|
||||
/*!
|
||||
* @brief Gets the BEE status flags.
|
||||
*
|
||||
* This function returns status of BEE peripheral.
|
||||
*
|
||||
* @param base BEE peripheral address.
|
||||
*
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::bee_status_flags_t
|
||||
*/
|
||||
uint32_t BEE_GetStatusFlags(BEE_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clears the BEE status flags.
|
||||
*
|
||||
* @param base BEE peripheral base address.
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::bee_status_flags_t
|
||||
*/
|
||||
void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Computes offset to be set for specifed memory location.
|
||||
*
|
||||
* This function calculates offset that must be set for BEE region to access physical memory location.
|
||||
*
|
||||
* @param addressMemory Address of physical memory location.
|
||||
*/
|
||||
static inline uint32_t BEE_GetOffset(uint32_t addressMemory)
|
||||
{
|
||||
return (addressMemory >> 16);
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_BEE_H_ */
|
||||
464
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cache.c
Normal file
464
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cache.c
Normal file
@@ -0,0 +1,464 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_cache.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
|
||||
#define L2CACHE_8WAYS_MASK 0xFFU
|
||||
#define L2CACHE_16WAYS_MASK 0xFFFFU
|
||||
#define L2CACHE_SMALLWAYS_NUM 8U
|
||||
#define L2CACHE_1KBCOVERTOB 1024U
|
||||
#define L2CACHE_SAMLLWAYS_SIZE 16U
|
||||
#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Set for all ways and waiting for the operation finished.
|
||||
* This is provided for all the background operations.
|
||||
*
|
||||
* @param auxCtlReg The auxiliary control register.
|
||||
* @param regAddr The register address to be operated.
|
||||
*/
|
||||
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates the Level 2 cache line by physical address.
|
||||
* This function invalidates a cache line by physcial address.
|
||||
*
|
||||
* @param address The physical addderss of the cache.
|
||||
* The format of the address shall be :
|
||||
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||
* Tag | index | 0
|
||||
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||
* The n is varies according to the index width.
|
||||
* @return The actual 32-byte aligned physical address be operated.
|
||||
*/
|
||||
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address);
|
||||
|
||||
/*!
|
||||
* @brief Cleans the Level 2 cache line based on the physical address.
|
||||
* This function cleans a cache line based on a physcial address.
|
||||
*
|
||||
* @param address The physical addderss of the cache.
|
||||
* The format of the address shall be :
|
||||
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||
* Tag | index | 0
|
||||
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||
* The n is varies according to the index width.
|
||||
* @return The actual 32-byte aligned physical address be operated.
|
||||
*/
|
||||
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and invalidates the Level 2 cache line based on the physical address.
|
||||
* This function cleans and invalidates a cache line based on a physcial address.
|
||||
*
|
||||
* @param address The physical addderss of the cache.
|
||||
* The format of the address shall be :
|
||||
* bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0
|
||||
* Tag | index | 0
|
||||
* Note: the physical address shall be aligned to the line size - 32B (256 bit).
|
||||
* so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero.
|
||||
* If the input address is not aligned, it will be changed to 32-byte aligned address.
|
||||
* The n is varies according to the index width.
|
||||
* @return The actual 32-byte aligned physical address be operated.
|
||||
*/
|
||||
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address);
|
||||
|
||||
/*!
|
||||
* @brief Gets the number of the Level 2 cache and the way size.
|
||||
* This function cleans and invalidates a cache line based on a physcial address.
|
||||
*
|
||||
* @param num_ways The number of the cache way.
|
||||
* @param size_way The way size.
|
||||
*/
|
||||
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way);
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
|
||||
{
|
||||
uint16_t mask = L2CACHE_8WAYS_MASK;
|
||||
uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
|
||||
|
||||
/* Check the ways used at first. */
|
||||
if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
|
||||
{
|
||||
mask = L2CACHE_16WAYS_MASK;
|
||||
}
|
||||
|
||||
/* Set the opeartion for all ways/entries of the cache. */
|
||||
*(uint32_t *)regAddr = mask;
|
||||
/* Waiting for until the operation is complete. */
|
||||
while ((*(uint32_t *)regAddr & mask) && timeout)
|
||||
{
|
||||
__ASM("nop");
|
||||
timeout--;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address)
|
||||
{
|
||||
/* Align the address first. */
|
||||
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||
/* Invalidate the cache line by physical address. */
|
||||
L2CACHEC->REG7_INV_PA = address;
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
static uint32_t L2CACHE_CleanLineByAddr(uint32_t address)
|
||||
{
|
||||
/* Align the address first. */
|
||||
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||
/* Invalidate the cache line by physical address. */
|
||||
L2CACHEC->REG7_CLEAN_PA = address;
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address)
|
||||
{
|
||||
/* Align the address first. */
|
||||
address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1);
|
||||
/* Clean and invalidate the cache line by physical address. */
|
||||
L2CACHEC->REG7_CLEAN_INV_PA = address;
|
||||
|
||||
return address;
|
||||
}
|
||||
|
||||
static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way)
|
||||
{
|
||||
assert(num_ways);
|
||||
assert(size_way);
|
||||
|
||||
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
|
||||
|
||||
*num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM;
|
||||
if (!size)
|
||||
{
|
||||
/* 0 internally mapped to the same size as 1 - 16KB.*/
|
||||
size += 1;
|
||||
}
|
||||
*size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB;
|
||||
}
|
||||
|
||||
void L2CACHE_Init(l2cache_config_t *config)
|
||||
{
|
||||
assert (config);
|
||||
|
||||
uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */
|
||||
uint8_t count;
|
||||
uint32_t auxReg = 0;
|
||||
|
||||
/*The aux register must be configured when the cachec is disabled
|
||||
* So disable first if the cache controller is enabled.
|
||||
*/
|
||||
if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK)
|
||||
{
|
||||
L2CACHE_Disable();
|
||||
}
|
||||
|
||||
/* Unlock all entries. */
|
||||
if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
|
||||
{
|
||||
waysNum = 0xFFFFU;
|
||||
}
|
||||
|
||||
for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count ++)
|
||||
{
|
||||
L2CACHE_LockdownByWayEnable(count, waysNum, false);
|
||||
}
|
||||
|
||||
/* Set the ways and way-size etc. */
|
||||
auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) |
|
||||
L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc);
|
||||
L2CACHEC->REG1_AUX_CONTROL = auxReg;
|
||||
|
||||
/* Set the tag/data ram latency. */
|
||||
if (config->lateConfig)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
/* Tag latency. */
|
||||
data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
|
||||
L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate)|
|
||||
L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate)|
|
||||
L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
|
||||
L2CACHEC->REG1_TAG_RAM_CONTROL = data;
|
||||
/* Data latency. */
|
||||
data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
|
||||
L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate)|
|
||||
L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate)|
|
||||
L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate);
|
||||
L2CACHEC->REG1_DATA_RAM_CONTROL = data;
|
||||
}
|
||||
}
|
||||
|
||||
void L2CACHE_GetDefaultConfig(l2cache_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||
uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT;
|
||||
|
||||
/* Get the default value */
|
||||
config->wayNum = (l2cache_way_num_t)number;
|
||||
config->waySize = (l2cache_way_size)size;
|
||||
config->repacePolicy = kL2CACHE_Roundrobin;
|
||||
config->lateConfig = NULL;
|
||||
config->istrPrefetchEnable = false;
|
||||
config->dataPrefetchEnable = false;
|
||||
config->nsLockdownEnable = false;
|
||||
config->writeAlloc = kL2CACHE_UseAwcache;
|
||||
}
|
||||
|
||||
void L2CACHE_Enable(void)
|
||||
{
|
||||
/* Invalidate first. */
|
||||
L2CACHE_Invalidate();
|
||||
/* Enable the level 2 cache controller. */
|
||||
L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK;
|
||||
}
|
||||
|
||||
void L2CACHE_Disable(void)
|
||||
{
|
||||
/* First CleanInvalidate all enties in the cache. */
|
||||
L2CACHE_CleanInvalidate();
|
||||
/* Disable the level 2 cache controller. */
|
||||
L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK;
|
||||
/* DSB - data sync barrier.*/
|
||||
__DSB();
|
||||
}
|
||||
|
||||
void L2CACHE_Invalidate(void)
|
||||
{
|
||||
/* Invalidate all entries in cache. */
|
||||
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY);
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
void L2CACHE_Clean(void)
|
||||
{
|
||||
/* Clean all entries of the cache. */
|
||||
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY);
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
void L2CACHE_CleanInvalidate(void)
|
||||
{
|
||||
/* Clean all entries of the cache. */
|
||||
L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY);
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t endAddr = address + size_byte;
|
||||
|
||||
/* Invalidate addresses in the range. */
|
||||
while (address < endAddr)
|
||||
{
|
||||
address = L2CACHE_InvalidateLineByAddr(address);
|
||||
/* Update the size. */
|
||||
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||
}
|
||||
|
||||
/* Cache sync. */
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t num_ways = 0;
|
||||
uint32_t size_way = 0;
|
||||
uint32_t endAddr = address + size_byte;
|
||||
|
||||
/* Get the number and size of the cache way. */
|
||||
L2CACHE_GetWayNumSize(&num_ways, &size_way);
|
||||
|
||||
/* Check if the clean size is over the cache size. */
|
||||
if ((endAddr - address) > num_ways * size_way)
|
||||
{
|
||||
L2CACHE_Clean();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clean addresses in the range. */
|
||||
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
|
||||
{
|
||||
/* Clean the address in the range. */
|
||||
address = L2CACHE_CleanLineByAddr(address);
|
||||
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||
}
|
||||
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t num_ways = 0;
|
||||
uint32_t size_way = 0;
|
||||
uint32_t endAddr = address + size_byte;
|
||||
|
||||
/* Get the number and size of the cache way. */
|
||||
L2CACHE_GetWayNumSize(&num_ways, &size_way);
|
||||
|
||||
/* Check if the clean size is over the cache size. */
|
||||
if ((endAddr - address) > num_ways * size_way)
|
||||
{
|
||||
L2CACHE_CleanInvalidate();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Clean addresses in the range. */
|
||||
while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr)
|
||||
{
|
||||
/* Clean the address in the range. */
|
||||
address = L2CACHE_CleanInvalidateLineByAddr(address);
|
||||
address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE;
|
||||
}
|
||||
|
||||
L2CACHEC->REG7_CACHE_SYNC = 0;
|
||||
}
|
||||
|
||||
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
|
||||
{
|
||||
uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >>
|
||||
L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT;
|
||||
num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM;
|
||||
|
||||
assert(mask < (1U << num_ways));
|
||||
assert(masterId < L2CACHE_LOCKDOWN_REGNUM);
|
||||
|
||||
uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN;
|
||||
uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN;
|
||||
|
||||
if (enable)
|
||||
{
|
||||
/* Data lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask;
|
||||
/* Instruction lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Data lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask;
|
||||
/* Instruction lockdown. */
|
||||
L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
|
||||
|
||||
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
#if (__DCACHE_PRESENT == 1U)
|
||||
uint32_t addr = address & (uint32_t)~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1);
|
||||
int32_t size = size_byte + address - addr;
|
||||
uint32_t linesize = 32U;
|
||||
|
||||
__DSB();
|
||||
while (size > 0)
|
||||
{
|
||||
SCB->ICIMVAU = addr;
|
||||
addr += linesize;
|
||||
size -= linesize;
|
||||
}
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_InvalidateByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
|
||||
|
||||
L1CACHE_InvalidateICacheByRange(address, size_byte);
|
||||
}
|
||||
|
||||
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_InvalidateByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
|
||||
L1CACHE_InvalidateDCacheByRange(address, size_byte);
|
||||
}
|
||||
|
||||
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
L1CACHE_CleanDCacheByRange(address, size_byte);
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_CleanByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
|
||||
}
|
||||
|
||||
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
L2CACHE_CleanInvalidateByRange(address, size_byte);
|
||||
#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
|
||||
#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
|
||||
}
|
||||
494
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cache.h
Normal file
494
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cache.h
Normal file
@@ -0,0 +1,494 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_CACHE_H_
|
||||
#define _FSL_CACHE_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup cache
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief cache driver version 2.0.1. */
|
||||
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
|
||||
#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
|
||||
#endif
|
||||
#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
|
||||
/*! @brief Number of level 2 cache controller ways. */
|
||||
typedef enum _l2cache_way_num
|
||||
{
|
||||
kL2CACHE_8ways = 0, /*!< 8 ways. */
|
||||
#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
|
||||
kL2CACHE_16ways /*!< 16 ways. */
|
||||
#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
|
||||
} l2cache_way_num_t;
|
||||
|
||||
/*! @brief Level 2 cache controller way size. */
|
||||
typedef enum _l2cache_way_size
|
||||
{
|
||||
kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
|
||||
kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
|
||||
kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
|
||||
kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
|
||||
kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
|
||||
kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
|
||||
} l2cache_way_size;
|
||||
|
||||
/*! @brief Level 2 cache controller replacement policy. */
|
||||
typedef enum _l2cache_replacement
|
||||
{
|
||||
kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
|
||||
kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
|
||||
} l2cache_replacement_t;
|
||||
|
||||
/*! @brief Level 2 cache controller force write allocate options. */
|
||||
typedef enum _l2cache_writealloc
|
||||
{
|
||||
kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
|
||||
kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
|
||||
kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
|
||||
} l2cache_writealloc_t;
|
||||
|
||||
/*! @brief Level 2 cache controller tag/data ram latency. */
|
||||
typedef enum _l2cache_latency
|
||||
{
|
||||
kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
|
||||
kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
|
||||
kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
|
||||
kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
|
||||
kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
|
||||
kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
|
||||
kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
|
||||
kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
|
||||
} l2cache_latency_t;
|
||||
|
||||
/*! @brief Level 2 cache controller tag/data ram latency configure structure. */
|
||||
typedef struct _l2cache_latency_config
|
||||
{
|
||||
l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
|
||||
l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
|
||||
l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
|
||||
l2cache_latency_t dataWriteLate; /*!< Data write latency. */
|
||||
l2cache_latency_t dataReadLate; /*!< Data Read latency. */
|
||||
l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
|
||||
} L2cache_latency_config_t;
|
||||
|
||||
/*! @brief Level 2 cache controller configure structure. */
|
||||
typedef struct _l2cache_config
|
||||
{
|
||||
/* ------------------------ l2 cachec basic settings ---------------------------- */
|
||||
l2cache_way_num_t wayNum; /*!< The number of ways. */
|
||||
l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
|
||||
l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */
|
||||
/* ------------------------ tag/data ram latency settings ----------------------- */
|
||||
L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
|
||||
/* ------------------------ Prefetch enable settings ---------------------------- */
|
||||
bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
|
||||
bool dataPrefetchEnable; /*!< Data prefetch enable. */
|
||||
/* ------------------------ Non-secure access settings -------------------------- */
|
||||
bool nsLockdownEnable; /*!< None-secure lockdown enable. */
|
||||
/* ------------------------ other settings -------------------------------------- */
|
||||
l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */
|
||||
} l2cache_config_t;
|
||||
#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Control for cortex-m7 L1 cache
|
||||
*@{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables cortex-m7 L1 instruction cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_EnableICache(void)
|
||||
{
|
||||
SCB_EnableICache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables cortex-m7 L1 instruction cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_DisableICache(void)
|
||||
{
|
||||
SCB_DisableICache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidate cortex-m7 L1 instruction cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_InvalidateICache(void)
|
||||
{
|
||||
SCB_InvalidateICache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidate cortex-m7 L1 instruction cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 I-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Enables cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_EnableDCache(void)
|
||||
{
|
||||
SCB_EnableDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_DisableDCache(void)
|
||||
{
|
||||
SCB_DisableDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidates cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_InvalidateDCache(void)
|
||||
{
|
||||
SCB_InvalidateDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_CleanDCache(void)
|
||||
{
|
||||
SCB_CleanDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans and Invalidates cortex-m7 L1 data cache.
|
||||
*
|
||||
*/
|
||||
static inline void L1CACHE_CleanInvalidateDCache(void)
|
||||
{
|
||||
SCB_CleanInvalidateDCache();
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Invalidates cortex-m7 L1 data cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
|
||||
uint32_t size = size_byte + address - startAddr;
|
||||
|
||||
SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans cortex-m7 L1 data cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be cleaned.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
|
||||
uint32_t size = size_byte + address - startAddr;
|
||||
|
||||
SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
|
||||
*
|
||||
* @param address The start address of the memory to be clean and invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L1 D-cache line size if
|
||||
* startAddr is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
|
||||
{
|
||||
uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1);
|
||||
uint32_t size = size_byte + address - startAddr;
|
||||
|
||||
SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
|
||||
/*!
|
||||
* @name Control for L2 pl310 cache
|
||||
*@{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the level 2 cache controller module.
|
||||
*
|
||||
* @param config Pointer to configuration structure. See "l2cache_config_t".
|
||||
*/
|
||||
void L2CACHE_Init(l2cache_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available default settings for the cache controller.
|
||||
*
|
||||
* This function initializes the cache controller configuration structure with default settings.
|
||||
* The default values are:
|
||||
* @code
|
||||
* config->waysNum = kL2CACHE_8ways;
|
||||
* config->waySize = kL2CACHE_32KbSize;
|
||||
* config->repacePolicy = kL2CACHE_Roundrobin;
|
||||
* config->lateConfig = NULL;
|
||||
* config->istrPrefetchEnable = false;
|
||||
* config->dataPrefetchEnable = false;
|
||||
* config->nsLockdownEnable = false;
|
||||
* config->writeAlloc = kL2CACHE_UseAwcache;
|
||||
* @endcode
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Enables the level 2 cache controller.
|
||||
* This function enables the cache controller. Must be written using a secure access.
|
||||
* If write with a Non-secure access will cause a DECERR response.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Enable(void);
|
||||
|
||||
/*!
|
||||
* @brief Disables the level 2 cache controller.
|
||||
* This function disables the cache controller. Must be written using a secure access.
|
||||
* If write with a Non-secure access will cause a DECERR response.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Disable(void);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates the Level 2 cache.
|
||||
* This function invalidates all entries in cache.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Invalidate(void);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function invalidates all cache lines between two physical addresses.
|
||||
*
|
||||
* @param address The start address of the memory to be invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans the level 2 cache controller.
|
||||
* This function cleans all entries in the level 2 cache controller.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_Clean(void);
|
||||
|
||||
/*!
|
||||
* @brief Cleans the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function cleans all cache lines between two physical addresses.
|
||||
*
|
||||
* @param address The start address of the memory to be cleaned.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and invalidates the level 2 cache controller.
|
||||
* This function cleans and invalidates all entries in the level 2 cache controller.
|
||||
*
|
||||
*/
|
||||
void L2CACHE_CleanInvalidate(void);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
|
||||
* This function cleans and invalidates all cache lines between two physical addresses.
|
||||
*
|
||||
* @param address The start address of the memory to be cleaned and invalidated.
|
||||
* @param size_byte The memory size.
|
||||
* @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
|
||||
* The startAddr here will be forced to align to L2 line size if startAddr
|
||||
* is not aligned. For the size_byte, application should make sure the
|
||||
* alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Enables or disables to lock down the data and instruction by way.
|
||||
* This function locks down the cached instruction/data by way and prevent the adresses from
|
||||
* being allocated and prevent dara from being evicted out of the level 2 cache.
|
||||
* But the normal cache maintenance operations that invalidate, clean or clean
|
||||
* and validate cache contents affect the locked-down cache lines as normal.
|
||||
*
|
||||
* @param masterId The master id, range from 0 ~ 7.
|
||||
* @param mask The ways to be enabled or disabled to lockdown.
|
||||
* each bit in value is related to each way of the cache. for example:
|
||||
* value: bit 0 ------ way 0.
|
||||
* value: bit 1 ------ way 1.
|
||||
* --------------------------
|
||||
* value: bit 15 ------ way 15.
|
||||
* Note: please make sure the value setting is align with your supported ways.
|
||||
* @param enable True enable the lockdown, false to disable the lockdown.
|
||||
*/
|
||||
void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
|
||||
|
||||
/*@}*/
|
||||
#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
|
||||
|
||||
/*!
|
||||
* @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
|
||||
* Mainly used for many drivers for easy cache operation.
|
||||
*@{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Invalidates all instruction caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be invalidated.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Invalidates all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be invalidated.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be cleaned.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*!
|
||||
* @brief Cleans and Invalidates all data caches by range.
|
||||
*
|
||||
* Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
|
||||
*
|
||||
* @param address The physical address.
|
||||
* @param size_byte size of the memory to be cleaned and invalidated.
|
||||
* @note address and size should be aligned to cache line size
|
||||
* 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
|
||||
* to align to the cache line size if startAddr is not aligned. For the size_byte, application should
|
||||
* make sure the alignment or make sure the right operation order if the size_byte is not aligned.
|
||||
*/
|
||||
void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_CACHE_H_*/
|
||||
843
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_clock.c
Normal file
843
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_clock.c
Normal file
@@ -0,0 +1,843 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/* External XTAL (OSC) clock frequency. */
|
||||
uint32_t g_xtalFreq;
|
||||
/* External RTC XTAL clock frequency. */
|
||||
uint32_t g_rtcXtalFreq;
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t CLOCK_GetPeriphClkFreq(void)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
/* Periph_clk2_clk ---> Periph_clk */
|
||||
if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
|
||||
{
|
||||
switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
|
||||
{
|
||||
/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
|
||||
break;
|
||||
|
||||
/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
|
||||
freq = CLOCK_GetOscFreq();
|
||||
break;
|
||||
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
|
||||
break;
|
||||
|
||||
case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
|
||||
}
|
||||
/* Pre_Periph_clk ---> Periph_clk */
|
||||
else
|
||||
{
|
||||
switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
|
||||
{
|
||||
/* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
|
||||
break;
|
||||
|
||||
/* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
|
||||
break;
|
||||
|
||||
/* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0);
|
||||
break;
|
||||
|
||||
/* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
|
||||
case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
|
||||
break;
|
||||
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
void CLOCK_InitExternalClk(bool bypassXtalOsc)
|
||||
{
|
||||
/* This device does not support bypass XTAL OSC. */
|
||||
assert(!bypassXtalOsc);
|
||||
|
||||
CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */
|
||||
while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0)
|
||||
{
|
||||
}
|
||||
CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */
|
||||
while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_DeinitExternalClk(void)
|
||||
{
|
||||
CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */
|
||||
}
|
||||
|
||||
void CLOCK_SwitchOsc(clock_osc_t osc)
|
||||
{
|
||||
if (osc == kCLOCK_RcOsc)
|
||||
XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK;
|
||||
else
|
||||
XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_InitRcOsc24M(void)
|
||||
{
|
||||
XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_DeinitRcOsc24M(void)
|
||||
{
|
||||
XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetFreq(clock_name_t name)
|
||||
{
|
||||
uint32_t freq;
|
||||
|
||||
switch (name)
|
||||
{
|
||||
case kCLOCK_CpuClk:
|
||||
/* Periph_clk ---> AHB Clock */
|
||||
case kCLOCK_AhbClk:
|
||||
/* Periph_clk ---> AHB Clock */
|
||||
freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
|
||||
break;
|
||||
|
||||
case kCLOCK_SemcClk:
|
||||
/* SEMC alternative clock ---> SEMC Clock */
|
||||
if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK)
|
||||
{
|
||||
/* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
|
||||
if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
|
||||
{
|
||||
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
|
||||
}
|
||||
/* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
|
||||
}
|
||||
}
|
||||
/* Periph_clk ---> SEMC Clock */
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetPeriphClkFreq();
|
||||
}
|
||||
|
||||
freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
|
||||
break;
|
||||
|
||||
case kCLOCK_IpgClk:
|
||||
/* Periph_clk ---> AHB Clock ---> IPG Clock */
|
||||
freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
|
||||
freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
|
||||
break;
|
||||
|
||||
case kCLOCK_OscClk:
|
||||
freq = CLOCK_GetOscFreq();
|
||||
break;
|
||||
case kCLOCK_RtcClk:
|
||||
freq = CLOCK_GetRtcFreq();
|
||||
break;
|
||||
case kCLOCK_ArmPllClk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllArm);
|
||||
break;
|
||||
case kCLOCK_Usb1PllClk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
|
||||
break;
|
||||
case kCLOCK_Usb1PllPfd0Clk:
|
||||
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0);
|
||||
break;
|
||||
case kCLOCK_Usb1PllPfd1Clk:
|
||||
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
|
||||
break;
|
||||
case kCLOCK_Usb1PllPfd2Clk:
|
||||
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2);
|
||||
break;
|
||||
case kCLOCK_Usb1PllPfd3Clk:
|
||||
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3);
|
||||
break;
|
||||
case kCLOCK_Usb2PllClk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2);
|
||||
break;
|
||||
case kCLOCK_SysPllClk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
|
||||
break;
|
||||
case kCLOCK_SysPllPfd0Clk:
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0);
|
||||
break;
|
||||
case kCLOCK_SysPllPfd1Clk:
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1);
|
||||
break;
|
||||
case kCLOCK_SysPllPfd2Clk:
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
|
||||
break;
|
||||
case kCLOCK_SysPllPfd3Clk:
|
||||
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3);
|
||||
break;
|
||||
case kCLOCK_EnetPll0Clk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllEnet0);
|
||||
break;
|
||||
case kCLOCK_EnetPll1Clk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllEnet1);
|
||||
break;
|
||||
case kCLOCK_AudioPllClk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
|
||||
break;
|
||||
case kCLOCK_VideoPllClk:
|
||||
freq = CLOCK_GetPllFreq(kCLOCK_PllVideo);
|
||||
break;
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
|
||||
{
|
||||
CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_MASK |
|
||||
CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider);
|
||||
|
||||
while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitArmPll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
|
||||
{
|
||||
CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_ENABLE_MASK |
|
||||
CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
|
||||
|
||||
while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitSysPll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
|
||||
{
|
||||
CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_ENABLE_MASK |
|
||||
CCM_ANALOG_PLL_USB1_POWER_MASK |
|
||||
CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK |
|
||||
CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider);
|
||||
|
||||
while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitUsb1Pll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_USB1 = 0U;
|
||||
}
|
||||
|
||||
void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
|
||||
{
|
||||
CCM_ANALOG->PLL_USB2 = CCM_ANALOG_PLL_USB2_ENABLE_MASK |
|
||||
CCM_ANALOG_PLL_USB2_POWER_MASK |
|
||||
CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK |
|
||||
CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider);
|
||||
|
||||
while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitUsb2Pll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_USB2 = 0U;
|
||||
}
|
||||
|
||||
void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
|
||||
{
|
||||
uint32_t pllAudio;
|
||||
uint32_t misc2 = 0;
|
||||
|
||||
CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
|
||||
CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator);
|
||||
|
||||
/*
|
||||
* Set post divider:
|
||||
*
|
||||
* ------------------------------------------------------------------------
|
||||
* | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 1 | 2 | 0 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 2 | 1 | 0 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 4 | 2 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 8 | 1 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 16 | 0 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
*/
|
||||
pllAudio = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider);
|
||||
|
||||
switch (config->postDivider)
|
||||
{
|
||||
case 16:
|
||||
pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0);
|
||||
misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1);
|
||||
misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2);
|
||||
misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1);
|
||||
break;
|
||||
|
||||
default:
|
||||
pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2);
|
||||
break;
|
||||
}
|
||||
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK))
|
||||
| misc2;
|
||||
|
||||
CCM_ANALOG->PLL_AUDIO = pllAudio;
|
||||
|
||||
while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitAudioPll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
|
||||
{
|
||||
uint32_t pllVideo;
|
||||
uint32_t misc2 = 0;
|
||||
|
||||
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator);
|
||||
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator);
|
||||
|
||||
/*
|
||||
* Set post divider:
|
||||
*
|
||||
* ------------------------------------------------------------------------
|
||||
* | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 1 | 2 | 0 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 2 | 1 | 0 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 4 | 2 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 8 | 1 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
* | 16 | 0 | 3 |
|
||||
* ------------------------------------------------------------------------
|
||||
*/
|
||||
pllVideo = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider);
|
||||
|
||||
switch (config->postDivider)
|
||||
{
|
||||
case 16:
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0);
|
||||
misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
break;
|
||||
|
||||
case 8:
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2);
|
||||
misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
break;
|
||||
|
||||
default:
|
||||
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2);
|
||||
break;
|
||||
}
|
||||
|
||||
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2;
|
||||
|
||||
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||||
|
||||
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitVideoPll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
|
||||
}
|
||||
|
||||
void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
|
||||
{
|
||||
uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider);
|
||||
|
||||
if (config->enableClkOutput0)
|
||||
{
|
||||
enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||||
}
|
||||
|
||||
if (config->enableClkOutput1)
|
||||
{
|
||||
enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||||
}
|
||||
|
||||
CCM_ANALOG->PLL_ENET = enet_pll;
|
||||
|
||||
/* Wait for stable */
|
||||
while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void CLOCK_DeinitEnetPll(void)
|
||||
{
|
||||
CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
|
||||
{
|
||||
uint32_t freq;
|
||||
uint32_t divSelect;
|
||||
uint64_t freqTmp;
|
||||
|
||||
const uint32_t enetRefClkFreq[] = {
|
||||
25000000U, /* 25M */
|
||||
50000000U, /* 50M */
|
||||
100000000U, /* 100M */
|
||||
125000000U /* 125M */
|
||||
};
|
||||
|
||||
/* check if PLL is enabled */
|
||||
if(!CLOCK_IsPllEnabled(CCM_ANALOG, pll))
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
|
||||
/* get pll reference clock */
|
||||
freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll);
|
||||
|
||||
/* check if pll is bypassed */
|
||||
if(CLOCK_IsPllBypassed(CCM_ANALOG, pll))
|
||||
{
|
||||
return freq;
|
||||
}
|
||||
|
||||
switch (pll)
|
||||
{
|
||||
case kCLOCK_PllArm:
|
||||
freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
|
||||
CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
|
||||
break;
|
||||
|
||||
case kCLOCK_PllSys:
|
||||
/* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
|
||||
freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
|
||||
|
||||
if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
|
||||
{
|
||||
freq *= 22U;
|
||||
}
|
||||
else
|
||||
{
|
||||
freq *= 20U;
|
||||
}
|
||||
|
||||
freq += (uint32_t)freqTmp;
|
||||
break;
|
||||
|
||||
case kCLOCK_PllUsb1:
|
||||
freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
|
||||
break;
|
||||
|
||||
case kCLOCK_PllAudio:
|
||||
/* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
|
||||
divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
|
||||
|
||||
freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
|
||||
|
||||
freq = freq * divSelect + (uint32_t)freqTmp;
|
||||
|
||||
/* AUDIO PLL output = PLL output frequency / POSTDIV. */
|
||||
|
||||
/*
|
||||
* Post divider:
|
||||
*
|
||||
* PLL_AUDIO[POST_DIV_SELECT]:
|
||||
* 0x00: 4
|
||||
* 0x01: 2
|
||||
* 0x02: 1
|
||||
*
|
||||
* MISC2[AUDO_DIV]:
|
||||
* 0x00: 1
|
||||
* 0x01: 2
|
||||
* 0x02: 1
|
||||
* 0x03: 4
|
||||
*/
|
||||
switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
|
||||
{
|
||||
case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U):
|
||||
freq = freq >> 2U;
|
||||
break;
|
||||
|
||||
case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U):
|
||||
freq = freq >> 1U;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK))
|
||||
{
|
||||
case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1):
|
||||
freq >>= 2U;
|
||||
break;
|
||||
|
||||
case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1):
|
||||
freq >>= 1U;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case kCLOCK_PllVideo:
|
||||
/* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
|
||||
divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
|
||||
|
||||
freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
|
||||
|
||||
freq = freq * divSelect + (uint32_t)freqTmp;
|
||||
|
||||
/* VIDEO PLL output = PLL output frequency / POSTDIV. */
|
||||
|
||||
/*
|
||||
* Post divider:
|
||||
*
|
||||
* PLL_VIDEO[POST_DIV_SELECT]:
|
||||
* 0x00: 4
|
||||
* 0x01: 2
|
||||
* 0x02: 1
|
||||
*
|
||||
* MISC2[VIDEO_DIV]:
|
||||
* 0x00: 1
|
||||
* 0x01: 2
|
||||
* 0x02: 1
|
||||
* 0x03: 4
|
||||
*/
|
||||
switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
|
||||
{
|
||||
case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U):
|
||||
freq = freq >> 2U;
|
||||
break;
|
||||
|
||||
case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U):
|
||||
freq = freq >> 1U;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
|
||||
{
|
||||
case CCM_ANALOG_MISC2_VIDEO_DIV(3):
|
||||
freq >>= 2U;
|
||||
break;
|
||||
|
||||
case CCM_ANALOG_MISC2_VIDEO_DIV(1):
|
||||
freq >>= 1U;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case kCLOCK_PllEnet0:
|
||||
divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
|
||||
>> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT;
|
||||
freq = enetRefClkFreq[divSelect];
|
||||
break;
|
||||
|
||||
case kCLOCK_PllEnet1:
|
||||
/* ref_enetpll1 if fixed at 25MHz. */
|
||||
freq = 25000000UL;
|
||||
break;
|
||||
|
||||
case kCLOCK_PllUsb2:
|
||||
freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U));
|
||||
break;
|
||||
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
|
||||
{
|
||||
uint32_t pfdIndex = (uint32_t)pfd;
|
||||
uint32_t pfd528;
|
||||
|
||||
pfd528 = CCM_ANALOG->PFD_528 & ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex));
|
||||
|
||||
/* Disable the clock output first. */
|
||||
CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex));
|
||||
|
||||
/* Set the new value and enable output. */
|
||||
CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex));
|
||||
}
|
||||
|
||||
void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
|
||||
{
|
||||
CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd);
|
||||
}
|
||||
|
||||
void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
|
||||
{
|
||||
uint32_t pfdIndex = (uint32_t)pfd;
|
||||
uint32_t pfd480;
|
||||
|
||||
pfd480 = CCM_ANALOG->PFD_480 & ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex));
|
||||
|
||||
/* Disable the clock output first. */
|
||||
CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex));
|
||||
|
||||
/* Set the new value and enable output. */
|
||||
CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex));
|
||||
}
|
||||
|
||||
void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd)
|
||||
{
|
||||
CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd);
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
|
||||
{
|
||||
uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
|
||||
|
||||
switch (pfd)
|
||||
{
|
||||
case kCLOCK_Pfd0:
|
||||
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
case kCLOCK_Pfd1:
|
||||
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
case kCLOCK_Pfd2:
|
||||
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
case kCLOCK_Pfd3:
|
||||
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
freq *= 18U;
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
|
||||
{
|
||||
uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
|
||||
|
||||
switch (pfd)
|
||||
{
|
||||
case kCLOCK_Pfd0:
|
||||
freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
case kCLOCK_Pfd1:
|
||||
freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
case kCLOCK_Pfd2:
|
||||
freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
case kCLOCK_Pfd3:
|
||||
freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT);
|
||||
break;
|
||||
|
||||
default:
|
||||
freq = 0U;
|
||||
break;
|
||||
}
|
||||
freq *= 18U;
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
|
||||
{
|
||||
CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ;
|
||||
USB1->USBCMD |= USBHS_USBCMD_RST_MASK;
|
||||
for (volatile uint32_t i = 0; i < 400000; i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
|
||||
{
|
||||
__ASM("nop");
|
||||
}
|
||||
PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
|
||||
{
|
||||
CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ;
|
||||
USB2->USBCMD |= USBHS_USBCMD_RST_MASK;
|
||||
for (volatile uint32_t i = 0; i < 400000; i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
|
||||
{
|
||||
__ASM("nop");
|
||||
}
|
||||
PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
|
||||
{
|
||||
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
|
||||
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
|
||||
USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
|
||||
USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
|
||||
|
||||
USBPHY1->PWD = 0;
|
||||
USBPHY1->CTRL |=
|
||||
USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK |
|
||||
USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
|
||||
USBPHY_CTRL_ENUTMILEVEL2_MASK |
|
||||
USBPHY_CTRL_ENUTMILEVEL3_MASK;
|
||||
return true;
|
||||
}
|
||||
bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
|
||||
{
|
||||
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
|
||||
CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll);
|
||||
USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
|
||||
USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
|
||||
|
||||
USBPHY2->PWD = 0;
|
||||
USBPHY2->CTRL |=
|
||||
USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK |
|
||||
USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
|
||||
USBPHY_CTRL_ENUTMILEVEL2_MASK |
|
||||
USBPHY_CTRL_ENUTMILEVEL3_MASK;
|
||||
|
||||
return true;
|
||||
}
|
||||
void CLOCK_DisableUsbhs0PhyPllClock(void)
|
||||
{
|
||||
CLOCK_DeinitUsb1Pll();
|
||||
USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
|
||||
|
||||
}
|
||||
void CLOCK_DisableUsbhs1PhyPllClock(void)
|
||||
{
|
||||
CLOCK_DeinitUsb2Pll();
|
||||
USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
|
||||
}
|
||||
1362
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_clock.h
Normal file
1362
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_clock.h
Normal file
File diff suppressed because it is too large
Load Diff
289
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cmp.c
Normal file
289
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cmp.c
Normal file
@@ -0,0 +1,289 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_cmp.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Get instance number for CMP module.
|
||||
*
|
||||
* @param base CMP peripheral base address
|
||||
*/
|
||||
static uint32_t CMP_GetInstance(CMP_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to CMP bases for each instance. */
|
||||
static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to CMP clocks for each instance. */
|
||||
static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Codes
|
||||
******************************************************************************/
|
||||
static uint32_t CMP_GetInstance(CMP_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++)
|
||||
{
|
||||
if (s_cmpBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_cmpBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void CMP_Init(CMP_Type *base, const cmp_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint8_t tmp8;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the clock. */
|
||||
CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Configure. */
|
||||
CMP_Enable(base, false); /* Disable the CMP module during configuring. */
|
||||
/* CMPx_CR1. */
|
||||
tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK);
|
||||
if (config->enableHighSpeed)
|
||||
{
|
||||
tmp8 |= CMP_CR1_PMODE_MASK;
|
||||
}
|
||||
if (config->enableInvertOutput)
|
||||
{
|
||||
tmp8 |= CMP_CR1_INV_MASK;
|
||||
}
|
||||
if (config->useUnfilteredOutput)
|
||||
{
|
||||
tmp8 |= CMP_CR1_COS_MASK;
|
||||
}
|
||||
if (config->enablePinOut)
|
||||
{
|
||||
tmp8 |= CMP_CR1_OPE_MASK;
|
||||
}
|
||||
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
|
||||
if (config->enableTriggerMode)
|
||||
{
|
||||
tmp8 |= CMP_CR1_TRIGM_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp8 &= ~CMP_CR1_TRIGM_MASK;
|
||||
}
|
||||
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
|
||||
base->CR1 = tmp8;
|
||||
|
||||
/* CMPx_CR0. */
|
||||
tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK;
|
||||
tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
|
||||
base->CR0 = tmp8;
|
||||
|
||||
CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
|
||||
}
|
||||
|
||||
void CMP_Deinit(CMP_Type *base)
|
||||
{
|
||||
/* Disable the CMP module. */
|
||||
CMP_Enable(base, false);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the clock. */
|
||||
CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void CMP_GetDefaultConfig(cmp_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
config->enableCmp = true; /* Enable the CMP module after initialization. */
|
||||
config->hysteresisMode = kCMP_HysteresisLevel0;
|
||||
config->enableHighSpeed = false;
|
||||
config->enableInvertOutput = false;
|
||||
config->useUnfilteredOutput = false;
|
||||
config->enablePinOut = false;
|
||||
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
|
||||
config->enableTriggerMode = false;
|
||||
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
|
||||
}
|
||||
|
||||
void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
|
||||
{
|
||||
uint8_t tmp8 = base->MUXCR;
|
||||
|
||||
tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
|
||||
tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
|
||||
base->MUXCR = tmp8;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
|
||||
void CMP_EnableDMA(CMP_Type *base, bool enable)
|
||||
{
|
||||
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
|
||||
|
||||
if (enable)
|
||||
{
|
||||
tmp8 |= CMP_SCR_DMAEN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp8 &= ~CMP_SCR_DMAEN_MASK;
|
||||
}
|
||||
base->SCR = tmp8;
|
||||
}
|
||||
#endif /* FSL_FEATURE_CMP_HAS_DMA */
|
||||
|
||||
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
|
||||
{
|
||||
assert(NULL != config);
|
||||
|
||||
uint8_t tmp8;
|
||||
|
||||
#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
|
||||
/* Choose the clock source for sampling. */
|
||||
if (config->enableSample)
|
||||
{
|
||||
base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */
|
||||
}
|
||||
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
|
||||
/* Set the filter count. */
|
||||
tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
|
||||
tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
|
||||
base->CR0 = tmp8;
|
||||
/* Set the filter period. It is used as the divider to bus clock. */
|
||||
base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
|
||||
}
|
||||
|
||||
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
|
||||
{
|
||||
uint8_t tmp8 = 0U;
|
||||
|
||||
if (NULL == config)
|
||||
{
|
||||
/* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
|
||||
base->DACCR = 0U;
|
||||
return;
|
||||
}
|
||||
/* CMPx_DACCR. */
|
||||
tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
|
||||
if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
|
||||
{
|
||||
tmp8 |= CMP_DACCR_VRSEL_MASK;
|
||||
}
|
||||
tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
|
||||
|
||||
base->DACCR = tmp8;
|
||||
}
|
||||
|
||||
void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
|
||||
{
|
||||
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
|
||||
|
||||
if (0U != (kCMP_OutputRisingInterruptEnable & mask))
|
||||
{
|
||||
tmp8 |= CMP_SCR_IER_MASK;
|
||||
}
|
||||
if (0U != (kCMP_OutputFallingInterruptEnable & mask))
|
||||
{
|
||||
tmp8 |= CMP_SCR_IEF_MASK;
|
||||
}
|
||||
base->SCR = tmp8;
|
||||
}
|
||||
|
||||
void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
|
||||
{
|
||||
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
|
||||
|
||||
if (0U != (kCMP_OutputRisingInterruptEnable & mask))
|
||||
{
|
||||
tmp8 &= ~CMP_SCR_IER_MASK;
|
||||
}
|
||||
if (0U != (kCMP_OutputFallingInterruptEnable & mask))
|
||||
{
|
||||
tmp8 &= ~CMP_SCR_IEF_MASK;
|
||||
}
|
||||
base->SCR = tmp8;
|
||||
}
|
||||
|
||||
uint32_t CMP_GetStatusFlags(CMP_Type *base)
|
||||
{
|
||||
uint32_t ret32 = 0U;
|
||||
|
||||
if (0U != (CMP_SCR_CFR_MASK & base->SCR))
|
||||
{
|
||||
ret32 |= kCMP_OutputRisingEventFlag;
|
||||
}
|
||||
if (0U != (CMP_SCR_CFF_MASK & base->SCR))
|
||||
{
|
||||
ret32 |= kCMP_OutputFallingEventFlag;
|
||||
}
|
||||
if (0U != (CMP_SCR_COUT_MASK & base->SCR))
|
||||
{
|
||||
ret32 |= kCMP_OutputAssertEventFlag;
|
||||
}
|
||||
return ret32;
|
||||
}
|
||||
|
||||
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
|
||||
{
|
||||
uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
|
||||
|
||||
if (0U != (kCMP_OutputRisingEventFlag & mask))
|
||||
{
|
||||
tmp8 |= CMP_SCR_CFR_MASK;
|
||||
}
|
||||
if (0U != (kCMP_OutputFallingEventFlag & mask))
|
||||
{
|
||||
tmp8 |= CMP_SCR_CFF_MASK;
|
||||
}
|
||||
base->SCR = tmp8;
|
||||
}
|
||||
347
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cmp.h
Normal file
347
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_cmp.h
Normal file
@@ -0,0 +1,347 @@
|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_CMP_H_
|
||||
#define _FSL_CMP_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup cmp
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief CMP driver version 2.0.0. */
|
||||
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Interrupt enable/disable mask.
|
||||
*/
|
||||
enum _cmp_interrupt_enable
|
||||
{
|
||||
kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */
|
||||
kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief Status flags' mask.
|
||||
*/
|
||||
enum _cmp_status_flags
|
||||
{
|
||||
kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */
|
||||
kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
|
||||
kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief CMP Hysteresis mode.
|
||||
*/
|
||||
typedef enum _cmp_hysteresis_mode
|
||||
{
|
||||
kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */
|
||||
kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */
|
||||
kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */
|
||||
kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */
|
||||
} cmp_hysteresis_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief CMP Voltage Reference source.
|
||||
*/
|
||||
typedef enum _cmp_reference_voltage_source
|
||||
{
|
||||
kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */
|
||||
kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */
|
||||
} cmp_reference_voltage_source_t;
|
||||
|
||||
/*!
|
||||
* @brief Configures the comparator.
|
||||
*/
|
||||
typedef struct _cmp_config
|
||||
{
|
||||
bool enableCmp; /*!< Enable the CMP module. */
|
||||
cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */
|
||||
bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */
|
||||
bool enableInvertOutput; /*!< Enable the inverted comparator output. */
|
||||
bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */
|
||||
bool enablePinOut; /*!< The comparator output is available on the associated pin. */
|
||||
#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
|
||||
bool enableTriggerMode; /*!< Enable the trigger mode. */
|
||||
#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
|
||||
} cmp_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Configures the filter.
|
||||
*/
|
||||
typedef struct _cmp_filter_config
|
||||
{
|
||||
#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
|
||||
bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */
|
||||
#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
|
||||
uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/
|
||||
uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */
|
||||
} cmp_filter_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Configures the internal DAC.
|
||||
*/
|
||||
typedef struct _cmp_dac_config
|
||||
{
|
||||
cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
|
||||
uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
|
||||
} cmp_dac_config_t;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @name Initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the CMP.
|
||||
*
|
||||
* This function initializes the CMP module. The operations included are as follows.
|
||||
* - Enabling the clock for CMP module.
|
||||
* - Configuring the comparator.
|
||||
* - Enabling the CMP module.
|
||||
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
|
||||
* any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void CMP_Init(CMP_Type *base, const cmp_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the CMP module.
|
||||
*
|
||||
* This function de-initializes the CMP module. The operations included are as follows.
|
||||
* - Disabling the CMP module.
|
||||
* - Disabling the clock for CMP module.
|
||||
*
|
||||
* This function disables the clock for the CMP.
|
||||
* Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
|
||||
* clock for the CMP, ensure that all the CMP instances are not used.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
*/
|
||||
void CMP_Deinit(CMP_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the CMP module.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param enable Enables or disables the module.
|
||||
*/
|
||||
static inline void CMP_Enable(CMP_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CR1 |= CMP_CR1_EN_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CR1 &= ~CMP_CR1_EN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes the CMP user configuration structure.
|
||||
*
|
||||
* This function initializes the user configuration structure to these default values.
|
||||
* @code
|
||||
* config->enableCmp = true;
|
||||
* config->hysteresisMode = kCMP_HysteresisLevel0;
|
||||
* config->enableHighSpeed = false;
|
||||
* config->enableInvertOutput = false;
|
||||
* config->useUnfilteredOutput = false;
|
||||
* config->enablePinOut = false;
|
||||
* config->enableTriggerMode = false;
|
||||
* @endcode
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void CMP_GetDefaultConfig(cmp_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Sets the input channels for the comparator.
|
||||
*
|
||||
* This function sets the input channels for the comparator.
|
||||
* Note that two input channels cannot be set the same way in the application. When the user selects the same input
|
||||
* from the analog mux to the positive and negative port, the comparator is disabled automatically.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param positiveChannel Positive side input channel number. Available range is 0-7.
|
||||
* @param negativeChannel Negative side input channel number. Available range is 0-7.
|
||||
*/
|
||||
void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Advanced Features
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
|
||||
/*!
|
||||
* @brief Enables/disables the DMA request for rising/falling events.
|
||||
*
|
||||
* This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
|
||||
* the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
|
||||
* if the DMA is disabled.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param enable Enables or disables the feature.
|
||||
*/
|
||||
void CMP_EnableDMA(CMP_Type *base, bool enable);
|
||||
#endif /* FSL_FEATURE_CMP_HAS_DMA */
|
||||
|
||||
#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE
|
||||
/*!
|
||||
* @brief Enables/disables the window mode.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param enable Enables or disables the feature.
|
||||
*/
|
||||
static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CR1 |= CMP_CR1_WE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CR1 &= ~CMP_CR1_WE_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */
|
||||
|
||||
#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE
|
||||
/*!
|
||||
* @brief Enables/disables the pass through mode.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param enable Enables or disables the feature.
|
||||
*/
|
||||
static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->MUXCR |= CMP_MUXCR_PSTM_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->MUXCR &= ~CMP_MUXCR_PSTM_MASK;
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */
|
||||
|
||||
/*!
|
||||
* @brief Configures the filter.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param config Pointer to the configuration structure.
|
||||
*/
|
||||
void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Configures the internal DAC.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param config Pointer to the configuration structure. "NULL" disables the feature.
|
||||
*/
|
||||
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Enables the interrupts.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param mask Mask value for interrupts. See "_cmp_interrupt_enable".
|
||||
*/
|
||||
void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Disables the interrupts.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param mask Mask value for interrupts. See "_cmp_interrupt_enable".
|
||||
*/
|
||||
void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Results
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the status flags.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
*
|
||||
* @return Mask value for the asserted flags. See "_cmp_status_flags".
|
||||
*/
|
||||
uint32_t CMP_GetStatusFlags(CMP_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clears the status flags.
|
||||
*
|
||||
* @param base CMP peripheral base address.
|
||||
* @param mask Mask value for the flags. See "_cmp_status_flags".
|
||||
*/
|
||||
void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask);
|
||||
|
||||
/* @} */
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _FSL_CMP_H_ */
|
||||
166
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_common.c
Normal file
166
platform/vendor_bsp/nxp/MIMXRT1052/drivers/fsl_common.c
Normal file
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|
||||
/*
|
||||
* The Clear BSD License
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted (subject to the limitations in the disclaimer below) provided
|
||||
* that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#define SDK_MEM_MAGIC_NUMBER 12345U
|
||||
|
||||
typedef struct _mem_align_control_block
|
||||
{
|
||||
uint16_t identifier; /*!< Identifier for the memory control block. */
|
||||
uint16_t offset; /*!< offset from aligned adress to real address */
|
||||
} mem_align_cb_t;
|
||||
|
||||
#ifndef __GIC_PRIO_BITS
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||
{
|
||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||
#if defined(__CC_ARM)
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
extern uint32_t Image$$RW_m_data$$Base[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) */
|
||||
uint32_t n;
|
||||
uint32_t ret;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* Copy the vector table from ROM to RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* Point the VTOR to the position of vector table */
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
ret = __VECTOR_RAM[irq + 16];
|
||||
/* make sure the __VECTOR_RAM is noncachable */
|
||||
__VECTOR_RAM[irq + 16] = irqHandler;
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
#endif /* __GIC_PRIO_BITS. */
|
||||
|
||||
#ifndef QN908XC_SERIES
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERSET[index] = 1u << intNumber;
|
||||
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||
}
|
||||
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||
SYSCON->STARTERCLR[index] = 1u << intNumber;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#endif /* QN908XC_SERIES */
|
||||
|
||||
void *SDK_Malloc(size_t size, size_t alignbytes)
|
||||
{
|
||||
mem_align_cb_t *p_cb = NULL;
|
||||
uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
|
||||
void *p_align_addr, *p_addr = malloc(alignedsize);
|
||||
|
||||
if (!p_addr)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
|
||||
|
||||
p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);
|
||||
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
|
||||
p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;
|
||||
|
||||
return (void *)p_align_addr;
|
||||
}
|
||||
|
||||
void SDK_Free(void *ptr)
|
||||
{
|
||||
mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);
|
||||
|
||||
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
free((void *)((uint32_t)ptr - p_cb->offset));
|
||||
}
|
||||
|
||||
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