mtvec exception handler use 4byte alignment

2019-10-09 12:10:19 +08:00
parent 19e65a4bb7
commit 308ad78e44
1 changed files with 1 additions and 1 deletions
--- a/arch/risc-v/bumblebee/gcc/riscv_port_s.S
+++ b/arch/risc-v/bumblebee/gcc/riscv_port_s.S
@@ -7,6 +7,6 @@
 irq_entry:
    j rv32_exception_entry

-.align 6
+.align 2
 trap_entry:
    j rv32_exception_entry