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add risc-v board Sipeed Longan Nano support

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This commit is contained in:
acevest
2019-10-10 18:42:52 +08:00
parent b6af64f40d
commit 41051e1452
17 changed files with 1101 additions and 0 deletions
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18
board/SipeedLonganNano/BSP/Inc/mcu_init.h Normal file
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#ifndef __MCU_INIT_H
#define __MCU_INIT_H
#include "gd32vf103.h"
#include "usart.h"
#define LEDR_GPIO_PORT GPIOC
#define LEDG_GPIO_PORT GPIOA
#define LEDB_GPIO_PORT GPIOA
#define LEDR_PIN GPIO_PIN_13
#define LEDG_PIN GPIO_PIN_1
#define LEDB_PIN GPIO_PIN_2
void board_init();
#endif //__MCU_INIT_H

10
board/SipeedLonganNano/BSP/Inc/usart.h Normal file
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#ifndef __USART_H
#define __USART_H
#define USART0_GPIO_TX_PIN GPIO_PIN_9
#define USART0_GPIO_RX_PIN GPIO_PIN_10
#define USART0_GPIO_PORT GPIOA
void usart0_init(int baud);
#endif // __USART_H

17
board/SipeedLonganNano/BSP/Src/mcu_init.c Normal file
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#include "mcu_init.h"
void board_init() {
SystemInit();
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOC);
gpio_init(LEDR_GPIO_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LEDR_PIN);
gpio_init(LEDG_GPIO_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LEDG_PIN);
gpio_init(LEDB_GPIO_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LEDB_PIN);
gpio_bit_set(LEDR_GPIO_PORT, LEDR_PIN);
gpio_bit_set(LEDG_GPIO_PORT, LEDG_PIN);
gpio_bit_set(LEDB_GPIO_PORT, LEDB_PIN);
}

28
board/SipeedLonganNano/BSP/Src/usart.c Normal file
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#include "gd32vf103.h"
#include "usart.h"
void usart0_init(int baud)
{
/* enable GPIO clock */
rcu_periph_clock_enable(RCU_GPIOA);
/* enable USART0 clock */
rcu_periph_clock_enable(RCU_USART0);
/* connect port to USART0_Tx */
gpio_init(USART0_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, USART0_GPIO_TX_PIN);
/* connect port to USART0_Rx */
gpio_init(USART0_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, USART0_GPIO_RX_PIN);
/* USART0 configure */
usart_deinit(USART0);
usart_baudrate_set(USART0, baud);
usart_word_length_set(USART0, USART_WL_8BIT);
usart_stop_bit_set(USART0, USART_STB_1BIT);
usart_parity_config(USART0, USART_PM_NONE);
usart_hardware_flow_rts_config(USART0, USART_RTS_DISABLE);
usart_hardware_flow_cts_config(USART0, USART_CTS_DISABLE);
usart_receive_config(USART0, USART_RECEIVE_ENABLE);
usart_transmit_config(USART0, USART_TRANSMIT_ENABLE);
usart_enable(USART0);
}

12
board/SipeedLonganNano/README.md Normal file
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#使用openocd调试
需要编译特定的openocd
```git clone https://github.com/riscv-mcu/riscv-openocd.git```
如果用的是Sipeed USB-JTAG/TTL RISC-V Debugger，需要在编译的时候enable ftdi
```
./configure --enable-cmsis-dap --enable-ftdi
```

70
board/SipeedLonganNano/TOS_CONFIG/tos_config.h Normal file
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#ifndef INC_TOS_CONFIG_H_
#define INC_TOS_CONFIG_H_
#include "gd32vf103.h"
#include "stddef.h"
// 配置TencentOS tiny默认支持的最大优先级数量
#define TOS_CFG_TASK_PRIO_MAX 10u
// 配置TencentOS tiny的内核是否开启时间片轮转
#define TOS_CFG_ROUND_ROBIN_EN 0u
// 配置TencentOS tiny是否校验指针合法
#define TOS_CFG_OBJECT_VERIFY 0u
// TencentOS tiny 事件模块功能宏
#define TOS_CFG_EVENT_EN 1u
// 配置TencentOS tiny是否开启动态内存模块
#define TOS_CFG_MMHEAP_EN 1u
// 配置TencentOS tiny动态内存池大小
#define TOS_CFG_MMHEAP_POOL_SIZE 8192
// 配置TencentOS tiny是否开启互斥锁模块
#define TOS_CFG_MUTEX_EN 1u
// 配置TencentOS tiny是否开启队列模块
#define TOS_CFG_QUEUE_EN 1u
// 配置TencentOS tiny是否开启软件定时器模块
#define TOS_CFG_TIMER_EN 0u
// 配置TencentOS tiny是否开启信号量模块
#define TOS_CFG_SEM_EN 1u
#define TOS_CFG_CPU_SYSTICK_PRIO 0xF
#if (TOS_CFG_QUEUE_EN > 0u)
#define TOS_CFG_MSG_EN 1u
#else
#define TOS_CFG_MSG_EN 0u
#endif
// 配置TencentOS tiny消息队列大小
#define TOS_CFG_MSG_POOL_SIZE 10u
// 配置TencentOS tiny空闲任务栈大小
#define TOS_CFG_IDLE_TASK_STK_SIZE 512u
// 配置TencentOS tiny中断栈大小
#define TOS_CFG_IRQ_STK_SIZE 128u
// 配置TencentOS tiny的tick频率
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
// 配置TencentOS tiny CPU频率
// 除4的原因是，Bumblebee内核通过core_clk_aon四分频来更新mtime寄存器
// 具体信息参见《Bumblebee内核简明数据手册》
#define TOS_CFG_CPU_CLOCK (SystemCoreClock/4)
// 配置是否将TIMER配置成函数模式
#define TOS_CFG_TIMER_AS_PROC 1u
#define TOS_CFG_VFS_EN 1u
#define TOS_CFG_MMBLK_EN 1u
#endif /* INC_TOS_CONFIG_H_ */

438
board/SipeedLonganNano/eclipse/hello_world/.cproject Normal file
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1
board/SipeedLonganNano/eclipse/hello_world/.gitignore vendored Normal file
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/Debug/

94
board/SipeedLonganNano/eclipse/hello_world/.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
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3
board/SipeedLonganNano/eclipse/hello_world/.settings/ilg.gnumcueclipse.debug.gdbjtag.openocd.prefs Normal file
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2
board/SipeedLonganNano/eclipse/hello_world/.settings/ilg.gnumcueclipse.managedbuild.cross.riscv.prefs Normal file
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48
board/SipeedLonganNano/eclipse/hello_world/.settings/language.settings.xml Normal file
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2
board/SipeedLonganNano/eclipse/hello_world/.settings/org.eclipse.ltk.core.refactoring.prefs Normal file
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61
board/SipeedLonganNano/eclipse/hello_world/gd32vf103_libopt.h Normal file
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@@ -0,0 +1,61 @@
/*!
\file gd32vf103_libopt.h
\brief library optional for gd32vf103
\version 2019-6-5, V1.0.0, demo for GD32VF103
*/
/*
Copyright (c) 2019, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32VF103_LIBOPT_H
#define GD32VF103_LIBOPT_H
#include "gd32vf103_adc.h"
#include "gd32vf103_bkp.h"
#include "gd32vf103_can.h"
#include "gd32vf103_crc.h"
#include "gd32vf103_dac.h"
#include "gd32vf103_dma.h"
#include "gd32vf103_eclic.h"
#include "gd32vf103_exmc.h"
#include "gd32vf103_exti.h"
#include "gd32vf103_fmc.h"
#include "gd32vf103_gpio.h"
#include "gd32vf103_i2c.h"
#include "gd32vf103_fwdgt.h"
#include "gd32vf103_dbg.h"
#include "gd32vf103_pmu.h"
#include "gd32vf103_rcu.h"
#include "gd32vf103_rtc.h"
#include "gd32vf103_spi.h"
#include "gd32vf103_timer.h"
#include "gd32vf103_usart.h"
#include "gd32vf103_wwdgt.h"
#include "n200_func.h"
#endif /* GD32VF103_LIBOPT_H */

175
board/SipeedLonganNano/eclipse/hello_world/link.lds Normal file
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OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
/* Run in FLASH */
flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K
/* Run in RAM */
/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k
ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K
*/
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash
.ilalign :
{
. = ALIGN(4);
PROVIDE( _ilm_lma = . );
} >flash AT>flash
.ialign :
{
PROVIDE( _ilm = . );
} >flash AT>flash
.text :
{
*(.rodata .rodata.*)
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash
. = ALIGN(4);
PROVIDE (__etext = .);
PROVIDE (_etext = .);/*0x80022c8*/
PROVIDE (etext = .);/*0x80022c8*/
PROVIDE( _eilm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash
. = ALIGN(4);
PROVIDE( _eilm = . );
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash
.data :
{
*(.rdata)
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800);
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . ); /*0X2000,0340*/
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram
}

83
board/SipeedLonganNano/eclipse/hello_world/main.c Normal file
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#include "mcu_init.h"
#include "tos.h"
#define TASK_SIZE 1024
k_task_t k_task_task1;
k_task_t k_task_task2;
uint8_t k_task1_stk[TASK_SIZE];
uint8_t k_task2_stk[TASK_SIZE];
int share = 0xCBA7F9;
k_sem_t sem;
typedef struct {
int port;
int pin;
} Led_t;
Led_t leds[] = {
{ LEDR_GPIO_PORT, LEDR_PIN },
{ LEDG_GPIO_PORT, LEDG_PIN },
{ LEDB_GPIO_PORT, LEDB_PIN }
};
void task1(void *pdata)
{
int task_cnt1 = 0;
while (1) {
printf("hello world from %s cnt: %d\n", __func__, task_cnt1++);
tos_sem_pend(&sem, ~0U);
for(int i=0; i<sizeof(leds)/sizeof(Led_t); i++) {
int on = !(task_cnt1 & (1 << i));
gpio_bit_write(leds[i].port, leds[i].pin, on);
}
}
}
void task2(void *pdata)
{
int task_cnt2 = 0;
while (1) {
share++;
for(int i=0; i<5; i++) {
printf("hello world from %s cnt: %08x\n", __func__, task_cnt2--);
tos_task_delay(200);
}
tos_sem_post(&sem);
}
}
void main(void) {
board_init();
usart0_init(115200);
tos_knl_init();
tos_task_create(&k_task_task1, "task1", task1, NULL, 3, k_task1_stk, TASK_SIZE, 0);
tos_task_create(&k_task_task2, "task2", task2, NULL, 3, k_task2_stk, TASK_SIZE, 0);
k_err_t err = tos_sem_create(&sem, 1);
if (err != K_ERR_NONE) {
goto die;
}
tos_knl_start();
die:
while (1) {
asm("wfi;");
}
}
int _put_char(int ch)
{
usart_data_transmit(USART0, (uint8_t) ch );
while (usart_flag_get(USART0, USART_FLAG_TBE)== RESET){
}
return ch;
}

39
board/SipeedLonganNano/openocd_sipeed_rv_debugger.cfg Normal file
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adapter_khz 1000
interface ftdi
ftdi_device_desc "Dual RS232"
ftdi_vid_pid 0x0403 0x6010
#autoexit true
#interface cmsis-dap
transport select jtag
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
#Reset Stretcher logic on FE310 is ~1 second long
#This doesn't apply if you use
# ftdi_set_signal, but still good to document
#adapter_nsrst_delay 1500
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6d
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME gd32vf103 0x08000000 0 0 0 $_TARGETNAME
riscv expose_csrs 3040-3071
init
#reset
#if {[ info exists pulse_srst]} {
# ftdi_set_signal nSRST 0
# ftdi_set_signal nSRST z
#}
halt
# We must turn on this because otherwise the IDE version debug cannot download the program into flash
#flash protect 0 0 last off