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adjust the order of registers on the stack

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This commit is contained in:
acevest
2019-10-06 15:27:40 +08:00
parent 44f0ac6579
commit e5e905e9bb
7 changed files with 288 additions and 294 deletions
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14
arch/risc-v/bumblebee/gcc/riscv_port.h
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@@ -24,8 +24,22 @@
#define CLINT_MTIMECMP 0x0008 #define CLINT_MTIMECMP 0x0008
#define CLINT_MTIME 0x0000 #define CLINT_MTIME 0x0000
// the bumblebee mstatus register is different
// name bit detail
// INTERRUPT 31 0: exception or nmi, 1 irq
// MINHV 30 reading irq vector table
// MPP 29:28 == mstatus.MPP
// MPIE 27 == mstatus.MPIE
// Reserved 26:24 0
// MPIL 23:16 previous interrupt level
// Reserved 15:12 0
// EXCCODE 11:0 exception code
#define SOC_MCAUSE_EXP_MASK 0x00000FFF
#ifndef __ASSEMBLER__
void port_cpu_init(); void port_cpu_init();
void port_systick_priority_set(uint32_t priority); void port_systick_priority_set(uint32_t priority);
#endif
#endif // _RISCV_PORT_H_ #endif // _RISCV_PORT_H_

168
arch/risc-v/bumblebee/gcc/riscv_port_s.S
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@@ -1,174 +1,12 @@
#include "port.h"
.global irq_entry .global irq_entry
.global trap_entry .global trap_entry
.extern k_curr_task .extern rv32_exception_entry
.extern k_next_task
.align 2 .align 2
irq_entry: irq_entry:
addi sp, sp, -32*REGBYTES j rv32_exception_entry
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
csrr t0, mepc
sw t0, 0*REGBYTES(sp)
csrr t0, mstatus
sw t0, 1*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
csrr a0, mcause
mv a1, sp
// the bumblebee mstatus register is different
// name bit detail
// INTERRUPT 31 0: exception or nmi, 1 irq
// MINHV 30 reading irq vector table
// MPP 29:28 == mstatus.MPP
// MPIE 27 == mstatus.MPIE
// Reserved 26:24 0
// MPIL 23:16 previous interrupt level
// Reserved 15:12 0
// EXCCODE 11:0 exception code
slli a0, a0, 20
srli a0, a0, 20
call cpu_irq_entry
la t0, k_curr_task
la t1, k_next_task
beq t0, t1, irq_restore
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t2, (t0) // t2 = k_curr_task->sp
sw sp, (t2) // k_curr_task->sp = sp
// switch task
lw t1, (t1) // t1 = k_next_task
sw t1, (t0) // k_curr_task = k_next_task
// load new task sp
lw sp, (t1)
irq_restore:
// restore context
lw t0, 0*REGBYTES(sp)
csrw mepc, t0
lw t0, 1*REGBYTES(sp)
csrw mstatus, t0
lw x1, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
lw x16, 16*REGBYTES(sp)
lw x17, 17*REGBYTES(sp)
lw x18, 18*REGBYTES(sp)
lw x19, 19*REGBYTES(sp)
lw x20, 20*REGBYTES(sp)
lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
lw x23, 23*REGBYTES(sp)
lw x24, 24*REGBYTES(sp)
lw x25, 25*REGBYTES(sp)
lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
lw x28, 28*REGBYTES(sp)
lw x29, 29*REGBYTES(sp)
lw x30, 30*REGBYTES(sp)
lw x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
.align 6 .align 6
trap_entry: trap_entry:
addi sp, sp, -32*REGBYTES j rv32_exception_entry
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
csrr t0, mepc
sw t0, 0*REGBYTES(sp)
csrr t0, mstatus
sw t0, 1*REGBYTES(sp)
call cpu_trap_entry
1:
j 1b

69
arch/risc-v/common/include/tos_cpu.h
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@@ -1,40 +1,46 @@
#ifndef _TOS_CPU_H_ #ifndef _TOS_CPU_H_
#define _TOS_CPU_H_ #define _TOS_CPU_H_
typedef struct cpu_context_st { typedef struct cpu_context_st {
union { cpu_data_t s0, x8, fp; };
union { cpu_data_t s1, x9; };
union { cpu_data_t s2, x18; };
union { cpu_data_t s3, x19; };
union { cpu_data_t s4, x20; };
union { cpu_data_t s5, x21; };
union { cpu_data_t s6, x22; };
union { cpu_data_t s7, x23; };
union { cpu_data_t s8, x24; };
union { cpu_data_t s9, x25; };
union { cpu_data_t s10,x26; };
union { cpu_data_t s11,x27; };
// caller save
union { cpu_data_t ra, x1; };
union { cpu_data_t gp, x3; };
union { cpu_data_t tp, x4; };
union { cpu_data_t t0, x5; };
union { cpu_data_t t1, x6; };
union { cpu_data_t t2, x7; };
union { cpu_data_t t3, x28; };
union { cpu_data_t t4, x29; };
union { cpu_data_t t5, x30; };
union { cpu_data_t t6, x31; };
union { cpu_data_t a0, x10; };
union { cpu_data_t a1, x11; };
union { cpu_data_t a2, x12; };
union { cpu_data_t a3, x13; };
union { cpu_data_t a4, x14; };
union { cpu_data_t a5, x15; };
union { cpu_data_t a6, x16; };
union { cpu_data_t a7, x17; };
cpu_data_t epc; cpu_data_t epc;
cpu_data_t mstatus; cpu_data_t mstatus;
union { cpu_data_t x1, ra; };
union { cpu_data_t x3, gp; };
union { cpu_data_t x4, tp; };
union { cpu_data_t x5, t0; };
union { cpu_data_t x6, t1; };
union { cpu_data_t x7, t2; };
union { cpu_data_t x8, s0, fp; };
union { cpu_data_t x9, s1; };
union { cpu_data_t x10, a0; };
union { cpu_data_t x11, a1; };
union { cpu_data_t x12, a2; };
union { cpu_data_t x13, a3; };
union { cpu_data_t x14, a4; };
union { cpu_data_t x15, a5; };
union { cpu_data_t x16, a6; };
union { cpu_data_t x17, a7; };
union { cpu_data_t x18, s2; };
union { cpu_data_t x19, s3; };
union { cpu_data_t x20, s4; };
union { cpu_data_t x21, s5; };
union { cpu_data_t x22, s6; };
union { cpu_data_t x23, s7; };
union { cpu_data_t x24, s8; };
union { cpu_data_t x25, s9; };
union { cpu_data_t x26, s10; };
union { cpu_data_t x27, s11; };
union { cpu_data_t x28, t3; };
union { cpu_data_t x29, t4; };
union { cpu_data_t x30, t5; };
union { cpu_data_t x31, t6; };
} cpu_context_t; } cpu_context_t;
__API__ uint32_t tos_cpu_clz(uint32_t val); __API__ uint32_t tos_cpu_clz(uint32_t val);
@@ -115,4 +121,5 @@ __KERNEL__ void cpu_standby_mode_enter(void);
tos_cpu_cpsr_restore(cpu_cpsr); \ tos_cpu_cpsr_restore(cpu_cpsr); \
} while (0) } while (0)
#endif /* _TOS_CPU_H_ */ #endif /* _TOS_CPU_H_ */

2
arch/risc-v/common/tos_cpu.c
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@@ -172,3 +172,5 @@ __API__ uint32_t tos_cpu_clz(uint32_t val)
return (nbr_lead_zeros); return (nbr_lead_zeros);
} }

321
arch/risc-v/rv32i/gcc/port_s.S
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@@ -1,3 +1,5 @@
#include "riscv_port.h"
.global port_int_disable .global port_int_disable
.global port_int_enable .global port_int_enable
@@ -82,42 +84,45 @@ port_sched_start:
sw t1, (t0) sw t1, (t0)
// restore context // restore context
lw t0, 0*REGBYTES(sp) lw t0, 30*REGBYTES(sp)
csrw mepc, t0 csrw mepc, t0
lw t0, 1*REGBYTES(sp) lw t0, 31*REGBYTES(sp)
csrw mstatus, t0 csrw mstatus, t0
lw x1, 2*REGBYTES(sp) lw s0, 0*REGBYTES(sp)
lw x3, 3*REGBYTES(sp) lw s1, 1*REGBYTES(sp)
lw x4, 4*REGBYTES(sp) lw s2, 2*REGBYTES(sp)
lw x5, 5*REGBYTES(sp) lw s3, 3*REGBYTES(sp)
lw x6, 6*REGBYTES(sp) lw s4, 4*REGBYTES(sp)
lw x7, 7*REGBYTES(sp) lw s5, 5*REGBYTES(sp)
lw x8, 8*REGBYTES(sp) lw s6, 6*REGBYTES(sp)
lw x9, 9*REGBYTES(sp) lw s7, 7*REGBYTES(sp)
lw x10, 10*REGBYTES(sp) lw s8, 8*REGBYTES(sp)
lw x11, 11*REGBYTES(sp) lw s9, 9*REGBYTES(sp)
lw x12, 12*REGBYTES(sp) lw s10, 10*REGBYTES(sp)
lw x13, 13*REGBYTES(sp) lw s11, 11*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp) // caller save
lw x16, 16*REGBYTES(sp) lw ra, 12*REGBYTES(sp)
lw x17, 17*REGBYTES(sp) lw gp, 13*REGBYTES(sp)
lw x18, 18*REGBYTES(sp) lw tp, 14*REGBYTES(sp)
lw x19, 19*REGBYTES(sp) lw t0, 15*REGBYTES(sp)
lw x20, 20*REGBYTES(sp) lw t1, 16*REGBYTES(sp)
lw x21, 21*REGBYTES(sp) lw t2, 17*REGBYTES(sp)
lw x22, 22*REGBYTES(sp) lw t3, 18*REGBYTES(sp)
lw x23, 23*REGBYTES(sp) lw t4, 19*REGBYTES(sp)
lw x24, 24*REGBYTES(sp) lw t5, 20*REGBYTES(sp)
lw x25, 25*REGBYTES(sp) lw t6, 21*REGBYTES(sp)
lw x26, 26*REGBYTES(sp) lw a0, 22*REGBYTES(sp)
lw x27, 27*REGBYTES(sp) lw a1, 23*REGBYTES(sp)
lw x28, 28*REGBYTES(sp) lw a2, 24*REGBYTES(sp)
lw x29, 29*REGBYTES(sp) lw a3, 25*REGBYTES(sp)
lw x30, 30*REGBYTES(sp) lw a4, 26*REGBYTES(sp)
lw x31, 31*REGBYTES(sp) lw a5, 27*REGBYTES(sp)
lw a6, 28*REGBYTES(sp)
lw a7, 29*REGBYTES(sp)
addi sp, sp, 32*REGBYTES addi sp, sp, 32*REGBYTES
@@ -128,44 +133,46 @@ port_sched_start:
.type port_context_switch, %function .type port_context_switch, %function
port_context_switch: port_context_switch:
addi sp, sp, -32*REGBYTES addi sp, sp, -32*REGBYTES
sw x1, 2*REGBYTES(sp)
sw x3, 3*REGBYTES(sp)
sw x4, 4*REGBYTES(sp)
sw x5, 5*REGBYTES(sp)
sw x6, 6*REGBYTES(sp)
sw x7, 7*REGBYTES(sp)
sw x8, 8*REGBYTES(sp)
sw x9, 9*REGBYTES(sp)
sw x10, 10*REGBYTES(sp)
sw x11, 11*REGBYTES(sp)
sw x12, 12*REGBYTES(sp)
sw x13, 13*REGBYTES(sp)
sw x14, 14*REGBYTES(sp)
sw x15, 15*REGBYTES(sp)
sw x16, 16*REGBYTES(sp)
sw x17, 17*REGBYTES(sp)
sw x18, 18*REGBYTES(sp)
sw x19, 19*REGBYTES(sp)
sw x20, 20*REGBYTES(sp)
sw x21, 21*REGBYTES(sp)
sw x22, 22*REGBYTES(sp)
sw x23, 23*REGBYTES(sp)
sw x24, 24*REGBYTES(sp)
sw x25, 25*REGBYTES(sp)
sw x26, 26*REGBYTES(sp)
sw x27, 27*REGBYTES(sp)
sw x28, 28*REGBYTES(sp)
sw x29, 29*REGBYTES(sp)
sw x30, 30*REGBYTES(sp)
sw x31, 31*REGBYTES(sp)
sw s0, 0*REGBYTES(sp)
sw s1, 1*REGBYTES(sp)
sw s2, 2*REGBYTES(sp)
sw s3, 3*REGBYTES(sp)
sw s4, 4*REGBYTES(sp)
sw s5, 5*REGBYTES(sp)
sw s6, 6*REGBYTES(sp)
sw s7, 7*REGBYTES(sp)
sw s8, 8*REGBYTES(sp)
sw s9, 9*REGBYTES(sp)
sw s10, 10*REGBYTES(sp)
sw s11, 11*REGBYTES(sp)
sw ra, 0*REGBYTES(sp) // caller save
sw ra, 12*REGBYTES(sp)
sw gp, 13*REGBYTES(sp)
sw tp, 14*REGBYTES(sp)
sw t0, 15*REGBYTES(sp)
sw t1, 16*REGBYTES(sp)
sw t2, 17*REGBYTES(sp)
sw t3, 18*REGBYTES(sp)
sw t4, 19*REGBYTES(sp)
sw t5, 20*REGBYTES(sp)
sw t6, 21*REGBYTES(sp)
sw a0, 22*REGBYTES(sp)
sw a1, 23*REGBYTES(sp)
sw a2, 24*REGBYTES(sp)
sw a3, 25*REGBYTES(sp)
sw a4, 26*REGBYTES(sp)
sw a5, 27*REGBYTES(sp)
sw a6, 28*REGBYTES(sp)
sw a7, 29*REGBYTES(sp)
sw ra, 30*REGBYTES(sp)
csrr t0, mstatus csrr t0, mstatus
li t1, MSTATUS_MPP li t1, MSTATUS_MPP
or t0, t0, t1 or t0, t0, t1
sw t0, 1*REGBYTES(sp) sw t0, 31*REGBYTES(sp)
// save sp to k_curr_task.sp // save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task la t0, k_curr_task // t0 = &k_curr_task
@@ -182,43 +189,165 @@ port_context_switch:
lw sp, (t1) lw sp, (t1)
// restore context // restore context
lw t0, 0*REGBYTES(sp) lw t0, 30*REGBYTES(sp)
csrw mepc, t0 csrw mepc, t0
lw t0, 1*REGBYTES(sp) lw t0, 31*REGBYTES(sp)
csrw mstatus, t0 csrw mstatus, t0
lw x1, 2*REGBYTES(sp)
lw x3, 3*REGBYTES(sp)
lw x4, 4*REGBYTES(sp)
lw x5, 5*REGBYTES(sp)
lw x6, 6*REGBYTES(sp)
lw x7, 7*REGBYTES(sp)
lw x8, 8*REGBYTES(sp)
lw x9, 9*REGBYTES(sp)
lw x10, 10*REGBYTES(sp)
lw x11, 11*REGBYTES(sp)
lw x12, 12*REGBYTES(sp)
lw x13, 13*REGBYTES(sp)
lw x14, 14*REGBYTES(sp)
lw x15, 15*REGBYTES(sp)
lw x16, 16*REGBYTES(sp)
lw x17, 17*REGBYTES(sp)
lw x18, 18*REGBYTES(sp)
lw x19, 19*REGBYTES(sp)
lw x20, 20*REGBYTES(sp)
lw x21, 21*REGBYTES(sp)
lw x22, 22*REGBYTES(sp)
lw x23, 23*REGBYTES(sp)
lw x24, 24*REGBYTES(sp)
lw x25, 25*REGBYTES(sp)
lw x26, 26*REGBYTES(sp)
lw x27, 27*REGBYTES(sp)
lw x28, 28*REGBYTES(sp)
lw x29, 29*REGBYTES(sp)
lw x30, 30*REGBYTES(sp)
lw x31, 31*REGBYTES(sp)
lw s0, 0*REGBYTES(sp)
lw s1, 1*REGBYTES(sp)
lw s2, 2*REGBYTES(sp)
lw s3, 3*REGBYTES(sp)
lw s4, 4*REGBYTES(sp)
lw s5, 5*REGBYTES(sp)
lw s6, 6*REGBYTES(sp)
lw s7, 7*REGBYTES(sp)
lw s8, 8*REGBYTES(sp)
lw s9, 9*REGBYTES(sp)
lw s10, 10*REGBYTES(sp)
lw s11, 11*REGBYTES(sp)
// caller save
lw ra, 12*REGBYTES(sp)
lw gp, 13*REGBYTES(sp)
lw tp, 14*REGBYTES(sp)
lw t0, 15*REGBYTES(sp)
lw t1, 16*REGBYTES(sp)
lw t2, 17*REGBYTES(sp)
lw t3, 18*REGBYTES(sp)
lw t4, 19*REGBYTES(sp)
lw t5, 20*REGBYTES(sp)
lw t6, 21*REGBYTES(sp)
lw a0, 22*REGBYTES(sp)
lw a1, 23*REGBYTES(sp)
lw a2, 24*REGBYTES(sp)
lw a3, 25*REGBYTES(sp)
lw a4, 26*REGBYTES(sp)
lw a5, 27*REGBYTES(sp)
lw a6, 28*REGBYTES(sp)
lw a7, 29*REGBYTES(sp)
addi sp, sp, 32*REGBYTES addi sp, sp, 32*REGBYTES
mret mret
.align 2
.global rv32_exception_entry
rv32_exception_entry:
addi sp, sp, -32*REGBYTES
sw s0, 0*REGBYTES(sp)
sw s1, 1*REGBYTES(sp)
sw s2, 2*REGBYTES(sp)
sw s3, 3*REGBYTES(sp)
sw s4, 4*REGBYTES(sp)
sw s5, 5*REGBYTES(sp)
sw s6, 6*REGBYTES(sp)
sw s7, 7*REGBYTES(sp)
sw s8, 8*REGBYTES(sp)
sw s9, 9*REGBYTES(sp)
sw s10, 10*REGBYTES(sp)
sw s11, 11*REGBYTES(sp)
// caller save
sw ra, 12*REGBYTES(sp)
sw gp, 13*REGBYTES(sp)
sw tp, 14*REGBYTES(sp)
sw t0, 15*REGBYTES(sp)
sw t1, 16*REGBYTES(sp)
sw t2, 17*REGBYTES(sp)
sw t3, 18*REGBYTES(sp)
sw t4, 19*REGBYTES(sp)
sw t5, 20*REGBYTES(sp)
sw t6, 21*REGBYTES(sp)
sw a0, 22*REGBYTES(sp)
sw a1, 23*REGBYTES(sp)
sw a2, 24*REGBYTES(sp)
sw a3, 25*REGBYTES(sp)
sw a4, 26*REGBYTES(sp)
sw a5, 27*REGBYTES(sp)
sw a6, 28*REGBYTES(sp)
sw a7, 29*REGBYTES(sp)
csrr t0, mepc
sw t0, 30*REGBYTES(sp)
csrr t0, mstatus
sw t0, 31*REGBYTES(sp)
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t1, (t0)
sw sp, (t1)
csrr a0, mcause
mv a1, sp
li t0, SOC_MCAUSE_EXP_MASK
and a0, a0, t0
call cpu_irq_entry
la t0, k_curr_task
la t1, k_next_task
beq t0, t1, irq_restore
// save sp to k_curr_task.sp
la t0, k_curr_task // t0 = &k_curr_task
lw t2, (t0) // t2 = k_curr_task->sp
sw sp, (t2) // k_curr_task->sp = sp
// switch task
lw t1, (t1) // t1 = k_next_task
sw t1, (t0) // k_curr_task = k_next_task
// load new task sp
lw sp, (t1)
irq_restore:
// restore context
lw t0, 30*REGBYTES(sp)
csrw mepc, t0
lw t0, 31*REGBYTES(sp)
csrw mstatus, t0
lw s0, 0*REGBYTES(sp)
lw s1, 1*REGBYTES(sp)
lw s2, 2*REGBYTES(sp)
lw s3, 3*REGBYTES(sp)
lw s4, 4*REGBYTES(sp)
lw s5, 5*REGBYTES(sp)
lw s6, 6*REGBYTES(sp)
lw s7, 7*REGBYTES(sp)
lw s8, 8*REGBYTES(sp)
lw s9, 9*REGBYTES(sp)
lw s10, 10*REGBYTES(sp)
lw s11, 11*REGBYTES(sp)
// caller save
lw ra, 12*REGBYTES(sp)
lw gp, 13*REGBYTES(sp)
lw tp, 14*REGBYTES(sp)
lw t0, 15*REGBYTES(sp)
lw t1, 16*REGBYTES(sp)
lw t2, 17*REGBYTES(sp)
lw t3, 18*REGBYTES(sp)
lw t4, 19*REGBYTES(sp)
lw t5, 20*REGBYTES(sp)
lw t6, 21*REGBYTES(sp)
lw a0, 22*REGBYTES(sp)
lw a1, 23*REGBYTES(sp)
lw a2, 24*REGBYTES(sp)
lw a3, 25*REGBYTES(sp)
lw a4, 26*REGBYTES(sp)
lw a5, 27*REGBYTES(sp)
lw a6, 28*REGBYTES(sp)
lw a7, 29*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret

6
arch/risc-v/spike/gcc/riscv_port.h
View File

@@ -23,8 +23,12 @@
#define CLINT_MTIMECMP 0x4000 #define CLINT_MTIMECMP 0x4000
#define CLINT_MTIME 0xBFF8 #define CLINT_MTIME 0xBFF8
#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF
#ifndef __ASSEMBLER__
void port_cpu_init(); void port_cpu_init();
void port_systick_priority_set(uint32_t priority); void port_systick_priority_set(uint32_t priority);
#endif /* __ASSEMBLER__ */
#endif // _RISCV_PORT_H_ #endif /* _RISCV_PORT_H_ */

2
board/GD32VF103C_START/eclipse/hello_world/.cproject
View File

@@ -105,7 +105,7 @@
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/GD32VF103_Firmware_Library/RISCV/drivers}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/GD32VF103_Firmware_Library/RISCV/drivers}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/rv32i}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/hello_world/TencentOS_tiny/arch/risc-v/bumblebee}&quot;"/>
</option> </option>