acevest
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f4d5ff70b2
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bumblebee use eclic_mtip_handler as systick handler
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2019-10-16 18:16:42 +08:00 |
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acevest
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f41e287c2a
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risc-v support all irq handler
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2019-10-16 18:10:03 +08:00 |
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acevest
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c17df06ff7
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reduce two instructions in risc-v irq handler
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2019-10-09 19:05:20 +08:00 |
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supowang
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7f001b4230
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add license for arch
add license for arch
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2019-10-09 15:52:17 +08:00 |
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acevest
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308ad78e44
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mtvec exception handler use 4byte alignment
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2019-10-09 12:10:19 +08:00 |
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acevest
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ae3ada8dfe
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reduce one instruction when switch to irq stack
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2019-10-08 20:44:58 +08:00 |
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acevest
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e5e905e9bb
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adjust the order of registers on the stack
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2019-10-08 14:41:30 +08:00 |
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acevest
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44f0ac6579
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irq context switch do not use flag variable anymore
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2019-10-08 14:41:30 +08:00 |
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acevest
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2fdc9f600c
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fix bumblebee trap_entry memory address alignment problem
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2019-10-08 14:41:30 +08:00 |
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acevest
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2d419440f3
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divide bumblebee and spike irq trap entry code
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2019-10-08 14:41:30 +08:00 |
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acevest
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a52bb94ed2
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initialize the clock tree of GD32VF103C_START to 108MHz
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2019-10-03 15:01:46 +08:00 |
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acevest
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384a4f6ef3
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enable set systick priority for bumblebee
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2019-09-26 22:11:24 +08:00 |
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acevest
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f03535a484
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detach risc-v cpu bumblebee level code from gd32v lib
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2019-09-26 22:11:07 +08:00 |
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acevest
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b1b2d1eabc
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organize risc-v code for spike and bumblebee
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2019-09-25 21:53:27 +08:00 |
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