5 Commits

Author	SHA1	Message	Date
acevest	308ad78e44	mtvec exception handler use 4byte alignment	2019-10-09 12:10:19 +08:00
acevest	e5e905e9bb	adjust the order of registers on the stack	2019-10-08 14:41:30 +08:00
acevest	44f0ac6579	irq context switch do not use flag variable anymore	2019-10-08 14:41:30 +08:00
acevest	2fdc9f600c	fix bumblebee trap_entry memory address alignment problem	2019-10-08 14:41:30 +08:00
acevest	2d419440f3	divide bumblebee and spike irq trap entry code	2019-10-08 14:41:30 +08:00