acevest
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c17df06ff7
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reduce two instructions in risc-v irq handler
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2019-10-09 19:05:20 +08:00 |
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acevest
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308ad78e44
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mtvec exception handler use 4byte alignment
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2019-10-09 12:10:19 +08:00 |
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acevest
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e5e905e9bb
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adjust the order of registers on the stack
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2019-10-08 14:41:30 +08:00 |
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acevest
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44f0ac6579
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irq context switch do not use flag variable anymore
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2019-10-08 14:41:30 +08:00 |
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acevest
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2fdc9f600c
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fix bumblebee trap_entry memory address alignment problem
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2019-10-08 14:41:30 +08:00 |
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acevest
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2d419440f3
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divide bumblebee and spike irq trap entry code
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2019-10-08 14:41:30 +08:00 |
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