first commit for opensource

first commit for opensource

platform/vendor_bsp/TI/MSP432P4xx/adc14.c

@@ -0,0 +1,755 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* DriverLib Includes */
+#include <adc14.h>
+#include <debug.h>
+#include <interrupt.h>
+
+/* Statics */
+static volatile uint32_t* const _ctlRegs[32] =
+{ &ADC14->MCTL[0], &ADC14->MCTL[1], &ADC14->MCTL[2], &ADC14->MCTL[3],
+        &ADC14->MCTL[4], &ADC14->MCTL[5], &ADC14->MCTL[6], &ADC14->MCTL[7],
+        &ADC14->MCTL[8], &ADC14->MCTL[9], &ADC14->MCTL[10],
+        &ADC14->MCTL[11], &ADC14->MCTL[12], &ADC14->MCTL[13],
+        &ADC14->MCTL[14], &ADC14->MCTL[15], &ADC14->MCTL[16],
+        &ADC14->MCTL[17], &ADC14->MCTL[18], &ADC14->MCTL[19],
+        &ADC14->MCTL[20], &ADC14->MCTL[21], &ADC14->MCTL[22],
+        &ADC14->MCTL[23], &ADC14->MCTL[24], &ADC14->MCTL[25],
+        &ADC14->MCTL[26], &ADC14->MCTL[27], &ADC14->MCTL[28],
+        &ADC14->MCTL[29], &ADC14->MCTL[30], &ADC14->MCTL[31] };
+
+static uint_fast8_t _getIndexForMemRegister(uint32_t reg)
+{
+    switch (reg)
+    {
+    case ADC_MEM0:
+        return 0;
+    case ADC_MEM1:
+        return 1;
+    case ADC_MEM2:
+        return 2;
+    case ADC_MEM3:
+        return 3;
+    case ADC_MEM4:
+        return 4;
+    case ADC_MEM5:
+        return 5;
+    case ADC_MEM6:
+        return 6;
+    case ADC_MEM7:
+        return 7;
+    case ADC_MEM8:
+        return 8;
+    case ADC_MEM9:
+        return 9;
+    case ADC_MEM10:
+        return 10;
+    case ADC_MEM11:
+        return 11;
+    case ADC_MEM12:
+        return 12;
+    case ADC_MEM13:
+        return 13;
+    case ADC_MEM14:
+        return 14;
+    case ADC_MEM15:
+        return 15;
+    case ADC_MEM16:
+        return 16;
+    case ADC_MEM17:
+        return 17;
+    case ADC_MEM18:
+        return 18;
+    case ADC_MEM19:
+        return 19;
+    case ADC_MEM20:
+        return 20;
+    case ADC_MEM21:
+        return 21;
+    case ADC_MEM22:
+        return 22;
+    case ADC_MEM23:
+        return 23;
+    case ADC_MEM24:
+        return 24;
+    case ADC_MEM25:
+        return 25;
+    case ADC_MEM26:
+        return 26;
+    case ADC_MEM27:
+        return 27;
+    case ADC_MEM28:
+        return 28;
+    case ADC_MEM29:
+        return 29;
+    case ADC_MEM30:
+        return 30;
+    case ADC_MEM31:
+        return 31;
+    default:
+        ASSERT(false);
+        return ADC_INVALID_MEM;
+
+    }
+}
+
+//*****************************************************************************
+//
+//!
+//! Returns a boolean value that tells if conversion is active/running or is
+//! not acMSP432 ted.
+//!
+//! Originally a public function, but moved to static. External customers should
+//! use the ADC14_isBusy function.
+//!
+//! \return true if conversion is active, false otherwise
+//
+//*****************************************************************************
+static bool ADCIsConversionRunning(void)
+{
+    return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
+}
+
+void ADC14_enableModule(void)
+{
+    BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 1;
+}
+
+bool ADC14_disableModule(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 0;
+
+    return true;
+}
+
+bool ADC14_enableSampleTimer(uint32_t multiSampleConvert)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 1;
+
+    if (multiSampleConvert == ADC_MANUAL_ITERATION)
+    {
+        BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 0;
+    } else
+    {
+        BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 1;
+    }
+
+    return true;
+}
+
+bool ADC14_disableSampleTimer(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 0;
+
+    return true;
+}
+
+bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider,
+        uint32_t clockDivider, uint32_t internalChannelMask)
+{
+    ASSERT(
+            clockSource == ADC_CLOCKSOURCE_ADCOSC
+            || clockSource == ADC_CLOCKSOURCE_SYSOSC
+            || clockSource == ADC_CLOCKSOURCE_ACLK
+            || clockSource == ADC_CLOCKSOURCE_MCLK
+            || clockSource == ADC_CLOCKSOURCE_SMCLK
+            || clockSource == ADC_CLOCKSOURCE_HSMCLK);
+
+    ASSERT(
+            clockPredivider == ADC_PREDIVIDER_1
+            || clockPredivider == ADC_PREDIVIDER_4
+            || clockPredivider == ADC_PREDIVIDER_32
+            || clockPredivider == ADC_PREDIVIDER_64);
+
+    ASSERT(
+            clockDivider == ADC_DIVIDER_1 || clockDivider == ADC_DIVIDER_2
+            || clockDivider == ADC_DIVIDER_3
+            || clockDivider == ADC_DIVIDER_4
+            || clockDivider == ADC_DIVIDER_5
+            || clockDivider == ADC_DIVIDER_6
+            || clockDivider == ADC_DIVIDER_7
+            || clockDivider == ADC_DIVIDER_8);
+
+    ASSERT(
+            !(internalChannelMask
+                    & ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1
+                            | ADC_MAPINTCH0 | ADC_TEMPSENSEMAP | ADC_BATTMAP)));
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    ADC14->CTL0 = (ADC14->CTL0
+            & ~(ADC14_CTL0_PDIV_MASK | ADC14_CTL0_DIV_MASK | ADC14_CTL0_SSEL_MASK))
+            | clockDivider | clockPredivider | clockSource;
+
+    ADC14->CTL1 = (ADC14->CTL1
+            & ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0
+                    | ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask;
+
+    return true;
+}
+
+void ADC14_setResolution(uint32_t resolution)
+{
+    ASSERT(
+            resolution == ADC_8BIT || resolution == ADC_10BIT
+            || resolution == ADC_12BIT || resolution == ADC_14BIT);
+
+    ADC14->CTL1 = (ADC14->CTL1 & ~ADC14_CTL1_RES_MASK) |  resolution;
+}
+
+uint_fast32_t ADC14_getResolution(void)
+{
+    return ADC14->CTL1 & ADC14_CTL1_RES_MASK;
+}
+
+bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal)
+{
+
+    ASSERT(
+            source == ADC_TRIGGER_ADCSC || source == ADC_TRIGGER_SOURCE1
+            || source == ADC_TRIGGER_SOURCE2
+            || source == ADC_TRIGGER_SOURCE3
+            || source == ADC_TRIGGER_SOURCE4
+            || source == ADC_TRIGGER_SOURCE5
+            || source == ADC_TRIGGER_SOURCE6
+            || source == ADC_TRIGGER_SOURCE7);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    if (invertSignal)
+    {
+        ADC14->CTL0 = (ADC14->CTL0
+                & ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source
+                | ADC14_CTL0_ISSH;
+    } else
+    {
+        ADC14->CTL0 = (ADC14->CTL0
+                & ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source;
+    }
+
+    return true;
+}
+
+bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth,
+        uint32_t secondPulseWidth)
+{
+    ASSERT(
+            firstPulseWidth == ADC_PULSE_WIDTH_4
+            || firstPulseWidth == ADC_PULSE_WIDTH_8
+            || firstPulseWidth == ADC_PULSE_WIDTH_16
+            || firstPulseWidth == ADC_PULSE_WIDTH_32
+            || firstPulseWidth == ADC_PULSE_WIDTH_64
+            || firstPulseWidth == ADC_PULSE_WIDTH_96
+            || firstPulseWidth == ADC_PULSE_WIDTH_128
+            || firstPulseWidth == ADC_PULSE_WIDTH_192);
+
+    ASSERT(
+            secondPulseWidth == ADC_PULSE_WIDTH_4
+            || secondPulseWidth == ADC_PULSE_WIDTH_8
+            || secondPulseWidth == ADC_PULSE_WIDTH_16
+            || secondPulseWidth == ADC_PULSE_WIDTH_32
+            || secondPulseWidth == ADC_PULSE_WIDTH_64
+            || secondPulseWidth == ADC_PULSE_WIDTH_96
+            || secondPulseWidth == ADC_PULSE_WIDTH_128
+            || secondPulseWidth == ADC_PULSE_WIDTH_192);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    ADC14->CTL0 = (ADC14->CTL0
+            & ~(ADC14_CTL0_SHT0_MASK | ADC14_CTL0_SHT1_MASK)) | secondPulseWidth
+            | (firstPulseWidth >> 4);
+
+    return true;
+}
+
+bool ADC14_configureMultiSequenceMode(uint32_t memoryStart, uint32_t memoryEnd,
+bool repeatMode)
+{
+    uint32_t ii;
+
+    ASSERT(
+            _getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
+            && _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    /* Clearing out any lingering EOS */
+    for (ii = 0; ii < 32; ii++)
+    {
+        BITBAND_PERI(*(_ctlRegs[ii]), ADC14_MCTLN_EOS_OFS) = 0;
+    }
+
+    /* Setting Start/Stop locations */
+    BITBAND_PERI(
+            (*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])),
+            ADC14_MCTLN_EOS_OFS) = 1;
+
+    ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
+                    | (_getIndexForMemRegister(memoryStart) << 16);
+
+    /* Setting multiple sample mode */
+    if (!repeatMode)
+    {
+        ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+                | (ADC14_CTL0_CONSEQ_1);
+    } else
+    {
+        ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+                | (ADC14_CTL0_CONSEQ_3);
+    }
+
+    return true;
+}
+
+bool ADC14_configureSingleSampleMode(uint32_t memoryDestination,
+bool repeatMode)
+{
+    ASSERT(_getIndexForMemRegister(memoryDestination) != 32);
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    /* Setting the destination register */
+    ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK))
+            | (_getIndexForMemRegister(memoryDestination) << 16);
+
+    /* Setting single sample mode */
+    if (!repeatMode)
+    {
+        ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+                | (ADC14_CTL0_CONSEQ_0);
+    } else
+    {
+        ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK))
+                | (ADC14_CTL0_CONSEQ_2);
+    }
+
+    return true;
+}
+
+bool ADC14_enableConversion(void)
+{
+    if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
+        return false;
+
+    ADC14->CTL0 |= (ADC14_CTL0_ENC);
+
+    return true;
+}
+
+bool ADC14_toggleConversionTrigger(void)
+{
+    if (!BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS))
+        return false;
+
+    if (BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS))
+    {
+        BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 0;
+    } else
+    {
+        BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 1;
+    }
+
+    return true;
+}
+
+void ADC14_disableConversion(void)
+{
+    ADC14->CTL0 &= ~(ADC14_CTL0_SC | ADC14_CTL0_ENC);
+}
+
+bool ADC14_isBusy(void)
+{
+    return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS);
+}
+
+bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect,
+        uint32_t channelSelect, bool differntialMode)
+{
+    uint32_t currentReg, ii;
+    uint32_t *curReg;
+
+    /* Initialization */
+    ii = 1;
+    currentReg = 0x01;
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    while (memorySelect != 0)
+    {
+        if (!(memorySelect & ii))
+        {
+            ii = ii << 1;
+            continue;
+        }
+
+        currentReg = memorySelect & ii;
+        memorySelect &= ~ii;
+        ii = ii << 1;
+
+        curReg = (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
+
+        if (differntialMode)
+        {
+            (*curReg) = ((*curReg)
+                    & ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
+                            | ADC14_MCTLN_DIF))
+                    | (channelSelect | refSelect | ADC14_MCTLN_DIF);
+        } else
+        {
+            (*curReg) = ((*curReg)
+                    & ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK
+                            | ADC14_MCTLN_DIF)) | (channelSelect | refSelect);
+        }
+
+    }
+
+    return true;
+}
+
+bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect)
+{
+    uint32_t currentReg, ii;
+    uint32_t *curRegPoint;
+
+    /* Initialization */
+    ii = 1;
+    currentReg = 0x01;
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    while (memorySelect != 0)
+    {
+        if (!(memorySelect & ii))
+        {
+            ii = ii << 1;
+            continue;
+        }
+
+        currentReg = memorySelect & ii;
+        memorySelect &= ~ii;
+        ii = ii << 1;
+
+        curRegPoint =
+                (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)];
+
+        if (windowSelect == ADC_COMP_WINDOW0)
+        {
+            (*curRegPoint) = ((*curRegPoint)
+                    & ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH))
+                    | (ADC14_MCTLN_WINC);
+        } else if (windowSelect == ADC_COMP_WINDOW1)
+        {
+            (*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH;
+        }
+
+    }
+
+    return true;
+}
+
+bool ADC14_disableComparatorWindow(uint32_t memorySelect)
+{
+    uint32_t currentReg, ii;
+
+    /* Initialization */
+    ii = 1;
+    currentReg = 0x01;
+
+    if (ADCIsConversionRunning())
+        return false;
+
+    while (memorySelect != 0)
+    {
+        if (!(memorySelect & ii))
+        {
+            ii = ii << 1;
+            continue;
+        }
+
+        currentReg = memorySelect & ii;
+        memorySelect &= ~ii;
+        ii = ii << 1;
+
+        (*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &=
+                ~ADC14_MCTLN_WINC;
+
+    }
+
+    return true;
+}
+
+bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high)
+{
+    if (ADCIsConversionRunning())
+        return false;
+        
+    if(BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS))
+    {
+        low = ((low << 2) | (0x8000 & low)) & 0xFFFC;
+        high = ((high << 2) | (0x8000 & high)) & 0xFFFC;
+    }
+
+    if (window == ADC_COMP_WINDOW0)
+    {
+        ADC14->HI0 = (high);
+        ADC14->LO0 = (low);
+
+    } else if (window == ADC_COMP_WINDOW1)
+    {
+        ADC14->HI1 = (high);
+        ADC14->LO1 = (low);
+
+    } else
+    {
+        ASSERT(false);
+        return false;
+    }
+
+    return true;
+}
+
+bool ADC14_setResultFormat(uint32_t resultFormat)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    if (resultFormat == ADC_UNSIGNED_BINARY)
+    {
+        BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 0;
+    } else if (resultFormat == ADC_SIGNED_BINARY)
+    {
+        BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 1;
+    } else
+    {
+        ASSERT(false);
+    }
+
+    return true;
+}
+
+uint_fast16_t ADC14_getResult(uint32_t memorySelect)
+{
+    return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)]
+            + 0x20));
+}
+
+void ADC14_getMultiSequenceResult(uint16_t* res)
+{
+    uint32_t *startAddr, *curAddr;
+    uint32_t ii;
+
+    startAddr = (uint32_t*) _ctlRegs[(ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK)
+            >> 16];
+
+    curAddr = startAddr;
+
+    for (ii = 0; ii < 32; ii++)
+    {
+        res[ii] = *((uint16_t*)(curAddr + 32));
+
+        if (BITBAND_PERI((*curAddr), ADC14_MCTLN_EOS_OFS))
+            break;
+
+        if (curAddr == _ctlRegs[31])
+            curAddr = (uint32_t*) _ctlRegs[0];
+        else
+            curAddr++;
+    }
+
+}
+
+void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd,
+        uint16_t* res)
+{
+    uint32_t ii = 0;
+    uint32_t *firstPoint, *secondPoint;
+
+    bool foundEnd = false;
+
+    ASSERT(
+            _getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM
+            && _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM);
+
+    firstPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryStart)];
+    secondPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryEnd)];
+
+    while (!foundEnd)
+    {
+        if (firstPoint == secondPoint)
+        {
+            foundEnd = true;
+        }
+
+        res[ii] = *(((uint16_t*) firstPoint) + 0x40);
+
+        if (firstPoint == _ctlRegs[31])
+            firstPoint = (uint32_t*) _ctlRegs[0];
+        else
+            firstPoint += 0x04;
+    }
+}
+
+bool ADC14_enableReferenceBurst(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 1;
+
+    return true;
+}
+
+bool ADC14_disableReferenceBurst(void)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 0;
+
+    return true;
+}
+
+bool ADC14_setPowerMode(uint32_t adcPowerMode)
+{
+    if (ADCIsConversionRunning())
+        return false;
+
+    switch (adcPowerMode)
+    {
+    case ADC_UNRESTRICTED_POWER_MODE:
+        ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
+                | (ADC14_CTL1_PWRMD_0);
+        break;
+    case ADC_ULTRA_LOW_POWER_MODE:
+        ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK))
+                | (ADC14_CTL1_PWRMD_2);
+        break;
+    default:
+        ASSERT(false);
+        return false;
+    }
+
+    return true;
+}
+
+void ADC14_enableInterrupt(uint_fast64_t mask)
+{
+    uint32_t stat = mask & 0xFFFFFFFF;
+
+    ADC14->IER0 |= stat;
+    stat = (mask >> 32);
+    ADC14->IER1 |= (stat);
+}
+
+void ADC14_disableInterrupt(uint_fast64_t mask)
+{
+    uint32_t stat = mask & 0xFFFFFFFF;
+
+    ADC14->IER0 &= ~stat;
+    stat = (mask >> 32);
+    ADC14->IER1 &= ~(stat);
+}
+
+uint_fast64_t ADC14_getInterruptStatus(void)
+{
+    uint_fast64_t status = ADC14->IFGR1;
+    return ((status << 32) | ADC14->IFGR0);
+}
+
+uint_fast64_t ADC14_getEnabledInterruptStatus(void)
+{
+    uint_fast64_t stat = ADC14->IER1;
+
+    return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->IER0);
+
+}
+
+void ADC14_clearInterruptFlag(uint_fast64_t mask)
+{
+    uint32_t stat = mask & 0xFFFFFFFF;
+
+    ADC14->CLRIFGR0 |= stat;
+    stat = (mask >> 32);
+    ADC14->CLRIFGR1 |= (stat);
+}
+
+void ADC14_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_ADC14, intHandler);
+
+    //
+    // Enable the ADC interrupt.
+    //
+    Interrupt_enableInterrupt(INT_ADC14);
+}
+
+void ADC14_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_ADC14);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_ADC14);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/aes256.c

@@ -0,0 +1,355 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <aes256.h>
+#include <interrupt.h>
+#include <debug.h>
+
+bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
+        uint_fast16_t keyLength)
+{
+    uint_fast8_t i;
+    uint16_t sCipherKey;
+
+    AES256_CMSIS(moduleInstance)->CTL0 |= 0;
+
+    switch (keyLength)
+    {
+    case AES256_KEYLENGTH_128BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
+        break;
+
+    case AES256_KEYLENGTH_192BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
+        break;
+
+    case AES256_KEYLENGTH_256BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
+        break;
+    default:
+        return false;
+    }
+
+    keyLength = keyLength / 8;
+
+    for (i = 0; i < keyLength; i = i + 2)
+    {
+        sCipherKey = (uint16_t) (cipherKey[i]);
+        sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->KEY = sCipherKey;
+    }
+
+    // Wait until key is written
+    while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS))
+        ;
+
+    return true;
+}
+
+void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data,
+        uint8_t * encryptedData)
+{
+    uint_fast8_t i;
+    uint16_t tempData = 0;
+    uint16_t tempVariable = 0;
+
+    // Set module to encrypt mode
+    AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
+
+    // Write data to encrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i]);
+        tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->DIN = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Encryption is initialized by setting AES256_STAT_KEYWR to 1
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
+
+    // Wait unit finished ~167 MCLK
+    while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
+        ;
+
+    // Write encrypted data back to variable
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempData = AES256_CMSIS(moduleInstance)->DOUT;
+        *(encryptedData + i) = (uint8_t) tempData;
+        *(encryptedData + i + 1) = (uint8_t) (tempData >> 8);
+    }
+}
+
+void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data,
+        uint8_t * decryptedData)
+{
+    uint_fast8_t i;
+    uint16_t tempData = 0;
+    uint16_t tempVariable = 0;
+
+    // Set module to decrypt mode
+    AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
+
+    // Write data to decrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i + 1] << 8);
+        tempVariable = tempVariable | ((uint16_t) (data[i]));
+        AES256_CMSIS(moduleInstance)->DIN = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Now decryption starts
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
+
+    // Wait unit finished ~167 MCLK
+    while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
+        ;
+
+    // Write encrypted data back to variable
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempData = AES256_CMSIS(moduleInstance)->DOUT;
+        *(decryptedData + i) = (uint8_t) tempData;
+        *(decryptedData + i + 1) = (uint8_t) (tempData >> 8);
+    }
+}
+
+bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey,
+        uint_fast16_t keyLength)
+{
+    uint8_t i;
+    uint16_t tempVariable = 0;
+
+    // Set module to decrypt mode
+    AES256_CMSIS(moduleInstance)->CTL0 =
+            (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
+
+    switch (keyLength)
+    {
+    case AES256_KEYLENGTH_128BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
+        break;
+
+    case AES256_KEYLENGTH_192BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
+        break;
+
+    case AES256_KEYLENGTH_256BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
+        break;
+
+    default:
+        return false;
+    }
+
+    keyLength = keyLength / 8;
+
+    // Write cipher key to key register
+    for (i = 0; i < keyLength; i = i + 2)
+    {
+        tempVariable = (uint16_t) (cipherKey[i]);
+        tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->KEY = tempVariable;
+    }
+
+    // Wait until key is processed ~52 MCLK
+    while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
+        ;
+
+    return true;
+}
+
+void AES256_clearInterruptFlag(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIFG_OFS) = 0;
+}
+
+uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_RDYIFG_OFS);
+}
+
+void AES256_enableInterrupt(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 1;
+}
+
+void AES256_disableInterrupt(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 0;
+}
+
+void AES256_reset(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_SWRST_OFS) = 1;
+}
+
+void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data)
+{
+    uint8_t i;
+    uint16_t tempVariable = 0;
+
+    // Set module to encrypt mode
+    AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK;
+
+    // Write data to encrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i]);
+        tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->DIN = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Encryption is initialized by setting AES256_STAT_KEYWR to 1
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
+}
+
+void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data)
+{
+    uint_fast8_t i;
+    uint16_t tempVariable = 0;
+
+    // Set module to decrypt mode
+    AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3);
+
+    // Write data to decrypt to module
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempVariable = (uint16_t) (data[i + 1] << 8);
+        tempVariable = tempVariable | ((uint16_t) (data[i]));
+        AES256_CMSIS(moduleInstance)->DIN = tempVariable;
+    }
+
+    // Key that is already written shall be used
+    // Now decryption starts
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1;
+}
+
+bool AES256_startSetDecipherKey(uint32_t moduleInstance,
+        const uint8_t * cipherKey, uint_fast16_t keyLength)
+{
+    uint_fast8_t i;
+    uint16_t tempVariable = 0;
+
+    AES256_CMSIS(moduleInstance)->CTL0 =
+            (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1;
+
+    switch (keyLength)
+    {
+    case AES256_KEYLENGTH_128BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT;
+        break;
+
+    case AES256_KEYLENGTH_192BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT;
+        break;
+
+    case AES256_KEYLENGTH_256BIT:
+        AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT;
+        break;
+
+    default:
+        return false;
+    }
+
+    keyLength = keyLength / 8;
+
+    // Write cipher key to key register
+    for (i = 0; i < keyLength; i = i + 2)
+    {
+        tempVariable = (uint16_t) (cipherKey[i]);
+        tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8);
+        AES256_CMSIS(moduleInstance)->KEY = tempVariable;
+    }
+
+    return true;
+}
+
+bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData)
+{
+    uint8_t i;
+    uint16_t tempData = 0;
+
+    // If module is busy, exit and return failure
+    if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS))
+        return false;
+
+    // Write encrypted data back to variable
+    for (i = 0; i < 16; i = i + 2)
+    {
+        tempData = AES256_CMSIS(moduleInstance)->DOUT;
+        *(outputData + i) = (uint8_t) tempData;
+        *(outputData + i + 1) = (uint8_t) (tempData >> 8);
+    }
+
+    return true;
+}
+
+bool AES256_isBusy(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS);
+}
+
+void AES256_clearErrorFlag(uint32_t moduleInstance)
+{
+    BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS) = 0;
+}
+
+uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS);
+}
+
+void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(INT_AES256, intHandler);
+    Interrupt_enableInterrupt(INT_AES256);
+}
+
+void AES256_unregisterInterrupt(uint32_t moduleInstance)
+{
+    Interrupt_disableInterrupt(INT_AES256);
+    Interrupt_unregisterInterrupt(INT_AES256);
+}
+
+uint32_t AES256_getInterruptStatus(uint32_t moduleInstance)
+{
+    return AES256_getInterruptFlagStatus(moduleInstance);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/aes256.h

@@ -0,0 +1,451 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef AES256_H_
+#define AES256_H_
+
+//*****************************************************************************
+//
+//! \addtogroup aes256_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+/* Module Defines and macro for easy access */
+#define AES256_CMSIS(x) ((AES256_Type *) x)
+
+//*****************************************************************************
+//
+// The following are deprecated values. Please refer to documentation for the
+// correct values to use.
+//
+//*****************************************************************************
+#define Key_128BIT                                                          128
+#define Key_192BIT                                                          192
+#define Key_256BIT                                                          256
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the keyLength parameter for
+// functions: AES256_setCipherKey(), AES256_setDecipherKey(), and
+// AES256_startSetDecipherKey().
+//
+//*****************************************************************************
+#define AES256_KEYLENGTH_128BIT                                             128
+#define AES256_KEYLENGTH_192BIT                                             192
+#define AES256_KEYLENGTH_256BIT                                             256
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the AES256_getErrorFlagStatus() function.
+//
+//*****************************************************************************
+#define AES256_ERROR_OCCURRED                                 AES256_CTL0_ERRFG
+#define AES256_NO_ERROR                                                    0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the AES256_isBusy() function.
+//
+//*****************************************************************************
+#define AES256_BUSY                                            AES256_STAT_BUSY
+#define AES256_NOT_BUSY                                                    0x00
+
+//*****************************************************************************
+//
+// The following are values that can be passed toThe following are values that
+// can be returned by the AES256_getInterruptFlagStatus() function.
+//
+//*****************************************************************************
+#define AES256_READY_INTERRUPT                                             0x01
+#define AES256_NOTREADY_INTERRUPT                                          0x00
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Loads a 128, 192 or 256 bit cipher key to AES256 module.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
+//!        that contains a 128 bit cipher key.
+//! \param keyLength is the length of the key.
+//!        Valid values are:
+//!        - \b AES256_KEYLENGTH_128BIT
+//!        - \b AES256_KEYLENGTH_192BIT
+//!        - \b AES256_KEYLENGTH_256BIT
+//!
+//! \return true if set correctly, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_setCipherKey(uint32_t moduleInstance,
+        const uint8_t *cipherKey, uint_fast16_t keyLength);
+
+//*****************************************************************************
+//
+//! \brief Encrypts a block of data using the AES256 module.
+//!
+//! The cipher key that is used for encryption should be loaded in advance by
+//! using function AES256_setCipherKey()
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains data to be encrypted.
+//! \param encryptedData is a pointer to an uint8_t array with a length of 16
+//!        bytes in that the encrypted data will be written.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_encryptData(uint32_t moduleInstance, const uint8_t *data,
+        uint8_t *encryptedData);
+
+//*****************************************************************************
+//
+//! \brief Decrypts a block of data using the AES256 module.
+//!
+//! This function requires a pregenerated decryption key. A key can be loaded
+//! and pregenerated by using function AES256_setDecipherKey() or
+//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains encrypted data to be decrypted.
+//! \param decryptedData is a pointer to an uint8_t array with a length of 16
+//!        bytes in that the decrypted data will be written.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_decryptData(uint32_t moduleInstance, const uint8_t *data,
+        uint8_t *decryptedData);
+
+//*****************************************************************************
+//
+//! \brief Sets the decipher key.
+//!
+//! The API AES256_startSetDecipherKey or AES256_setDecipherKey must be invoked
+//! before invoking AES256_startDecryptData.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
+//!        that contains a 128 bit cipher key.
+//! \param keyLength is the length of the key.
+//!        Valid values are:
+//!        - \b AES256_KEYLENGTH_128BIT
+//!        - \b AES256_KEYLENGTH_192BIT
+//!        - \b AES256_KEYLENGTH_256BIT
+//!
+//! \return true if set, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_setDecipherKey(uint32_t moduleInstance,
+        const uint8_t *cipherKey, uint_fast16_t keyLength);
+
+//*****************************************************************************
+//
+//! \brief Clears the AES256 ready interrupt flag.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESRDYIFG of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_clearInterruptFlag(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Gets the AES256 ready interrupt flag status.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! \return One of the following:
+//!         - \b AES256_READY_INTERRUPT
+//!         - \b AES256_NOTREADY_INTERRUPT
+//!         \n indicating the status of the AES256 ready status
+//
+//*****************************************************************************
+extern uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Enables AES256 ready interrupt.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESRDYIE of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_enableInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Disables AES256 ready interrupt.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESRDYIE of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_disableInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Resets AES256 Module immediately.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESSWRST of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_reset(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Starts an encryption process on the AES256 module.
+//!
+//! The cipher key that is used for decryption should be loaded in advance by
+//! using function AES256_setCipherKey(). This is a non-blocking equivalent pf
+//! AES256_encryptData(). It is recommended to use the interrupt functionality
+//! to check for procedure completion then use the AES256_getDataOut() API to
+//! retrieve the encrypted data.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains data to be encrypted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_startEncryptData(uint32_t moduleInstance,
+        const uint8_t *data);
+
+//*****************************************************************************
+//
+//! \brief Decypts a block of data using the AES256 module.
+//!
+//! This is the non-blocking equivalant of AES256_decryptData(). This function
+//! requires a pregenerated decryption key. A key can be loaded and
+//! pregenerated by using function AES256_setDecipherKey() or
+//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. It is
+//! recommended to use interrupt to check for procedure completion then use the
+//! AES256_getDataOut() API to retrieve the decrypted data.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param data is a pointer to an uint8_t array with a length of 16 bytes that
+//!        contains encrypted data to be decrypted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_startDecryptData(uint32_t moduleInstance,
+        const uint8_t *data);
+
+//*****************************************************************************
+//
+//! \brief Sets the decipher key
+//!
+//! The API AES256_startSetDecipherKey() or AES256_setDecipherKey() must be
+//! invoked before invoking AES256_startDecryptData.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes
+//!        that contains a 128 bit cipher key.
+//! \param keyLength is the length of the key.
+//!        Valid values are:
+//!        - \b AES256_KEYLENGTH_128BIT
+//!        - \b AES256_KEYLENGTH_192BIT
+//!        - \b AES256_KEYLENGTH_256BIT
+//!
+//! \return true if set correctly, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_startSetDecipherKey(uint32_t moduleInstance,
+        const uint8_t *cipherKey, uint_fast16_t keyLength);
+
+//*****************************************************************************
+//
+//! \brief Reads back the output data from AES256 module.
+//!
+//! This function is meant to use after an encryption or decryption process
+//! that was started and finished by initiating an interrupt by use of
+//! AES256_startEncryptData or AES256_startDecryptData functions.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//! \param outputData is a pointer to an uint8_t array with a length of 16
+//!        bytes in that the data will be written.
+//!
+//! \return true if data is valid, otherwise false
+//
+//*****************************************************************************
+extern bool AES256_getDataOut(uint32_t moduleInstance,
+        uint8_t *outputData);
+
+//*****************************************************************************
+//
+//! \brief Gets the AES256 module busy status.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! \return true if busy, false otherwise
+//
+//*****************************************************************************
+extern bool AES256_isBusy(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Clears the AES256 error flag.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! Modified bits are \b AESERRFG of \b AESACTL0 register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AES256_clearErrorFlag(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! \brief Gets the AES256 error flag status.
+//!
+//! \param moduleInstance is the base address of the AES256 module.
+//!
+//! \return One of the following:
+//!         - \b AES256_ERROR_OCCURRED
+//!         - \b AES256_NO_ERROR
+//!         \n indicating the error flag status
+//
+//*****************************************************************************
+extern uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the AES interrupt.
+//!
+//! \param moduleInstance Instance of the AES256 module
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! AES interrupt occurs.
+//!
+//! This function registers the handler to be called when a AES
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific AES interrupts must be enabled
+//! via AES256_enableInterrupt().  It is the interrupt handler's responsibility
+//! to clear the interrupt source via AES256_clearInterrupt().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void AES256_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the AES interrupt
+//!
+//! \param moduleInstance Instance of the AES256 module
+//!
+//! This function unregisters the handler to be called when AES
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void AES256_unregisterInterrupt(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the current interrupt flag for the peripheral.
+//!
+//! \param moduleInstance Instance of the AES256 module
+//!
+//! \return The currently triggered interrupt flag for the module.
+//
+//*****************************************************************************
+extern uint32_t AES256_getInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* AES256_H_ */
+

platform/vendor_bsp/TI/MSP432P4xx/comp_e.c

@@ -0,0 +1,317 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <comp_e.h>
+#include <interrupt.h>
+#include <debug.h>
+
+static uint16_t __getRegisterSettingForInput(uint32_t input)
+{
+    switch (input)
+    {
+    case COMP_E_INPUT0:
+        return COMP_E_CTL0_IPSEL_0;
+    case COMP_E_INPUT1:
+        return COMP_E_CTL0_IPSEL_1;
+    case COMP_E_INPUT2:
+        return COMP_E_CTL0_IPSEL_2;
+    case COMP_E_INPUT3:
+        return COMP_E_CTL0_IPSEL_3;
+    case COMP_E_INPUT4:
+        return COMP_E_CTL0_IPSEL_4;
+    case COMP_E_INPUT5:
+        return COMP_E_CTL0_IPSEL_5;
+    case COMP_E_INPUT6:
+        return COMP_E_CTL0_IPSEL_6;
+    case COMP_E_INPUT7:
+        return COMP_E_CTL0_IPSEL_7;
+    case COMP_E_INPUT8:
+        return COMP_E_CTL0_IPSEL_8;
+    case COMP_E_INPUT9:
+        return COMP_E_CTL0_IPSEL_9;
+    case COMP_E_INPUT10:
+        return COMP_E_CTL0_IPSEL_10;
+    case COMP_E_INPUT11:
+        return COMP_E_CTL0_IPSEL_11;
+    case COMP_E_INPUT12:
+        return COMP_E_CTL0_IPSEL_12;
+    case COMP_E_INPUT13:
+        return COMP_E_CTL0_IPSEL_13;
+    case COMP_E_INPUT14:
+        return COMP_E_CTL0_IPSEL_14;
+    case COMP_E_INPUT15:
+        return COMP_E_CTL0_IPSEL_15;
+    case COMP_E_VREF:
+        return COMP_E_VREF;
+    default:
+        ASSERT(false);
+        return 0x11;
+    }
+
+}
+
+bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config)
+{
+    uint_fast8_t positiveTerminalInput = __getRegisterSettingForInput(
+            config->positiveTerminalInput);
+    uint_fast8_t negativeTerminalInput = __getRegisterSettingForInput(
+            config->negativeTerminalInput);
+    bool retVal = true;
+
+    ASSERT(positiveTerminalInput < 0x10); ASSERT(negativeTerminalInput < 0x10);
+    ASSERT(positiveTerminalInput != negativeTerminalInput);
+    ASSERT(
+            config->outputFilterEnableAndDelayLevel
+            <= COMP_E_FILTEROUTPUT_DLYLVL4);
+
+    /* Reset COMPE Control 1 & Interrupt Registers for initialization */
+    COMP_E_CMSIS(comparator)->CTL0 = 0;
+    COMP_E_CMSIS(comparator)->INT = 0;
+
+    // Set the Positive Terminal
+    if (COMP_E_VREF != positiveTerminalInput)
+    {
+        // Enable Positive Terminal Input Mux and Set to the appropriate input
+        COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN
+                + positiveTerminalInput;
+
+        // Disable the input buffer
+        COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput);
+    } else
+    {
+        //  Reset and Set COMPE Control 2 Register
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0;
+    }
+
+    // Set the Negative Terminal
+    if (COMP_E_VREF != negativeTerminalInput)
+    {
+        // Enable Negative Terminal Input Mux and Set  to the appropriate input
+        COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN
+                + (negativeTerminalInput << 8);
+
+        // Disable the input buffer
+        COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput);
+    } else
+    {
+        // Reset and Set COMPE Control 2 Register
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1;
+    }
+
+    // Reset and Set COMPE Control 1 Register
+    COMP_E_CMSIS(comparator)->CTL1 = config->powerMode
+            + config->outputFilterEnableAndDelayLevel
+            + config->invertedOutputPolarity;
+
+    return retVal;
+}
+
+void COMP_E_setReferenceVoltage(uint32_t comparator,
+        uint_fast16_t supplyVoltageReferenceBase,
+        uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
+        uint_fast16_t upperLimitSupplyVoltageFractionOf32)
+{
+    ASSERT(supplyVoltageReferenceBase <= COMP_E_VREFBASE2_5V);
+    ASSERT(upperLimitSupplyVoltageFractionOf32 <= 32);
+    ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32); ASSERT(
+            upperLimitSupplyVoltageFractionOf32
+            >= lowerLimitSupplyVoltageFractionOf32);
+
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_MRVS_OFS) = 0;
+    COMP_E_CMSIS(comparator)->CTL2 &= COMP_E_CTL2_RSEL;
+
+    // Set Voltage Source(Vcc | Vref, resistor ladder or not)
+    if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase)
+    {
+        COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_1;
+    } else if (lowerLimitSupplyVoltageFractionOf32 == 32)
+    {
+        COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_3;
+    } else
+    {
+        COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_2;
+    }
+
+    // Set COMPE Control 2 Register
+    COMP_E_CMSIS(comparator)->CTL2 |= supplyVoltageReferenceBase
+            + ((upperLimitSupplyVoltageFractionOf32 - 1) << 8)
+            + (lowerLimitSupplyVoltageFractionOf32 - 1);
+}
+
+void COMP_E_setReferenceAccuracy(uint32_t comparator,
+        uint_fast16_t referenceAccuracy)
+{
+    ASSERT(
+            (referenceAccuracy == COMP_E_ACCURACY_STATIC)
+            || (referenceAccuracy == COMP_E_ACCURACY_CLOCKED));
+
+    if (referenceAccuracy)
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 1;
+    else
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 0;
+
+}
+
+void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode)
+{
+    COMP_E_CMSIS(comparator)->CTL1 = (COMP_E_CMSIS(comparator)->CTL1
+            & ~(COMP_E_CTL1_PWRMD_MASK)) | powerMode;
+}
+
+void COMP_E_enableModule(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 1;
+}
+
+void COMP_E_disableModule(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 0;
+}
+
+void COMP_E_shortInputs(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 1;
+}
+
+void COMP_E_unshortInputs(uint32_t comparator)
+{
+    BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 0;
+}
+
+void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
+{
+    ASSERT(inputPort <= COMP_E_INPUT15);
+
+    COMP_E_CMSIS(comparator)->CTL3 |= (inputPort);
+}
+
+void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort)
+{
+    ASSERT(inputPort <= COMP_E_INPUT15);
+
+    COMP_E_CMSIS(comparator)->CTL3 &= ~(inputPort);
+}
+
+void COMP_E_swapIO(uint32_t comparator)
+{
+    COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_EX; // Toggle CEEX bit
+}
+
+uint8_t COMP_E_outputValue(uint32_t comparator)
+{
+    return COMP_E_CMSIS(comparator)->CTL1 & COMP_E_CTL1_OUT;
+}
+
+void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask)
+{
+    // Set the Interrupt enable bit
+    COMP_E_CMSIS(comparator)->INT |= mask;
+}
+
+uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator)
+{
+    return COMP_E_getInterruptStatus(comparator) &
+    COMP_E_CMSIS(comparator)->INT;
+}
+
+void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask)
+{
+    COMP_E_CMSIS(comparator)->INT &= ~(mask);
+}
+
+void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask)
+{
+    COMP_E_CMSIS(comparator)->INT &= ~(mask);
+}
+
+uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator)
+{
+    return (COMP_E_CMSIS(comparator)->INT & (COMP_E_OUTPUT_INTERRUPT_FLAG |
+    COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY |
+    COMP_E_INTERRUPT_FLAG_READY));
+}
+
+void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
+        uint_fast8_t edgeDirection)
+{
+    ASSERT(edgeDirection <= COMP_E_RISINGEDGE);
+
+    // Set the edge direction that will trigger an interrupt
+    if (COMP_E_RISINGEDGE == edgeDirection)
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1;
+    else if (COMP_E_FALLINGEDGE == edgeDirection)
+        BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 0;
+}
+
+void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator)
+{
+    COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_IES;
+}
+
+void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void))
+{
+    switch (comparator)
+    {
+    case COMP_E0_BASE:
+        Interrupt_registerInterrupt(INT_COMP_E0, intHandler);
+        Interrupt_enableInterrupt(INT_COMP_E0);
+        break;
+    case COMP_E1_BASE:
+        Interrupt_registerInterrupt(INT_COMP_E1, intHandler);
+        Interrupt_enableInterrupt(INT_COMP_E1);
+        break;
+    default:
+        ASSERT(false);
+    }
+}
+
+void COMP_E_unregisterInterrupt(uint32_t comparator)
+{
+    switch (comparator)
+    {
+    case COMP_E0_BASE:
+        Interrupt_disableInterrupt(INT_COMP_E0);
+        Interrupt_unregisterInterrupt(INT_COMP_E0);
+        break;
+    case COMP_E1_BASE:
+        Interrupt_disableInterrupt(INT_COMP_E1);
+        Interrupt_unregisterInterrupt(INT_COMP_E1);
+        break;
+    default:
+        ASSERT(false);
+    }
+}
+

platform/vendor_bsp/TI/MSP432P4xx/comp_e.h

@@ -0,0 +1,733 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef COMP_E_H_
+#define COMP_E_H_
+
+//*****************************************************************************
+//
+//! \addtogroup comp_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+/* Module defines for Comp */
+#define COMP_E_CMSIS(x) ((COMP_E_Type *) x)
+
+#define COMP_E_FILTEROUTPUT_OFF                                            0x00
+#define COMP_E_FILTEROUTPUT_DLYLVL1         (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_0)
+#define COMP_E_FILTEROUTPUT_DLYLVL2         (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_1)
+#define COMP_E_FILTEROUTPUT_DLYLVL3         (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_2)
+#define COMP_E_FILTEROUTPUT_DLYLVL4         (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_3)
+
+#define COMP_E_INPUT0                                                    (0x01)
+#define COMP_E_INPUT1                                                    (0x02)
+#define COMP_E_INPUT2                                                    (0x04)
+#define COMP_E_INPUT3                                                    (0x08)
+#define COMP_E_INPUT4                                                    (0x10)
+#define COMP_E_INPUT5                                                    (0x20)
+#define COMP_E_INPUT6                                                    (0x40)
+#define COMP_E_INPUT7                                                    (0x80)
+#define COMP_E_INPUT8                                                   (0x100)
+#define COMP_E_INPUT9                                                   (0x200)
+#define COMP_E_INPUT10                                                  (0x400)
+#define COMP_E_INPUT11                                                  (0x800)
+#define COMP_E_INPUT12                                                 (0x1000)
+#define COMP_E_INPUT13                                                 (0x2000)
+#define COMP_E_INPUT14                                                 (0x4000)
+#define COMP_E_INPUT15                                                 (0x8000)
+#define COMP_E_VREF                                                      (0x9F)
+
+#define COMP_E_NORMALOUTPUTPOLARITY                      (!(COMP_E_CTL1_OUTPOL))
+#define COMP_E_INVERTEDOUTPUTPOLARITY                       (COMP_E_CTL1_OUTPOL)
+
+#define COMP_E_REFERENCE_AMPLIFIER_DISABLED               (COMP_E_CTL2_CEREFL_0)
+#define COMP_E_VREFBASE1_2V                               (COMP_E_CTL2_CEREFL_1)
+#define COMP_E_VREFBASE2_0V                               (COMP_E_CTL2_CEREFL_2)
+#define COMP_E_VREFBASE2_5V                               (COMP_E_CTL2_CEREFL_3)
+
+#define COMP_E_ACCURACY_STATIC                             (!COMP_E_CTL2_REFACC)
+#define COMP_E_ACCURACY_CLOCKED                             (COMP_E_CTL2_REFACC)
+
+#define COMP_E_HIGH_SPEED_MODE                             (COMP_E_CTL1_PWRMD_0)
+#define COMP_E_NORMAL_MODE                                 (COMP_E_CTL1_PWRMD_1)
+#define COMP_E_ULTRA_LOW_POWER_MODE                        (COMP_E_CTL1_PWRMD_2)
+
+#define COMP_E_OUTPUT_INTERRUPT                                  (COMP_E_INT_IE)
+#define COMP_E_INVERTED_POLARITY_INTERRUPT                      (COMP_E_INT_IIE)
+#define COMP_E_READY_INTERRUPT                                (COMP_E_INT_RDYIE)
+
+#define COMP_E_OUTPUT_INTERRUPT_FLAG                            (COMP_E_INT_IFG)
+#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY                (COMP_E_INT_IIFG)
+#define COMP_E_INTERRUPT_FLAG_READY                          (COMP_E_INT_RDYIFG)
+
+#define COMP_E_FALLINGEDGE                                  (!(COMP_E_CTL1_IES))
+#define COMP_E_RISINGEDGE                                      (COMP_E_CTL1_IES)
+
+#define COMP_E_LOW                                                         (0x0)
+#define COMP_E_HIGH                                            (COMP_E_CTL1_OUT)
+
+//*****************************************************************************
+//
+//!     ypedef COMP_E_Config
+//! \brief Type definition for \link _COMP_E_Config \endlink structure
+//!
+//! \struct _COMP_E_Config
+//! \brief Configuration structure for Comparator module. See 
+//!        \link COMP_E_initModule \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct _COMP_E_Config
+{
+    uint_fast16_t positiveTerminalInput;
+    uint_fast16_t negativeTerminalInput;
+    uint_fast8_t outputFilterEnableAndDelayLevel;
+    uint_fast8_t invertedOutputPolarity;
+    uint_fast16_t powerMode;
+} COMP_E_Config;
+
+//*****************************************************************************
+//
+//! Initializes the Comparator Module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param config Configuration structure for the Comparator module
+//!
+//! <hr>
+//! <b>Configuration options for \link COMP_E_Config \endlink structure.</b>
+//! <hr>
+//!
+//! \param positiveTerminalInput selects the input to the positive terminal.
+//!        Valid values are
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!        - \b COMP_E_VREF
+//!        \n Modified bits are \b CEIPSEL and \b CEIPEN of \b CECTL0 register,
+//!        \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register.
+//! \param negativeTerminalInput selects the input to the negative terminal.
+//!        \n Valid values are:
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!        - \b COMP_E_VREF
+//!        \n Modified bits are \b CEIMSEL and \b CEIMEN of \b CECTL0 register,
+//!        \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register.
+//! \param outputFilterEnableAndDelayLevel controls the output filter delay
+//!       state, which is either off or enabled with a specified delay level.
+//!        \n Valid values are
+//!        - \b COMP_E_FILTEROUTPUT_OFF [Default]
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL1
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL2
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL3
+//!        - \b COMP_E_FILTEROUTPUT_DLYLVL4
+//!        \n This parameter is device specific and delay levels should be found
+//!        in the device's datasheet.
+//!        \n Modified bits are \b CEF and \b CEFDLY of \b CECTL1 register.
+//! \param invertedOutputPolarity controls if the output will be inverted or
+//!        not. Valid values are
+//!        - \b COMP_E_NORMALOUTPUTPOLARITY - indicates the output should be
+//!             normal. [Default]
+//!        - \b COMP_E_INVERTEDOUTPUTPOLARITY -  the output should be inverted.
+//!        \n Modified bits are \b CEOUTPOL of \b CECTL1 register.
+//! \param powerMode controls the power mode of the module
+//!        - \b COMP_E_HIGH_SPEED_MODE [default]
+//!        - \b COMP_E_NORMAL_MODE
+//!        - \b COMP_E_ULTRA_LOW_POWER_MODE
+//! Upon successful initialization of the Comparator module, this function will
+//! have reset all necessary register bits and set the given options in the
+//! registers. To actually use the comparator module, the COMP_E_enableModule()
+//! function must be explicitly called before use.
+//! If a Reference Voltage is set to a terminal, the Voltage should be set
+//! using the COMP_E_setReferenceVoltage() function.
+//!
+//! \return true or false of the initialization process.
+//
+//*****************************************************************************
+extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config);
+
+//*****************************************************************************
+//
+//! Generates a Reference Voltage to the terminal selected during
+//! initialization.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param supplyVoltageReferenceBase decides the source and max amount of
+//!       Voltage that can be used as a reference.
+//!        Valid values are
+//!        - \b COMP_E_REFERENCE_AMPLIFIER_DISABLED
+//!        - \b COMP_E_VREFBASE1_2V
+//!        - \b COMP_E_VREFBASE2_0V
+//!        - \b COMP_E_VREFBASE2_5V
+//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the
+//!       equation to generate the reference voltage for the upper limit
+//!       reference voltage. Valid values are between 0 and 32.
+//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the
+//!       equation to generate the reference voltage for the lower limit
+//!       reference voltage. Valid values are between 0 and 32.
+//!  <br>Modified bits are \b CEREF0 of \b CECTL2 register.
+//!
+//! Use this function to generate a voltage to serve as a reference to the
+//! terminal selected at initialization. The voltage is determined by the
+//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage
+//! numerators are equal, then a static reference is defined, whereas they are
+//! different then a hysteresis effect is generated.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setReferenceVoltage(uint32_t comparator,
+        uint_fast16_t supplyVoltageReferenceBase,
+        uint_fast16_t lowerLimitSupplyVoltageFractionOf32,
+        uint_fast16_t upperLimitSupplyVoltageFractionOf32);
+
+//*****************************************************************************
+//
+//! Sets the reference accuracy
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param referenceAccuracy is the reference accuracy setting of the
+//!      comparator. Clocked is for low power/low accuracy.
+//!      Valid values are
+//!      - \b COMP_E_ACCURACY_STATIC
+//!      - \b COMP_E_ACCURACY_CLOCKED
+//!      <br>Modified bits are \b CEREFACC of \b CECTL2 register.
+//!
+//! The reference accuracy is set to the desired setting. Clocked is better for
+//!  low power operations but has a lower accuracy.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setReferenceAccuracy(uint32_t comparator,
+        uint_fast16_t referenceAccuracy);
+
+//*****************************************************************************
+//
+//! Sets the power mode
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param powerMode decides the power mode
+//!        Valid values are
+//!        - \b COMP_E_HIGH_SPEED_MODE
+//!        - \b COMP_E_NORMAL_MODE
+//!        - \b COMP_E_ULTRA_LOW_POWER_MODE
+//!        <br>Modified bits are \b CEPWRMD of \b CECTL1 register.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode);
+
+//*****************************************************************************
+//
+//! Turns on the Comparator module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function sets the bit that enables the operation of the
+//! Comparator module.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_enableModule(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Turns off the Comparator module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function clears the CEON bit disabling the operation of the Comparator
+//! module, saving from excess power consumption.
+//!
+//! Modified bits are \b CEON of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_disableModule(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Shorts the two input pins chosen during initialization.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function sets the bit that shorts the devices attached to the input
+//! pins chosen from the initialization of the comparator.
+//!
+//! Modified bits are \b CESHORT of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_shortInputs(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Disables the short of the two input pins chosen during initialization.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function clears the bit that shorts the devices attached to the input
+//! pins chosen from the initialization of the comparator.
+//!
+//! Modified bits are \b CESHORT of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_unshortInputs(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Disables the input buffer of the selected input port to effectively allow
+//! for analog signals.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param inputPort is the port in which the input buffer will be disabled.
+//!        Valid values are a logical OR of the following:
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!       <br> Modified bits are \b CEPDx of \b CECTL3 register.
+//!
+//! This function sets the bit to disable the buffer for the specified input
+//! port to allow for analog signals from any of the comparator input pins. This
+//! bit is automatically set when the input is initialized to be used with the
+//! comparator module. This function should be used whenever an analog input is
+//! connected to one of these pins to prevent parasitic voltage from causing
+//! unexpected results.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_disableInputBuffer(uint32_t comparator,
+        uint_fast16_t inputPort);
+
+//*****************************************************************************
+//
+//! Enables the input buffer of the selected input port to allow for digital
+//! signals.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param inputPort is the port in which the input buffer will be enabled.
+//!        Valid values are a logical OR of the following:
+//!        - \b COMP_E_INPUT0 [Default]
+//!        - \b COMP_E_INPUT1
+//!        - \b COMP_E_INPUT2
+//!        - \b COMP_E_INPUT3
+//!        - \b COMP_E_INPUT4
+//!        - \b COMP_E_INPUT5
+//!        - \b COMP_E_INPUT6
+//!        - \b COMP_E_INPUT7
+//!        - \b COMP_E_INPUT8
+//!        - \b COMP_E_INPUT9
+//!        - \b COMP_E_INPUT10
+//!        - \b COMP_E_INPUT11
+//!        - \b COMP_E_INPUT12
+//!        - \b COMP_E_INPUT13
+//!        - \b COMP_E_INPUT14
+//!        - \b COMP_E_INPUT15
+//!      <br> Modified bits are \b CEPDx of \b CECTL3 register.
+//!
+//! This function clears the bit to enable the buffer for the specified input
+//! port to allow for digital signals from any of the comparator input pins.
+//! This should not be reset if there is an analog signal connected to the
+//! specified input pin to prevent from unexpected results.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_enableInputBuffer(uint32_t comparator,
+        uint_fast16_t inputPort);
+
+//*****************************************************************************
+//
+//! Toggles the bit that swaps which terminals the inputs go to, while also
+//! inverting the output of the comparator.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \ bCOMP_E0
+//!         - \ bCOMP_E1
+//!
+//! This function toggles the bit that controls which input goes to which
+//! terminal. After initialization, this bit is set to 0, after toggling it once
+//! the inputs are routed to the opposite terminal and the output is inverted.
+//!
+//! Modified bits are \b CEEX of \b CECTL1 register.
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_swapIO(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Returns the output value of the Comparator module.
+//!
+//! \param comparator is the instance of the Comparator module. Valid parameters
+//! vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! Returns the output value of the Comparator module.
+//!
+//! \return COMP_E_HIGH or COMP_E_LOW as the output value of the Comparator
+//!          module.
+//
+//*****************************************************************************
+extern uint8_t COMP_E_outputValue(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Enables selected Comparator interrupt sources.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!        Mask value is the logical OR of any of the following
+//!        - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
+//!        - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted
+//!                                                 polarity
+//!        - \b COMP_E_READY_INTERRUPT - Ready interrupt
+//!
+//! Enables the indicated Comparator interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor. The default trigger for the non-inverted
+//! interrupt is a rising edge of the output, this can be changed with the
+//! interruptSetEdgeDirection() function.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Disables selected Comparator interrupt sources.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param mask is the bit mask of the interrupt sources to be disabled.
+//!        Mask value is the logical OR of any of the following
+//!        - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt
+//!        - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted
+//!                                                 polarity
+//!        - \b COMP_E_READY_INTERRUPT - Ready interrupt
+//!
+//! Disables the indicated Comparator interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Clears Comparator interrupt flags.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param mask is a bit mask of the interrupt sources to be cleared.
+//!        Mask value is the logical OR of any of the following
+//!        - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag
+//!        - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag
+//!                                                     inverted polarity
+//!        - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag
+//!
+//! The Comparator interrupt source is cleared, so that it no longer asserts.
+//! The highest interrupt flag is automatically cleared when an interrupt vector
+//! generator is used.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current Comparator interrupt status.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This returns the interrupt status for the Comparator module based on which
+//! flag is passed.
+//!
+//! \return The current interrupt flag status for the corresponding mask.
+//
+//*****************************************************************************
+extern uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Enables selected Comparator interrupt sources masked with the enabled
+//! interrupts. This function is useful to call in ISRs to get a list
+//! of pending interrupts that are actually enabled and could have caused the
+//! ISR.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! Enables the indicated Comparator interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor. The default trigger for the non-inverted
+//! interrupt is a rising edge of the output, this can be changed with the
+//! COMP_E_setInterruptEdgeDirection() function.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Explicitly sets the edge direction that would trigger an interrupt.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//! \param edgeDirection determines which direction the edge would have to go
+//!       to generate an interrupt based on the non-inverted interrupt flag.
+//!        Valid values are
+//!        - \b COMP_E_FALLINGEDGE - sets the bit to generate an interrupt when
+//!             the output of the comparator falls from HIGH to LOW if the
+//!             normal interrupt bit is set(and LOW to HIGH if the inverted
+//!             interrupt enable bit is set). [Default]
+//!        - \b COMP_E_RISINGEDGE - sets the bit to generate an interrupt when the
+//!             output of the comparator rises from LOW to HIGH if the normal
+//!             interrupt bit is set(and HIGH to LOW if the inverted interrupt
+//!             enable bit is set).
+//!        <br>Modified bits are \b CEIES of \b CECTL1 register.
+//!
+//! This function will set which direction the output will have to go, whether
+//! rising or falling, to generate an interrupt based on a non-inverted
+//! interrupt.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_setInterruptEdgeDirection(uint32_t comparator,
+        uint_fast8_t edgeDirection);
+
+//*****************************************************************************
+//
+//! Toggles the edge direction that would trigger an interrupt.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function will toggle which direction the output will have to go,
+//! whether rising or falling, to generate an interrupt based on a non-inverted
+//! interrupt. If the direction was rising, it is now falling, if it was
+//! falling, it is now rising.
+//!
+//! Modified bits are \b CEIES of \b CECTL1 register.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the Comparator E interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! Comparator interrupt occurs.
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function registers the handler to be called when a Comparator
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific Comparator interrupts must be enabled
+//! via COMP_E_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via COMP_E_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void COMP_E_registerInterrupt(uint32_t comparator,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the Comparator E interrupt
+//!
+//! \param comparator is the instance of the Comparator module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b COMP_E0_BASE
+//!         - \b COMP_E1_BASE
+//!
+//! This function unregisters the handler to be called when Comparator E
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void COMP_E_unregisterInterrupt(uint32_t comparator);
+
+/* Backwards Compatibility Layer */
+#define COMP_E_enable(a) COMP_E_enableModule(a)
+#define COMP_E_disable(a) COMP_E_disableModule(a)
+#define COMP_E_IOSwap(a) COMP_E_swapIO(a)
+#define COMP_E_interruptToggleEdgeDirection(a) COMP_E_toggleInterruptEdgeDirection(a)
+#define COMP_E_clearInterrupt(a,b) COMP_E_clearInterruptFlag(a,b)
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
+#endif /* COMP_E_H_ */

platform/vendor_bsp/TI/MSP432P4xx/cpu.c

@@ -0,0 +1,430 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <cpu.h>
+#include <msp.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+uint32_t __attribute__((naked)) CPU_cpsid(void)
+{
+    uint32_t ret;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsid   i\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(__ICCARM__)
+uint32_t CPU_cpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsid   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(__CC_ARM)
+__asm uint32_t CPU_cpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs r0, PRIMASK;
+    cpsid i;
+    bx lr
+}
+#endif
+#if defined(__TI_ARM__)
+uint32_t CPU_cpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsid   i\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+uint32_t __attribute__((naked)) CPU_primask(void)
+{
+    uint32_t ret;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(__ICCARM__)
+uint32_t CPU_primask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(__CC_ARM)
+__asm uint32_t CPU_primask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs r0, PRIMASK;
+    bx lr
+}
+#endif
+#if defined(__TI_ARM__)
+uint32_t CPU_primask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction.  Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+uint32_t __attribute__((naked)) CPU_cpsie(void)
+{
+    uint32_t ret;
+
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsie   i\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(__ICCARM__)
+uint32_t CPU_cpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsie   i\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(__CC_ARM)
+__asm uint32_t CPU_cpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    mrs r0, PRIMASK;
+    cpsie i;
+    bx lr
+}
+#endif
+#if defined(__TI_ARM__)
+uint32_t CPU_cpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+            "    cpsie   i\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPUWFI instruction.
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+void __attribute__((naked)) CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n"
+            "    bx      lr\n");
+}
+#endif
+#if defined(__ICCARM__)
+void CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+#if defined(__CC_ARM)
+__asm void CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    wfi;
+    bx lr
+}
+#endif
+#if defined(__TI_ARM__)
+void CPU_wfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+            "    bx      lr\n");
+}
+#endif
+#if defined(__ICCARM__)
+void CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+#if defined(__CC_ARM)
+__asm void CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    msr BASEPRI, r0;
+    bx lr
+}
+#endif
+#if defined(__TI_ARM__)
+void CPU_basepriSet(uint32_t newBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+uint32_t __attribute__((naked)) CPU_basepriGet(void)
+{
+    uint32_t ret;
+
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+            "    bx      lr\n"
+            : "=r" (ret));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ret);
+}
+#endif
+#if defined(__ICCARM__)
+uint32_t CPU_basepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(__CC_ARM)
+__asm uint32_t CPU_basepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    mrs r0, BASEPRI;
+    bx lr
+}
+#endif
+#if defined(__TI_ARM__)
+uint32_t CPU_basepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+            "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif

platform/vendor_bsp/TI/MSP432P4xx/cpu.h

@@ -0,0 +1,76 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern uint32_t CPU_cpsid(void);
+extern uint32_t CPU_cpsie(void);
+extern uint32_t CPU_primask(void);
+extern void CPU_wfi(void);
+extern uint32_t CPU_basepriGet(void);
+extern void CPU_basepriSet(uint32_t newBasepri);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
+

platform/vendor_bsp/TI/MSP432P4xx/crc32.c

@@ -0,0 +1,147 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include "crc32.h"
+#include <msp.h>
+#include <debug.h>
+
+
+void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        CRC32->INIRES16 = seed;
+    else
+    {
+        CRC32->INIRES32_HI = ((seed & 0xFFFF0000) >> 16);
+        CRC32->INIRES32_LO = (seed & 0xFFFF);
+    }
+}
+
+void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        HWREG8(&(CRC32->DI16)) = dataIn;
+    else
+        HWREG8(&(CRC32->DI32)) = dataIn;
+}
+
+void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        CRC32->DI16 = dataIn;
+    else
+        CRC32->DI32 = dataIn;
+}
+
+void CRC32_set32BitData(uint32_t dataIn)
+{
+    //CRC32->DI32 = dataIn & 0xFFFF;
+    //CRC32->DI32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+
+    HWREG16(&(CRC32->DI32)) = dataIn & 0xFFFF;
+    HWREG16(&(CRC32->DI32)) = (uint16_t)(
+            (dataIn & 0xFFFF0000) >> 16);
+}
+
+void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        HWREG8(&(CRC32->DIRB16)) = dataIn;
+    else
+        HWREG8(&(CRC32->DIRB32)) = dataIn;
+}
+
+void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType)
+{
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        CRC32->DIRB16 = dataIn;
+    else
+        CRC32->DIRB32 = dataIn;
+}
+
+void CRC32_set32BitDataReversed(uint32_t dataIn)
+{
+    //CRC32->DIRB32 = dataIn & 0xFFFF;
+    //CRC32->DIRB32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16);
+
+    HWREG16(&(CRC32->DIRB32)) = dataIn & 0xFFFF;
+    HWREG16(&(CRC32->DIRB32)) = (uint16_t)(
+            (dataIn & 0xFFFF0000) >> 16);
+
+}
+
+uint32_t CRC32_getResult(uint_fast8_t crcType)
+{
+    uint32_t result;
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        return CRC32->INIRES16;
+    else
+    {
+        result = CRC32->INIRES32_HI;
+        result = (result << 16);
+        result |= CRC32->INIRES32_LO;
+        return (result);
+    }
+}
+
+uint32_t CRC32_getResultReversed(uint_fast8_t crcType)
+{
+    uint32_t result;
+    ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType));
+
+    if (CRC16_MODE == crcType)
+        return CRC32->RESR16;
+    else
+    {
+        result = CRC32->RESR32_HI;
+        result = (result << 16);
+        result |= CRC32->RESR32_LO;
+        return (result);
+    }
+}
+

platform/vendor_bsp/TI/MSP432P4xx/crc32.h

@@ -0,0 +1,235 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef _CRC_32_H
+
+//*****************************************************************************
+//
+//! \addtogroup crc32_api
+//! @{
+//
+//*****************************************************************************
+
+#include <stdint.h>
+
+#define CRC16_MODE 0x00
+#define CRC32_MODE 0x01
+
+//*****************************************************************************
+//
+//! Sets the seed for the CRC.
+//!
+//! \param seed is the seed for the CRC to start generating a signature from.
+//!        Modified bits are \b CRC16INIRESL0 of \b CRC16INIRESL0 register.
+//!            \b CRC32INIRESL0 of \b CRC32INIRESL0 register
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function sets the seed for the CRC to begin generating a signature with
+//! the given seed and all passed data. Using this function resets the CRC32
+//! signature.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Sets the 8 Bit data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIB0 of \b CRC16DIB0 register.
+//!                            \b CRC32DIB0 of \b CRC32DIB0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function sets the given data into the CRC module to generate the new
+//! signature from the current signature and new data. Bit 0 is
+//!    treated as LSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Sets the 16 Bit data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIW0 of \b CRC16DIW0 register.
+//!                          \b CRC32DIW0 of \b CRC32DIW0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function sets the given data into the CRC module to generate the new
+//! signature from the current signature and new data. Bit 0 is
+//!    treated as LSB
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Sets the 32 Bit data to add into the CRC module to generate a new signature.
+//!    Available only for CRC32_MODE and not for CRC16_MODE
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC32DIL0 of \b CRC32DIL0 register.
+//!
+//! This function sets the given data into the CRC module to generate the new
+//! signature from the current signature and new data. Bit 0 is
+//!    treated as LSB
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set32BitData(uint32_t dataIn);
+
+//*****************************************************************************
+//
+//! Translates the data by reversing the bits in each 8 bit data and then sets
+//! this data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIRBB0 of \b CRC16DIRBB0 register.
+//!                             \b CRC32DIRBB0 of \b CRC32DIRBB0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function first reverses the bits in each byte of the data and then
+//! generates the new signature from the current signature and new translated
+//! data. Bit 0 is treated as MSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Translates the data by reversing the bits in each 16 bit data and then
+//!    sets this data to add into the CRC module to generate a new signature.
+//!
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC16DIRBW0 of \b CRC16DIRBW0 register.
+//!                             \b CRC32DIRBW0 of \b CRC32DIRBW0 register.
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function first reverses the bits in each byte of the data and then
+//! generates the new signature from the current signature and new translated
+//! data.  Bit 0 is treated as MSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Translates the data by reversing the bits in each 32 Bit Data and then
+//!    sets this data to add into the CRC module to generate a new signature.
+//!    Available only for CRC32 mode and not for CRC16 mode
+//! \param dataIn is the data to be added, through the CRC module, to the
+//!       signature.
+//!        Modified bits are \b CRC32DIRBL0 of \b CRC32DIRBL0 register.
+//!
+//! This function first reverses the bits in each byte of the data and then
+//! generates the new signature from the current signature and new translated
+//! data.  Bit 0 is treated as MSB.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern void CRC32_set32BitDataReversed(uint32_t dataIn);
+
+//*****************************************************************************
+//
+//! Returns the value of CRC Signature Result.
+//!
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function returns the value of the signature result generated by the CRC.
+//! Bit 0 is treated as LSB.
+//! \return uint32_t Result
+//
+//*****************************************************************************
+extern uint32_t CRC32_getResult(uint_fast8_t crcType);
+
+//*****************************************************************************
+//
+//! Returns the bit-wise reversed format of the 32 bit Signature Result.
+//!
+//! \param crcType selects between CRC32 and CRC16
+//!            Valid values are \b CRC16_MODE and \b CRC32_MODE
+//!
+//! This function returns the bit-wise reversed format of the Signature Result.
+//! Bit 0 is treated as MSB.
+//!
+//! \return uint32_t Result
+//
+//*****************************************************************************
+extern uint32_t CRC32_getResultReversed(uint_fast8_t crcType);
+
+/* Defines for future devices that might have multiple instances */
+#define CRC32_setSeedMultipleInstance(a,b,c) CRC32_setSeed(b,c)
+#define CRC32_set8BitDataMultipleInstance(a,b,c)  CRC32_set8BitData(b,c)
+#define CRC32_set16BitDataMultipleInstance(a,b,c) CRC32_set16BitData(b,c)
+#define CRC32_set32BitDataMultipleInstance(a,b) CRC32_set32BitData(b)
+#define CRC32_set8BitDataReversedMultipleInstance(a,b,c) CRC32_set8BitDataReversed(b,c)
+#define CRC32_set16BitDataReversedMultipleInstance(a,b,c) CRC32_set16BitDataReversed(b,c)
+#define CRC32_set32BitDataReversedMultipleInstance(a,b) CRC32_set32BitDataReversed(b)
+#define CRC32_getResultMultipleInstance(a,b) CRC32_getResult()
+#define CRC32_getResultReversedMultipleInstance(a,b) CRC32_getResultReversed(b)
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
+#endif

platform/vendor_bsp/TI/MSP432P4xx/cs.c

@@ -0,0 +1,958 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <driverlib.h>
+#include <debug.h>
+
+/* Statics */
+static uint32_t hfxtFreq;
+static uint32_t lfxtFreq;
+
+#ifdef DEBUG
+
+bool _CSIsClockDividerValid(uint8_t divider)
+{
+    return ((divider == CS_CLOCK_DIVIDER_1) || (divider == CS_CLOCK_DIVIDER_2)
+            || (divider == CS_CLOCK_DIVIDER_4) || (divider == CS_CLOCK_DIVIDER_8)
+            || (divider == CS_CLOCK_DIVIDER_16) || (divider == CS_CLOCK_DIVIDER_32)
+            || (divider == CS_CLOCK_DIVIDER_64) || (divider == CS_CLOCK_DIVIDER_128));
+}
+
+#endif
+
+static uint32_t _CSGetHFXTFrequency()
+{
+    if (hfxtFreq >= CS_1MHZ && hfxtFreq <= CS_4MHZ)
+        return CS_CTL2_HFXTFREQ_0;
+    else if (hfxtFreq > CS_4MHZ && hfxtFreq <= CS_8MHZ)
+        return CS_CTL2_HFXTFREQ_1;
+    else if (hfxtFreq > CS_8MHZ && hfxtFreq <= CS_16MHZ)
+        return CS_CTL2_HFXTFREQ_2;
+    else if (hfxtFreq > CS_16MHZ && hfxtFreq <= CS_24MHZ)
+        return CS_CTL2_HFXTFREQ_3;
+    else if (hfxtFreq > CS_24MHZ && hfxtFreq <= CS_32MHZ)
+        return CS_CTL2_HFXTFREQ_4;
+    else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ)
+        return CS_CTL2_HFXTFREQ_5;
+    else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ)
+        return CS_CTL2_HFXTFREQ_5;
+    else
+    {
+        ASSERT(false);
+        return 0;
+    }
+
+}
+
+static uint32_t _CSGetDividerValue(uint32_t wDivider)
+{
+    switch (wDivider)
+    {
+    case CS_CLOCK_DIVIDER_1:
+        return 1;
+    case CS_CLOCK_DIVIDER_2:
+        return 2;
+    case CS_CLOCK_DIVIDER_4:
+        return 4;
+    case CS_CLOCK_DIVIDER_8:
+        return 8;
+    case CS_CLOCK_DIVIDER_16:
+        return 16;
+    case CS_CLOCK_DIVIDER_32:
+        return 32;
+    case CS_CLOCK_DIVIDER_64:
+        return 64;
+    case CS_CLOCK_DIVIDER_128:
+        return 128;
+    default:
+        ASSERT(false);
+        return 1;
+    }
+}
+
+static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider)
+{
+    uint_fast8_t bDivider;
+
+    bDivider = _CSGetDividerValue(wDivider);
+
+    switch (wClockSource)
+    {
+    case CS_LFXTCLK_SELECT:
+    {
+        if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+        {
+            CS_clearInterruptFlag(CS_LFXT_FAULT);
+
+            if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+            {
+                if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+                    return (128000 / bDivider);
+                else
+                    return (32768 / bDivider);
+            }
+        }
+        return lfxtFreq / bDivider;
+    }
+    case CS_HFXTCLK_SELECT:
+    {
+        if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+        {
+            CS_clearInterruptFlag(CS_HFXT_FAULT);
+
+            if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+            {
+                if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+                    return (128000 / bDivider);
+                else
+                    return (32768 / bDivider);
+            }
+        }
+        return hfxtFreq / bDivider;
+    }
+    case CS_VLOCLK_SELECT:
+        return CS_VLOCLK_FREQUENCY / bDivider;
+    case CS_REFOCLK_SELECT:
+    {
+        if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
+            return (128000 / bDivider);
+        else
+            return (32768 / bDivider);
+    }
+    case CS_DCOCLK_SELECT:
+        return (CS_getDCOFrequency() / bDivider);
+    case CS_MODOSC_SELECT:
+        return CS_MODCLK_FREQUENCY / bDivider;
+    default:
+        ASSERT(false);
+        return 0;
+    }
+}
+
+//******************************************************************************
+// Internal function for getting DCO nominal frequency
+//******************************************************************************
+static uint32_t _CSGetDOCFrequency(void)
+{
+    uint32_t dcoFreq;
+
+    switch (CS->CTL0 & CS_CTL0_DCORSEL_MASK)
+    {
+    case CS_CTL0_DCORSEL_0:
+        dcoFreq = 1500000;
+        break;
+    case CS_CTL0_DCORSEL_1:
+        dcoFreq = 3000000;
+        break;
+    case CS_CTL0_DCORSEL_2:
+        dcoFreq = 6000000;
+        break;
+    case CS_CTL0_DCORSEL_3:
+        dcoFreq = 12000000;
+        break;
+    case CS_CTL0_DCORSEL_4:
+        dcoFreq = 24000000;
+        break;
+    case CS_CTL0_DCORSEL_5:
+        dcoFreq = 48000000;
+        break;
+    default:
+        dcoFreq = 0;
+    }
+
+    return (dcoFreq);
+}
+
+void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
+        uint32_t hfxt_XT_CLK_frequency)
+{
+    hfxtFreq = hfxt_XT_CLK_frequency;
+    lfxtFreq = lfxt_XT_CLK_frequency;
+}
+
+void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource,
+        uint32_t clockSourceDivider)
+{
+    ASSERT(_CSIsClockDividerValid(clockSourceDivider));
+
+    /* Unlocking the CS Module */
+    CS->KEY = CS_KEY;
+
+    switch (selectedClockSignal)
+    {
+    case CS_ACLK:
+    {
+        /* Making sure that the clock signal for ACLK isn't set to anything
+         * invalid
+         */
+        ASSERT(
+                (selectedClockSignal != CS_DCOCLK_SELECT)
+                && (selectedClockSignal != CS_MODOSC_SELECT)
+                && (selectedClockSignal != CS_HFXTCLK_SELECT));
+
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS))
+            ;
+
+        /* Setting the divider and source */
+        CS->CTL1 = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS)
+                | (clockSource << CS_ACLK_SRC_BITPOS))
+                | (CS->CTL1 & ~(CS_CTL1_SELA_MASK | CS_CTL1_DIVA_MASK));
+
+        /* Waiting for ACLK to be ready again */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_MCLK:
+    {
+
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS))
+            ;
+
+        CS->CTL1 = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS)
+                | (clockSource << CS_MCLK_SRC_BITPOS))
+                | (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK));
+
+        /* Waiting for MCLK to be ready */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_SMCLK:
+    {
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS))
+            ;
+
+        CS->CTL1 = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS)
+                | (clockSource << CS_HSMCLK_SRC_BITPOS))
+                | (CS->CTL1 & ~(CS_CTL1_DIVS_MASK | CS_CTL1_SELS_MASK));
+
+        /* Waiting for SMCLK to be ready */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_HSMCLK:
+    {
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS))
+            ;
+
+        CS->CTL1 = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS)
+                | (clockSource << CS_HSMCLK_SRC_BITPOS))
+                | (CS->CTL1 & ~(CS_CTL1_DIVHS_MASK | CS_CTL1_SELS_MASK));
+
+        /* Waiting for HSMCLK to be ready */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    case CS_BCLK:
+    {
+
+        /* Waiting for the clock source ready bit to be valid before
+         * changing */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS))
+            ;
+
+        /* Setting the clock source and then returning
+         * (cannot divide CLK)
+         */
+        if (clockSource == CS_LFXTCLK_SELECT)
+            BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 0;
+        else if (clockSource == CS_REFOCLK_SELECT)
+            BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 1;
+        else
+            ASSERT(false);
+
+        /* Waiting for BCLK to be ready */
+        while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS))
+            ;
+
+        break;
+    }
+    default:
+    {
+        /* Should never get here */
+        ASSERT(false);
+    }
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+bool CS_startHFXT(bool bypassMode)
+{
+    return CS_startHFXTWithTimeout(bypassMode, 0);
+}
+
+bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout)
+{
+    uint32_t wHFFreqRange;
+    uint_fast8_t bNMIStatus;
+    bool boolTimeout;
+
+    /* Unlocking the CS Module */
+    CS->KEY = CS_KEY;
+
+    /* Saving status and temporarily disabling NMIs for UCS faults */
+    bNMIStatus = SysCtl_A_getNMISourceStatus() & SYSCTL_A_CS_SRC;
+    SysCtl_A_disableNMISource(SYSCTL_A_CS_SRC);
+
+    /* Determining which frequency range to use */
+    wHFFreqRange = _CSGetHFXTFrequency();
+    boolTimeout = (timeout == 0) ? false : true;
+
+    /* Setting to maximum drive strength  */
+    BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
+    CS->CTL2 = (CS->CTL2 & (~CS_CTL2_HFXTFREQ_MASK)) | (wHFFreqRange);
+
+    if (bypassMode)
+    {
+        BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 1;
+    } else
+    {
+        BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 0;
+    }
+
+    /* Starting and Waiting for frequency stabilization */
+    BITBAND_PERI(CS->CTL2, CS_CTL2_HFXT_EN_OFS) = 1;
+    while (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
+    {
+        if (boolTimeout && ((--timeout) == 0))
+            break;
+
+        BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_HFXTIFG_OFS) = 1;
+    }
+    
+    /* Setting the drive strength */
+    if (!bypassMode)
+    {
+        if (wHFFreqRange != CS_CTL2_HFXTFREQ_0)
+            BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1;
+        else
+            BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 0;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+
+    /* Enabling the NMI state */
+    SysCtl_A_enableNMISource(bNMIStatus);
+    
+    if (boolTimeout && timeout == 0)
+        return false;
+
+    return true;
+}
+
+bool CS_startLFXT(uint32_t xtDrive)
+{
+    return CS_startLFXTWithTimeout(xtDrive, 0);
+}
+
+bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout)
+{
+    uint8_t bNMIStatus;
+    bool boolBypassMode, boolTimeout;
+
+    ASSERT(lfxtFreq != 0)
+    ASSERT(
+            (xtDrive == CS_LFXT_DRIVE0) || (xtDrive == CS_LFXT_DRIVE1)
+            || (xtDrive == CS_LFXT_DRIVE2)
+            || (xtDrive == CS_LFXT_DRIVE3)
+            || (xtDrive == CS_LFXT_BYPASS));
+
+    /* Unlocking the CS Module */
+    CS->KEY = CS_KEY;
+
+    /* Saving status and temporarily disabling NMIs for UCS faults */
+    bNMIStatus = SysCtl_A_getNMISourceStatus() & SYSCTL_A_CS_SRC;
+    SysCtl_A_disableNMISource(SYSCTL_A_CS_SRC);
+    boolBypassMode = (xtDrive == CS_LFXT_BYPASS) ? true : false;
+    boolTimeout = (timeout == 0) ? false : true;
+
+    /* Setting to maximum drive strength  */
+    if (boolBypassMode)
+    {
+        BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 1;
+    } else
+    {
+        CS->CTL2 |= (CS_LFXT_DRIVE3);
+        BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 0;
+    }
+
+    /* Waiting for frequency stabilization */
+    BITBAND_PERI(CS->CTL2, CS_CTL2_LFXT_EN_OFS) = 1;
+
+    while (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
+    {
+        if (boolTimeout && ((--timeout) == 0))
+            break;
+
+        BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_LFXTIFG_OFS) = 1;
+    }
+
+    /* Setting the drive strength */
+    if (!boolBypassMode)
+    {
+        CS->CTL2 = ((CS->CTL2 & ~CS_LFXT_DRIVE3) | xtDrive);
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+
+    /* Enabling the NMI state */
+    SysCtl_A_enableNMISource(bNMIStatus);
+    
+    if (boolTimeout && timeout == 0)
+        return false;
+
+    return true;
+}
+
+void CS_enableClockRequest(uint32_t selectClock)
+{
+    ASSERT(
+            selectClock == CS_ACLK || selectClock == CS_HSMCLK
+            || selectClock == CS_SMCLK || selectClock == CS_MCLK);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    CS->CLKEN |= selectClock;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_disableClockRequest(uint32_t selectClock)
+{
+    ASSERT(
+            selectClock == CS_ACLK || selectClock == CS_HSMCLK
+            || selectClock == CS_SMCLK || selectClock == CS_MCLK);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    CS->CLKEN &= ~selectClock;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency)
+{
+    ASSERT(
+            referenceFrequency == CS_REFO_32KHZ
+            || referenceFrequency == CS_REFO_128KHZ);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS) = referenceFrequency;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_enableDCOExternalResistor(void)
+{
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 1;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_setDCOExternalResistorCalibration(uint_fast8_t calData,
+        uint_fast8_t freqRange)
+{
+    uint_fast8_t rselVal;
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK) >> CS_CTL0_DCORSEL_OFS;
+
+    CS->CTL0 &= ~CS_CTL0_DCORSEL_MASK;
+
+    if ((freqRange == CS_OVER32MHZ))
+    {
+        CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK;
+        CS->DCOERCAL1 |= (calData);
+    } else
+    {
+        CS->DCOERCAL0 &= ~CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK;
+        CS->DCOERCAL0 |= (calData) << CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS;
+    }
+
+    CS->CTL0 |= (rselVal) << CS_CTL0_DCORSEL_OFS;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+
+}
+
+void CS_disableDCOExternalResistor(void)
+{
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 0;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_setDCOCenteredFrequency(uint32_t dcoFreq)
+{
+    ASSERT(
+            dcoFreq == CS_DCO_FREQUENCY_1_5 || dcoFreq == CS_DCO_FREQUENCY_3
+            || dcoFreq == CS_DCO_FREQUENCY_6
+            || dcoFreq == CS_DCO_FREQUENCY_12
+            || dcoFreq == CS_DCO_FREQUENCY_24
+            || dcoFreq == CS_DCO_FREQUENCY_48);
+
+    /* Unlocking the CS Module */
+    CS->KEY = CS_KEY;
+
+    /* Resetting Tuning Parameters and Setting the frequency */
+    CS->CTL0 = ((CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dcoFreq);
+
+    /* Locking the CS Module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_tuneDCOFrequency(int16_t tuneParameter)
+{
+    CS->KEY = CS_KEY;
+
+    uint16_t dcoTuneMask = 0x1FFF;
+    uint16_t dcoTuneSigned = 0x1000;
+
+    dcoTuneMask = 0x3FF;
+    dcoTuneSigned = 0x200;
+
+    if (tuneParameter < 0)
+    {
+        CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter & dcoTuneMask)
+                | dcoTuneSigned);
+    } else
+    {
+        CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter & dcoTuneMask));
+    }
+
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+uint32_t CS_getDCOFrequency(void)
+{
+    float dcoConst;
+    int32_t calVal;
+    uint32_t centeredFreq;
+    int16_t dcoTune;
+    uint_fast8_t tlvLength;
+    SysCtl_A_CSCalTLV_Info *csInfo;
+    uint32_t retVal;
+
+    centeredFreq = _CSGetDOCFrequency();
+
+    /* Parsing the TLV and getting the maximum erase pulses */
+    SysCtl_A_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo);
+
+    if (tlvLength == 0)
+    {
+        return centeredFreq;
+    }
+    
+    dcoTune = CS->CTL0 & 0x3FF;
+    if (dcoTune & 0x200)
+    {
+        dcoTune = dcoTune | 0xFE00;
+    }
+
+    if (dcoTune == 0)
+        return (uint32_t) centeredFreq;
+
+    /* DCORSEL = 5  */
+    if ((centeredFreq == 48000000))
+    {
+        /* External Resistor */
+        if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+        {
+            dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
+            calVal = csInfo->rDCOER_FCAL_RSEL5;
+        }
+        /* Internal Resistor */
+        else
+        {
+            dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5);
+            calVal = csInfo->rDCOIR_FCAL_RSEL5;
+        }
+    }
+    /* DCORSEL = 4 */
+    else
+    {
+        /* External Resistor */
+        if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+        {
+            dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04);
+            calVal = csInfo->rDCOER_FCAL_RSEL04;
+        }
+        /* Internal Resistor */
+        else
+        {
+            dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04);
+            calVal = csInfo->rDCOIR_FCAL_RSEL04;
+        }
+    }
+    retVal = (uint32_t) (centeredFreq)
+            / (1 - ((dcoConst * dcoTune) / ((1 + dcoConst * (768 - calVal)))));
+
+    return retVal;
+}
+
+void CS_setDCOFrequency(uint32_t dcoFrequency)
+{
+    int32_t nomFreq, calVal, dcoSigned;
+    int16_t dcoTune;
+    float dcoConst;
+    bool rsel5 = false;
+    dcoSigned = (int32_t) dcoFrequency;
+    uint_fast8_t tlvLength;
+    SysCtl_A_CSCalTLV_Info *csInfo;
+
+    if (dcoFrequency < 2000000)
+    {
+        nomFreq = CS_15MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_1_5);
+    } else if (dcoFrequency < 4000000)
+    {
+        nomFreq = CS_3MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_3);
+    } else if (dcoFrequency < 8000000)
+    {
+        nomFreq = CS_6MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_6);
+    } else if (dcoFrequency < 16000000)
+    {
+        nomFreq = CS_12MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12);
+    } else if (dcoFrequency < 32000000)
+    {
+        nomFreq = CS_24MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_24);
+    } else if (dcoFrequency < 640000001)
+    {
+        nomFreq = CS_48MHZ;
+        CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48);
+        rsel5 = true;
+    } else
+    {
+        ASSERT(false);
+        return;
+    }
+    
+    /* Parsing the TLV and getting the maximum erase pulses */
+    SysCtl_A_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo);
+
+    if (dcoFrequency == nomFreq || tlvLength == 0)
+    {
+        CS_tuneDCOFrequency(0);
+        return;
+    }
+
+    if (rsel5)
+    {
+        /* External Resistor*/
+        if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+        {
+            dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5);
+            calVal = csInfo->rDCOER_FCAL_RSEL5;
+        }
+        /* Internal Resistor */
+        else
+        {
+            dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5);
+            calVal = csInfo->rDCOIR_FCAL_RSEL5;
+        }
+    }
+    /* DCORSEL = 4 */
+    else
+    {
+        /* External Resistor */
+        if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
+        {
+            dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04);
+            calVal = csInfo->rDCOER_FCAL_RSEL04;
+        }
+        /* Internal Resistor */
+        else
+        {
+            dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04);
+            calVal = csInfo->rDCOIR_FCAL_RSEL04;
+        }
+    }
+
+    dcoTune = (int16_t) (((dcoSigned - nomFreq)
+            * (1.0f + dcoConst * (768.0f - calVal))) / (dcoSigned * dcoConst));
+
+    CS_tuneDCOFrequency(dcoTune);
+
+}
+
+uint32_t CS_getBCLK(void)
+{
+    if (BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS))
+        return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1);
+    else
+        return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
+}
+
+uint32_t CS_getHSMCLK(void)
+{
+    uint32_t wSource, wDivider;
+
+    wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS;
+    wDivider = ((CS->CTL1 & CS_CTL1_DIVHS_MASK) << CS_HSMCLK_DIV_BITPOS);
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+}
+
+uint32_t CS_getACLK(void)
+{
+    uint32_t wSource, wDivider;
+
+    wSource = (CS->CTL1 & CS_CTL1_SELA_MASK) >> CS_ACLK_SRC_BITPOS;
+    wDivider = ((CS->CTL1 & CS_CTL1_DIVA_MASK) << CS_ACLK_DIV_BITPOS);
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+}
+
+uint32_t CS_getSMCLK(void)
+{
+    uint32_t wDivider, wSource;
+
+    wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS;
+    wDivider = ((CS->CTL1 & CS_CTL1_DIVS_MASK));
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+
+}
+
+uint32_t CS_getMCLK(void)
+{
+    uint32_t wSource, wDivider;
+
+    wSource = (CS->CTL1 & CS_CTL1_SELM_MASK) << CS_MCLK_SRC_BITPOS;
+    wDivider = ((CS->CTL1 & CS_CTL1_DIVM_MASK) << CS_MCLK_DIV_BITPOS);
+
+    return _CSComputeCLKFrequency(wSource, wDivider);
+}
+
+void CS_enableFaultCounter(uint_fast8_t counterSelect)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 1;
+    } else
+    {
+        BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 1;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_disableFaultCounter(uint_fast8_t counterSelect)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 0;
+    } else
+    {
+        BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 0;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_resetFaultCounter(uint_fast8_t counterSelect)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTHF_OFS) = 1;
+    } else
+    {
+        BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTLF_OFS) = 1;
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue)
+{
+    ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER ||
+            counterSelect == CS_HFXT_FAULT_COUNTER);
+
+    ASSERT(countValue == CS_FAULT_COUNTER_4096_CYCLES ||
+            countValue == CS_FAULT_COUNTER_8192_CYCLES ||
+            countValue == CS_FAULT_COUNTER_16384_CYCLES ||
+            countValue == CS_FAULT_COUNTER_32768_CYCLES);
+
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    if (counterSelect == CS_HFXT_FAULT_COUNTER)
+    {
+        CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTHF_MASK) | (countValue << 4));
+    } else
+    {
+        CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTLF_MASK) | (countValue));
+    }
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_enableInterrupt(uint32_t flags)
+{
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    CS->IE |= flags;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_disableInterrupt(uint32_t flags)
+{
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    CS->IE &= ~flags;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+uint32_t CS_getInterruptStatus(void)
+{
+    return CS->IFG;
+}
+
+uint32_t CS_getEnabledInterruptStatus(void)
+{
+    return CS_getInterruptStatus() & CS->IE;
+}
+
+void CS_clearInterruptFlag(uint32_t flags)
+{
+    /* Unlocking the module */
+    CS->KEY = CS_KEY;
+
+    CS->CLRIFG |= flags;
+
+    /* Locking the module */
+    BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1;
+}
+
+void CS_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_CS, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_CS);
+}
+
+void CS_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_CS);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_CS);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/cs.h

@@ -0,0 +1,837 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __CS_H__
+#define __CS_H__
+
+//*****************************************************************************
+//
+//! \addtogroup cs_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define CS_CLOCK_DIVIDER_1 CS_CTL1_DIVS_0
+#define CS_CLOCK_DIVIDER_2 CS_CTL1_DIVS_1
+#define CS_CLOCK_DIVIDER_4 CS_CTL1_DIVS_2
+#define CS_CLOCK_DIVIDER_8 CS_CTL1_DIVS_3
+#define CS_CLOCK_DIVIDER_16 CS_CTL1_DIVS_4
+#define CS_CLOCK_DIVIDER_32 CS_CTL1_DIVS_5
+#define CS_CLOCK_DIVIDER_64 CS_CTL1_DIVS_6
+#define CS_CLOCK_DIVIDER_128 CS_CTL1_DIVS_7
+
+#define CS_LFXTCLK_SELECT   CS_CTL1_SELM_0
+#define CS_HFXTCLK_SELECT   CS_CTL1_SELM_5
+#define CS_VLOCLK_SELECT    CS_CTL1_SELM_1
+#define CS_REFOCLK_SELECT   CS_CTL1_SELM_2
+#define CS_DCOCLK_SELECT    CS_CTL1_SELM_3
+#define CS_MODOSC_SELECT    CS_CTL1_SELM_4
+
+#define CS_KEY 0x695A
+
+/* Number of positions to shift for divider calculation */
+#define CS_ACLK_DIV_BITPOS 0x04
+#define CS_MCLK_DIV_BITPOS 0x0C
+#define CS_SMCLK_DIV_BITPOS 0x00
+#define CS_HSMCLK_DIV_BITPOS 0x08
+
+/* Number of positions to shift for source calculation */
+#define CS_ACLK_SRC_BITPOS 0x08
+#define CS_MCLK_SRC_BITPOS 0x00
+#define CS_SMCLK_SRC_BITPOS 0x04
+#define CS_HSMCLK_SRC_BITPOS 0x04
+
+/* REFO Clock Values */
+#define CS_REFO_32KHZ 0x00
+#define CS_REFO_128KHZ 0x01
+
+/* Frequency Values */
+#define CS_VLOCLK_FREQUENCY 10000
+#define CS_MODCLK_FREQUENCY 24000000
+
+/* Interrupts */
+#define CS_LFXT_FAULT   CS_IE_LFXTIE
+#define CS_HFXT_FAULT   CS_IE_HFXTIE
+#define CS_DCO_OPEN_FAULT   CS_IE_DCOR_OPNIE
+#define CS_STARTCOUNT_LFXT_FAULT   CS_IE_FCNTLFIE
+#define CS_STARTCOUNT_HFXT_FAULT   CS_IE_FCNTHFIE
+#define CS_DCO_SHORT_FAULT   CS_IFG_DCOR_SHTIFG
+
+#define CS_HFXT_DRIVE CS_CTL2_HFXTDRIVE
+#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS
+
+#define CS_LFXT_DRIVE0 CS_CTL2_LFXTDRIVE_0
+#define CS_LFXT_DRIVE1 CS_CTL2_LFXTDRIVE_1
+#define CS_LFXT_DRIVE2 CS_CTL2_LFXTDRIVE_2
+#define CS_LFXT_DRIVE3 CS_CTL2_LFXTDRIVE_3
+#define CS_LFXT_BYPASS CS_CTL2_LFXTBYPASS
+
+#define CS_ACLK CS_CLKEN_ACLK_EN
+#define CS_MCLK CS_CLKEN_MCLK_EN
+#define CS_SMCLK CS_CLKEN_SMCLK_EN
+#define CS_HSMCLK CS_CLKEN_HSMCLK_EN
+#define CS_BCLK CS_STAT_BCLK_READY
+
+#define CS_LFXTCLK  0x01
+
+#define CS_1MHZ 1000000
+#define CS_15MHZ 1500000
+#define CS_3MHZ 3000000
+#define CS_4MHZ 4000000
+#define CS_6MHZ 6000000
+#define CS_8MHZ 8000000
+#define CS_12MHZ 12000000
+#define CS_16MHZ 16000000
+#define CS_24MHZ 24000000
+#define CS_32MHZ 32000000
+#define CS_40MHZ 40000000
+#define CS_48MHZ 48000000
+
+#define CS_DCO_FREQUENCY_1_5 CS_CTL0_DCORSEL_0
+#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1
+#define CS_DCO_FREQUENCY_6 CS_CTL0_DCORSEL_2
+#define CS_DCO_FREQUENCY_12 CS_CTL0_DCORSEL_3
+#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
+#define CS_DCO_FREQUENCY_48 CS_CTL0_DCORSEL_5
+
+#define CS_HFXT_FAULT_COUNTER 0x01
+#define CS_LFXT_FAULT_COUNTER 0x02
+
+#define CS_FAULT_COUNTER_4096_CYCLES CS_CTL3_FCNTLF_0
+#define CS_FAULT_COUNTER_8192_CYCLES CS_CTL3_FCNTLF_1
+#define CS_FAULT_COUNTER_16384_CYCLES CS_CTL3_FCNTLF_2
+#define CS_FAULT_COUNTER_32768_CYCLES CS_CTL3_FCNTLF_3
+
+#define CS_OVER32MHZ    0x01
+#define CS_UNDER32MHZ   0x02
+
+/* Accounting for cross peripheral calls with predefines */
+#ifndef __MCU_HAS_SYSCTL_A__
+
+#define SysCtl_A_getNMISourceStatus SysCtl_getNMISourceStatus
+#define SysCtl_A_disableNMISource SysCtl_disableNMISource
+#define SysCtl_A_getNMISourceStatus SysCtl_getNMISourceStatus
+#define SysCtl_A_enableNMISource SysCtl_enableNMISource
+#define SysCtl_A_getTLVInfo SysCtl_getTLVInfo
+#define SYSCTL_A_CS_SRC SYSCTL_CS_SRC
+#define SysCtl_A_CSCalTLV_Info SysCtl_CSCalTLV_Info
+
+#endif
+
+
+//******************************************************************************
+//
+//! This function sets the external clock sources LFXT and HFXT crystal
+//! oscillator frequency values. This function must be called if an external
+//! crystal LFXT or HFXT is used and the user intends to call
+//! CS_getSMCLK, CS_getMCLK, CS_getBCLK,  CS_getHSMCLK, CS_getACLK and
+//! any of the HFXT oscillator control functions
+//!
+//! \param lfxt_XT_CLK_frequency is the LFXT crystal frequencies in Hz
+//! \param hfxt_XT_CLK_frequency is the HFXT crystal frequencies in Hz
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency,
+        uint32_t hfxt_XT_CLK_frequency);
+
+//******************************************************************************
+//
+//! This function initializes each of the clock signals. The user must ensure
+//! that this function is called for each clock signal. If not, the default
+//! state is assumed for the particular clock signal. Refer to DriverLib
+//! documentation for CS module or Device Family User's Guide for details of
+//! default clock signal states. 
+//!
+//! Note that this function is blocking and will wait on the appropriate bit
+//! to be set in the CSSTAT READY register to be set before setting the clock
+//! source.
+//!
+//! Also note that when HSMCLK and SMCLK share the same clock signal. If you
+//! change the clock signal for HSMCLK, the clock signal for SMCLK will change
+//! also (and vice-versa).
+//!
+//! HFXTCLK is not available for BCLK or ACLK.
+//!
+//! \param selectedClockSignal Clock signal to initialize.
+//!           - \b CS_ACLK,
+//!           - \b CS_MCLK,
+//!           - \b CS_HSMCLK
+//!           - \b CS_SMCLK
+//!           - \b CS_BCLK  [clockSourceDivider is ignored for this parameter]
+//! \param clockSource  Clock source for the selectedClockSignal signal.
+//!            - \b CS_LFXTCLK_SELECT,
+//!            - \b CS_HFXTCLK_SELECT,
+//!            - \b CS_VLOCLK_SELECT,     [Not available for BCLK]
+//!            - \b CS_DCOCLK_SELECT,     [Not available for ACLK, BCLK]
+//!            - \b CS_REFOCLK_SELECT,
+//!            - \b CS_MODOSC_SELECT      [Not available for ACLK, BCLK]
+//! \param clockSourceDivider - selected the clock divider to calculate
+//!         clock signal from clock source. This parameter is ignored when
+//!         setting BLCK. Valid values are:
+//!           - \b CS_CLOCK_DIVIDER_1,
+//!           - \b CS_CLOCK_DIVIDER_2,
+//!           - \b CS_CLOCK_DIVIDER_4,
+//!           - \b CS_CLOCK_DIVIDER_8,
+//!           - \b CS_CLOCK_DIVIDER_16,
+//!           - \b CS_CLOCK_DIVIDER_32,
+//!           - \b CS_CLOCK_DIVIDER_64,
+//!           - \b CS_CLOCK_DIVIDER_128
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_initClockSignal(uint32_t selectedClockSignal,
+        uint32_t clockSource, uint32_t clockSourceDivider);
+
+//******************************************************************************
+//
+//! Initializes the HFXT crystal oscillator, which supports crystal frequencies
+//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared, with no timeout. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function.
+//!
+//! \param bypassMode When this variable is set, the oscillator will start
+//! in bypass mode and the signal can be generated by a digital square wave.
+//!
+//! \return true if started correctly, false otherwise
+//
+//******************************************************************************
+extern bool CS_startHFXT(bool bypassMode);
+
+//******************************************************************************
+//
+//! Initializes the HFXT crystal oscillator, which supports crystal frequencies
+//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared, with no timeout. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function. This function has a timeout associated with
+//! stabilizing the oscillator.
+//!
+//! \param bypassMode When this variable is set, the oscillator will start
+//! in bypass mode and the signal can be generated by a digital square wave.
+//!
+//! \param timeout is the count value that gets decremented every time the loop
+//!         that clears oscillator fault flags gets executed.
+//!
+//! \return true if started correctly, false otherwise
+//
+//******************************************************************************
+extern bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout);
+
+//******************************************************************************
+//
+//! Initializes the LFXT crystal oscillator, which supports crystal frequencies
+//! up to 50kHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared, with no timeout. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function.
+//!
+//! \param xtDrive is the target drive strength for the LFXT crystal
+//!                  oscillator.
+//!      Valid values are:
+//!         - \b CS_LFXT_DRIVE0,
+//!         - \b CS_LFXT_DRIVE1,
+//!         - \b CS_LFXT_DRIVE2,
+//!         - \b CS_LFXT_DRIVE3,  [Default Value]
+//!         - \b CS_LFXT_BYPASS
+//!
+//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start
+//! in bypass mode and the signal can be generated by a digital square wave.
+//!
+//! \return true if started correctly, false otherwise
+//
+//******************************************************************************
+extern bool CS_startLFXT(uint32_t xtDrive);
+
+//******************************************************************************
+//
+//! Initializes the LFXT crystal oscillator, which supports crystal frequencies
+//! up to 50kHz, depending on the selected drive strength. Loops
+//! until all oscillator fault flags are cleared. See the
+//! device-specific data sheet for appropriate drive settings. NOTE: User must
+//! call CS_setExternalClockSourceFrequency to set frequency of external clocks
+//! before calling this function. This function has a timeout associated with
+//! stabilizing the oscillator.
+//!
+//! \param xtDrive is the target drive strength for the LFXT crystal
+//!                  oscillator.
+//!      Valid values are:
+//!         - \b CS_LFXT_DRIVE0,
+//!         - \b CS_LFXT_DRIVE1,
+//!         - \b CS_LFXT_DRIVE2,
+//!         - \b CS_LFXT_DRIVE3,  [Default Value]
+//!         - \b CS_LFXT_BYPASS
+//!
+//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will
+//! start in bypass mode and the signal can be generated by a digital square
+//! wave.
+//!
+//! \param timeout is the count value that gets decremented every time the loop
+//!         that clears oscillator fault flags gets executed.
+//!
+//! \return true if started correctly, false otherwise
+//
+//******************************************************************************
+extern bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout);
+
+//******************************************************************************
+//
+//! Selects between the frequency of the internal REFO clock source
+//!
+//! \param referenceFrequency selects between the valid frequencies:
+//!        - \b CS_REFO_32KHZ,
+//!        - \b CS_REFO_128KHZ,
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency);
+
+//******************************************************************************
+//
+//! Enables conditional module requests
+//!
+//! \param selectClock selects specific request enables. Valid values are
+//!        are a logical OR of the following values:
+//!        - \b CS_ACLK,
+//!        - \b CS_HSMCLK,
+//!        - \b CS_SMCLK,
+//!        - \b CS_MCLK
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_enableClockRequest(uint32_t selectClock);
+
+//******************************************************************************
+//
+//! Disables conditional module requests
+//!
+//! \param selectClock selects specific request disables. Valid values are
+//!        are a logical OR of the following values:
+//!        - \b CS_ACLK,
+//!        - \b CS_HSMCLK,
+//!        - \b CS_SMCLK,
+//!        - \b CS_MCLK
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_disableClockRequest(uint32_t selectClock);
+
+//******************************************************************************
+//
+//! Get the current ACLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! \link CS_setExternalClockSourceFrequency() \endlink API was invoked before
+//! in case LFXT is being used.
+//!
+//! \return Current ACLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getACLK(void);
+
+//******************************************************************************
+//
+//! Get the current SMCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or
+//! HFXT is being used.
+//!
+//! \return Current SMCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getSMCLK(void);
+
+//******************************************************************************
+//
+//! Get the current MCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or
+//! HFXT is being used.
+//!
+//! \return Current MCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getMCLK(void);
+
+//******************************************************************************
+//
+//! Get the current BCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in
+//! case LFXT or HFXT is being used.
+//!
+//! \return Current BCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getBCLK(void);
+
+//******************************************************************************
+//
+//! Get the current HSMCLK frequency.
+//!
+//! If a oscillator fault is set, the frequency returned will be based on the
+//! fail safe mechanism of CS module. The user of this API must ensure that
+//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in
+//! case LFXT or HFXT is being used.
+//!
+//! \return Current HSMCLK frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getHSMCLK(void);
+
+//******************************************************************************
+//
+//! Sets the centered frequency of DCO operation.  Each frequency represents
+//! the centred frequency of a particular frequency range. Further tuning can
+//! be achieved by using the CS_tuneDCOFrequency function. Note that setting
+//! the nominal frequency will reset the tuning parameters.
+//!
+//! \param dcoFreq selects between the valid frequencies:
+//!        - \b CS_DCO_FREQUENCY_1_5, [1MHz to 2MHz]
+//!        - \b CS_DCO_FREQUENCY_3,   [2MHz to 4MHz]
+//!        - \b CS_DCO_FREQUENCY_6,   [4MHz to 8MHz]
+//!        - \b CS_DCO_FREQUENCY_12,  [8MHz to 16MHz]
+//!        - \b CS_DCO_FREQUENCY_24,  [16MHz to 32MHz]
+//!        - \b CS_DCO_FREQUENCY_48   [32MHz to 64MHz]
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_setDCOCenteredFrequency(uint32_t dcoFreq);
+
+//******************************************************************************
+//
+//! Automatically sets/tunes the DCO to the given frequency. Any valid value
+//! up to max frequency in the spec can be given to this function and the API
+//! will do its best to determine the correct tuning parameter.
+//!
+//! \note The frequency ranges that can be custom tuned on early release MSP432
+//! devices is limited. For further details on supported tunable frequencies,
+//! please refer to the device errata sheet or data sheet.
+//!
+//! \param dcoFrequency Frequency in Hz that the user wants to set the DCO to.
+//!
+//! \note This function uses floating point math to calculate the DCO tuning
+//!         parameter. If efficiency is a concern, the user should use the
+//!         \link FPU_enableModule \endlink function (if available) to enable
+//!         the floating point co-processor.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setDCOFrequency(uint32_t dcoFrequency);
+
+//******************************************************************************
+//
+//! Tunes the DCO to a specific frequency. Tuning of the DCO is based off of the
+//! following equation in the user's guide:
+//!
+//! See the user's guide for more detailed information about DCO tuning.
+//!
+//! \note This function is not currently available on pre-release MSP432 devices.
+//!  On early release versions of MSP432, the DCO calibration information has not been
+//!  populated making the DCO only able to operate at the pre-calibrated centered 
+//!  frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
+//!  function. While this function will be added on the final devices being released,
+//!  for early silicon please default to the pre-calibrated DCO center frequencies.
+//!
+//! \param tuneParameter Tuning parameter in 2's Compliment representation.
+//!  Can be negative or positive.
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_tuneDCOFrequency(int16_t tuneParameter);
+
+//******************************************************************************
+//
+//! Enables the external resistor for DCO operation
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_enableDCOExternalResistor(void);
+
+//******************************************************************************
+//
+//! Disables the external resistor for DCO operation
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_disableDCOExternalResistor(void);
+
+//******************************************************************************
+//
+//! Sets the calibration value for the DCO when using the external resistor
+//! mode. This value is used for tuning the DCO to custom frequencies. By
+//! default, the value in the CS module is populated by the calibration
+//! data of the suggested external resistor (see device datasheet).
+//!
+//! \param calData is the calibration data constant for the external resistor.
+//!
+//! \param freqRange is the range of the DCO to set the external calibration
+//!             for. Frequencies above 32MHZ have a different calibration value
+//!             than frequencies below 32MHZ.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData,
+                                                 uint_fast8_t freqRange);
+
+//******************************************************************************
+//
+//! Gets the current tuned DCO frequency. If no tuning has been done, this
+//! returns the nominal DCO frequency of the current DCO range. Note that this
+//! function will grab any constant/calibration data from the DDDS table
+//! without any user interaction needed.
+//!
+//! \note This function uses floating point math to calculate the DCO tuning
+//!         parameter. If efficiency is a concern, the user should use the
+//!         \link FPU_enableModule \endlink function (if available) to enable
+//!         the floating point co-processor.
+//!
+//! \return Current DCO frequency in Hz
+//
+//******************************************************************************
+extern uint32_t CS_getDCOFrequency(void);
+
+//******************************************************************************
+//
+//! Automatically sets/tunes the DCO to the given frequency. Any valid value
+//! up to (and including) 64Mhz can be given to this function and the API
+//! will do its best to determine the correct tuning parameter.
+//!
+//!
+//! \note This function is not currently available on pre-release MSP432 devices.
+//!  On early release versions of MSP432, the DCO calibration information has not been
+//!  populated making the DCO only able to operate at the pre-calibrated centered 
+//!  frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink
+//!  function. While this function will be added on the final devices being released,
+//!  for early silicon please default to the pre-calibrated DCO center frequencies.
+//!
+//! \param dcoFrequency Frequency in Hz (1500000 - 64000000) that the user wants
+//!         to set the DCO to.
+//!
+//! \note This function uses floating point math to calculate the DCO tuning
+//!         parameter. If efficiency is a concern, the user should use the
+//!         \link FPU_enableModule \endlink function (if available) to enable
+//!         the floating point co-processor.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void CS_setDCOFrequency(uint32_t dcoFrequency);
+
+//******************************************************************************
+//
+//! Enables the fault counter for the CS module. This function can enable
+//! either the HFXT fault counter or the LFXT fault counter.
+//!
+//! \param counterSelect selects the fault counter to enable
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_enableFaultCounter(uint_fast8_t counterSelect);
+
+//******************************************************************************
+//
+//! Disables the fault counter for the CS module. This function can disable
+//! either the HFXT fault counter or the LFXT fault counter.
+//!
+//! \param counterSelect selects the fault counter to disable
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_disableFaultCounter(uint_fast8_t counterSelect);
+
+//******************************************************************************
+//
+//! Resets the fault counter for the CS module. This function can reset
+//! either the HFXT fault counter or the LFXT fault counter.
+//!
+//! \param counterSelect selects the fault counter to reset
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_resetFaultCounter(uint_fast8_t counterSelect);
+
+//******************************************************************************
+//
+//! Sets the count for the start value of the fault counter. This function can
+//! be used to set either the HFXT count or the LFXT count.
+//!
+//! \param counterSelect selects the fault counter to reset
+//!        - \b CS_HFXT_FAULT_COUNTER
+//!        - \b CS_LFXT_FAULT_COUNTER
+//! \param countValue selects the cycles to set the fault counter to
+//!        - \b CS_FAULT_COUNTER_4096_CYCLES
+//!        - \b CS_FAULT_COUNTER_8192_CYCLES
+//!        - \b CS_FAULT_COUNTER_16384_CYCLES
+//!        - \b CS_FAULT_COUNTER_32768_CYCLES
+//!
+//! \return NONE
+//
+//******************************************************************************
+extern void CS_startFaultCounter(uint_fast8_t counterSelect,
+        uint_fast8_t countValue);
+
+//*****************************************************************************
+//
+//! Enables individual clock control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCO_OPEN_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!
+//! This function enables the indicated clock system interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual clock system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be disabled.  Must
+//! be a logical OR of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCOMIN_FAULT,
+//!                     - \b CS_DCOMAX_FAULT,
+//!                     - \b CS_DCO_OPEN_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending interrupts
+//! that are actually enabled and could have caused the ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCO_OPEN_FAULT,
+//!                     - \b CS_DCO_SHORT_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t CS_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCO_OPEN_FAULT,
+//!                     - \b CS_DCO_SHORT_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t CS_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears clock system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of:
+//!                     - \b CS_LFXT_FAULT,
+//!                     - \b CS_HFXT_FAULT,
+//!                     - \b CS_DCO_OPEN_FAULT,
+//!                     - \b CS_STARTCOUNT_LFXT_FAULT,
+//!                     - \b CS_STARTCOUNT_HFXT_FAULT,
+//!
+//! The specified clock system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the clock system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the clock
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific clock system interrupts must be enabled
+//! via CS_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via CS_clearInterruptFlag().
+//!
+//! Clock System can generate interrupts when
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the clock system.
+//!
+//! This function unregisters the handler to be called when a clock system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void CS_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif

platform/vendor_bsp/TI/MSP432P4xx/debug.h

@@ -0,0 +1,76 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long line);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+#ifdef DEBUG
+#define assert(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define assert(expr)
+#endif
+
+#endif // __DEBUG_H__

platform/vendor_bsp/TI/MSP432P4xx/dma.c

@@ -0,0 +1,850 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <stdint.h>
+
+#include <debug.h>
+#include <interrupt.h>
+#include <dma.h>
+
+void DMA_enableModule(void)
+{
+    //
+    // Set the master enable bit in the config register.
+    //
+    DMA_Control->CFG = DMA_CFG_MASTEN;
+}
+
+void DMA_disableModule(void)
+{
+    //
+    // Clear the master enable bit in the config register.
+    //
+    DMA_Control->CFG = 0;
+}
+
+uint32_t DMA_getErrorStatus(void)
+{
+    //
+    // Return the DMA error status.
+    //
+    return DMA_Control->ERRCLR;
+}
+
+void DMA_clearErrorStatus(void)
+{
+    //
+    // Clear the DMA error interrupt.
+    //
+    DMA_Control->ERRCLR = 1;
+}
+
+void DMA_enableChannel(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // Set the bit for this channel in the enable set register.
+    //
+    DMA_Control->ENASET = 1 << (channelNum & 0x0F);
+}
+
+void DMA_disableChannel(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // Set the bit for this channel in the enable clear register.
+    //
+    DMA_Control->ENACLR = 1 << (channelNum & 0x0F);
+}
+
+bool DMA_isChannelEnabled(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // AND the specified channel bit with the enable register and return the
+    // result.
+    //
+    return ((DMA_Control->ENASET & (1 << (channelNum & 0x0F))) ? true : false);
+}
+
+void DMA_setControlBase(void *controlTable)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(((uint32_t) controlTable & ~0x3FF) == (uint32_t) controlTable);
+    ASSERT((uint32_t) controlTable >= 0x20000000);
+
+    //
+    // Program the base address into the register.
+    //
+    DMA_Control->CTLBASE = (uint32_t) controlTable;
+}
+
+void* DMA_getControlBase(void)
+{
+    //
+    // Read the current value of the control base register and return it to
+    // the caller.
+    //
+    return ((void *) DMA_Control->CTLBASE);
+}
+
+void* DMA_getControlAlternateBase(void)
+{
+    //
+    // Read the current value of the control base register and return it to
+    // the caller.
+    //
+    return ((void *) DMA_Control->ATLBASE);
+}
+
+void DMA_requestChannel(uint32_t channelNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // Set the bit for this channel in the software DMA request register.
+    //
+    DMA_Control->SWREQ = 1 << (channelNum & 0x0F);
+}
+
+void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+    ASSERT(
+            (attr
+                    & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
+                            | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
+            == 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Set the useburst bit for this channel if set in config.
+    //
+    if (attr & UDMA_ATTR_USEBURST)
+    {
+        DMA_Control->USEBURSTSET = 1 << channelNum;
+    }
+
+    //
+    // Set the alternate control select bit for this channel,
+    // if set in config.
+    //
+    if (attr & UDMA_ATTR_ALTSELECT)
+    {
+        DMA_Control->ALTSET = 1 << channelNum;
+    }
+
+    //
+    // Set the high priority bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        DMA_Control->PRIOSET = 1 << channelNum;
+    }
+
+    //
+    // Set the request mask bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_REQMASK)
+    {
+        DMA_Control->REQMASKSET = 1 << channelNum;
+    }
+}
+
+void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+    ASSERT(
+            (attr
+                    & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT
+                            | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK))
+            == 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Clear the useburst bit for this channel if set in config.
+    //
+    if (attr & UDMA_ATTR_USEBURST)
+    {
+        DMA_Control->USEBURSTCLR = 1 << channelNum;
+    }
+
+    //
+    // Clear the alternate control select bit for this channel, if set in
+    // config.
+    //
+    if (attr & UDMA_ATTR_ALTSELECT)
+    {
+        DMA_Control->ALTCLR = 1 << channelNum;
+    }
+
+    //
+    // Clear the high priority bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_HIGH_PRIORITY)
+    {
+        DMA_Control->PRIOCLR = 1 << channelNum;
+    }
+
+    //
+    // Clear the request mask bit for this channel, if set in config.
+    //
+    if (attr & UDMA_ATTR_REQMASK)
+    {
+        DMA_Control->REQMASKCLR = 1 << channelNum;
+    }
+}
+
+uint32_t DMA_getChannelAttribute(uint32_t channelNum)
+{
+    uint32_t attr = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Check to see if useburst bit is set for this channel.
+    //
+    if (DMA_Control->USEBURSTSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_USEBURST;
+    }
+
+    //
+    // Check to see if the alternate control bit is set for this channel.
+    //
+    if (DMA_Control->ALTSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_ALTSELECT;
+    }
+
+    //
+    // Check to see if the high priority bit is set for this channel.
+    //
+    if (DMA_Control->PRIOSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_HIGH_PRIORITY;
+    }
+
+    //
+    // Check to see if the request mask bit is set for this channel.
+    //
+    if (DMA_Control->REQMASKSET & (1 << channelNum))
+    {
+        attr |= UDMA_ATTR_REQMASK;
+    }
+
+    //
+    // Return the configuration flags.
+    //
+    return (attr);
+}
+
+void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control)
+{
+    DMA_ControlTable *pCtl;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 64);
+    ASSERT(DMA_Control->CTLBASE != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    pCtl = (DMA_ControlTable *) DMA_Control->CTLBASE;
+
+    //
+    // Get the current control word value and mask off the fields to be
+    // changed, then OR in the new settings.
+    //
+    pCtl[channelStructIndex].control = ((pCtl[channelStructIndex].control
+            & ~(UDMA_CHCTL_DSTINC_M | UDMA_CHCTL_DSTSIZE_M | UDMA_CHCTL_SRCINC_M
+                    | UDMA_CHCTL_SRCSIZE_M | UDMA_CHCTL_ARBSIZE_M
+                    | UDMA_CHCTL_NXTUSEBURST)) | control);
+}
+
+void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode,
+        void *srcAddr, void *dstAddr, uint32_t transferSize)
+{
+    DMA_ControlTable *controlTable;
+    uint32_t control;
+    uint32_t increment;
+    uint32_t bufferBytes;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 64);
+    ASSERT(DMA->CTLBASE != 0);
+    ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER);
+    ASSERT((transferSize != 0) && (transferSize <= 1024));
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
+
+    //
+    // Get the current control word value and mask off the mode and size
+    // fields.
+    //
+    control = (controlTable[channelStructIndex].control
+            & ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // Adjust the mode if the alt control structure is selected.
+    //
+    if (channelStructIndex & UDMA_ALT_SELECT)
+    {
+        if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
+                || (mode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            mode |= UDMA_MODE_ALT_SELECT;
+        }
+    }
+
+    //
+    // Set the transfer size and mode in the control word (but don't write the
+    // control word yet as it could kick off a transfer).
+    //
+    control |= mode | ((transferSize - 1) << 4);
+
+    //
+    // Get the address increment value for the source, from the control word.
+    //
+    increment = (control & UDMA_CHCTL_SRCINC_M);
+
+    //
+    // Compute the ending source address of the transfer.  If the source
+    // increment is set to none, then the ending address is the same as the
+    // beginning.
+    //
+    if (increment != UDMA_SRC_INC_NONE)
+    {
+        increment = increment >> 26;
+        bufferBytes = transferSize << increment;
+        srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes - 1);
+    }
+
+    //
+    // Load the source ending address into the control block.
+    //
+    controlTable[channelStructIndex].srcEndAddr = srcAddr;
+
+    //
+    // Get the address increment value for the destination, from the control
+    // word.
+    //
+    increment = control & UDMA_CHCTL_DSTINC_M;
+
+    //
+    // Compute the ending destination address of the transfer.  If the
+    // destination increment is set to none, then the ending address is the
+    // same as the beginning.
+    //
+    if (increment != UDMA_DST_INC_NONE)
+    {
+        //
+        // There is a special case if this is setting up a scatter-gather
+        // transfer.  The destination pointer must point to the end of
+        // the alternate structure for this channel instead of calculating
+        // the end of the buffer in the normal way.
+        //
+        if ((mode == UDMA_MODE_MEM_SCATTER_GATHER)
+                || (mode == UDMA_MODE_PER_SCATTER_GATHER))
+        {
+            dstAddr = (void *) &controlTable[channelStructIndex
+                    | UDMA_ALT_SELECT].spare;
+        }
+        //
+        // Not a scatter-gather transfer, calculate end pointer normally.
+        //
+        else
+        {
+            increment = increment >> 30;
+            bufferBytes = transferSize << increment;
+            dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes - 1);
+        }
+    }
+
+    //
+    // Load the destination ending address into the control block.
+    //
+    controlTable[channelStructIndex].dstEndAddr = dstAddr;
+
+    //
+    // Write the new control word value.
+    //
+    controlTable[channelStructIndex].control = control;
+}
+
+void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount,
+        void *taskList, uint32_t isPeriphSG)
+{
+    DMA_ControlTable *controlTable;
+    DMA_ControlTable *pTaskTable;
+
+    //
+    // Check the parameters
+    //
+    ASSERT((channelNum & 0xffff) < 8);
+    ASSERT(DMA->CTLBASE != 0);
+    ASSERT(taskList != 0);
+    ASSERT(taskCount <= 1024);
+    ASSERT(taskCount != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelNum parameter, extract just the channel number
+    // from this parameter.
+    //
+    channelNum &= 0x0F;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
+
+    //
+    // Get a handy pointer to the task list
+    //
+    pTaskTable = (DMA_ControlTable *) taskList;
+
+    //
+    // Compute the ending address for the source pointer.  This address is the
+    // last element of the last task in the task table
+    //
+    controlTable[channelNum].srcEndAddr = &pTaskTable[taskCount - 1].spare;
+
+    //
+    // Compute the ending address for the destination pointer.  This address
+    // is the end of the alternate structure for this channel.
+    //
+    controlTable[channelNum].dstEndAddr = &controlTable[channelNum
+            | UDMA_ALT_SELECT].spare;
+
+    //
+    // Compute the control word.  Most configurable items are fixed for
+    // scatter-gather.  Item and increment sizes are all 32-bit and arb
+    // size must be 4.  The count is the number of items in the task list
+    // times 4 (4 words per task).
+    //
+    controlTable[channelNum].control = (UDMA_CHCTL_DSTINC_32
+            | UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_SRCINC_32
+            | UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_ARBSIZE_4
+            | (((taskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S)
+            | (isPeriphSG ?
+            UDMA_CHCTL_XFERMODE_PER_SG :
+                            UDMA_CHCTL_XFERMODE_MEM_SG));
+
+    //
+    // Scatter-gather operations can leave the alt bit set.  So if doing
+    // back to back scatter-gather transfers, the second attempt may not
+    // work correctly because the alt bit is set.  Therefore, clear the
+    // alt bit here to ensure that it is always cleared before a new SG
+    // transfer is started.
+    //
+    DMA_Control->ALTCLR = 1 << channelNum;
+}
+
+uint32_t DMA_getChannelSize(uint32_t channelStructIndex)
+{
+    DMA_ControlTable *controlTable;
+    uint32_t control;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 16);
+    ASSERT(DMA->CTLBASE != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
+
+    //
+    // Get the current control word value and mask off all but the size field
+    // and the mode field.
+    //
+    control = (controlTable[channelStructIndex].control
+            & (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+    //
+    // If the size field and mode field are 0 then the transfer is finished
+    // and there are no more items to transfer
+    //
+    if (control == 0)
+    {
+        return (0);
+    }
+
+    //
+    // Otherwise, if either the size field or more field is non-zero, then
+    // not all the items have been transferred.
+    //
+    else
+    {
+        //
+        // Shift the size field and add one, then return to user.
+        //
+        return ((control >> 4) + 1);
+    }
+}
+
+uint32_t DMA_getChannelMode(uint32_t channelStructIndex)
+{
+    DMA_ControlTable *controlTable;
+    uint32_t control;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((channelStructIndex & 0xffff) < 64);
+    ASSERT(DMA->CTLBASE != 0);
+
+    //
+    // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+    // passed as the channelStructIndex parameter, extract just the channel
+    // index from this parameter.
+    //
+    channelStructIndex &= 0x3f;
+
+    //
+    // Get the base address of the control table.
+    //
+    controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE;
+
+    //
+    // Get the current control word value and mask off all but the mode field.
+    //
+    control =
+            (controlTable[channelStructIndex].control & UDMA_CHCTL_XFERMODE_M);
+
+    //
+    // Check if scatter/gather mode, and if so, mask off the alt bit.
+    //
+    if (((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER)
+            || ((control & ~UDMA_MODE_ALT_SELECT)
+                    == UDMA_MODE_PER_SCATTER_GATHER))
+    {
+        control &= ~UDMA_MODE_ALT_SELECT;
+    }
+
+    //
+    // Return the mode to the caller.
+    //
+    return (control);
+}
+
+void DMA_assignChannel(uint32_t mapping)
+{
+    switch (mapping)
+    {
+    case DMA_CH0_RESERVED0:
+    case DMA_CH0_EUSCIA0TX:
+    case DMA_CH0_EUSCIB0TX0:
+    case DMA_CH0_EUSCIB3TX1:
+    case DMA_CH0_EUSCIB2TX2:
+    case DMA_CH0_EUSCIB1TX3:
+    case DMA_CH0_TIMERA0CCR0:
+    case DMA_CH0_AESTRIGGER0:
+        DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH1_RESERVED0:
+    case DMA_CH1_EUSCIA0RX:
+    case DMA_CH1_EUSCIB0RX0:
+    case DMA_CH1_EUSCIB3RX1:
+    case DMA_CH1_EUSCIB2RX2:
+    case DMA_CH1_EUSCIB1RX3:
+    case DMA_CH1_TIMERA0CCR2:
+    case DMA_CH1_AESTRIGGER1:
+        DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH2_RESERVED0:
+    case DMA_CH2_EUSCIA1TX:
+    case DMA_CH2_EUSCIB1TX0:
+    case DMA_CH2_EUSCIB0TX1:
+    case DMA_CH2_EUSCIB3TX2:
+    case DMA_CH2_EUSCIB2TX3:
+    case DMA_CH2_TIMERA1CCR0:
+    case DMA_CH2_AESTRIGGER2:
+        DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH3_RESERVED0:
+    case DMA_CH3_EUSCIA1RX:
+    case DMA_CH3_EUSCIB1RX0:
+    case DMA_CH3_EUSCIB0RX1:
+    case DMA_CH3_EUSCIB3RX2:
+    case DMA_CH3_EUSCIB2RX3:
+    case DMA_CH3_TIMERA1CCR2:
+    case DMA_CH3_RESERVED1:
+        DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH4_RESERVED0:
+    case DMA_CH4_EUSCIA2TX:
+    case DMA_CH4_EUSCIB2TX0:
+    case DMA_CH4_EUSCIB1TX1:
+    case DMA_CH4_EUSCIB0TX2:
+    case DMA_CH4_EUSCIB3TX3:
+    case DMA_CH4_TIMERA2CCR0:
+    case DMA_CH4_RESERVED1:
+        DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH5_RESERVED0:
+    case DMA_CH5_EUSCIA2RX:
+    case DMA_CH5_EUSCIB2RX0:
+    case DMA_CH5_EUSCIB1RX1:
+    case DMA_CH5_EUSCIB0RX2:
+    case DMA_CH5_EUSCIB3RX3:
+    case DMA_CH5_TIMERA2CCR2:
+    case DMA_CH5_RESERVED1:
+        DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH6_RESERVED0:
+    case DMA_CH6_EUSCIA3TX:
+    case DMA_CH6_EUSCIB3TX0:
+    case DMA_CH6_EUSCIB2TX1:
+    case DMA_CH6_EUSCIB1TX2:
+    case DMA_CH6_EUSCIB0TX3:
+    case DMA_CH6_TIMERA3CCR0:
+    case DMA_CH6_EXTERNALPIN:
+        DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F;
+        break;
+    case DMA_CH7_RESERVED0:
+    case DMA_CH7_EUSCIA3RX:
+    case DMA_CH7_EUSCIB3RX0:
+    case DMA_CH7_EUSCIB2RX1:
+    case DMA_CH7_EUSCIB1RX2:
+    case DMA_CH7_EUSCIB0RX3:
+    case DMA_CH7_TIMERA3CCR2:
+    case DMA_CH7_ADC14:
+        DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F;
+        break;
+    default:
+        ASSERT(false);
+    }
+
+}
+
+void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel)
+{
+    ASSERT(
+            interruptNumber == DMA_INT1 || interruptNumber == DMA_INT2
+            || interruptNumber == DMA_INT3);
+
+    if (interruptNumber == DMA_INT1)
+    {
+        DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG
+                & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
+    } else if (interruptNumber == DMA_INT2)
+    {
+        DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG
+                & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
+    } else if (interruptNumber == DMA_INT3)
+    {
+        DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG
+                & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel;
+    }
+
+    /* Enabling the assigned interrupt */
+    DMA_enableInterrupt(interruptNumber);
+}
+
+void DMA_requestSoftwareTransfer(uint32_t channel)
+{
+    DMA_Channel->SW_CHTRIG |= (1 << channel);
+}
+
+uint32_t DMA_getInterruptStatus(void)
+{
+    return DMA_Channel->INT0_SRCFLG;
+}
+
+void DMA_clearInterruptFlag(uint32_t channel)
+{
+    DMA_Channel->INT0_CLRFLG |= (1 << channel);
+}
+
+void DMA_enableInterrupt(uint32_t interruptNumber)
+{
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3));
+
+    if (interruptNumber == DMA_INT1)
+    {
+        DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT2)
+    {
+        DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT3)
+    {
+        DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN;
+    }
+
+}
+
+void DMA_disableInterrupt(uint32_t interruptNumber)
+{
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3));
+
+    if (interruptNumber == DMA_INT1)
+    {
+        DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT2)
+    {
+        DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN;
+    } else if (interruptNumber == DMA_INT3)
+    {
+        DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN;
+    }
+}
+
+void DMA_registerInterrupt(uint32_t interruptNumber, void (*intHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(intHandler);
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3)
+            || (interruptNumber == DMA_INTERR));
+
+    //
+    // Register the interrupt handler.
+    //
+    Interrupt_registerInterrupt(interruptNumber, intHandler);
+
+    //
+    // Enable the memory management fault.
+    //
+    Interrupt_enableInterrupt(interruptNumber);
+
+}
+
+void DMA_unregisterInterrupt(uint32_t interruptNumber)
+{
+    ASSERT(
+            (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1)
+            || (interruptNumber == DMA_INT2)
+            || (interruptNumber == DMA_INT3)
+            || (interruptNumber == DMA_INTERR));
+
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(interruptNumber);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(interruptNumber);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/driverlib.h

@@ -0,0 +1,97 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __DRIVERLIB__H_
+#define __DRIVERLIB__H_
+
+/* Common Modules */
+#include "adc14.h"
+#include "aes256.h"
+#include "comp_e.h"
+#include "cpu.h"
+#include "crc32.h"
+#include "cs.h"
+#include "dma.h"
+#include "eusci.h"
+#include "fpu.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "interrupt.h"
+#include "mpu.h"
+#include "pcm.h"
+#include "pmap.h"
+#include "pss.h"
+#include "ref_a.h"
+#include "reset.h"
+#include "rom.h"
+#include "rom_map.h"
+#include "rtc_c.h"
+#include "spi.h"
+#include "systick.h"
+#include "timer32.h"
+#include "timer_a.h"
+#include "uart.h"
+#include "wdt_a.h"
+
+/* Specific modules for MSP432P4111 */
+#if defined(__MCU_HAS_SYSCTL_A__)
+#include "sysctl_a.h"
+#else
+#include "sysctl.h"
+#endif
+
+#if defined(__MCU_HAS_FLCTL_A__)
+#include "flash_a.h"
+#else
+#include "flash.h"
+#endif
+
+#if defined(__MCU_HAS_LCD_F__)
+#include "lcd_f.h"
+#endif
+
+/* Offset Definitions */
+#define HWREG8(x)         (*((volatile uint8_t *)(x)))
+#define HWREG16(x)        (*((volatile uint16_t *)(x)))
+#define HWREG32(x)        (*((volatile uint32_t *)(x)))
+#define HWREG(x)          (HWREG16(x))
+#define HWREG8_L(x)       (*((volatile uint8_t *)((uint8_t *)&x)))
+#define HWREG8_H(x)       (*((volatile uint8_t *)(((uint8_t *)&x)+1)))
+#define HWREG16_L(x)      (*((volatile uint16_t *)((uint16_t *)&x)))
+#define HWREG16_H(x)      (*((volatile uint16_t *)(((uint16_t *)&x)+1)))
+
+
+#endif

platform/vendor_bsp/TI/MSP432P4xx/eusci.h

@@ -0,0 +1,45 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef EUSCI_H_
+#define EUSCI_H_
+
+#include <msp.h>
+
+#define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x)
+#define EUSCI_B_CMSIS(x) ((EUSCI_B_Type *) x)
+
+#endif /* EUSCI_H_ */

platform/vendor_bsp/TI/MSP432P4xx/flash.h

@@ -0,0 +1,943 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define FLASH_BURST_PRG_BIT 0x03
+
+/* Interrupts */
+#define FLASH_PROGRAM_ERROR         FLCTL_IFG_PRG_ERR
+#define FLASH_BENCHMARK_INT         FLCTL_IFG_BMRK
+#define FLASH_ERASE_COMPLETE        FLCTL_IFG_ERASE
+#define FLASH_BRSTPRGM_COMPLETE     FLCTL_IFG_PRGB
+#define FLASH_WRDPRGM_COMPLETE      FLCTL_IFG_PRG
+#define FLASH_POSTVERIFY_FAILED     FLCTL_IFG_AVPST
+#define FLASH_PREVERIFY_FAILED      FLCTL_IFG_AVPRE
+#define FLASH_BRSTRDCMP_COMPLETE    FLCTL_IFG_RDBRST
+
+#define FLASH_NORMAL_READ_MODE            FLCTL_BANK0_RDCTL_RD_MODE_0
+#define FLASH_MARGIN0_READ_MODE           FLCTL_BANK0_RDCTL_RD_MODE_1
+#define FLASH_MARGIN1_READ_MODE           FLCTL_BANK0_RDCTL_RD_MODE_2
+#define FLASH_PROGRAM_VERIFY_READ_MODE    FLCTL_BANK0_RDCTL_RD_MODE_3
+#define FLASH_ERASE_VERIFY_READ_MODE      FLCTL_BANK0_RDCTL_RD_MODE_4
+#define FLASH_LEAKAGE_VERIFY_READ_MODE    FLCTL_BANK0_RDCTL_RD_MODE_5
+#define FLASH_MARGIN0B_READ_MODE          FLCTL_BANK0_RDCTL_RD_MODE_9
+#define FLASH_MARGIN1B_READ_MODE          FLCTL_BANK0_RDCTL_RD_MODE_10
+
+#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7
+
+#define FLASH_BANK0                 0x00
+#define FLASH_BANK1                 0x01
+#define FLASH_DATA_READ             0x00
+#define FLASH_INSTRUCTION_FETCH     0x01
+
+#define FLASH_MAIN_MEMORY_SPACE_BANK0     0x01
+#define FLASH_MAIN_MEMORY_SPACE_BANK1     0x02
+#define FLASH_INFO_MEMORY_SPACE_BANK0      0x03
+#define FLASH_INFO_MEMORY_SPACE_BANK1      0x04
+
+#define FLASH_MAIN_SPACE    FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0
+#define FLASH_INFO_SPACE    FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1
+#define FLASH_1_PATTERN FLCTL_RDBRST_CTLSTAT_DATA_CMP
+#define FLASH_0_PATTERN 0x00
+
+#define FLASH_SECTOR0               FLCTL_BANK0_MAIN_WEPROT_PROT0
+#define FLASH_SECTOR1               FLCTL_BANK0_MAIN_WEPROT_PROT1
+#define FLASH_SECTOR2               FLCTL_BANK0_MAIN_WEPROT_PROT2
+#define FLASH_SECTOR3               FLCTL_BANK0_MAIN_WEPROT_PROT3
+#define FLASH_SECTOR4               FLCTL_BANK0_MAIN_WEPROT_PROT4
+#define FLASH_SECTOR5               FLCTL_BANK0_MAIN_WEPROT_PROT5
+#define FLASH_SECTOR6               FLCTL_BANK0_MAIN_WEPROT_PROT6
+#define FLASH_SECTOR7               FLCTL_BANK0_MAIN_WEPROT_PROT7
+#define FLASH_SECTOR8               FLCTL_BANK0_MAIN_WEPROT_PROT8
+#define FLASH_SECTOR9               FLCTL_BANK0_MAIN_WEPROT_PROT9
+#define FLASH_SECTOR10              FLCTL_BANK0_MAIN_WEPROT_PROT10
+#define FLASH_SECTOR11              FLCTL_BANK0_MAIN_WEPROT_PROT11
+#define FLASH_SECTOR12              FLCTL_BANK0_MAIN_WEPROT_PROT12
+#define FLASH_SECTOR13              FLCTL_BANK0_MAIN_WEPROT_PROT13
+#define FLASH_SECTOR14              FLCTL_BANK0_MAIN_WEPROT_PROT14
+#define FLASH_SECTOR15              FLCTL_BANK0_MAIN_WEPROT_PROT15
+#define FLASH_SECTOR16              FLCTL_BANK0_MAIN_WEPROT_PROT16
+#define FLASH_SECTOR17              FLCTL_BANK0_MAIN_WEPROT_PROT17
+#define FLASH_SECTOR18              FLCTL_BANK0_MAIN_WEPROT_PROT18
+#define FLASH_SECTOR19              FLCTL_BANK0_MAIN_WEPROT_PROT19
+#define FLASH_SECTOR20              FLCTL_BANK0_MAIN_WEPROT_PROT20
+#define FLASH_SECTOR21              FLCTL_BANK0_MAIN_WEPROT_PROT21
+#define FLASH_SECTOR22              FLCTL_BANK0_MAIN_WEPROT_PROT22
+#define FLASH_SECTOR23              FLCTL_BANK0_MAIN_WEPROT_PROT23
+#define FLASH_SECTOR24              FLCTL_BANK0_MAIN_WEPROT_PROT24
+#define FLASH_SECTOR25              FLCTL_BANK0_MAIN_WEPROT_PROT25
+#define FLASH_SECTOR26              FLCTL_BANK0_MAIN_WEPROT_PROT26
+#define FLASH_SECTOR27              FLCTL_BANK0_MAIN_WEPROT_PROT27
+#define FLASH_SECTOR28              FLCTL_BANK0_MAIN_WEPROT_PROT28
+#define FLASH_SECTOR29              FLCTL_BANK0_MAIN_WEPROT_PROT29
+#define FLASH_SECTOR30              FLCTL_BANK0_MAIN_WEPROT_PROT30
+#define FLASH_SECTOR31              FLCTL_BANK0_MAIN_WEPROT_PROT31
+
+#define FLASH_NOVER     0
+#define FLASH_BURSTPOST FLCTL_PRGBRST_CTLSTAT_AUTO_PST
+#define FLASH_BURSTPRE FLCTL_PRGBRST_CTLSTAT_AUTO_PRE
+#define FLASH_REGPRE FLCTL_PRG_CTLSTAT_VER_PRE
+#define FLASH_REGPOST FLCTL_PRG_CTLSTAT_VER_PST
+#define FLASH_FULLVER (FLCTL_PRGBRST_CTLSTAT_AUTO_PST |                        \
+                    FLCTL_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_PRG_CTLSTAT_VER_PRE \
+                    | FLCTL_PRG_CTLSTAT_VER_PST)
+
+#define FLASH_COLLATED_WRITE_MODE  0x01
+#define FLASH_IMMEDIATE_WRITE_MODE 0x02
+
+#define __INFO_FLASH_TECH_START__  0x00200000
+#define __INFO_FLASH_TECH_MIDDLE__ 0x00202000
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Calculates the flash bank and sector number given an address. Stores the 
+//! results into the two pointers given as parameters. The user must provide
+//! a valid memory address (an address in SRAM for example will give an invalid
+//! result).
+//!
+//! \param addr Address to calculate the bank/sector information for
+//!
+//! \param sectorNum The sector number will be stored in here after the function
+//!                     completes.
+//!
+//! \param sectorNum The bank number will be stored in here after the function
+//!                     completes.
+//!
+//! \note For simplicity, this API only works with address in MAIN flash memory.
+//!        For calculating the sector/bank number of an address in info memory,
+//!         please refer to your device datasheet/
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *sectorNum, 
+                                uint32_t *bankNum);
+
+//*****************************************************************************
+//
+//! Enables read buffering on accesses to a specified bank of flash memory
+//!
+//! \param memoryBank is the value of the memory bank to enable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_BANK0,
+//!  - \b FLASH_BANK1
+//!
+//! \param accessMethod is the value of the access type to enable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_DATA_READ,
+//!  - \b FLASH_INSTRUCTION_FETCH
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod);
+
+//*****************************************************************************
+//
+//! Disables read buffering on accesses to a specified bank of flash memory
+//!
+//! \param memoryBank is the value of the memory bank to disable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_BANK0,
+//!  - \b FLASH_BANK1
+//!
+//! \param accessMethod is the value of the access type to disable read
+//!  buffering. Must ne only one of the following values:
+//!  - \b FLASH_DATA_READ,
+//!  - \b FLASH_INSTRUCTION_FETCH
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod);
+
+//*****************************************************************************
+//
+//! Disables program protection on the given sector mask. This setting can be
+//! applied on a sector-wise bases on a given memory space (INFO or MAIN).
+//!
+//! \param memorySpace is the value of the memory bank to disable program
+//!  protection. Must be only one of the following values:
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK1
+//!
+//! \param sectorMask is a bit mask of the sectors to disable program
+//!  protection. Must be a bitfield of the following values:
+//!  - \b FLASH_SECTOR0,
+//!  - \b FLASH_SECTOR1,
+//!  - \b FLASH_SECTOR2,
+//!  - \b FLASH_SECTOR3,
+//!  - \b FLASH_SECTOR4,
+//!  - \b FLASH_SECTOR5,
+//!  - \b FLASH_SECTOR6,
+//!  - \b FLASH_SECTOR7,
+//!  - \b FLASH_SECTOR8,
+//!  - \b FLASH_SECTOR9,
+//!  - \b FLASH_SECTOR10,
+//!  - \b FLASH_SECTOR11,
+//!  - \b FLASH_SECTOR12,
+//!  - \b FLASH_SECTOR13,
+//!  - \b FLASH_SECTOR14,
+//!  - \b FLASH_SECTOR15,
+//!  - \b FLASH_SECTOR16,
+//!  - \b FLASH_SECTOR17,
+//!  - \b FLASH_SECTOR18,
+//!  - \b FLASH_SECTOR19,
+//!  - \b FLASH_SECTOR20,
+//!  - \b FLASH_SECTOR21,
+//!  - \b FLASH_SECTOR22,
+//!  - \b FLASH_SECTOR23,
+//!  - \b FLASH_SECTOR24,
+//!  - \b FLASH_SECTOR25,
+//!  - \b FLASH_SECTOR26,
+//!  - \b FLASH_SECTOR27,
+//!  - \b FLASH_SECTOR28,
+//!  - \b FLASH_SECTOR29,
+//!  - \b FLASH_SECTOR30,
+//!  - \b FLASH_SECTOR31
+//!
+//!  \note Flash sector sizes are 4KB and the number of sectors may vary
+//!  depending on the specific device. Also, for INFO memory space, only sectors
+//!  \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
+//!
+//! \note Not all devices will contain a dedicated INFO memory. Please check the
+//!  device datasheet to see if your device has INFO memory available for use.
+//!  For devices without INFO memory, any operation related to the INFO memory 
+//!  will be ignored by the hardware.
+//!
+//! \return true if sector protection disabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace,
+        uint32_t sectorMask);
+
+//*****************************************************************************
+//
+//! Enables program protection on the given sector mask. This setting can be
+//! applied on a sector-wise bases on a given memory space (INFO or MAIN).
+//!
+//! \param memorySpace is the value of the memory bank to enable program
+//!  protection. Must be only one of the following values:
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK1
+//!
+//! \param sectorMask is a bit mask of the sectors to enable program
+//!  protection. Must be a bitfield of the following values:
+//!  - \b FLASH_SECTOR0,
+//!  - \b FLASH_SECTOR1,
+//!  - \b FLASH_SECTOR2,
+//!  - \b FLASH_SECTOR3,
+//!  - \b FLASH_SECTOR4,
+//!  - \b FLASH_SECTOR5,
+//!  - \b FLASH_SECTOR6,
+//!  - \b FLASH_SECTOR7,
+//!  - \b FLASH_SECTOR8,
+//!  - \b FLASH_SECTOR9,
+//!  - \b FLASH_SECTOR10,
+//!  - \b FLASH_SECTOR11,
+//!  - \b FLASH_SECTOR12,
+//!  - \b FLASH_SECTOR13,
+//!  - \b FLASH_SECTOR14,
+//!  - \b FLASH_SECTOR15,
+//!  - \b FLASH_SECTOR16,
+//!  - \b FLASH_SECTOR17,
+//!  - \b FLASH_SECTOR18,
+//!  - \b FLASH_SECTOR19,
+//!  - \b FLASH_SECTOR20,
+//!  - \b FLASH_SECTOR21,
+//!  - \b FLASH_SECTOR22,
+//!  - \b FLASH_SECTOR23,
+//!  - \b FLASH_SECTOR24,
+//!  - \b FLASH_SECTOR25,
+//!  - \b FLASH_SECTOR26,
+//!  - \b FLASH_SECTOR27,
+//!  - \b FLASH_SECTOR28,
+//!  - \b FLASH_SECTOR29,
+//!  - \b FLASH_SECTOR30,
+//!  - \b FLASH_SECTOR31
+//!
+//!  \note Flash sector sizes are 4KB and the number of sectors may vary
+//!  depending on the specific device. Also, for INFO memory space, only sectors
+//!  \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist.
+//!
+//! \note Not all devices will contain a dedicated INFO memory. Please check the
+//!  device datasheet to see if your device has INFO memory available for use.
+//!  For devices without INFO memory, any operation related to the INFO memory 
+//!  will be ignored by the hardware.
+//!
+//! \return true if sector protection enabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_protectSector(uint_fast8_t memorySpace,
+        uint32_t sectorMask);
+
+//*****************************************************************************
+//
+//! Returns the sector protection for given sector mask and memory space
+//!
+//! \param memorySpace is the value of the memory bank to check for program
+//!  protection. Must be only one of the following values:
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_MAIN_MEMORY_SPACE_BANK1,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK0,
+//!  - \b FLASH_INFO_MEMORY_SPACE_BANK1
+//!
+//! \param sector is the sector to check for program protection.
+//!  Must be one of the following values:
+//!  - \b FLASH_SECTOR0,
+//!  - \b FLASH_SECTOR1,
+//!  - \b FLASH_SECTOR2,
+//!  - \b FLASH_SECTOR3,
+//!  - \b FLASH_SECTOR4,
+//!  - \b FLASH_SECTOR5,
+//!  - \b FLASH_SECTOR6,
+//!  - \b FLASH_SECTOR7,
+//!  - \b FLASH_SECTOR8,
+//!  - \b FLASH_SECTOR9,
+//!  - \b FLASH_SECTOR10,
+//!  - \b FLASH_SECTOR11,
+//!  - \b FLASH_SECTOR12,
+//!  - \b FLASH_SECTOR13,
+//!  - \b FLASH_SECTOR14,
+//!  - \b FLASH_SECTOR15,
+//!  - \b FLASH_SECTOR16,
+//!  - \b FLASH_SECTOR17,
+//!  - \b FLASH_SECTOR18,
+//!  - \b FLASH_SECTOR19,
+//!  - \b FLASH_SECTOR20,
+//!  - \b FLASH_SECTOR21,
+//!  - \b FLASH_SECTOR22,
+//!  - \b FLASH_SECTOR23,
+//!  - \b FLASH_SECTOR24,
+//!  - \b FLASH_SECTOR25,
+//!  - \b FLASH_SECTOR26,
+//!  - \b FLASH_SECTOR27,
+//!  - \b FLASH_SECTOR28,
+//!  - \b FLASH_SECTOR29,
+//!  - \b FLASH_SECTOR30,
+//!  - \b FLASH_SECTOR31
+//!
+//!  Note that flash sector sizes are 4KB and the number of sectors may vary
+//!  depending on the specific device. Also, for INFO memory space, only sectors
+//!  FLASH_SECTOR0 and FLASH_SECTOR1 will exist.
+//!
+//! \note Not all devices will contain a dedicated INFO memory. Please check the
+//!  device datasheet to see if your device has INFO memory available for use.
+//!  For devices without INFO memory, any operation related to the INFO memory 
+//!  will be ignored by the hardware.
+//!
+//! \return true if sector protection enabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace,
+        uint32_t sector);
+
+//*****************************************************************************
+//
+//! Verifies a given segment of memory based off either a high (1) or low (0)
+//! state.
+//!
+//! \param verifyAddr Start address where verification will begin
+//!
+//! \param length Length in bytes to verify based off the pattern
+//!
+//! \param pattern The pattern which verification will check versus. This can
+//!  either be a low pattern (each register will be checked versus a pattern
+//!  of 32 zeros, or a high pattern (each register will be checked versus a
+//!  pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN
+//!
+//!  \note There are no sector/boundary restrictions for this function,
+//!  however it is encouraged to proved a start address aligned on 32-bit
+//!  boundaries.  Providing an unaligned address will result in unaligned data
+//!  accesses and detriment efficiency.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot verify a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return true if memory verification is successful, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length,
+        uint_fast8_t pattern);
+
+//*****************************************************************************
+//
+//!  Performs a mass erase on all unprotected flash sectors. Protected sectors
+//!  are ignored.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot erase a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return true if mass erase completes successfully, false otherwise
+//
+//*****************************************************************************
+extern bool FlashCtl_performMassErase(void);
+
+//*****************************************************************************
+//
+//!  Initiates a mass erase and returns control back to the program. This is a
+//!  non-blocking function, however it is the user's responsibility to perform
+//!  the necessary verification requirements after the interrupt is set to
+//!  signify completion. 
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashCtl_initiateMassErase(void);
+
+//*****************************************************************************
+//
+//! Erases a sector of MAIN or INFO flash memory.
+//!
+//! \param addr The start of the sector to erase. Note that with flash,
+//!         the minimum allowed size that can be erased is a flash sector
+//!         (which is 4KB on the MSP432 family). If an address is provided to
+//!         this function which is not on a 4KB boundary, the entire sector
+//!         will still be erased.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot erase a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return true if sector erase is successful, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_eraseSector(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Program a portion of flash memory with the provided data
+//!
+//! \param src Pointer to the data source to program into flash
+//!
+//! \param dest Pointer to the destination in flash to program
+//!
+//! \param length Length in bytes to program
+//!
+//!  \note There are no sector/boundary restrictions for this function,
+//!  however it is encouraged to proved a start address aligned on 32-bit
+//!  boundaries.  Providing an unaligned address will result in unaligned data
+//!  accesses and detriment efficiency.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot program a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return Whether or not the program succeeded
+//
+//*****************************************************************************
+extern bool FlashCtl_programMemory(void* src, void* dest, uint32_t length);
+
+//*****************************************************************************
+//
+//! Setups pre/post verification of burst and regular flash programming
+//! instructions. Note that this API is for advanced users that are programming
+//! their own flash drivers. The program/erase APIs are not affected by this
+//! setting and take care of the verification requirements.
+//!
+//! \param verificationSetting Verification setting to set. This value can
+//!  be a bitwise OR of the following values:
+//!     - \b FLASH_BURSTPOST,
+//!     - \b FLASH_BURSTPRE,
+//!     - \b FLASH_REGPRE,
+//!     - \b FLASH_REGPOST
+//!     - \b FLASH_NOVER No verification enabled
+//!     - \b FLASH_FULLVER Full verification enabled
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_setProgramVerification(uint32_t verificationSetting);
+
+//*****************************************************************************
+//
+//! Clears pre/post verification of burst and regular flash programming
+//! instructions. Note that this API is for advanced users that are programming
+//! their own flash drivers. The program/erase APIs are not affected by this
+//! setting and take care of the verification requirements.
+//!
+//! \param verificationSetting Verification setting to clear. This value can
+//!  be a bitwise OR of the following values:
+//!     - \b FLASH_BURSTPOST,
+//!     - \b FLASH_BURSTPRE,
+//!     - \b FLASH_REGPRE,
+//!     - \b FLASH_REGPOST
+//!     - \b FLASH_NOVER No verification enabled
+//!     - \b FLASH_FULLVER Full verification enabled
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_clearProgramVerification(uint32_t verificationSetting);
+
+//*****************************************************************************
+//
+//! Enables  word programming of flash memory.
+//!
+//! This function will enable word programming of the flash memory and set the
+//! mode of behavior when the flash write occurs.
+//!
+//! \param mode The mode specifies the behavior of the flash controller when
+//!        programming words to flash. In \b FLASH_IMMEDIATE_WRITE_MODE, the
+//!        program operation happens immediately on the write to flash while
+//!        in \b FLASH_COLLATED_WRITE_MODE the write will be delayed until a full
+//!        128-bits have been collated. Possible values include:
+//!             - \b FLASH_IMMEDIATE_WRITE_MODE
+//!             - \b FLASH_COLLATED_WRITE_MODE
+//!
+//!
+//! Refer to the user's guide for further documentation.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_enableWordProgramming(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Disables  word programming of flash memory.
+//!
+//! Refer to FlashCtl_enableWordProgramming and the user's guide for description
+//! on the difference between full word and immediate programming
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_disableWordProgramming(void);
+
+//*****************************************************************************
+//
+//! Returns if word programming mode is enabled (and if it is, the specific mode)
+//!
+//! Refer to FlashCtl_enableWordProgramming and the user's guide for description
+//! on the difference between full word and immediate programming
+//!
+//! \return a zero value if word programming is disabled,
+//!             - \b FLASH_IMMEDIATE_WRITE_MODE
+//!             - \b FLASH_COLLATED_WRITE_MODE
+//!
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_isWordProgrammingEnabled(void);
+
+//*****************************************************************************
+//
+//!  Sets the flash read mode to be used by default flash read operations.
+//!  Note that the proper wait states must be set prior to entering this
+//!   function.
+//!
+//! \param flashBank Flash bank to set read mode for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//! \param readMode The read mode to set. Valid values are:
+//!  - \b FLASH_NORMAL_READ_MODE,
+//!  - \b FLASH_MARGIN0_READ_MODE,
+//!  - \b FLASH_MARGIN1_READ_MODE,
+//!  - \b FLASH_PROGRAM_VERIFY_READ_MODE,
+//!  - \b FLASH_ERASE_VERIFY_READ_MODE,
+//!  - \b FLASH_LEAKAGE_VERIFY_READ_MODE,
+//!  - \b FLASH_MARGIN0B_READ_MODE,
+//!  - \b FLASH_MARGIN1B_READ_MODE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode);
+
+//*****************************************************************************
+//
+//!  Gets the flash read mode to be used by default flash read operations.
+//!
+//! \param flashBank Flash bank to set read mode for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//! \return Returns the read mode to set. Valid values are:
+//!  - \b FLASH_NORMAL_READ_MODE,
+//!  - \b FLASH_MARGIN0_READ_MODE,
+//!  - \b FLASH_MARGIN1_READ_MODE,
+//!  - \b FLASH_PROGRAM_VERIFY_READ_MODE,
+//!  - \b FLASH_ERASE_VERIFY_READ_MODE,
+//!  - \b FLASH_LEAKAGE_VERIFY_READ_MODE,
+//!  - \b FLASH_MARGIN0B_READ_MODE,
+//!  - \b FLASH_MARGIN1B_READ_MODE
+//!
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getReadMode(uint32_t flashBank);
+
+//*****************************************************************************
+//
+//! Changes the number of wait states that are used by the flash controller
+//! for read operations. When changing frequency ranges of the clock, this
+//! functions must be used in order to allow for readable flash memory.
+//!
+//! \param waitState The number of wait states to set. Note that only
+//!     bits 0-3 are used.
+//!
+//! \param flashBank Flash bank to set wait state for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//
+//*****************************************************************************
+extern void FlashCtl_setWaitState(uint32_t bank, uint32_t waitState);
+
+//*****************************************************************************
+//
+//! Returns the set number of flash wait states for the given flash bank.
+//!
+//! \param flashBank Flash bank to set wait state for. Valid values are:
+//!         - \b FLASH_BANK0
+//!         - \b FLASH_BANK1
+//!
+//! \return The wait state setting for the specified flash bank
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getWaitState(uint32_t bank);
+
+//*****************************************************************************
+//
+//! Enables individual flash control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! This function enables the indicated flash system interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual flash system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be disabled.  Must
+//! be a logical OR of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! This function disables the indicated flash system interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list
+//! of pending interrupts that are actually enabled and could have caused the
+//! ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears flash system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of:
+//!         - \b FLASH_PROGRAM_ERROR,
+//!         - \b FLASH_BENCHMARK_INT,
+//!         - \b FLASH_ERASE_COMPLETE,
+//!         - \b FLASH_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_WRDPRGM_COMPLETE,
+//!         - \b FLASH_POSTVERIFY_FAILED,
+//!         - \b FLASH_PREVERIFY_FAILED,
+//!         - \b FLASH_BRSTRDCMP_COMPLETE
+//!
+//! The specified flash system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for flash clock system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the clock
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific flash controller interrupts must be enabled
+//! via FlashCtl_enableInterrupt().  It is the interrupt handler's
+//! responsibility to clear the interrupt source via
+//! FlashCtl_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash system.
+//!
+//! This function unregisters the handler to be called when a clock system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_unregisterInterrupt(void);
+
+
+//*****************************************************************************
+//
+//! Initiates a sector erase of MAIN or INFO flash memory. Note that this 
+//! function simply initaites the sector erase, but does no verification
+//! which is required by the flash controller. The user must manually set
+//! and enable interrupts on the flash controller to fire on erase completion
+//! and then use the FlashCtl_verifyMemory function to verify that the sector
+//! was actually erased
+//!
+//! \param addr The start of the sector to erase. Note that with flash,
+//!         the minimum allowed size that can be erased is a flash sector
+//!         (which is 4KB on the MSP432 family). If an address is provided to
+//!         this function which is not on a 4KB boundary, the entire sector
+//!         will still be erased.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashCtl_initiateSectorErase(uint32_t addr);
+
+
+/* The following functions are advanced functions that are used by the flash
+ * driver to remask a failed bit in the event of a post or pre verification
+ * failure. They are meant to be advanced functions and should not be used
+ * by the majority of users (unless you are writing your own flash driver).
+ */
+extern uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr);
+extern uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr);
+extern uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr);
+extern uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr);
+extern void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size);
+extern void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __FLASH_H__

platform/vendor_bsp/TI/MSP432P4xx/flash_a.h

@@ -0,0 +1,850 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __FLASH_A_H__
+#define __FLASH_A_H__
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define FLASH_A_BURST_PRG_BIT 0x03
+#define FLASH_A_SECTOR_SIZE 4096
+
+/* Interrupts */
+#define FLASH_A_PROGRAM_ERROR         FLCTL_A_IFG_PRG_ERR
+#define FLASH_A_BENCHMARK_INT         FLCTL_A_IFG_BMRK
+#define FLASH_A_ERASE_COMPLETE        FLCTL_A_IFG_ERASE
+#define FLASH_A_BRSTPRGM_COMPLETE     FLCTL_A_IFG_PRGB
+#define FLASH_A_WRDPRGM_COMPLETE      FLCTL_A_IFG_PRG
+#define FLASH_A_POSTVERIFY_FAILED     FLCTL_A_IFG_AVPST
+#define FLASH_A_PREVERIFY_FAILED      FLCTL_A_IFG_AVPRE
+#define FLASH_A_BRSTRDCMP_COMPLETE    FLCTL_A_IFG_RDBRST
+
+#define FLASH_A_NORMAL_READ_MODE            FLCTL_A_BANK0_RDCTL_RD_MODE_0
+#define FLASH_A_MARGIN0_READ_MODE           FLCTL_A_BANK0_RDCTL_RD_MODE_1
+#define FLASH_A_MARGIN1_READ_MODE           FLCTL_A_BANK0_RDCTL_RD_MODE_2
+#define FLASH_A_PROGRAM_VERIFY_READ_MODE    FLCTL_A_BANK0_RDCTL_RD_MODE_3
+#define FLASH_A_ERASE_VERIFY_READ_MODE      FLCTL_A_BANK0_RDCTL_RD_MODE_4
+#define FLASH_A_LEAKAGE_VERIFY_READ_MODE    FLCTL_A_BANK0_RDCTL_RD_MODE_5
+#define FLASH_A_MARGIN0B_READ_MODE          FLCTL_A_BANK0_RDCTL_RD_MODE_9
+#define FLASH_A_MARGIN1B_READ_MODE          FLCTL_A_BANK0_RDCTL_RD_MODE_10
+
+#define FLASH_A_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7
+
+#define FLASH_A_BANK0                 0x00
+#define FLASH_A_BANK1                 0x01
+#define FLASH_A_DATA_READ             0x00
+#define FLASH_A_INSTRUCTION_FETCH     0x01
+
+#define FLASH_A_MAIN_MEMORY_SPACE_BANK0     0x01
+#define FLASH_A_MAIN_MEMORY_SPACE_BANK1     0x02
+#define FLASH_A_INFO_MEMORY_SPACE_BANK0      0x03
+#define FLASH_A_INFO_MEMORY_SPACE_BANK1      0x04
+
+#define FLASH_A_MAIN_SPACE    FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0
+#define FLASH_A_INFO_SPACE    FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1
+#define FLASH_A_1_PATTERN FLCTL_A_RDBRST_CTLSTAT_DATA_CMP
+#define FLASH_A_0_PATTERN 0x00
+
+#define FLASH_A_SECTOR0               FLCTL_A_BANK0_MAIN_WEPROT_PROT0
+#define FLASH_A_SECTOR1               FLCTL_A_BANK0_MAIN_WEPROT_PROT1
+#define FLASH_A_SECTOR2               FLCTL_A_BANK0_MAIN_WEPROT_PROT2
+#define FLASH_A_SECTOR3               FLCTL_A_BANK0_MAIN_WEPROT_PROT3
+#define FLASH_A_SECTOR4               FLCTL_A_BANK0_MAIN_WEPROT_PROT4
+#define FLASH_A_SECTOR5               FLCTL_A_BANK0_MAIN_WEPROT_PROT5
+#define FLASH_A_SECTOR6               FLCTL_A_BANK0_MAIN_WEPROT_PROT6
+#define FLASH_A_SECTOR7               FLCTL_A_BANK0_MAIN_WEPROT_PROT7
+#define FLASH_A_SECTOR8               FLCTL_A_BANK0_MAIN_WEPROT_PROT8
+#define FLASH_A_SECTOR9               FLCTL_A_BANK0_MAIN_WEPROT_PROT9
+#define FLASH_A_SECTOR10              FLCTL_A_BANK0_MAIN_WEPROT_PROT10
+#define FLASH_A_SECTOR11              FLCTL_A_BANK0_MAIN_WEPROT_PROT11
+#define FLASH_A_SECTOR12              FLCTL_A_BANK0_MAIN_WEPROT_PROT12
+#define FLASH_A_SECTOR13              FLCTL_A_BANK0_MAIN_WEPROT_PROT13
+#define FLASH_A_SECTOR14              FLCTL_A_BANK0_MAIN_WEPROT_PROT14
+#define FLASH_A_SECTOR15              FLCTL_A_BANK0_MAIN_WEPROT_PROT15
+#define FLASH_A_SECTOR16              FLCTL_A_BANK0_MAIN_WEPROT_PROT16
+#define FLASH_A_SECTOR17              FLCTL_A_BANK0_MAIN_WEPROT_PROT17
+#define FLASH_A_SECTOR18              FLCTL_A_BANK0_MAIN_WEPROT_PROT18
+#define FLASH_A_SECTOR19              FLCTL_A_BANK0_MAIN_WEPROT_PROT19
+#define FLASH_A_SECTOR20              FLCTL_A_BANK0_MAIN_WEPROT_PROT20
+#define FLASH_A_SECTOR21              FLCTL_A_BANK0_MAIN_WEPROT_PROT21
+#define FLASH_A_SECTOR22              FLCTL_A_BANK0_MAIN_WEPROT_PROT22
+#define FLASH_A_SECTOR23              FLCTL_A_BANK0_MAIN_WEPROT_PROT23
+#define FLASH_A_SECTOR24              FLCTL_A_BANK0_MAIN_WEPROT_PROT24
+#define FLASH_A_SECTOR25              FLCTL_A_BANK0_MAIN_WEPROT_PROT25
+#define FLASH_A_SECTOR26              FLCTL_A_BANK0_MAIN_WEPROT_PROT26
+#define FLASH_A_SECTOR27              FLCTL_A_BANK0_MAIN_WEPROT_PROT27
+#define FLASH_A_SECTOR28              FLCTL_A_BANK0_MAIN_WEPROT_PROT28
+#define FLASH_A_SECTOR29              FLCTL_A_BANK0_MAIN_WEPROT_PROT29
+#define FLASH_A_SECTOR30              FLCTL_A_BANK0_MAIN_WEPROT_PROT30
+#define FLASH_A_SECTOR31              FLCTL_A_BANK0_MAIN_WEPROT_PROT31
+
+#define FLASH_A_NOVER     0
+#define FLASH_A_BURSTPOST FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST
+#define FLASH_A_BURSTPRE FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE
+#define FLASH_A_REGPRE FLCTL_A_PRG_CTLSTAT_VER_PRE
+#define FLASH_A_REGPOST FLCTL_A_PRG_CTLSTAT_VER_PST
+#define FLASH_A_FULLVER (FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST |                        \
+                FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_A_PRG_CTLSTAT_VER_PRE \
+                | FLCTL_A_PRG_CTLSTAT_VER_PST)
+
+#define FLASH_A_COLLATED_WRITE_MODE  0x01
+#define FLASH_A_IMMEDIATE_WRITE_MODE 0x02
+
+/* Internal parameters/definitions */
+#define __INFO_FLASH_A_TECH_START__  0x00200000
+#define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000
+
+typedef struct __sFlashCtl_ProtectionRegister
+{
+    uint32_t B0_MAIN_R0;
+    uint32_t B0_MAIN_R1;
+    uint32_t B0_MAIN_R2;
+    uint32_t B0_MAIN_R3;
+    uint32_t B0_MAIN_R4;
+    uint32_t B0_MAIN_R5;
+    uint32_t B0_MAIN_R6;
+    uint32_t B0_MAIN_R7;
+    uint32_t B1_MAIN_R0;
+    uint32_t B1_MAIN_R1;
+    uint32_t B1_MAIN_R2;
+    uint32_t B1_MAIN_R3;
+    uint32_t B1_MAIN_R4;
+    uint32_t B1_MAIN_R5;
+    uint32_t B1_MAIN_R6;
+    uint32_t B1_MAIN_R7;
+    uint32_t B0_INFO_R0;
+    uint32_t B1_INFO_R0;
+} __FlashCtl_ProtectionRegister;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Calculates the flash bank and sector number given an address. Stores the
+//! results into the two pointers given as parameters. The user must provide
+//! a valid memory address (an address in SRAM for example will give an invalid
+//! result).
+//!
+//! \param addr Address to calculate the bank/sector information for
+//!
+//! \param sectorNum The sector number will be stored in here after the function
+//!                     completes.
+//!
+//! \param sectorNum The bank number will be stored in here after the function
+//!                     completes.
+//!
+//! \note For simplicity, this API only works with address in MAIN flash memory.
+//!        For calculating the sector/bank number of an address in info memory,
+//!         please refer to your device datasheet/
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_getMemoryInfo(uint32_t addr, uint32_t *sectorNum,
+        uint32_t *bankNum);
+
+//*****************************************************************************
+//
+//! Enables read buffering on accesses to a specified bank of flash memory
+//!
+//! \param memoryBank is the value of the memory bank to enable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_A_BANK0,
+//!  - \b FLASH_A_BANK1
+//!
+//! \param accessMethod is the value of the access type to enable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_A_DATA_READ,
+//!  - \b FLASH_A_INSTRUCTION_FETCH
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_enableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod);
+
+//*****************************************************************************
+//
+//! Disables read buffering on accesses to a specified bank of flash memory
+//!
+//! \param memoryBank is the value of the memory bank to disable read
+//!  buffering. Must be only one of the following values:
+//!  - \b FLASH_A_BANK0,
+//!  - \b FLASH_A_BANK1
+//!
+//! \param accessMethod is the value of the access type to disable read
+//!  buffering. Must ne only one of the following values:
+//!  - \b FLASH_A_DATA_READ,
+//!  - \b FLASH_A_INSTRUCTION_FETCH
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_disableReadBuffering(uint_fast8_t memoryBank,
+        uint_fast8_t accessMethod);
+
+//*****************************************************************************
+//
+//! Enables protection on the given flash memory range from writes. Note that
+//! this function only works on flash memory and giving in an address to ROM
+//! or SRAM will result in unreliable behavior.
+//!
+//! \param startAddr is the start address of the memory to protect
+//!
+//! \param endAddr is the end address of the memory to protect
+//!
+//! \note Flash memory is organized by protection by sector sizes. This means
+//!         that you will only be able to protect/unprotect memory based off
+//!         4096 aligned boundaries.
+//!
+//! \return true if sector protection enabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_protectMemory(uint32_t startAddr, uint32_t endAddr);
+
+//*****************************************************************************
+//
+//! Disables protection on the given flash memory range from writes. Note that
+//! this function only works on flash memory and giving in an address to ROM
+//! or SRAM will result in unreliable behavior.
+//!
+//! \param startAddr is the start address of the memory to unprotect
+//!
+//! \param endAddr is the end address of the memory to unprotect
+//!
+//! \note Flash memory is organized by protection by sector sizes. This means
+//!         that you will only be able to protect/unprotect memory based off
+//!         4096 aligned boundaries.
+//!
+//! \return true if sector protection enabled false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_unprotectMemory(uint32_t startAddr, uint32_t endAddr);
+
+//*****************************************************************************
+//
+//! Scans over the given memory range and returns false if any of the inclusive
+//! memory addresses is protect from writes.
+//!
+//! \param startAddr is the start address to scan
+//!
+//! \param endAddr is the end address to scan
+//!
+//! \return true if sector protection enabled on any of the incluseive memory
+//!             addresses, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_isMemoryRangeProtected(uint32_t startAddr,
+        uint32_t endAddr);
+
+//*****************************************************************************
+//
+//! Scans over the given memory range and returns false if any of the inclusive
+//! memory addresses is protect from writes.
+//!
+//! \param startAddr is the start address to scan
+//!
+//! \param endAddr is the end address to scan
+//!
+//! \return true if sector protection enabled on any of the incluseive memory
+//!             addresses, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_isMemoryProtected(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Verifies a given segment of memory based off either a high (1) or low (0)
+//! state.
+//!
+//! \param verifyAddr Start address where verification will begin
+//!
+//! \param length Length in bytes to verify based off the pattern
+//!
+//! \param pattern The pattern which verification will check versus. This can
+//!  either be a low pattern (each register will be checked versus a pattern
+//!  of 32 zeros, or a high pattern (each register will be checked versus a
+//!  pattern of 32 ones). Valid values are: FLASH_A_0_PATTERN, FLASH_A_1_PATTERN
+//!
+//!  \note There are no sector/boundary restrictions for this function,
+//!  however it is encouraged to proved a start address aligned on 32-bit
+//!  boundaries.  Providing an unaligned address will result in unaligned data
+//!  accesses and detriment efficiency.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot verify a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return true if memory verification is successful, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_verifyMemory(void* verifyAddr, uint32_t length,
+    uint_fast8_t pattern);
+
+//*****************************************************************************
+//
+//!  Performs a mass erase on all unprotected flash sectors. Protected sectors
+//!  are ignored.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot erase a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return true if mass erase completes successfully, false otherwise
+//
+//*****************************************************************************
+extern bool FlashCtl_A_performMassErase(void);
+
+//*****************************************************************************
+//
+//!  Initiates a mass erase and returns control back to the program. This is a
+//!  non-blocking function, however it is the user's responsibility to perform
+//!  the necessary verification requirements after the interrupt is set to
+//!  signify completion.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashCtl_A_initiateMassErase(void);
+
+//*****************************************************************************
+//
+//! Erases a sector of MAIN or INFO flash memory.
+//!
+//! \param addr The start of the sector to erase. Note that with flash,
+//!         the minimum allowed size that can be erased is a flash sector
+//!         (which is 4KB on the MSP432 family). If an address is provided to
+//!         this function which is not on a 4KB boundary, the entire sector
+//!         will still be erased.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot erase a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return true if sector erase is successful, false otherwise.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_eraseSector(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Program a portion of flash memory with the provided data
+//!
+//! \param src Pointer to the data source to program into flash
+//!
+//! \param dest Pointer to the destination in flash to program
+//!
+//! \param length Length in bytes to program
+//!
+//!  \note There are no sector/boundary restrictions for this function,
+//!  however it is encouraged to proved a start address aligned on 32-bit
+//!  boundaries.  Providing an unaligned address will result in unaligned data
+//!  accesses and detriment efficiency.
+//!
+//!  \note This function is blocking and will not exit until operation has
+//!  either completed or failed due to an error. Furthermore, given the
+//!  complex verification requirements of the flash controller, master
+//!  interrupts are disabled throughout execution of this function. The original
+//!  interrupt context is saved at the start of execution and restored prior
+//!  to exit of the API.
+//!
+//!  \note Due to the hardware limitations of the flash controller, this
+//!  function cannot program a memory adress in the same flash bank that it
+//!  is executing from. If using the ROM version of this API (by using the
+//!  (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides
+//!  in flash then special care needs to be taken to ensure no code execution
+//!  or reads happen in the flash bank being programmed while this API is
+//!  being executed.
+//!
+//! \return Whether or not the program succeeded
+//
+//*****************************************************************************
+extern bool FlashCtl_A_programMemory(void* src, void* dest,
+        uint32_t length);
+
+//*****************************************************************************
+//
+//! Setups pre/post verification of burst and regular flash programming
+//! instructions. Note that this API is for advanced users that are programming
+//! their own flash drivers. The program/erase APIs are not affected by this
+//! setting and take care of the verification requirements.
+//!
+//! \param verificationSetting Verification setting to set. This value can
+//!  be a bitwise OR of the following values:
+//!     - \b FLASH_A_BURSTPOST,
+//!     - \b FLASH_A_BURSTPRE,
+//!     - \b FLASH_A_REGPRE,
+//!     - \b FLASH_A_REGPOST
+//!     - \b FLASH_A_NOVER No verification enabled
+//!     - \b FLASH_A_FULLVER Full verification enabled
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_A_setProgramVerification(uint32_t verificationSetting);
+
+//*****************************************************************************
+//
+//! Clears pre/post verification of burst and regular flash programming
+//! instructions. Note that this API is for advanced users that are programming
+//! their own flash drivers. The program/erase APIs are not affected by this
+//! setting and take care of the verification requirements.
+//!
+//! \param verificationSetting Verification setting to clear. This value can
+//!  be a bitwise OR of the following values:
+//!     - \b FLASH_A_BURSTPOST,
+//!     - \b FLASH_A_BURSTPRE,
+//!     - \b FLASH_A_REGPRE,
+//!     - \b FLASH_A_REGPOST
+//!     - \b FLASH_A_NOVER No verification enabled
+//!     - \b FLASH_A_FULLVER Full verification enabled
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_A_clearProgramVerification(
+        uint32_t verificationSetting);
+
+//*****************************************************************************
+//
+//! Enables  word programming of flash memory.
+//!
+//! This function will enable word programming of the flash memory and set the
+//! mode of behavior when the flash write occurs.
+//!
+//! \param mode The mode specifies the behavior of the flash controller when
+//!        programming words to flash. In \b FLASH_A_IMMEDIATE_WRITE_MODE, the
+//!        program operation happens immediately on the write to flash while
+//!        in \b FLASH_A_COLLATED_WRITE_MODE the write will be delayed until a full
+//!        128-bits have been collated. Possible values include:
+//!             - \b FLASH_A_IMMEDIATE_WRITE_MODE
+//!             - \b FLASH_A_COLLATED_WRITE_MODE
+//!
+//!
+//! Refer to the user's guide for further documentation.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void FlashCtl_A_enableWordProgramming(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Disables  word programming of flash memory.
+//!
+//! Refer to FlashCtl_A_enableWordProgramming and the user's guide for description
+//! on the difference between full word and immediate programming
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_disableWordProgramming(void);
+
+//*****************************************************************************
+//
+//! Returns if word programming mode is enabled (and if it is, the specific mode)
+//!
+//! Refer to FlashCtl_A_enableWordProgramming and the user's guide for description
+//! on the difference between full word and immediate programming
+//!
+//! \return a zero value if word programming is disabled,
+//!             - \b FLASH_A_IMMEDIATE_WRITE_MODE
+//!             - \b FLASH_A_COLLATED_WRITE_MODE
+//!
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_A_isWordProgrammingEnabled(void);
+
+//*****************************************************************************
+//
+//!  Sets the flash read mode to be used by default flash read operations.
+//!  Note that the proper wait states must be set prior to entering this
+//!   function.
+//!
+//! \param flashBank Flash bank to set read mode for. Valid values are:
+//!         - \b FLASH_A_BANK0
+//!         - \b FLASH_A_BANK1
+//!
+//! \param readMode The read mode to set. Valid values are:
+//!  - \b FLASH_A_NORMAL_READ_MODE,
+//!  - \b FLASH_A_MARGIN0_READ_MODE,
+//!  - \b FLASH_A_MARGIN1_READ_MODE,
+//!  - \b FLASH_A_PROGRAM_VERIFY_READ_MODE,
+//!  - \b FLASH_A_ERASE_VERIFY_READ_MODE,
+//!  - \b FLASH_A_LEAKAGE_VERIFY_READ_MODE,
+//!  - \b FLASH_A_MARGIN0B_READ_MODE,
+//!  - \b FLASH_A_MARGIN1B_READ_MODE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern bool FlashCtl_A_setReadMode(uint32_t flashBank, uint32_t readMode);
+
+//*****************************************************************************
+//
+//!  Gets the flash read mode to be used by default flash read operations.
+//!
+//! \param flashBank Flash bank to set read mode for. Valid values are:
+//!         - \b FLASH_A_BANK0
+//!         - \b FLASH_A_BANK1
+//!
+//! \return Returns the read mode to set. Valid values are:
+//!  - \b FLASH_A_NORMAL_READ_MODE,
+//!  - \b FLASH_A_MARGIN0_READ_MODE,
+//!  - \b FLASH_A_MARGIN1_READ_MODE,
+//!  - \b FLASH_A_PROGRAM_VERIFY_READ_MODE,
+//!  - \b FLASH_A_ERASE_VERIFY_READ_MODE,
+//!  - \b FLASH_A_LEAKAGE_VERIFY_READ_MODE,
+//!  - \b FLASH_A_MARGIN0B_READ_MODE,
+//!  - \b FLASH_A_MARGIN1B_READ_MODE
+//!
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_A_getReadMode(uint32_t flashBank);
+
+//*****************************************************************************
+//
+//! Changes the number of wait states that are used by the flash controller
+//! for read operations. When changing frequency ranges of the clock, this
+//! functions must be used in order to allow for readable flash memory.
+//!
+//! \param waitState The number of wait states to set. Note that only
+//!     bits 0-3 are used.
+//!
+//! \param flashBank Flash bank to set wait state for. Valid values are:
+//!         - \b FLASH_A_BANK0
+//!         - \b FLASH_A_BANK1
+//!
+//
+//*****************************************************************************
+extern void FlashCtl_A_setWaitState(uint32_t bank, uint32_t waitState);
+
+//*****************************************************************************
+//
+//! Returns the set number of flash wait states for the given flash bank.
+//!
+//! \param flashBank Flash bank to set wait state for. Valid values are:
+//!         - \b FLASH_A_BANK0
+//!         - \b FLASH_A_BANK1
+//!
+//! \return The wait state setting for the specified flash bank
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_A_getWaitState(uint32_t bank);
+
+//*****************************************************************************
+//
+//! Enables individual flash control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b FLASH_A_PROGRAM_ERROR,
+//!         - \b FLASH_A_BENCHMARK_INT,
+//!         - \b FLASH_A_ERASE_COMPLETE,
+//!         - \b FLASH_A_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_A_WRDPRGM_COMPLETE,
+//!         - \b FLASH_A_POSTVERIFY_FAILED,
+//!         - \b FLASH_A_PREVERIFY_FAILED,
+//!         - \b FLASH_A_BRSTRDCMP_COMPLETE
+//!
+//! This function enables the indicated flash system interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual flash system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be disabled.  Must
+//! be a logical OR of:
+//!         - \b FLASH_A_PROGRAM_ERROR,
+//!         - \b FLASH_A_BENCHMARK_INT,
+//!         - \b FLASH_A_ERASE_COMPLETE,
+//!         - \b FLASH_A_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_A_WRDPRGM_COMPLETE,
+//!         - \b FLASH_A_POSTVERIFY_FAILED,
+//!         - \b FLASH_A_PREVERIFY_FAILED,
+//!         - \b FLASH_A_BRSTRDCMP_COMPLETE
+//!
+//! This function disables the indicated flash system interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list
+//! of pending interrupts that are actually enabled and could have caused the
+//! ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//!         - \b FLASH_A_PROGRAM_ERROR,
+//!         - \b FLASH_A_BENCHMARK_INT,
+//!         - \b FLASH_A_ERASE_COMPLETE,
+//!         - \b FLASH_A_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_A_WRDPRGM_COMPLETE,
+//!         - \b FLASH_A_POSTVERIFY_FAILED,
+//!         - \b FLASH_A_PREVERIFY_FAILED,
+//!         - \b FLASH_A_BRSTRDCMP_COMPLETE
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_A_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b FLASH_A_PROGRAM_ERROR,
+//!         - \b FLASH_A_BENCHMARK_INT,
+//!         - \b FLASH_A_ERASE_COMPLETE,
+//!         - \b FLASH_A_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_A_WRDPRGM_COMPLETE,
+//!         - \b FLASH_A_POSTVERIFY_FAILED,
+//!         - \b FLASH_A_PREVERIFY_FAILED,
+//!         - \b FLASH_A_BRSTRDCMP_COMPLETE
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t FlashCtl_A_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears flash system interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of:
+//!         - \b FLASH_A_PROGRAM_ERROR,
+//!         - \b FLASH_A_BENCHMARK_INT,
+//!         - \b FLASH_A_ERASE_COMPLETE,
+//!         - \b FLASH_A_BRSTPRGM_COMPLETE,
+//!         - \b FLASH_A_WRDPRGM_COMPLETE,
+//!         - \b FLASH_A_POSTVERIFY_FAILED,
+//!         - \b FLASH_A_PREVERIFY_FAILED,
+//!         - \b FLASH_A_BRSTRDCMP_COMPLETE
+//!
+//! The specified flash system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for flash clock system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the clock
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific flash controller interrupts must be enabled
+//! via FlashCtl_A_enableInterrupt().  It is the interrupt handler's
+//! responsibility to clear the interrupt source via
+//! FlashCtl_A_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash system.
+//!
+//! This function unregisters the handler to be called when a clock system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FlashCtl_A_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Initiates a sector erase of MAIN or INFO flash memory. Note that this
+//! function simply initaites the sector erase, but does no verification
+//! which is required by the flash controller. The user must manually set
+//! and enable interrupts on the flash controller to fire on erase completion
+//! and then use the FlashCtl_A_verifyMemory function to verify that the sector
+//! was actually erased
+//!
+//! \param addr The start of the sector to erase. Note that with flash,
+//!         the minimum allowed size that can be erased is a flash sector
+//!         (which is 4KB on the MSP432 family). If an address is provided to
+//!         this function which is not on a 4KB boundary, the entire sector
+//!         will still be erased.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashCtl_A_initiateSectorErase(uint32_t addr);
+
+/* The following functions are advanced functions that are used by the flash
+ * driver to remask a failed bit in the event of a post or pre verification
+ * failure. They are meant to be advanced functions and should not be used
+ * by the majority of users (unless you are writing your own flash driver).
+ */
+extern uint8_t __FlashCtl_A_remaskData8Post(uint8_t data, uint32_t addr);
+extern uint8_t __FlashCtl_A_remaskData8Pre(uint8_t data, uint32_t addr);
+extern uint32_t __FlashCtl_A_remaskData32Post(uint32_t data, uint32_t addr);
+extern uint32_t __FlashCtl_A_remaskData32Pre(uint32_t data, uint32_t addr);
+extern void __FlashCtl_A_remaskBurstDataPost(uint32_t addr, uint32_t size);
+extern void __FlashCtl_A_remaskBurstDataPre(uint32_t addr, uint32_t size);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __FLASH_A_H__

platform/vendor_bsp/TI/MSP432P4xx/fpu.c

@@ -0,0 +1,115 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <fpu.h>
+
+void FPU_enableModule(void)
+{
+    //
+    // Enable the coprocessors used by the floating-point unit.
+    //
+    SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK))
+            | SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK);
+}
+
+void FPU_disableModule(void)
+{
+    //
+    // Disable the coprocessors used by the floating-point unit.
+    //
+    SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK)));
+}
+
+void FPU_enableStacking(void)
+{
+    //
+    // Enable automatic state preservation for the floating-point unit, and
+    // disable lazy state preservation (meaning that the floating-point state
+    // is always stacked when floating-point instructions are used).
+    //
+    FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN_Msk) | FPU_FPCCR_ASPEN_Msk;
+}
+
+void FPU_enableLazyStacking(void)
+{
+    //
+    // Enable automatic and lazy state preservation for the floating-point
+    // unit.
+    //
+    FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
+}
+
+void FPU_disableStacking(void)
+{
+    //
+    // Disable automatic and lazy state preservation for the floating-point
+    // unit.
+    //
+    FPU->FPCCR &= ~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk);
+}
+
+void FPU_setHalfPrecisionMode(uint32_t mode)
+{
+    //
+    // Set the half-precision floating-point format.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_AHP_Msk)) | mode;
+}
+
+void FPU_setNaNMode(uint32_t mode)
+{
+    //
+    // Set the NaN mode.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_DN_Msk)) | mode;
+}
+
+void FPU_setFlushToZeroMode(uint32_t mode)
+{
+    //
+    // Set the flush-to-zero mode.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_FZ_Msk)) | mode;
+}
+
+void FPU_setRoundingMode(uint32_t mode)
+{
+    //
+    // Set the rounding mode.
+    //
+    FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_RMode_Msk)) | mode;
+}
+

platform/vendor_bsp/TI/MSP432P4xx/fpu.h

@@ -0,0 +1,285 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __FPU_H__
+#define __FPU_H__
+
+//*****************************************************************************
+//
+//!
+//! \addtogroup fpu_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Values that can be passed to FPUHalfPrecisionSet as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_HALF_IEEE           0x00000000
+#define FPU_HALF_ALTERNATE      0x04000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPU_setNaNMode as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_NAN_PROPAGATE       0x00000000
+#define FPU_NAN_DEFAULT         0x02000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPU_setFlushToZeroMode as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_FLUSH_TO_ZERO_DIS   0x00000000
+#define FPU_FLUSH_TO_ZERO_EN    0x01000000
+
+//*****************************************************************************
+//
+// Values that can be passed to FPU_setRoundingMode as the mode parameter.
+//
+//*****************************************************************************
+#define FPU_ROUND_NEAREST       0x00000000
+#define FPU_ROUND_POS_INF       0x00400000
+#define FPU_ROUND_NEG_INF       0x00800000
+#define FPU_ROUND_ZERO          0x00c00000
+
+//*****************************************************************************
+//
+//! Enables the floating-point unit.
+//!
+//! This function enables the floating-point unit, allowing the floating-point
+//! instructions to be executed.  This function must be called prior to
+//! performing any hardware floating-point operations; failure to do so results
+//! in a NOCP usage fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_enableModule(void);
+
+//*****************************************************************************
+//
+//! Disables the floating-point unit.
+//!
+//! This function disables the floating-point unit, preventing floating-point
+//! instructions from executing (generating a NOCP usage fault instead).
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_disableModule(void);
+
+//*****************************************************************************
+//
+//! Enables the stacking of floating-point registers.
+//!
+//! This function enables the stacking of floating-point registers s0-s15 when
+//! an interrupt is handled.  When enabled, space is reserved on the stack for
+//! the floating-point context and the floating-point state is saved into this
+//! stack space.  Upon return from the interrupt, the floating-point context is
+//! restored.
+//!
+//! If the floating-point registers are not stacked, floating-point
+//! instructions cannot be safely executed in an interrupt handler because the
+//! values of s0-s15 are not likely to be preserved for the interrupted code.
+//! On the other hand, stacking the floating-point registers increases the
+//! stacking operation from 8 words to 26 words, also increasing the interrupt
+//! response latency.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_enableStacking(void);
+
+//*****************************************************************************
+//
+//! Enables the lazy stacking of floating-point registers.
+//!
+//! This function enables the lazy stacking of floating-point registers s0-s15
+//! when an interrupt is handled.  When lazy stacking is enabled, space is
+//! reserved on the stack for the floating-point context, but the
+//! floating-point state is not saved.  If a floating-point instruction is
+//! executed from within the interrupt context, the floating-point context is
+//! first saved into the space reserved on the stack.  On completion of the
+//! interrupt handler, the floating-point context is only restored if it was
+//! saved (as the result of executing a floating-point instruction).
+//!
+//! This method provides a compromise between fast interrupt response (because
+//! the floating-point state is not saved on interrupt entry) and the ability
+//! to use floating-point in interrupt handlers (because the floating-point
+//! state is saved if floating-point instructions are used).
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_enableLazyStacking(void);
+
+//*****************************************************************************
+//
+//! Disables the stacking of floating-point registers.
+//!
+//! This function disables the stacking of floating-point registers s0-s15 when
+//! an interrupt is handled.  When floating-point context stacking is disabled,
+//! floating-point operations performed in an interrupt handler destroy the
+//! floating-point context of the main thread of execution.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_disableStacking(void);
+
+//*****************************************************************************
+//
+//! Selects the format of half-precision floating-point values.
+//!
+//! \param mode is the format for half-precision floating-point value, which
+//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
+//!
+//! This function selects between the IEEE half-precision floating-point
+//! representation and the Cortex-M processor alternative representation.  The
+//! alternative representation has a larger range but does not have a way to
+//! encode infinity (positive or negative) or NaN (quiet or signalling).  The
+//! default setting is the IEEE format.
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setHalfPrecisionMode(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Selects the NaN mode.
+//!
+//! \param mode is the mode for NaN results; which is 
+//! either \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
+//!
+//! This function selects the handling of NaN results during floating-point
+//! computations.  NaNs can either propagate (the default), or they can return
+//! the default NaN.
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setNaNMode(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Selects the flush-to-zero mode.
+//!
+//! \param mode is the flush-to-zero mode; which is either
+//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
+//!
+//! This function enables or disables the flush-to-zero mode of the
+//! floating-point unit.  When disabled (the default), the floating-point unit
+//! is fully IEEE compliant.  When enabled, values close to zero are treated as
+//! zero, greatly improving the execution speed at the expense of some accuracy
+//! (as well as IEEE compliance).
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setFlushToZeroMode(uint32_t mode);
+
+//*****************************************************************************
+//
+//! Selects the rounding mode for floating-point results.
+//!
+//! \param mode is the rounding mode.
+//!
+//! This function selects the rounding mode for floating-point results.  After
+//! a floating-point operation, the result is rounded toward the specified
+//! value.  The default mode is \b FPU_ROUND_NEAREST.
+//!
+//! The following rounding modes are available (as specified by \e mode):
+//!
+//! - \b FPU_ROUND_NEAREST - round toward the nearest value
+//! - \b FPU_ROUND_POS_INF - round toward positive infinity
+//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
+//! - \b FPU_ROUND_ZERO - round toward zero
+//!
+//! \note Unless this function is called prior to executing any floating-point
+//! instructions, the default mode is used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void FPU_setRoundingMode(uint32_t mode);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
+#endif // __FPU_H__

platform/vendor_bsp/TI/MSP432P4xx/gpio.c

@@ -0,0 +1,355 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <gpio.h>
+#include <debug.h>
+#include <interrupt.h>
+
+
+static const uint32_t GPIO_PORT_TO_INT[] =
+{ 0x00,
+INT_PORT1,
+INT_PORT2,
+INT_PORT3,
+INT_PORT4,
+INT_PORT5,
+INT_PORT6 };
+
+static const uint32_t GPIO_PORT_TO_BASE[] =
+{   0x00,
+    (uint32_t)P1,
+    (uint32_t)P1+1,
+    (uint32_t)P3,
+    (uint32_t)P3+1,
+    (uint32_t)P5,
+    (uint32_t)P5+1,
+    (uint32_t)P7,
+    (uint32_t)P7+1,
+    (uint32_t)P9,
+    (uint32_t)P9+1,
+    (uint32_t)PJ
+};
+
+void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
+{
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
+}
+
+
+void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
+{
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PAREN) &= ~selectedPins;
+}
+
+
+void GPIO_setAsPeripheralModuleFunctionOutputPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t mode)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins;
+    switch (mode)
+    {
+    case GPIO_PRIMARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+        break;
+    case GPIO_SECONDARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+        HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
+        break;
+    case GPIO_TERTIARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
+        break;
+    }
+}
+
+
+void GPIO_setAsPeripheralModuleFunctionInputPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t mode)
+{
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+    switch (mode)
+    {
+    case GPIO_PRIMARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+        break;
+    case GPIO_SECONDARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+        HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
+        break;
+    case GPIO_TERTIARY_MODULE_FUNCTION:
+        HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins;
+        HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins;
+        break;
+    }
+}
+
+
+void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
+}
+
+
+void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
+}
+
+
+void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PAOUT) ^= selectedPins;
+}
+
+
+void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+
+    HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins;
+}
+
+
+void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins;
+    HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins;
+}
+
+
+uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+    uint_fast16_t inputPinValue;
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    inputPinValue = HWREG16(baseAddress + OFS_LIB_PAIN) & (selectedPins);
+
+    if (inputPinValue > 0)
+        return GPIO_INPUT_PIN_HIGH;
+    return GPIO_INPUT_PIN_LOW;
+}
+
+
+void GPIO_enableInterrupt(uint_fast8_t selectedPort, uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PAIE) |= selectedPins;
+}
+
+
+void GPIO_disableInterrupt(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG16(baseAddress + OFS_LIB_PAIE) &= ~selectedPins;
+}
+
+
+uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+    return HWREG16(baseAddress + OFS_LIB_PAIFG) & selectedPins;
+}
+
+
+void GPIO_clearInterruptFlag(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+
+    HWREG16(baseAddress + OFS_LIB_PAIFG) &= ~selectedPins;
+}
+
+
+void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort,
+        uint_fast16_t selectedPins, uint_fast8_t edgeSelect)
+{
+
+    uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort];
+
+
+    if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect)
+        HWREG16(baseAddress + OFS_LIB_PAIES) &= ~selectedPins;
+    else
+        HWREG16(baseAddress + OFS_LIB_PAIES) |= selectedPins;
+}
+
+uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort)
+{
+    uint_fast16_t pendingInts;
+    uint32_t baseAddr;
+
+    pendingInts = GPIO_getInterruptStatus(selectedPort, 0xFFFF);
+    baseAddr = GPIO_PORT_TO_BASE[selectedPort];
+
+    ASSERT(baseAddr != 0xFFFF);
+
+    switch (selectedPort)
+    {
+    case GPIO_PORT_P1:
+    case GPIO_PORT_P3:
+    case GPIO_PORT_P5:
+    case GPIO_PORT_P7:
+    case GPIO_PORT_P9:
+        return (HWREG8(baseAddr + OFS_LIB_P1IE) & pendingInts);
+    case GPIO_PORT_P2:
+    case GPIO_PORT_P4:
+    case GPIO_PORT_P6:
+    case GPIO_PORT_P8:
+    case GPIO_PORT_P10:
+        return (HWREG8(baseAddr + OFS_LIB_P2IE) & pendingInts);
+    case GPIO_PORT_PJ:
+        return (HWREG16(baseAddr + OFS_LIB_PAIE) & pendingInts);
+    default:
+        return 0;
+    }
+}
+
+
+void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort,
+        uint_fast8_t selectedPins)
+{
+    uint32_t baseAddr;
+
+    baseAddr = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG8(baseAddr + OFS_LIB_PADS) |= selectedPins;
+
+}
+
+void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort,
+        uint_fast8_t selectedPins)
+{
+    uint32_t baseAddr;
+
+    baseAddr = GPIO_PORT_TO_BASE[selectedPort];
+
+    HWREG8(baseAddr + OFS_LIB_PADS) &= ~selectedPins;
+
+}
+
+void GPIO_registerInterrupt(uint_fast8_t selectedPort, void (*intHandler)(void))
+{
+    uint32_t wPortInt;
+
+    wPortInt = GPIO_PORT_TO_INT[selectedPort];
+
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(wPortInt, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(wPortInt);
+}
+
+
+void GPIO_unregisterInterrupt(uint_fast8_t selectedPort)
+{
+    uint32_t wPortInt;
+
+    wPortInt = GPIO_PORT_TO_INT[selectedPort];
+
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(wPortInt);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(wPortInt);
+}
+
+

platform/vendor_bsp/TI/MSP432P4xx/i2c.c

@@ -0,0 +1,765 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <i2c.h>
+#include <interrupt.h>
+#include <debug.h>
+
+
+void I2C_initMaster(uint32_t moduleInstance, const eUSCI_I2C_MasterConfig *config)
+{
+    uint_fast16_t preScalarValue;
+
+    ASSERT(
+            (EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource)
+            || (EUSCI_B_I2C_CLOCKSOURCE_SMCLK
+                    == config->selectClockSource));
+
+    ASSERT(
+            (EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate)
+            || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate)
+            || (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate));
+
+    ASSERT(
+            (EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration)
+            || (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG
+                    == config->autoSTOPGeneration)
+            || (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD
+                    == config->autoSTOPGeneration));
+
+    /* Disable the USCI module and clears the other bits of control register */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+            1;
+
+    /* Configure Automatic STOP condition generation */
+    EUSCI_B_CMSIS(moduleInstance)->CTLW1 =
+            (EUSCI_B_CMSIS(moduleInstance)->CTLW1 & ~EUSCI_B_CTLW1_ASTP_MASK)
+                    | (config->autoSTOPGeneration);
+
+    /* Byte Count Threshold */
+    EUSCI_B_CMSIS(moduleInstance)->TBCNT = config->byteCounterThreshold;
+
+    /*
+     * Configure as I2C master mode.
+     * UCMST = Master mode
+     * UCMODE_3 = I2C mode
+     * UCSYNC = Synchronous mode
+     */
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+            (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_B_CTLW0_SSEL_MASK)
+                    | (config->selectClockSource | EUSCI_B_CTLW0_MST
+                            | EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC
+                            | EUSCI_B_CTLW0_SWRST);
+
+    /*
+     * Compute the clock divider that achieves the fastest speed less than or
+     * equal to the desired speed.  The numerator is biased to favor a larger
+     * clock divider so that the resulting clock is always less than or equal
+     * to the desired clock, never greater.
+     */
+    preScalarValue = (uint16_t) (config->i2cClk / config->dataRate);
+
+    EUSCI_B_CMSIS(moduleInstance)->BRW = preScalarValue;
+}
+
+void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress,
+        uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable)
+{
+    ASSERT(
+            (EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset)
+            || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset)
+            || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset)
+            || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset));
+
+    /* Disable the USCI module */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+            1;
+
+    /* Clear USCI master mode */
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+            (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_MST))
+                    | (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC);
+
+    /* Set up the slave address. */
+    HWREG16((uint32_t)&EUSCI_B_CMSIS(moduleInstance)->I2COA0 + slaveAddressOffset) =
+            slaveAddress + slaveOwnAddressEnable;
+}
+
+void I2C_enableModule(uint32_t moduleInstance)
+{
+    /* Reset the UCSWRST bit to enable the USCI Module */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+            0;
+}
+
+void I2C_disableModule(uint32_t moduleInstance)
+{
+    /* Set the UCSWRST bit to disable the USCI Module */
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+            1;
+    ;
+}
+
+void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress)
+{
+    /* Set the address of the slave with which the master will communicate */
+    EUSCI_B_CMSIS(moduleInstance)->I2CSA = (slaveAddress);
+}
+
+void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode)
+{
+    ASSERT(
+            (EUSCI_B_I2C_TRANSMIT_MODE == mode)
+            || (EUSCI_B_I2C_RECEIVE_MODE == mode));
+
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+            (EUSCI_B_CMSIS(moduleInstance)->CTLW0
+                    & (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode;
+
+}
+
+uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance)
+{
+    //Set USCI in Receive mode
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TR_OFS) = 0;
+
+    //Send start
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT + EUSCI_B_CTLW0_TXSTP);
+
+    //Poll for receive interrupt flag.
+    while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
+        ;
+
+    //Send single byte data.
+    return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
+}
+
+void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData)
+{
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = transmitData;
+}
+
+uint8_t I2C_slaveGetData(uint32_t moduleInstance)
+{
+    //Read a byte.
+    return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
+}
+
+uint8_t I2C_isBusBusy(uint32_t moduleInstance)
+{
+    //Return the bus busy status.
+    return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->STATW,
+            EUSCI_B_STATW_BBUSY_OFS);
+}
+
+void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData)
+{
+    //Store current TXIE status
+    uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
+
+    //Poll for transmit interrupt flag.
+    while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
+        ;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    //Poll for transmit interrupt flag.
+    while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG))
+        ;
+
+    //Send stop condition.
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TXSTP;
+
+    //Clear transmit interrupt flag before enabling interrupt again
+    EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(EUSCI_B_IFG_TXIFG);
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
+}
+
+bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    uint_fast16_t txieStatus;
+    uint32_t timeout2 = timeout;
+
+    ASSERT(timeout > 0);
+
+    //Store current TXIE status
+    txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
+
+    //Poll for transmit interrupt flag.
+    while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) && --timeout)
+        ;
+
+    //Check if transfer timed out
+    if (timeout == 0)
+        return false;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    //Poll for transmit interrupt flag.
+    while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+            && --timeout2)
+        ;
+
+    //Check if transfer timed out
+    if (timeout2 == 0)
+        return false;
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+
+    //Clear transmit interrupt flag before enabling interrupt again
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,EUSCI_B_IFG_TXIFG0_OFS) = 0;
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData)
+{
+    //Store current transmit interrupt enable
+    uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
+
+    //Poll for transmit interrupt flag.
+    while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+        ;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
+}
+
+bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    uint_fast16_t txieStatus;
+
+    ASSERT(timeout > 0);
+
+    //Store current transmit interrupt enable
+    txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0;
+
+    //Disable transmit interrupt enable
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE,EUSCI_B_IE_TXIE0_OFS) = 0;
+
+    //Send start condition.
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR + EUSCI_B_CTLW0_TXSTT;
+
+    //Poll for transmit interrupt flag.
+    while ((!(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+            && --timeout))
+        ;
+
+    //Check if transfer timed out
+    if (timeout == 0)
+        return false;
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    //Reinstate transmit interrupt enable
+    EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData)
+{
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while
+            (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+            ;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+}
+
+bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    ASSERT(timeout > 0);
+
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+                EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
+            ;
+
+        //Check if transfer timed out
+        if (timeout == 0)
+            return false;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData)
+{
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while
+            (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+            ;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    //Poll for transmit interrupt flag.
+    while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+        ;
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+}
+
+bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance,
+        uint8_t txData, uint32_t timeout)
+{
+    uint32_t timeout2 = timeout;
+
+    ASSERT(timeout > 0);
+
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+                EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
+            ;
+
+        //Check if transfer timed out
+        if (timeout == 0)
+            return false;
+    }
+
+    //Send single byte data.
+    EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData;
+
+    //Poll for transmit interrupt flag.
+    while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+            && --timeout2)
+        ;
+
+    //Check if transfer timed out
+    if (timeout2 == 0)
+        return false;
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+
+    return true;
+}
+
+void I2C_masterSendMultiByteStop(uint32_t moduleInstance)
+{
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while
+            (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS))
+            ;
+    }
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+}
+
+bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance,
+        uint32_t timeout)
+{
+    ASSERT(timeout > 0);
+
+    //If interrupts are not used, poll for flags
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS))
+    {
+        //Poll for transmit interrupt flag.
+        while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+                EUSCI_B_IFG_TXIFG0_OFS)) && --timeout)
+            ;
+
+        //Check if transfer timed out
+        if (timeout == 0)
+            return false;
+    }
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+
+    return 0x01;
+}
+
+void I2C_masterReceiveStart(uint32_t moduleInstance)
+{
+    //Set USCI in Receive mode
+    EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
+            (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & (~EUSCI_B_CTLW0_TR))
+            | EUSCI_B_CTLW0_TXSTT;
+}
+
+uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance)
+{
+    return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
+}
+
+uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance)
+{
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) =
+            1;
+
+    //Wait for Stop to finish
+    while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS))
+    {
+        // Wait for RX buffer
+        while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
+            ;
+    }
+
+    /* Capture data from receive buffer after setting stop bit due to
+     MSP430 I2C critical timing. */
+    return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
+}
+
+bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance,
+        uint8_t *txData, uint32_t timeout)
+{
+    uint32_t timeout2 = timeout;
+
+    ASSERT(timeout > 0);
+
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+
+    //Wait for Stop to finish
+    while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS)
+            && --timeout)
+        ;
+
+    //Check if transfer timed out
+    if (timeout == 0)
+        return false;
+
+    // Wait for RX buffer
+    while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_RXIFG_OFS))
+            && --timeout2)
+        ;
+
+    //Check if transfer timed out
+    if (timeout2 == 0)
+        return false;
+
+    //Capture data from receive buffer after setting stop bit due to
+    //MSP430 I2C critical timing.
+    *txData = (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK);
+
+    return true;
+}
+
+void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance)
+{
+    //Send stop condition.
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTP_OFS) = 1;
+}
+
+uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance)
+{
+    //Polling RXIFG0 if RXIE is not enabled
+    if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS))
+    {
+        while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG,
+                EUSCI_B_IFG_RXIFG0_OFS))
+            ;
+    }
+
+    //Read a byte.
+    return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK) ;
+}
+
+uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->RXBUF;
+}
+
+uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
+}
+
+uint8_t I2C_masterIsStopSent(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
+            EUSCI_B_CTLW0_TXSTP_OFS);
+}
+
+bool I2C_masterIsStartSent(uint32_t moduleInstance)
+{
+    return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,
+            EUSCI_B_CTLW0_TXSTT_OFS);
+}
+
+void I2C_masterSendStart(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXSTT_OFS) =
+            1;
+}
+
+void I2C_enableMultiMasterMode(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+            1;
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 1;
+}
+
+void I2C_disableMultiMasterMode(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_SWRST_OFS) =
+            1;
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_MM_OFS) = 0;
+}
+
+void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+
+    //Enable the interrupt masked bit
+    EUSCI_B_CMSIS(moduleInstance)->IE |= mask;
+}
+
+void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+
+    //Disable the interrupt masked bit
+    EUSCI_B_CMSIS(moduleInstance)->IE &= ~(mask);
+}
+
+void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+    //Clear the I2C interrupt source.
+    EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(mask);
+}
+
+uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
+{
+    ASSERT(
+            0x00
+            == (mask
+                    & ~(EUSCI_B_I2C_STOP_INTERRUPT
+                            + EUSCI_B_I2C_START_INTERRUPT
+                            + EUSCI_B_I2C_NAK_INTERRUPT
+                            + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT
+                            + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT
+                            + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT
+                            + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT0
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT1
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT2
+                            + EUSCI_B_I2C_TRANSMIT_INTERRUPT3
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT0
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT1
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT2
+                            + EUSCI_B_I2C_RECEIVE_INTERRUPT3)));
+    //Return the interrupt status of the request masked bit.
+    return EUSCI_B_CMSIS(moduleInstance)->IFG & mask;
+}
+
+uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance)
+{
+    return I2C_getInterruptStatus(moduleInstance,
+    EUSCI_B_CMSIS(moduleInstance)->IE);
+}
+
+uint_fast16_t I2C_getMode(uint32_t moduleInstance)
+{
+    //Read the I2C mode.
+    return (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & EUSCI_B_CTLW0_TR);
+}
+
+void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_B0_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB0);
+        break;
+    case EUSCI_B1_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB1);
+        break;
+#ifdef EUSCI_B2_BASE
+    case EUSCI_B2_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB2);
+        break;
+#endif
+#ifdef EUSCI_B3_BASE
+    case EUSCI_B3_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIB3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
+
+void I2C_unregisterInterrupt(uint32_t moduleInstance)
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_B0_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIB0);
+        Interrupt_unregisterInterrupt(INT_EUSCIB0);
+        break;
+    case EUSCI_B1_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIB1);
+        Interrupt_unregisterInterrupt(INT_EUSCIB1);
+        break;
+#ifdef EUSCI_B2_BASE
+    case EUSCI_B2_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIB2);
+        Interrupt_unregisterInterrupt(INT_EUSCIB2);
+        break;
+#endif
+#ifdef EUSCI_B3_BASE
+    case EUSCI_B3_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIB3);
+        Interrupt_unregisterInterrupt(INT_EUSCIB3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
+
+void I2C_slaveSendNAK(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0,EUSCI_B_CTLW0_TXNACK_OFS)
+            = 1;
+}

platform/vendor_bsp/TI/MSP432P4xx/interrupt.c

@@ -0,0 +1,538 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <debug.h>
+#include <cpu.h>
+#include <interrupt.h>
+
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const uint32_t g_pulPriority[] =
+{ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4,
+NVIC_APINT_PRIGROUP_5_3, NVIC_APINT_PRIGROUP_6_2,
+NVIC_APINT_PRIGROUP_7_1 };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulRegs[] =
+{ 0, NVIC_SYS_PRI1_R, NVIC_SYS_PRI2_R, NVIC_SYS_PRI3_R, NVIC_PRI0_R,
+NVIC_PRI1_R, NVIC_PRI2_R, NVIC_PRI3_R, NVIC_PRI4_R, NVIC_PRI5_R,
+NVIC_PRI6_R, NVIC_PRI7_R, NVIC_PRI8_R, NVIC_PRI9_R, NVIC_PRI10_R,
+NVIC_PRI11_R, NVIC_PRI12_R, NVIC_PRI13_R, NVIC_PRI14_R, NVIC_PRI15_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt enable for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulEnRegs[] =
+{ NVIC_EN0_R, NVIC_EN1_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt disable for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulDisRegs[] =
+{ NVIC_DIS0_R, NVIC_DIS1_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt pend for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulPendRegs[] =
+{ NVIC_PEND0_R, NVIC_PEND1_R };
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt unpend for that
+// interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pulUnpendRegs[] =
+{ NVIC_UNPEND0_R, NVIC_UNPEND1_R };
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts.  It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger.  Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void IntDefaultHandler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while (1)
+    {
+    }
+}
+
+//*****************************************************************************
+//
+// The processor vector table.
+//
+// This contains a list of the handlers for the various interrupt sources in
+// the system.  The layout of this list is defined by the hardware; assertion
+// of an interrupt causes the processor to start executing directly at the
+// address given in the corresponding location in this list.
+//
+//*****************************************************************************
+#if defined(ewarm)
+#pragma data_alignment=1024
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) @ "VTABLE";
+#elif defined(ccs)
+#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
+void (*g_pfnRAMVectors[NUM_INTERRUPTS + 1])(void);
+#else
+static __attribute__((section("vtable")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) __attribute__((aligned(1024)));
+#endif
+
+bool Interrupt_enableMaster(void)
+{
+    //
+    // Enable processor interrupts.
+    //
+    return (CPU_cpsie());
+}
+
+bool Interrupt_disableMaster(void)
+{
+    //
+    // Disable processor interrupts.
+    //
+    return (CPU_cpsid());
+}
+
+void Interrupt_registerInterrupt(uint32_t interruptNumber,
+        void (*intHandler)(void))
+{
+    uint32_t ulIdx, ulValue;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Make sure that the RAM vector table is correctly aligned.
+    //
+    ASSERT(((uint32_t) g_pfnRAMVectors & 0x000000ff) == 0);
+
+    //
+    // See if the RAM vector table has been initialized.
+    //
+    if (SCB->VTOR != (uint32_t) g_pfnRAMVectors)
+    {
+        //
+        // Copy the vector table from the beginning of FLASH to the RAM vector
+        // table.
+        //
+        ulValue = SCB->VTOR;
+        for (ulIdx = 0; ulIdx < (NUM_INTERRUPTS + 1); ulIdx++)
+        {
+            g_pfnRAMVectors[ulIdx] = (void (*)(void)) HWREG32(
+                    (ulIdx * 4) + ulValue);
+        }
+
+        //
+        // Point the NVIC at the RAM vector table.
+        //
+        SCB->VTOR = (uint32_t) g_pfnRAMVectors;
+    }
+
+    //
+    // Save the interrupt handler.
+    //
+    g_pfnRAMVectors[interruptNumber] = intHandler;
+}
+
+void Interrupt_unregisterInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Reset the interrupt handler.
+    //
+    g_pfnRAMVectors[interruptNumber] = IntDefaultHandler;
+}
+
+void Interrupt_setPriorityGrouping(uint32_t bits)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(bits < NUM_PRIORITY);
+
+    //
+    // Set the priority grouping.
+    //
+    SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits];
+}
+
+uint32_t Interrupt_getPriorityGrouping(void)
+{
+    uint32_t ulLoop, ulValue;
+
+    //
+    // Read the priority grouping.
+    //
+    ulValue = SCB->AIRCR & NVIC_APINT_PRIGROUP_M;
+
+    //
+    // Loop through the priority grouping values.
+    //
+    for (ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
+    {
+        //
+        // Stop looping if this value matches.
+        //
+        if (ulValue == g_pulPriority[ulLoop])
+        {
+            break;
+        }
+    }
+
+    //
+    // Return the number of priority bits.
+    //
+    return (ulLoop);
+}
+
+void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority)
+{
+    uint32_t ulTemp;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
+
+    //
+    // Set the interrupt priority.
+    //
+    ulTemp = HWREG32(g_pulRegs[interruptNumber >> 2]);
+    ulTemp &= ~(0xFF << (8 * (interruptNumber & 3)));
+    ulTemp |= priority << (8 * (interruptNumber & 3));
+    HWREG32 (g_pulRegs[interruptNumber >> 2]) = ulTemp;
+}
+
+uint8_t Interrupt_getPriority(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1)));
+
+    //
+    // Return the interrupt priority.
+    //
+    return ((HWREG32(g_pulRegs[interruptNumber >> 2])
+            >> (8 * (interruptNumber & 3))) & 0xFF);
+}
+
+void Interrupt_enableInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to enable.
+    //
+    if (interruptNumber == FAULT_MPU)
+    {
+        //
+        // Enable the MemManage interrupt.
+        //
+        SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+    } else if (interruptNumber == FAULT_BUS)
+    {
+        //
+        // Enable the bus fault interrupt.
+        //
+        SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
+    } else if (interruptNumber == FAULT_USAGE)
+    {
+        //
+        // Enable the usage fault interrupt.
+        //
+        SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Enable the System Tick interrupt.
+        //
+        SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Enable the general interrupt.
+        //
+        HWREG32 (g_pulEnRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+void Interrupt_disableInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to disable.
+    //
+    if (interruptNumber == FAULT_MPU)
+    {
+        //
+        // Disable the MemManage interrupt.
+        //
+        SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk);
+    } else if (interruptNumber == FAULT_BUS)
+    {
+        //
+        // Disable the bus fault interrupt.
+        //
+        SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA_Msk);
+    } else if (interruptNumber == FAULT_USAGE)
+    {
+        //
+        // Disable the usage fault interrupt.
+        //
+        SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA_Msk);
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Disable the System Tick interrupt.
+        //
+        SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Disable the general interrupt.
+        //
+        HWREG32 (g_pulDisRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+bool Interrupt_isEnabled(uint32_t interruptNumber)
+{
+    uint32_t ulRet;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Initialize the return value.
+    //
+    ulRet = 0;
+
+    //
+    // Determine the interrupt to disable.
+    //
+    if (interruptNumber == FAULT_MPU)
+    {
+        //
+        // Check the MemManage interrupt.
+        //
+        ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA_Msk;
+    } else if (interruptNumber == FAULT_BUS)
+    {
+        //
+        // Check the bus fault interrupt.
+        //
+        ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA_Msk;
+    } else if (interruptNumber == FAULT_USAGE)
+    {
+        //
+        // Check the usage fault interrupt.
+        //
+        ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA_Msk;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Check the System Tick interrupt.
+        //
+        ulRet = SysTick->CTRL & SysTick_CTRL_ENABLE_Msk;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Check the general interrupt.
+        //
+        ulRet = HWREG32(g_pulEnRegs[(interruptNumber - 16) / 32])
+                & (1 << ((interruptNumber - 16) & 31));
+    }
+    return (ulRet);
+}
+
+void Interrupt_pendInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to pend.
+    //
+    if (interruptNumber == FAULT_NMI)
+    {
+        //
+        // Pend the NMI interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk;
+    } else if (interruptNumber == FAULT_PENDSV)
+    {
+        //
+        // Pend the PendSV interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Pend the SysTick interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG32 (g_pulPendRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+void Interrupt_unpendInterrupt(uint32_t interruptNumber)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(interruptNumber < (NUM_INTERRUPTS+1));
+
+    //
+    // Determine the interrupt to unpend.
+    //
+    if (interruptNumber == FAULT_PENDSV)
+    {
+        //
+        // Unpend the PendSV interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk;
+    } else if (interruptNumber == FAULT_SYSTICK)
+    {
+        //
+        // Unpend the SysTick interrupt.
+        //
+        SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+    } else if (interruptNumber >= 16)
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG32 (g_pulUnpendRegs[(interruptNumber - 16) / 32]) = 1
+                << ((interruptNumber - 16) & 31);
+    }
+}
+
+void Interrupt_setPriorityMask(uint8_t priorityMask)
+{
+    CPU_basepriSet(priorityMask);
+}
+
+uint8_t Interrupt_getPriorityMask(void)
+{
+    return (CPU_basepriGet());
+}
+
+void Interrupt_setVectorTableAddress(uint32_t addr)
+{
+    SCB->VTOR = addr;
+}
+
+uint32_t Interrupt_getVectorTableAddress(void)
+{
+    return SCB->VTOR;
+}
+
+void Interrupt_enableSleepOnIsrExit(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
+}
+
+void Interrupt_disableSleepOnIsrExit(void)
+{
+    SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+}

platform/vendor_bsp/TI/MSP432P4xx/interrupt.h

@@ -0,0 +1,581 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+/******************************************************************************
+* NVIC interrupts                                                             *
+******************************************************************************/
+/* System exceptions */
+#define FAULT_NMI                                       ( 2) /* NMI fault */
+#define FAULT_HARD                                      ( 3) /* Hard fault */
+#define FAULT_MPU                                       ( 4) /* MPU fault */
+#define FAULT_BUS                                       ( 5) /* Bus fault */
+#define FAULT_USAGE                                     ( 6) /* Usage fault */
+#define FAULT_SVCALL                                    (11) /* SVCall */
+#define FAULT_DEBUG                                     (12) /* Debug monitor */
+#define FAULT_PENDSV                                    (14) /* PendSV */
+#define FAULT_SYSTICK                                   (15) /* System Tick */
+
+/* External interrupts */
+#define INT_PSS                                         (16) /* PSS IRQ */
+#define INT_CS                                          (17) /* CS IRQ */
+#define INT_PCM                                         (18) /* PCM IRQ */
+#define INT_WDT_A                                       (19) /* WDT_A IRQ */
+#define INT_FPU                                         (20) /* FPU IRQ */
+#define INT_FLCTL                                       (21) /* FLCTL IRQ */
+#define INT_COMP_E0                                     (22) /* COMP_E0 IRQ */
+#define INT_COMP_E1                                     (23) /* COMP_E1 IRQ */
+#define INT_TA0_0                                       (24) /* TA0_0 IRQ */
+#define INT_TA0_N                                       (25) /* TA0_N IRQ */
+#define INT_TA1_0                                       (26) /* TA1_0 IRQ */
+#define INT_TA1_N                                       (27) /* TA1_N IRQ */
+#define INT_TA2_0                                       (28) /* TA2_0 IRQ */
+#define INT_TA2_N                                       (29) /* TA2_N IRQ */
+#define INT_TA3_0                                       (30) /* TA3_0 IRQ */
+#define INT_TA3_N                                       (31) /* TA3_N IRQ */
+#define INT_EUSCIA0                                     (32) /* EUSCIA0 IRQ */
+#define INT_EUSCIA1                                     (33) /* EUSCIA1 IRQ */
+#define INT_EUSCIA2                                     (34) /* EUSCIA2 IRQ */
+#define INT_EUSCIA3                                     (35) /* EUSCIA3 IRQ */
+#define INT_EUSCIB0                                     (36) /* EUSCIB0 IRQ */
+#define INT_EUSCIB1                                     (37) /* EUSCIB1 IRQ */
+#define INT_EUSCIB2                                     (38) /* EUSCIB2 IRQ */
+#define INT_EUSCIB3                                     (39) /* EUSCIB3 IRQ */
+#define INT_ADC14                                       (40) /* ADC14 IRQ */
+#define INT_T32_INT1                                    (41) /* T32_INT1 IRQ */
+#define INT_T32_INT2                                    (42) /* T32_INT2 IRQ */
+#define INT_T32_INTC                                    (43) /* T32_INTC IRQ */
+#define INT_AES256                                      (44) /* AES256 IRQ */
+#define INT_RTC_C                                       (45) /* RTC_C IRQ */
+#define INT_DMA_ERR                                     (46) /* DMA_ERR IRQ */
+#define INT_DMA_INT3                                    (47) /* DMA_INT3 IRQ */
+#define INT_DMA_INT2                                    (48) /* DMA_INT2 IRQ */
+#define INT_DMA_INT1                                    (49) /* DMA_INT1 IRQ */
+#define INT_DMA_INT0                                    (50) /* DMA_INT0 IRQ */
+#define INT_PORT1                                       (51) /* PORT1 IRQ */
+#define INT_PORT2                                       (52) /* PORT2 IRQ */
+#define INT_PORT3                                       (53) /* PORT3 IRQ */
+#define INT_PORT4                                       (54) /* PORT4 IRQ */
+#define INT_PORT5                                       (55) /* PORT5 IRQ */
+#define INT_PORT6                                       (56) /* PORT6 IRQ */
+#define INT_LCD_F                                       (57) /* PORT6 IRQ */
+
+#define NUM_INTERRUPTS                                  (57)
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK       ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+#define NUM_PRIORITY            8
+
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_SYS_PRI1_R         0xE000ED18  // System Handler Priority 1
+#define NVIC_SYS_PRI2_R         0xE000ED1C  // System Handler Priority 2
+#define NVIC_SYS_PRI3_R         0xE000ED20  // System Handler Priority 3
+#define NVIC_PRI0_R             0xE000E400  // Interrupt 0-3 Priority
+#define NVIC_PRI1_R             0xE000E404  // Interrupt 4-7 Priority
+#define NVIC_PRI2_R             0xE000E408  // Interrupt 8-11 Priority
+#define NVIC_PRI3_R             0xE000E40C  // Interrupt 12-15 Priority
+#define NVIC_PRI4_R             0xE000E410  // Interrupt 16-19 Priority
+#define NVIC_PRI5_R             0xE000E414  // Interrupt 20-23 Priority
+#define NVIC_PRI6_R             0xE000E418  // Interrupt 24-27 Priority
+#define NVIC_PRI7_R             0xE000E41C  // Interrupt 28-31 Priority
+#define NVIC_PRI8_R             0xE000E420  // Interrupt 32-35 Priority
+#define NVIC_PRI9_R             0xE000E424  // Interrupt 36-39 Priority
+#define NVIC_PRI10_R            0xE000E428  // Interrupt 40-43 Priority
+#define NVIC_PRI11_R            0xE000E42C  // Interrupt 44-47 Priority
+#define NVIC_PRI12_R            0xE000E430  // Interrupt 48-51 Priority
+#define NVIC_PRI13_R            0xE000E434  // Interrupt 52-55 Priority
+#define NVIC_PRI14_R            0xE000E438  // Interrupt 56-59 Priority
+#define NVIC_PRI15_R            0xE000E43C  // Interrupt 60-63 Priority
+#define NVIC_EN0_R              0xE000E100  // Interrupt 0-31 Set Enable
+#define NVIC_EN1_R              0xE000E104  // Interrupt 32-54 Set Enable
+#define NVIC_DIS0_R             0xE000E180  // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1_R             0xE000E184  // Interrupt 32-54 Clear Enable
+#define NVIC_PEND0_R            0xE000E200  // Interrupt 0-31 Set Pending
+#define NVIC_PEND1_R            0xE000E204  // Interrupt 32-54 Set Pending
+#define NVIC_UNPEND0_R          0xE000E280  // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1_R          0xE000E284  // Interrupt 32-54 Clear Pending
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! This function allows the processor to respond to interrupts.  This function
+//! does not affect the set of interrupts enabled in the interrupt controller;
+//! it just gates the single interrupt from the controller to the processor.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+extern bool Interrupt_enableMaster(void);
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! This function prevents the processor from receiving interrupts.  This
+//! function does not affect the set of interrupts enabled in the interrupt
+//! controller; it just gates the single interrupt from the controller to the
+//! processor.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+extern bool Interrupt_disableMaster(void);
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//! \param intHandler is a pointer to the function to be called.
+//!
+//! \note The use of this function (directly or indirectly via a peripheral
+//! driver interrupt register function) moves the interrupt vector table from
+//! flash to SRAM.  Therefore, care must be taken when linking the application
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;
+//! otherwise the NVIC does not look in the correct portion of memory for the
+//! vector table (it requires the vector table be on a 1 kB memory alignment).
+//! Normally, the SRAM vector table is so placed via the use of linker scripts.
+//! See the discussion of compile-time versus run-time interrupt handler
+//! registration in the introduction to this chapter.
+//!
+//! \note This function is only used if the customer wants to specify the 
+//!  interrupt handler at run time. In most cases, this is done through means
+//!  of the user setting the ISR function pointer in the startup file. Refer
+//!  Refer to the Module Operation section for more details.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_registerInterrupt(uint32_t interruptNumber,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor.  The interrupt source is
+//! automatically disabled (via Interrupt_disableInterrupt()) if necessary.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_unregisterInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param bits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! sub-priority levels in the interrupt priority specification.  The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the MSP432 family, three bits are available for hardware interrupt
+//! prioritization and therefore priority grouping values of three through
+//! seven have the same effect.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setPriorityGrouping(uint32_t bits);
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! sub-priority levels in the interrupt priority specification.
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+extern uint32_t Interrupt_getPriorityGrouping(void);
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//! \param priority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt.  When multiple
+//! interrupts are asserted simultaneously, the ones with the highest priority
+//! are processed before the lower priority interrupts.  Smaller numbers
+//! correspond to higher interrupt priorities; priority 0 is the highest
+//! interrupt priority.
+//!
+//! The hardware priority mechanism only looks at the upper N bits of the
+//! priority level (where N is 3 for the MSP432 family), so any
+//! prioritization must be performed in those bits.  The remaining bits can be
+//! used to sub-prioritize the interrupt sources, and may be used by the
+//! hardware priority mechanism on a future part.  This arrangement allows
+//! priorities to migrate to different NVIC implementations without changing
+//! the gross prioritization of the interrupts.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority);
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt.  See
+//! Interrupt_setPriority() for a definition of the priority value.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
+//! specified.
+//
+//*****************************************************************************
+extern uint8_t Interrupt_getPriority(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller.  Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! Valid values will vary from part to part, so it is important to check the
+//! device specific datasheet, however for MSP432 101 the following values can
+//! be provided:
+//!     - \b FAULT_NMI
+//!     - \b FAULT_HARD
+//!     - \b FAULT_MPU
+//!     - \b FAULT_BUS
+//!     - \b FAULT_USAGE
+//!     - \b FAULT_SVCALL
+//!     - \b FAULT_DEBUG
+//!     - \b FAULT_PENDSV
+//!     - \b FAULT_SYSTICK
+//!     - \b INT_PSS
+//!     - \b INT_CS
+//!     - \b INT_PCM
+//!     - \b INT_WDT_A
+//!     - \b INT_FPU
+//!     - \b INT_FLCTL
+//!     - \b INT_COMP0
+//!     - \b INT_COMP1
+//!     - \b INT_TA0_0
+//!     - \b INT_TA0_N
+//!     - \b INT_TA1_0
+//!     - \b INT_TA1_N
+//!     - \b INT_TA2_0
+//!     - \b INT_TA2_N
+//!     - \b INT_TA3_0
+//!     - \b INT_TA3_N
+//!     - \b INT_EUSCIA0
+//!     - \b INT_EUSCIA1
+//!     - \b INT_EUSCIA2
+//!     - \b INT_EUSCIA3
+//!     - \b INT_EUSCIB0
+//!     - \b INT_EUSCIB1
+//!     - \b INT_EUSCIB2
+//!     - \b INT_EUSCIB3
+//!     - \b INT_ADC14
+//!     - \b INT_T32_INT1
+//!     - \b INT_T32_INT2
+//!     - \b INT_T32_INTC
+//!     - \b INT_AES
+//!     - \b INT_RTCC
+//!     - \b INT_DMA_ERR
+//!     - \b INT_DMA_INT3
+//!     - \b INT_DMA_INT2
+//!     - \b INT_DMA_INT1
+//!     - \b INT_DMA_INT0
+//!     - \b INT_PORT1
+//!     - \b INT_PORT2
+//!     - \b INT_PORT3
+//!     - \b INT_PORT4
+//!     - \b INT_PORT5
+//!     - \b INT_PORT6
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_enableInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller.  Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_disableInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Returns if a peripheral interrupt is enabled.
+//!
+//! \param interruptNumber specifies the interrupt to check.
+//!
+//! This function checks if the specified interrupt is enabled in the interrupt
+//! controller.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return A non-zero value if the interrupt is enabled.
+//
+//*****************************************************************************
+extern bool Interrupt_isEnabled(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller.  Pending an
+//! interrupt causes the interrupt controller to execute the corresponding
+//! interrupt handler at the next available time, based on the current
+//! interrupt state priorities. For example, if called by a higher priority
+//! interrupt handler, the specified interrupt handler is not called until
+//! after the current interrupt handler has completed execution.  The interrupt
+//! must have been enabled for it to be called.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_pendInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Un-pends an interrupt.
+//!
+//! \param interruptNumber specifies the interrupt to be un-pended.
+//!
+//! The specified interrupt is un-pended in the interrupt controller.  This
+//! will cause any previously generated interrupts that have not been handled
+//! yet (due to higher priority interrupts or the interrupt no having been
+//! enabled yet) to be discarded.
+//!
+//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt
+//! parameter
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_unpendInterrupt(uint32_t interruptNumber);
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param priorityMask is the priority level that is masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level are masked.  Masking
+//! interrupts can be used to globally disable a set of interrupts with
+//! priority below a predetermined threshold.  A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 allows interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater are blocked.
+//!
+//! The hardware priority mechanism only looks at the upper N bits of the
+//! priority level (where N is 3 for the MSP432 family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setPriorityMask(uint8_t priorityMask);
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level.  The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked.  A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 allows interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater are blocked.
+//!
+//! The hardware priority mechanism only looks at the upper N bits of the
+//! priority level (where N is 3 for the MSP432 family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+extern uint8_t Interrupt_getPriorityMask(void);
+
+//*****************************************************************************
+//
+//! Sets the address of the vector table. This function is for advanced users
+//! who might want to switch between multiple instances of vector tables
+//! (perhaps between flash/ram).
+//!
+//! \param addr is the new address of the vector table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Interrupt_setVectorTableAddress(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Returns the address of the interrupt vector table.
+//!
+//! \return Address of the vector table.
+//
+//*****************************************************************************
+extern uint32_t Interrupt_getVectorTableAddress(void);
+
+//*****************************************************************************
+//
+//! Enables the processor to sleep when exiting an ISR. For low power operation,
+//! this is ideal as power cycles are not wasted with the processing required
+//! for waking up from an ISR and going back to sleep.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Interrupt_enableSleepOnIsrExit(void);
+
+//*****************************************************************************
+//
+//! Disables the processor to sleep when exiting an ISR.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Interrupt_disableSleepOnIsrExit(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __INTERRUPT_H__

platform/vendor_bsp/TI/MSP432P4xx/lcd_f.c

@@ -0,0 +1,278 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <stdint.h>
+#include <driverlib.h>
+
+/* Configuration functions */
+void LCD_F_initModule(LCD_F_Config *initParams)
+{
+    BITBAND_PERI(LCD_F->CTL,LCD_F_CTL_ON_OFS) = 0;
+
+    LCD_F->CTL = (LCD_F->CTL
+            & ~(LCD_F_CTL_MX_MASK | LCD_F_CTL_SSEL_MASK | LCD_F_CTL_LP
+                    | LCD_F_CTL_ON | LCD_F_CTL_DIV_MASK | LCD_F_CTL_PRE_MASK
+                    | LCD_F_CTL_SON))
+            | (initParams->muxRate | initParams->clockSource
+                    | initParams->waveforms | initParams->segments
+                    | initParams->clockDivider | initParams->clockPrescaler);
+}
+
+void LCD_F_turnOn(void)
+{
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 1;
+}
+
+void LCD_F_turnOff(void)
+{
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+}
+
+/* Memory management functions */
+void LCD_F_clearAllMemory(void)
+{
+    BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_CLRM_OFS) = 1;
+}
+
+void LCD_F_clearAllBlinkingMemory(void)
+{
+    BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_CLRBM_OFS) = 1;
+}
+
+void LCD_F_selectDisplayMemory(uint_fast16_t displayMemory)
+{
+    BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_DISP_OFS) = displayMemory;
+}
+
+void LCD_F_setBlinkingControl(uint_fast16_t clockPrescalar,
+        uint_fast16_t divider, uint_fast16_t mode)
+{
+    LCD_F->BMCTL = (LCD_F->BMCTL
+            & ~(LCD_F_BMCTL_BLKPRE_MASK | LCD_F_BMCTL_BLKDIV_MASK
+                    | LCD_F_BMCTL_BLKMOD_MASK)) | clockPrescalar | mode
+            | divider;
+}
+
+void LCD_F_setAnimationControl(uint_fast16_t clockPrescalar,
+        uint_fast16_t divider, uint_fast16_t frames)
+{
+    LCD_F->ANMCTL = (LCD_F->ANMCTL
+            & ~(LCD_F_ANMCTL_ANMPRE_MASK | LCD_F_ANMCTL_ANMDIV_MASK
+                    | LCD_F_ANMCTL_ANMSTP_MASK)) | clockPrescalar | divider
+            | frames;
+}
+
+void LCD_F_enableAnimation(void)
+{
+    BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMEN_OFS) = 1;
+}
+
+void LCD_F_disableAnimation(void)
+{
+    BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMEN_OFS) = 0;
+}
+
+void LCD_F_clearAllAnimationMemory(void)
+{
+    BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMCLR_OFS) = 1;
+}
+
+/* Pin Configuration Functions */
+void LCD_F_setPinAsLCDFunction(uint_fast8_t pin)
+{
+    uint32_t val = (pin & 0x1F);
+
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+
+    if((pin >> 5) == 0)
+    {
+        BITBAND_PERI(LCD_F->PCTL0, val) = 1;
+    }
+    else
+    {
+        BITBAND_PERI(LCD_F->PCTL1, val) = 1;
+    }
+}
+
+void LCD_F_setPinAsPortFunction(uint_fast8_t pin)
+{
+    uint32_t val = (pin & 0x1F);
+
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+
+    if((pin >> 5) == 0)
+    {
+        BITBAND_PERI(LCD_F->PCTL0, val) = 0;
+    }
+    else
+    {
+        BITBAND_PERI(LCD_F->PCTL1, val) = 0;
+    }
+}
+
+void LCD_F_setPinsAsLCDFunction(uint_fast8_t startPin, uint8_t endPin)
+{
+    uint32_t startIdx = startPin >> 5;
+    uint32_t endIdx = endPin >> 5;
+    uint32_t startPos = startPin & 0x1F;
+    uint32_t endPos = endPin & 0x1F;
+
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+
+    if (startIdx == endIdx)
+    {
+        if (startIdx == 0)
+        {
+            LCD_F->PCTL0 = (0xFFFFFFFF >> (31 - endPos))
+                    & (0xFFFFFFFF << startPos);
+        } else
+        {
+            LCD_F->PCTL1 = (0xFFFFFFFF >> (31 - endPos))
+                    & (0xFFFFFFFF << startPos);
+        }
+    } else
+    {
+        LCD_F->PCTL0 = (0xFFFFFFFF << startPos);
+        LCD_F->PCTL1 = (0xFFFFFFFF >> (31 - endPos));
+    }
+}
+
+void LCD_F_setPinAsCOM(uint8_t pin, uint_fast8_t com)
+{
+    uint32_t val = (pin & 0x1F);
+    uint8_t muxRate = LCD_F->CTL | LCD_F_CTL_MX_MASK;
+
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+
+    if((pin >> 5) == 0)
+    {
+        BITBAND_PERI(LCD_F->CSSEL0, val) = 1;
+    }
+    else
+    {
+        BITBAND_PERI(LCD_F->CSSEL1, val) = 1;
+    }
+
+    /* Set LCDMem to COM as well for corresponding pins */
+    if(muxRate <= LCD_F_CTL_MX_3)
+    {
+        if(pin & 1)
+        {
+            HWREG8(LCD_F_BASE + OFS_LCDM0W + pin / 2) |= (com & 0xF) << 4;
+            HWREG8(LCD_F_BASE + OFS_LCDBM0W + pin / 2) |= (com & 0xF) << 4;
+        }
+        else
+        {
+            HWREG8(LCD_F_BASE + OFS_LCDM0W + pin / 2) |= (com & 0xF);
+            HWREG8(LCD_F_BASE + OFS_LCDBM0W + pin / 2) |= (com & 0xF);
+        }
+    }
+    else
+    {
+        //5-mux, 6-mux, 7-mux, 8-mux
+        HWREG8(LCD_F_BASE + OFS_LCDM0W + pin) |= com;
+        HWREG8(LCD_F_BASE + OFS_LCDBM0W + pin) |= com;
+    }
+}
+
+void LCD_F_setPinAsSEG(uint_fast8_t pin)
+{
+    uint32_t val = (pin & 0x1F);
+    uint8_t muxRate = LCD_F->CTL | LCD_F_CTL_MX_MASK;
+
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+
+    if((pin >> 5) == 0)
+    {
+        BITBAND_PERI(LCD_F->CSSEL0, val) = 0;
+    }
+    else
+    {
+        BITBAND_PERI(LCD_F->CSSEL1, val) = 0;
+    }
+}
+
+void LCD_F_selectBias(uint_fast16_t bias)
+{
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+    LCD_F->VCPCTL = (LCD_F->VCPCTL & ~LCD_F_VCPCTL_LCD2B) | bias;
+}
+
+void LCD_F_setVLCDSource(uint_fast16_t v2v3v4Source, uint_fast16_t v5Source)
+{
+    BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0;
+    LCD_F->VCPCTL = (LCD_F->VCPCTL
+            & ~(LCD_F_VCPCTL_REXT | LCD_F_VCPCTL_EXTBIAS
+                    | LCD_F_VCPCTL_R03EXT)) | v2v3v4Source | v5Source;
+}
+
+/* Interrupt Management */
+void LCD_F_clearInterrupt(uint32_t mask)
+{
+    LCD_F->CLRIFG |= mask;
+}
+
+uint32_t LCD_F_getInterruptStatus(void)
+{
+    return LCD_F->IFG;
+}
+
+uint32_t LCD_F_getEnabledInterruptStatus(void)
+{
+    return (LCD_F->IFG & LCD_F->IE);
+}
+
+void LCD_F_enableInterrupt(uint32_t mask)
+{
+    LCD_F->IE |= mask;
+}
+
+void LCD_F_disableInterrupt(uint32_t mask)
+{
+    LCD_F->IE &= ~mask;
+}
+
+void LCD_F_registerInterrupt(void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(INT_LCD_F, intHandler);
+    Interrupt_enableInterrupt(INT_LCD_F);
+}
+
+void LCD_F_unregisterInterrupt(void)
+{
+    Interrupt_disableInterrupt(INT_LCD_F);
+    Interrupt_unregisterInterrupt(INT_LCD_F);
+}

platform/vendor_bsp/TI/MSP432P4xx/mpu.c

@@ -0,0 +1,194 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <debug.h>
+#include <interrupt.h>
+#include <mpu.h>
+
+void MPU_enableModule(uint32_t mpuConfig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(!(mpuConfig & ~(MPU_CONFIG_PRIV_DEFAULT | MPU_CONFIG_HARDFLT_NMI)));
+
+    //
+    // Set the MPU control bits according to the flags passed by the user,
+    // and also set the enable bit.
+    //
+    MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE_Msk;
+}
+
+void MPU_disableModule(void)
+{
+    //
+    // Turn off the MPU enable bit.
+    //
+    MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+
+}
+
+uint32_t MPU_getRegionCount(void)
+{
+    //
+    // Read the DREGION field of the MPU type register and mask off
+    // the bits of interest to get the count of regions.
+    //
+    return ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> NVIC_MPU_TYPE_DREGION_S);
+}
+
+void MPU_enableRegion(uint32_t region)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+
+    //
+    // Select the region to modify.
+    //
+    MPU->RNR = region;
+
+    //
+    // Modify the enable bit in the region attributes.
+    //
+    MPU->RASR |= MPU_RASR_ENABLE_Msk;
+}
+
+void MPU_disableRegion(uint32_t region)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+
+    //
+    // Select the region to modify.
+    //
+    MPU->RNR = region;
+
+    //
+    // Modify the enable bit in the region attributes.
+    //
+    MPU->RASR &= ~MPU_RASR_ENABLE_Msk;
+}
+
+void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+
+    //
+    // Program the base address, use the region field to select the
+    // region at the same time.
+    //
+    MPU->RBAR = addr | region | MPU_RBAR_VALID_Msk;
+
+    //
+    // Program the region attributes.  Set the TEX field and the S, C,
+    // and B bits to fixed values that are suitable for all Stellaris
+    // memory.
+    //
+    MPU->RASR = (flags & ~(MPU_RASR_TEX_Msk | MPU_RASR_C_Msk)) | MPU_RASR_S_Msk
+            | MPU_RASR_B_Msk;
+}
+
+void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(region < 8);
+    ASSERT(addr);
+    ASSERT(pflags);
+
+    //
+    // Select the region to get.
+    //
+    MPU->RNR = region;
+
+    //
+    // Read and store the base address for the region.
+    //
+    *addr = MPU->RBAR & MPU_RBAR_ADDR_Msk;
+
+    //
+    // Read and store the region attributes.
+    //
+    *pflags = MPU->RASR;
+}
+
+void MPU_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(intHandler);
+
+    //
+    // Register the interrupt handler.
+    //
+    Interrupt_registerInterrupt(FAULT_MPU, intHandler);
+
+}
+
+void MPU_unregisterInterrupt(void)
+{
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(FAULT_MPU);
+}
+
+void MPU_enableInterrupt(void)
+{
+
+    //
+    // Enable the memory management fault.
+    //
+    Interrupt_enableInterrupt(FAULT_MPU);
+
+}
+
+void MPU_disableInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(FAULT_MPU);
+}

platform/vendor_bsp/TI/MSP432P4xx/mpu.h

@@ -0,0 +1,449 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __MPU_H__
+#define __MPU_H__
+
+//*****************************************************************************
+//
+//! \addtogroup mpu_api
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPU_enableModule.
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_CONFIG_HARDFLT_NMI      MPU_CTRL_HFNMIENA_Msk
+#define MPU_CONFIG_NONE             0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B            (4 << 1)
+#define MPU_RGN_SIZE_64B            (5 << 1)
+#define MPU_RGN_SIZE_128B           (6 << 1)
+#define MPU_RGN_SIZE_256B           (7 << 1)
+#define MPU_RGN_SIZE_512B           (8 << 1)
+
+#define MPU_RGN_SIZE_1K             (9 << 1)
+#define MPU_RGN_SIZE_2K             (10 << 1)
+#define MPU_RGN_SIZE_4K             (11 << 1)
+#define MPU_RGN_SIZE_8K             (12 << 1)
+#define MPU_RGN_SIZE_16K            (13 << 1)
+#define MPU_RGN_SIZE_32K            (14 << 1)
+#define MPU_RGN_SIZE_64K            (15 << 1)
+#define MPU_RGN_SIZE_128K           (16 << 1)
+#define MPU_RGN_SIZE_256K           (17 << 1)
+#define MPU_RGN_SIZE_512K           (18 << 1)
+
+#define MPU_RGN_SIZE_1M             (19 << 1)
+#define MPU_RGN_SIZE_2M             (20 << 1)
+#define MPU_RGN_SIZE_4M             (21 << 1)
+#define MPU_RGN_SIZE_8M             (22 << 1)
+#define MPU_RGN_SIZE_16M            (23 << 1)
+#define MPU_RGN_SIZE_32M            (24 << 1)
+#define MPU_RGN_SIZE_64M            (25 << 1)
+#define MPU_RGN_SIZE_128M           (26 << 1)
+#define MPU_RGN_SIZE_256M           (27 << 1)
+#define MPU_RGN_SIZE_512M           (28 << 1)
+
+#define MPU_RGN_SIZE_1G             (29 << 1)
+#define MPU_RGN_SIZE_2G             (30 << 1)
+#define MPU_RGN_SIZE_4G             (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC           0x00000000
+#define MPU_RGN_PERM_NOEXEC         0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO  0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO  0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO  0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW  0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO  0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO  0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0       0x00000100
+#define MPU_SUB_RGN_DISABLE_1       0x00000200
+#define MPU_SUB_RGN_DISABLE_2       0x00000400
+#define MPU_SUB_RGN_DISABLE_3       0x00000800
+#define MPU_SUB_RGN_DISABLE_4       0x00001000
+#define MPU_SUB_RGN_DISABLE_5       0x00002000
+#define MPU_SUB_RGN_DISABLE_6       0x00004000
+#define MPU_SUB_RGN_DISABLE_7       0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPU_setRegion.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE              1
+#define MPU_RGN_DISABLE             0
+
+#define NVIC_MPU_TYPE_DREGION_S     8
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables and configures the MPU for use.
+//!
+//! \param mpuConfig is the logical OR of the possible configurations.
+//!
+//! This function enables the Cortex-M memory protection unit.  It also
+//! configures the default behavior when in privileged mode and while handling
+//! a hard fault or NMI.  Prior to enabling the MPU, at least one region must
+//! be set by calling MPU_setRegion() or else by enabling the default region for
+//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
+//! MPU_enableModule().  Once the MPU is enabled, a memory management fault is
+//! generated for memory access violations.
+//!
+//! The \e mpuConfig parameter should be the logical OR of any of the
+//! following:
+//!
+//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
+//! privileged mode and when no other regions are defined.  If this option
+//! is not enabled, then there must be at least one valid region already
+//! defined when the MPU is enabled.
+//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
+//! exception handler.  If this option is not enabled, then the MPU is
+//! disabled while in one of these exception handlers and the default
+//! memory map is applied.
+//! - \b MPU_CONFIG_NONE chooses none of the above options.  In this case,
+//! no default memory map is provided in privileged mode, and the MPU is
+//! not enabled in the fault handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_enableModule(uint32_t mpuConfig);
+
+//*****************************************************************************
+//
+//! Disables the MPU for use.
+//!
+//! This function disables the Cortex-M memory protection unit.  When the
+//! MPU is disabled, the default memory map is used and memory management
+//! faults are not generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_disableModule(void);
+
+//*****************************************************************************
+//
+//! Gets the count of regions supported by the MPU.
+//!
+//! This function is used to get the total number of regions that are supported
+//! by the MPU, including regions that are already programmed.
+//!
+//! \return The number of memory protection regions that are available
+//! for programming using MPU_setRegion().
+//
+//*****************************************************************************
+extern uint32_t MPU_getRegionCount(void);
+
+//*****************************************************************************
+//
+//! Enables a specific region.
+//!
+//! \param region is the region number to enable. Valid values are between
+//!  0 and 7 inclusively.
+//!
+//! This function is used to enable a memory protection region.  The region
+//! should already be configured with the MPU_setRegion() function.  Once
+//! enabled, the memory protection rules of the region are applied and access
+//! violations cause a memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_enableRegion(uint32_t region);
+
+//*****************************************************************************
+//
+//! Disables a specific region.
+//!
+//! \param region is the region number to disable. Valid values are between
+//!  0 and 7 inclusively.
+//!
+//! This function is used to disable a previously enabled memory protection
+//! region.  The region remains configured if it is not overwritten with
+//! another call to MPU_setRegion(), and can be enabled again by calling
+//! MPU_enableRegion().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_disableRegion(uint32_t region);
+
+//*****************************************************************************
+//
+//! Sets up the access rules for a specific region.
+//!
+//! \param region is the region number to set up.
+//! \param addr is the base address of the region.  It must be aligned
+//! according to the size of the region specified in flags.
+//! \param flags is a set of flags to define the attributes of the region.
+//!
+//! This function sets up the protection rules for a region.  The region has
+//! a base address and a set of attributes including the size. The base
+//! address parameter, \e addr, must be aligned according to the size, and
+//! the size must be a power of 2.
+//!
+//! \param region is the region number to set. Valid values are between
+//!  0 and 7 inclusively.
+//!
+//! The \e flags parameter is the logical OR of all of the attributes
+//! of the region.  It is a combination of choices for region size,
+//! execute permission, read/write permissions, disabled sub-regions,
+//! and a flag to determine if the region is enabled.
+//!
+//! The size flag determines the size of a region and must be one of the
+//! following:
+//!
+//! - \b MPU_RGN_SIZE_32B
+//! - \b MPU_RGN_SIZE_64B
+//! - \b MPU_RGN_SIZE_128B
+//! - \b MPU_RGN_SIZE_256B
+//! - \b MPU_RGN_SIZE_512B
+//! - \b MPU_RGN_SIZE_1K
+//! - \b MPU_RGN_SIZE_2K
+//! - \b MPU_RGN_SIZE_4K
+//! - \b MPU_RGN_SIZE_8K
+//! - \b MPU_RGN_SIZE_16K
+//! - \b MPU_RGN_SIZE_32K
+//! - \b MPU_RGN_SIZE_64K
+//! - \b MPU_RGN_SIZE_128K
+//! - \b MPU_RGN_SIZE_256K
+//! - \b MPU_RGN_SIZE_512K
+//! - \b MPU_RGN_SIZE_1M
+//! - \b MPU_RGN_SIZE_2M
+//! - \b MPU_RGN_SIZE_4M
+//! - \b MPU_RGN_SIZE_8M
+//! - \b MPU_RGN_SIZE_16M
+//! - \b MPU_RGN_SIZE_32M
+//! - \b MPU_RGN_SIZE_64M
+//! - \b MPU_RGN_SIZE_128M
+//! - \b MPU_RGN_SIZE_256M
+//! - \b MPU_RGN_SIZE_512M
+//! - \b MPU_RGN_SIZE_1G
+//! - \b MPU_RGN_SIZE_2G
+//! - \b MPU_RGN_SIZE_4G
+//!
+//! The execute permission flag must be one of the following:
+//!
+//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
+//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
+//!
+//! The read/write access permissions are applied separately for the
+//! privileged and user modes.  The read/write access flags must be one
+//! of the following:
+//!
+//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
+//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
+//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
+//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
+//!
+//! The region is automatically divided into 8 equally-sized sub-regions by
+//! the MPU.  Sub-regions can only be used in regions of size 256 bytes
+//! or larger.  Any of these 8 sub-regions can be disabled, allowing for
+//! creation of ``holes'' in a region which can be left open, or overlaid
+//! by another region with different attributes.  Any of the 8 sub-regions
+//! can be disabled with a logical OR of any of the following flags:
+//!
+//! - \b MPU_SUB_RGN_DISABLE_0
+//! - \b MPU_SUB_RGN_DISABLE_1
+//! - \b MPU_SUB_RGN_DISABLE_2
+//! - \b MPU_SUB_RGN_DISABLE_3
+//! - \b MPU_SUB_RGN_DISABLE_4
+//! - \b MPU_SUB_RGN_DISABLE_5
+//! - \b MPU_SUB_RGN_DISABLE_6
+//! - \b MPU_SUB_RGN_DISABLE_7
+//!
+//! Finally, the region can be initially enabled or disabled with one of
+//! the following flags:
+//!
+//! - \b MPU_RGN_ENABLE
+//! - \b MPU_RGN_DISABLE
+//!
+//! As an example, to set a region with the following attributes: size of
+//! 32 KB, execution enabled, read-only for both privileged and user, one
+//! sub-region disabled, and initially enabled; the \e flags parameter would
+//! have the following value:
+//!
+//! <code>
+//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
+//!  MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
+//! </code>
+//!
+//! \note This function writes to multiple registers and is not protected
+//! from interrupts.  It is possible that an interrupt which accesses a
+//! region may occur while that region is in the process of being changed.
+//! The safest way to handle this is to disable a region before changing it.
+//! Refer to the discussion of this in the API Detailed Description section.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current settings for a specific region.
+//!
+//! \param region is the region number to get. Valid values are between
+//!  0 and 7 inclusively.
+//! \param addr points to storage for the base address of the region.
+//! \param pflags points to the attribute flags for the region.
+//!
+//! This function retrieves the configuration of a specific region.  The
+//! meanings and format of the parameters is the same as that of the
+//! MPU_setRegion() function.
+//!
+//! This function can be used to save the configuration of a region for later
+//! use with the MPU_setRegion() function.  The region's enable state is
+//! preserved in the attributes that are saved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the memory management fault.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! memory management fault occurs.
+//!
+//! This function sets and enables the handler to be called when the MPU
+//! generates a memory management fault due to a protection region access
+//! violation.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the memory management fault.
+//!
+//! This function disables and clears the handler to be called when a
+//! memory management fault occurs.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Enables the interrupt for the memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_enableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Disables the interrupt for the memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void MPU_disableInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif //  __MPU_H__

platform/vendor_bsp/TI/MSP432P4xx/pcm.c

@@ -0,0 +1,609 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <pcm.h>
+#include <debug.h>
+#include <interrupt.h>
+#include <wdt_a.h>
+#include <rtc_c.h>
+#include <cpu.h>
+
+static bool __PCM_setCoreVoltageLevelAdvanced(uint_fast8_t voltageLevel,
+        uint32_t timeOut, bool blocking)
+{
+    uint8_t powerMode, bCurrentVoltageLevel;
+    uint32_t regValue;
+    bool boolTimeout;
+
+    ASSERT(voltageLevel == PCM_VCORE0 || voltageLevel == PCM_VCORE1);
+
+    /* Getting current power mode and level */
+    powerMode = PCM_getPowerMode();
+    bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
+
+    boolTimeout = timeOut > 0 ? true : false;
+
+    /* If we are already at the power mode they requested, return */
+    if (bCurrentVoltageLevel == voltageLevel)
+        return true;
+
+    while (bCurrentVoltageLevel != voltageLevel)
+    {
+        regValue = PCM->CTL0;
+
+        switch (PCM_getPowerState())
+        {
+        case PCM_AM_LF_VCORE1:
+        case PCM_AM_DCDC_VCORE1:
+        case PCM_AM_LDO_VCORE0:
+            PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
+                    | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            break;
+        case PCM_AM_LF_VCORE0:
+        case PCM_AM_DCDC_VCORE0:
+        case PCM_AM_LDO_VCORE1:
+            PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
+                    | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            break;
+        default:
+            ASSERT(false);
+        }
+
+        if(blocking)
+        {
+            while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+            {
+                if (boolTimeout && !(--timeOut))
+                    return false;
+
+            }
+        }
+        else
+        {
+            return true;
+        }
+
+        bCurrentVoltageLevel = PCM_getCoreVoltageLevel();
+    }
+
+    /* Changing the power mode if we are stuck in LDO mode */
+    if (powerMode != PCM_getPowerMode())
+    {
+        if (powerMode == PCM_DCDC_MODE)
+            return PCM_setPowerMode(PCM_DCDC_MODE);
+        else
+            return PCM_setPowerMode(PCM_LF_MODE);
+    }
+
+    return true;
+
+}
+
+
+bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel)
+{
+    return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, true);
+}
+
+bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
+        uint32_t timeOut)
+{
+    return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, timeOut, true);
+}
+
+bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel)
+{
+    return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, false);
+}
+
+uint8_t PCM_getPowerMode(void)
+{
+    uint8_t currentPowerState;
+
+    currentPowerState = PCM_getPowerState();
+
+    switch (currentPowerState)
+    {
+    case PCM_AM_LDO_VCORE0:
+    case PCM_AM_LDO_VCORE1:
+    case PCM_LPM0_LDO_VCORE0:
+    case PCM_LPM0_LDO_VCORE1:
+        return PCM_LDO_MODE;
+    case PCM_AM_DCDC_VCORE0:
+    case PCM_AM_DCDC_VCORE1:
+    case PCM_LPM0_DCDC_VCORE0:
+    case PCM_LPM0_DCDC_VCORE1:
+        return PCM_DCDC_MODE;
+    case PCM_LPM0_LF_VCORE0:
+    case PCM_LPM0_LF_VCORE1:
+    case PCM_AM_LF_VCORE1:
+    case PCM_AM_LF_VCORE0:
+        return PCM_LF_MODE;
+    default:
+        ASSERT(false);
+        return false;
+
+    }
+}
+
+uint8_t PCM_getCoreVoltageLevel(void)
+{
+    uint8_t currentPowerState = PCM_getPowerState();
+
+    switch (currentPowerState)
+    {
+    case PCM_AM_LDO_VCORE0:
+    case PCM_AM_DCDC_VCORE0:
+    case PCM_AM_LF_VCORE0:
+    case PCM_LPM0_LDO_VCORE0:
+    case PCM_LPM0_DCDC_VCORE0:
+    case PCM_LPM0_LF_VCORE0:
+        return PCM_VCORE0;
+    case PCM_AM_LDO_VCORE1:
+    case PCM_AM_DCDC_VCORE1:
+    case PCM_AM_LF_VCORE1:
+    case PCM_LPM0_LDO_VCORE1:
+    case PCM_LPM0_DCDC_VCORE1:
+    case PCM_LPM0_LF_VCORE1:
+        return PCM_VCORE1;
+    case PCM_LPM3:
+        return PCM_VCORELPM3;
+    default:
+        ASSERT(false);
+        return false;
+
+    }
+}
+
+static bool __PCM_setPowerModeAdvanced(uint_fast8_t powerMode, uint32_t timeOut,
+bool blocking)
+{
+    uint8_t bCurrentPowerMode, bCurrentPowerState;
+    uint32_t regValue;
+    bool boolTimeout;
+
+    ASSERT(
+            powerMode == PCM_LDO_MODE || powerMode == PCM_DCDC_MODE
+            || powerMode == PCM_LF_MODE);
+
+    /* Getting Current Power Mode */
+    bCurrentPowerMode = PCM_getPowerMode();
+
+    /* If the power mode being set it the same as the current mode, return */
+    if (powerMode == bCurrentPowerMode)
+        return true;
+
+    bCurrentPowerState = PCM_getPowerState();
+
+    boolTimeout = timeOut > 0 ? true : false;
+
+    /* Go through the while loop while we haven't achieved the power mode */
+    while (bCurrentPowerMode != powerMode)
+    {
+        regValue = PCM->CTL0;
+
+        switch (bCurrentPowerState)
+        {
+        case PCM_AM_DCDC_VCORE0:
+        case PCM_AM_LF_VCORE0:
+            PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
+                    | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            break;
+        case PCM_AM_LF_VCORE1:
+        case PCM_AM_DCDC_VCORE1:
+            PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
+                    | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            break;
+        case PCM_AM_LDO_VCORE1:
+        {
+            if (powerMode == PCM_DCDC_MODE)
+            {
+                PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
+                        | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            } else if (powerMode == PCM_LF_MODE)
+            {
+                PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
+                        | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            } else
+                ASSERT(false);
+
+            break;
+        }
+        case PCM_AM_LDO_VCORE0:
+        {
+            if (powerMode == PCM_DCDC_MODE)
+            {
+                PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
+                        | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            } else if (powerMode == PCM_LF_MODE)
+            {
+                PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
+                        | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
+            } else
+                ASSERT(false);
+
+            break;
+        }
+        default:
+            ASSERT(false);
+        }
+
+        if (blocking)
+        {
+            while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+            {
+                if (boolTimeout && !(--timeOut))
+                    return false;
+
+            }
+        } else
+            return true;
+
+        bCurrentPowerMode = PCM_getPowerMode();
+        bCurrentPowerState = PCM_getPowerState();
+    }
+
+    return true;
+
+}
+
+bool PCM_setPowerMode(uint_fast8_t powerMode)
+{
+    return __PCM_setPowerModeAdvanced(powerMode, 0, true);
+}
+
+bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode)
+{
+    return __PCM_setPowerModeAdvanced(powerMode, 0, false);
+}
+
+bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut)
+{
+    return __PCM_setPowerModeAdvanced(powerMode, timeOut, true);
+}
+
+static bool __PCM_setPowerStateAdvanced(uint_fast8_t powerState,
+        uint32_t timeout,
+        bool blocking)
+{
+    uint8_t bCurrentPowerState;
+    bCurrentPowerState = PCM_getPowerState();
+
+    ASSERT(
+            powerState == PCM_AM_LDO_VCORE0 || powerState == PCM_AM_LDO_VCORE1
+            || powerState == PCM_AM_DCDC_VCORE0 || powerState == PCM_AM_DCDC_VCORE1
+            || powerState == PCM_AM_LF_VCORE0 || powerState == PCM_AM_LF_VCORE1
+            || powerState == PCM_LPM0_LDO_VCORE0 || powerState == PCM_LPM0_LDO_VCORE1
+            || powerState == PCM_LPM0_DCDC_VCORE0 || powerState == PCM_LPM0_DCDC_VCORE1
+            || powerState == PCM_LPM3 || powerState == PCM_LPM35_VCORE0
+            || powerState == PCM_LPM45 || powerState == PCM_LPM4);
+
+    if (bCurrentPowerState == powerState)
+        return true;
+
+    switch (powerState)
+    {
+    case PCM_AM_LDO_VCORE0:
+        return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+                && __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking));
+    case PCM_AM_LDO_VCORE1:
+        return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+                && __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking));
+    case PCM_AM_DCDC_VCORE0:
+        return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+                && __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking));
+    case PCM_AM_DCDC_VCORE1:
+        return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+                && __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking));
+    case PCM_AM_LF_VCORE0:
+        return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+                && __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking));
+    case PCM_AM_LF_VCORE1:
+        return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+                && __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking));
+    case PCM_LPM0_LDO_VCORE0:
+        if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+                || !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_LDO_VCORE1:
+        if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+                || !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_DCDC_VCORE0:
+        if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+                || !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout,
+                        blocking))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_DCDC_VCORE1:
+        if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+                || !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout,
+                        blocking))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_LF_VCORE0:
+        if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking)
+                || !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM0_LF_VCORE1:
+        if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking)
+                || !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking))
+            break;
+        return PCM_gotoLPM0();
+    case PCM_LPM3:
+        return PCM_gotoLPM3();
+    case PCM_LPM4:
+        return PCM_gotoLPM4();
+    case PCM_LPM45:
+        return PCM_shutdownDevice(PCM_LPM45);
+    case PCM_LPM35_VCORE0:
+        return PCM_shutdownDevice(PCM_LPM35_VCORE0);
+    default:
+        ASSERT(false);
+        return false;
+    }
+
+    return false;
+
+}
+
+bool PCM_setPowerState(uint_fast8_t powerState)
+{
+    return __PCM_setPowerStateAdvanced(powerState, 0, true);
+}
+
+bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout)
+{
+    return __PCM_setPowerStateAdvanced(powerState, timeout, true);
+}
+
+bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState)
+{
+    return __PCM_setPowerStateAdvanced(powerState, 0, false);
+}
+
+bool PCM_shutdownDevice(uint32_t shutdownMode)
+{
+    uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ?
+            PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
+
+    ASSERT(
+            shutdownMode == PCM_SHUTDOWN_PARTIAL
+            || shutdownMode == PCM_SHUTDOWN_COMPLETE);
+
+    /* If a power transition is occuring, return false */
+    if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+        return false;
+
+    /* Initiating the shutdown */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    PCM->CTL0 = (PCM_KEY | shutdownModeBits
+            | (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)));
+
+    CPU_wfi();
+
+    return true;
+}
+
+bool PCM_gotoLPM4(void)
+{
+    /* Disabling RTC_C and WDT_A */
+    WDT_A_holdTimer();
+    RTC_C_holdClock();
+
+    /* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */
+    return PCM_gotoLPM3();
+}
+
+bool PCM_gotoLPM4InterruptSafe(void)
+{
+    bool slHappenedCorrect;
+
+    /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but 
+     master interrupts are disabled and a WFI happens the WFI will
+     immediately exit. */
+    Interrupt_disableMaster();
+
+    slHappenedCorrect = PCM_gotoLPM4();
+
+    /* Enabling and Disabling Interrupts very quickly so that the
+     processor catches any pending interrupts */
+    Interrupt_enableMaster();
+    Interrupt_disableMaster();
+
+    return slHappenedCorrect;
+}
+
+bool PCM_gotoLPM0(void)
+{
+    /* If we are in the middle of a state transition, return false */
+    if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+        return false;
+
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+    CPU_wfi();
+
+    return true;
+}
+
+bool PCM_gotoLPM0InterruptSafe(void)
+{
+    bool slHappenedCorrect;
+
+    /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but 
+     master interrupts are disabled and a WFI happens the WFI will
+     immediately exit. */
+    Interrupt_disableMaster();
+
+    slHappenedCorrect = PCM_gotoLPM0();
+
+    /* Enabling and Disabling Interrupts very quickly so that the
+     processor catches any pending interrupts */
+    Interrupt_enableMaster();
+    Interrupt_disableMaster();
+
+    return slHappenedCorrect;
+}
+
+bool PCM_gotoLPM3(void)
+{
+    uint_fast8_t bCurrentPowerState;
+    uint_fast8_t currentPowerMode;
+
+    /* If we are in the middle of a state transition, return false */
+    if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
+        return false;
+
+    /* If we are in the middle of a shutdown, return false */
+    if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
+            || (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
+        return false;
+
+    currentPowerMode = PCM_getPowerMode();
+    bCurrentPowerState = PCM_getPowerState();
+
+    if (currentPowerMode == PCM_DCDC_MODE)
+        PCM_setPowerMode(PCM_LDO_MODE);
+
+    /* Clearing the SDR */
+    PCM->CTL0 = (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY;
+
+    /* Setting the sleep deep bit */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    CPU_wfi();
+
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+    return PCM_setPowerState(bCurrentPowerState);
+}
+
+bool PCM_gotoLPM3InterruptSafe(void)
+{
+    bool lpmHappenedCorrect;
+
+    /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but 
+     master interrupts are disabled and a WFI happens the WFI will
+     immediately exit. */
+    Interrupt_disableMaster();
+
+    lpmHappenedCorrect = PCM_gotoLPM3();
+
+    /* Enabling and Disabling Interrupts very quickly so that the
+     processor catches any pending interrupts */
+    Interrupt_enableMaster();
+    Interrupt_disableMaster();
+
+    return lpmHappenedCorrect;
+}
+
+uint8_t PCM_getPowerState(void)
+{
+    return (PCM->CTL0 | PCM_CTL0_CPM_MASK);
+}
+
+void PCM_enableRudeMode(void)
+{
+
+    PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK)) | PCM_KEY
+            | PCM_CTL1_FORCE_LPM_ENTRY;
+}
+
+void PCM_disableRudeMode(void)
+{
+    PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK | PCM_CTL1_FORCE_LPM_ENTRY))
+            | PCM_KEY;
+}
+
+void PCM_enableInterrupt(uint32_t flags)
+{
+    PCM->IE |= flags;
+}
+
+void PCM_disableInterrupt(uint32_t flags)
+{
+    PCM->IE &= ~flags;
+}
+
+uint32_t PCM_getInterruptStatus(void)
+{
+    return PCM->IFG;
+}
+
+uint32_t PCM_getEnabledInterruptStatus(void)
+{
+    return PCM_getInterruptStatus() & PCM->IE;
+}
+
+void PCM_clearInterruptFlag(uint32_t flags)
+{
+    PCM->CLRIFG |= flags;
+}
+
+void PCM_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_PCM, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_PCM);
+}
+
+void PCM_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_PCM);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_PCM);
+}

platform/vendor_bsp/TI/MSP432P4xx/pcm.h

@@ -0,0 +1,711 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __PCM_H__
+#define __PCM_H__
+
+//*****************************************************************************
+//
+//! \addtogroup pcm_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables 
+//
+//*****************************************************************************
+#define PCM_KEY 0x695A0000
+
+/* Power Modes */
+#define PCM_AM_LDO_VCORE0      0x00
+#define PCM_AM_LDO_VCORE1      0x01
+#define PCM_AM_DCDC_VCORE0     0x04
+#define PCM_AM_DCDC_VCORE1     0x05
+#define PCM_AM_LF_VCORE0      0x08
+#define PCM_AM_LF_VCORE1      0x09
+#define PCM_LPM0_LDO_VCORE0    0x10
+#define PCM_LPM0_LDO_VCORE1    0x11
+#define PCM_LPM0_DCDC_VCORE0   0x14
+#define PCM_LPM0_DCDC_VCORE1   0x15
+#define PCM_LPM0_LF_VCORE0    0x18
+#define PCM_LPM0_LF_VCORE1    0x19
+#define PCM_LPM3               0x20
+#define PCM_LPM4               0x21
+#define PCM_LPM35_VCORE0       0xC0
+#define PCM_LPM45              0xA0
+
+#define PCM_VCORE0     0x00
+#define PCM_VCORE1     0x01
+#define PCM_VCORELPM3   0x02
+
+#define PCM_LDO_MODE   0x00
+#define PCM_DCDC_MODE  0x01
+#define PCM_LF_MODE   0x02
+
+#define PCM_SHUTDOWN_PARTIAL PCM_LPM35_VCORE0
+#define PCM_SHUTDOWN_COMPLETE PCM_LPM45
+
+#define PCM_DCDCERROR PCM_IE_DCDC_ERROR_IE
+#define PCM_AM_INVALIDTRANSITION PCM_IE_AM_INVALID_TR_IE
+#define PCM_SM_INVALIDCLOCK PCM_IE_LPM_INVALID_CLK_IE
+#define PCM_SM_INVALIDTRANSITION PCM_IE_LPM_INVALID_TR_IE
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//******************************************************************************
+//
+//! Sets the core voltage level (Vcore). The function will take care of all
+//! power state transitions needed to shift between core voltage levels.
+//! Because transitions between voltage levels may require changes power modes,
+//! the power mode might temporarily be change. The power mode will be returned
+//! to the original state (with the new voltage level) at the end of a
+//! successful execution of this function.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param voltageLevel The voltage level to be shifted to.
+//!           - \b PCM_VCORE0,
+//!           - \b PCM_VCORE1
+//!
+//! \return true if voltage level set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel);
+
+//******************************************************************************
+//
+//! Returns the current powers state of the system see the
+//! PCM_setCoreVoltageLevel function for specific information about the modes.
+//!
+//! \return The current voltage of the system
+//!
+//! Possible return values include:
+//!     - \b PCM_VCORE0
+//!     - \b PCM_VCORE1
+//!     - \b PCM_VCORELPM3
+//!
+//
+//******************************************************************************
+extern uint8_t PCM_getCoreVoltageLevel(void);
+
+//******************************************************************************
+//
+//! Sets the core voltage level (Vcore). This function will take care of all
+//! power state transitions needed to shift between core voltage levels.
+//! Because transitions between voltage levels may require changes power modes,
+//! the power mode might temporarily be change. The power mode will be returned
+//! to the original state (with the new voltage level) at the end of a
+//! successful execution of this function.
+//!
+//! This function is similar to PCMSetCoreVoltageLevel, however a timeout
+//! mechanism is used.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param voltageLevel The voltage level to be shifted to.
+//!           - \b PCM_VCORE0,
+//!           - \b PCM_VCORE1
+//!
+//! \param timeOut Number of loop iterations to timeout when checking for
+//!         power state transitions. This should be used for debugging initial
+//!         power/hardware configurations. After a stable hardware base is
+//!         established, the PCMSetCoreVoltageLevel function should be used
+//!
+//! \return true if voltage level set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel,
+        uint32_t timeOut);
+
+//******************************************************************************
+//
+//! Sets the core voltage level (Vcore).  This function is similar to
+//! PCM_setCoreVoltageLevel, however there are no polling flags to ensure
+//! a state has changed. Execution is returned back to the calling program
+//  and it is up to the user to ensure proper state transitions happen
+//! correctly. For MSP432, changing into different power modes/states
+//! require very specific logic. This function will initiate only one state
+//! transition and then return. It is up to the user to keep calling this
+//! function until the correct power state has been achieved.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param voltageLevel The voltage level to be shifted to.
+//!           - \b PCM_VCORE0,
+//!           - \b PCM_VCORE1
+//!
+//! \return true if voltage level set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel);
+
+//******************************************************************************
+//
+//! Switches between power modes. This function will take care of all
+//! power state transitions needed to shift between power modes. Note for
+//! changing to DCDC mode, specific hardware considerations are required.
+//!
+//! Refer to the device specific data sheet for specifics about power modes.
+//!
+//! \param powerMode The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_LDO_MODE,
+//!           - \b PCM_DCDC_MODE,
+//!           - \b PCM_LF_MODE
+//!
+//! \return true if power mode is set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setPowerMode(uint_fast8_t powerMode);
+
+//******************************************************************************
+//
+//! Switches between power modes. This function will take care of all
+//! power state transitions needed to shift between power modes. Note for
+//! changing to DCDC mode, specific hardware considerations are required.
+//!
+//! This function is similar to PCMSetPowerMode, however a timeout
+//! mechanism is used.
+//!
+//! Refer to the device specific data sheet for specifics about power modes.
+//!
+//! \param powerMode The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_LDO_MODE,
+//!           - \b PCM_DCDC_MODE,
+//!           - \b PCM_LF_MODE
+//!
+//! \param timeOut Number of loop iterations to timeout when checking for
+//!         power state transitions. This should be used for debugging initial
+//!         power/hardware configurations. After a stable hardware base is
+//!         established, the PCMSetPowerMode function should be used
+//!
+//! \return true if power mode is set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode,
+        uint32_t timeOut);
+
+//******************************************************************************
+//
+//! Sets the core voltage level (Vcore).  This function is similar to
+//! PCM_setPowerMode, however there are no polling flags to ensure
+//! a state has changed. Execution is returned back to the calling program
+//  and it is up to the user to ensure proper state transitions happen
+//! correctly. For MSP432, changing into different power modes/states
+//! require very specific logic. This function will initiate only one state
+//! transition and then return. It is up to the user to keep calling this
+//! function until the correct power state has been achieved.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param powerMode The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_LDO_MODE,
+//!           - \b PCM_DCDC_MODE,
+//!           - \b PCM_LF_MODE
+//!
+//! \return true if power mode change was initiated, false otherwise
+//
+//******************************************************************************
+extern bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode);
+
+//******************************************************************************
+//
+//! Returns the current powers state of the system see the \b PCM_setPowerState
+//! function for specific information about the modes.
+//!
+//! \return The current power mode of the system
+//!
+//
+//******************************************************************************
+extern uint8_t PCM_getPowerMode(void);
+
+//******************************************************************************
+//
+//! Switches between power states. This is a convenience function that combines
+//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as
+//! the LPM0/LPM3 functions.
+//!
+//! Refer to the device specific data sheet for specifics about power states.
+//!
+//! \param powerState The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_AM_LDO_VCORE0,      [Active Mode, LDO, VCORE0]
+//!           - \b PCM_AM_LDO_VCORE1,      [Active Mode, LDO, VCORE1]
+//!           - \b PCM_AM_DCDC_VCORE0,     [Active Mode, DCDC, VCORE0]
+//!           - \b PCM_AM_DCDC_VCORE1,     [Active Mode, DCDC, VCORE1]
+//!           - \b PCM_AM_LF_VCORE0,       [Active Mode, Low Frequency, VCORE0]
+//!           - \b PCM_AM_LF_VCORE1,       [Active Mode, Low Frequency, VCORE1]
+//!           - \b PCM_LPM0_LDO_VCORE0,    [LMP0, LDO, VCORE0]
+//!           - \b PCM_LPM0_LDO_VCORE1,    [LMP0, LDO, VCORE1]
+//!           - \b PCM_LPM0_DCDC_VCORE0,   [LMP0, DCDC, VCORE0]
+//!           - \b PCM_LPM0_DCDC_VCORE1,   [LMP0, DCDC, VCORE1]
+//!           - \b PCM_LPM0_LF_VCORE0,     [LMP0, Low Frequency, VCORE0]
+//!           - \b PCM_LPM0_LF_VCORE1,     [LMP0, Low Frequency, VCORE1]
+//!           - \b PCM_LPM3,               [LPM3]
+//!           - \b PCM_LPM35_VCORE0,       [LPM3.5 VCORE 0]
+//!           - \b PCM_LPM4,               [LPM4]
+//!           - \b PCM_LPM45,              [LPM4.5]
+//!
+//! \return true if power state is set, false otherwise.
+//
+//******************************************************************************
+extern bool PCM_setPowerState(uint_fast8_t powerState);
+
+//******************************************************************************
+//
+//! Switches between power states. This is a convenience function that combines
+//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as
+//! the LPM modes.
+//!
+//! This function is similar to PCM_setPowerState, however a timeout
+//! mechanism is used.
+//!
+//! Refer to the device specific data sheet for specifics about power states.
+//!
+//! \param powerState The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_AM_LDO_VCORE0,      [Active Mode, LDO, VCORE0]
+//!           - \b PCM_AM_LDO_VCORE1,      [Active Mode, LDO, VCORE1]
+//!           - \b PCM_AM_DCDC_VCORE0,     [Active Mode, DCDC, VCORE0]
+//!           - \b PCM_AM_DCDC_VCORE1,     [Active Mode, DCDC, VCORE1]
+//!           - \b PCM_AM_LF_VCORE0,       [Active Mode, Low Frequency, VCORE0]
+//!           - \b PCM_AM_LF_VCORE1,       [Active Mode, Low Frequency, VCORE1]
+//!           - \b PCM_LPM0_LDO_VCORE0,    [LMP0, LDO, VCORE0]
+//!           - \b PCM_LPM0_LDO_VCORE1,    [LMP0, LDO, VCORE1]
+//!           - \b PCM_LPM0_DCDC_VCORE0,   [LMP0, DCDC, VCORE0]
+//!           - \b PCM_LPM0_DCDC_VCORE1,   [LMP0, DCDC, VCORE1]
+//!           - \b PCM_LPM0_LF_VCORE0,     [LMP0, Low Frequency, VCORE0]
+//!           - \b PCM_LPM0_LF_VCORE1,     [LMP0, Low Frequency, VCORE1]
+//!           - \b PCM_LPM3,               [LPM3]
+//!           - \b PCM_LPM35_VCORE0,       [LPM3.5 VCORE 0]
+//!           - \b PCM_LPM4,               [LPM4]
+//!           - \b PCM_LPM45,              [LPM4.5]
+//!
+//! \param timeout Number of loop iterations to timeout when checking for
+//!         power state transitions. This should be used for debugging initial
+//!         power/hardware configurations. After a stable hardware base is
+//!         established, the PCMSetPowerMode function should be used
+//!
+//! \return true if power state is set, false otherwise. It is important to
+//!         note that if a timeout occurs, false will be returned, however the
+//!         power state at this point is not guaranteed to be the same as the
+//!         state prior to the function call
+//
+//******************************************************************************
+extern bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState,
+        uint32_t timeout);
+
+//******************************************************************************
+//
+//! Returns the current powers state of the system see the PCMChangePowerState
+//! function for specific information about the states.
+//!
+//! Refer to \link PCM_setPowerState \endlink for possible return values.
+//!
+//! \return The current power state of the system
+//
+//******************************************************************************
+extern uint8_t PCM_getPowerState(void);
+
+//******************************************************************************
+//
+//! Sets the power state of the part.  This function is similar to
+//! PCM_getPowerState, however there are no polling flags to ensure
+//! a state has changed. Execution is returned back to the calling program
+//  and it is up to the user to ensure proper state transitions happen
+//! correctly. For MSP432, changing into different power modes/states
+//! require very specific logic. This function will initiate only one state
+//! transition and then return. It is up to the user to keep calling this
+//! function until the correct power state has been achieved.
+//!
+//! Refer to the device specific data sheet for specifics about core voltage
+//! levels.
+//!
+//! \param powerState The voltage modes to be shifted to. Valid values are:
+//!           - \b PCM_AM_LDO_VCORE0,      [Active Mode, LDO, VCORE0]
+//!           - \b PCM_AM_LDO_VCORE1,      [Active Mode, LDO, VCORE1]
+//!           - \b PCM_AM_DCDC_VCORE0,     [Active Mode, DCDC, VCORE0]
+//!           - \b PCM_AM_DCDC_VCORE1,     [Active Mode, DCDC, VCORE1]
+//!           - \b PCM_AM_LF_VCORE0,       [Active Mode, Low Frequency, VCORE0]
+//!           - \b PCM_AM_LF_VCORE1,       [Active Mode, Low Frequency, VCORE1]
+//!           - \b PCM_LPM0_LDO_VCORE0,    [LMP0, LDO, VCORE0]
+//!           - \b PCM_LPM0_LDO_VCORE1,    [LMP0, LDO, VCORE1]
+//!           - \b PCM_LPM0_DCDC_VCORE0,   [LMP0, DCDC, VCORE0]
+//!           - \b PCM_LPM0_DCDC_VCORE1,   [LMP0, DCDC, VCORE1]
+//!           - \b PCM_LPM0_LF_VCORE0,     [LMP0, Low Frequency, VCORE0]
+//!           - \b PCM_LPM0_LF_VCORE1,     [LMP0, Low Frequency, VCORE1]
+//!           - \b PCM_LPM3,               [LPM3]
+//!           - \b PCM_LPM35_VCORE0,       [LPM3.5 VCORE 0]
+//!           - \b PCM_LPM45,              [LPM4.5]
+//!
+//! \return true if power state change was initiated, false otherwise
+//
+//******************************************************************************
+extern bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM3.5/LPM4.5 mode.
+//!
+//! Refer to the device specific data sheet for specifics about shutdown modes.
+//!
+//! The following events will cause a wake up from LPM3.5 mode:
+//! - Device reset
+//! - External reset RST
+//! - Enabled RTC, WDT, and wake-up I/O only interrupt events
+//!
+//! The following events will cause a wake up from the LPM4.5 mode:
+//! - Device reset
+//! - External reset RST
+//! - Wake-up I/O only interrupt events
+//!
+//! \param shutdownMode Specific mode to go to. Valid values are:
+//!            - \b PCM_LPM35_VCORE0
+//!            - \b PCM_LPM45
+//!
+//!
+//! \return false if LPM state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_shutdownDevice(uint32_t shutdownMode);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM0.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//!
+//! \return false if LPM0 state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM0(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM3
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//! Note that since LPM3 cannot be entered from  a DCDC power modes, the
+//! power mode is first switched to LDO operation (if in DCDC mode), 
+//! LPM3 is entered, and the DCDC mode is restored on wake up.
+//!
+//! \return false if LPM3 state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM3(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM0 while maintaining a safe
+//! interrupt handling mentality. This function is meant to be used in
+//! situations where the user wants to go to LPM0, however does not want
+//! to go to "miss" any interrupts due to the fact that going to LPM0 is not
+//! an atomic operation. This function will modify the PRIMASK and on exit of
+//! the program the master interrupts will be disabled.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//!
+//! \return false if LPM0 state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM0InterruptSafe(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM3 while maintaining a safe
+//! interrupt handling mentality. This function is meant to be used in
+//! situations where the user wants to go to LPM3, however does not want
+//! to go to "miss" any interrupts due to the fact that going to LPM3 is not
+//! an atomic operation. This function will modify the PRIMASK and on exit of
+//! the program the master interrupts will be disabled.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//! Note that since LPM3 cannot be entered from  a DCDC power modes, the
+//! power mode is first switched to LDO operation (if in DCDC mode), the LPM3
+//! is entered, and the DCDC mode is restored on wake up.
+//!
+//! \return false if LPM3 cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM3InterruptSafe(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM4. LPM4 is the exact same with LPM3, just
+//! with RTC_C and WDT_A disabled. When waking up, RTC_C and WDT_A will remain
+//! disabled until reconfigured by the user.
+//!
+//! \return false if LPM4 state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM4(void);
+
+//******************************************************************************
+//
+//! Transitions the device into LPM4 while maintaining a safe
+//! interrupt handling mentality. This function is meant to be used in
+//! situations where the user wants to go to LPM4, however does not want
+//! to go to "miss" any interrupts due to the fact that going to LPM4 is not
+//! an atomic operation. This function will modify the PRIMASK and on exit of
+//! the program the master interrupts will be disabled.
+//!
+//! Refer to the device specific data sheet for specifics about low power modes.
+//! Note that since LPM3 cannot be entered from  a DCDC power modes, the
+//! power mode is first switched to LDO operation (if in DCDC mode), 
+//! LPM4 is entered, and the DCDC mode is restored on wake up.
+//!
+//! \return false if LPM4 state cannot be entered, true otherwise.
+//
+//******************************************************************************
+extern bool PCM_gotoLPM4InterruptSafe(void);
+
+//******************************************************************************
+//
+//! Enables "rude mode" entry into LPM3 and shutdown modes. With this mode
+//! enabled, an entry into shutdown or LPM3 will occur even if there are
+//! clock systems active. The system will forcibly  turn off all clock/systems
+//! when going into these modes.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void PCM_enableRudeMode(void);
+
+//******************************************************************************
+//
+//! Disables "rude mode" entry into LPM3 and shutdown modes. With this
+//! mode disabled, an entry into shutdown or LPM3 will wait for any
+//! active clock requests to free up before going into LPM3 or shutdown.
+//!
+//! \return None
+//
+//******************************************************************************
+extern void PCM_disableRudeMode(void);
+
+//*****************************************************************************
+//
+//! Enables individual power control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! This function enables the indicated power control interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_enableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Disables individual power control interrupt sources.
+//!
+//! \param flags is a bit mask of the interrupt sources to be enabled.  Must
+//! be a logical OR of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! This function disables the indicated power control interrupt sources.  Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_disableInterrupt(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t PCM_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \return The current interrupt status, enumerated as a bit field of:
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//
+//*****************************************************************************
+extern uint32_t PCM_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears power system interrupt sources.
+//!
+//! The specified power system interrupt sources are cleared, so that they no
+//! longer assert.  This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared.  Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \param flags is a bit mask of the interrupt sources to be cleared.  Must
+//! be a logical OR of
+//!         - \b PCM_DCDCERROR,
+//!         - \b PCM_AM_INVALIDTRANSITION,
+//!         - \b PCM_SM_INVALIDCLOCK,
+//!         - \b PCM_SM_INVALIDTRANSITION
+//!
+//! \note The interrupt sources vary based on the part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_clearInterruptFlag(uint32_t flags);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the power system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the power
+//! system interrupt occurs.
+//!
+//! This function registers the handler to be called when a clock system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific PCM  interrupts must be enabled
+//! via PCM_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via \link PCM_clearInterruptFlag \endlink .
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the power system.
+//!
+//! This function unregisters the handler to be called when a power system
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PCM_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __PCM_H__

platform/vendor_bsp/TI/MSP432P4xx/pmap.c

@@ -0,0 +1,66 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <debug.h>
+#include <pmap.h>
+
+
+void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
+        uint8_t numberOfPorts, uint8_t portMapReconfigure)
+{
+    uint_fast16_t i;
+
+    ASSERT(
+            (portMapReconfigure == PMAP_ENABLE_RECONFIGURATION)
+                    || (portMapReconfigure == PMAP_DISABLE_RECONFIGURATION));
+
+    //Get write-access to port mapping registers:
+    PMAP->KEYID = PMAP_KEYID_VAL;
+
+    //Enable/Disable reconfiguration during runtime
+    PMAP->CTL = (PMAP->CTL & ~PMAP_CTL_PRECFG) | portMapReconfigure;
+
+    //Configure Port Mapping:
+    
+    for (i = 0; i < numberOfPorts * 8; i++)
+    {
+        HWREG8(PMAP_BASE + i + pxMAPy) = portMapping[i];
+    }
+
+    //Disable write-access to port mapping registers:
+    PMAP->KEYID = 0;
+}
+

platform/vendor_bsp/TI/MSP432P4xx/pmap.h

@@ -0,0 +1,129 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __PMAP_H__
+#define __PMAP_H__
+
+//*****************************************************************************
+//
+//! \addtogroup pmap_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+//The following are values that can be passed to the PMAP_configurePorts() API
+//as the portMapReconfigure parameter.
+//
+//*****************************************************************************
+#define PMAP_ENABLE_RECONFIGURATION     PMAP_CTL_PRECFG
+#define PMAP_DISABLE_RECONFIGURATION    0x00
+
+//*****************************************************************************
+//
+//The following are values that can be passed to the PMAP_configurePorts() API
+//as the pxMAPy parameter.
+//
+//*****************************************************************************
+#define PMAP_P1MAP ((uint32_t)P1MAP - PMAP_BASE)
+#define PMAP_P2MAP ((uint32_t)P2MAP - PMAP_BASE)
+#define PMAP_P3MAP ((uint32_t)P3MAP - PMAP_BASE)
+#define PMAP_P4MAP ((uint32_t)P4MAP - PMAP_BASE)
+#define PMAP_P5MAP ((uint32_t)P5MAP - PMAP_BASE)
+#define PMAP_P6MAP ((uint32_t)P6MAP - PMAP_BASE)
+#define PMAP_P7MAP ((uint32_t)P7MAP - PMAP_BASE)
+
+
+//*****************************************************************************
+//
+//Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! This function configures the MSP432 Port Mapper
+//!
+//! \param portMapping is the pointer to init Data
+//! \param pxMAPy is the Port Mapper to initialize
+//! \param numberOfPorts is the number of Ports to initialize
+//! \param portMapReconfigure is used to enable/disable reconfiguration
+//!             Valid values are
+//!             \b PMAP_ENABLE_RECONFIGURATION
+//!             \b PMAP_DISABLE_RECONFIGURATION [Default value]
+//! Modified registers are \b PMAPKEYID, \b PMAPCTL
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy,
+        uint8_t numberOfPorts, uint8_t portMapReconfigure);
+
+/* Defines for future devices that might have multiple instances */
+#define PMAP_configurePortsMultipleInstance(a,b,c,d,e) PMAP_configurePorts(b,c,d,e)
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif

platform/vendor_bsp/TI/MSP432P4xx/pss.c

@@ -0,0 +1,224 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <pss.h>
+#include <interrupt.h>
+#include <debug.h>
+#include <cpu.h>
+
+static void __PSSUnlock()
+{
+    PSS->KEY = PSS_KEY_VALUE;
+}
+
+static void __PSSLock()
+{
+    PSS->KEY = 0;
+}
+
+
+void PSS_enableForcedDCDCOperation(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 1;
+
+    __PSSLock();
+}
+
+void PSS_disableForcedDCDCOperation(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 0;
+
+    __PSSLock();
+
+}
+
+void PSS_enableHighSidePinToggle(bool activeLow)
+{
+    __PSSUnlock();
+
+    if (activeLow)
+        PSS->CTL0 |= (PSS_CTL0_SVMHOE | PSS_CTL0_SVMHOUTPOLAL);
+    else
+    {
+        BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOUTPOLAL_OFS) = 0;
+        BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 1;
+    }
+
+    __PSSLock();
+}
+
+void PSS_disableHighSidePinToggle(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_enableHighSide(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_disableHighSide(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 1;
+
+    __PSSLock();
+}
+
+void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode)
+{
+    __PSSUnlock();
+
+    if (powerMode == PSS_FULL_PERFORMANCE_MODE)
+        BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 0;
+    else
+        BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 1;
+
+    __PSSLock();
+}
+
+uint_fast8_t PSS_getHighSidePerformanceMode(void)
+{
+    if (BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS))
+        return PSS_NORMAL_PERFORMANCE_MODE;
+    else
+        return PSS_FULL_PERFORMANCE_MODE;
+}
+
+void PSS_enableHighSideMonitor(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 1;
+
+    __PSSLock();
+}
+
+void PSS_disableHighSideMonitor(void)
+{
+    __PSSUnlock();
+
+    BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 0;
+
+    __PSSLock();
+}
+
+void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage)
+{
+    __PSSUnlock();
+
+    ASSERT(!(triggerVoltage & 0xF8))
+
+    PSS->CTL0 &= ~PSS_CTL0_SVSMHTH_MASK;
+    PSS->CTL0 |= (triggerVoltage & 0x07) << PSS_CTL0_SVSMHTH_OFS;
+
+    __PSSLock();
+}
+
+uint_fast8_t PSS_getHighSideVoltageTrigger(void)
+{
+    return (uint_fast8_t)((PSS->CTL0 & PSS_CTL0_SVSMHTH_MASK)
+            >> PSS_CTL0_SVSMHTH_OFS);
+}
+
+void PSS_enableInterrupt(void)
+{
+    __PSSUnlock();
+    BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 1;
+    __PSSLock();
+}
+
+void PSS_disableInterrupt(void)
+{
+    __PSSUnlock();
+    BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 0;
+    __PSSLock();
+}
+
+uint32_t PSS_getInterruptStatus(void)
+{
+    return PSS->IFG;
+}
+
+void PSS_clearInterruptFlag(void)
+{
+    __PSSUnlock();
+    BITBAND_PERI(PSS->CLRIFG,PSS_CLRIFG_CLRSVSMHIFG_OFS) = 0;
+    __PSSLock();
+}
+
+void PSS_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_PSS, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt(INT_PSS);
+}
+
+void PSS_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt(INT_PSS);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_PSS);
+}

platform/vendor_bsp/TI/MSP432P4xx/pss.h

@@ -0,0 +1,321 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __PSS_H__
+#define __PSS_H__
+
+//*****************************************************************************
+//
+//! \addtogroup pss_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define PSS_KEY_VALUE PSS_KEY_KEY_VAL
+
+#define PSS_SVSMH PSS_IE_SVSMHIE
+
+#define PSS_FULL_PERFORMANCE_MODE   0x01
+#define PSS_NORMAL_PERFORMANCE_MODE 0x00
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables output of the High Side interrupt flag on the device \b SVMHOUT pin
+//!
+//! \param activeLow True if the signal should be logic low when SVSMHIFG
+//!     is set. False if signal should be high when \b SVSMHIFG is set.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableHighSidePinToggle(bool activeLow);
+
+//*****************************************************************************
+//
+//! Disables output of the High Side interrupt flag on the device \b SVMHOUT pin
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableHighSidePinToggle(void);
+
+//*****************************************************************************
+//
+//! Enables high side voltage supervisor/monitor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableHighSide(void);
+
+//*****************************************************************************
+//
+//! Disables high side voltage supervisor/monitor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableHighSide(void);
+
+//*****************************************************************************
+//
+//! Sets the performance mode of the high side regulator. Full performance
+//! mode allows for the best response times while normal performance mode is
+//! optimized for the lowest possible current consumption.
+//!
+//! \param powerMode is the performance mode to set. Valid values are one of
+//! the following:
+//!     - \b PSS_FULL_PERFORMANCE_MODE,
+//!     - \b PSS_NORMAL_PERFORMANCE_MODE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode);
+
+//*****************************************************************************
+//
+//! Gets the performance mode of the high side voltage regulator. Refer to the
+//! user's guide for specific information about information about the different
+//! performance modes.
+//!
+//! \return Performance mode of the voltage regulator
+//
+//*****************************************************************************
+extern uint_fast8_t PSS_getHighSidePerformanceMode(void);
+
+//*****************************************************************************
+//
+//! Sets the high side voltage supervisor to monitor mode
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableHighSideMonitor(void);
+
+//*****************************************************************************
+//
+//! Switches the high side of the power supply system to be a supervisor instead
+//! of a monitor
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableHighSideMonitor(void);
+
+//*****************************************************************************
+//
+//! Sets the voltage level at which the high side of the device voltage
+//! regulator triggers a reset. This value is represented as an unsigned eight
+//! bit integer where only the lowest three bits are most significant.
+//!
+//! \param triggerVoltage Voltage level in which high side supervisor/monitor
+//!         triggers a reset. See the device specific data sheet for details
+//!         on these voltage levels.
+//!
+//! Typical values will vary from part to part (so it is very important to
+//! check the SVSH section of the data sheet. For reference only, the typical
+//! MSP432 101 values are listed below:
+//!     - 0 --> 1.57V
+//!     - 1 --> 1.62V
+//!     - 2 --> 1.83V
+//!     - 3 --> 2V
+//!     - 4 --> 2.25V
+//!     - 5 --> 2.4V
+//!     - 6 --> 2.6V
+//!     - 7 --> 2.8V
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage);
+
+//*****************************************************************************
+//
+//! Returns the voltage level at which the high side of the device voltage
+//! regulator triggers a reset.
+//!
+//! \return The voltage level that the high side voltage supervisor/monitor
+//! triggers a reset. This value is represented as an unsigned eight
+//! bit integer where only the lowest three bits are most significant.
+//! See \link PSS_setHighSideVoltageTrigger \endlink for information regarding
+//! the return value
+//
+//*****************************************************************************
+extern uint_fast8_t PSS_getHighSideVoltageTrigger(void);
+
+//*****************************************************************************
+//
+//! Enables the power supply system interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Disables the power supply system interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \return The current interrupt status ( \b PSS_SVSMH )
+//!
+//*****************************************************************************
+extern uint32_t PSS_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears power supply system interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_clearInterruptFlag(void);
+
+
+//*****************************************************************************
+//
+//! Enables the "forced" mode of the DCDC regulator. In this mode, the fail
+//! safe mechanism that disables the regulator to LDO mode when the supply
+//! voltage falls below the minimum supply voltage required for DCDC operation
+//! is turned off.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_enableForcedDCDCOperation(void);
+
+
+//*****************************************************************************
+//
+//! Disables the "forced" mode of the DCDC regulator. In this mode, the fail
+//! safe mechanism that disables the regulator to LDO mode when the supply
+//! voltage falls below the minimum supply voltage required for DCDC operation
+//! is turned on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_disableForcedDCDCOperation(void);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the power supply system interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the power
+//! supply system interrupt occurs.
+//!
+//! This function registers the handler to be called when a power supply system
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific PSS interrupts must be enabled
+//! via PSS_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via PSS_clearInterruptFlag().
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the power supply system
+//!
+//! This function unregisters the handler to be called when a power supply
+//! system interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void PSS_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __PSS_H__

platform/vendor_bsp/TI/MSP432P4xx/ref_a.c

@@ -0,0 +1,116 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <ref_a.h>
+#include <debug.h>
+
+void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect)
+{
+    ASSERT(referenceVoltageSelect <= REF_A_VREF2_5V);
+
+    REF_A->CTL0 = (REF_A->CTL0 &  ~REF_A_CTL0_VSEL_3) | referenceVoltageSelect;
+}
+
+void REF_A_disableTempSensor(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 1;
+}
+
+void REF_A_enableTempSensor(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 0;
+}
+
+void REF_A_enableReferenceVoltageOutput(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 1;
+}
+
+void REF_A_disableReferenceVoltageOutput(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 0;
+}
+
+void REF_A_enableReferenceVoltage(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 1;
+}
+
+void REF_A_disableReferenceVoltage(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 0;
+}
+
+uint_fast8_t REF_A_getBandgapMode(void)
+{
+    return (REF_A->CTL0 & REF_A_CTL0_BGMODE);
+}
+
+bool REF_A_isBandgapActive(void)
+{
+    return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGACT_OFS);
+}
+
+bool REF_A_isRefGenBusy(void)
+{
+    return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENBUSY_OFS);
+}
+
+bool REF_A_isRefGenActive(void)
+{
+    return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENACT_OFS);
+}
+
+bool REF_A_getBufferedBandgapVoltageStatus(void)
+{
+    return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGRDY_OFS);
+}
+
+bool REF_A_getVariableReferenceVoltageStatus(void)
+{
+    return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENRDY_OFS);
+}
+
+void REF_A_setReferenceVoltageOneTimeTrigger(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENOT_OFS) = 1;
+}
+
+void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void)
+{
+    BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGOT_OFS) = 1;
+}
+

platform/vendor_bsp/TI/MSP432P4xx/ref_a.h

@@ -0,0 +1,346 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __REF_B_H__
+#define __REF_B_H__
+
+//*****************************************************************************
+//
+//! \addtogroup ref_api
+//! @{
+//
+//*****************************************************************************
+
+#include <msp.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//The following are values that can be passed to Ref_setReferenceVoltage()
+//in the referenceVoltageSelect parameter.
+//
+//*****************************************************************************
+#define REF_A_VREF1_2V  REF_A_CTL0_VSEL_0
+#define REF_A_VREF1_45V REF_A_CTL0_VSEL_1
+#define REF_A_VREF2_5V  REF_A_CTL0_VSEL_3
+
+//*****************************************************************************
+//
+//The following are values that are returned by Ref_getBandgapMode().
+//
+//*****************************************************************************
+#define REF_A_STATICMODE 0x0
+#define REF_A_SAMPLEMODE REF_A_CTL0_BGMODE
+
+//*****************************************************************************
+//
+//! Sets the reference voltage for the voltage generator.
+//!
+//! \param referenceVoltageSelect is the desired voltage to generate for a
+//!       reference voltage.
+//!        Valid values are:
+//!        - \b REF_A_VREF1_2V [Default]
+//!        - \b REF_A_VREF1_45V
+//!        - \b REF_A_VREF2_5V
+//!        Modified bits are \b REFVSEL of \b REFCTL0 register.
+//!
+//! This function sets the reference voltage generated by the voltage generator
+//! to be used by other peripherals. This reference voltage will only be valid
+//! while the REF module is in control.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns \b REF_BUSY,
+//! this function  will have no effect.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect);
+
+//*****************************************************************************
+//
+//! Disables the internal temperature sensor to save power consumption.
+//!
+//! This function is used to turn off the internal temperature sensor to save
+//! on power consumption. The temperature sensor is enabled by default. Please
+//! note, that giving ADC12 module control over the REF module, the state of the
+//! temperature sensor is dependent on the controls of the ADC12 module.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink  returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFTCOFF of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_disableTempSensor(void);
+
+//*****************************************************************************
+//
+//! Enables the internal temperature sensor.
+//!
+//! This function is used to turn on the internal temperature sensor to use by
+//! other peripherals. The temperature sensor is enabled by default.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFTCOFF of \b REFCTL0 register.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_enableTempSensor(void);
+
+//*****************************************************************************
+//
+//! Outputs the reference voltage to an output pin.
+//!
+//! This function is used to output the reference voltage being generated to an
+//! output pin. Please note, the output pin is device specific. Please note,
+//! that giving ADC12 module control over the REF module, the state of the
+//! reference voltage as an output to a pin is dependent on the controls of the
+//! ADC12 module.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFOUT of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_enableReferenceVoltageOutput(void);
+
+//*****************************************************************************
+//
+//! Disables the reference voltage as an output to a pin.
+//!
+//! This function is used to disables the reference voltage being generated to
+//! be given to an output pin.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! \b REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFOUT of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_disableReferenceVoltageOutput(void);
+
+//*****************************************************************************
+//
+//! Enables the reference voltage to be used by peripherals.
+//!
+//! This function is used to enable the generated reference voltage to be used
+//! other peripherals or by an output pin, if enabled. Please note, that giving
+//! ADC12 module control over the REF module, the state of the reference voltage
+//! is dependent on the controls of the ADC12 module.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//! REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFON of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_enableReferenceVoltage(void);
+
+//*****************************************************************************
+//
+//! Disables the reference voltage.
+//!
+//! This function is used to disable the generated reference voltage.
+//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns
+//!  \b  REF_A_BUSY, this function will have no effect.
+//!
+//! Modified bits are \b REFON of \b REFCTL0 register.
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_disableReferenceVoltage(void);
+
+//*****************************************************************************
+//
+//! Returns the bandgap mode of the REF module.
+//!
+//! This function is used to return the bandgap mode of the REF module,
+//! requested by the peripherals using the bandgap. If a peripheral requests
+//! static mode, then the bandgap mode will be static for all modules, whereas
+//! if all of the peripherals using the bandgap request sample mode, then that
+//! will be the mode returned. Sample mode allows the bandgap to be active only
+//! when necessary to save on power consumption, static mode requires the
+//! bandgap to be active until no peripherals are using it anymore.
+//!
+//! \return The bandgap mode of the REF module:
+//!        - \b REF_A_STATICMODE if the bandgap is operating in static mode
+//!        - \b REF_A_SAMPLEMODE if the bandgap is operating in sample mode
+//
+//*****************************************************************************
+extern uint_fast8_t REF_A_getBandgapMode(void);
+
+//*****************************************************************************
+//
+//! Returns the active status of the bandgap in the REF module.
+//!
+//! This function is used to return the active status of the bandgap in the REF
+//! module. If the bandgap is in use by a peripheral, then the status will be
+//! seen as active.
+//!
+//! \return true if the bandgap is being used, false otherwise
+//
+//*****************************************************************************
+extern bool REF_A_isBandgapActive(void);
+
+//*****************************************************************************
+//
+//! Returns the busy status of the reference generator in the REF module.
+//!
+//! This function is used to return the busy status of the reference generator
+//! in the REF module. If the ref. generator is in use by a peripheral, then the
+//! status will be seen as busy.
+//!
+//! \return true if the reference generator is being used, false otherwise.
+//*****************************************************************************
+extern bool REF_A_isRefGenBusy(void);
+
+//*****************************************************************************
+//
+//! Returns the active status of the reference generator in the REF module.
+//!
+//! This function is used to return the active status of the reference generator
+//! in the REF module. If the ref. generator is on and ready to use, then the
+//! status will be seen as active.
+//!
+//! \return true if the reference generator is active, false otherwise.
+//
+//*****************************************************************************
+extern bool REF_A_isRefGenActive(void);
+
+//*****************************************************************************
+//
+//! Returns the busy status of the reference generator in the REF module.
+//!
+//! This function is used to return the buys status of the buffered bandgap
+//! voltage in the REF module. If the ref. generator is on and ready to use,
+//! then the status will be seen as active.
+//!
+//! \return true if the buffered bandgap voltage is ready to be used, false
+//!         otherwise
+//
+//*****************************************************************************
+extern bool REF_A_getBufferedBandgapVoltageStatus(void);
+
+//*****************************************************************************
+//
+//! Returns the busy status of the variable reference voltage in the REF module.
+//!
+//! This function is used to return the buys status of the variable reference
+//! voltage in the REF module. If the ref. generator is on and ready to use,
+//! then the status will be seen as active.
+//!
+//! \return true if the variable bandgap voltage is ready to be used, false
+//!         otherwise
+//
+//*****************************************************************************
+extern bool REF_A_getVariableReferenceVoltageStatus(void);
+
+//*****************************************************************************
+//
+//! Enables the one-time trigger of the reference voltage.
+//!
+//! Triggers the one-time generation of the variable reference voltage.  Once
+//! the reference voltage request is set, this bit is cleared by hardware
+//!
+//! Modified bits are \b REFGENOT of \b REFCTL0 register.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_setReferenceVoltageOneTimeTrigger(void);
+
+//*****************************************************************************
+//
+//! Enables the one-time trigger of the buffered bandgap voltage.
+//!
+//! Triggers the one-time generation of the buffered bandgap voltage.  Once
+//! the buffered bandgap voltage request is set, this bit is cleared by hardware
+//!
+//! Modified bits are \b RefGOT of \b REFCTL0 register.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void);
+
+/* Defines for future devices that might have multiple instances */
+#define REF_A_setReferenceVoltageMultipleInstance(a,b) REF_A_setReferenceVoltage(b)
+#define REF_A_disableTempSensorMultipleInstance(a) REF_A_disableTempSensor()
+#define REF_A_enableTempSensorMultipleInstance(a) REF_A_enableTempSensor()
+#define REF_A_enableReferenceVoltageOutputMultipleInstance(a) REF_A_enableReferenceVoltageOutput()
+#define REF_A_disableReferenceVoltageOutputMultipleInstance(a) REF_A_disableReferenceVoltageOutput()
+#define REF_A_enableReferenceVoltageMultipleInstance(a) REF_A_enableReferenceVoltage()
+#define REF_A_disableReferenceVoltageMultipleInstance(a) REF_A_disableReferenceVoltage()
+#define REF_A_getBandgapModeMultipleInstance(a) REF_A_getBandgapMode()
+#define REF_A_isBandgapActiveMultipleInstance(a) REF_A_isBandgapActive()
+#define REF_A_isRefGenBusyMultipleInstance(a) REF_A_isRefGenBusy()
+#define REF_A_isRefGenActiveMultipleInstance(a) REF_A_isRefGenActive()
+#define REF_A_getBufferedBandgapVoltageStatusMultipleInstance(a) REF_A_getBufferedBandgapVoltageStatus()
+#define REF_A_getVariableReferenceVoltageStatusMultipleInstance(a) REF_A_getVariableReferenceVoltageStatus()
+#define REF_A_setReferenceVoltageOneTimeTriggerMultipleInstance(a) REF_A_setReferenceVoltageOneTimeTrigger()
+#define REF_A_setBufferedBandgapVoltageOneTimeTriggerMultipleInstance(a) REF_A_setBufferedBandgapVoltageOneTimeTrigger()
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __REF_A_H__

platform/vendor_bsp/TI/MSP432P4xx/reset.c

@@ -0,0 +1,99 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <reset.h>
+#include <debug.h>
+
+void ResetCtl_initiateSoftReset(void)
+{
+    RSTCTL->RESET_REQ |= (RESET_KEY | RESET_SOFT_RESET);
+}
+
+void ResetCtl_initiateSoftResetWithSource(uint32_t source)
+{
+    RSTCTL->SOFTRESET_SET |= (source);
+}
+
+uint32_t ResetCtl_getSoftResetSource(void)
+{
+    return RSTCTL->SOFTRESET_STAT;
+}
+
+void ResetCtl_clearSoftResetSource(uint32_t mask)
+{
+    RSTCTL->SOFTRESET_CLR |= mask;
+}
+
+void ResetCtl_initiateHardReset(void)
+{
+    RSTCTL->RESET_REQ |= (RESET_KEY | RESET_HARD_RESET);
+}
+
+void ResetCtl_initiateHardResetWithSource(uint32_t source)
+{
+    RSTCTL->HARDRESET_SET |= (source);
+}
+
+uint32_t ResetCtl_getHardResetSource(void)
+{
+    return RSTCTL->HARDRESET_STAT;
+}
+
+void ResetCtl_clearHardResetSource(uint32_t mask)
+{
+    RSTCTL->HARDRESET_CLR |= mask;
+}
+
+uint32_t ResetCtl_getPSSSource(void)
+{
+    return RSTCTL->PSSRESET_STAT;
+}
+
+void ResetCtl_clearPSSFlags(void)
+{
+    RSTCTL->PSSRESET_CLR |= RSTCTL_PSSRESET_CLR_CLR;
+}
+
+uint32_t ResetCtl_getPCMSource(void)
+{
+    return RSTCTL->PCMRESET_STAT;
+}
+
+void ResetCtl_clearPCMFlags(void)
+{
+    RSTCTL->PCMRESET_CLR |= RSTCTL_PCMRESET_CLR_CLR;
+}
+

platform/vendor_bsp/TI/MSP432P4xx/reset.h

@@ -0,0 +1,343 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __RESET_H__
+#define __RESET_H__
+
+//*****************************************************************************
+//
+//! \addtogroup reset_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Control specific variables 
+//
+//*****************************************************************************
+#define RESET_KEY   0x6900
+#define RESET_HARD_RESET RSTCTL_RESET_REQ_HARD_REQ
+#define RESET_SOFT_RESET RSTCTL_RESET_REQ_SOFT_REQ
+
+#define RESET_SRC_0 RSTCTL_HARDRESET_CLR_SRC0
+#define RESET_SRC_1 RSTCTL_HARDRESET_CLR_SRC1
+#define RESET_SRC_2 RSTCTL_HARDRESET_CLR_SRC2
+#define RESET_SRC_3 RSTCTL_HARDRESET_CLR_SRC3
+#define RESET_SRC_4 RSTCTL_HARDRESET_CLR_SRC4
+#define RESET_SRC_5 RSTCTL_HARDRESET_CLR_SRC5
+#define RESET_SRC_6 RSTCTL_HARDRESET_CLR_SRC6
+#define RESET_SRC_7 RSTCTL_HARDRESET_CLR_SRC7
+#define RESET_SRC_8 RSTCTL_HARDRESET_CLR_SRC8
+#define RESET_SRC_9 RSTCTL_HARDRESET_CLR_SRC9
+#define RESET_SRC_10 RSTCTL_HARDRESET_CLR_SRC10
+#define RESET_SRC_11 RSTCTL_HARDRESET_CLR_SRC11
+#define RESET_SRC_12 RSTCTL_HARDRESET_CLR_SRC12
+#define RESET_SRC_13 RSTCTL_HARDRESET_CLR_SRC13
+#define RESET_SRC_14 RSTCTL_HARDRESET_CLR_SRC14
+#define RESET_SRC_15 RSTCTL_HARDRESET_CLR_SRC15
+
+#define RESET_VCCDET    RSTCTL_PSSRESET_CLR_BGREF
+#define RESET_SVSH_TRIP RSTCTL_PSSRESET_CLR_SVSMH
+#define RESET_BGREF_BAD RSTCTL_PSSRESET_CLR_BGREF
+
+#define RESET_LPM35   RSTCTL_PCMRESET_CLR_LPM35
+#define RESET_LPM45   RSTCTL_PCMRESET_CLR_LPM45
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Initiates a soft system reset.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateSoftReset(void);
+
+//*****************************************************************************
+//
+//! Initiates a soft system reset with a particular source given. This source
+//! is generic and can be assigned by the user.
+//!
+//! \param source Source of the reset. Valid values are:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateSoftResetWithSource(uint32_t source);
+
+//*****************************************************************************
+//
+//! Retrieves previous soft reset sources
+//!
+//! \return the bitwise or of previous reset sources. These sources must be
+//! cleared using the \link ResetCtl_clearSoftResetSource \endlink function to
+//! be cleared.
+//! Possible values include:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getSoftResetSource(void);
+
+//*****************************************************************************
+//
+//! Clears the reset sources associated with at soft reset
+//!
+//! \param mask - Bitwise OR of any of the following values:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearSoftResetSource(uint32_t mask);
+
+//*****************************************************************************
+//
+//! Initiates a hard system reset.
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateHardReset(void);
+
+//*****************************************************************************
+//
+//! Initiates a hard system reset with a particular source given. This source
+//! is generic and can be assigned by the user.
+//!
+//! \param source - Valid values are one the following values:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_initiateHardResetWithSource(uint32_t source);
+
+//*****************************************************************************
+//
+//! Retrieves previous hard reset sources
+//!
+//! \return the bitwise or of previous reset sources. These sources must be
+//! cleared using the \link ResetCtl_clearHardResetSource \endlink function to
+//! be cleared.
+//! Possible values include:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getHardResetSource(void);
+
+//*****************************************************************************
+//
+//! Clears the reset sources associated with at hard reset
+//!
+//! \param mask - Bitwise OR of any of the following values:
+//!             - \b RESET_SRC_0,
+//!             - \b RESET_SRC_1,
+//!             - \b RESET_SRC_2,
+//!             - \b RESET_SRC_3,
+//!             - \b RESET_SRC_4,
+//!             - \b RESET_SRC_5,
+//!             - \b RESET_SRC_6,
+//!             - \b RESET_SRC_7,
+//!             - \b RESET_SRC_8,
+//!             - \b RESET_SRC_9,
+//!             - \b RESET_SRC_10,
+//!             - \b RESET_SRC_11,
+//!             - \b RESET_SRC_12,
+//!             - \b RESET_SRC_13,
+//!             - \b RESET_SRC_14,
+//!             - \b RESET_SRC_15
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearHardResetSource(uint32_t mask);
+
+//*****************************************************************************
+//
+//! Indicates the last cause of a power-on reset (POR) due to PSS operation.
+//! Note that the bits returned from this function may be set in different
+//! combinations. When a cold power up occurs, the value of all the values ORed
+//! together could be returned as a cold power up causes these conditions.
+//!
+//! \return  Bitwise OR of any of the following values:
+//!                 - RESET_VCCDET,
+//!                 - RESET_SVSH_TRIP,
+//!                 - RESET_BGREF_BAD
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getPSSSource(void);
+
+//*****************************************************************************
+//
+//! Clears the  PSS reset source flags
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearPSSFlags(void);
+
+//*****************************************************************************
+//
+//! Indicates the last cause of a power-on reset (POR) due to PCM operation.
+//!
+//! \return  Bitwise OR of any of the following values:
+//!                 - RESET_LPM35,
+//!                 - RESET_LPM45
+//
+//*****************************************************************************
+extern uint32_t ResetCtl_getPCMSource(void);
+
+//*****************************************************************************
+//
+//! Clears the corresponding PCM reset source flags
+//!
+//! \return none
+//
+//*****************************************************************************
+extern void ResetCtl_clearPCMFlags(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __RESET_H__

platform/vendor_bsp/TI/MSP432P4xx/rtc_c.c

@@ -0,0 +1,338 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <rtc_c.h>
+#include <interrupt.h>
+#include <debug.h>
+
+
+void RTC_C_startClock(void)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+    BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 0;
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+void RTC_C_holdClock(void)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+    BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+    RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_CALF_3)) | frequencySelect;
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
+        uint_fast8_t offsetValue)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+    RTC_C->OCAL = offsetValue + offsetDirection;
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
+        uint_fast8_t offsetValue)
+{
+    while (!BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCRDY_OFS))
+        ;
+
+    RTC_C->TCMP = offsetValue + offsetDirection;
+
+    if (BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCOK_OFS))
+        return true;
+    else
+        return false;
+}
+
+void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
+        uint_fast16_t formatSelect)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+
+    BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
+
+    if (formatSelect)
+        BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 1;
+    else
+        BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 0;
+
+    RTC_C->TIM0 = (calendarTime->minutes<<RTC_C_TIM0_MIN_OFS) | calendarTime->seconds;
+    RTC_C->TIM1 = (calendarTime->dayOfWeek<<RTC_C_TIM1_DOW_OFS) | calendarTime->hours;
+    RTC_C->DATE = (calendarTime->month<<RTC_C_DATE_MON_OFS) | calendarTime->dayOfmonth;
+    RTC_C->YEAR = calendarTime->year;
+
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+RTC_C_Calendar RTC_C_getCalendarTime(void)
+{
+    RTC_C_Calendar tempCal;
+
+    while (!(BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_RDY_OFS)))
+        ;
+
+    tempCal.seconds = RTC_C->TIM0 & RTC_C_TIM0_SEC_MASK;
+    tempCal.minutes = (RTC_C->TIM0 & RTC_C_TIM0_MIN_MASK)>>RTC_C_TIM0_MIN_OFS;
+    tempCal.hours   = RTC_C->TIM1 & RTC_C_TIM1_HOUR_MASK;
+    tempCal.dayOfWeek   = (RTC_C->TIM1 & RTC_C_TIM1_DOW_MASK)>>RTC_C_TIM1_DOW_OFS;
+    tempCal.dayOfmonth = RTC_C->DATE & RTC_C_DATE_DAY_MASK;
+    tempCal.month = (RTC_C->DATE & RTC_C_DATE_MON_MASK)>>RTC_C_DATE_MON_OFS;
+    tempCal.year = RTC_C->YEAR;
+
+    return (tempCal);
+}
+
+void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm,
+        uint_fast8_t dayOfWeekAlarm, uint_fast8_t dayOfmonthAlarm)
+{
+    //Each of these is XORed with 0x80 to turn on if an integer is passed,
+    //or turn OFF if RTC_ALARM_OFF (0x80) is passed.
+    RTC_C->AMINHR = ((hoursAlarm ^ 0x80) << 8 )| (minutesAlarm ^ 0x80);
+    RTC_C->ADOWDAY = ((dayOfmonthAlarm ^ 0x80) << 8 )| (dayOfWeekAlarm ^ 0x80);
+}
+
+void RTC_C_setCalendarEvent(uint_fast16_t eventSelect)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+    RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_TEV_3)) | eventSelect;
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleEventDivider)
+{
+    HWREG8(&RTC_C->PS0CTL + prescaleSelect) &= ~(RTC_C_PS0CTL_RT0IP_7);
+    HWREG8(&RTC_C->PS0CTL + prescaleSelect) |=
+            prescaleEventDivider;
+}
+
+uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect)
+{
+    if (RTC_C_PRESCALE_0 == prescaleSelect)
+    {
+        return (RTC_C->PS & RTC_C_PS_RT0PS_MASK);
+    } else if (RTC_C_PRESCALE_1 == prescaleSelect)
+    {
+        return (RTC_C->PS & RTC_C_PS_RT1PS_MASK)>>RTC_C_PS_RT1PS_OFS;
+    } else
+    {
+        return (0);
+    }
+}
+
+void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleCounterValue)
+{
+    RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
+
+    if (RTC_C_PRESCALE_0 == prescaleSelect)
+    {
+        RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT0PS_MASK) | prescaleCounterValue;
+    } else if (RTC_C_PRESCALE_1 == prescaleSelect)
+    {
+        RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT1PS_MASK)
+                | (prescaleCounterValue << RTC_C_PS_RT1PS_OFS);
+    }
+
+    BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+}
+
+uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert)
+{
+    RTC_C->BCD2BIN = valueToConvert;
+    return (RTC_C->BCD2BIN);
+}
+
+uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert)
+{
+    RTC_C->BIN2BCD = valueToConvert;
+    return (RTC_C->BIN2BCD);
+}
+
+void RTC_C_enableInterrupt(uint8_t interruptMask)
+{
+    if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+            + RTC_C_CTL0_RDYIE))
+    {
+        RTC_C->CTL0 = RTC_C_KEY | (interruptMask
+                & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+                + RTC_C_CTL0_RDYIE));
+        BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 1;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->PS1CTL,RTC_C_PS1CTL_RT1PSIE_OFS) = 1;
+    }
+}
+
+void RTC_C_disableInterrupt(uint8_t interruptMask)
+{
+    if (interruptMask & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+            + RTC_C_CTL0_RDYIE))
+    {
+        RTC_C->CTL0 = RTC_C_KEY
+                | (RTC_C->CTL0 & ~((interruptMask | RTC_C_CTL0_KEY_MASK)
+                & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE
+                + RTC_C_CTL0_RDYIE)));
+        BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 0;
+    }
+
+    if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS) = 0;
+    }
+}
+
+uint_fast8_t RTC_C_getInterruptStatus(void)
+{
+    uint_fast8_t tempInterruptFlagMask = 0x00;
+    uint_fast8_t interruptFlagMask = RTC_C_TIME_EVENT_INTERRUPT
+            | RTC_C_CLOCK_ALARM_INTERRUPT | RTC_C_CLOCK_READ_READY_INTERRUPT
+            | RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT
+            | RTC_C_OSCILLATOR_FAULT_INTERRUPT;
+
+    tempInterruptFlagMask |= (RTC_C->CTL0 & (interruptFlagMask >> 4));
+
+    tempInterruptFlagMask = tempInterruptFlagMask << 4;
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        if (BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS))
+        {
+            tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT;
+        }
+    }
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        if (BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS))
+        {
+            tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT;
+        }
+    }
+
+    return (tempInterruptFlagMask);
+}
+
+uint_fast8_t RTC_C_getEnabledInterruptStatus(void)
+{
+
+    uint32_t intStatus = RTC_C_getInterruptStatus();
+
+    if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_OFIE_OFS))
+    {
+        intStatus &= ~RTC_C_OSCILLATOR_FAULT_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_TEVIE_OFS))
+    {
+        intStatus &= ~RTC_C_TIME_EVENT_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_AIE_OFS))
+    {
+        intStatus &= ~RTC_C_CLOCK_ALARM_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_RDYIE_OFS))
+    {
+        intStatus &= ~RTC_C_CLOCK_READ_READY_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS))
+    {
+        intStatus &= ~RTC_C_PRESCALE_TIMER0_INTERRUPT;
+    }
+
+    if (!BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS))
+    {
+        intStatus &= ~RTC_C_PRESCALE_TIMER1_INTERRUPT;
+    }
+
+    return intStatus;
+}
+
+void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask)
+{
+    if (interruptFlagMask
+            & (RTC_C_TIME_EVENT_INTERRUPT + RTC_C_CLOCK_ALARM_INTERRUPT
+                    + RTC_C_CLOCK_READ_READY_INTERRUPT
+                    + RTC_C_OSCILLATOR_FAULT_INTERRUPT))
+    {
+        RTC_C->CTL0 = RTC_C_KEY
+                | (RTC_C->CTL0 & ~((interruptFlagMask >> 4) | RTC_C_CTL0_KEY_MASK));
+        BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
+    }
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS) = 0;
+    }
+
+    if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT)
+    {
+        BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS) = 0;
+    }
+}
+
+void RTC_C_registerInterrupt(void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(INT_RTC_C, intHandler);
+    Interrupt_enableInterrupt(INT_RTC_C);
+}
+
+void RTC_C_unregisterInterrupt(void)
+{
+    Interrupt_disableInterrupt(INT_RTC_C);
+    Interrupt_unregisterInterrupt(INT_RTC_C);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/rtc_c.h

@@ -0,0 +1,661 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef RTC_C_H_
+#define RTC_C_H_
+
+//*****************************************************************************
+//
+//! \addtogroup rtc_api
+//! @{
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+//The following is a struct that can be passed to RTC_CalendarInit() in the
+//CalendarTime parameter, as well as returned by RTC_getCalendarTime()
+//
+//*****************************************************************************
+typedef struct _RTC_C_Calendar
+{
+    uint_fast8_t seconds;
+    uint_fast8_t minutes;
+    uint_fast8_t hours;
+    uint_fast8_t dayOfWeek;
+    uint_fast8_t dayOfmonth;
+    uint_fast8_t month;
+    uint_fast16_t year;
+} RTC_C_Calendar;
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_setCalibrationData()
+//
+//*****************************************************************************
+#define RTC_C_CALIBRATIONFREQ_OFF   (RTC_C_CTL13_CALF_0)
+#define RTC_C_CALIBRATIONFREQ_512HZ (RTC_C_CTL13_CALF_1)
+#define RTC_C_CALIBRATIONFREQ_256HZ (RTC_C_CTL13_CALF_2)
+#define RTC_C_CALIBRATIONFREQ_1HZ   (RTC_C_CTL13_CALF_3)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_setCalibrationData()
+//
+//*****************************************************************************
+#define RTC_C_CALIBRATION_DOWN1PPM  ( !(RTC_C_OCAL_OCALS) )
+#define RTC_C_CALIBRATION_UP1PPM    (RTC_C_OCAL_OCALS)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to
+//RTC_setTemperatureCompensation()
+//
+//*****************************************************************************
+#define RTC_C_COMPENSATION_DOWN1PPM  ( !(RTC_C_TCMP_TCMPS) )
+#define RTC_C_COMPENSATION_UP1PPM    (RTC_C_TCMP_TCMPS)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_iniRTC_Calendar()
+//
+//*****************************************************************************
+#define RTC_C_FORMAT_BINARY  ( !(RTC_C_CTL13_BCD) )
+#define RTC_C_FORMAT_BCD     (RTC_C_CTL13_BCD)
+
+//*****************************************************************************
+//
+//The following is a value that can be passed to RTC_seRTC_CalendarAlarm()
+//
+//*****************************************************************************
+#define RTC_C_ALARMCONDITION_OFF  (0x80)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_seRTC_CalendarEvent()
+//in the eventSelect parameter.
+//
+//*****************************************************************************
+#define RTC_C_CALENDAREVENT_MINUTECHANGE  (RTC_C_CTL13_TEV_0)
+#define RTC_C_CALENDAREVENT_HOURCHANGE    (RTC_C_CTL13_TEV_1)
+#define RTC_C_CALENDAREVENT_NOON          (RTC_C_CTL13_TEV_2)
+#define RTC_C_CALENDAREVENT_MIDNIGHT      (RTC_C_CTL13_TEV_3)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_definePrescaleEvent()
+//
+//*****************************************************************************
+#define RTC_C_PRESCALE_0  (0x0)
+#define RTC_C_PRESCALE_1  (0x1)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to RTC_definePrescaleEvent()
+//in the prescaleEventDivider parameter.
+//
+//*****************************************************************************
+#define RTC_C_PSEVENTDIVIDER_2   (RTC_C_PS0CTL_RT0IP_0)
+#define RTC_C_PSEVENTDIVIDER_4   (RTC_C_PS0CTL_RT0IP_1)
+#define RTC_C_PSEVENTDIVIDER_8   (RTC_C_PS0CTL_RT0IP_2)
+#define RTC_C_PSEVENTDIVIDER_16  (RTC_C_PS0CTL_RT0IP_3)
+#define RTC_C_PSEVENTDIVIDER_32  (RTC_C_PS0CTL_RT0IP_4)
+#define RTC_C_PSEVENTDIVIDER_64  (RTC_C_PS0CTL_RT0IP_5)
+#define RTC_C_PSEVENTDIVIDER_128 (RTC_C_PS0CTL_RT0IP_6)
+#define RTC_C_PSEVENTDIVIDER_256 (RTC_C_PS0CTL_RT0IP_7)
+
+//*****************************************************************************
+//
+//The following are values that can be passed to the interrupt functions
+//
+//*****************************************************************************
+#define RTC_C_OSCILLATOR_FAULT_INTERRUPT  RTC_C_CTL0_OFIE
+#define RTC_C_TIME_EVENT_INTERRUPT        RTC_C_CTL0_TEVIE
+#define RTC_C_CLOCK_ALARM_INTERRUPT       RTC_C_CTL0_AIE
+#define RTC_C_CLOCK_READ_READY_INTERRUPT  RTC_C_CTL0_RDYIE
+#define RTC_C_PRESCALE_TIMER0_INTERRUPT   0x02
+#define RTC_C_PRESCALE_TIMER1_INTERRUPT   0x01
+
+//*****************************************************************************
+//
+//! Starts the RTC.
+//!
+//! This function clears the RTC main hold bit to allow the RTC to function.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_startClock(void);
+
+//*****************************************************************************
+//
+//! Holds the RTC.
+//!
+//! This function sets the RTC main hold bit to disable RTC functionality.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_holdClock(void);
+
+//*****************************************************************************
+//
+//! Allows and Sets the frequency output to RTCLK pin for calibration
+//! measurement.
+//!
+//! \param frequencySelect is the frequency output to RTCLK.
+//!        Valid values are
+//!        - \b   RTC_C_CALIBRATIONFREQ_OFF - turn off calibration
+//!                                                 output [Default]
+//!        - \b   RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz
+//!                                                     for calibration
+//!        - \b   RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz
+//!                                                     for calibration
+//!        - \b   RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz
+//!                                                     for calibration
+//!
+//! This function sets a frequency to measure at the RTCLK output pin. After
+//! testing the set frequency, the calibration could be set accordingly.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect);
+
+//*****************************************************************************
+//
+//! Sets the specified calibration for the RTC.
+//!
+//! \param offsetDirection is the direction that the calibration offset will
+//!        go. Valid values are
+//!        - \b   RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1
+//!        - \b   RTC_C_CALIBRATION_UP1PPM - calibrat at steps of +1
+//! \param offsetValue is the value that the offset will be a factor of; a
+//!       valid value is any integer from 1-240.
+//!
+//! This function sets the calibration offset to make the RTC as accurate as
+//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the
+//! offsetValue should be from 1-240 and is multiplied by the direction setting
+//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalibrationData(uint_fast8_t offsetDirection,
+        uint_fast8_t offsetValue);
+
+//*****************************************************************************
+//
+//! Sets the specified temperature compensation for the RTC.
+//!
+//! \param offsetDirection is the direction that the calibration offset will
+//!        go. Valid values are
+//!        - \b   RTC_C_COMPENSATION_DOWN1PPM - calibrate at steps of -1
+//!        - \b   RTC_C_COMPENSATION_UP1PPM - calibrate at steps of +1
+//! \param offsetValue is the value that the offset will be a factor of; a
+//!       value is any integer from 1-240.
+//!
+//! This function sets the calibration offset to make the RTC as accurate as
+//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the
+//! offsetValue should be from 1-240 and is multiplied by the direction setting
+//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm).
+//!
+//! \return true if calibration was set, false if it could not be set
+//!
+//
+//*****************************************************************************
+extern bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection,
+        uint_fast8_t offsetValue);
+
+//*****************************************************************************
+//
+//! Initializes the settings to operate the RTC in Calendar mode.
+//!
+//! \param calendarTime is the structure containing the values for the Calendar
+//!       to be initialized to.
+//!        Valid values should be of type Calendar and should contain the
+//!        following members and corresponding values:
+//!        - \b   seconds between 0-59
+//!        - \b   minutes between 0-59
+//!        - \b   hours between 0-24
+//!        - \b   dayOfWeek between 0-6
+//!        - \b   dayOfmonth between 0-31
+//!        - \b   year between 0-4095
+//!        \note Values beyond the ones specified may result in eradic behavior.
+//! \param formatSelect is the format for the Calendar registers to use.
+//!        Valid values are
+//!        - \b   RTC_FORMAT_BINARY [Default]
+//!        - \b   RTC_FORMAT_BCD
+//!
+//! This function initializes the Calendar mode of the RTC module.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime,
+        uint_fast16_t formatSelect);
+
+//*****************************************************************************
+//
+//! Returns the Calendar Time stored in the Calendar registers of the RTC.
+//!
+//!
+//! This function returns the current Calendar time in the form of a Calendar
+//! structure.
+//!
+//! \return A Calendar structure containing the current time.
+//
+//*****************************************************************************
+extern RTC_C_Calendar RTC_C_getCalendarTime(void);
+
+//*****************************************************************************
+//
+//! Sets and Enables the desired Calendar Alarm settings.
+//!
+//! \param minutesAlarm is the alarm condition for the minutes.
+//!        Valid values are
+//!        - An integer between 0-59, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//! \param hoursAlarm is the alarm condition for the hours.
+//!        Valid values are
+//!        - An integer between 0-24, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//! \param dayOfWeekAlarm is the alarm condition for the day of week.
+//!        Valid values are
+//!        - An integer between 0-6, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//! \param dayOfmonthAlarm is the alarm condition for the day of the month.
+//!        Valid values are
+//!        - An integer between 0-31, OR
+//!        - \b   RTC_C_ALARMCONDITION_OFF [Default]
+//!
+//! This function sets a Calendar interrupt condition to assert the RTCAIFG
+//! interrupt flag. The condition is a logical and of all of the parameters.
+//! For example if the minutes and hours alarm is set, then the interrupt will
+//! only assert when the minutes AND the hours change to the specified setting.
+//! Use the RTC_ALARM_OFF for any alarm settings that should not be apart of
+//! the alarm condition.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm,
+        uint_fast8_t hoursAlarm, uint_fast8_t dayOfWeekAlarm,
+        uint_fast8_t dayOfmonthAlarm);
+
+//*****************************************************************************
+//
+//! Sets a single specified Calendar interrupt condition.
+//!
+//! \param eventSelect is the condition selected.
+//!        Valid values are
+//!        - \b   RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every
+//!             minute
+//!        - \b   RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour
+//!        - \b   RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12
+//!        - \b   RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0
+//!
+//! This function sets a specified event to assert the RTCTEVIFG interrupt. This
+//! interrupt is independent from the Calendar alarm interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setCalendarEvent(uint_fast16_t eventSelect);
+
+//*****************************************************************************
+//
+//! Sets up an interrupt condition for the selected Prescaler.
+//!
+//! \param prescaleSelect is the prescaler to define an interrupt for.
+//!        Valid values are
+//!        - \b   RTC_C_PRESCALE_0
+//!        - \b   RTC_C_PRESCALE_1
+//! \param prescaleEventDivider is a divider to specify when an interrupt can
+//!       occur based on the clock source of the selected prescaler.
+//!       (Does not affect timer of the selected prescaler).
+//!       Valid values are
+//!       - \b   RTC_C_PSEVENTDIVIDER_2 [Default]
+//!       - \b   RTC_C_PSEVENTDIVIDER_4
+//!       - \b   RTC_C_PSEVENTDIVIDER_8
+//!       - \b   RTC_C_PSEVENTDIVIDER_16
+//!       - \b   RTC_C_PSEVENTDIVIDER_32
+//!       - \b   RTC_C_PSEVENTDIVIDER_64
+//!       - \b   RTC_C_PSEVENTDIVIDER_128
+//!       - \b   RTC_C_PSEVENTDIVIDER_256
+//!
+//! This function sets the condition for an interrupt to assert based on the
+//! individual prescalers.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleEventDivider);
+
+//*****************************************************************************
+//
+//! Returns the selected Prescaler value.
+//!
+//! \param prescaleSelect is the prescaler to obtain the value of.
+//!        Valid values are
+//!        - \b   RTC_C_PRESCALE_0
+//!        - \b   RTC_C_PRESCALE_1
+//!
+//! This function returns the value of the selected prescale counter register.
+//! The counter should be held before reading. If in counter mode, the
+//! individual prescaler can be held, while in Calendar mode the whole RTC must
+//! be held.
+//!
+//! \return The value of the specified Prescaler count register
+//
+//*****************************************************************************
+extern uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect);
+
+//*****************************************************************************
+//
+//! Sets the selected Prescaler value.
+//!
+//! \param prescaleSelect is the prescaler to set the value for.
+//!        Valid values are
+//!        - \b   RTC_C_PRESCALE_0
+//!        - \b   RTC_C_PRESCALE_1
+//! \param prescaleCounterValue is the specified value to set the prescaler to;
+//!       a valid value is any integer from 0-255.
+//!
+//! This function sets the prescale counter value. Before setting the prescale
+//! counter, it should be held.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect,
+        uint_fast8_t prescaleCounterValue);
+
+//*****************************************************************************
+//
+//! Returns the given BCD value in Binary Format
+//!
+//! \param valueToConvert is the raw value in BCD format to convert to
+//!        Binary.
+//!
+//! This function converts BCD values to Binary format.
+//!
+//! \return The Binary version of the valueToConvert parameter.
+//
+//*****************************************************************************
+extern uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert);
+
+//*****************************************************************************
+//
+//! Returns the given Binary value in BCD Format
+//!
+
+//! \param valueToConvert is the raw value in Binary format to convert to
+//!        BCD.
+//!
+//! This function converts Binary values to BCD format.
+//!
+//! \return The BCD version of the valueToConvert parameter.
+//
+//*****************************************************************************
+extern uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert);
+
+//*****************************************************************************
+//
+//! Enables selected RTC interrupt sources.
+//!
+//! \param interruptMask is a bit mask of the interrupts to enable.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is
+//!             a problem with the 32kHz oscillator, while the RTC is running.
+//!
+//! This function enables the selected RTC interrupt source.  Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_enableInterrupt(uint8_t interruptMask);
+
+//*****************************************************************************
+//
+//! Disables selected RTC interrupt sources.
+//!
+//! \param interruptMask is a bit mask of the interrupts to disable.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a
+//!             problem with the 32kHz oscillator, while the RTC is running.
+//!
+//! This function disables the selected RTC interrupt source.  Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_disableInterrupt(uint8_t interruptMask);
+
+//*****************************************************************************
+//
+//! Returns the status of the interrupts flags.
+//!
+//! \return A bit mask of the selected interrupt flag's status.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a
+//!             problem with the 32kHz oscillator, while the RTC is running.
+//
+//*****************************************************************************
+extern uint_fast8_t RTC_C_getInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Returns the status of the interrupts flags masked with the enabled
+//! interrupts.  This function is useful to call in ISRs to get a
+//! list of pending interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \return A bit mask of the selected interrupt flag's status.
+//!        Mask Value is the logical OR of any of the following
+//!        - \b  RTC_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a problem
+//!             with the 32kHz oscillator, while the RTC is running.
+//
+//*****************************************************************************
+extern uint_fast8_t RTC_C_getEnabledInterruptStatus(void);
+
+//*****************************************************************************
+//
+//! Clears selected RTC interrupt flags.
+//!
+//! \param interruptFlagMask is a bit mask of the interrupt flags to be
+//!        cleared. Mask Value is the logical OR of any of the following
+//!        - \b  RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in
+//!             counter mode or when Calendar event condition defined by
+//!             defineCalendarEvent() is met.
+//!        - \b  RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in
+//!             Calendar mode is met.
+//!        - \b  RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar
+//!             registers are settled.
+//!        - \b  RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0
+//!             event condition is met.
+//!        - \b  RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1
+//!             event condition is met.
+//!        - \b  RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is
+//!             a problem with the 32kHz oscillator, while the RTC is running.
+//!
+//! This function clears the RTC interrupt flag is cleared, so that it no longer
+//! asserts.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the RTC interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! RTC interrupt occurs.
+//!
+//! This function registers the handler to be called when a RTC
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific AES interrupts must be enabled
+//! via RTC_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via RTC_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void RTC_C_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the RTC interrupt
+//!
+//! This function unregisters the handler to be called when RTC
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void RTC_C_unregisterInterrupt(void);
+
+/* Defines for future devices that might have multiple instances */
+#define RTC_C_startClockMultipleInstance(a) RTC_C_startClock()
+#define RTC_C_holdClockMultipleInstance(a) RTC_C_holdClock()
+#define RTC_C_setCalibrationFrequencyMultipleInstance(a,b) RTC_C_setCalibrationFrequency(b)
+#define RTC_C_setCalibrationDataMultipleInstance(a,b,c) RTC_C_setCalibrationData(b,c)
+#define RTC_C_setTemperatureCompensationMultipleInstance(a,b,c) RTC_C_setTemperatureCompensation(b,c)
+#define RTC_C_initCalendarMultipleInstance(a,b,c) RTC_C_initCalendar(b,c)
+#define RTC_C_getCalendarTimeMultipleInstance(a) RTC_C_getCalendarTime()
+#define RTC_C_setCalendarAlarmMultipleInstance(a,b,c,d,e) RTC_C_setCalendarAlarm(b,c,d,e)
+#define RTC_C_setCalendarEventMultipleInstance(a,b) RTC_C_setCalendarEvent(b)
+#define RTC_C_definePrescaleEventMultipleInstance(a,b,c) RTC_C_definePrescaleEvent(b,c)
+#define RTC_C_getPrescaleValueMultipleInstance(a,b) RTC_C_getPrescaleValue(b)
+#define RTC_C_setPrescaleValueMultipleInstance(a,b,c) RTC_C_setPrescaleValue(b,c)
+#define RTC_C_convertBCDToBinaryMultipleInstance(a,b) RTC_C_convertBCDToBinary(b)
+#define RTC_C_convertBinaryToBCDMultipleInstance(a,b) RTC_C_convertBinaryToBCD(b)
+#define RTC_C_enableInterruptMultipleInstance(a,b) RTC_C_enableInterrupt(b)
+#define RTC_C_disableInterruptMultipleInstance(a,b) RTC_C_disableInterrupt(b)
+#define RTC_C_getInterruptStatusMultipleInstance(a) RTC_C_getInterruptStatus()
+#define RTC_C_getEnabledInterruptStatusMultipleInstance(a) RTC_C_getEnabledInterruptStatus()
+#define RTC_C_clearInterruptFlagMultipleInstance(a,b) RTC_C_clearInterruptFlag(b)
+#define RTC_C_registerInterruptMultipleInstance(a,b) RTC_C_registerInterrupt(b)
+#define RTC_C_unregisterInterruptMultipleInstance(a) RTC_C_unregisterInterrupt()
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* RTC_H */

platform/vendor_bsp/TI/MSP432P4xx/spi.h

@@ -0,0 +1,822 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef SPI_H_
+#define SPI_H_
+
+//*****************************************************************************
+//
+//! \addtogroup spi_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <msp.h>
+#include "eusci.h"
+
+/* Configuration Defines */
+#define EUSCI_SPI_CLOCKSOURCE_ACLK    EUSCI_B_CTLW0_SSEL__ACLK
+#define EUSCI_SPI_CLOCKSOURCE_SMCLK   EUSCI_B_CTLW0_SSEL__SMCLK
+
+#define EUSCI_SPI_MSB_FIRST    EUSCI_B_CTLW0_MSB
+#define EUSCI_SPI_LSB_FIRST    0x00
+
+#define EUSCI_SPI_BUSY        EUSCI_A_STATW_BUSY
+#define EUSCI_SPI_NOT_BUSY    0x00
+
+#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT    0x00
+#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT    EUSCI_B_CTLW0_CKPH
+
+#define EUSCI_SPI_3PIN                      EUSCI_B_CTLW0_MODE_0
+#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH   EUSCI_B_CTLW0_MODE_1
+#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW    EUSCI_B_CTLW0_MODE_2
+
+#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH    EUSCI_B_CTLW0_CKPL
+#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW     0x00
+
+#define EUSCI_SPI_TRANSMIT_INTERRUPT    EUSCI_B_IE_TXIE_OFS
+#define EUSCI_SPI_RECEIVE_INTERRUPT     EUSCI_B_IE_RXIE_OFS
+
+#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE           EUSCI_B_CTLW0_STEM
+#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS    0x00
+
+//*****************************************************************************
+//
+//!     ypedef eUSCI_SPI_MasterConfig
+//! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure
+//!
+//! \struct _eUSCI_SPI_MasterConfig
+//! \brief Configuration structure for master mode in the \b SPI module. See
+//!          \link SPI_initMaster \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct _eUSCI_SPI_MasterConfig
+{
+    uint_fast8_t selectClockSource;
+    uint32_t clockSourceFrequency;
+    uint32_t desiredSpiClock;
+    uint_fast16_t msbFirst;
+    uint_fast16_t clockPhase;
+    uint_fast16_t clockPolarity;
+    uint_fast16_t spiMode;
+} eUSCI_SPI_MasterConfig;
+
+//*****************************************************************************
+//
+//!     ypedef eUSCI_SPI_SlaveConfig
+//! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure
+//!
+//! \struct _eUSCI_SPI_SlaveConfig
+//! \brief Configuration structure for slave mode in the \b SPI module. See
+//!          \link SPI_initSlave \endlink for parameter documentation.
+//
+//*****************************************************************************
+typedef struct _eUSCI_SPI_SlaveConfig
+{
+    uint_fast16_t msbFirst;
+    uint_fast16_t clockPhase;
+    uint_fast16_t clockPolarity;
+    uint_fast16_t spiMode;
+} eUSCI_SPI_SlaveConfig;
+
+//*****************************************************************************
+//
+//! Initializes the SPI Master block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//! \param config Configuration structure for SPI master mode
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_SPI_MasterConfig \endlink structure.</b>
+//! <hr>
+//!
+//! \param selectClockSource selects clock source. Valid values are
+//!         - \b  EUSCI_SPI_CLOCKSOURCE_ACLK
+//!         - \b  EUSCI_SPI_CLOCKSOURCE_SMCLK
+//! \param clockSourceFrequency is the frequency of the selected clock source
+//! \param desiredSpiClock is the desired clock rate for SPI communication
+//! \param msbFirst controls the direction of the receive and transmit shift
+//!      register. Valid values are
+//!         - \b  EUSCI_SPI_MSB_FIRST
+//!         - \b  EUSCI_SPI_LSB_FIRST [Default Value]
+//! \param clockPhase is clock phase select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!                                                          [Default Value]
+//!         - \b  EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW  [Default Value]
+//! \param spiMode is SPI mode select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_3PIN [Default Value]
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW
+//! Upon successful initialization of the SPI master block, this function
+//! will have set the bus speed for the master, but the SPI Master block
+//! still remains disabled and must be enabled with SPI_enableModule()
+//!
+//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB,\b UCSSELx,
+//! \b UCSWRST bits of \b UCAxCTLW0 register
+//!
+//! \return true
+//
+//*****************************************************************************
+extern bool SPI_initMaster(uint32_t moduleInstance,
+        const eUSCI_SPI_MasterConfig *config);
+
+//*****************************************************************************
+//
+//! Selects 4Pin Functionality
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param select4PinFunctionality selects Clock source. Valid values are
+//!         - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
+//!         - \b EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
+//! This function should be invoked only in 4-wire mode. Invoking this function
+//! has no effect in 3-wire mode.
+//!
+//! Modified bits are \b UCSTEM bit of \b UCAxCTLW0 register
+//!
+//! \return true
+//
+//*****************************************************************************
+extern void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
+        uint_fast8_t select4PinFunctionality);
+
+//*****************************************************************************
+//
+//! Initializes the SPI Master clock.At the end of this function call, SPI
+//! module is left enabled.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param clockSourceFrequency is the frequency of the selected clock source
+//! \param desiredSpiClock is the desired clock rate for SPI communication.
+//!
+//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register and
+//! \b UCAxBRW register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SPI_changeMasterClock(uint32_t moduleInstance,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
+
+//*****************************************************************************
+//
+//! Initializes the SPI Slave block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//! \param config Configuration structure for SPI slave mode
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_SPI_SlaveConfig \endlink structure.</b>
+//! <hr>
+//!
+//! \param msbFirst controls the direction of the receive and transmit shift
+//!      register. Valid values are
+//!         - \b  EUSCI_SPI_MSB_FIRST
+//!         - \b  EUSCI_SPI_LSB_FIRST [Default Value]
+//! \param clockPhase is clock phase select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!                                                          [Default Value]
+//!         - \b  EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!         - \b  EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value]
+//! \param spiMode is SPI mode select.
+//!         Valid values are
+//!         - \b  EUSCI_SPI_3PIN [Default Value]
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH
+//!         - \b  EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW
+//! Upon successful initialization of the SPI slave block, this function
+//! will have initialized the slave block, but the SPI Slave block
+//! still remains disabled and must be enabled with SPI_enableModule()
+//!
+//! Modified bits are \b UCMSB, \b UC7BIT, \b UCMST, \b UCCKPL, \b UCCKPH,
+//! \b UCMODE, \b UCSWRST bits of \b UCAxCTLW0
+//!
+//! \return true
+//*****************************************************************************
+extern bool SPI_initSlave(uint32_t moduleInstance,
+        const eUSCI_SPI_SlaveConfig *config);
+
+//*****************************************************************************
+//
+//! Changes the SPI clock phase and polarity.At the end of this function call,
+//! SPI module is left enabled.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param clockPhase is clock phase select.
+//!         Valid values are:
+//!             - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
+//!                                                          [Default Value]
+//!             - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
+//! \param clockPolarity is clock polarity select.
+//!         Valid values are:
+//!             - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
+//!             - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW  [Default Value]
+//!
+//! Modified bits are \b UCSWRST, \b UCCKPH, \b UCCKPL, \b UCSWRST bits of
+//! \b UCAxCTLW0
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
+        uint_fast16_t clockPhase, uint_fast16_t clockPolarity);
+
+//*****************************************************************************
+//
+//! Transmits a byte from the SPI Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param transmitData data to be transmitted from the SPI module
+//!
+//! This function will place the supplied data into SPI transmit data register
+//! to start transmission
+//!
+//! Modified register is \b UCAxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_transmitData(uint32_t moduleInstance,
+        uint_fast8_t transmitData);
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the SPI Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//!
+//! This function reads a byte of data from the SPI receive data Register.
+//!
+//! \return Returns the byte received from by the SPI module, cast as an
+//! uint8_t.
+//
+//*****************************************************************************
+extern uint8_t SPI_receiveData(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables the SPI block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//!
+//! This will enable operation of the SPI block.
+//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_enableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Disables the SPI block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//!
+//! This will disable operation of the SPI block.
+//!
+//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_disableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the RX Buffer of the SPI for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//!
+//! Returns the address of the SPI RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the TX Buffer of the SPI for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//!
+//! Returns the address of the SPI TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return NONE
+//
+//*****************************************************************************
+extern uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Indicates whether or not the SPI bus is busy.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//!
+//! This function returns an indication of whether or not the SPI bus is
+//! busy.This function checks the status of the bus via UCBBUSY bit
+//!
+//! \return EUSCI_SPI_BUSY if the SPI module transmitting or receiving
+//! is busy; otherwise, returns EUSCI_SPI_NOT_BUSY.
+//
+//*****************************************************************************
+extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables individual SPI interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated SPI interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//!       - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt
+//!       - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt
+//!
+//! Modified registers are \b UCAxIFG and \b UCAxIE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Disables individual SPI interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param mask is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! Disables the indicated SPI interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//!       - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt
+//!       - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt
+//!
+//! Modified register is \b UCAxIE
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current SPI interrupt status.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//! \param mask Mask of interrupt to filter. This can include:
+//!          - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//!          - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//!
+//! Modified registers are \b UCAxIFG.
+//!
+//! \return The current interrupt status as the mask of the set flags
+//! Mask parameter can be either any of the following selection:
+//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//
+//*****************************************************************************
+extern uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance,
+        uint16_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current SPI interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! Modified registers are \b UCAxIFG.
+//!
+//! \return The current interrupt status as the mask of the set flags
+//! Mask parameter can be either any of the following selection:
+//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//
+//*****************************************************************************
+extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Clears the selected SPI interrupt status flag.
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! \param mask is the masked interrupt flag to be cleared.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt
+//! Modified registers are \b UCAxIFG.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer capture compare interrupt.
+//!
+//! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!  It is important to note that for eUSCI modules, only "B" modules such as
+//!  EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the
+//!  I2C mode.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! timer capture compare interrupt occurs.
+//!
+//! This function registers the handler to be called when a timer
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific SPI interrupts must be enabled
+//! via SPI_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via SPI_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the timer
+//!
+//! \param moduleInstance is the instance of the eUSCI A/B module. Valid
+//! parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!         - \b EUSCI_B0_BASE
+//!         - \b EUSCI_B1_BASE
+//!         - \b EUSCI_B2_BASE
+//!         - \b EUSCI_B3_BASE
+//!
+//! This function unregisters the handler to be called when timer
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SPI_unregisterInterrupt(uint32_t moduleInstance);
+
+/* Backwards Compatibility Layer */
+#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT            0x00
+#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT          UCCKPH
+
+#define EUSCI_B_SPI_MSB_FIRST                                             UCMSB
+#define EUSCI_B_SPI_LSB_FIRST                                              0x00
+
+#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH                        UCCKPL
+#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW                           0x00
+
+#define EUSCI_B_SPI_CLOCKSOURCE_ACLK                               UCSSEL__ACLK
+#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK                             UCSSEL__SMCLK
+
+#define EUSCI_B_SPI_3PIN                                               UCMODE_0
+#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH                            UCMODE_1
+#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW                             UCMODE_2
+
+#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS                   0x00
+#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE                        UCSTEM
+
+#define EUSCI_B_SPI_TRANSMIT_INTERRUPT                                   UCTXIE
+#define EUSCI_B_SPI_RECEIVE_INTERRUPT                                    UCRXIE
+
+#define EUSCI_B_SPI_BUSY                                                 UCBUSY
+#define EUSCI_B_SPI_NOT_BUSY                                               0x00
+
+#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT            0x00
+#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT          UCCKPH
+
+#define EUSCI_A_SPI_MSB_FIRST                                             UCMSB
+#define EUSCI_A_SPI_LSB_FIRST                                              0x00
+
+#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH                        UCCKPL
+#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW                           0x00
+
+#define EUSCI_A_SPI_CLOCKSOURCE_ACLK                               UCSSEL__ACLK
+#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK                             UCSSEL__SMCLK
+
+#define EUSCI_A_SPI_3PIN                                               UCMODE_0
+#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH                            UCMODE_1
+#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW                             UCMODE_2
+
+#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS                   0x00
+#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE                        UCSTEM
+
+#define EUSCI_A_SPI_TRANSMIT_INTERRUPT                                   UCTXIE
+#define EUSCI_A_SPI_RECEIVE_INTERRUPT                                    UCRXIE
+
+#define EUSCI_A_SPI_BUSY                                                 UCBUSY
+#define EUSCI_A_SPI_NOT_BUSY                                               0x00
+
+extern void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
+        uint8_t select4PinFunctionality);
+extern void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
+extern bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
+        uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode);
+extern void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
+        uint16_t clockPhase, uint16_t clockPolarity);
+extern void EUSCI_A_SPI_transmitData(uint32_t baseAddress,
+        uint8_t transmitData);
+extern uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress);
+extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress,
+        uint8_t mask);
+extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_A_SPI_enable(uint32_t baseAddress);
+extern void EUSCI_A_SPI_disable(uint32_t baseAddress);
+extern uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
+extern uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(
+        uint32_t baseAddress);
+extern bool EUSCI_A_SPI_isBusy(uint32_t baseAddress);
+extern void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
+        uint8_t select4PinFunctionality);
+extern void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
+        uint32_t clockSourceFrequency, uint32_t desiredSpiClock);
+extern bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
+        uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode);
+extern void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
+        uint16_t clockPhase, uint16_t clockPolarity);
+extern void EUSCI_B_SPI_transmitData(uint32_t baseAddress,
+        uint8_t transmitData);
+extern uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress);
+extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask);
+extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress,
+        uint8_t mask);
+extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask);
+extern void EUSCI_B_SPI_enable(uint32_t baseAddress);
+extern void EUSCI_B_SPI_disable(uint32_t baseAddress);
+extern uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress);
+extern uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(
+        uint32_t baseAddress);
+extern bool EUSCI_B_SPI_isBusy(uint32_t baseAddress);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* SPI_H_ */
+

platform/vendor_bsp/TI/MSP432P4xx/sysctl.c

@@ -0,0 +1,280 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* DriverLib Includes */
+#include <sysctl.h>
+#include <debug.h>
+
+#ifdef DEBUG
+
+static bool SysCtlSRAMBankValid(uint8_t sramBank)
+{
+    return(
+            sramBank == SYSCTL_SRAM_BANK7 ||
+            sramBank == SYSCTL_SRAM_BANK6 ||
+            sramBank == SYSCTL_SRAM_BANK5 ||
+            sramBank == SYSCTL_SRAM_BANK4 ||
+            sramBank == SYSCTL_SRAM_BANK3 ||
+            sramBank == SYSCTL_SRAM_BANK2 ||
+            sramBank == SYSCTL_SRAM_BANK1
+    );
+}
+
+static bool SysCtlSRAMBankValidRet(uint8_t sramBank)
+{
+    sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 &
+            SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 &
+            SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 &
+            SYSCTL_SRAM_BANK1);
+
+    return (sramBank == 0);
+}
+
+static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral)
+{
+    hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT &
+            SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 &
+            SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 &
+            SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 &
+            SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 &
+            SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE &
+            SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 &
+            SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 &
+            SYSCTL_PERIPH_TIMER16_0);
+
+    return (hwPeripheral == 0);
+}
+#endif
+
+void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
+        uint_fast8_t *length, uint32_t **data_address)
+{
+    /* TLV Structure Start Address */
+    uint32_t *TLV_address = (uint32_t *) TLV_START;
+
+    while (((*TLV_address != tag)) // check for tag and instance
+            && (*TLV_address != TLV_TAGEND))         // do range check first
+    {
+        if (*TLV_address == tag)
+        {
+            if(instance == 0)
+            {
+                break;
+            }
+
+            /* Repeat until requested instance is reached */
+            instance--;
+        }
+
+        TLV_address += (*(TLV_address + 1)) + 2;
+    }
+
+    /* Check if Tag match happened... */
+    if (*TLV_address == tag)
+    {
+        /* Return length = Address + 1 */
+        *length = (*(TLV_address + 1))*4;
+        /* Return address of first data/value info = Address + 2 */
+        *data_address = (uint32_t *) (TLV_address + 2);
+    }
+    // If there was no tag match and the end of TLV structure was reached..
+    else
+    {
+        // Return 0 for TAG not found
+        *length = 0;
+        // Return 0 for TAG not found
+        *data_address = 0;
+    }
+}
+
+uint_least32_t SysCtl_getSRAMSize(void)
+{
+    return SYSCTL->SRAM_SIZE;
+}
+
+uint_least32_t SysCtl_getFlashSize(void)
+{
+    return SYSCTL->FLASH_SIZE;
+}
+
+void SysCtl_disableNMISource(uint_fast8_t flags)
+{
+    SYSCTL->NMI_CTLSTAT &= ~(flags);
+}
+
+void SysCtl_enableNMISource(uint_fast8_t flags)
+{
+    SYSCTL->NMI_CTLSTAT |= flags;
+}
+
+uint_fast8_t SysCtl_getNMISourceStatus(void)
+{
+    return SYSCTL->NMI_CTLSTAT;
+}
+
+void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValid(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
+        ;
+
+    SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
+}
+
+void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValid(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY))
+       ;
+
+    switch (sramBank)
+    {
+    case SYSCTL_SRAM_BANK7:
+        sramBank = SYSCTL_SRAM_BANK6 +  SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+                        + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 
+                        + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK6:
+        sramBank =   SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4
+                        + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 
+                        + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK5:
+        sramBank =   SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3  
+                + SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK4:
+        sramBank =   SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 
+                        + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK3:
+        sramBank =   SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK2:
+        sramBank = SYSCTL_SRAM_BANK1;
+        break;
+    case SYSCTL_SRAM_BANK1:
+        sramBank = 0;
+        break;
+    default:
+        return;
+    }
+
+    SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN);
+}
+
+void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValidRet(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
+            ;
+
+    SYSCTL->SRAM_BANKRET |= sramBank;
+}
+
+void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
+{
+    ASSERT(SysCtlSRAMBankValidRet(sramBank));
+
+    /* Waiting for SRAM Ready Bit to be set */
+    while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY))
+            ;
+
+    SYSCTL->SRAM_BANKRET &= ~sramBank;
+}
+
+void SysCtl_rebootDevice(void)
+{
+    SYSCTL->REBOOT_CTL = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY);
+}
+
+void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
+{
+    ASSERT(SysCtlPeripheralIsValid(devices));
+    SYSCTL->PERIHALT_CTL &= ~devices;
+}
+
+void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
+{
+    ASSERT(SysCtlPeripheralIsValid(devices));
+    SYSCTL->PERIHALT_CTL |= devices;
+}
+
+void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
+{
+    if (resetType)
+        SYSCTL->WDTRESET_CTL |=
+                SYSCTL_WDTRESET_CTL_TIMEOUT;
+    else
+        SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_TIMEOUT;
+}
+
+void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
+{
+    ASSERT(resetType <= SYSCTL_HARD_RESET);
+
+    if (resetType)
+        SYSCTL->WDTRESET_CTL |=
+                SYSCTL_WDTRESET_CTL_VIOLATION;
+    else
+        SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_VIOLATION;
+}
+
+void SysCtl_enableGlitchFilter(void)
+{
+    SYSCTL->DIO_GLTFLT_CTL |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
+}
+
+void SysCtl_disableGlitchFilter(void)
+{
+    SYSCTL->DIO_GLTFLT_CTL &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN;
+}
+
+uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
+        uint32_t temperature)
+{
+    return HWREG16(TLV_BASE + refVoltage + temperature);
+}

platform/vendor_bsp/TI/MSP432P4xx/sysctl.h

@@ -0,0 +1,544 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables 
+//
+//*****************************************************************************
+#define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
+#define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
+#define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
+#define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
+#define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
+#define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
+#define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
+
+#define SYSCTL_HARD_RESET 1
+#define SYSCTL_SOFT_RESET 0
+
+#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
+#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
+#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
+#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
+#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
+#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
+#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
+#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
+#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
+#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
+#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
+#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
+#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
+#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
+#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
+#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
+
+#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
+#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
+#define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
+#define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
+
+#define SYSCTL_REBOOT_KEY   0x6900
+
+#define SYSCTL_1_2V_REF        (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
+#define SYSCTL_1_45V_REF       (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
+#define SYSCTL_2_5V_REF        (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
+
+#define SYSCTL_85_DEGREES_C    4
+#define SYSCTL_30_DEGREES_C    0
+
+
+#define TLV_START               0x00201004
+#define TLV_TAG_RESERVED1      1
+#define TLV_TAG_RESERVED2      2
+#define TLV_TAG_CS             3
+#define TLV_TAG_FLASHCTL       4
+#define TLV_TAG_ADC14          5
+#define TLV_TAG_RESERVED6      6
+#define TLV_TAG_RESERVED7      7
+#define TLV_TAG_REF            8
+#define TLV_TAG_RESERVED9      9
+#define TLV_TAG_RESERVED10     10
+#define TLV_TAG_DEVINFO        11
+#define TLV_TAG_DIEREC         12
+#define TLV_TAG_RANDNUM        13
+#define TLV_TAG_RESERVED14     14
+#define TLV_TAG_BSL            15
+#define TLV_TAGEND             0x0BD0E11D
+
+//*****************************************************************************
+//
+// Structures for TLV definitions
+// 
+//*****************************************************************************
+typedef struct
+{
+    uint32_t    maxProgramPulses;
+    uint32_t    maxErasePulses;
+} SysCtl_FlashTLV_Info;
+
+typedef struct
+{
+    uint32_t rDCOIR_FCAL_RSEL04;
+    uint32_t rDCOIR_FCAL_RSEL5;
+    uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
+    uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
+    uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
+    uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
+    uint32_t rDCOIR_CONSTK_RSEL04;
+    uint32_t rDCOIR_CONSTK_RSEL5;
+    uint32_t rDCOER_FCAL_RSEL04;
+    uint32_t rDCOER_FCAL_RSEL5;
+    uint32_t rDCOER_MAXPOSTUNE_RSEL04;
+    uint32_t rDCOER_MAXNEGTUNE_RSEL04;
+    uint32_t rDCOER_MAXPOSTUNE_RSEL5;
+    uint32_t rDCOER_MAXNEGTUNE_RSEL5;
+    uint32_t rDCOER_CONSTK_RSEL04;
+    uint32_t rDCOER_CONSTK_RSEL5;
+
+} SysCtl_CSCalTLV_Info;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_getSRAMSize(void);
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_getFlashSize(void);
+
+//*****************************************************************************
+//
+//! Reboots the device and causes the device to re-initialize itself.
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+extern void SysCtl_rebootDevice(void);
+
+//*****************************************************************************
+//
+//! The TLV structure uses a tag or base address to identify segments of the
+//! table where information is stored. Some examples of TLV tags are Peripheral
+//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
+//! the value of a tag and the length of the tag.
+//!
+//! \param tag represents the tag for which the information needs to be
+//!        retrieved.
+//!        Valid values are:
+//!        - \b TLV_TAG_RESERVED1
+//!        - \b TLV_TAG_RESERVED2
+//!        - \b TLV_TAG_CS
+//!        - \b TLV_TAG_FLASHCTL
+//!        - \b TLV_TAG_ADC14
+//!        - \b TLV_TAG_RESERVED6
+//!        - \b TLV_TAG_RESERVED7
+//!        - \b TLV_TAG_REF
+//!        - \b TLV_TAG_RESERVED9
+//!        - \b TLV_TAG_RESERVED10
+//!        - \b TLV_TAG_DEVINFO
+//!        - \b TLV_TAG_DIEREC
+//!        - \b TLV_TAG_RANDNUM
+//!        - \b TLV_TAG_RESERVED14
+//! \param instance In some cases a specific tag may have more than one
+//!        instance. For example there may be multiple instances of timer
+//!        calibration data present under a single Timer Cal tag. This variable
+//!        specifies the instance for which information is to be retrieved (0,
+//!        1, etc.). When only one instance exists; 0 is passed.
+//! \param length Acts as a return through indirect reference. The function
+//!        retrieves the value of the TLV tag length. This value is pointed to
+//!        by *length and can be used by the application level once the
+//!        function is called. If the specified tag is not found then the
+//!        pointer is null 0.
+//! \param data_address acts as a return through indirect reference. Once the
+//!        function is called data_address points to the pointer that holds the
+//!        value retrieved from the specified TLV tag. If the specified tag is
+//!        not found then the pointer is null 0.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
+        uint_fast8_t *length, uint32_t **data_address);
+
+//*****************************************************************************
+//
+//! Enables a set of banks in the SRAM. This can be used to optimize power
+//! consumption when every SRAM bank isn't needed. It is important to note
+//! that when a  higher bank is enabled, all of the SRAM banks below that bank
+//! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7,
+//! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled
+//! (SRAM_BANK0 is reserved and always enabled).
+//!
+//! \param sramBank The SRAM bank tier to enable.
+//!        Must be only one of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//!
+//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Disables a set of banks in the SRAM. This can be used to optimize power
+//! consumption when every SRAM bank isn't needed. It is important to note
+//! that when a  higher bank is disabled, all of the SRAM banks above that bank
+//! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5,
+//! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled.
+//!
+//! \param sramBank The SRAM bank tier to disable.
+//!        Must be only one of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//!
+//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Enables retention of the specified SRAM bank register when the device goes
+//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
+//! banks specified with this function will be placed into retention mode. By
+//! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is
+//! disabled. Retention of individual banks can be set without the restrictions
+//! of the enable/disable functions.
+//!
+//! \param sramBank The SRAM banks to enable retention
+//!        Can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//! \note  \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Disables retention of the specified SRAM bank register when the device goes
+//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
+//! banks specified with this function will not be placed into retention mode.
+//! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved)
+//! is disabled. Retention of individual banks can be set without the
+//! restrictions of the enable/disable SRAM bank functions.
+//!
+//! \param sramBank The SRAM banks to disable retention
+//!        Can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_SRAM_BANK1,
+//!                 - \b SYSCTL_SRAM_BANK2,
+//!                 - \b SYSCTL_SRAM_BANK3,
+//!                 - \b SYSCTL_SRAM_BANK4,
+//!                 - \b SYSCTL_SRAM_BANK5,
+//!                 - \b SYSCTL_SRAM_BANK6,
+//!                 - \b SYSCTL_SRAM_BANK7
+//! \note  \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled.
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank);
+
+//*****************************************************************************
+//
+//! Makes it so that the provided peripherals will either halt execution after
+//! a CPU HALT. Parameters in this function can be combined to account for
+//! multiple peripherals. By default, all peripherals keep running after a
+//! CPU HALT.
+//!
+//! \param devices The peripherals to continue running after a CPU HALT
+//!         This can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_PERIPH_DMA,
+//!                 - \b SYSCTL_PERIPH_WDT,
+//!                 - \b SYSCTL_PERIPH_ADC,
+//!                 - \b SYSCTL_PERIPH_EUSCIB3,
+//!                 - \b SYSCTL_PERIPH_EUSCIB2,
+//!                 - \b SYSCTL_PERIPH_EUSCIB1
+//!                 - \b SYSCTL_PERIPH_EUSCIB0,
+//!                 - \b SYSCTL_PERIPH_EUSCIA3,
+//!                 - \b SYSCTL_PERIPH_EUSCIA2
+//!                 - \b SYSCTL_PERIPH_EUSCIA1,
+//!                 - \b SYSCTL_PERIPH_EUSCIA0,
+//!                 - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
+//!                 - \b SYSCTL_PERIPH_TIMER16_3,
+//!                 - \b SYSCTL_PERIPH_TIMER16_2,
+//!                 - \b SYSCTL_PERIPH_TIMER16_1,
+//!                 - \b SYSCTL_PERIPH_TIMER16_0
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices);
+
+//*****************************************************************************
+//
+//! Makes it so that the provided peripherals will either halt execution after
+//! a CPU HALT. Parameters in this function can be combined to account for
+//! multiple peripherals. By default, all peripherals keep running after a
+//! CPU HALT.
+//!
+//! \param devices The peripherals to disable after a CPU HALT
+//!
+//! The \e devices parameter can be a bitwise OR of the following values:
+//!         This can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_PERIPH_DMA,
+//!                 - \b SYSCTL_PERIPH_WDT,
+//!                 - \b SYSCTL_PERIPH_ADC,
+//!                 - \b SYSCTL_PERIPH_EUSCIB3,
+//!                 - \b SYSCTL_PERIPH_EUSCIB2,
+//!                 - \b SYSCTL_PERIPH_EUSCIB1
+//!                 - \b SYSCTL_PERIPH_EUSCIB0,
+//!                 - \b SYSCTL_PERIPH_EUSCIA3,
+//!                 - \b SYSCTL_PERIPH_EUSCIA2
+//!                 - \b SYSCTL_PERIPH_EUSCIA1,
+//!                 - \b SYSCTL_PERIPH_EUSCIA0,
+//!                 - \b SYSCTL_PERIPH_TIMER32_0_MODULE,
+//!                 - \b SYSCTL_PERIPH_TIMER16_3,
+//!                 - \b SYSCTL_PERIPH_TIMER16_2,
+//!                 - \b SYSCTL_PERIPH_TIMER16_1,
+//!                 - \b SYSCTL_PERIPH_TIMER16_0
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog timeout occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_HARD_RESET,
+//!         - \b SYSCTL_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog password violation
+//! occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_HARD_RESET,
+//!         - \b SYSCTL_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Disables NMIs for the provided modules. When disabled, a NMI flag will not
+//! occur when a fault condition comes from the corresponding modules.
+//!
+//! \param flags The NMI sources to disable
+//! Can be a bitwise OR of the following parameters:
+//!         - \b SYSCTL_NMIPIN_SRC,
+//!         - \b SYSCTL_PCM_SRC,
+//!         - \b SYSCTL_PSS_SRC,
+//!         - \b SYSCTL_CS_SRC
+//!
+//
+//*****************************************************************************
+extern void SysCtl_disableNMISource(uint_fast8_t flags);
+
+//*****************************************************************************
+//
+//! Enables NMIs for the provided modules. When enabled, a NMI flag will
+//! occur when a fault condition comes from the corresponding modules.
+//!
+//! \param flags The NMI sources to enable
+//! Can be a bitwise OR of the following parameters:
+//!         - \b SYSCTL_NMIPIN_SRC,
+//!         - \b SYSCTL_PCM_SRC,
+//!         - \b SYSCTL_PSS_SRC,
+//!         - \b SYSCTL_CS_SRC
+//!
+//
+//*****************************************************************************
+extern void SysCtl_enableNMISource(uint_fast8_t flags);
+
+//*****************************************************************************
+//
+//! Returns the current sources of NMIs that are enabled
+//!
+//! \return Bitwise OR of NMI flags that are enabled
+//
+//*****************************************************************************
+extern uint_fast8_t SysCtl_getNMISourceStatus(void);
+
+//*****************************************************************************
+//
+//! Enables glitch suppression on the reset pin of the device. Refer to the
+//! device data sheet for specific information about glitch suppression
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_enableGlitchFilter(void);
+
+//*****************************************************************************
+//
+//! Disables glitch suppression on the reset pin of the device. Refer to the
+//! device data sheet for specific information about glitch suppression
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_disableGlitchFilter(void);
+
+//*****************************************************************************
+//
+//! Retrieves the calibration constant of the temperature sensor to be used
+//! in temperature calculation.
+//!
+//! \param refVoltage Reference voltage being used.
+//!
+//! The \e refVoltage parameter must be only one of the following values:
+//!         - \b SYSCTL_1_2V_REF
+//!         - \b SYSCTL_1_45V_REF
+//!         - \b SYSCTL_2_5V_REF
+//!
+//! \param temperature is the calibration temperature that the user wants to be
+//!     returned.
+//!
+//! The \e temperature parameter must be only one of the following values:
+//!         - \b SYSCTL_30_DEGREES_C
+//!         - \b SYSCTL_85_DEGREES_C
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage,
+        uint32_t temperature);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __SYSCTL_H__

platform/vendor_bsp/TI/MSP432P4xx/sysctl_a.c

@@ -0,0 +1,409 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* DriverLib Includes */
+#include <sysctl_a.h>
+#include <debug.h>
+
+void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
+        uint_fast8_t *length, uint32_t **data_address)
+{
+    /* TLV Structure Start Address */
+    uint32_t *TLV_address = (uint32_t *) TLV_START;
+
+    if(*TLV_address == 0xFFFFFFFF)
+    {
+        *length = 0;
+        // Return 0 for TAG not found
+        *data_address = 0;
+        return;
+    }
+
+    while (((*TLV_address != tag)) // check for tag and instance
+    && (*TLV_address != TLV_TAGEND))         // do range check first
+    {
+        if (*TLV_address == tag)
+        {
+            if (instance == 0)
+            {
+                break;
+            }
+
+            /* Repeat until requested instance is reached */
+            instance--;
+        }
+
+        TLV_address += (*(TLV_address + 1)) + 2;
+    }
+
+    /* Check if Tag match happened... */
+    if (*TLV_address == tag)
+    {
+        /* Return length = Address + 1 */
+        *length = (*(TLV_address + 1)) * 4;
+        /* Return address of first data/value info = Address + 2 */
+        *data_address = (uint32_t *) (TLV_address + 2);
+    }
+    // If there was no tag match and the end of TLV structure was reached..
+    else
+    {
+        // Return 0 for TAG not found
+        *length = 0;
+        // Return 0 for TAG not found
+        *data_address = 0;
+    }
+}
+
+uint_least32_t SysCtl_A_getSRAMSize(void)
+{
+    return SYSCTL_A->SRAM_SIZE;
+}
+
+uint_least32_t SysCtl_A_getFlashSize(void)
+{
+    return SYSCTL_A->MAINFLASH_SIZE;
+}
+
+uint_least32_t SysCtl_A_getInfoFlashSize(void)
+{
+    return SYSCTL_A->INFOFLASH_SIZE;
+}
+
+void SysCtl_A_disableNMISource(uint_fast8_t flags)
+{
+    SYSCTL_A->NMI_CTLSTAT &= ~(flags);
+}
+
+void SysCtl_A_enableNMISource(uint_fast8_t flags)
+{
+    SYSCTL_A->NMI_CTLSTAT |= flags;
+}
+
+uint_fast8_t SysCtl_A_getNMISourceStatus(void)
+{
+    return SYSCTL_A->NMI_CTLSTAT;
+}
+
+void SysCtl_A_rebootDevice(void)
+{
+    SYSCTL_A->REBOOT_CTL = (SYSCTL_A_REBOOT_CTL_REBOOT | SYSCTL_A_REBOOT_KEY);
+}
+
+void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices)
+{
+    SYSCTL_A->PERIHALT_CTL &= ~devices;
+}
+
+void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices)
+{
+    SYSCTL_A->PERIHALT_CTL |= devices;
+}
+
+void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType)
+{
+    if (resetType)
+        SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_TIMEOUT;
+    else
+        SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_TIMEOUT;
+}
+
+void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType)
+{
+    if (resetType)
+        SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_VIOLATION;
+    else
+        SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_VIOLATION;
+}
+
+void SysCtl_A_enableGlitchFilter(void)
+{
+    SYSCTL_A->DIO_GLTFLT_CTL |= SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN;
+}
+
+void SysCtl_A_disableGlitchFilter(void)
+{
+    SYSCTL_A->DIO_GLTFLT_CTL &= ~SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN;
+}
+
+uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage,
+        uint32_t temperature)
+{
+    return HWREG16(TLV_BASE + refVoltage + temperature);
+}
+
+bool SysCtl_A_enableSRAM(uint32_t addr)
+{
+    uint32_t bankSize, bankBit;
+
+    /* If SRAM is busy, return false */
+    if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY))
+        return false;
+
+    /* Grabbing the bank size */
+    bankSize = SysCtl_A_getSRAMSize()  / SYSCTL_A->SRAM_NUMBANKS;
+    bankBit = (addr - SRAM_BASE) / bankSize;
+
+    if (bankBit < 32)
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL0 |= (1 << bankBit);
+    } else if (bankBit < 64)
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL1 |= (1 << (bankBit - 32));
+    } else if (bankBit < 96)
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL2 |= (1 << (bankBit - 64));
+    } else
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL3 |= (1 << (bankBit - 96));
+    }
+
+
+    return true;
+}
+
+bool SysCtl_A_disableSRAM(uint32_t addr)
+{
+    uint32_t bankSize, bankBit;
+
+    /* If SRAM is busy, return false */
+    if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY))
+        return false;
+
+    /* Grabbing the bank size */
+    bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS;
+    bankBit = (addr - SRAM_BASE) / bankSize;
+
+    if (bankBit < 32)
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL0 &= ~(0xFFFFFFFF << bankBit);
+    } else if (bankBit < 64)
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL1 &= ~(0xFFFFFFFF << (bankBit - 32));
+    } else if (bankBit < 96)
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL2 &= ~(0xFFFFFFFF << (bankBit - 64));
+    } else
+    {
+        SYSCTL_A->SRAM_BANKEN_CTL3 &= ~(0xFFFFFFFF << (bankBit - 96));
+    }
+
+
+    return true;
+}
+
+bool SysCtl_A_enableSRAMRetention(uint32_t startAddr,
+        uint32_t endAddr)
+{
+    uint32_t blockSize, blockBitStart, blockBitEnd;
+
+    if (startAddr > endAddr)
+        return false;
+
+    /* If SRAM is busy, return false */
+    if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY))
+        return false;
+
+    /* Getting how big each bank is and how many blocks we have per bank */
+    blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS;
+    blockBitStart = (startAddr - SRAM_BASE) / blockSize;
+    blockBitEnd = (endAddr - SRAM_BASE) / blockSize;
+
+    if (blockBitStart < 32)
+    {
+        if (blockBitEnd < 32)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF >> (31 - blockBitEnd))
+                    & (0xFFFFFFFF << blockBitStart);
+            return true;
+        } else if (blockBitEnd < 64)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
+            SYSCTL_A->SRAM_BLKRET_CTL1 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 32)));
+        } else if (blockBitEnd < 96)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
+            SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF;
+            SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 64)));
+        } else
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart);
+            SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF;
+            SYSCTL_A->SRAM_BLKRET_CTL2 = 0xFFFFFFFF;
+            SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 96)));
+        }
+    } else if (blockBitStart < 64)
+    {
+        if (blockBitEnd < 64)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL1 |= ((0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 32)))
+                    & (0xFFFFFFFF << (blockBitStart - 32)));
+            return true;
+        }
+
+        SYSCTL_A->SRAM_BLKRET_CTL1 = (0xFFFFFFFF << (blockBitStart - 32));
+
+        if (blockBitEnd < 96)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 64)));
+        } else
+        {
+
+            SYSCTL_A->SRAM_BLKRET_CTL2 |= 0xFFFFFFFF;
+            SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 96)));
+        }
+    } else if (blockBitStart < 96)
+    {
+        if (blockBitEnd < 96)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 64)))
+                    & (0xFFFFFFFF << (blockBitStart - 64));
+            return true;
+        } else
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF << (blockBitStart - 64));
+            SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 96)));
+        }
+    } else
+    {
+        SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF >> (31 - (blockBitEnd - 96)))
+                & (0xFFFFFFFF << (blockBitStart - 96));
+    }
+
+    return true;
+
+}
+
+bool SysCtl_A_disableSRAMRetention(uint32_t startAddr,
+        uint32_t endAddr)
+{
+    uint32_t blockSize, blockBitStart, blockBitEnd;
+
+    if (startAddr > endAddr)
+        return false;
+
+    /* If SRAM is busy, return false */
+    if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY))
+        return false;
+
+
+    /* Getting how big each bank is and how many blocks we have per bank */
+    blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS;
+    blockBitStart = (startAddr - SRAM_BASE) / blockSize;
+    blockBitEnd = (endAddr - SRAM_BASE) / blockSize;
+
+    if (blockBitStart < 32)
+    {
+        if (blockBitEnd < 32)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF >> (31 - blockBitEnd))
+                    & (0xFFFFFFFF << blockBitStart));
+            return true;
+        }
+
+        SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF << blockBitStart));
+
+        if (blockBitEnd < 64)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 32))));
+        } else if (blockBitEnd < 96)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL1 = 0;
+            SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 64)));
+        } else
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL1 = 0;
+            SYSCTL_A->SRAM_BLKRET_CTL2 = 0;
+            SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 96)));
+        }
+    } else if (blockBitStart < 64)
+    {
+        if (blockBitEnd < 64)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 32)))
+                    & (0xFFFFFFFF << (blockBitStart - 32)));
+            return true;
+        }
+
+        SYSCTL_A->SRAM_BLKRET_CTL1 &= ~(0xFFFFFFFF << (blockBitStart - 32));
+
+        if (blockBitEnd < 96)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 64)));
+        } else
+        {
+
+            SYSCTL_A->SRAM_BLKRET_CTL2 = 0;
+            SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 96)));
+        }
+    } else if (blockBitStart < 96)
+    {
+        if (blockBitEnd < 96)
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL2 &= ~((0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 64)))
+                    & (0xFFFFFFFF << (blockBitStart - 64)));
+        } else
+        {
+            SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF << (blockBitStart - 64));
+            SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF
+                    >> (31 - (blockBitEnd - 96)));
+        }
+    } else
+    {
+        SYSCTL_A->SRAM_BLKRET_CTL3 &= ~((0xFFFFFFFF >> (31 - (blockBitEnd - 96)))
+                & (0xFFFFFFFF << (blockBitStart - 96)));
+    }
+
+    return true;
+}

platform/vendor_bsp/TI/MSP432P4xx/sysctl_a.h

@@ -0,0 +1,559 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __SYSCTL_A_H__
+#define __SYSCTL_A_H__
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_a_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define SYSCTL_A_HARD_RESET 1
+#define SYSCTL_A_SOFT_RESET 0
+
+#define SYSCTL_A_PERIPH_LCD SYSCTL_A_PERIHALT_CTL_HALT_LCD
+#define SYSCTL_A_PERIPH_DMA SYSCTL_A_PERIHALT_CTL_HALT_DMA
+#define SYSCTL_A_PERIPH_WDT SYSCTL_A_PERIHALT_CTL_HALT_WDT
+#define SYSCTL_A_PERIPH_ADC SYSCTL_A_PERIHALT_CTL_HALT_ADC
+#define SYSCTL_A_PERIPH_EUSCIB3 SYSCTL_A_PERIHALT_CTL_HALT_EUB3
+#define SYSCTL_A_PERIPH_EUSCIB2 SYSCTL_A_PERIHALT_CTL_HALT_EUB2
+#define SYSCTL_A_PERIPH_EUSCIB1 SYSCTL_A_PERIHALT_CTL_HALT_EUB1
+#define SYSCTL_A_PERIPH_EUSCIB0 SYSCTL_A_PERIHALT_CTL_HALT_EUB0
+#define SYSCTL_A_PERIPH_EUSCIA3 SYSCTL_A_PERIHALT_CTL_HALT_EUA3
+#define SYSCTL_A_PERIPH_EUSCIA2 SYSCTL_A_PERIHALT_CTL_HALT_EUA2
+#define SYSCTL_A_PERIPH_EUSCIA1 SYSCTL_A_PERIHALT_CTL_HALT_EUA1
+#define SYSCTL_A_PERIPH_EUSCIA0 SYSCTL_A_PERIHALT_CTL_HALT_EUA0
+#define SYSCTL_A_PERIPH_TIMER32_0_MODULE SYSCTL_A_PERIHALT_CTL_HALT_T32_0
+#define SYSCTL_A_PERIPH_TIMER16_3 SYSCTL_A_PERIHALT_CTL_HALT_T16_3
+#define SYSCTL_A_PERIPH_TIMER16_2 SYSCTL_A_PERIHALT_CTL_HALT_T16_2
+#define SYSCTL_A_PERIPH_TIMER16_1 SYSCTL_A_PERIHALT_CTL_HALT_T16_1
+#define SYSCTL_A_PERIPH_TIMER16_0 SYSCTL_A_PERIHALT_CTL_HALT_T16_0
+
+#define SYSCTL_A_NMIPIN_SRC SYSCTL_A_NMI_CTLSTAT_PIN_SRC
+#define SYSCTL_A_PCM_SRC SYSCTL_A_NMI_CTLSTAT_PCM_SRC
+#define SYSCTL_A_PSS_SRC SYSCTL_A_NMI_CTLSTAT_PSS_SRC
+#define SYSCTL_A_CS_SRC SYSCTL_A_NMI_CTLSTAT_CS_SRC
+
+#define SYSCTL_A_REBOOT_KEY   0x6900
+
+#define SYSCTL_A_1_2V_REF        (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
+#define SYSCTL_A_1_45V_REF       (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
+#define SYSCTL_A_2_5V_REF        (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
+
+#define SYSCTL_A_85_DEGREES_C    4
+#define SYSCTL_A_30_DEGREES_C    0
+
+#define SYSCTL_A_BANKMASK       0x80000000
+#define SRAMCTL_CTL0_BANK       0x10000000
+#define SRAMCTL_CTL1_BANK       0x20000000
+#define SRAMCTL_CTL2_BANK       0x30000000
+#define SRAMCTL_CTL3_BANK       0x40000000
+
+
+#define TLV_START               0x00201004
+#define TLV_TAG_RESERVED1      1
+#define TLV_TAG_RESERVED2      2
+#define TLV_TAG_CS             3
+#define TLV_TAG_FLASHCTL       4
+#define TLV_TAG_ADC14          5
+#define TLV_TAG_RESERVED6      6
+#define TLV_TAG_RESERVED7      7
+#define TLV_TAG_REF            8
+#define TLV_TAG_RESERVED9      9
+#define TLV_TAG_RESERVED10     10
+#define TLV_TAG_DEVINFO        11
+#define TLV_TAG_DIEREC         12
+#define TLV_TAG_RANDNUM        13
+#define TLV_TAG_RESERVED14     14
+#define TLV_TAG_BSL            15
+#define TLV_TAGEND             0x0BD0E11D
+
+//*****************************************************************************
+//
+// Structures for TLV definitions
+//
+//*****************************************************************************
+typedef struct
+{
+    uint32_t    maxProgramPulses;
+    uint32_t    maxErasePulses;
+} SysCtl_A_FlashTLV_Info;
+
+typedef struct
+{
+    uint32_t rDCOIR_FCAL_RSEL04;
+    uint32_t rDCOIR_FCAL_RSEL5;
+    uint32_t rDCOIR_MAXPOSTUNE_RSEL04;
+    uint32_t rDCOIR_MAXNEGTUNE_RSEL04;
+    uint32_t rDCOIR_MAXPOSTUNE_RSEL5;
+    uint32_t rDCOIR_MAXNEGTUNE_RSEL5;
+    uint32_t rDCOIR_CONSTK_RSEL04;
+    uint32_t rDCOIR_CONSTK_RSEL5;
+    uint32_t rDCOER_FCAL_RSEL04;
+    uint32_t rDCOER_FCAL_RSEL5;
+    uint32_t rDCOER_MAXPOSTUNE_RSEL04;
+    uint32_t rDCOER_MAXNEGTUNE_RSEL04;
+    uint32_t rDCOER_MAXPOSTUNE_RSEL5;
+    uint32_t rDCOER_MAXNEGTUNE_RSEL5;
+    uint32_t rDCOER_CONSTK_RSEL04;
+    uint32_t rDCOER_CONSTK_RSEL5;
+
+} SysCtl_A_CSCalTLV_Info;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_A_getSRAMSize(void);
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! \return The total number of bytes of main flash memory.
+//!
+//! \note This returns the total amount of main memory flash. To find how much
+//!        INFO memory is available, use the \link SysCtl_A_getInfoFlashSize
+//!         \endlink function.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_A_getFlashSize(void);
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! \return The total number of bytes of flash of INFO flash memory.
+//!
+//! \note This returns the total amount of INFO memory flash. To find how much
+//!        main  memory is available, use the \link SysCtl_A_getFlashSize
+//!         \endlink function.
+//
+//*****************************************************************************
+extern uint_least32_t SysCtl_A_getInfoFlashSize(void);
+
+//*****************************************************************************
+//
+//! Reboots the device and causes the device to re-initialize itself.
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+extern void SysCtl_A_rebootDevice(void);
+
+//*****************************************************************************
+//
+//! The TLV structure uses a tag or base address to identify segments of the
+//! table where information is stored. Some examples of TLV tags are Peripheral
+//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves
+//! the value of a tag and the length of the tag.
+//!
+//! \param tag represents the tag for which the information needs to be
+//!        retrieved.
+//!        Valid values are:
+//!        - \b TLV_TAG_RESERVED1
+//!        - \b TLV_TAG_RESERVED2
+//!        - \b TLV_TAG_CS
+//!        - \b TLV_TAG_FLASHCTL
+//!        - \b TLV_TAG_ADC14
+//!        - \b TLV_TAG_RESERVED6
+//!        - \b TLV_TAG_RESERVED7
+//!        - \b TLV_TAG_REF
+//!        - \b TLV_TAG_RESERVED9
+//!        - \b TLV_TAG_RESERVED10
+//!        - \b TLV_TAG_DEVINFO
+//!        - \b TLV_TAG_DIEREC
+//!        - \b TLV_TAG_RANDNUM
+//!        - \b TLV_TAG_RESERVED14
+//! \param instance In some cases a specific tag may have more than one
+//!        instance. For example there may be multiple instances of timer
+//!        calibration data present under a single Timer Cal tag. This variable
+//!        specifies the instance for which information is to be retrieved (0,
+//!        1, etc.). When only one instance exists; 0 is passed.
+//! \param length Acts as a return through indirect reference. The function
+//!        retrieves the value of the TLV tag length. This value is pointed to
+//!        by *length and can be used by the application level once the
+//!        function is called. If the specified tag is not found then the
+//!        pointer is null 0.
+//! \param data_address acts as a return through indirect reference. Once the
+//!        function is called data_address points to the pointer that holds the
+//!        value retrieved from the specified TLV tag. If the specified tag is
+//!        not found then the pointer is null 0.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance,
+        uint_fast8_t *length, uint32_t **data_address);
+
+//*****************************************************************************
+//
+//! Enables areas of SRAM memory. This can be used to optimize power
+//! consumption when every SRAM bank isn't needed. 
+//! This function takes in a 32-bit address to the area in SRAM to to enable.
+//! It will convert this address into the corresponding register settings and
+//! set them in the register accordingly. Note that passing an address to an
+//! area other than SRAM will result in unreliable behavior. Addresses should
+//! be given with reference to the SRAM_DATA area of SRAM (usually starting at
+//! 0x20000000).
+//!
+//! \param addr Break address of SRAM to enable. All SRAM below this address
+//!     will also be enabled. If an unaligned address is given the appropriate
+//!     aligned address will be calculated.
+//!
+//! \note The first bank of SRAM is reserved and always enabled.
+//!
+//! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is
+//!               not set in the STAT register, this function will return false.
+//
+//*****************************************************************************
+extern bool SysCtl_A_enableSRAM(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Disables areas of SRAM memory. This can be used to optimize power
+//! consumption when every SRAM bank isn't needed. It is important to note
+//! that when a  higher bank is disabled, all of the SRAM banks above that bank
+//! are also disabled. For example, if the address of 0x2001FA0 is given, all
+//! SRAM banks from 0x2001FA0 to the top of SRAM will be disabled.
+//! This function takes in a 32-bit address to the area in SRAM to to disable.
+//! It will convert this address into the corresponding register settings and
+//! set them in the register accordingly. Note that passing an address to an
+//! area other than SRAM will result in unreliable behavior. Addresses should
+//! be given with reference to the SRAM_DATA area of SRAM (usually starting at
+//! 0x20000000).
+//!
+//! \param addr Break address of SRAM to disable. All SRAM above this address
+//!     will also be disabled. If an unaligned address is given the appropriate
+//!     aligned address will be calculated.
+//!
+//! \note The first bank of SRAM is reserved and always enabled.
+//!
+//! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is
+//!               not set in the STAT register, this function will return false.
+//
+//*****************************************************************************
+extern bool SysCtl_A_disableSRAM(uint32_t addr);
+
+//*****************************************************************************
+//
+//! Enables retention of the specified SRAM block address range when the device
+//! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
+//! banks specified with this function will be placed into retention mode.
+//! Retention of individual blocks can be set without the restrictions of the
+//! enable/disable functions. Note that any memory range given outside of SRAM
+//! will result in unreliable behavior. Also note that any unaligned addresses
+//! will be truncated to the closest aligned address before the address given.
+//! Addresses should be given with reference to the SRAM_DATA area of SRAM
+//! (usually starting at 0x20000000).
+//!
+//! \param startAddr Start address to enable retention
+//!
+//! \param endtAddr End address to enable retention
+//!
+//! \note  Block 0 is reserved and retention is always enabled.
+//!
+//! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is
+//!               not set in the STAT register, this function will return false.
+//
+//*****************************************************************************
+extern bool SysCtl_A_enableSRAMRetention(uint32_t startAddr,
+        uint32_t endAddr);
+
+//*****************************************************************************
+//
+//! Disables retention of the specified SRAM block address range when the device
+//! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM
+//! banks specified with this function will be placed into retention mode.
+//! Retention of individual blocks can be set without the restrictions of the
+//! enable/disable functions. Note that any memory range given outside of SRAM
+//! will result in unreliable behavior. Also note that any unaligned addresses
+//! will be truncated to the closest aligned address before the address given.
+//! Addresses should be given with reference to the SRAM_DATA area of SRAM
+//! (usually starting at 0x20000000).
+//!
+//! \param startAddr Start address to disable retention
+//!
+//! \param endtAddr End address to disable retention
+//!
+//! \note  Block 0 is reserved and retention is always enabled.
+//!
+//! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is
+//!               not set in the STAT register, this function will return false.
+//
+//*****************************************************************************
+extern bool SysCtl_A_disableSRAMRetention(uint32_t startAddr,
+        uint32_t endAddr);
+
+//*****************************************************************************
+//
+//! Makes it so that the provided peripherals will either halt execution after
+//! a CPU HALT. Parameters in this function can be combined to account for
+//! multiple peripherals. By default, all peripherals keep running after a
+//! CPU HALT.
+//!
+//! \param devices The peripherals to continue running after a CPU HALT
+//!         This can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_A_PERIPH_LCD,
+//!                 - \b SYSCTL_A_PERIPH_DMA,
+//!                 - \b SYSCTL_A_PERIPH_WDT,
+//!                 - \b SYSCTL_A_PERIPH_ADC,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB3,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB2,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB1
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB0,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA3,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA2
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA1,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA0,
+//!                 - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_3,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_2,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_1,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_0
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices);
+
+//*****************************************************************************
+//
+//! Makes it so that the provided peripherals will either halt execution after
+//! a CPU HALT. Parameters in this function can be combined to account for
+//! multiple peripherals. By default, all peripherals keep running after a
+//! CPU HALT.
+//!
+//! \param devices The peripherals to disable after a CPU HALT
+//!
+//! The \e devices parameter can be a bitwise OR of the following values:
+//!         This can be a bitwise OR of the following values:
+//!                 - \b SYSCTL_A_PERIPH_LCD,
+//!                 - \b SYSCTL_A_PERIPH_DMA,
+//!                 - \b SYSCTL_A_PERIPH_WDT,
+//!                 - \b SYSCTL_A_PERIPH_ADC,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB3,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB2,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB1
+//!                 - \b SYSCTL_A_PERIPH_EUSCIB0,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA3,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA2
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA1,
+//!                 - \b SYSCTL_A_PERIPH_EUSCIA0,
+//!                 - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_3,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_2,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_1,
+//!                 - \b SYSCTL_A_PERIPH_TIMER16_0
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog timeout occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_A_HARD_RESET,
+//!         - \b SYSCTL_A_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog password violation
+//! occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!         - \b SYSCTL_A_HARD_RESET,
+//!         - \b SYSCTL_A_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Disables NMIs for the provided modules. When disabled, a NMI flag will not
+//! occur when a fault condition comes from the corresponding modules.
+//!
+//! \param flags The NMI sources to disable
+//! Can be a bitwise OR of the following parameters:
+//!         - \b SYSCTL_A_NMIPIN_SRC,
+//!         - \b SYSCTL_A_PCM_SRC,
+//!         - \b SYSCTL_A_PSS_SRC,
+//!         - \b SYSCTL_A_CS_SRC
+//!
+//
+//*****************************************************************************
+extern void SysCtl_A_disableNMISource(uint_fast8_t flags);
+
+//*****************************************************************************
+//
+//! Enables NMIs for the provided modules. When enabled, a NMI flag will
+//! occur when a fault condition comes from the corresponding modules.
+//!
+//! \param flags The NMI sources to enable
+//! Can be a bitwise OR of the following parameters:
+//!         - \b SYSCTL_A_NMIPIN_SRC,
+//!         - \b SYSCTL_A_PCM_SRC,
+//!         - \b SYSCTL_A_PSS_SRC,
+//!         - \b SYSCTL_A_CS_SRC
+//!
+//
+//*****************************************************************************
+extern void SysCtl_A_enableNMISource(uint_fast8_t flags);
+
+//*****************************************************************************
+//
+//! Returns the current sources of NMIs that are enabled
+//!
+//! \return NMI source status
+//
+//*****************************************************************************
+extern uint_fast8_t SysCtl_A_getNMISourceStatus(void);
+
+//*****************************************************************************
+//
+//! Enables glitch suppression on the reset pin of the device. Refer to the
+//! device data sheet for specific information about glitch suppression
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_A_enableGlitchFilter(void);
+
+//*****************************************************************************
+//
+//! Disables glitch suppression on the reset pin of the device. Refer to the
+//! device data sheet for specific information about glitch suppression
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void SysCtl_A_disableGlitchFilter(void);
+
+//*****************************************************************************
+//
+//! Retrieves the calibration constant of the temperature sensor to be used
+//! in temperature calculation.
+//!
+//! \param refVoltage Reference voltage being used.
+//!
+//! The \e refVoltage parameter must be only one of the following values:
+//!         - \b SYSCTL_A_1_2V_REF
+//!         - \b SYSCTL_A_1_45V_REF
+//!         - \b SYSCTL_A_2_5V_REF
+//!
+//! \param temperature is the calibration temperature that the user wants to be
+//!     returned.
+//!
+//! The \e temperature parameter must be only one of the following values:
+//!         - \b SYSCTL_A_30_DEGREES_C
+//!         - \b SYSCTL_A_85_DEGREES_C
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage,
+        uint32_t temperature);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __SYSCTL_A_H__

platform/vendor_bsp/TI/MSP432P4xx/systick.c

@@ -0,0 +1,118 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <debug.h>
+#include <interrupt.h>
+#include <systick.h>
+
+void SysTick_enableModule(void)
+{
+    //
+    // Enable SysTick.
+    //
+    SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+void SysTick_disableModule(void)
+{
+    //
+    // Disable SysTick.
+    //
+    SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
+}
+
+void SysTick_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(FAULT_SYSTICK, intHandler);
+
+}
+
+void SysTick_unregisterInterrupt(void)
+{
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(FAULT_SYSTICK);
+}
+
+void SysTick_enableInterrupt(void)
+{
+    //
+    // Enable the SysTick interrupt.
+    //
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+void SysTick_disableInterrupt(void)
+{
+    //
+    // Disable the SysTick interrupt.
+    //
+    SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk);
+}
+
+void SysTick_setPeriod(uint32_t period)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((period > 0) && (period <= 16777216));
+
+    //
+    // Set the period of the SysTick counter.
+    //
+    SysTick->LOAD = period - 1;
+}
+
+uint32_t SysTick_getPeriod(void)
+{
+    //
+    // Return the period of the SysTick counter.
+    //
+    return (SysTick->LOAD + 1);
+}
+
+uint32_t SysTick_getValue(void)
+{
+    //
+    // Return the current value of the SysTick counter.
+    //
+    return (SysTick->VAL);
+}

platform/vendor_bsp/TI/MSP432P4xx/systick.h

@@ -0,0 +1,219 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include <stdint.h>
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This function starts the SysTick counter.  If an interrupt handler has been
+//! registered, it is called when the SysTick counter rolls over.
+//!
+//! \note Calling this function causes the SysTick counter to (re)commence
+//! counting from its current value.  The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTick_setPeriod().  If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force the reload.  Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_enableModule(void);
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This function stops the SysTick counter.  If an interrupt handler has been
+//! registered, it is not called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_disableModule(void);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This function registers the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function unregisters the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function enables the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler is not required to clear the SysTick
+//! interrupt source because it is cleared automatically by the NVIC when the
+//! interrupt handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_enableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function disables the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_disableInterrupt(void);
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param period is the number of clock ticks in each period of the SysTick
+//! counter and must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately.  If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written.  Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the \e period supplied here on
+//! the next clock after SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void SysTick_setPeriod(uint32_t period);
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+extern uint32_t SysTick_getPeriod(void);
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter, which is
+//! a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+extern uint32_t SysTick_getValue(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __SYSTICK_H__

platform/vendor_bsp/TI/MSP432P4xx/timer32.c

@@ -0,0 +1,151 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <timer32.h>
+#include <interrupt.h>
+#include <debug.h>
+
+void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution,
+        uint32_t mode)
+{
+    /* Setting up one shot or continuous mode */
+    if (mode == TIMER32_PERIODIC_MODE)
+        BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
+                    = 1;
+    else if (mode == TIMER32_FREE_RUN_MODE)
+        BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS)
+                    = 0;
+    else
+        ASSERT(false);
+
+    /* Setting the resolution of the timer */
+    if (resolution == TIMER32_16BIT)
+        BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+                    = 0;
+    else if (resolution == TIMER32_32BIT)
+        BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+                    = 1;
+    else
+        ASSERT(false);
+
+    /* Setting the PreScaler */
+    ASSERT(
+            resolution == TIMER32_PRESCALER_1
+            || resolution == TIMER32_PRESCALER_16
+            || resolution == TIMER32_PRESCALER_256);
+
+    TIMER32_CMSIS(timer)->CONTROL = TIMER32_CMSIS(timer)->CONTROL
+            & (~TIMER32_CONTROL_PRESCALE_MASK) | preScaler;
+
+}
+
+void Timer32_setCount(uint32_t timer, uint32_t count)
+{
+    if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+            && (count > UINT16_MAX))
+        TIMER32_CMSIS(timer)->LOAD = UINT16_MAX;
+    else
+        TIMER32_CMSIS(timer)->LOAD = count;
+}
+
+void Timer32_setCountInBackground(uint32_t timer, uint32_t count)
+{
+    if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS)
+            && (count > UINT16_MAX))
+        TIMER32_CMSIS(timer)->BGLOAD = UINT16_MAX;
+    else
+        TIMER32_CMSIS(timer)->BGLOAD = count;
+}
+
+uint32_t Timer32_getValue(uint32_t timer)
+{
+    return TIMER32_CMSIS(timer)->VALUE;
+}
+
+void Timer32_startTimer(uint32_t timer, bool oneShot)
+{
+    ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
+
+    if (oneShot)
+        BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
+                    = 1;
+    else
+        BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS)
+                    = 0;
+
+    TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_ENABLE;
+}
+
+void Timer32_haltTimer(uint32_t timer)
+{
+    ASSERT(timer == TIMER32_0_MODULE || timer == TIMER32_1_MODULE);
+
+    TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_ENABLE;
+}
+
+void Timer32_enableInterrupt(uint32_t timer)
+{
+    TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_IE;
+}
+
+void Timer32_disableInterrupt(uint32_t timer)
+{
+    TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_IE;
+}
+
+void Timer32_clearInterruptFlag(uint32_t timer)
+{
+    TIMER32_CMSIS(timer)->INTCLR |= 0x01;
+}
+
+uint32_t Timer32_getInterruptStatus(uint32_t timer)
+{
+    return TIMER32_CMSIS(timer)->MIS;
+}
+
+void Timer32_registerInterrupt(uint32_t timerInterrupt,
+        void (*intHandler)(void))
+{
+    Interrupt_registerInterrupt(timerInterrupt, intHandler);
+    Interrupt_enableInterrupt(timerInterrupt);
+}
+
+void Timer32_unregisterInterrupt(uint32_t timerInterrupt)
+{
+    Interrupt_disableInterrupt(timerInterrupt);
+    Interrupt_unregisterInterrupt(timerInterrupt);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/timer32.h

@@ -0,0 +1,361 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef TIMER32_H_
+#define TIMER32_H_
+
+//*****************************************************************************
+//
+//! \addtogroup timer32_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include <stdint.h>
+#include <stdbool.h>
+#include <msp.h>
+
+//*****************************************************************************
+//
+// Control specific variables
+//
+//*****************************************************************************
+#define TIMER32_CMSIS(x) ((Timer32_Type *) x)
+
+#define TIMER_OFFSET    0x020
+
+#define TIMER32_0_BASE   (uint32_t)TIMER32_1
+#define TIMER32_1_BASE   (uint32_t)TIMER32_2
+
+#define TIMER32_0_INTERRUPT         INT_T32_INT1
+#define TIMER32_1_INTERRUPT         INT_T32_INT2
+#define TIMER32_COMBINED_INTERRUPT  INT_T32_INTC
+
+#define TIMER32_16BIT            0x00
+#define TIMER32_32BIT            0x01
+
+#define TIMER32_PRESCALER_1      0x00
+#define TIMER32_PRESCALER_16     0x04
+#define TIMER32_PRESCALER_256    0x08
+
+#define TIMER32_FREE_RUN_MODE   0x00
+#define TIMER32_PERIODIC_MODE   0x01
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Initializes the Timer32 module
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! \param preScaler is the prescaler (or divider) to apply to the clock
+//! source given to the Timer32 module.
+//!         Valid values are
+//!         - \b TIMER32_PRESCALER_1 [DEFAULT]
+//!         - \b TIMER32_PRESCALER_16
+//!         - \b TIMER32_PRESCALER_256
+//! \param resolution is the bit resolution of the Timer32 module.
+//!         Valid values are
+//!         - \b TIMER32_16BIT [DEFAULT]
+//!         - \b TIMER32_32BIT
+//! \param mode selects between free run and periodic mode. In free run
+//! mode, the value of the timer is reset to UINT16_MAX (for 16-bit mode) or
+//! UINT32_MAX (for 16-bit mode) when the timer reaches zero. In periodic mode,
+//! the timer is reset to the value set by the Timer32_setCount function.
+//!         Valid values are
+//!         - \b TIMER32_FREE_RUN_MODE [DEFAULT]
+//!         - \b TIMER32_PERIODIC_MODE
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_initModule(uint32_t timer, uint32_t preScaler,
+        uint32_t resolution, uint32_t mode);
+
+//*****************************************************************************
+//
+//! Sets the count of the timer and resets the current value to the value
+//! passed. This value is set on the next rising edge of the clock provided to
+//! the timer module
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//! \param count Value of the timer to set. Note that
+//! if the timer is in 16-bit mode and a value is passed in that exceeds
+//! UINT16_MAX, the value will be truncated to UINT16_MAX.
+//!
+//! Also note that if the timer is operating in periodic mode, the value passed
+//! into this function will represent the new period of the timer (the value
+//! which is reloaded into the timer each time it reaches a zero value).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_setCount(uint32_t timer, uint32_t count);
+
+//*****************************************************************************
+//
+//! Sets the count of the timer without resetting the current value. When the
+//! current value of the timer reaches zero, the value passed into this function
+//! will be set as the new count value.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//! \param count Value of the timer to set in the background. Note that
+//! if the timer is in 16-bit mode and a value is passed in that exceeds
+//! UINT16_MAX, the value will be truncated to UINT16_MAX.
+//!
+//! Also note that if the timer is operating in periodic mode, the value passed
+//! into this function will represent the new period of the timer (the value
+//! which is reloaded into the timer each time it reaches a zero value).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_setCountInBackground(uint32_t timer, uint32_t count);
+
+//*****************************************************************************
+//
+//! Returns the current value of the timer.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! \return The current count of the timer.
+//
+//*****************************************************************************
+extern uint32_t Timer32_getValue(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Starts the timer. The Timer32_initModule function should be called (in
+//! conjunction with Timer32_setCount if periodic mode is desired) prior to
+//  starting the timer.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! \param oneShot sets whether the Timer32 module operates in one shot
+//!  or continuous mode. In one shot mode, the timer will halt when a zero is
+//!  reached and stay halted until either:
+//!         - The user calls the Timer32PeriodSet function
+//!         - The Timer32_initModule is called to reinitialize the timer with one-shot
+//!             mode disabled.
+//!
+//! A true value will cause the timer to operate in one shot mode while a false
+//! value will cause the timer to operate in continuous mode
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_startTimer(uint32_t timer, bool oneShot);
+
+//*****************************************************************************
+//
+//! Halts the timer. Current count and setting values are preserved.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void Timer32_haltTimer(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Enables a Timer32 interrupt source.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! Enables the indicated Timer32 interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_enableInterrupt(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Disables a Timer32 interrupt source.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! Disables the indicated Timer32 interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_disableInterrupt(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Clears Timer32 interrupt source.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! The Timer32 interrupt source is cleared, so that it no longer asserts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_clearInterruptFlag(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Gets the current Timer32 interrupt status.
+//!
+//! \param timer is the instance of the Timer32 module.
+//! Valid parameters must be one of the following values:
+//!         - \b TIMER32_0_BASE
+//!         - \b TIMER32_1_BASE
+//!
+//! This returns the interrupt status for the Timer32 module. A positive value
+//! will indicate that an interrupt is pending while a zero value will indicate
+//! that no interrupt is pending.
+//!
+//! \return The current interrupt status
+//
+//*****************************************************************************
+extern uint32_t Timer32_getInterruptStatus(uint32_t timer);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for Timer32 interrupts.
+//!
+//! \param timerInterrupt is the specific interrupt to register. For the
+//! Timer32 module, there are a total of three different interrupts: one
+//! interrupt for each two Timer32 modules, and a "combined" interrupt which
+//! is a logical OR of each individual Timer32 interrupt.
+//!         - \b TIMER32_0_INTERRUPT
+//!         - \b TIMER32_1_INTERRUPT
+//!         - \b TIMER32_COMBINED_INTERRUPT
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! Timer32 interrupt occurs.
+//!
+//! This function registers the handler to be called when an Timer32
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific Timer32 interrupts must be enabled
+//! via Timer32_enableInterrupt().  It is the interrupt handler's
+//! responsibility to clear the interrupt source
+//! via Timer32_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_registerInterrupt(uint32_t timerInterrupt,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the Timer32 interrupt.
+//!
+//! \param timerInterrupt is the specific interrupt to register. For the
+//! Timer32 module, there are a total of three different interrupts: one
+//! interrupt for each two Timer32 modules, and a "combined" interrupt which
+//! is a logical OR of each individual Timer32 interrupt.
+//!         - \b TIMER32_0_INTERRUPT
+//!         - \b TIMER32_1_INTERRUPT
+//!         - \b TIMER32_COMBINED_INTERRUPT
+//!
+//! This function unregisters the handler to be called when a Timer32
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void Timer32_unregisterInterrupt(uint32_t timerInterrupt);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* TIMER32_H_ */

platform/vendor_bsp/TI/MSP432P4xx/timer_a.c

@@ -0,0 +1,812 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <timer_a.h>
+#include <interrupt.h>
+#include <debug.h>
+
+static void privateTimer_AProcessClockSourceDivider(uint32_t timer,
+        uint16_t clockSourceDivider)
+{
+    TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_ID__8;
+    TIMER_A_CMSIS(timer)->EX0 &= ~TIMER_A_EX0_IDEX_MASK;
+
+    switch (clockSourceDivider)
+    {
+    case TIMER_A_CLOCKSOURCE_DIVIDER_1:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_2:
+        TIMER_A_CMSIS(timer)->CTL |= ((clockSourceDivider - 1) << 6);
+        TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_4:
+        TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
+        TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_8:
+        TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
+        TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0;
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_3:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_5:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_6:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_7:
+        TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__1;
+        TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider - 1);
+        break;
+
+    case TIMER_A_CLOCKSOURCE_DIVIDER_10:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_12:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_14:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_16:
+        TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__2;
+        TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 2 - 1);
+        break;
+
+    case TIMER_A_CLOCKSOURCE_DIVIDER_20:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_24:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_28:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_32:
+        TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4;
+        TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 4 - 1);
+        break;
+    case TIMER_A_CLOCKSOURCE_DIVIDER_40:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_48:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_56:
+    case TIMER_A_CLOCKSOURCE_DIVIDER_64:
+        TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8;
+        TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 8 - 1);
+        break;
+    }
+}
+
+void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode)
+{
+    ASSERT(
+            (TIMER_A_UPDOWN_MODE == timerMode)
+            || (TIMER_A_CONTINUOUS_MODE == timerMode)
+            || (TIMER_A_UP_MODE == timerMode));
+
+    TIMER_A_CMSIS(timer)->CTL |= timerMode;
+}
+
+void Timer_A_configureContinuousMode(uint32_t timer,
+        const Timer_A_ContinuousModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    ASSERT(
+            (TIMER_A_TAIE_INTERRUPT_ENABLE == config->timerInterruptEnable_TAIE)
+            || (TIMER_A_TAIE_INTERRUPT_DISABLE
+                    == config->timerInterruptEnable_TAIE));
+
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_DIVIDER_1 == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_2
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_4
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_8
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_3
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_5
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_6
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_7
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_10
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_12
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_14
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_16
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_20
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_24
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_28
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_32
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_40
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_48
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_56
+                    == config->clockSourceDivider)
+            || (TIMER_A_CLOCKSOURCE_DIVIDER_64
+                    == config->clockSourceDivider));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->CTL = (TIMER_A_CMSIS(timer)->CTL
+            & ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    + TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR
+                    + TIMER_A_TAIE_INTERRUPT_ENABLE))
+            | (config->clockSource + config->timerClear
+                    + config->timerInterruptEnable_TAIE);
+}
+
+void Timer_A_configureUpMode(uint32_t timer, const Timer_A_UpModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->CTL &=
+            ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+                    + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
+
+    TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + config->timerClear
+            + config->timerInterruptEnable_TAIE);
+
+    if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
+            == config->captureCompareInterruptEnable_CCR0_CCIE)
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
+    else
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
+
+    TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
+}
+
+void Timer_A_configureUpDownMode(uint32_t timer,
+        const Timer_A_UpDownModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    ASSERT(
+            (TIMER_A_DO_CLEAR == config->timerClear)
+            || (TIMER_A_SKIP_CLEAR == config->timerClear));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->CTL &=
+            ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+                    + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
+
+    TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_STOP_MODE
+            + config->timerClear + config->timerInterruptEnable_TAIE);
+    if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE
+            == config->captureCompareInterruptEnable_CCR0_CCIE)
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1;
+    else
+        BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0;
+
+    TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
+}
+
+void Timer_A_initCapture(uint32_t timer,
+        const Timer_A_CaptureModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == config->captureRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == config->captureRegister));
+
+    ASSERT(
+            (TIMER_A_CAPTUREMODE_NO_CAPTURE == config->captureMode)
+            || (TIMER_A_CAPTUREMODE_RISING_EDGE == config->captureMode)
+            || (TIMER_A_CAPTUREMODE_FALLING_EDGE == config->captureMode)
+            || (TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
+                    == config->captureMode));
+
+    ASSERT(
+            (TIMER_A_CAPTURE_INPUTSELECT_CCIxA == config->captureInputSelect)
+            || (TIMER_A_CAPTURE_INPUTSELECT_CCIxB
+                    == config->captureInputSelect)
+            || (TIMER_A_CAPTURE_INPUTSELECT_GND
+                    == config->captureInputSelect)
+            || (TIMER_A_CAPTURE_INPUTSELECT_Vcc
+                    == config->captureInputSelect));
+
+    ASSERT(
+            (TIMER_A_CAPTURE_ASYNCHRONOUS == config->synchronizeCaptureSource)
+            || (TIMER_A_CAPTURE_SYNCHRONOUS
+                    == config->synchronizeCaptureSource));
+
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
+                    == config->captureInterruptEnable)
+            || (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+                    == config->captureInterruptEnable));
+
+    ASSERT(
+            (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_RESET
+                    == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET_RESET
+                    == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_SET
+                    == config->captureOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET_SET
+                    == config->captureOutputMode));
+
+    if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister)
+    {
+        //CaptureCompare register 0 only supports certain modes
+        ASSERT(
+                (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode)
+                || (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode)
+                || (TIMER_A_OUTPUTMODE_TOGGLE
+                        == config->captureOutputMode)
+                || (TIMER_A_OUTPUTMODE_RESET
+                        == config->captureOutputMode));
+    }
+    uint8_t idx = (config->captureRegister>>1)-1;
+    TIMER_A_CMSIS(timer)->CCTL[idx] =
+            (TIMER_A_CMSIS(timer)->CCTL[idx]
+                    & ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE
+                            | TIMER_A_CAPTURE_INPUTSELECT_Vcc
+                            | TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR
+                            | TIMER_A_TAIE_INTERRUPT_ENABLE | TIMER_A_CCTLN_CM_3))
+                    | (config->captureMode | config->captureInputSelect
+                            | config->synchronizeCaptureSource
+                            | config->captureInterruptEnable
+                            | config->captureOutputMode | TIMER_A_CCTLN_CAP);
+
+}
+
+void Timer_A_initCompare(uint32_t timer,
+        const Timer_A_CompareModeConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == config->compareRegister));
+
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+                    == config->compareInterruptEnable)
+            || (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE
+                    == config->compareInterruptEnable));
+
+    ASSERT(
+            (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_SET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET_SET
+                    == config->compareOutputMode));
+
+    if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
+    {
+        //CaptureCompare register 0 only supports certain modes
+        ASSERT(
+                (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
+                || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
+                || (TIMER_A_OUTPUTMODE_TOGGLE
+                        == config->compareOutputMode)
+                || (TIMER_A_OUTPUTMODE_RESET
+                        == config->compareOutputMode));
+    }
+
+    uint8_t idx = (config->compareRegister>>1)-1;
+    TIMER_A_CMSIS(timer)->CCTL[idx] =
+            (TIMER_A_CMSIS(timer)->CCTL[idx]
+             & ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+             | TIMER_A_OUTPUTMODE_RESET_SET | TIMER_A_CCTLN_CAP))
+             | (config->compareInterruptEnable + config->compareOutputMode);
+
+   TIMER_A_CMSIS(timer)->CCR[idx] = config->compareValue;
+
+}
+
+uint16_t Timer_A_getCounterValue(uint32_t timer)
+{
+    uint_fast16_t voteOne, voteTwo, res;
+
+    voteTwo = TIMER_A_CMSIS(timer)->R;
+
+    do
+    {
+        voteOne = voteTwo;
+        voteTwo = TIMER_A_CMSIS(timer)->R;
+
+        if (voteTwo > voteOne)
+            res = voteTwo - voteOne;
+        else if (voteOne > voteTwo)
+            res = voteOne - voteTwo;
+        else
+            res = 0;
+
+    } while (res > TIMER_A_THRESHOLD);
+
+    return voteTwo;
+
+}
+
+void Timer_A_clearTimer(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL , TIMER_A_CTL_CLR_OFS) = 1;
+}
+
+uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer,
+        uint_fast16_t captureCompareRegister, uint_fast16_t synchronizedSetting)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    ASSERT(
+            (TIMER_A_READ_CAPTURE_COMPARE_INPUT == synchronizedSetting)
+            || (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT
+                    == synchronizedSetting));
+
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    if (TIMER_A_CMSIS(timer)->CCTL[idx] & synchronizedSetting)
+        return TIMER_A_CAPTURECOMPARE_INPUT_HIGH;
+    else
+        return TIMER_A_CAPTURECOMPARE_INPUT_LOW;
+}
+
+uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_OUT_OFS))
+        return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH;
+    else
+        return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW;
+}
+
+uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    return (TIMER_A_CMSIS(timer)->CCR[idx]);
+}
+
+void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer,
+        uint_fast16_t captureCompareRegister,
+        uint_fast8_t outputModeOutBitValue)
+{
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    TIMER_A_CMSIS(timer)->CCTL[idx] =
+            ((TIMER_A_CMSIS(timer)->CCTL[idx])
+                    & ~(TIMER_A_OUTPUTMODE_RESET_SET))
+                    | (outputModeOutBitValue);
+}
+
+void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config)
+{
+    ASSERT(
+            (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource)
+            || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK
+                    == config->clockSource));
+
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == config->compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == config->compareRegister));
+
+    ASSERT(
+            (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_SET_RESET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_TOGGLE_SET
+                    == config->compareOutputMode)
+            || (TIMER_A_OUTPUTMODE_RESET_SET
+                    == config->compareOutputMode));
+
+    privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider);
+
+    TIMER_A_CMSIS(timer)->CTL &=
+            ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE
+                    + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE);
+
+    TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_UP_MODE
+            + TIMER_A_DO_CLEAR);
+
+    TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod;
+
+    TIMER_A_CMSIS(timer)->CCTL[0] &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE
+            + TIMER_A_OUTPUTMODE_RESET_SET);
+
+    uint8_t idx = (config->compareRegister>>1) - 1;
+    TIMER_A_CMSIS(timer)->CCTL[idx] |= config->compareOutputMode;
+    TIMER_A_CMSIS(timer)->CCR[idx] = config->dutyCycle;
+}
+
+void Timer_A_stopTimer(uint32_t timer)
+{
+    TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_MC_3;
+}
+
+void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister,
+        uint_fast16_t compareValue)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister));
+
+    uint8_t idx = (compareRegister>>1) - 1;
+    TIMER_A_CMSIS(timer)->CCR[idx] = compareValue;
+}
+
+void Timer_A_clearInterruptFlag(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IFG_OFS) = 0;
+}
+
+void Timer_A_clearCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIFG_OFS) = 0;
+}
+
+void Timer_A_enableInterrupt(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 1;
+}
+
+void Timer_A_disableInterrupt(uint32_t timer)
+{
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 0;
+}
+
+uint32_t Timer_A_getInterruptStatus(uint32_t timer)
+{
+    return (TIMER_A_CMSIS(timer)->CTL) & TIMER_A_CTL_IFG;
+}
+
+void Timer_A_enableCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 1;
+}
+
+void Timer_A_disableCaptureCompareInterrupt(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    ASSERT(
+            (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_1
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_2
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_3
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_4
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_5
+                    == captureCompareRegister)
+            || (TIMER_A_CAPTURECOMPARE_REGISTER_6
+                    == captureCompareRegister));
+                    
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 0;
+
+}
+
+uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer,
+        uint_fast16_t captureCompareRegister, uint_fast16_t mask)
+{
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    return (TIMER_A_CMSIS(timer)->CCTL[idx]) & mask;
+}
+
+uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer)
+{
+    if (TIMER_A_CMSIS(timer)->CTL & TIMER_A_CTL_IE)
+    {
+        return Timer_A_getInterruptStatus(timer);
+    } else
+    {
+        return 0;
+    }
+
+}
+
+uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer,
+        uint_fast16_t captureCompareRegister)
+{
+    uint8_t idx = (captureCompareRegister>>1) - 1;
+    if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS))
+        return Timer_A_getCaptureCompareInterruptStatus(timer,
+                captureCompareRegister,
+                TIMER_A_CAPTURE_OVERFLOW |
+                TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG);
+    else
+        return 0;
+}
+
+void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect,
+        void (*intHandler)(void))
+{
+    if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_BASE:
+            Interrupt_registerInterrupt(INT_TA0_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA0_0);
+            break;
+        case TIMER_A1_BASE:
+            Interrupt_registerInterrupt(INT_TA1_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA1_0);
+            break;
+        case TIMER_A2_BASE:
+            Interrupt_registerInterrupt(INT_TA2_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA2_0);
+            break;
+        case TIMER_A3_BASE:
+            Interrupt_registerInterrupt(INT_TA3_0, intHandler);
+            Interrupt_enableInterrupt(INT_TA3_0);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_BASE:
+            Interrupt_registerInterrupt(INT_TA0_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA0_N);
+            break;
+        case TIMER_A1_BASE:
+            Interrupt_registerInterrupt(INT_TA1_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA1_N);
+            break;
+        case TIMER_A2_BASE:
+            Interrupt_registerInterrupt(INT_TA2_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA2_N);
+            break;
+        case TIMER_A3_BASE:
+            Interrupt_registerInterrupt(INT_TA3_N, intHandler);
+            Interrupt_enableInterrupt(INT_TA3_N);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else
+    {
+        ASSERT(false);
+    }
+}
+
+void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect)
+{
+    if (interruptSelect == TIMER_A_CCR0_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_BASE:
+            Interrupt_disableInterrupt(INT_TA0_0);
+            Interrupt_unregisterInterrupt(INT_TA0_0);
+            break;
+        case TIMER_A1_BASE:
+            Interrupt_disableInterrupt(INT_TA1_0);
+            Interrupt_unregisterInterrupt(INT_TA1_0);
+            break;
+        case TIMER_A2_BASE:
+            Interrupt_disableInterrupt(INT_TA2_0);
+            Interrupt_unregisterInterrupt(INT_TA2_0);
+            break;
+        case TIMER_A3_BASE:
+            Interrupt_disableInterrupt(INT_TA3_0);
+            Interrupt_unregisterInterrupt(INT_TA3_0);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT)
+    {
+        switch (timer)
+        {
+        case TIMER_A0_BASE:
+            Interrupt_disableInterrupt(INT_TA0_N);
+            Interrupt_unregisterInterrupt(INT_TA0_N);
+            break;
+        case TIMER_A1_BASE:
+            Interrupt_disableInterrupt(INT_TA1_N);
+            Interrupt_unregisterInterrupt(INT_TA1_N);
+            break;
+        case TIMER_A2_BASE:
+            Interrupt_disableInterrupt(INT_TA2_N);
+            Interrupt_unregisterInterrupt(INT_TA2_N);
+            break;
+        case TIMER_A3_BASE:
+            Interrupt_disableInterrupt(INT_TA3_N);
+            Interrupt_unregisterInterrupt(INT_TA3_N);
+            break;
+        default:
+            ASSERT(false);
+        }
+    } else
+    {
+        ASSERT(false);
+    }
+}
+

platform/vendor_bsp/TI/MSP432P4xx/uart.c

@@ -0,0 +1,396 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#include <uart.h>
+#include <interrupt.h>
+#include <debug.h>
+#include <eusci.h>
+
+bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config)
+{
+    bool retVal = true;
+
+    ASSERT(
+            (EUSCI_A_UART_MODE == config->uartMode)
+            || (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE
+                    == config->uartMode)
+            || (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE
+                    == config->uartMode)
+            || (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
+                    == config->uartMode));
+
+    ASSERT(
+            (EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource)
+            || (EUSCI_A_UART_CLOCKSOURCE_SMCLK
+                    == config->selectClockSource));
+
+    ASSERT(
+            (EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst)
+            || (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst));
+
+    ASSERT(
+            (EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits)
+            || (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits));
+
+    ASSERT(
+            (EUSCI_A_UART_NO_PARITY == config->parity)
+            || (EUSCI_A_UART_ODD_PARITY == config->parity)
+            || (EUSCI_A_UART_EVEN_PARITY == config->parity));
+
+    /* Disable the USCI Module */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
+
+    /* Clock source select */
+    EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+            (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK)
+                    | config->selectClockSource;
+
+    /* MSB, LSB select */
+    if (config->msborLsbFirst)
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1;
+    else
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0;
+
+    /* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */
+    if (config->numberofStopBits)
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1;
+    else
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0;
+
+    /* Parity */
+    switch (config->parity)
+    {
+    case EUSCI_A_UART_NO_PARITY:
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0;
+        break;
+    case EUSCI_A_UART_ODD_PARITY:
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0;
+        break;
+    case EUSCI_A_UART_EVEN_PARITY:
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1;
+        BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1;
+        break;
+    }
+
+    /* BaudRate Control Register */
+    EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar;
+    EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8)
+            + (config->firstModReg << 4) + config->overSampling);
+
+    /* Asynchronous mode & 8 bit character select & clear mode */
+    EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
+            (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+                    & ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM
+                            | EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode;
+
+    return retVal;
+}
+
+void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
+{
+    /* If interrupts are not used, poll for flags */
+    if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
+        while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
+            ;
+
+    EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData;
+}
+
+uint8_t UART_receiveData(uint32_t moduleInstance)
+{
+    /* If interrupts are not used, poll for flags */
+    if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_RXIE_OFS))
+        while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS))
+            ;
+
+    return EUSCI_A_CMSIS(moduleInstance)->RXBUF;
+}
+
+void UART_enableModule(uint32_t moduleInstance)
+{
+    /* Reset the UCSWRST bit to enable the USCI Module */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
+}
+
+void UART_disableModule(uint32_t moduleInstance)
+{
+    /* Set the UCSWRST bit to disable the USCI Module */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
+}
+
+uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    ASSERT(
+            0x00 != mask
+            && (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR
+                    + EUSCI_A_UART_OVERRUN_ERROR
+                    + EUSCI_A_UART_PARITY_ERROR
+                    + EUSCI_A_UART_BREAK_DETECT
+                    + EUSCI_A_UART_RECEIVE_ERROR
+                    + EUSCI_A_UART_ADDRESS_RECEIVED
+                    + EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY));
+
+    return EUSCI_A_CMSIS(moduleInstance)->STATW & mask;
+}
+
+void UART_setDormant(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1;
+}
+
+void UART_resetDormant(uint32_t moduleInstance)
+{
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0;
+}
+
+void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress)
+{
+    /* Set UCTXADDR bit */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1;
+
+    /* Place next byte to be sent into the transmit buffer */
+    EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress;
+}
+
+void UART_transmitBreak(uint32_t moduleInstance)
+{
+    /* Set UCTXADDR bit */
+    BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1;
+
+    /* If current mode is automatic baud-rate detection */
+    if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
+            == (EUSCI_A_CMSIS(moduleInstance)->CTLW0
+                    & EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE))
+        EUSCI_A_CMSIS(moduleInstance)->TXBUF =
+        EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC;
+    else
+        EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC;
+
+    /* If interrupts are not used, poll for flags */
+    if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS))
+        while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS))
+            ;
+}
+
+uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF;
+}
+
+uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
+{
+    return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF;
+}
+
+void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime)
+{
+    ASSERT(
+            (EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime)
+            || (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime)
+            || (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime)
+            || (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime));
+
+    EUSCI_A_CMSIS(moduleInstance)->CTLW1 =
+            (EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK))
+                    | deglitchTime;
+
+}
+
+void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    uint_fast8_t locMask;
+
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                            | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                            | EUSCI_A_UART_BREAKCHAR_INTERRUPT
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                    | EUSCI_A_UART_STARTBIT_INTERRUPT
+                    | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
+
+    EUSCI_A_CMSIS(moduleInstance)->IE |= locMask;
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                    | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
+    EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask;
+}
+
+void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    uint_fast8_t locMask;
+
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                            | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                            | EUSCI_A_UART_BREAKCHAR_INTERRUPT
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)));
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT
+                    | EUSCI_A_UART_STARTBIT_INTERRUPT
+                    | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT));
+    EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask;
+
+    locMask = (mask
+            & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
+                    | EUSCI_A_UART_BREAKCHAR_INTERRUPT));
+    EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask;
+}
+
+uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
+
+    return EUSCI_A_CMSIS(moduleInstance)->IFG & mask;
+}
+
+uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance)
+{
+    uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance,
+    EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG);
+    uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE;
+
+    if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT;
+    }
+
+    if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT;
+    }
+
+    intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0;
+
+    if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT;
+    }
+
+    if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT))
+    {
+        intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT;
+    }
+
+    return intStatus;
+}
+
+void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
+{
+    ASSERT(
+            !(mask
+                    & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
+                            | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG)));
+
+    //Clear the UART interrupt source.
+    EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask);
+}
+
+void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_A0_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA0);
+        break;
+    case EUSCI_A1_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA1);
+        break;
+#ifdef EUSCI_A2_BASE
+    case EUSCI_A2_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA2);
+        break;
+#endif
+#ifdef EUSCI_A3_BASE
+    case EUSCI_A3_BASE:
+        Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
+        Interrupt_enableInterrupt(INT_EUSCIA3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}
+
+void UART_unregisterInterrupt(uint32_t moduleInstance)
+{
+    switch (moduleInstance)
+    {
+    case EUSCI_A0_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIA0);
+        Interrupt_unregisterInterrupt(INT_EUSCIA0);
+        break;
+    case EUSCI_A1_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIA1);
+        Interrupt_unregisterInterrupt(INT_EUSCIA1);
+        break;
+#ifdef EUSCI_A2_BASE
+    case EUSCI_A2_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIA2);
+        Interrupt_unregisterInterrupt(INT_EUSCIA2);
+        break;
+#endif
+#ifdef EUSCI_A3_BASE
+    case EUSCI_A3_BASE:
+        Interrupt_disableInterrupt(INT_EUSCIA3);
+        Interrupt_unregisterInterrupt(INT_EUSCIA3);
+        break;
+#endif
+    default:
+        ASSERT(false);
+    }
+}

platform/vendor_bsp/TI/MSP432P4xx/uart.h

@@ -0,0 +1,760 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef UART_H_
+#define UART_H_
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <msp.h>
+#include "eusci.h"
+
+#define DEFAULT_SYNC                                    0x00
+#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC             0x55
+
+#define EUSCI_A_UART_NO_PARITY                          0x00
+#define EUSCI_A_UART_ODD_PARITY                         0x01
+#define EUSCI_A_UART_EVEN_PARITY                        0x02
+
+#define EUSCI_A_UART_MSB_FIRST                          EUSCI_A_CTLW0_MSB
+#define EUSCI_A_UART_LSB_FIRST                          0x00
+
+#define EUSCI_A_UART_MODE                               EUSCI_A_CTLW0_MODE_0
+#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE        EUSCI_A_CTLW0_MODE_1
+#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE   EUSCI_A_CTLW0_MODE_2
+#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE  EUSCI_A_CTLW0_MODE_3
+
+#define EUSCI_A_UART_CLOCKSOURCE_SMCLK                  EUSCI_A_CTLW0_SSEL__SMCLK
+#define EUSCI_A_UART_CLOCKSOURCE_ACLK                   EUSCI_A_CTLW0_SSEL__ACLK
+
+#define EUSCI_A_UART_ONE_STOP_BIT                       0x00
+#define EUSCI_A_UART_TWO_STOP_BITS                      EUSCI_A_CTLW0_SPB
+
+#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION   0x01
+#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION  0x00
+
+#define EUSCI_A_UART_RECEIVE_INTERRUPT                  EUSCI_A_IE_RXIE
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT                 EUSCI_A_IE_TXIE
+#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT    EUSCI_A_CTLW0_RXEIE
+#define EUSCI_A_UART_BREAKCHAR_INTERRUPT                EUSCI_A_CTLW0_BRKIE
+#define EUSCI_A_UART_STARTBIT_INTERRUPT                 EUSCI_A_IE_STTIE
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT        EUSCI_B_IE_STPIE
+
+#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG             EUSCI_A_IFG_RXIFG
+#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG            EUSCI_A_IFG_TXIFG
+#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG            EUSCI_A_IFG_STTIFG
+#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG   EUSCI_A_IFG_TXCPTIFG
+
+#define EUSCI_A_UART_LISTEN_ENABLE                      EUSCI_A_STATW_LISTEN
+#define EUSCI_A_UART_FRAMING_ERROR                      EUSCI_A_STATW_FE
+#define EUSCI_A_UART_OVERRUN_ERROR                      EUSCI_A_STATW_OE
+#define EUSCI_A_UART_PARITY_ERROR                       EUSCI_A_STATW_PE
+#define EUSCI_A_UART_BREAK_DETECT                       EUSCI_A_STATW_BRK
+#define EUSCI_A_UART_RECEIVE_ERROR                      EUSCI_A_STATW_RXERR
+#define EUSCI_A_UART_ADDRESS_RECEIVED                   EUSCI_A_STATW_ADDR_IDLE
+#define EUSCI_A_UART_IDLELINE                           EUSCI_A_STATW_ADDR_IDLE
+#define EUSCI_A_UART_BUSY                               EUSCI_A_STATW_BUSY
+
+#define EUSCI_A_UART_DEGLITCH_TIME_2ns                  0x00
+#define EUSCI_A_UART_DEGLITCH_TIME_50ns                 0x0001
+#define EUSCI_A_UART_DEGLITCH_TIME_100ns                0x0002
+#define EUSCI_A_UART_DEGLITCH_TIME_200ns                (0x0001 + 0x0002)
+
+//*****************************************************************************
+//
+//!     ypedef eUSCI_eUSCI_UART_Config
+//! \brief Type definition for \link _eUSCI_UART_Config \endlink
+//!     structure
+//!
+//! \struct _eUSCI_eUSCI_UART_Config
+//! \brief Configuration structure for compare mode in the \b UART module. See
+//!          \link UART_initModule \endlink for parameter
+//!                 documentation.
+//
+//*****************************************************************************
+typedef struct _eUSCI_eUSCI_UART_Config
+{
+    uint_fast8_t selectClockSource;
+    uint_fast16_t clockPrescalar;
+    uint_fast8_t firstModReg;
+    uint_fast8_t secondModReg;
+    uint_fast8_t parity;
+    uint_fast16_t msborLsbFirst;
+    uint_fast16_t numberofStopBits;
+    uint_fast16_t uartMode;
+    uint_fast8_t overSampling;
+} eUSCI_UART_Config;
+
+//*****************************************************************************
+//
+//! Initialization routine for the UART block. The values to be written
+//! into the UCAxBRW and UCAxMCTLW registers should be pre-computed and passed
+//! into the initialization function
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//! \param config Configuration structure for the UART module
+//!
+//! <hr>
+//! <b>Configuration options for \link eUSCI_UART_Config \endlink
+//!         structure.</b>
+//! <hr>
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode.
+//! \param selectClockSource selects Clock source. Valid values are
+//!       - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK
+//!       - \b EUSCI_A_UART_CLOCKSOURCE_ACLK
+//! \param clockPrescalar is the value to be written into UCBRx bits
+//! \param firstModReg  is First modulation stage register setting. This
+//!     value is a pre-calculated value which can be obtained from the Device
+//!     User Guide.This value is written into UCBRFx bits of UCAxMCTLW.
+//! \param secondModReg is Second modulation stage register setting.
+//!     This value is a pre-calculated value which can be obtained from the
+//!     Device User Guide. This value is written into UCBRSx bits of
+//!     UCAxMCTLW.
+//! \param parity is the desired parity. Valid values are
+//!      - \b EUSCI_A_UART_NO_PARITY  [Default Value],
+//!      - \b EUSCI_A_UART_ODD_PARITY,
+//!      - \b EUSCI_A_UART_EVEN_PARITY
+//! \param msborLsbFirst controls direction of receive and transmit shift
+//!     register. Valid values are
+//!      - \b EUSCI_A_UART_MSB_FIRST
+//!      - \b EUSCI_A_UART_LSB_FIRST [Default Value]
+//! \param numberofStopBits indicates one/two STOP bits
+//!      Valid values are
+//!      - \b EUSCI_A_UART_ONE_STOP_BIT [Default Value]
+//!      - \b EUSCI_A_UART_TWO_STOP_BITS
+//! \param uartMode selects the mode of operation
+//!      Valid values are
+//!      - \b EUSCI_A_UART_MODE  [Default Value],
+//!      - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE,
+//!      - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE,
+//!      - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE
+//! \param overSampling indicates low frequency or oversampling baud
+//!      generation
+//!     Valid values are
+//!      - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION
+//!      - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION
+//!
+//! Upon successful initialization of the UART block, this function
+//! will have initialized the module, but the UART block still remains
+//! disabled and must be enabled with UART_enableModule()
+//!
+//! Refer to
+//! <a href="http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430BaudRateConverter/index.html">
+//! this calculator </a> for help on calculating values for the parameters.
+//!
+//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB,
+//! \b UCMODEx, \b UCSYNC bits of \b UCAxCTL0 and \b UCSSELx,
+//! \b UCSWRST bits of \b UCAxCTL1
+//!
+//! \return true or
+//!         STATUS_FAIL of the initialization process
+//
+//*****************************************************************************
+extern bool UART_initModule(uint32_t moduleInstance,
+        const eUSCI_UART_Config *config);
+
+//*****************************************************************************
+//
+//! Transmits a byte from the UART Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param transmitData data to be transmitted from the UART module
+//!
+//! This function will place the supplied data into UART transmit data register
+//! to start transmission
+//!
+//! Modified register is \b UCAxTXBUF
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_transmitData(uint32_t moduleInstance,
+        uint_fast8_t transmitData);
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the UART Module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as  EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! This function reads a byte of data from the UART receive data Register.
+//!
+//! Modified register is \b UCAxRXBUF
+//!
+//! \return Returns the byte received from by the UART module, cast as an
+//! uint8_t.
+//
+//*****************************************************************************
+extern uint8_t UART_receiveData(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Enables the UART block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! This will enable operation of the UART block.
+//!
+//! Modified register is \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_enableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Disables the UART block.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! This will disable operation of the UART block.
+//!
+//! Modified register is \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_disableModule(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Gets the current UART status flags.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the masked interrupt flag status to be returned.
+//!
+//! This returns the status for the UART  module based on which
+//! flag is passed. mask parameter can be either any of the following
+//! selection.
+//! - \b EUSCI_A_UART_LISTEN_ENABLE
+//! - \b EUSCI_A_UART_FRAMING_ERROR
+//! - \b EUSCI_A_UART_OVERRUN_ERROR
+//! - \b EUSCI_A_UART_PARITY_ERROR
+//! - \b eUARTBREAK_DETECT
+//! - \b EUSCI_A_UART_RECEIVE_ERROR
+//! - \b EUSCI_A_UART_ADDRESS_RECEIVED
+//! - \b EUSCI_A_UART_IDLELINE
+//! - \b EUSCI_A_UART_BUSY
+//!
+//! Modified register is \b UCAxSTAT
+//!
+//! \return the masked status flag
+//
+//*****************************************************************************
+extern uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance,
+        uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Sets the UART module in dormant mode
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Puts USCI in sleep mode
+//! Only characters that are preceded by an idle-line or with address bit set
+//! UCRXIFG. In UART mode with automatic baud-rate detection, only the
+//! combination of a break and synch field sets UCRXIFG.
+//!
+//! Modified register is \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_setDormant(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Re-enables UART module from dormant mode
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Not dormant. All received characters set UCRXIFG.
+//!
+//! Modified bits are \b UCDORM of \b UCAxCTL1 register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_resetDormant(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Transmits the next byte to be transmitted marked as address depending on
+//! selected multiprocessor mode
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param transmitAddress is the next byte to be transmitted
+//!
+//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_transmitAddress(uint32_t moduleInstance,
+        uint_fast8_t transmitAddress);
+
+//*****************************************************************************
+//
+//! Transmit break. Transmits a break with the next write to the transmit
+//! buffer. In UART mode with automatic baud-rate detection,
+//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to
+//! generate the required break/synch fields.
+//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer.
+//! Also ensures module is ready for transmitting the next data
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  asEUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Modified register is \b UCAxCTL1, \b UCAxTXBUF
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_transmitBreak(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the RX Buffer of the UART for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Returns the address of the UART RX Buffer. This can be used in conjunction
+//! with the DMA to store the received data directly to memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Returns the address of the TX Buffer of the UART for the DMA module.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! Returns the address of the UART TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Sets the deglitch time
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param deglitchTime is the selected deglitch time
+//!     Valid values are
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_2ns
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_50ns
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_100ns
+//!         - \b EUSCI_A_UART_DEGLITCH_TIME_200ns
+//!
+//!
+//! Returns the address of the UART TX Buffer. This can be used in conjunction
+//! with the DMA to obtain transmitted data directly from memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UART_selectDeglitchTime(uint32_t moduleInstance,
+        uint32_t deglitchTime);
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated UART interrupt sources.  The interrupt flag is first
+//! and then the corresponding interrupt is enabled. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt
+//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive
+//!                             erroneous-character interrupt enable
+//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt
+//!                                           enable
+//!
+//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! Disables the indicated UART interrupt sources.  Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The mask parameter is the logical OR of any of the following:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt
+//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive
+//!                             erroneous-character interrupt enable
+//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt
+//!                                             enable
+//!
+//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current UART interrupt status.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is the masked interrupt flag status to be returned.
+//!        Mask value is the logical OR of any of the following:
+//!        - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG
+//!        - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG
+//!        - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG
+//!        - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG
+//!
+//!
+//! \return The current interrupt status as an ORed bit mask:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
+//
+//*****************************************************************************
+extern uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance,
+        uint8_t mask);
+
+//*****************************************************************************
+//
+//! Gets the current UART interrupt status masked with the enabled interrupts.
+//! This function is useful to call in ISRs to get a list of pending
+//! interrupts that are actually enabled and could have caused
+//! the ISR.
+
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//!
+//! \return The current interrupt status as an ORed bit mask:
+//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag
+//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag
+//
+//*****************************************************************************
+extern uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance);
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode
+//! \param mask is a bit mask of the interrupt sources to be cleared.
+//!
+//! The UART interrupt source is cleared, so that it no longer asserts.
+//! The highest interrupt flag is automatically cleared when an interrupt vector
+//! generator is used.
+//!
+//! The mask parameter has the same definition as the mask parameter to
+//! EUSCI_A_UART_enableInterrupt().
+//!
+//! Modified register is \b UCAxIFG
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for UART interrupts.
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! timer capture compare interrupt occurs.
+//!
+//! This function registers the handler to be called when an UART
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific UART interrupts must be enabled
+//! via UART_enableInterrupt().  It is the interrupt handler's responsibility to
+//! clear the interrupt source via UART_clearInterruptFlag().
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_registerInterrupt(uint32_t moduleInstance,
+        void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the UART module
+//!
+//! \param moduleInstance is the instance of the eUSCI A (UART) module.
+//! Valid parameters vary from part to part, but can include:
+//!         - \b EUSCI_A0_BASE
+//!         - \b EUSCI_A1_BASE
+//!         - \b EUSCI_A2_BASE
+//!         - \b EUSCI_A3_BASE
+//!  <br> It is important to note that for eUSCI modules, only "A" modules such
+//!  as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the
+//!  UART mode.
+//!
+//! This function unregisters the handler to be called when timer
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void UART_unregisterInterrupt(uint32_t moduleInstance);
+
+/* Backwards Compatibility Layer */
+#define EUSCI_A_UART_transmitData UART_transmitData
+#define EUSCI_A_UART_receiveData UART_receiveData
+#define EUSCI_A_UART_enableInterrupt UART_enableInterrupt
+#define EUSCI_A_UART_disableInterrupt UART_disableInterrupt
+#define EUSCI_A_UART_getInterruptStatus UART_getInterruptStatus
+#define EUSCI_A_UART_clearInterruptFlag UART_clearInterruptFlag
+#define EUSCI_A_UART_enable UART_enableModule
+#define EUSCI_A_UART_disable UART_disableModule
+#define EUSCI_A_UART_queryStatusFlags UART_queryStatusFlags
+#define EUSCI_A_UART_setDormant UART_setDormant
+#define EUSCI_A_UART_resetDormant UART_resetDormant
+#define EUSCI_A_UART_transmitAddress UART_transmitAddress
+#define EUSCI_A_UART_transmitBreak UART_transmitBreak
+#define EUSCI_A_UART_getReceiveBufferAddressForDMA UART_getReceiveBufferAddressForDMA
+#define EUSCI_A_UART_getTransmitBufferAddressForDMA UART_getTransmitBufferAddressForDMA
+#define EUSCI_A_UART_selectDeglitchTime UART_selectDeglitchTime
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif /* UART_H_ */

platform/vendor_bsp/TI/MSP432P4xx/wdt_a.c

@@ -0,0 +1,119 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+/* Standard Includes */
+#include <stdint.h>
+
+/* DriverLib Includes */
+#include <driverlib.h>
+#include <debug.h>
+
+
+void WDT_A_holdTimer(void)
+{
+    //Set Hold bit
+    uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_HOLD);
+
+    WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
+}
+
+void WDT_A_startTimer(void)
+{
+    //Reset Hold bit
+    uint8_t newWDTStatus = (WDT_A->CTL & ~(WDT_A_CTL_HOLD));
+
+    WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
+}
+
+void WDT_A_clearTimer(void)
+{
+    //Set Counter Clear bit
+    uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_CNTCL);
+
+    WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus;
+}
+
+void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockIterations)
+{
+    WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD +
+            clockSelect + clockIterations;
+}
+
+void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockIterations)
+{
+
+    WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD + WDT_A_CTL_TMSEL
+            + clockSelect + clockIterations;
+}
+
+void WDT_A_setPasswordViolationReset(uint_fast8_t resetType)
+{
+    SysCtl_setWDTPasswordViolationResetType(resetType);
+}
+
+void WDT_A_setTimeoutReset(uint_fast8_t resetType)
+{
+    SysCtl_setWDTTimeoutResetType(resetType);
+}
+
+void WDT_A_registerInterrupt(void (*intHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    Interrupt_registerInterrupt(INT_WDT_A, intHandler);
+
+    //
+    // Enable the system control interrupt.
+    //
+    Interrupt_enableInterrupt (INT_WDT_A);
+}
+
+void WDT_A_unregisterInterrupt(void)
+{
+    //
+    // Disable the interrupt.
+    //
+    Interrupt_disableInterrupt (INT_WDT_A);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    Interrupt_unregisterInterrupt(INT_WDT_A);
+}
+

platform/vendor_bsp/TI/MSP432P4xx/wdt_a.h

@@ -0,0 +1,306 @@
+/*
+ * -------------------------------------------
+ *    MSP432 DriverLib - v3_40_00_10 
+ * -------------------------------------------
+ *
+ * --COPYRIGHT--,BSD,BSD
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * --/COPYRIGHT--*/
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+//*****************************************************************************
+//
+//! \addtogroup wdt_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <msp.h>
+#include <stdint.h>
+#include "sysctl.h"
+
+#define WDT_A_HARD_RESET SYSCTL_HARD_RESET
+#define WDT_A_SOFT_RESET SYSCTL_SOFT_RESET
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the clockSelect parameter for
+// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
+//
+//*****************************************************************************
+#define WDT_A_CLOCKSOURCE_SMCLK                                     (WDT_A_CTL_SSEL_0)
+#define WDT_A_CLOCKSOURCE_ACLK                                      (WDT_A_CTL_SSEL_1)
+#define WDT_A_CLOCKSOURCE_VLOCLK                                    (WDT_A_CTL_SSEL_2)
+#define WDT_A_CLOCKSOURCE_XCLK                                      (WDT_A_CTL_SSEL_3)
+#define WDT_A_CLOCKSOURCE_BCLK                                      (WDT_A_CTL_SSEL_4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the clockDivider parameter
+// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit().
+//
+//*****************************************************************************
+#define WDT_A_CLOCKDIVIDER_2G                                         (WDT_A_CTL_IS_0)
+#define WDT_A_CLOCKDIVIDER_128M                                       (WDT_A_CTL_IS_1)
+#define WDT_A_CLOCKDIVIDER_8192K                                      (WDT_A_CTL_IS_2)
+#define WDT_A_CLOCKDIVIDER_512K                                       (WDT_A_CTL_IS_3)
+#define WDT_A_CLOCKDIVIDER_32K                                        (WDT_A_CTL_IS_4)
+#define WDT_A_CLOCKDIVIDER_8192                                       (WDT_A_CTL_IS_5)
+#define WDT_A_CLOCKDIVIDER_512                                        (WDT_A_CTL_IS_6)
+#define WDT_A_CLOCKDIVIDER_64                                         (WDT_A_CTL_IS_7)
+#define WDT_A_CLOCKITERATIONS_2G    WDT_A_CLOCKDIVIDER_2G
+#define WDT_A_CLOCKITERATIONS_128M  WDT_A_CLOCKDIVIDER_128M
+#define WDT_A_CLOCKITERATIONS_8192K WDT_A_CLOCKDIVIDER_8192K
+#define WDT_A_CLOCKITERATIONS_512K  WDT_A_CLOCKDIVIDER_512K
+#define WDT_A_CLOCKITERATIONS_32K   WDT_A_CLOCKDIVIDER_32K
+#define WDT_A_CLOCKITERATIONS_8192  WDT_A_CLOCKDIVIDER_8192
+#define WDT_A_CLOCKITERATIONS_512   WDT_A_CLOCKDIVIDER_512
+#define WDT_A_CLOCKITERATIONS_64    WDT_A_CLOCKDIVIDER_64
+
+/* Forward compatibility layer */
+#ifdef __MCU_HAS_SYSCTL_A__
+
+#define SysCtl_setWDTPasswordViolationResetType SysCtl_A_setWDTPasswordViolationResetType
+#define SysCtl_setWDTTimeoutResetType SysCtl_A_setWDTTimeoutResetType
+
+#endif
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Holds the Watchdog Timer.
+//!
+//! This function stops the watchdog timer from running. This way no interrupt
+//! or PUC is asserted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_holdTimer(void);
+
+//*****************************************************************************
+//
+//! Starts the Watchdog Timer.
+//!
+//! This function starts the watchdog timer functionality to start counting.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_startTimer(void);
+
+//*****************************************************************************
+//
+//! Clears the timer counter of the Watchdog Timer.
+//!
+//! This function clears the watchdog timer count to 0x0000h. This function
+//! is used to "service the dog" when operating in watchdog mode.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_clearTimer(void);
+
+//*****************************************************************************
+//
+//! Sets the clock source for the Watchdog Timer in watchdog mode.
+//!
+//! \param clockSelect is the clock source that the watchdog timer will use.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
+//!        - \b WDT_A_CLOCKSOURCE_ACLK
+//!        - \b WDT_A_CLOCKSOURCE_VLOCLK
+//!        - \b WDT_A_CLOCKSOURCE_BCLK
+//! \param clockIterations is the number of clock iterations for a watchdog
+//!         timeout.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKITERATIONS_2G [Default]
+//!        - \b WDT_A_CLOCKITERATIONS_128M
+//!        - \b WDT_A_CLOCKITERATIONS_8192K
+//!        - \b WDT_A_CLOCKITERATIONS_512K
+//!        - \b WDT_A_CLOCKITERATIONS_32K
+//!        - \b WDT_A_CLOCKITERATIONS_8192
+//!        - \b WDT_A_CLOCKITERATIONS_512
+//!        - \b WDT_A_CLOCKITERATIONS_64
+//!
+//! This function sets the watchdog timer in watchdog mode, which will cause a
+//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a
+//! call to WDT_A_resetTimer() before the timer runs out.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockDivider);
+
+//*****************************************************************************
+//
+//! Sets the clock source for the Watchdog Timer in timer interval mode.
+//!
+//! \param clockSelect is the clock source that the watchdog timer will use.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKSOURCE_SMCLK [Default]
+//!        - \b WDT_A_CLOCKSOURCE_ACLK
+//!        - \b WDT_A_CLOCKSOURCE_VLOCLK
+//!        - \b WDT_A_CLOCKSOURCE_BCLK
+//! \param clockIterations is the number of clock iterations for a watchdog
+//!         interval.
+//!        Valid values are
+//!        - \b WDT_A_CLOCKITERATIONS_2G [Default]
+//!        - \b WDT_A_CLOCKITERATIONS_128M
+//!        - \b WDT_A_CLOCKITERATIONS_8192K
+//!        - \b WDT_A_CLOCKITERATIONS_512K
+//!        - \b WDT_A_CLOCKITERATIONS_32K
+//!        - \b WDT_A_CLOCKITERATIONS_8192
+//!        - \b WDT_A_CLOCKITERATIONS_512
+//!        - \b WDT_A_CLOCKITERATIONS_64
+//!
+//! This function sets the watchdog timer as timer interval mode, which will
+//! assert an interrupt without causing a PUC.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void WDT_A_initIntervalTimer(uint_fast8_t clockSelect,
+        uint_fast8_t clockDivider);
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the watchdog interrupt.
+//!
+//! \param intHandler is a pointer to the function to be called when the
+//! watchdog interrupt occurs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void WDT_A_registerInterrupt(void (*intHandler)(void));
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the watchdog.
+//!
+//! This function unregisters the handler to be called when a watchdog
+//! interrupt occurs.  This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa Interrupt_registerInterrupt() for important information about
+//! registering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+extern void WDT_A_unregisterInterrupt(void);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog password violation
+//! occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!     - \b WDT_A_HARD_RESET
+//!     - \b WDT_A_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void WDT_A_setPasswordViolationReset(uint_fast8_t resetType);
+
+//*****************************************************************************
+//
+//! Sets the type of RESET that happens when a watchdog timeout occurs.
+//!
+//! \param resetType The type of reset to set
+//!
+//! The \e resetType parameter must be only one of the following values:
+//!     - \b WDT_A_HARD_RESET
+//!     - \b WDT_A_SOFT_RESET
+//!
+//! \return None.
+//
+//
+//*****************************************************************************
+extern void WDT_A_setTimeoutReset(uint_fast8_t resetType);
+
+/* Defines for future devices that might have multiple instances */
+#define WDT_A_holdTimerMultipleTimer(a)  WDT_A_holdTimer()
+#define WDT_A_startTimerMultipleTimer(a) WDT_A_startTimer()
+#define WDT_A_resetTimerMultipleTimer(a) WDT_A_clearTimer()
+#define WDT_A_initWatchdogTimerMultipleTimer(a,b,c) WDT_A_initWatchdogTimer(b,c)
+#define WDT_A_initIntervalTimerMultipleTimer(a,b,c) WDT_A_initIntervalTimer(b,c)
+#define WDT_A_registerInterruptMultipleTimer(a,b) WDT_A_registerInterrupt(b)
+#define WDT_A_unregisterInterruptMultipleTimer(a) WDT_A_unregisterInterrupt()
+
+/* Backwards compatibility layer */
+#define WDT_A_hold WDT_A_holdTimerMultipleTimer
+#define WDT_A_start WDT_A_startTimerMultipleTimer
+#define WDT_A_resetTimer WDT_A_resetTimerMultipleTimer
+#define WDT_A_watchdogTimerInit WDT_A_initWatchdogTimerMultipleTimer
+#define WDT_A_intervalTimerInit WDT_A_initIntervalTimerMultipleTimer
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+#endif // __WATCHDOG_H__

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/CMSIS/GD/GD32F20x/Include/gd32f20x.h

@@ -0,0 +1,273 @@
+/*!
+    \file  gd32f20x.h
+    \brief general definitions for GD32F20x
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_H
+#define GD32F20X_H
+
+#ifdef cplusplus
+ extern "C" {
+#endif 
+
+/* define GD32F20x */
+#if !defined (GD32F20X_CL)
+ #error "Please select first the target gd32f20x device used in your application (in gd32f20x.h file)"
+#endif /* GD32F20X */
+
+/* define value of high speed crystal oscillator (HXTAL) in Hz */
+#if !defined  HXTAL_VALUE    
+#ifdef GD32F20X_CL   
+#define HXTAL_VALUE    ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
+#endif /* HXTAL_VALUE */
+#endif /* high speed crystal oscillator value */
+ 
+/* define startup timeout value of high speed crystal oscillator (HXTAL) */
+#if !defined  (HXTAL_STARTUP_TIMEOUT)
+#define HXTAL_STARTUP_TIMEOUT   ((uint16_t)0xFFFF)
+#endif /* high speed crystal oscillator startup timeout */
+
+/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
+#if !defined  (IRC8M_VALUE) 
+#define IRC8M_VALUE  ((uint32_t)8000000)
+#endif /* internal 8MHz RC oscillator value */
+
+/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
+#if !defined  (IRC8M_STARTUP_TIMEOUT)
+#define IRC8M_STARTUP_TIMEOUT   ((uint16_t)0x0500)
+#endif /* internal 8MHz RC oscillator startup timeout */
+
+/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
+#if !defined  (IRC40K_VALUE) 
+#define IRC40K_VALUE  ((uint32_t)40000)
+#endif /* internal 40KHz RC oscillator value */
+
+/* define value of low speed crystal oscillator (LXTAL)in Hz */
+#if !defined  (LXTAL_VALUE) 
+#define LXTAL_VALUE  ((uint32_t)32768)
+#endif /* low speed crystal oscillator value */
+
+/* GD32F20x firmware library version number V2.0 */
+#define __GD32F20x_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version     */
+#define __GD32F20x_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version     */
+#define __GD32F20x_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version     */
+#define __GD32F20x_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __GD32F20x_STDPERIPH_VERSION        ((__GD32F20x_STDPERIPH_VERSION_MAIN << 24)\
+                                            |(__GD32F20x_STDPERIPH_VERSION_SUB1 << 16)\
+                                            |(__GD32F20x_STDPERIPH_VERSION_SUB2 << 8)\
+                                            |(__GD32F20x_STDPERIPH_VERSION_RC))
+
+/* configuration of the Cortex-M3 processor and core peripherals */
+#define __MPU_PRESENT             0        /*!< GD32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS          4        /*!< GD32F20X uses 4 bits for the Priority levels        */
+#define __VENDOR_SYSTICKCONFIG    0        /*!< set to 1 if different systick config is used        */
+
+/* define interrupt number */
+typedef enum IRQn
+{
+    /* Cortex-M3 processor exceptions numbers */
+    NonMaskableInt_IRQn         = -14,    /*!< 2 non maskable interrupt                                              */
+    MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 memory management interrupt                               */
+    BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 bus fault interrupt                                       */
+    UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 usage fault interrupt                                     */
+    SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV call interrupt                                        */
+    DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 debug monitor interrupt                                  */
+    PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 pend SV interrupt                                        */
+    SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 system tick interrupt                                    */
+    /* interruput numbers */
+    WWDGT_IRQn                  = 0,      /*!< WWDGT interrupt                                                       */
+    LVD_IRQn                    = 1,      /*!< LVD from EXTI line interrupt                                          */
+    TAMPER_IRQn                 = 2,      /*!< tamper interrupt                                                      */
+    RTC_IRQn                    = 3,      /*!< RTC global interrupt                                                  */
+    FMC_IRQn                    = 4,      /*!< FMC global interrupt                                                  */
+    RCU_IRQn                    = 5,      /*!< RCU global interrupt                                                  */
+    EXTI0_IRQn                  = 6,      /*!< EXTI line0 interrupt                                                  */
+    EXTI1_IRQn                  = 7,      /*!< EXTI line1 interrupt                                                  */
+    EXTI2_IRQn                  = 8,      /*!< EXTI line2 interrupt                                                  */
+    EXTI3_IRQn                  = 9,      /*!< EXTI line3 interrupt                                                  */
+    EXTI4_IRQn                  = 10,     /*!< EXTI line4 interrupt                                                  */
+    DMA0_Channel0_IRQn          = 11,     /*!< DMA0 channel 0 global interrupt                                       */
+    DMA0_Channel1_IRQn          = 12,     /*!< DMA0 channel 1 global interrupt                                       */
+    DMA0_Channel2_IRQn          = 13,     /*!< DMA0 channel 2 global interrupt                                       */
+    DMA0_Channel3_IRQn          = 14,     /*!< DMA0 channel 3 global interrupt                                       */
+    DMA0_Channel4_IRQn          = 15,     /*!< DMA0 channel 4 global interrupt                                       */
+    DMA0_Channel5_IRQn          = 16,     /*!< DMA0 channel 5 global interrupt                                       */
+    DMA0_Channel6_IRQn          = 17,     /*!< DMA0 channel 6 global interrupt                                       */
+    ADC0_1_IRQn                 = 18,     /*!< ADC0 and ADC1 global interrupts                                       */
+    CAN0_TX_IRQn                = 19,     /*!< CAN0 TX interrupt                                                     */
+    CAN0_RX0_IRQn               = 20,     /*!< CAN0 RX0 interrupt                                                    */
+    CAN0_RX1_IRQn               = 21,     /*!< CAN0 RX1 interrupt                                                    */
+    CAN0_EWMC_IRQn              = 22,     /*!< CAN0 EWMC interrupt                                                   */
+    EXTI5_9_IRQn                = 23,     /*!< EXTI[9:5] interrupts                                                  */
+    TIMER0_BRK_TIMER8_IRQn      = 24,     /*!< TIMER0 break interrupt and TIMER8 global interrupt                    */
+    TIMER0_UP_TIMER9_IRQn       = 25,     /*!< TIMER0 update Interrupt and TIMER9 global interrupt                   */
+    TIMER0_TRG_CMT_TIMER10_IRQn = 26,     /*!< TIMER0 trigger and commutation interrupt and TIMER10 global interrupt */
+    TIMER0_Channel_IRQn         = 27,     /*!< TIMER0 channel capture compare interrupt                                      */
+    TIMER1_IRQn                 = 28,     /*!< TIMER1 global interrupt                                               */
+    TIMER2_IRQn                 = 29,     /*!< TIMER2 global interrupt                                               */
+    TIMER3_IRQn                 = 30,     /*!< TIMER3 global interrupt                                               */
+    I2C0_EV_IRQn                = 31,     /*!< I2C0 event interrupt                                                  */
+    I2C0_ER_IRQn                = 32,     /*!< I2C0 error interrupt                                                  */
+    I2C1_EV_IRQn                = 33,     /*!< I2C1 event interrupt                                                  */
+    I2C1_ER_IRQn                = 34,     /*!< I2C1 error interrupt                                                  */
+    SPI0_IRQn                   = 35,     /*!< SPI0 global interrupt                                                 */
+    SPI1_IRQn                   = 36,     /*!< SPI1 global interrupt                                                 */
+    USART0_IRQn                 = 37,     /*!< USART0 global interrupt                                               */
+    USART1_IRQn                 = 38,     /*!< USART1 global interrupt                                               */
+    USART2_IRQn                 = 39,     /*!< USART2 global interrupt                                               */
+    EXTI10_15_IRQn              = 40,     /*!< EXTI[15:10] interrupts                                                */
+    RTC_Alarm_IRQn              = 41,     /*!< RTC alarm from EXTI line interrupt                                    */
+    USBFS_WKUP_IRQn             = 42,     /*!< USBFS wakeUp from EXTI line interrupt                                 */
+    TIMER7_BRK_TIMER11_IRQn     = 43,     /*!< TIMER7 break interrupt and TIMER11 global interrupt                   */
+    TIMER7_UP_TIMER12_IRQn      = 44,     /*!< TIMER7 update interrupt and TIMER12 global interrupt                  */
+    TIMER7_TRG_CMT_TIMER13_IRQn = 45,     /*!< TIMER7 trigger and commutation interrupt and TIMER13 global interrupt */
+    TIMER7_Channel_IRQn         = 46,     /*!< TIMER7 Channel Capture Compare Interrupt                                      */
+    ADC2_IRQn                   = 47,     /*!< ADC2 global interrupt                                                 */
+    EXMC_IRQn                   = 48,     /*!< EXMC global interrupt                                                 */
+    SDIO_IRQn                   = 49,     /*!< SDIO global interrupt                                                 */
+    TIMER4_IRQn                 = 50,     /*!< TIMER4 global interrupt                                               */
+    SPI2_IRQn                   = 51,     /*!< SPI2 global interrupt                                                 */
+    UART3_IRQn                  = 52,     /*!< UART3 global interrupt                                                */
+    UART4_IRQn                  = 53,     /*!< UART4 global interrupt                                                */
+    TIMER5_IRQn                 = 54,     /*!< TIMER5 global interrupt                                               */
+    TIMER6_IRQn                 = 55,     /*!< TIMER6 global interrupt                                               */
+    DMA1_Channel0_IRQn          = 56,     /*!< DMA1 Channel 0 global interrupt                                       */
+    DMA1_Channel1_IRQn          = 57,     /*!< DMA1 Channel 1 global interrupt                                       */
+    DMA1_Channel2_IRQn          = 58,     /*!< DMA1 Channel 2 global interrupt                                       */
+    DMA1_Channel3_IRQn          = 59,     /*!< DMA1 Channel 3 global interrupt                                       */
+    DMA1_Channel4_IRQn          = 60,     /*!< DMA1 Channel 4 global interrupt                                       */
+    ENET_IRQn                   = 61,     /*!< ENET global interrupt                                                 */
+    ENET_WKUP_IRQn              = 62,     /*!< ENET wakeup through EXTI line interrupt                               */
+    CAN1_TX_IRQn                = 63,     /*!< CAN1 TX interrupt                                                     */
+    CAN1_RX0_IRQn               = 64,     /*!< CAN1 RX0 interrupt                                                    */
+    CAN1_RX1_IRQn               = 65,     /*!< CAN1 RX1 interrupt                                                    */
+    CAN1_EWMC_IRQn              = 66,     /*!< CAN1 EWMC interrupt                                                   */
+    USBFS_IRQn                  = 67,      /*!< USBFS global interrupt                                               */
+    DMA1_Channel5_IRQn          = 69,      /*!< DMA1 Channel 5 global interrupt                                      */
+    DMA1_Channel6_IRQn          = 70,      /*!< DMA1 Channel 6 global interrupt                                      */
+    USART5_IRQn                 = 71,      /*!< USART5 global interrupt                                              */
+    I2C2_EV_IRQn                = 72,      /*!< I2C2 event interrupt                                                 */
+    I2C2_ER_IRQn                = 73,      /*!< I2C2 error interrupt                                                 */
+    DCI_IRQn                    = 78,      /*!< DCI global interrupt                                                 */
+    CAU_IRQn                    = 79,      /*!< CAU global interrupt                                                 */
+    HAU_TRNG_IRQn               = 80,      /*!< HAU or TRNG global interrupt                                         */
+    UART6_IRQn                  = 82,      /*!< UART6 global interrupt                                               */
+    UART7_IRQn                  = 83,      /*!< UART7 global interrupt                                               */
+    TLI_IRQn                    = 88,      /*!< TLI global interrupt                                                 */
+    TLI_ER_IRQn                 = 89       /*!< TLI global error interrupt                                           */
+} IRQn_Type;
+
+/* includes */
+#include "core_cm3.h"
+#include "system_gd32f20x.h"
+#include <stdint.h>
+
+/* enum definitions */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+typedef enum {RESET = 0, SET = !RESET} FlagStatus;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
+
+/* bit operations */
+#define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
+#define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
+#define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))
+#define BIT(x)                       ((uint32_t)((uint32_t)0x01U<<(x)))
+#define BITS(start, end)             ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 
+#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
+
+/* main flash and SRAM memory map */
+#define FLASH_BASE            ((uint32_t)0x08000000U)        /*!< main FLASH base address                         */
+#define SRAM_BASE             ((uint32_t)0x20000000U)        /*!< SRAM base address                               */
+#define OB_BASE               ((uint32_t)0x1FFFF800U)        /*!< OB base address                                 */
+#define SRAM_BB_BASE          ((uint32_t)0x22000000)         /*!< SRAM base address in the bit-band region        */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000)         /*!< Peripheral base address in the bit-band region  */
+#define DBG_BASE              ((uint32_t)0xE0042000U)        /*!< DBG base address                                */
+#define EXMC_BASE             ((uint32_t)0xA0000000U)        /*!< EXMC register base address                      */
+
+/* peripheral memory map */
+#define APB1_BUS_BASE         ((uint32_t)0x40000000U)        /*!< apb1 base address                               */
+#define APB2_BUS_BASE         ((uint32_t)0x40010000U)        /*!< apb2 base address                               */
+#define AHB1_BUS_BASE         ((uint32_t)0x40018000U)        /*!< ahb1 base address                               */
+#define AHB2_BUS_BASE         ((uint32_t)0x50000000U)        /*!< ahb2 base address                               */
+
+/* advanced peripheral bus 1 memory map */
+#define TIMER_BASE            (APB1_BUS_BASE + 0x00000000U)  /*!< TIMER base address                              */
+#define RTC_BASE              (APB1_BUS_BASE + 0x00002800U)  /*!< RTC base address                                */
+#define WWDGT_BASE            (APB1_BUS_BASE + 0x00002C00U)  /*!< WWDGT base address                              */
+#define FWDGT_BASE            (APB1_BUS_BASE + 0x00003000U)  /*!< FWDGT base address                              */
+#define SPI_BASE              (APB1_BUS_BASE + 0x00003800U)  /*!< SPI base address                                */
+#define USART_BASE            (APB1_BUS_BASE + 0x00004400U)  /*!< USART base address                              */
+#define I2C_BASE              (APB1_BUS_BASE + 0x00005400U)  /*!< I2C base address                                */
+#define CAN_BASE              (APB1_BUS_BASE + 0x00006400U)  /*!< CAN base address                                */
+#define BKP_BASE              (APB1_BUS_BASE + 0x00006C00U)  /*!< BKP base address                                */
+#define PMU_BASE              (APB1_BUS_BASE + 0x00007000U)  /*!< PMU base address                                */
+#define DAC_BASE              (APB1_BUS_BASE + 0x00007400U)  /*!< DAC base address                                */
+
+/* advanced peripheral bus 2 memory map */
+#define AFIO_BASE             (APB2_BUS_BASE + 0x00000000U)  /*!< AFIO base address                               */
+#define EXTI_BASE             (APB2_BUS_BASE + 0x00000400U)  /*!< EXTI base address                               */
+#define GPIO_BASE             (APB2_BUS_BASE + 0x00000800U)  /*!< GPIO base address                               */
+#define ADC_BASE              (APB2_BUS_BASE + 0x00002400U)  /*!< ADC base address                                */
+#define TLI_BASE              (APB2_BUS_BASE + 0x00006800U)  /*!< TLI base address                                */
+
+/* advanced high performance bus 1 memory map */
+#define SDIO_BASE             (AHB1_BUS_BASE + 0x00000000U)  /*!< SDIO base address                               */
+#define DMA_BASE              (AHB1_BUS_BASE + 0x00008000U)  /*!< DMA base address                                */
+#define RCU_BASE              (AHB1_BUS_BASE + 0x00009000U)  /*!< RCU base address                                */
+#define FMC_BASE              (AHB1_BUS_BASE + 0x0000A000U)  /*!< FMC base address                                */
+#define CRC_BASE              (AHB1_BUS_BASE + 0x0000B000U)  /*!< CRC base address                                */
+#define ENET_BASE             (AHB1_BUS_BASE + 0x00010000U)  /*!< ENET base address                               */
+
+/* advanced high performance bus 2 memory map */
+#define USBFS_BASE            (AHB2_BUS_BASE + 0x00000000U)  /*!< USBFS base address                              */
+#define DCI_BASE              (AHB2_BUS_BASE + 0x00050000U)  /*!< DCI base address                                */
+#define CAU_BASE              (AHB2_BUS_BASE + 0x00060000U)  /*!< CAU base address                                */
+#define HAU_BASE              (AHB2_BUS_BASE + 0x00060400U)  /*!< HAU base address                                */
+#define TRNG_BASE             (AHB2_BUS_BASE + 0x00060800U)  /*!< TRNG base address                               */
+
+/* define marco USE_STDPERIPH_DRIVER */
+#if !defined  USE_STDPERIPH_DRIVER
+#define USE_STDPERIPH_DRIVER
+#endif 
+#ifdef USE_STDPERIPH_DRIVER
+#include "gd32f20x_libopt.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+#ifdef cplusplus
+}
+#endif
+#endif 

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/CMSIS/GD/GD32F20x/Include/system_gd32f20x.h

@@ -0,0 +1,58 @@
+/*!
+    \file  system_gd32f20x.h
+    \brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for
+           GD32F20x Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32F20X_H
+#define SYSTEM_GD32F20X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit (void);
+/* update the SystemCoreClock with current core clock retrieved from cpu registers */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32F20X_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/CMSIS/GD/GD32F20x/Source/ARM/startup_gd32f20x_cl.s

@@ -0,0 +1,437 @@
+;/*!
+;    \file  startup_gd32f20x_cl.s
+;    \brief start up file
+
+;    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+;    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+;    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+;*/
+
+;/*
+;    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+;    All rights reserved.
+
+;    Redistribution and use in source and binary forms, with or without modification, 
+;are permitted provided that the following conditions are met:
+
+;    1. Redistributions of source code must retain the above copyright notice, this 
+;       list of conditions and the following disclaimer.
+;    2. Redistributions in binary form must reproduce the above copyright notice, 
+;       this list of conditions and the following disclaimer in the documentation 
+;       and/or other materials provided with the distribution.
+;    3. Neither the name of the copyright holder nor the names of its contributors 
+;       may be used to endorse or promote products derived from this software without 
+;       specific prior written permission.
+
+;    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+;OF SUCH DAMAGE.
+;*/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size          EQU     0x00002000
+
+                    AREA    STACK, NOINIT, READWRITE, ALIGN = 3
+Stack_Mem           SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size           EQU     0x00002000
+
+                    AREA    HEAP, NOINIT, READWRITE, ALIGN = 3
+__heap_base
+Heap_Mem            SPACE   Heap_Size
+__heap_limit
+
+
+                    PRESERVE8
+                    THUMB
+
+;                   /* reset Vector Mapped to at Address 0 */
+                    AREA    RESET, DATA, READONLY
+                    EXPORT  __Vectors
+                    EXPORT  __Vectors_End
+                    EXPORT  __Vectors_Size
+
+__Vectors           DCD     __initial_sp                      ; Top of Stack
+                    DCD     Reset_Handler                     ; Reset Handler
+                    DCD     NMI_Handler                       ; NMI Handler
+                    DCD     HardFault_Handler                 ; Hard Fault Handler
+                    DCD     MemManage_Handler                 ; MPU Fault Handler
+                    DCD     BusFault_Handler                  ; Bus Fault Handler
+                    DCD     UsageFault_Handler                ; Usage Fault Handler
+                    DCD     0                                 ; Reserved
+                    DCD     0                                 ; Reserved
+                    DCD     0                                 ; Reserved
+                    DCD     0                                 ; Reserved
+                    DCD     SVC_Handler                       ; SVCall Handler
+                    DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                    DCD     0                                 ; Reserved
+                    DCD     PendSV_Handler                    ; PendSV Handler
+                    DCD     SysTick_Handler                   ; SysTick Handler
+
+;                   /* external interrupts handler */
+                    DCD     WWDGT_IRQHandler                  ; 16:Window Watchdog Timer
+                    DCD     LVD_IRQHandler                    ; 17:LVD through EXTI Line detect
+                    DCD     TAMPER_IRQHandler                 ; 18:Tamper Interrupt   
+                    DCD     RTC_IRQHandler                    ; 19:RTC through EXTI Line
+                    DCD     FMC_IRQHandler                    ; 20:FMC
+                    DCD     RCU_IRQHandler                    ; 21:RCU
+                    DCD     EXTI0_IRQHandler                  ; 22:EXTI Line 0
+                    DCD     EXTI1_IRQHandler                  ; 23:EXTI Line 1
+                    DCD     EXTI2_IRQHandler                  ; 24:EXTI Line 2
+                    DCD     EXTI3_IRQHandler                  ; 25:EXTI Line 3
+                    DCD     EXTI4_IRQHandler                  ; 26:EXTI Line 4
+                    DCD     DMA0_Channel0_IRQHandler          ; 27:DMA0 Channel 0
+                    DCD     DMA0_Channel1_IRQHandler          ; 28:DMA0 Channel 1
+                    DCD     DMA0_Channel2_IRQHandler          ; 29:DMA0 Channel 2
+                    DCD     DMA0_Channel3_IRQHandler          ; 30:DMA0 Channel 3
+                    DCD     DMA0_Channel4_IRQHandler          ; 31:DMA0 Channel 4
+                    DCD     DMA0_Channel5_IRQHandler          ; 32:DMA0 Channel 5 
+                    DCD     DMA0_Channel6_IRQHandler          ; 33:DMA0 Channel 6
+                    DCD     ADC0_1_IRQHandler                 ; 34:ADC0 and ADC1
+                    DCD     CAN0_TX_IRQHandler                ; 35:CAN0 TX
+                    DCD     CAN0_RX0_IRQHandler               ; 36:CAN0 RX0
+                    DCD     CAN0_RX1_IRQHandler               ; 37:CAN0 RX1
+                    DCD     CAN0_EWMC_IRQHandler              ; 38:CAN0 EWMC
+                    DCD     EXTI5_9_IRQHandler                ; 39:EXTI Line 5 to EXTI Line 9
+                    DCD     TIMER0_BRK_TIMER8_IRQHandler      ; 40:TIMER0 Break and TIMER8 global
+                    DCD     TIMER0_UP_TIMER9_IRQHandler       ; 41:TIMER0 Update and TIMER9 global
+                    DCD     TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global
+                    DCD     TIMER0_Channel_IRQHandler         ; 43:TIMER0 Channel Capture Compare
+                    DCD     TIMER1_IRQHandler                 ; 44:TIMER1
+                    DCD     TIMER2_IRQHandler                 ; 45:TIMER2
+                    DCD     TIMER3_IRQHandler                 ; 46:TIMER3
+                    DCD     I2C0_EV_IRQHandler                ; 47:I2C0 Event
+                    DCD     I2C0_ER_IRQHandler                ; 48:I2C0 Error
+                    DCD     I2C1_EV_IRQHandler                ; 49:I2C1 Event
+                    DCD     I2C1_ER_IRQHandler                ; 50:I2C1 Error
+                    DCD     SPI0_IRQHandler                   ; 51:SPI0
+                    DCD     SPI1_IRQHandler                   ; 52:SPI1
+                    DCD     USART0_IRQHandler                 ; 53:USART0
+                    DCD     USART1_IRQHandler                 ; 54:USART1
+                    DCD     USART2_IRQHandler                 ; 55:USART2
+                    DCD     EXTI10_15_IRQHandler              ; 56:EXTI Line 10 to EXTI Line 15
+                    DCD     RTC_Alarm_IRQHandler              ; 57:RTC Alarm through EXTI Line
+                    DCD     USBFS_WKUP_IRQHandler             ; 58:USBFS WakeUp from suspend through EXTI Line
+                    DCD     TIMER7_BRK_TIMER11_IRQHandler     ; 59:TIMER7 Break Interrupt and TIMER11 global
+                    DCD     TIMER7_UP_TIMER12_IRQHandler      ; 60:TIMER7 Update Interrupt and TIMER12 global
+                    DCD     TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13
+                    DCD     TIMER7_Channel_IRQHandler         ; 62:TIMER7 Channel Capture Compare 
+                    DCD     ADC2_IRQHandler                   ; 63:ADC2
+                    DCD     EXMC_IRQHandler                   ; 64:EXMC
+                    DCD     SDIO_IRQHandler                   ; 65:SDIO
+                    DCD     TIMER4_IRQHandler                 ; 66:TIMER4
+                    DCD     SPI2_IRQHandler                   ; 67:SPI2
+                    DCD     UART3_IRQHandler                  ; 68:UART3
+                    DCD     UART4_IRQHandler                  ; 69:UART4
+                    DCD     TIMER5_IRQHandler                 ; 70:TIMER5
+                    DCD     TIMER6_IRQHandler                 ; 71:TIMER6
+                    DCD     DMA1_Channel0_IRQHandler          ; 72:DMA1 Channel0
+                    DCD     DMA1_Channel1_IRQHandler          ; 73:DMA1 Channel1
+                    DCD     DMA1_Channel2_IRQHandler          ; 74:DMA1 Channel2
+                    DCD     DMA1_Channel3_IRQHandler          ; 75:DMA1 Channel3
+                    DCD     DMA1_Channel4_IRQHandler          ; 76:DMA1 Channel4
+                    DCD     ENET_IRQHandler                   ; 77:Ethernet
+                    DCD     ENET_WKUP_IRQHandler              ; 78:Ethernet Wakeup through EXTI line
+                    DCD     CAN1_TX_IRQHandler                ; 79:CAN1 TX
+                    DCD     CAN1_RX0_IRQHandler               ; 80:CAN1 RX0
+                    DCD     CAN1_RX1_IRQHandler               ; 81:CAN1 RX1
+                    DCD     CAN1_EWMC_IRQHandler              ; 82:CAN1 EWMC
+                    DCD     USBFS_IRQHandler                  ; 83:USBFS
+                    DCD     0                                 ; 84:Reserved
+                    DCD     DMA1_Channel5_IRQHandler          ; 85:DMA1 Channel5
+                    DCD     DMA1_Channel6_IRQHandler          ; 86:DMA1 Channel6
+                    DCD     USART5_IRQHandler                 ; 87:USART5
+                    DCD     I2C2_EV_IRQHandler                ; 88:I2C2 Event
+                    DCD     I2C2_ER_IRQHandler                ; 89:I2C2 Error
+                    DCD     0                                 ; 90:Reserved
+                    DCD     0                                 ; 91:Reserved
+                    DCD     0                                 ; 92:Reserved
+                    DCD     0                                 ; 93:Reserved
+                    DCD     DCI_IRQHandler                    ; 94:DCI                                            
+                    DCD     CAU_IRQHandler                    ; 95:CAU                                      
+                    DCD     HAU_TRNG_IRQHandler               ; 96:HAU and TRNG
+                    DCD     0                                 ; 97:Reserved
+                    DCD     UART6_IRQHandler                  ; 98:UART6
+                    DCD     UART7_IRQHandler                  ; 99:UART7
+                    DCD     0                                 ; 100:Reserved
+                    DCD     0                                 ; 101:Reserved
+                    DCD     0                                 ; 102:Reserved
+                    DCD     0                                 ; 103:Reserved
+                    DCD     TLI_IRQHandler                    ; 104:TLI
+                    DCD     TLI_ER_IRQHandler                 ; 105:TLI error
+__Vectors_End
+
+__Vectors_Size      EQU  __Vectors_End - __Vectors
+
+                    AREA    |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler       PROC
+                    EXPORT  Reset_Handler                     [WEAK]
+                    IMPORT  __main
+                    IMPORT  SystemInit  
+                    LDR     R0, =SystemInit
+                    BLX     R0
+                    LDR     R0, =__main
+                    BX      R0
+                    ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler         PROC
+                    EXPORT  NMI_Handler                         [WEAK]
+                    B       .
+                    ENDP
+
+HardFault_Handler   PROC
+                    EXPORT  HardFault_Handler                   [WEAK]
+                    B       .
+                    ENDP
+
+MemManage_Handler   PROC
+                    EXPORT  MemManage_Handler                   [WEAK]
+                    B       .
+                    ENDP
+
+BusFault_Handler    PROC
+                    EXPORT  BusFault_Handler                    [WEAK]
+                    B       .
+                    ENDP
+
+UsageFault_Handler  PROC
+                    EXPORT  UsageFault_Handler                  [WEAK]
+                    B       .
+                    ENDP
+
+SVC_Handler         PROC
+                    EXPORT  SVC_Handler                         [WEAK]
+                    B       .
+                    ENDP
+
+DebugMon_Handler    PROC
+                    EXPORT  DebugMon_Handler                    [WEAK]
+                    B       .
+                    ENDP
+
+PendSV_Handler      PROC
+                    EXPORT  PendSV_Handler                      [WEAK]
+                    B       .
+                    ENDP
+
+SysTick_Handler     PROC
+                    EXPORT  SysTick_Handler                     [WEAK]
+                    B       .
+                    ENDP
+
+Default_Handler     PROC
+;                   /* external interrupts handler */    
+                    EXPORT  WWDGT_IRQHandler                    [WEAK]
+                    EXPORT  LVD_IRQHandler                      [WEAK]
+                    EXPORT  TAMPER_IRQHandler                   [WEAK]
+                    EXPORT  RTC_IRQHandler                      [WEAK]
+                    EXPORT  FMC_IRQHandler                      [WEAK]
+                    EXPORT  RCU_IRQHandler                      [WEAK]
+                    EXPORT  EXTI0_IRQHandler                    [WEAK]
+                    EXPORT  EXTI1_IRQHandler                    [WEAK]
+                    EXPORT  EXTI2_IRQHandler                    [WEAK]
+                    EXPORT  EXTI3_IRQHandler                    [WEAK]
+                    EXPORT  EXTI4_IRQHandler                    [WEAK]
+                    EXPORT  DMA0_Channel0_IRQHandler            [WEAK]
+                    EXPORT  DMA0_Channel1_IRQHandler            [WEAK]
+                    EXPORT  DMA0_Channel2_IRQHandler            [WEAK]
+                    EXPORT  DMA0_Channel3_IRQHandler            [WEAK]
+                    EXPORT  DMA0_Channel4_IRQHandler            [WEAK]
+                    EXPORT  DMA0_Channel5_IRQHandler            [WEAK]
+                    EXPORT  DMA0_Channel6_IRQHandler            [WEAK]
+                    EXPORT  ADC0_1_IRQHandler                   [WEAK]
+                    EXPORT  CAN0_TX_IRQHandler                  [WEAK]
+                    EXPORT  CAN0_RX0_IRQHandler                 [WEAK]
+                    EXPORT  CAN0_RX1_IRQHandler                 [WEAK]
+                    EXPORT  CAN0_EWMC_IRQHandler                [WEAK]
+                    EXPORT  EXTI5_9_IRQHandler                  [WEAK]
+                    EXPORT  TIMER0_BRK_TIMER8_IRQHandler        [WEAK]
+                    EXPORT  TIMER0_UP_TIMER9_IRQHandler         [WEAK]
+                    EXPORT  TIMER0_TRG_CMT_TIMER10_IRQHandler   [WEAK]
+                    EXPORT  TIMER0_Channel_IRQHandler           [WEAK]
+                    EXPORT  TIMER1_IRQHandler                   [WEAK]
+                    EXPORT  TIMER2_IRQHandler                   [WEAK]
+                    EXPORT  TIMER3_IRQHandler                   [WEAK]
+                    EXPORT  I2C0_EV_IRQHandler                  [WEAK]
+                    EXPORT  I2C0_ER_IRQHandler                  [WEAK]
+                    EXPORT  I2C1_EV_IRQHandler                  [WEAK]
+                    EXPORT  I2C1_ER_IRQHandler                  [WEAK]
+                    EXPORT  SPI0_IRQHandler                     [WEAK]
+                    EXPORT  SPI1_IRQHandler                     [WEAK]
+                    EXPORT  USART0_IRQHandler                   [WEAK]
+                    EXPORT  USART1_IRQHandler                   [WEAK]
+                    EXPORT  USART2_IRQHandler                   [WEAK]
+                    EXPORT  EXTI10_15_IRQHandler                [WEAK]
+                    EXPORT  RTC_Alarm_IRQHandler                [WEAK]
+                    EXPORT  USBFS_WKUP_IRQHandler               [WEAK]
+                    EXPORT  TIMER7_BRK_TIMER11_IRQHandler       [WEAK]
+                    EXPORT  TIMER7_UP_TIMER12_IRQHandler        [WEAK]
+                    EXPORT  TIMER7_TRG_CMT_TIMER13_IRQHandler   [WEAK]
+                    EXPORT  TIMER7_Channel_IRQHandler           [WEAK]
+                    EXPORT  ADC2_IRQHandler                     [WEAK]
+                    EXPORT  EXMC_IRQHandler                     [WEAK]
+                    EXPORT  SDIO_IRQHandler                     [WEAK]  
+                    EXPORT  TIMER4_IRQHandler                   [WEAK]
+                    EXPORT  SPI2_IRQHandler                     [WEAK]
+                    EXPORT  UART3_IRQHandler                    [WEAK]
+                    EXPORT  UART4_IRQHandler                    [WEAK]
+                    EXPORT  TIMER5_IRQHandler                   [WEAK]
+                    EXPORT  TIMER6_IRQHandler                   [WEAK]
+                    EXPORT  DMA1_Channel0_IRQHandler            [WEAK]
+                    EXPORT  DMA1_Channel1_IRQHandler            [WEAK]
+                    EXPORT  DMA1_Channel2_IRQHandler            [WEAK]
+                    EXPORT  DMA1_Channel3_IRQHandler            [WEAK]
+                    EXPORT  DMA1_Channel4_IRQHandler            [WEAK]
+                    EXPORT  ENET_IRQHandler                     [WEAK]
+                    EXPORT  ENET_WKUP_IRQHandler                [WEAK]
+                    EXPORT  CAN1_TX_IRQHandler                  [WEAK]
+                    EXPORT  CAN1_RX0_IRQHandler                 [WEAK]
+                    EXPORT  CAN1_RX1_IRQHandler                 [WEAK]
+                    EXPORT  CAN1_EWMC_IRQHandler                [WEAK]
+                    EXPORT  USBFS_IRQHandler                    [WEAK]                                
+                    EXPORT  DMA1_Channel5_IRQHandler            [WEAK]                                   
+                    EXPORT  DMA1_Channel6_IRQHandler            [WEAK]                                   
+                    EXPORT  USART5_IRQHandler                   [WEAK]                                           
+                    EXPORT  I2C2_EV_IRQHandler                  [WEAK]                                              
+                    EXPORT  I2C2_ER_IRQHandler                  [WEAK]                                                                                
+                    EXPORT  DCI_IRQHandler                      [WEAK]                                             
+                    EXPORT  CAU_IRQHandler                      [WEAK]                                     
+                    EXPORT  HAU_TRNG_IRQHandler                 [WEAK]
+                    EXPORT  UART6_IRQHandler                    [WEAK]
+                    EXPORT  UART7_IRQHandler                    [WEAK]
+                    EXPORT  TLI_IRQHandler                      [WEAK]
+                    EXPORT  TLI_ER_IRQHandler                   [WEAK]   
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FMC_IRQHandler 
+RCU_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC0_1_IRQHandler
+CAN0_TX_IRQHandler
+CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_TIMER8_IRQHandler
+TIMER0_UP_TIMER9_IRQHandler
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBFS_WKUP_IRQHandler
+TIMER7_BRK_TIMER11_IRQHandler
+TIMER7_UP_TIMER12_IRQHandler
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+TIMER7_Channel_IRQHandler
+ADC2_IRQHandler
+EXMC_IRQHandler
+SDIO_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+ENET_IRQHandler
+ENET_WKUP_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_EWMC_IRQHandler
+USBFS_IRQHandler
+DMA1_Channel5_IRQHandler                                  
+DMA1_Channel6_IRQHandler                                               
+USART5_IRQHandler                                                            
+I2C2_EV_IRQHandler                                                          
+I2C2_ER_IRQHandler                                                                                                
+DCI_IRQHandler                                                                
+CAU_IRQHandler                                                         
+HAU_TRNG_IRQHandler                 
+UART6_IRQHandler
+UART7_IRQHandler                    
+TLI_IRQHandler                     
+TLI_ER_IRQHandler 
+
+                B       .
+                ENDP
+
+                ALIGN
+
+; user Initial Stack & Heap
+
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap PROC
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+                 ENDP
+                     
+                 ALIGN
+
+                 ENDIF
+
+                 END

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/CMSIS/GD/GD32F20x/Source/IAR/startup_gd32f20x_cl.s

@@ -0,0 +1,622 @@
+;/*!
+;    \file  startup_gd32f20x_cl.s
+;    \brief start up file
+
+;    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+;    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+;    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+;*/
+
+;/*
+;    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+;    All rights reserved.
+
+;    Redistribution and use in source and binary forms, with or without modification, 
+;are permitted provided that the following conditions are met:
+
+;    1. Redistributions of source code must retain the above copyright notice, this 
+;       list of conditions and the following disclaimer.
+;    2. Redistributions in binary form must reproduce the above copyright notice, 
+;       this list of conditions and the following disclaimer in the documentation 
+;       and/or other materials provided with the distribution.
+;    3. Neither the name of the copyright holder nor the names of its contributors 
+;       may be used to endorse or promote products derived from this software without 
+;       specific prior written permission.
+
+;    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+;OF SUCH DAMAGE.
+;*/
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)                       ; top of stack
+        DCD     Reset_Handler                     ; Reset Handler
+                                                  
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler  
+        DCD     BusFault_Handler                  ; Bus Fault Handler 
+        DCD     UsageFault_Handler                ; Usage Fault Handler 
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+                                                  
+        ; External Interrupts                     
+        DCD     WWDGT_IRQHandler                  ; Vector Number 16,Window Watchdog Timer
+        DCD     LVD_IRQHandler                    ; Vector Number 17,LVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler                 ; Vector Number 18,Tamper Interrupt   
+        DCD     RTC_IRQHandler                    ; Vector Number 19,RTC through EXTI Line
+        DCD     FMC_IRQHandler                    ; Vector Number 20,FMC
+        DCD     RCU_IRQHandler                    ; Vector Number 21,RCU
+        DCD     EXTI0_IRQHandler                  ; Vector Number 22,EXTI Line 0
+        DCD     EXTI1_IRQHandler                  ; Vector Number 23,EXTI Line 1
+        DCD     EXTI2_IRQHandler                  ; Vector Number 24,EXTI Line 2
+        DCD     EXTI3_IRQHandler                  ; Vector Number 25,EXTI Line 3
+        DCD     EXTI4_IRQHandler                  ; Vector Number 26,EXTI Line 4
+        DCD     DMA0_Channel0_IRQHandler          ; Vector Number 27,DMA0 Channel 0
+        DCD     DMA0_Channel1_IRQHandler          ; Vector Number 28,DMA0 Channel 1
+        DCD     DMA0_Channel2_IRQHandler          ; Vector Number 29,DMA0 Channel 2
+        DCD     DMA0_Channel3_IRQHandler          ; Vector Number 30,DMA0 Channel 3
+        DCD     DMA0_Channel4_IRQHandler          ; Vector Number 31,DMA0 Channel 4
+        DCD     DMA0_Channel5_IRQHandler          ; Vector Number 32,DMA0 Channel 5 
+        DCD     DMA0_Channel6_IRQHandler          ; Vector Number 33,DMA0 Channel 6
+        DCD     ADC0_1_IRQHandler                 ; Vector Number 34,ADC0 and ADC1
+        DCD     CAN0_TX_IRQHandler                ; Vector Number 35,CAN0 TX
+        DCD     CAN0_RX0_IRQHandler               ; Vector Number 36,CAN0 RX0
+        DCD     CAN0_RX1_IRQHandler               ; Vector Number 37,CAN0 RX1
+        DCD     CAN0_EWMC_IRQHandler              ; Vector Number 38,CAN0 EWMC
+        DCD     EXTI5_9_IRQHandler                ; Vector Number 39,EXTI Line 5 to EXTI Line 9
+        DCD     TIMER0_BRK_TIMER8_IRQHandler      ; Vector Number 40,TIMER0 Break and TIMER8 global
+        DCD     TIMER0_UP_TIMER9_IRQHandler       ; Vector Number 41,TIMER0 Update and TIMER9 global
+        DCD     TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global
+        DCD     TIMER0_Channel_IRQHandler         ; Vector Number 43,TIMER0 Channel Capture Compare
+        DCD     TIMER1_IRQHandler                 ; Vector Number 44,TIMER1
+        DCD     TIMER2_IRQHandler                 ; Vector Number 45,TIMER2
+        DCD     TIMER3_IRQHandler                 ; Vector Number 46,TIMER3
+        DCD     I2C0_EV_IRQHandler                ; Vector Number 47,I2C0 Event
+        DCD     I2C0_ER_IRQHandler                ; Vector Number 48,I2C0 Error
+        DCD     I2C1_EV_IRQHandler                ; Vector Number 49,I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; Vector Number 50,I2C1 Error
+        DCD     SPI0_IRQHandler                   ; Vector Number 51,SPI0
+        DCD     SPI1_IRQHandler                   ; Vector Number 52,SPI1
+        DCD     USART0_IRQHandler                 ; Vector Number 53,USART0
+        DCD     USART1_IRQHandler                 ; Vector Number 54,USART1
+        DCD     USART2_IRQHandler                 ; Vector Number 55,USART2
+        DCD     EXTI10_15_IRQHandler              ; Vector Number 56,EXTI Line 10 to EXTI Line 15
+        DCD     RTC_Alarm_IRQHandler              ; Vector Number 57,RTC Alarm through EXTI Line
+        DCD     USBFS_WKUP_IRQHandler             ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line
+        DCD     TIMER7_BRK_TIMER11_IRQHandler     ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global
+        DCD     TIMER7_UP_TIMER12_IRQHandler      ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global
+        DCD     TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13
+        DCD     TIMER7_Channel_IRQHandler         ; Vector Number 62,TIMER7 Channel Capture Compare 
+        DCD     ADC2_IRQHandler                   ; Vector Number 63,ADC2
+        DCD     EXMC_IRQHandler                   ; Vector Number 64,EXMC
+        DCD     SDIO_IRQHandler                   ; Vector Number 65,SDIO
+        DCD     TIMER4_IRQHandler                 ; Vector Number 66,TIMER4
+        DCD     SPI2_IRQHandler                   ; Vector Number 67,SPI2
+        DCD     UART3_IRQHandler                  ; Vector Number 68,UART3
+        DCD     UART4_IRQHandler                  ; Vector Number 69,UART4
+        DCD     TIMER5_IRQHandler                 ; Vector Number 70,TIMER5
+        DCD     TIMER6_IRQHandler                 ; Vector Number 71,TIMER6
+        DCD     DMA1_Channel0_IRQHandler          ; Vector Number 72,DMA1 Channel0
+        DCD     DMA1_Channel1_IRQHandler          ; Vector Number 73,DMA1 Channel1
+        DCD     DMA1_Channel2_IRQHandler          ; Vector Number 74,DMA1 Channel2
+        DCD     DMA1_Channel3_IRQHandler          ; Vector Number 75,DMA1 Channel3
+        DCD     DMA1_Channel4_IRQHandler          ; Vector Number 76,DMA1 Channel4
+        DCD     ENET_IRQHandler                   ; Vector Number 77,Ethernet
+        DCD     ENET_WKUP_IRQHandler              ; Vector Number 78,Ethernet Wakeup through EXTI line
+        DCD     CAN1_TX_IRQHandler                ; Vector Number 79,CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; Vector Number 80,CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; Vector Number 81,CAN1 RX1
+        DCD     CAN1_EWMC_IRQHandler              ; Vector Number 82,CAN1 EWMC
+        DCD     USBFS_IRQHandler                  ; Vector Number 83,USBFS
+        DCD     0                                 ; Vector Number 84,Reserved
+        DCD     DMA1_Channel5_IRQHandler          ; Vector Number 85,DMA1 Channel5
+        DCD     DMA1_Channel6_IRQHandler          ; Vector Number 86,DMA1 Channel6
+        DCD     USART5_IRQHandler                 ; Vector Number 87,USART5
+        DCD     I2C2_EV_IRQHandler                ; Vector Number 88,I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; Vector Number 89,I2C2 Error
+        DCD     0                                 ; Vector Number 90,Reserved
+        DCD     0                                 ; Vector Number 91,Reserved
+        DCD     0                                 ; Vector Number 92,Reserved
+        DCD     0                                 ; Vector Number 93,Reserved
+        DCD     DCI_IRQHandler                    ; Vector Number 94,DCI                                            
+        DCD     CAU_IRQHandler                    ; Vector Number 95,CAU                                      
+        DCD     HAU_TRNG_IRQHandler               ; Vector Number 96,HAU and TRNG
+        DCD     0                                 ; Vector Number 97,Reserved
+        DCD     UART6_IRQHandler                  ; Vector Number 98,UART6
+        DCD     UART7_IRQHandler                  ; Vector Number 99,UART7
+        DCD     0                                 ; Vector Number 100,Reserved
+        DCD     0                                 ; Vector Number 101,Reserved
+        DCD     0                                 ; Vector Number 102,Reserved
+        DCD     0                                 ; Vector Number 103,Reserved
+        DCD     TLI_IRQHandler                    ; Vector Number 104,TLI
+        DCD     TLI_ER_IRQHandler                 ; Vector Number 105,TLI error
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, = SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+                
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+              
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+       
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+                
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+                
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+                
+        PUBWEAK WWDGT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+        B WWDGT_IRQHandler
+                        
+        PUBWEAK LVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+        B LVD_IRQHandler
+        
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+                       
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+                        
+        PUBWEAK RCU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_IRQHandler
+        B RCU_IRQHandler
+                        
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+                        
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+                        
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+                        
+        PUBWEAK DMA0_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+        B DMA0_Channel0_IRQHandler
+        
+                
+        PUBWEAK DMA0_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+        B DMA0_Channel1_IRQHandler
+
+        PUBWEAK DMA0_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+        B DMA0_Channel2_IRQHandler
+                        
+        PUBWEAK DMA0_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+        B DMA0_Channel3_IRQHandler
+
+        PUBWEAK DMA0_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+        B DMA0_Channel4_IRQHandler
+        
+        PUBWEAK DMA0_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+        B DMA0_Channel5_IRQHandler
+
+        PUBWEAK DMA0_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+        B DMA0_Channel6_IRQHandler
+                
+        PUBWEAK ADC0_1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_1_IRQHandler
+        B ADC0_1_IRQHandler
+                         
+        PUBWEAK CAN0_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_TX_IRQHandler
+        B CAN0_TX_IRQHandler
+                        
+        PUBWEAK CAN0_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX0_IRQHandler
+        B CAN0_RX0_IRQHandler
+                        
+        PUBWEAK CAN0_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+        B CAN0_RX1_IRQHandler
+                        
+        PUBWEAK CAN0_EWMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+        B CAN0_EWMC_IRQHandler
+                        
+        PUBWEAK EXTI5_9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+        B EXTI5_9_IRQHandler
+        
+        PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_TIMER8_IRQHandler
+        B TIMER0_BRK_TIMER8_IRQHandler
+                        
+        PUBWEAK TIMER0_UP_TIMER9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_TIMER9_IRQHandler
+        B TIMER0_UP_TIMER9_IRQHandler
+        
+        PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+        B TIMER0_TRG_CMT_TIMER10_IRQHandler
+                       
+        PUBWEAK TIMER0_Channel_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+        B TIMER0_Channel_IRQHandler
+                        
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+                        
+        PUBWEAK TIMER2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+        B TIMER2_IRQHandler
+        
+       PUBWEAK TIMER3_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+       B TIMER3_IRQHandler
+                        
+        PUBWEAK I2C0_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+        B I2C0_EV_IRQHandler
+                
+        PUBWEAK I2C0_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+        B I2C0_ER_IRQHandler
+                        
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+                       
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+                        
+        PUBWEAK SPI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+        B SPI0_IRQHandler
+                        
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+          PUBWEAK USART0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+        B USART0_IRQHandler
+        
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK EXTI10_15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+        B EXTI10_15_IRQHandler
+        
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+        
+         PUBWEAK USBFS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_WKUP_IRQHandler
+        B USBFS_WKUP_IRQHandler
+        
+        PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_BRK_TIMER11_IRQHandler
+        B TIMER7_BRK_TIMER11_IRQHandler
+
+        PUBWEAK TIMER7_UP_TIMER12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_UP_TIMER12_IRQHandler
+        B TIMER7_UP_TIMER12_IRQHandler
+
+        PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+        B TIMER7_TRG_CMT_TIMER13_IRQHandler
+
+        PUBWEAK TIMER7_Channel_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_Channel_IRQHandler
+        B TIMER7_Channel_IRQHandler
+
+        PUBWEAK ADC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC2_IRQHandler
+        B ADC2_IRQHandler
+
+        PUBWEAK EXMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+        B EXMC_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDIO_IRQHandler
+        B SDIO_IRQHandler
+
+        PUBWEAK TIMER4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+        B TIMER4_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK TIMER5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_IRQHandler
+        B TIMER5_IRQHandler
+
+        PUBWEAK TIMER6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER6_IRQHandler
+        B TIMER6_IRQHandler
+
+        PUBWEAK DMA1_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+        B DMA1_Channel0_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK ENET_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_IRQHandler
+        B ENET_IRQHandler
+
+        PUBWEAK ENET_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_WKUP_IRQHandler
+        B ENET_WKUP_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_EWMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_EWMC_IRQHandler
+        B CAN1_EWMC_IRQHandler
+
+        PUBWEAK USBFS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_IRQHandler
+        B USBFS_IRQHandler
+        
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        
+        PUBWEAK USART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART5_IRQHandler
+        B USART5_IRQHandler
+        
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+        
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+        
+        PUBWEAK DCI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCI_IRQHandler
+        B DCI_IRQHandler
+        
+        PUBWEAK CAU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAU_IRQHandler
+        B CAU_IRQHandler
+
+        PUBWEAK HAU_TRNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HAU_TRNG_IRQHandler
+        B HAU_TRNG_IRQHandler
+        
+        PUBWEAK UART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART6_IRQHandler
+        B UART6_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+                                    
+        PUBWEAK TLI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TLI_IRQHandler
+        B TLI_IRQHandler
+
+        PUBWEAK TLI_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TLI_ER_IRQHandler
+        B TLI_ER_IRQHandler
+        
+        END

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_adc.h

@@ -0,0 +1,412 @@
+/*!
+    \file  gd32f20x_adc.h
+    \brief definitions for the ADC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_ADC_H
+#define GD32F20X_ADC_H
+
+#include "gd32f20x.h"
+
+/* ADC definitions */
+#define ADC0                             ADC_BASE
+#define ADC1                             (ADC_BASE + 0x400U)
+#define ADC2                             (ADC_BASE + 0x1800U)
+
+/* registers definitions */
+#define ADC_STAT(adcx)                   REG32((adcx) + 0x00U)            /*!< ADC status register */
+#define ADC_CTL0(adcx)                   REG32((adcx) + 0x04U)            /*!< ADC control register 0 */
+#define ADC_CTL1(adcx)                   REG32((adcx) + 0x08U)            /*!< ADC control register 1 */
+#define ADC_SAMPT0(adcx)                 REG32((adcx) + 0x0CU)            /*!< ADC sampling time register 0 */
+#define ADC_SAMPT1(adcx)                 REG32((adcx) + 0x10U)            /*!< ADC sampling time register 1 */
+#define ADC_IOFF0(adcx)                  REG32((adcx) + 0x14U)            /*!< ADC inserted channel data offset register 0 */
+#define ADC_IOFF1(adcx)                  REG32((adcx) + 0x18U)            /*!< ADC inserted channel data offset register 1 */
+#define ADC_IOFF2(adcx)                  REG32((adcx) + 0x1CU)            /*!< ADC inserted channel data offset register 2 */
+#define ADC_IOFF3(adcx)                  REG32((adcx) + 0x20U)            /*!< ADC inserted channel data offset register 3 */
+#define ADC_WDHT(adcx)                   REG32((adcx) + 0x24U)            /*!< ADC watchdog high threshold register */
+#define ADC_WDLT(adcx)                   REG32((adcx) + 0x28U)            /*!< ADC watchdog low threshold register */
+#define ADC_RSQ0(adcx)                   REG32((adcx) + 0x2CU)            /*!< ADC regular sequence register 0 */
+#define ADC_RSQ1(adcx)                   REG32((adcx) + 0x30U)            /*!< ADC regular sequence register 1 */
+#define ADC_RSQ2(adcx)                   REG32((adcx) + 0x34U)            /*!< ADC regular sequence register 2 */
+#define ADC_ISQ(adcx)                    REG32((adcx) + 0x38U)            /*!< ADC inserted sequence register */
+#define ADC_IDATA0(adcx)                 REG32((adcx) + 0x3CU)            /*!< ADC inserted data register 0 */
+#define ADC_IDATA1(adcx)                 REG32((adcx) + 0x40U)            /*!< ADC inserted data register 1 */
+#define ADC_IDATA2(adcx)                 REG32((adcx) + 0x44U)            /*!< ADC inserted data register 2 */
+#define ADC_IDATA3(adcx)                 REG32((adcx) + 0x48U)            /*!< ADC inserted data register 3 */
+#define ADC_RDATA(adcx)                  REG32((adcx) + 0x4CU)            /*!< ADC regular data register */
+#define ADC_OVSAMPCTL(adcx)              REG32((adcx) + 0x80U)            /*!< ADC oversampling control register */
+
+/* bits definitions */
+/* ADC_STAT */
+#define ADC_STAT_WDE                     BIT(0)                           /*!< analog watchdog event flag */
+#define ADC_STAT_EOC                     BIT(1)                           /*!< end of conversion */
+#define ADC_STAT_EOIC                    BIT(2)                           /*!< inserted channel end of conversion */
+#define ADC_STAT_STIC                    BIT(3)                           /*!< inserted channel start flag */
+#define ADC_STAT_STRC                    BIT(4)                           /*!< regular channel start flag */
+
+/* ADC_CTL0 */
+#define ADC_CTL0_WDCHSEL                 BITS(0,4)                        /*!< analog watchdog channel select bits */
+#define ADC_CTL0_EOCIE                   BIT(5)                           /*!< interrupt enable for EOC */
+#define ADC_CTL0_WDEIE                   BIT(6)                           /*!< analog watchdog interrupt enable */
+#define ADC_CTL0_EOICIE                  BIT(7)                           /*!< interrupt enable for inserted channels */
+#define ADC_CTL0_SM                      BIT(8)                           /*!< scan mode */
+#define ADC_CTL0_WDSC                    BIT(9)                           /*!< when in scan mode, analog watchdog is effective on a single channel */
+#define ADC_CTL0_ICA                     BIT(10)                          /*!< automatic inserted group conversion */
+#define ADC_CTL0_DISRC                   BIT(11)                          /*!< discontinuous mode on regular channels */
+#define ADC_CTL0_DISIC                   BIT(12)                          /*!< discontinuous mode on inserted channels */
+#define ADC_CTL0_DISNUM                  BITS(13,15)                      /*!< discontinuous mode channel count */
+#define ADC_CTL0_SYNCM                   BITS(16,19)                      /*!< sync mode selection */
+#define ADC_CTL0_IWDEN                   BIT(22)                          /*!< analog watchdog enable on inserted channels */
+#define ADC_CTL0_RWDEN                   BIT(23)                          /*!< analog watchdog enable on regular channels */
+
+/* ADC_CTL1 */
+#define ADC_CTL1_ADCON                   BIT(0)                           /*!< ADC converter on */
+#define ADC_CTL1_CTN                     BIT(1)                           /*!< continuous conversion */
+#define ADC_CTL1_CLB                     BIT(2)                           /*!< ADC calibration */
+#define ADC_CTL1_RSTCLB                  BIT(3)                           /*!< reset calibration */
+#define ADC_CTL1_DMA                     BIT(8)                           /*!< direct memory access mode */
+#define ADC_CTL1_DAL                     BIT(11)                          /*!< data alignment */
+#define ADC_CTL1_ETSIC                   BITS(12,14)                      /*!< external trigger select for inserted channel */
+#define ADC_CTL1_ETEIC                   BIT(15)                          /*!< external trigger enable for inserted channel */
+#define ADC_CTL1_ETSRC                   BITS(17,19)                      /*!< external trigger select for regular channel */
+#define ADC_CTL1_ETERC                   BIT(20)                          /*!< external trigger enable for regular channel */
+#define ADC_CTL1_SWICST                  BIT(21)                          /*!< start on inserted channel */
+#define ADC_CTL1_SWRCST                  BIT(22)                          /*!< start on regular channel */
+#define ADC_CTL1_TSVREN                  BIT(23)                          /*!< channel 16 and 17 enable of ADC0 */
+
+/* ADC_SAMPTx  x=0,1 */
+#define ADC_SAMPTX_SPTN                  BITS(0,2)                        /*!< channel n sample time selection */
+
+/* ADC_IOFFx x=0..3 */
+#define ADC_IOFFX_IOFF                   BITS(0,11)                       /*!< data offset for inserted channel x */
+
+/* ADC_WDHT */
+#define ADC_WDHT_WDHT                    BITS(0,11)                       /*!< analog watchdog high threshold */
+
+/* ADC_WDLT */
+#define ADC_WDLT_WDLT                    BITS(0,11)                       /*!< analog watchdog low threshold */
+
+/* ADC_RSQx x=0..2 */
+#define ADC_RSQX_RSQN                    BITS(0,4)                        /*!< x conversion in regular sequence */
+#define ADC_RSQ0_RL                      BITS(20,23)                      /*!< regular channel sequence length */
+
+/* ADC_ISQ */
+#define ADC_ISQ_ISQN                     BITS(0,4)                        /*!< n conversion in regular sequence */
+#define ADC_ISQ_IL                       BITS(20,21)                      /*!< inserted sequence length */
+
+/* ADC_IDATAx x=0..3*/
+#define ADC_IDATAX_IDATAN                BITS(0,15)                       /*!< inserted channel x conversion data  */
+
+/* ADC_RDATA */
+#define ADC_RDATA_RDATA                  BITS(0,15)                       /*!< regular channel data */
+#define ADC_RDATA_ADC1RDTR               BITS(16,31)                      /*!< ADC1 regular channel data */
+
+/* ADC_OVSAMPCTL */
+#define ADC_OVSAMPCTL_OVSEN              BIT(0)                           /*!< oversampling enable */
+#define ADC_OVSAMPCTL_OVSR               BITS(2,4)                        /*!< oversampling ratio */
+#define ADC_OVSAMPCTL_OVSS               BITS(5,8)                        /*!< oversampling shift */
+#define ADC_OVSAMPCTL_TOVS               BIT(9)                           /*!< triggered oversampling */
+#define ADC_OVSAMPCTL_DRES               BITS(12,13)                      /*!< oversampling shift */
+
+/* constants definitions */
+/* adc_stat register value */
+#define ADC_FLAG_WDE                     ADC_STAT_WDE                                /*!< analog watchdog event flag */
+#define ADC_FLAG_EOC                     ADC_STAT_EOC                                /*!< end of group conversion flag */
+#define ADC_FLAG_EOIC                    ADC_STAT_EOIC                               /*!< end of inserted channel group conversion flag */
+#define ADC_FLAG_STIC                    ADC_STAT_STIC                               /*!< inserted channel start flag */
+#define ADC_FLAG_STRC                    ADC_STAT_STRC                               /*!< regular channel start flag */
+
+/* adc_ctl0 register value */
+#define CTL0_DISNUM(regval)             (BITS(13,15) & ((uint32_t)(regval) << 13))   /*!< write value to ADC_CTL0_DISNUM bit field */
+
+/* scan mode */
+#define ADC_SCAN_MODE                   ADC_CTL0_SM                                  /*!< scan mode */
+
+/* inserted channel group convert automatically */
+#define ADC_INSERTED_CHANNEL_AUTO       ADC_CTL0_ICA                                 /*!< inserted channel group convert automatically */
+
+/* ADC sync mode */
+#define CTL0_SYNCM(regval)              (BITS(16,19) & ((uint32_t)(regval) << 16))   /*!< write value to ADC_CTL0_SYNCM bit field */
+#define ADC_MODE_FREE                                        CTL0_SYNCM(0)           /*!< all the ADCs work independently */
+#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL          CTL0_SYNCM(1)           /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
+#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION          CTL0_SYNCM(2)           /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
+#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST     CTL0_SYNCM(3)           /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
+#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW     CTL0_SYNCM(4)           /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
+#define ADC_DAUL_INSERTED_PARALLEL                           CTL0_SYNCM(5)           /*!< ADC0 and ADC1 work in inserted parallel mode only */
+#define ADC_DAUL_REGULAL_PARALLEL                            CTL0_SYNCM(6)           /*!< ADC0 and ADC1 work in regular parallel mode only */
+#define ADC_DAUL_REGULAL_FOLLOWUP_FAST                       CTL0_SYNCM(7)           /*!< ADC0 and ADC1 work in follow-up fast mode only */
+#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW                       CTL0_SYNCM(8)           /*!< ADC0 and ADC1 work in follow-up slow mode only */
+#define ADC_DAUL_INSERTED_TRIGGER_ROTATION                   CTL0_SYNCM(9)           /*!< ADC0 and ADC1 work in trigger rotation mode only */
+
+/* adc_ctl1 register value */
+#define ADC_DATAALIGN_RIGHT              ((uint32_t)0x00000000U)                     /*!< LSB alignment */
+#define ADC_DATAALIGN_LEFT               ADC_CTL1_DAL                                /*!< MSB alignment */
+
+/* continuous mode */
+#define ADC_CONTINUOUS_MODE              ADC_CTL1_CTN                                /*!< continuous mode */
+
+/* external trigger select for regular channel */
+#define CTL1_ETSRC(regval)               (BITS(17,19) & ((uint32_t)(regval) << 17))  /*!< write value to ADC_CTL1_ETSRC bit field */
+/* for ADC0 and ADC1 regular channel */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH0    CTL1_ETSRC(0)                               /*!< TIMER0 CH0 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH1    CTL1_ETSRC(1)                               /*!< TIMER0 CH1 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T0_CH2    CTL1_ETSRC(2)                               /*!< TIMER0 CH2 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T1_CH1    CTL1_ETSRC(3)                               /*!< TIMER1 CH1 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO   CTL1_ETSRC(4)                               /*!< TIMER2 TRGO event select */
+#define ADC0_1_EXTTRIG_REGULAR_T3_CH3    CTL1_ETSRC(5)                               /*!< TIMER3 CH3 event select */
+#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO   CTL1_ETSRC(6)                               /*!< TIMER7 TRGO event select */
+#define ADC0_1_EXTTRIG_REGULAR_EXTI_11   CTL1_ETSRC(6)                               /*!< external interrupt line 11 */
+#define ADC0_1_2_EXTTRIG_REGULAR_NONE    CTL1_ETSRC(7)                               /*!< software trigger */
+/* for ADC2 regular channel */
+#define ADC2_EXTTRIG_REGULAR_T2_CH0      CTL1_ETSRC(0)                               /*!< TIMER2 CH0 event select */
+#define ADC2_EXTTRIG_REGULAR_T1_CH2      CTL1_ETSRC(1)                               /*!< TIMER1 CH2 event select */
+#define ADC2_EXTTRIG_REGULAR_T0_CH2      CTL1_ETSRC(2)                               /*!< TIMER0 CH2 event select */
+#define ADC2_EXTTRIG_REGULAR_T7_CH0      CTL1_ETSRC(3)                               /*!< TIMER7 CH0 event select */
+#define ADC2_EXTTRIG_REGULAR_T7_TRGO     CTL1_ETSRC(4)                               /*!< TIMER7 TRGO event select */
+#define ADC2_EXTTRIG_REGULAR_T4_CH0      CTL1_ETSRC(5)                               /*!< TIMER4 CH0 event select */
+#define ADC2_EXTTRIG_REGULAR_T4_CH2      CTL1_ETSRC(6)                               /*!< TIMER4 CH2 event select */
+
+/* external trigger mode for inserted channel */
+#define CTL1_ETSIC(regval)               (BITS(12,14) & ((uint32_t)(regval) << 12))  /*!< write value to ADC_CTL1_ETSIC bit field */
+/* for ADC0 and ADC1 inserted channel */
+#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO  CTL1_ETSIC(0)                               /*!< TIMER0 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_T0_CH3   CTL1_ETSIC(1)                               /*!< TIMER0 CH3 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO  CTL1_ETSIC(2)                               /*!< TIMER1 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_T1_CH0   CTL1_ETSIC(3)                               /*!< TIMER1 CH0 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T2_CH3   CTL1_ETSIC(4)                               /*!< TIMER2 CH3 event select */
+#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO  CTL1_ETSIC(5)                               /*!< TIMER3 TRGO event select */
+#define ADC0_1_EXTTRIG_INSERTED_EXTI_15  CTL1_ETSIC(6)                               /*!< external interrupt line 15 */
+#define ADC0_1_EXTTRIG_INSERTED_T7_CH3   CTL1_ETSIC(6)                               /*!< TIMER7 CH3 event select */
+#define ADC0_1_2_EXTTRIG_INSERTED_NONE   CTL1_ETSIC(7)                               /*!< software trigger */
+/* for ADC2 inserted channel */
+#define ADC2_EXTTRIG_INSERTED_T0_TRGO    CTL1_ETSIC(0)                               /*!< TIMER0 TRGO event select */
+#define ADC2_EXTTRIG_INSERTED_T0_CH3     CTL1_ETSIC(1)                               /*!< TIMER0 CH3 event select */
+#define ADC2_EXTTRIG_INSERTED_T3_CH2     CTL1_ETSIC(2)                               /*!< TIMER3 CH2 event select */
+#define ADC2_EXTTRIG_INSERTED_T7_CH1     CTL1_ETSIC(3)                               /*!< TIMER7 CH1 event select */
+#define ADC2_EXTTRIG_INSERTED_T7_CH3     CTL1_ETSIC(4)                               /*!< TIMER7 CH3 event select */
+#define ADC2_EXTTRIG_INSERTED_T4_TRGO    CTL1_ETSIC(5)                               /*!< TIMER4 TRGO event select */
+#define ADC2_EXTTRIG_INSERTED_T4_CH3     CTL1_ETSIC(6)                               /*!< TIMER4 CH3 event select */
+
+/* adc_samptx register value */
+#define SAMPTX_SPT(regval)               (BITS(0,2) & ((uint32_t)(regval) << 0))     /*!< write value to ADC_SAMPTX_SPT bit field */
+#define ADC_SAMPLETIME_1POINT5           SAMPTX_SPT(0)                               /*!< 1.5 sampling cycles */
+#define ADC_SAMPLETIME_7POINT5           SAMPTX_SPT(1)                               /*!< 7.5 sampling cycles */
+#define ADC_SAMPLETIME_13POINT5          SAMPTX_SPT(2)                               /*!< 13.5 sampling cycles */
+#define ADC_SAMPLETIME_28POINT5          SAMPTX_SPT(3)                               /*!< 28.5 sampling cycles */
+#define ADC_SAMPLETIME_41POINT5          SAMPTX_SPT(4)                               /*!< 41.5 sampling cycles */
+#define ADC_SAMPLETIME_55POINT5          SAMPTX_SPT(5)                               /*!< 55.5 sampling cycles */
+#define ADC_SAMPLETIME_71POINT5          SAMPTX_SPT(6)                               /*!< 71.5 sampling cycles */
+#define ADC_SAMPLETIME_239POINT5         SAMPTX_SPT(7)                               /*!< 239.5 sampling cycles */
+
+/* adc_ioffx register value */
+#define IOFFX_IOFF(regval)               (BITS(0,11) & ((uint32_t)(regval) << 0))    /*!< write value to ADC_IOFFX_IOFF bit field */
+
+/* adc_wdht register value */
+#define WDHT_WDHT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    /*!< write value to ADC_WDHT_WDHT bit field */
+
+/* adc_wdlt register value */
+#define WDLT_WDLT(regval)                (BITS(0,11) & ((uint32_t)(regval) << 0))    /*!< write value to ADC_WDLT_WDLT bit field */
+
+/* adc_rsqx register value */
+#define RSQ0_RL(regval)                  (BITS(20,23) & ((uint32_t)(regval) << 20))  /*!< write value to ADC_RSQ0_RL bit field */
+
+/* adc_isq register value */
+#define ISQ_IL(regval)                   (BITS(20,21) & ((uint32_t)(regval) << 20))  /*!< write value to ADC_ISQ_IL bit field */
+
+/* adc_ovsampctl register value */
+#define OVSAMPCTL_DRES(regval)           (BITS(12,13) & ((uint32_t)(regval) << 12))  /*!< write value to ADC_OVSAMPCTL_DRES bit field */
+#define ADC_RESOLUTION_12B               OVSAMPCTL_DRES(0)                           /*!< 12-bit ADC resolution */
+#define ADC_RESOLUTION_10B               OVSAMPCTL_DRES(1)                           /*!< 10-bit ADC resolution */
+#define ADC_RESOLUTION_8B                OVSAMPCTL_DRES(2)                           /*!< 8-bit ADC resolution */
+#define ADC_RESOLUTION_6B                OVSAMPCTL_DRES(3)                           /*!< 6-bit ADC resolution */
+
+#define OVSAMPCTL_OVSS(regval)           (BITS(5,8) & ((uint32_t)(regval) << 5))     /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
+#define ADC_OVERSAMPLING_SHIFT_NONE      OVSAMPCTL_OVSS(0)                           /*!< no oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_1B        OVSAMPCTL_OVSS(1)                           /*!< 1-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_2B        OVSAMPCTL_OVSS(2)                           /*!< 2-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_3B        OVSAMPCTL_OVSS(3)                           /*!< 3-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_4B        OVSAMPCTL_OVSS(4)                           /*!< 4-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_5B        OVSAMPCTL_OVSS(5)                           /*!< 5-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_6B        OVSAMPCTL_OVSS(6)                           /*!< 6-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_7B        OVSAMPCTL_OVSS(7)                           /*!< 7-bit oversampling shift */
+#define ADC_OVERSAMPLING_SHIFT_8B        OVSAMPCTL_OVSS(8)                           /*!< 8-bit oversampling shift */
+
+#define OVSAMPCTL_OVSR(regval)           (BITS(2,4) & ((uint32_t)(regval) << 2))     /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
+#define ADC_OVERSAMPLING_RATIO_MUL2      OVSAMPCTL_OVSR(0)                           /*!< oversampling ratio multiple 2 */
+#define ADC_OVERSAMPLING_RATIO_MUL4      OVSAMPCTL_OVSR(1)                           /*!< oversampling ratio multiple 4 */
+#define ADC_OVERSAMPLING_RATIO_MUL8      OVSAMPCTL_OVSR(2)                           /*!< oversampling ratio multiple 8 */
+#define ADC_OVERSAMPLING_RATIO_MUL16     OVSAMPCTL_OVSR(3)                           /*!< oversampling ratio multiple 16 */
+#define ADC_OVERSAMPLING_RATIO_MUL32     OVSAMPCTL_OVSR(4)                           /*!< oversampling ratio multiple 32 */
+#define ADC_OVERSAMPLING_RATIO_MUL64     OVSAMPCTL_OVSR(5)                           /*!< oversampling ratio multiple 64 */
+#define ADC_OVERSAMPLING_RATIO_MUL128    OVSAMPCTL_OVSR(6)                           /*!< oversampling ratio multiple 128 */
+#define ADC_OVERSAMPLING_RATIO_MUL256    OVSAMPCTL_OVSR(7)                           /*!< oversampling ratio multiple 256 */
+
+#define ADC_OVERSAMPLING_ALL_CONVERT     0U                                          /*!< all oversampled conversions for a channel are done consecutively after a trigger */
+#define ADC_OVERSAMPLING_ONE_CONVERT     1U                                          /*!< each oversampled conversion for a channel needs a trigger */
+
+/* ADC channel group definitions */
+#define ADC_REGULAR_CHANNEL              ((uint8_t)0x01U)                            /*!< ADC regular channel group */
+#define ADC_INSERTED_CHANNEL             ((uint8_t)0x02U)                            /*!< ADC inserted channel group */
+#define ADC_REGULAR_INSERTED_CHANNEL     ((uint8_t)0x03U)                            /*!< both regular and inserted channel group */
+
+#define ADC_CHANNEL_DISCON_DISABLE       ((uint8_t)0x04U)                            /*!< disable discontinuous mode of regular & inserted channel */
+
+/* ADC inserted channel definitions */
+#define ADC_INSERTED_CHANNEL_0           ((uint8_t)0x00U)                            /*!< ADC inserted channel 0 */
+#define ADC_INSERTED_CHANNEL_1           ((uint8_t)0x01U)                            /*!< ADC inserted channel 1 */
+#define ADC_INSERTED_CHANNEL_2           ((uint8_t)0x02U)                            /*!< ADC inserted channel 2 */
+#define ADC_INSERTED_CHANNEL_3           ((uint8_t)0x03U)                            /*!< ADC inserted channel 3 */
+
+/* ADC channel definitions */
+#define ADC_CHANNEL_0                    ((uint8_t)0x00U)                            /*!< ADC channel 0 */
+#define ADC_CHANNEL_1                    ((uint8_t)0x01U)                            /*!< ADC channel 1 */
+#define ADC_CHANNEL_2                    ((uint8_t)0x02U)                            /*!< ADC channel 2 */
+#define ADC_CHANNEL_3                    ((uint8_t)0x03U)                            /*!< ADC channel 3 */
+#define ADC_CHANNEL_4                    ((uint8_t)0x04U)                            /*!< ADC channel 4 */
+#define ADC_CHANNEL_5                    ((uint8_t)0x05U)                            /*!< ADC channel 5 */
+#define ADC_CHANNEL_6                    ((uint8_t)0x06U)                            /*!< ADC channel 6 */
+#define ADC_CHANNEL_7                    ((uint8_t)0x07U)                            /*!< ADC channel 7 */
+#define ADC_CHANNEL_8                    ((uint8_t)0x08U)                            /*!< ADC channel 8 */
+#define ADC_CHANNEL_9                    ((uint8_t)0x09U)                            /*!< ADC channel 9 */
+#define ADC_CHANNEL_10                   ((uint8_t)0x0AU)                            /*!< ADC channel 10 */
+#define ADC_CHANNEL_11                   ((uint8_t)0x0BU)                            /*!< ADC channel 11 */
+#define ADC_CHANNEL_12                   ((uint8_t)0x0CU)                            /*!< ADC channel 12 */
+#define ADC_CHANNEL_13                   ((uint8_t)0x0DU)                            /*!< ADC channel 13 */
+#define ADC_CHANNEL_14                   ((uint8_t)0x0EU)                            /*!< ADC channel 14 */
+#define ADC_CHANNEL_15                   ((uint8_t)0x0FU)                            /*!< ADC channel 15 */
+#define ADC_CHANNEL_16                   ((uint8_t)0x10U)                            /*!< ADC channel 16 */
+#define ADC_CHANNEL_17                   ((uint8_t)0x11U)                            /*!< ADC channel 17 */
+
+/* ADC interrupt */
+#define ADC_INT_WDE                      ADC_STAT_WDE                                /*!< analog watchdog event interrupt */
+#define ADC_INT_EOC                      ADC_STAT_EOC                                /*!< end of group conversion interrupt */
+#define ADC_INT_EOIC                     ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt */
+
+/* ADC interrupt flag */
+#define ADC_INT_FLAG_WDE                 ADC_STAT_WDE                                /*!< analog watchdog event interrupt flag */
+#define ADC_INT_FLAG_EOC                 ADC_STAT_EOC                                /*!< end of group conversion interrupt flag */
+#define ADC_INT_FLAG_EOIC                ADC_STAT_EOIC                               /*!< end of inserted group conversion interrupt flag */
+
+/* function declarations */
+/* initialization configure */
+/* reset ADC */
+void adc_deinit(uint32_t adc_periph);
+/* configure the ADC sync mode */
+void adc_mode_config(uint32_t mode);
+/* enable or disable ADC special function */
+void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus new_value);
+/* configure ADC data alignment */
+void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment);
+/* enable ADC interface */
+void adc_enable(uint32_t adc_periph);
+/* disable ADC interface */
+void adc_disable(uint32_t adc_periph);
+/* ADC calibration and reset calibration */
+void adc_calibration_enable(uint32_t adc_periph);
+/* enable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_enable(void);
+/* disable the temperature sensor and Vrefint channel */
+void adc_tempsensor_vrefint_disable(void);
+
+/* function configuration */
+/* DMA configure */
+/* enable DMA request */
+void adc_dma_mode_enable(uint32_t adc_periph);
+/* disable DMA request */
+void adc_dma_mode_disable(uint32_t adc_periph);
+
+/* regular group and inserted group configure */
+/* configure ADC discontinuous mode */
+void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length);
+
+/* configure the length of regular channel group or inserted channel group */
+void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length);
+/* configure ADC regular channel */
+void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
+/* configure ADC inserted channel */
+void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time);
+/* configure ADC inserted channel offset */
+void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset);
+
+/* configure ADC external trigger source */
+void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
+/* configure ADC external trigger */
+void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
+/* enable ADC software trigger */
+void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group);
+
+/* get channel data */
+/* read ADC regular group data register */
+uint16_t adc_regular_data_read(uint32_t adc_periph);
+/* read ADC inserted group data register */
+uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel);
+/* read the last ADC0 and ADC1 conversion result data in sync mode */
+uint32_t adc_sync_mode_convert_value_read(void);
+
+/* watchdog configure */
+/* configure ADC analog watchdog single channel */
+void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
+/* configure ADC analog watchdog group channel */
+void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
+/* disable ADC analog watchdog */
+void adc_watchdog_disable(uint32_t adc_periph);
+/* configure ADC analog watchdog threshold */
+void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold);
+
+/* interrupt & flag functions */
+/* get the ADC flag bits */
+FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag);
+/* clear the ADC flag bits */
+void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag);
+/* get the ADC interrupt flag */
+FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt);
+/* clear the ADC interrupt flag */
+void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt);
+/* enable ADC interrupt */
+void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt);
+/* disable ADC interrupt */
+void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt);
+
+/* configure ADC resolution */
+void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
+/* configure ADC oversample mode */
+void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio);
+/* enable ADC oversample mode */
+void adc_oversample_mode_enable(uint32_t adc_periph);
+/* disable ADC oversample mode */
+void adc_oversample_mode_disable(uint32_t adc_periph);
+
+#endif /* GD32F20X_ADC_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_bkp.h

@@ -0,0 +1,274 @@
+/*!
+    \file  gd32f20x_bkp.h
+    \brief definitions for the BKP
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_BKP_H
+#define GD32F20X_BKP_H
+
+#include "gd32f20x.h"
+
+/* BKP definitions */
+#define BKP                             BKP_BASE                 /*!< BKP base address */
+
+/* registers definitions */
+#define BKP_DATA0                       REG16((BKP) + 0x04U)     /*!< BKP data register 0 */
+#define BKP_DATA1                       REG16((BKP) + 0x08U)     /*!< BKP data register 1 */
+#define BKP_DATA2                       REG16((BKP) + 0x0CU)     /*!< BKP data register 2 */
+#define BKP_DATA3                       REG16((BKP) + 0x10U)     /*!< BKP data register 3 */
+#define BKP_DATA4                       REG16((BKP) + 0x14U)     /*!< BKP data register 4 */
+#define BKP_DATA5                       REG16((BKP) + 0x18U)     /*!< BKP data register 5 */
+#define BKP_DATA6                       REG16((BKP) + 0x1CU)     /*!< BKP data register 6 */
+#define BKP_DATA7                       REG16((BKP) + 0x20U)     /*!< BKP data register 7 */
+#define BKP_DATA8                       REG16((BKP) + 0x24U)     /*!< BKP data register 8 */
+#define BKP_DATA9                       REG16((BKP) + 0x28U)     /*!< BKP data register 9 */
+#define BKP_DATA10                      REG16((BKP) + 0x40U)     /*!< BKP data register 10 */
+#define BKP_DATA11                      REG16((BKP) + 0x44U)     /*!< BKP data register 11 */
+#define BKP_DATA12                      REG16((BKP) + 0x48U)     /*!< BKP data register 12 */
+#define BKP_DATA13                      REG16((BKP) + 0x4CU)     /*!< BKP data register 13 */
+#define BKP_DATA14                      REG16((BKP) + 0x50U)     /*!< BKP data register 14 */
+#define BKP_DATA15                      REG16((BKP) + 0x54U)     /*!< BKP data register 15 */
+#define BKP_DATA16                      REG16((BKP) + 0x58U)     /*!< BKP data register 16 */
+#define BKP_DATA17                      REG16((BKP) + 0x5CU)     /*!< BKP data register 17 */
+#define BKP_DATA18                      REG16((BKP) + 0x60U)     /*!< BKP data register 18 */
+#define BKP_DATA19                      REG16((BKP) + 0x64U)     /*!< BKP data register 19 */
+#define BKP_DATA20                      REG16((BKP) + 0x68U)     /*!< BKP data register 20 */
+#define BKP_DATA21                      REG16((BKP) + 0x6CU)     /*!< BKP data register 21 */
+#define BKP_DATA22                      REG16((BKP) + 0x70U)     /*!< BKP data register 22 */
+#define BKP_DATA23                      REG16((BKP) + 0x74U)     /*!< BKP data register 23 */
+#define BKP_DATA24                      REG16((BKP) + 0x78U)     /*!< BKP data register 24 */
+#define BKP_DATA25                      REG16((BKP) + 0x7CU)     /*!< BKP data register 25 */
+#define BKP_DATA26                      REG16((BKP) + 0x80U)     /*!< BKP data register 26 */
+#define BKP_DATA27                      REG16((BKP) + 0x84U)     /*!< BKP data register 27 */
+#define BKP_DATA28                      REG16((BKP) + 0x88U)     /*!< BKP data register 28 */
+#define BKP_DATA29                      REG16((BKP) + 0x8CU)     /*!< BKP data register 29 */
+#define BKP_DATA30                      REG16((BKP) + 0x90U)     /*!< BKP data register 30 */
+#define BKP_DATA31                      REG16((BKP) + 0x94U)     /*!< BKP data register 31 */
+#define BKP_DATA32                      REG16((BKP) + 0x98U)     /*!< BKP data register 32 */
+#define BKP_DATA33                      REG16((BKP) + 0x9CU)     /*!< BKP data register 33 */
+#define BKP_DATA34                      REG16((BKP) + 0xA0U)     /*!< BKP data register 34 */
+#define BKP_DATA35                      REG16((BKP) + 0xA4U)     /*!< BKP data register 35 */
+#define BKP_DATA36                      REG16((BKP) + 0xA8U)     /*!< BKP data register 36 */
+#define BKP_DATA37                      REG16((BKP) + 0xACU)     /*!< BKP data register 37 */
+#define BKP_DATA38                      REG16((BKP) + 0xB0U)     /*!< BKP data register 38 */
+#define BKP_DATA39                      REG16((BKP) + 0xB4U)     /*!< BKP data register 39 */
+#define BKP_DATA40                      REG16((BKP) + 0xB8U)     /*!< BKP data register 40 */
+#define BKP_DATA41                      REG16((BKP) + 0xBCU)     /*!< BKP data register 41 */
+#define BKP_OCTL                        REG16((BKP) + 0x2CU)     /*!< RTC signal output control register */
+#define BKP_TPCTL0                      REG16((BKP) + 0x30U)     /*!< tamper pin control register 0 */
+#define BKP_TPCS                        REG16((BKP) + 0x34U)     /*!< tamper control and status register */
+#define BKP_TPCTL1                      REG16((BKP) + 0x38U)     /*!< tamper pin control register 1 */
+
+/* bits definitions */
+/* BKP_DATA */
+#define BKP_DATA                        BITS(0,15)               /*!< backup data */
+
+/* BKP_OCTL */
+#define BKP_OCTL_RCCV                   BITS(0,6)                /*!< RTC clock calibration value */
+#define BKP_OCTL_COEN                   BIT(7)                   /*!< RTC clock calibration output enable */
+#define BKP_OCTL_ASOEN                  BIT(8)                   /*!< RTC alarm or second signal output enable */
+#define BKP_OCTL_ROSEL                  BIT(9)                   /*!< RTC output selection */
+#define BKP_OCTL_CCOSEL                 BIT(14)                  /*!< RTC clock output selection */
+#define BKP_OCTL_CALDIR                 BIT(15)                  /*!< RTC clock calibration direction */
+
+/* BKP_TPCTL0 */
+#define BKP_TPCTL0_TPEN0                BIT(0)                   /*!< tamper0 detection enable */
+#define BKP_TPCTL0_TPAL0                BIT(1)                   /*!< tamper0 pin active level */
+
+/* BKP_TPCS */
+#define BKP_TPCS_TER0                   BIT(0)                   /*!< tamper0 event reset */
+#define BKP_TPCS_TIR0                   BIT(1)                   /*!< tamper0 interrupt reset */
+#define BKP_TPCS_TPIE0                  BIT(2)                   /*!< tamper0 interrupt enable */
+#define BKP_TPCS_TER1                   BIT(5)                   /*!< tamper1 event reset */
+#define BKP_TPCS_TIR1                   BIT(6)                   /*!< tamper1 interrupt reset */
+#define BKP_TPCS_TPIE1                  BIT(7)                   /*!< tamper1 interrupt enable */
+#define BKP_TPCS_TEF0                   BIT(8)                   /*!< tamper0 event flag */
+#define BKP_TPCS_TIF0                   BIT(9)                   /*!< tamper0 interrupt flag */
+#define BKP_TPCS_TEF1                   BIT(14)                  /*!< tamper1 event flag */
+#define BKP_TPCS_TIF1                   BIT(15)                  /*!< tamper1 interrupt flag */
+
+/* BKP_TPCTL1 */
+#define BKP_TPCTL1_TPEN1                BIT(8)                   /*!< tamper1 detection enable */
+#define BKP_TPCTL1_TPAL1                BIT(9)                   /*!< tamper1 pin active level */
+#define BKP_TPCTL1_TPM2                 BIT(14)                  /*!< the second waveform detection enable */
+#define BKP_TPCTL1_TPM1                 BIT(15)                  /*!< the first waveform detection enable */
+
+/* constants definitions */
+/* tamperx definitions */
+typedef enum 
+{
+    TAMPER_0 = 0,                                                /*!< BKP tamper0 */
+    TAMPER_1,                                                    /*!< BKP tamper1 */
+}bkp_tamper_enum;
+
+/* BKP data register number */
+typedef enum 
+{
+    BKP_DATA_0 = 1,                                              /*!< BKP data register 0 */
+    BKP_DATA_1,                                                  /*!< BKP data register 1 */
+    BKP_DATA_2,                                                  /*!< BKP data register 2 */
+    BKP_DATA_3,                                                  /*!< BKP data register 3 */
+    BKP_DATA_4,                                                  /*!< BKP data register 4 */
+    BKP_DATA_5,                                                  /*!< BKP data register 5 */
+    BKP_DATA_6,                                                  /*!< BKP data register 6 */
+    BKP_DATA_7,                                                  /*!< BKP data register 7 */
+    BKP_DATA_8,                                                  /*!< BKP data register 8 */
+    BKP_DATA_9,                                                  /*!< BKP data register 9 */
+    BKP_DATA_10,                                                 /*!< BKP data register 10 */
+    BKP_DATA_11,                                                 /*!< BKP data register 11 */
+    BKP_DATA_12,                                                 /*!< BKP data register 12 */
+    BKP_DATA_13,                                                 /*!< BKP data register 13 */
+    BKP_DATA_14,                                                 /*!< BKP data register 14 */
+    BKP_DATA_15,                                                 /*!< BKP data register 15 */
+    BKP_DATA_16,                                                 /*!< BKP data register 16 */
+    BKP_DATA_17,                                                 /*!< BKP data register 17 */
+    BKP_DATA_18,                                                 /*!< BKP data register 18 */
+    BKP_DATA_19,                                                 /*!< BKP data register 19 */
+    BKP_DATA_20,                                                 /*!< BKP data register 20 */
+    BKP_DATA_21,                                                 /*!< BKP data register 21 */
+    BKP_DATA_22,                                                 /*!< BKP data register 22 */
+    BKP_DATA_23,                                                 /*!< BKP data register 23 */
+    BKP_DATA_24,                                                 /*!< BKP data register 24 */
+    BKP_DATA_25,                                                 /*!< BKP data register 25 */
+    BKP_DATA_26,                                                 /*!< BKP data register 26 */
+    BKP_DATA_27,                                                 /*!< BKP data register 27 */
+    BKP_DATA_28,                                                 /*!< BKP data register 28 */
+    BKP_DATA_29,                                                 /*!< BKP data register 29 */
+    BKP_DATA_30,                                                 /*!< BKP data register 30 */
+    BKP_DATA_31,                                                 /*!< BKP data register 31 */
+    BKP_DATA_32,                                                 /*!< BKP data register 32 */
+    BKP_DATA_33,                                                 /*!< BKP data register 33 */
+    BKP_DATA_34,                                                 /*!< BKP data register 34 */
+    BKP_DATA_35,                                                 /*!< BKP data register 35 */
+    BKP_DATA_36,                                                 /*!< BKP data register 36 */
+    BKP_DATA_37,                                                 /*!< BKP data register 37 */
+    BKP_DATA_38,                                                 /*!< BKP data register 38 */
+    BKP_DATA_39,                                                 /*!< BKP data register 39 */
+    BKP_DATA_40,                                                 /*!< BKP data register 40 */
+    BKP_DATA_41,                                                 /*!< BKP data register 41 */
+}bkp_data_register_enum;
+
+/* BKP register */
+#define BKP_DATA0_9(number)             REG16((BKP) + 0x04U + (number) * 0x04U)
+#define BKP_DATA10_41(number)           REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
+
+/* get data of BKP data register */
+#define BKP_DATA_GET(regval)            GET_BITS((uint32_t)(regval), 0, 15)
+
+/* RTC clock calibration value */
+#define OCTL_RCCV(regval)               (BITS(0,6) & ((uint32_t)(regval) << 0))
+
+/* RTC output selection */
+#define RTC_OUTPUT_ALARM_PULSE          ((uint16_t)0x0000U)      /*!< RTC alarm pulse is selected as the RTC output */
+#define RTC_OUTPUT_SECOND_PULSE         ((uint16_t)0x0200U)      /*!< RTC second pulse is selected as the RTC output */
+
+/* RTC clock output selection */
+#define RTC_CLOCK_DIV64                 ((uint16_t)0x0000U)      /*!< RTC clock div 64 */
+#define RTC_CLOCK_DIV1                  ((uint16_t)0x4000U)      /*!< RTC clock div 1 */
+
+/* RTC clock calibration direction */
+#define RTC_CLOCK_SLOWED_DOWN           ((uint16_t)0x0000U)      /*!< RTC clock slow down */
+#define RTC_CLOCK_SPEED_UP              ((uint16_t)0x8000U)      /*!< RTC clock speed up */
+
+/* tamper pin active level */
+#define TAMPER_PIN_ACTIVE_HIGH          ((uint16_t)0x0000U)      /*!< the tamper pin is active high */
+#define TAMPER_PIN_ACTIVE_LOW           ((uint16_t)0x0002U)      /*!< the tamper pin is active low */
+
+/* tamper flag */
+#define BKP_FLAG_TAMPER0                BKP_TPCS_TEF0            /*!< tamper0 event flag */
+#define BKP_FLAG_TAMPER1_WAVEDETECT     BKP_TPCS_TEF1            /*!< tamper1/waveform detect event flag */
+
+/* tamper interrupt flag */
+#define BKP_INT_FLAG_TAMPER0            BKP_TPCS_TIF0            /*!< tamper0 interrupt flag */
+#define BKP_INT_FLAG_TAMPER1_WAVEDETECT BKP_TPCS_TIF1            /*!< tamper1/waveform detect interrupt flag */
+
+/* waveform detection mode */
+#define BKP_WAVEFORM_DETECT_1           BKP_TPCTL1_TPM1          /*!< the first waveform detection */
+#define BKP_WAVEFORM_DETECT_2           BKP_TPCTL1_TPM2          /*!< the second waveform detection */
+
+/* function declarations */
+/* initialization functions */
+/* reset BKP registers */
+void bkp_deinit(void);
+/* write BKP data register */
+void bkp_data_write(bkp_data_register_enum register_number, uint16_t data);
+/* read BKP data register */
+uint16_t bkp_data_read(bkp_data_register_enum register_number);
+
+/* function configuration */
+/* RTC related functions */
+/* enable RTC clock calibration output */
+void bkp_rtc_calibration_output_enable(void);
+/* disable RTC clock calibration output */
+void bkp_rtc_calibration_output_disable(void);
+/* enable RTC alarm or second signal output */
+void bkp_rtc_signal_output_enable(void);
+/* disable RTC alarm or second signal output */
+void bkp_rtc_signal_output_disable(void);
+/* select RTC output */
+void bkp_rtc_output_select(uint16_t outputsel);
+/* RTC clock output selection */
+void bkp_rtc_clock_output_select(uint16_t clocksel);
+/* RTC clock calibration direction */
+void bkp_rtc_clock_calibration_direction(uint16_t direction);
+/* set RTC clock calibration value */
+void bkp_rtc_calibration_value_set(uint8_t value);
+
+/* tamper pin related functions */
+/* enable tamper pin detection */
+void bkp_tamper_detection_enable(bkp_tamper_enum tamperx);
+/* disable tamper pin detection */
+void bkp_tamper_detection_disable(bkp_tamper_enum tamperx);
+/* set tamper pin active level */
+void bkp_tamper_active_level_set(bkp_tamper_enum tamperx, uint16_t level);
+
+/* interrupt & flag functions */
+/* enable tamper pin interrupt */
+void bkp_tamper_interrupt_enable(bkp_tamper_enum tamperx);
+/* disable tamper pin interrupt */
+void bkp_tamper_interrupt_disable(bkp_tamper_enum tamperx);
+/* waveform detect configure */
+void bkp_waveform_detect_enable(uint16_t waveform_detect_mode, ControlStatus newvalue);
+/* get BKP flag state */
+FlagStatus bkp_flag_get(uint16_t flag);
+/* clear BKP flag state */
+void bkp_flag_clear(uint16_t flag);
+/* get BKP interrupt flag state */
+FlagStatus bkp_interrupt_flag_get(uint16_t flag);
+/* clear BKP interrupt flag state */
+void bkp_interrupt_flag_clear(uint16_t flag);
+
+#endif /* GD32F20X_BKP_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_can.h

@@ -0,0 +1,729 @@
+/*!
+    \file  gd32f20x_can.h
+    \brief definitions for the CAN
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_CAN_H
+#define GD32F20X_CAN_H
+
+#include "gd32f20x.h"
+
+/* CAN definitions */
+#define CAN0                               CAN_BASE                      /*!< CAN0 base address */
+#define CAN1                               (CAN0 + 0x00000400U)          /*!< CAN1 base address */
+
+/* registers definitions */
+#define CAN_CTL(canx)                      REG32((canx) + 0x00U)         /*!< CAN control register */
+#define CAN_STAT(canx)                     REG32((canx) + 0x04U)         /*!< CAN status register */
+#define CAN_TSTAT(canx)                    REG32((canx) + 0x08U)         /*!< CAN transmit status register*/
+#define CAN_RFIFO0(canx)                   REG32((canx) + 0x0CU)         /*!< CAN receive FIFO0 register */
+#define CAN_RFIFO1(canx)                   REG32((canx) + 0x10U)         /*!< CAN receive FIFO1 register */
+#define CAN_INTEN(canx)                    REG32((canx) + 0x14U)         /*!< CAN interrupt enable register */
+#define CAN_ERR(canx)                      REG32((canx) + 0x18U)         /*!< CAN error register */
+#define CAN_BT(canx)                       REG32((canx) + 0x1CU)         /*!< CAN bit timing register */
+#define CAN_TMI0(canx)                     REG32((canx) + 0x180U)        /*!< CAN transmit mailbox0 identifier register */
+#define CAN_TMP0(canx)                     REG32((canx) + 0x184U)        /*!< CAN transmit mailbox0 property register */
+#define CAN_TMDATA00(canx)                 REG32((canx) + 0x188U)        /*!< CAN transmit mailbox0 data0 register */
+#define CAN_TMDATA10(canx)                 REG32((canx) + 0x18CU)        /*!< CAN transmit mailbox0 data1 register */
+#define CAN_TMI1(canx)                     REG32((canx) + 0x190U)        /*!< CAN transmit mailbox1 identifier register */
+#define CAN_TMP1(canx)                     REG32((canx) + 0x194U)        /*!< CAN transmit mailbox1 property register */
+#define CAN_TMDATA01(canx)                 REG32((canx) + 0x198U)        /*!< CAN transmit mailbox1 data0 register */
+#define CAN_TMDATA11(canx)                 REG32((canx) + 0x19CU)        /*!< CAN transmit mailbox1 data1 register */
+#define CAN_TMI2(canx)                     REG32((canx) + 0x1A0U)        /*!< CAN transmit mailbox2 identifier register */
+#define CAN_TMP2(canx)                     REG32((canx) + 0x1A4U)        /*!< CAN transmit mailbox2 property register */
+#define CAN_TMDATA02(canx)                 REG32((canx) + 0x1A8U)        /*!< CAN transmit mailbox2 data0 register */
+#define CAN_TMDATA12(canx)                 REG32((canx) + 0x1ACU)        /*!< CAN transmit mailbox2 data1 register */
+#define CAN_RFIFOMI0(canx)                 REG32((canx) + 0x1B0U)        /*!< CAN receive FIFO0 mailbox identifier register */
+#define CAN_RFIFOMP0(canx)                 REG32((canx) + 0x1B4U)        /*!< CAN receive FIFO0 mailbox property register */
+#define CAN_RFIFOMDATA00(canx)             REG32((canx) + 0x1B8U)        /*!< CAN receive FIFO0 mailbox data0 register */
+#define CAN_RFIFOMDATA10(canx)             REG32((canx) + 0x1BCU)        /*!< CAN receive FIFO0 mailbox data1 register */
+#define CAN_RFIFOMI1(canx)                 REG32((canx) + 0x1C0U)        /*!< CAN receive FIFO1 mailbox identifier register */
+#define CAN_RFIFOMP1(canx)                 REG32((canx) + 0x1C4U)        /*!< CAN receive FIFO1 mailbox property register */
+#define CAN_RFIFOMDATA01(canx)             REG32((canx) + 0x1C8U)        /*!< CAN receive FIFO1 mailbox data0 register */
+#define CAN_RFIFOMDATA11(canx)             REG32((canx) + 0x1CCU)        /*!< CAN receive FIFO1 mailbox data1 register */
+#define CAN_FCTL(canx)                     REG32((canx) + 0x200U)        /*!< CAN filter control register */
+#define CAN_FMCFG(canx)                    REG32((canx) + 0x204U)        /*!< CAN filter mode register */
+#define CAN_FSCFG(canx)                    REG32((canx) + 0x20CU)        /*!< CAN filter scale register */
+#define CAN_FAFIFO(canx)                   REG32((canx) + 0x214U)        /*!< CAN filter associated FIFO register */
+#define CAN_FW(canx)                       REG32((canx) + 0x21CU)        /*!< CAN filter working register */
+#define CAN_F0DATA0(canx)                  REG32((canx) + 0x240U)        /*!< CAN filter 0 data 0 register */
+#define CAN_F1DATA0(canx)                  REG32((canx) + 0x248U)        /*!< CAN filter 1 data 0 register */
+#define CAN_F2DATA0(canx)                  REG32((canx) + 0x250U)        /*!< CAN filter 2 data 0 register */
+#define CAN_F3DATA0(canx)                  REG32((canx) + 0x258U)        /*!< CAN filter 3 data 0 register */
+#define CAN_F4DATA0(canx)                  REG32((canx) + 0x260U)        /*!< CAN filter 4 data 0 register */
+#define CAN_F5DATA0(canx)                  REG32((canx) + 0x268U)        /*!< CAN filter 5 data 0 register */
+#define CAN_F6DATA0(canx)                  REG32((canx) + 0x270U)        /*!< CAN filter 6 data 0 register */
+#define CAN_F7DATA0(canx)                  REG32((canx) + 0x278U)        /*!< CAN filter 7 data 0 register */
+#define CAN_F8DATA0(canx)                  REG32((canx) + 0x280U)        /*!< CAN filter 8 data 0 register */
+#define CAN_F9DATA0(canx)                  REG32((canx) + 0x288U)        /*!< CAN filter 9 data 0 register */
+#define CAN_F10DATA0(canx)                 REG32((canx) + 0x290U)        /*!< CAN filter 10 data 0 register */
+#define CAN_F11DATA0(canx)                 REG32((canx) + 0x298U)        /*!< CAN filter 11 data 0 register */
+#define CAN_F12DATA0(canx)                 REG32((canx) + 0x2A0U)        /*!< CAN filter 12 data 0 register */
+#define CAN_F13DATA0(canx)                 REG32((canx) + 0x2A8U)        /*!< CAN filter 13 data 0 register */
+#define CAN_F14DATA0(canx)                 REG32((canx) + 0x2B0U)        /*!< CAN filter 14 data 0 register */
+#define CAN_F15DATA0(canx)                 REG32((canx) + 0x2B8U)        /*!< CAN filter 15 data 0 register */
+#define CAN_F16DATA0(canx)                 REG32((canx) + 0x2C0U)        /*!< CAN filter 16 data 0 register */
+#define CAN_F17DATA0(canx)                 REG32((canx) + 0x2C8U)        /*!< CAN filter 17 data 0 register */
+#define CAN_F18DATA0(canx)                 REG32((canx) + 0x2D0U)        /*!< CAN filter 18 data 0 register */
+#define CAN_F19DATA0(canx)                 REG32((canx) + 0x2D8U)        /*!< CAN filter 19 data 0 register */
+#define CAN_F20DATA0(canx)                 REG32((canx) + 0x2E0U)        /*!< CAN filter 20 data 0 register */
+#define CAN_F21DATA0(canx)                 REG32((canx) + 0x2E8U)        /*!< CAN filter 21 data 0 register */
+#define CAN_F22DATA0(canx)                 REG32((canx) + 0x2F0U)        /*!< CAN filter 22 data 0 register */
+#define CAN_F23DATA0(canx)                 REG32((canx) + 0x3F8U)        /*!< CAN filter 23 data 0 register */
+#define CAN_F24DATA0(canx)                 REG32((canx) + 0x300U)        /*!< CAN filter 24 data 0 register */
+#define CAN_F25DATA0(canx)                 REG32((canx) + 0x308U)        /*!< CAN filter 25 data 0 register */
+#define CAN_F26DATA0(canx)                 REG32((canx) + 0x310U)        /*!< CAN filter 26 data 0 register */
+#define CAN_F27DATA0(canx)                 REG32((canx) + 0x318U)        /*!< CAN filter 27 data 0 register */
+#define CAN_F0DATA1(canx)                  REG32((canx) + 0x244U)        /*!< CAN filter 0 data 1 register */
+#define CAN_F1DATA1(canx)                  REG32((canx) + 0x24CU)        /*!< CAN filter 1 data 1 register */
+#define CAN_F2DATA1(canx)                  REG32((canx) + 0x254U)        /*!< CAN filter 2 data 1 register */
+#define CAN_F3DATA1(canx)                  REG32((canx) + 0x25CU)        /*!< CAN filter 3 data 1 register */
+#define CAN_F4DATA1(canx)                  REG32((canx) + 0x264U)        /*!< CAN filter 4 data 1 register */
+#define CAN_F5DATA1(canx)                  REG32((canx) + 0x26CU)        /*!< CAN filter 5 data 1 register */
+#define CAN_F6DATA1(canx)                  REG32((canx) + 0x274U)        /*!< CAN filter 6 data 1 register */
+#define CAN_F7DATA1(canx)                  REG32((canx) + 0x27CU)        /*!< CAN filter 7 data 1 register */
+#define CAN_F8DATA1(canx)                  REG32((canx) + 0x284U)        /*!< CAN filter 8 data 1 register */
+#define CAN_F9DATA1(canx)                  REG32((canx) + 0x28CU)        /*!< CAN filter 9 data 1 register */
+#define CAN_F10DATA1(canx)                 REG32((canx) + 0x294U)        /*!< CAN filter 10 data 1 register */
+#define CAN_F11DATA1(canx)                 REG32((canx) + 0x29CU)        /*!< CAN filter 11 data 1 register */
+#define CAN_F12DATA1(canx)                 REG32((canx) + 0x2A4U)        /*!< CAN filter 12 data 1 register */
+#define CAN_F13DATA1(canx)                 REG32((canx) + 0x2ACU)        /*!< CAN filter 13 data 1 register */
+#define CAN_F14DATA1(canx)                 REG32((canx) + 0x2B4U)        /*!< CAN filter 14 data 1 register */
+#define CAN_F15DATA1(canx)                 REG32((canx) + 0x2BCU)        /*!< CAN filter 15 data 1 register */
+#define CAN_F16DATA1(canx)                 REG32((canx) + 0x2C4U)        /*!< CAN filter 16 data 1 register */
+#define CAN_F17DATA1(canx)                 REG32((canx) + 0x24CU)        /*!< CAN filter 17 data 1 register */
+#define CAN_F18DATA1(canx)                 REG32((canx) + 0x2D4U)        /*!< CAN filter 18 data 1 register */
+#define CAN_F19DATA1(canx)                 REG32((canx) + 0x2DCU)        /*!< CAN filter 19 data 1 register */
+#define CAN_F20DATA1(canx)                 REG32((canx) + 0x2E4U)        /*!< CAN filter 20 data 1 register */
+#define CAN_F21DATA1(canx)                 REG32((canx) + 0x2ECU)        /*!< CAN filter 21 data 1 register */
+#define CAN_F22DATA1(canx)                 REG32((canx) + 0x2F4U)        /*!< CAN filter 22 data 1 register */
+#define CAN_F23DATA1(canx)                 REG32((canx) + 0x2FCU)        /*!< CAN filter 23 data 1 register */
+#define CAN_F24DATA1(canx)                 REG32((canx) + 0x304U)        /*!< CAN filter 24 data 1 register */
+#define CAN_F25DATA1(canx)                 REG32((canx) + 0x30CU)        /*!< CAN filter 25 data 1 register */
+#define CAN_F26DATA1(canx)                 REG32((canx) + 0x314U)        /*!< CAN filter 26 data 1 register */
+#define CAN_F27DATA1(canx)                 REG32((canx) + 0x31CU)        /*!< CAN filter 27 data 1 register */
+
+/* CAN transmit mailbox bank */
+#define CAN_TMI(canx, bank)                REG32((canx) + 0x180U + ((bank) * 0x10U))      /*!< CAN transmit mailbox identifier register */
+#define CAN_TMP(canx, bank)                REG32((canx) + 0x184U + ((bank) * 0x10U))      /*!< CAN transmit mailbox property register */
+#define CAN_TMDATA0(canx, bank)            REG32((canx) + 0x188U + ((bank) * 0x10U))      /*!< CAN transmit mailbox data0 register */
+#define CAN_TMDATA1(canx, bank)            REG32((canx) + 0x18CU + ((bank) * 0x10U))      /*!< CAN transmit mailbox data1 register */
+
+/* CAN filter bank */
+#define CAN_FDATA0(canx, bank)             REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
+#define CAN_FDATA1(canx, bank)             REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
+
+/* CAN receive fifo mailbox bank */
+#define CAN_RFIFOMI(canx, bank)            REG32((canx) + 0x1B0U + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox identifier register */
+#define CAN_RFIFOMP(canx, bank)            REG32((canx) + 0x1B4U + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox property register */
+#define CAN_RFIFOMDATA0(canx, bank)        REG32((canx) + 0x1B8U + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox data0 register */
+#define CAN_RFIFOMDATA1(canx, bank)        REG32((canx) + 0x1BCU + ((bank) * 0x10U))      /*!< CAN receive FIFO mailbox data1 register */
+
+/* bits definitions */
+/* CAN_CTL */
+#define CAN_CTL_IWMOD                      BIT(0)                       /*!< initial working mode */
+#define CAN_CTL_SLPWMOD                    BIT(1)                       /*!< sleep working mode */
+#define CAN_CTL_TFO                        BIT(2)                       /*!< transmit FIFO order */
+#define CAN_CTL_RFOD                       BIT(3)                       /*!< receive FIFO overwrite disable */
+#define CAN_CTL_ARD                        BIT(4)                       /*!< automatic retransmission disable */
+#define CAN_CTL_AWU                        BIT(5)                       /*!< automatic wakeup */
+#define CAN_CTL_ABOR                       BIT(6)                       /*!< automatic bus-off recovery */
+#define CAN_CTL_TTC                        BIT(7)                       /*!< time triggered communication */
+#define CAN_CTL_SWRST                      BIT(15)                      /*!< CAN software reset */
+#define CAN_CTL_DFZ                        BIT(16)                      /*!< CAN debug freeze */
+
+/* CAN_STAT */
+#define CAN_STAT_IWS                       BIT(0)                       /*!< initial working state */
+#define CAN_STAT_SLPWS                     BIT(1)                       /*!< sleep working state */
+#define CAN_STAT_ERRIF                     BIT(2)                       /*!< error interrupt flag*/
+#define CAN_STAT_WUIF                      BIT(3)                       /*!< status change interrupt flag of wakeup from sleep working mode */
+#define CAN_STAT_SLPIF                     BIT(4)                       /*!< status change interrupt flag of sleep working mode entering */
+#define CAN_STAT_TS                        BIT(8)                       /*!< transmitting state */
+#define CAN_STAT_RS                        BIT(9)                       /*!< receiving state */
+#define CAN_STAT_LASTRX                    BIT(10)                      /*!< last sample value of rx pin */
+#define CAN_STAT_RXL                       BIT(11)                      /*!< CAN rx signal */
+
+/* CAN_TSTAT */
+#define CAN_TSTAT_MTF0                     BIT(0)                       /*!< mailbox0 transmit finished */
+#define CAN_TSTAT_MTFNERR0                 BIT(1)                       /*!< mailbox0 transmit finished and no error */
+#define CAN_TSTAT_MAL0                     BIT(2)                       /*!< mailbox0 arbitration lost */
+#define CAN_TSTAT_MTE0                     BIT(3)                       /*!< mailbox0 transmit error */
+#define CAN_TSTAT_MST0                     BIT(7)                       /*!< mailbox0 stop transmitting */
+#define CAN_TSTAT_MTF1                     BIT(8)                       /*!< mailbox1 transmit finished */
+#define CAN_TSTAT_MTFNERR1                 BIT(9)                       /*!< mailbox1 transmit finished and no error */
+#define CAN_TSTAT_MAL1                     BIT(10)                      /*!< mailbox1 arbitration lost */
+#define CAN_TSTAT_MTE1                     BIT(11)                      /*!< mailbox1 transmit error */
+#define CAN_TSTAT_MST1                     BIT(15)                      /*!< mailbox1 stop transmitting */
+#define CAN_TSTAT_MTF2                     BIT(16)                      /*!< mailbox2 transmit finished */
+#define CAN_TSTAT_MTFNERR2                 BIT(17)                      /*!< mailbox2 transmit finished and no error */
+#define CAN_TSTAT_MAL2                     BIT(18)                      /*!< mailbox2 arbitration lost */
+#define CAN_TSTAT_MTE2                     BIT(19)                      /*!< mailbox2 transmit error */
+#define CAN_TSTAT_MST2                     BIT(23)                      /*!< mailbox2 stop transmitting */
+#define CAN_TSTAT_NUM                      BITS(24,25)                  /*!< mailbox number */
+#define CAN_TSTAT_TME0                     BIT(26)                      /*!< transmit mailbox0 empty */
+#define CAN_TSTAT_TME1                     BIT(27)                      /*!< transmit mailbox1 empty */
+#define CAN_TSTAT_TME2                     BIT(28)                      /*!< transmit mailbox2 empty */
+#define CAN_TSTAT_TMLS0                    BIT(29)                      /*!< last sending priority flag for mailbox0 */
+#define CAN_TSTAT_TMLS1                    BIT(30)                      /*!< last sending priority flag for mailbox1 */
+#define CAN_TSTAT_TMLS2                    BIT(31)                      /*!< last sending priority flag for mailbox2 */
+
+/* CAN_RFIFO0 */
+#define CAN_RFIFO0_RFL0                    BITS(0,1)                    /*!< receive FIFO0 length */
+#define CAN_RFIFO0_RFF0                    BIT(3)                       /*!< receive FIFO0 full */
+#define CAN_RFIFO0_RFO0                    BIT(4)                       /*!< receive FIFO0 overfull */
+#define CAN_RFIFO0_RFD0                    BIT(5)                       /*!< receive FIFO0 dequeue */
+
+/* CAN_RFIFO1 */
+#define CAN_RFIFO1_RFL1                    BITS(0,1)                    /*!< receive FIFO1 length */
+#define CAN_RFIFO1_RFF1                    BIT(3)                       /*!< receive FIFO1 full */
+#define CAN_RFIFO1_RFO1                    BIT(4)                       /*!< receive FIFO1 overfull */
+#define CAN_RFIFO1_RFD1                    BIT(5)                       /*!< receive FIFO1 dequeue */
+
+/* CAN_INTEN */
+#define CAN_INTEN_TMEIE                    BIT(0)                       /*!< transmit mailbox empty interrupt enable */
+#define CAN_INTEN_RFNEIE0                  BIT(1)                       /*!< receive FIFO0 not empty interrupt enable */
+#define CAN_INTEN_RFFIE0                   BIT(2)                       /*!< receive FIFO0 full interrupt enable */
+#define CAN_INTEN_RFOIE0                   BIT(3)                       /*!< receive FIFO0 overfull interrupt enable */
+#define CAN_INTEN_RFNEIE1                  BIT(4)                       /*!< receive FIFO1 not empty interrupt enable */
+#define CAN_INTEN_RFFIE1                   BIT(5)                       /*!< receive FIFO1 full interrupt enable */
+#define CAN_INTEN_RFOIE1                   BIT(6)                       /*!< receive FIFO1 overfull interrupt enable */
+#define CAN_INTEN_WERRIE                   BIT(8)                       /*!< warning error interrupt enable */
+#define CAN_INTEN_PERRIE                   BIT(9)                       /*!< passive error interrupt enable */
+#define CAN_INTEN_BOIE                     BIT(10)                      /*!< bus-off interrupt enable */
+#define CAN_INTEN_ERRNIE                   BIT(11)                      /*!< error number interrupt enable */
+#define CAN_INTEN_ERRIE                    BIT(15)                      /*!< error interrupt enable */
+#define CAN_INTEN_WIE                      BIT(16)                      /*!< wakeup interrupt enable */
+#define CAN_INTEN_SLPWIE                   BIT(17)                      /*!< sleep working interrupt enable */
+
+/* CAN_ERR */
+#define CAN_ERR_WERR                       BIT(0)                       /*!< warning error */
+#define CAN_ERR_PERR                       BIT(1)                       /*!< passive error */
+#define CAN_ERR_BOERR                      BIT(2)                       /*!< bus-off error */
+#define CAN_ERR_ERRN                       BITS(4,6)                    /*!< error number */
+#define CAN_ERR_TECNT                      BITS(16,23)                  /*!< transmit error count */
+#define CAN_ERR_RECNT                      BITS(24,31)                  /*!< receive error count */
+
+/* CAN_BT */
+#define CAN_BT_BAUDPSC                     BITS(0,9)                    /*!< baudrate prescaler */
+#define CAN_BT_BS1                         BITS(16,19)                  /*!< bit segment 1 */
+#define CAN_BT_BS2                         BITS(20,22)                  /*!< bit segment 2 */
+#define CAN_BT_SJW                         BITS(24,25)                  /*!< resynchronization jump width */
+#define CAN_BT_LCMOD                       BIT(30)                      /*!< loopback communication mode */
+#define CAN_BT_SCMOD                       BIT(31)                      /*!< silent communication mode */
+
+/* CAN_TMIx */
+#define CAN_TMI_TEN                        BIT(0)                       /*!< transmit enable */
+#define CAN_TMI_FT                         BIT(1)                       /*!< frame type */
+#define CAN_TMI_FF                         BIT(2)                       /*!< frame format */
+#define CAN_TMI_EFID                       BITS(3,31)                   /*!< the frame identifier */
+#define CAN_TMI_SFID                       BITS(21,31)                  /*!< the frame identifier */
+
+/* CAN_TMPx */
+#define CAN_TMP_DLENC                      BITS(0,3)                    /*!< data length code */
+#define CAN_TMP_TSEN                       BIT(8)                       /*!< time stamp enable */
+#define CAN_TMP_TS                         BITS(16,31)                  /*!< time stamp */
+
+/* CAN_TMDATA0x */
+#define CAN_TMDATA0_DB0                    BITS(0,7)                    /*!< transmit data byte 0 */
+#define CAN_TMDATA0_DB1                    BITS(8,15)                   /*!< transmit data byte 1 */
+#define CAN_TMDATA0_DB2                    BITS(16,23)                  /*!< transmit data byte 2 */
+#define CAN_TMDATA0_DB3                    BITS(24,31)                  /*!< transmit data byte 3 */
+
+/* CAN_TMDATA1x */
+#define CAN_TMDATA1_DB4                    BITS(0,7)                    /*!< transmit data byte 4 */
+#define CAN_TMDATA1_DB5                    BITS(8,15)                   /*!< transmit data byte 5 */
+#define CAN_TMDATA1_DB6                    BITS(16,23)                  /*!< transmit data byte 6 */
+#define CAN_TMDATA1_DB7                    BITS(24,31)                  /*!< transmit data byte 7 */
+
+/* CAN_RFIFOMIx */
+#define CAN_RFIFOMI_FT                     BIT(1)                       /*!< frame type */
+#define CAN_RFIFOMI_FF                     BIT(2)                       /*!< frame format */
+#define CAN_RFIFOMI_EFID                   BITS(3,31)                   /*!< the frame identifier */
+#define CAN_RFIFOMI_SFID                   BITS(21,31)                  /*!< the frame identifier */
+
+/* CAN_RFIFOMPx */
+#define CAN_RFIFOMP_DLENC                  BITS(0,3)                    /*!< receive data length code */
+#define CAN_RFIFOMP_FI                     BITS(8,15)                   /*!< filter index */
+#define CAN_RFIFOMP_TS                     BITS(16,31)                  /*!< time stamp */
+
+/* CAN_RFIFOMDATA0x */
+#define CAN_RFIFOMDATA0_DB0                BITS(0,7)                    /*!< receive data byte 0 */
+#define CAN_RFIFOMDATA0_DB1                BITS(8,15)                   /*!< receive data byte 1 */
+#define CAN_RFIFOMDATA0_DB2                BITS(16,23)                  /*!< receive data byte 2 */
+#define CAN_RFIFOMDATA0_DB3                BITS(24,31)                  /*!< receive data byte 3 */
+
+/* CAN_RFIFOMDATA1x */
+#define CAN_RFIFOMDATA1_DB4                BITS(0,7)                    /*!< receive data byte 4 */
+#define CAN_RFIFOMDATA1_DB5                BITS(8,15)                   /*!< receive data byte 5 */
+#define CAN_RFIFOMDATA1_DB6                BITS(16,23)                  /*!< receive data byte 6 */
+#define CAN_RFIFOMDATA1_DB7                BITS(24,31)                  /*!< receive data byte 7 */
+
+/* CAN_FCTL */
+#define CAN_FCTL_FLD                       BIT(0)                       /*!< filter lock disable */
+#define CAN_FCTL_HBC1F                     BITS(8,13)                   /*!< header bank of CAN1 filter */
+
+/* CAN_FMCFG */
+#define CAN_FMCFG_FMOD(regval)             BIT(regval)                  /*!< filter mode, list or mask*/
+
+/* CAN_FSCFG */
+#define CAN_FSCFG_FS(regval)               BIT(regval)                  /*!< filter scale, 32 bits or 16 bits*/
+
+/* CAN_FAFIFO */
+#define CAN_FAFIFOR_FAF(regval)            BIT(regval)                  /*!< filter associated with FIFO */
+
+/* CAN_FW */
+#define CAN_FW_FW(regval)                  BIT(regval)                  /*!< filter working */
+
+/* CAN_FxDATAy */
+#define CAN_FDATA_FD(regval)               BIT(regval)                  /*!< filter data */
+
+/* constants definitions */
+/* define the CAN bit position and its register index offset */
+#define CAN_REGIDX_BIT(regidx, bitpos)              (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define CAN_REG_VAL(canx, offset)                   (REG32((canx) + ((uint32_t)(offset) >> 6)))
+#define CAN_BIT_POS(val)                            ((uint32_t)(val) & 0x1FU)
+
+#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1)   (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
+#define CAN_REG_VALS(canx, offset)                  (REG32((canx) + ((uint32_t)(offset) >> 12)))
+#define CAN_BIT_POS0(val)                           (((uint32_t)(val) >> 6) & 0x1FU)
+#define CAN_BIT_POS1(val)                           ((uint32_t)(val) & 0x1FU)
+
+/* register offset */
+#define STAT_REG_OFFSET                    ((uint8_t)0x04U)             /*!< STAT register offset */
+#define TSTAT_REG_OFFSET                   ((uint8_t)0x08U)             /*!< TSTAT register offset */
+#define RFIFO0_REG_OFFSET                  ((uint8_t)0x0CU)             /*!< RFIFO0 register offset */
+#define RFIFO1_REG_OFFSET                  ((uint8_t)0x10U)             /*!< RFIFO1 register offset */
+#define ERR_REG_OFFSET                     ((uint8_t)0x18U)             /*!< ERR register offset */
+
+/* CAN flags */
+typedef enum
+{
+    /* flags in TSTAT register */
+    CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U),              /*!< mailbox 2 transmit error */ 
+    CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U),              /*!< mailbox 1 transmit error */ 
+    CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U),               /*!< mailbox 0 transmit error */ 
+    CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U),              /*!< mailbox 2 transmit finished */ 
+    CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U),               /*!< mailbox 1 transmit finished */ 
+    CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U),               /*!< mailbox 0 transmit finished */ 
+    /* flags in RFIFO0 register */
+    CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U),              /*!< receive FIFO0 overfull */ 
+    CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U),              /*!< receive FIFO0 full */ 
+    /* flags in RFIFO1 register */
+    CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U),              /*!< receive FIFO1 overfull */ 
+    CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U),              /*!< receive FIFO1 full */ 
+    /* flags in ERR register */
+    CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U),                /*!< bus-off error */ 
+    CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U),                 /*!< passive error */ 
+    CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U),                 /*!< warning error */ 
+}can_flag_enum;
+
+/* CAN interrupt flags */
+typedef enum
+{
+    /* interrupt flags in STAT register */
+    CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U),     /*!< status change interrupt flag of sleep working mode entering */ 
+    CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16),       /*!< status change interrupt flag of wakeup from sleep working mode */ 
+    CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15),      /*!< error interrupt flag */ 
+    /* interrupt flags in TSTAT register */
+    CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U),     /*!< mailbox 2 transmit finished interrupt flag */
+    CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U),      /*!< mailbox 1 transmit finished interrupt flag */
+    CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U),      /*!< mailbox 0 transmit finished interrupt flag */
+    /* interrupt flags in RFIFO0 register */
+    CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U),     /*!< receive FIFO0 overfull interrupt flag */
+    CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U),     /*!< receive FIFO0 full interrupt flag */
+    /* interrupt flags in RFIFO0 register */
+    CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U),     /*!< receive FIFO1 overfull interrupt flag */
+    CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U),     /*!< receive FIFO1 full interrupt flag */
+}can_interrupt_flag_enum;
+
+/* CAN initiliaze parameters structure */
+typedef struct
+{
+    uint8_t working_mode;                                               /*!< CAN working mode */ 
+    uint8_t resync_jump_width;                                          /*!< CAN resynchronization jump width */
+    uint8_t time_segment_1;                                             /*!< time segment 1 */
+    uint8_t time_segment_2;                                             /*!< time segment 2 */
+    ControlStatus time_triggered;                                       /*!< time triggered communication mode */
+    ControlStatus auto_bus_off_recovery;                                /*!< automatic bus-off recovery */
+    ControlStatus auto_wake_up;                                         /*!< automatic wake-up mode */
+    ControlStatus auto_retrans;                                         /*!< automatic retransmission mode disable */
+    ControlStatus rec_fifo_overwrite;                                   /*!< receive FIFO overwrite mode */
+    ControlStatus trans_fifo_order;                                     /*!< transmit FIFO order */
+    uint16_t prescaler;                                                 /*!< baudrate prescaler */
+}can_parameter_struct;
+
+/* CAN transmit message structure */
+typedef struct
+{
+    uint32_t tx_sfid;                                                   /*!< standard format frame identifier */
+    uint32_t tx_efid;                                                   /*!< extended format frame identifier */
+    uint8_t tx_ff;                                                      /*!< format of frame, standard or extended format */
+    uint8_t tx_ft;                                                      /*!< type of frame, data or remote */
+    uint8_t tx_dlen;                                                    /*!< data length */
+    uint8_t tx_data[8];                                                 /*!< transmit data */
+}can_trasnmit_message_struct;
+
+/* CAN receive message structure */
+typedef struct
+{
+    uint32_t rx_sfid;                                                   /*!< standard format frame identifier */
+    uint32_t rx_efid;                                                   /*!< extended format frame identifier */
+    uint8_t rx_ff;                                                      /*!< format of frame, standard or extended format */
+    uint8_t rx_ft;                                                      /*!< type of frame, data or remote */
+    uint8_t rx_dlen;                                                    /*!< data length */
+    uint8_t rx_data[8];                                                 /*!< receive data */
+    uint8_t rx_fi;                                                      /*!< filtering index */
+} can_receive_message_struct;
+
+/* CAN filter parameters structure */
+typedef struct
+{
+    uint16_t filter_list_high;                                          /*!< filter list number high bits*/
+    uint16_t filter_list_low;                                           /*!< filter list number low bits */
+    uint16_t filter_mask_high;                                          /*!< filter mask number high bits */
+    uint16_t filter_mask_low;                                           /*!< filter mask number low bits */
+    uint16_t filter_fifo_number;                                        /*!< receive FIFO associated with the filter */
+    uint16_t filter_number;                                             /*!< filter number */
+    uint16_t filter_mode;                                               /*!< filter mode, list or mask */
+    uint16_t filter_bits;                                               /*!< filter scale */
+    ControlStatus filter_enable;                                        /*!< filter work or not */
+}can_filter_parameter_struct;
+
+/* CAN errors */
+typedef enum
+{
+    CAN_ERROR_NONE = 0,                                                 /*!< no error */
+    CAN_ERROR_FILL,                                                     /*!< fill error */
+    CAN_ERROR_FORMATE,                                                  /*!< format error */
+    CAN_ERROR_ACK,                                                      /*!< ACK error */
+    CAN_ERROR_BITRECESSIVE,                                             /*!< bit recessive error */
+    CAN_ERROR_BITDOMINANTER,                                            /*!< bit dominant error */
+    CAN_ERROR_CRC,                                                      /*!< CRC error */
+    CAN_ERROR_SOFTWARECFG,                                              /*!< software configure */
+}can_error_enum;
+
+/* transmit states */
+typedef enum
+{
+    CAN_TRANSMIT_FAILED = 0,                                            /*!< CAN transmitted failure */
+    CAN_TRANSMIT_OK = 1,                                                /*!< CAN transmitted success */
+    CAN_TRANSMIT_PENDING = 2,                                           /*!< CAN transmitted pending */
+    CAN_TRANSMIT_NOMAILBOX = 4,                                         /*!< no empty mailbox to be used for CAN */
+}can_transmit_state_enum;
+
+typedef enum
+{
+    CAN_INIT_STRUCT = 0,                                                /* CAN initiliaze parameters struct */
+    CAN_FILTER_STRUCT,                                                  /* CAN filter parameters struct */
+    CAN_TX_MESSAGE_STRUCT,                                              /* CAN transmit message struct */
+    CAN_RX_MESSAGE_STRUCT,                                              /* CAN receive message struct */
+}can_struct_type_enum;
+
+/* CAN baudrate prescaler*/
+#define BT_BAUDPSC(regval)                 (BITS(0,9) & ((uint32_t)(regval) << 0))
+
+/* CAN bit segment 1*/
+#define BT_BS1(regval)                     (BITS(16,19) & ((uint32_t)(regval) << 16))
+
+/* CAN bit segment 2*/
+#define BT_BS2(regval)                     (BITS(20,22) & ((uint32_t)(regval) << 20))
+
+/* CAN resynchronization jump width*/
+#define BT_SJW(regval)                     (BITS(24,25) & ((uint32_t)(regval) << 24))
+
+/* CAN communication mode*/
+#define BT_MODE(regval)                    (BITS(30,31) & ((uint32_t)(regval) << 30))
+
+/* CAN FDATA high 16 bits */
+#define FDATA_MASK_HIGH(regval)            (BITS(16,31) & ((uint32_t)(regval) << 16))
+
+/* CAN FDATA low 16 bits */
+#define FDATA_MASK_LOW(regval)             (BITS(0,15) & ((uint32_t)(regval) << 0))
+
+/* CAN1 filter start bank_number*/
+#define FCTL_HBC1F(regval)                 (BITS(8,13) & ((uint32_t)(regval) << 8))
+
+/* CAN transmit mailbox extended identifier*/
+#define TMI_EFID(regval)                   (BITS(3,31) & ((uint32_t)(regval) << 3))
+
+/* CAN transmit mailbox standard identifier*/
+#define TMI_SFID(regval)                   (BITS(21,31) & ((uint32_t)(regval) << 21))
+
+/* transmit data byte 0 */
+#define TMDATA0_DB0(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* transmit data byte 1 */
+#define TMDATA0_DB1(regval)                (BITS(8,15) & ((uint32_t)(regval) << 8))
+
+/* transmit data byte 2 */
+#define TMDATA0_DB2(regval)                (BITS(16,23) & ((uint32_t)(regval) << 16))
+
+/* transmit data byte 3 */                 
+#define TMDATA0_DB3(regval)                (BITS(24,31) & ((uint32_t)(regval) << 24))
+
+/* transmit data byte 4 */                 
+#define TMDATA1_DB4(regval)                (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* transmit data byte 5 */                 
+#define TMDATA1_DB5(regval)                (BITS(8,15) & ((uint32_t)(regval) << 8))
+
+/* transmit data byte 6 */                 
+#define TMDATA1_DB6(regval)                (BITS(16,23) & ((uint32_t)(regval) << 16))
+
+/* transmit data byte 7 */                 
+#define TMDATA1_DB7(regval)                (BITS(24,31) & ((uint32_t)(regval) << 24))
+
+/* receive mailbox extended identifier*/
+#define GET_RFIFOMI_EFID(regval)           GET_BITS((uint32_t)(regval), 3, 31)
+
+/* receive mailbox standrad identifier*/
+#define GET_RFIFOMI_SFID(regval)           GET_BITS((uint32_t)(regval), 21, 31)
+
+/* receive data length */
+#define GET_RFIFOMP_DLENC(regval)          GET_BITS((uint32_t)(regval), 0, 3)
+
+/* the index of the filter by which the frame is passed */
+#define GET_RFIFOMP_FI(regval)             GET_BITS((uint32_t)(regval), 8, 15)
+
+/* receive data byte 0 */
+#define GET_RFIFOMDATA0_DB0(regval)        GET_BITS((uint32_t)(regval), 0, 7)
+
+/* receive data byte 1 */
+#define GET_RFIFOMDATA0_DB1(regval)        GET_BITS((uint32_t)(regval), 8, 15)
+
+/* receive data byte 2 */
+#define GET_RFIFOMDATA0_DB2(regval)        GET_BITS((uint32_t)(regval), 16, 23)
+
+/* receive data byte 3 */
+#define GET_RFIFOMDATA0_DB3(regval)        GET_BITS((uint32_t)(regval), 24, 31)
+
+/* receive data byte 4 */
+#define GET_RFIFOMDATA1_DB4(regval)        GET_BITS((uint32_t)(regval), 0, 7)
+
+/* receive data byte 5 */
+#define GET_RFIFOMDATA1_DB5(regval)        GET_BITS((uint32_t)(regval), 8, 15)
+
+/* receive data byte 6 */
+#define GET_RFIFOMDATA1_DB6(regval)        GET_BITS((uint32_t)(regval), 16, 23)
+
+/* receive data byte 7 */
+#define GET_RFIFOMDATA1_DB7(regval)        GET_BITS((uint32_t)(regval), 24, 31)
+
+/* error number */        
+#define GET_ERR_ERRN(regval)               GET_BITS((uint32_t)(regval), 4, 6)
+
+/* transmit error count */        
+#define GET_ERR_TECNT(regval)              GET_BITS((uint32_t)(regval), 16, 23)
+
+/* receive  error count */        
+#define GET_ERR_RECNT(regval)              GET_BITS((uint32_t)(regval), 24, 31)
+
+/* CAN errors */
+#define ERR_ERRN(regval)                   (BITS(4,6) & ((uint32_t)(regval) << 4))
+#define CAN_ERRN_0                         ERR_ERRN(0)                  /*!< no error */
+#define CAN_ERRN_1                         ERR_ERRN(1)                  /*!< fill error */
+#define CAN_ERRN_2                         ERR_ERRN(2)                  /*!< format error */
+#define CAN_ERRN_3                         ERR_ERRN(3)                  /*!< ACK error */
+#define CAN_ERRN_4                         ERR_ERRN(4)                  /*!< bit recessive error */
+#define CAN_ERRN_5                         ERR_ERRN(5)                  /*!< bit dominant error */
+#define CAN_ERRN_6                         ERR_ERRN(6)                  /*!< CRC error */
+#define CAN_ERRN_7                         ERR_ERRN(7)                  /*!< software error */
+
+#define CAN_STATE_PENDING                  ((uint32_t)0x00000000U)      /*!< CAN pending */
+
+/* CAN communication mode */
+#define CAN_NORMAL_MODE                    ((uint8_t)0x00U)             /*!< normal communication mode */
+#define CAN_LOOPBACK_MODE                  ((uint8_t)0x01U)             /*!< loopback communication mode */
+#define CAN_SILENT_MODE                    ((uint8_t)0x02U)             /*!< silent communication mode */
+#define CAN_SILENT_LOOPBACK_MODE           ((uint8_t)0x03U)             /*!< loopback and silent communication mode */
+
+/* CAN resynchronisation jump width */
+#define CAN_BT_SJW_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
+#define CAN_BT_SJW_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
+#define CAN_BT_SJW_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
+#define CAN_BT_SJW_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
+
+/* CAN time segment 1 */
+#define CAN_BT_BS1_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
+#define CAN_BT_BS1_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
+#define CAN_BT_BS1_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
+#define CAN_BT_BS1_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
+#define CAN_BT_BS1_5TQ                     ((uint8_t)0x04U)             /*!< 5 time quanta */
+#define CAN_BT_BS1_6TQ                     ((uint8_t)0x05U)             /*!< 6 time quanta */
+#define CAN_BT_BS1_7TQ                     ((uint8_t)0x06U)             /*!< 7 time quanta */
+#define CAN_BT_BS1_8TQ                     ((uint8_t)0x07U)             /*!< 8 time quanta */
+#define CAN_BT_BS1_9TQ                     ((uint8_t)0x08U)             /*!< 9 time quanta */
+#define CAN_BT_BS1_10TQ                    ((uint8_t)0x09U)             /*!< 10 time quanta */
+#define CAN_BT_BS1_11TQ                    ((uint8_t)0x0AU)             /*!< 11 time quanta */
+#define CAN_BT_BS1_12TQ                    ((uint8_t)0x0BU)             /*!< 12 time quanta */
+#define CAN_BT_BS1_13TQ                    ((uint8_t)0x0CU)             /*!< 13 time quanta */
+#define CAN_BT_BS1_14TQ                    ((uint8_t)0x0DU)             /*!< 14 time quanta */
+#define CAN_BT_BS1_15TQ                    ((uint8_t)0x0EU)             /*!< 15 time quanta */
+#define CAN_BT_BS1_16TQ                    ((uint8_t)0x0FU)             /*!< 16 time quanta */
+
+/* CAN time segment 2 */
+#define CAN_BT_BS2_1TQ                     ((uint8_t)0x00U)             /*!< 1 time quanta */
+#define CAN_BT_BS2_2TQ                     ((uint8_t)0x01U)             /*!< 2 time quanta */
+#define CAN_BT_BS2_3TQ                     ((uint8_t)0x02U)             /*!< 3 time quanta */
+#define CAN_BT_BS2_4TQ                     ((uint8_t)0x03U)             /*!< 4 time quanta */
+#define CAN_BT_BS2_5TQ                     ((uint8_t)0x04U)             /*!< 5 time quanta */
+#define CAN_BT_BS2_6TQ                     ((uint8_t)0x05U)             /*!< 6 time quanta */
+#define CAN_BT_BS2_7TQ                     ((uint8_t)0x06U)             /*!< 7 time quanta */
+#define CAN_BT_BS2_8TQ                     ((uint8_t)0x07U)             /*!< 8 time quanta */
+
+/* CAN mailbox number */
+#define CAN_MAILBOX0                       ((uint8_t)0x00U)             /*!< mailbox0 */
+#define CAN_MAILBOX1                       ((uint8_t)0x01U)             /*!< mailbox1 */
+#define CAN_MAILBOX2                       ((uint8_t)0x02U)             /*!< mailbox2 */
+#define CAN_NOMAILBOX                      ((uint8_t)0x03U)             /*!< no mailbox empty */
+
+/* CAN frame format */
+#define CAN_FF_STANDARD                    ((uint32_t)0x00000000U)      /*!< standard frame */
+#define CAN_FF_EXTENDED                    ((uint32_t)0x00000004U)      /*!< extended frame */
+
+/* CAN receive fifo */
+#define CAN_FIFO0                          ((uint8_t)0x00U)             /*!< receive FIFO0 */
+#define CAN_FIFO1                          ((uint8_t)0x01U)             /*!< receive FIFO1 */
+
+/* frame number of receive fifo */
+#define CAN_RFIF_RFL_MASK                  ((uint32_t)0x00000003U)      /*!< mask for frame number in receive FIFOx */
+
+#define CAN_SFID_MASK                      ((uint32_t)0x000007FFU)      /*!< mask of standard identifier */
+#define CAN_EFID_MASK                      ((uint32_t)0x1FFFFFFFU)      /*!< mask of extended identifier */
+
+/* CAN working mode */
+#define CAN_MODE_INITIALIZE                ((uint8_t)0x01U)             /*!< CAN initialize mode */
+#define CAN_MODE_NORMAL                    ((uint8_t)0x02U)             /*!< CAN normal mode */
+#define CAN_MODE_SLEEP                     ((uint8_t)0x04U)             /*!< CAN sleep mode */
+
+/* filter bits */
+#define CAN_FILTERBITS_16BIT               ((uint8_t)0x00U)             /*!< CAN filter 16 bits */
+#define CAN_FILTERBITS_32BIT               ((uint8_t)0x01U)             /*!< CAN filter 32 bits */
+
+/* filter mode */
+#define CAN_FILTERMODE_MASK                ((uint8_t)0x00U)             /*!< mask mode */
+#define CAN_FILTERMODE_LIST                ((uint8_t)0x01U)             /*!< list mode */
+
+/* filter 16 bits mask */
+#define CAN_FILTER_MASK_16BITS             ((uint32_t)0x0000FFFFU)      /*!< can filter 16 bits mask */
+
+/* frame type */
+#define CAN_FT_DATA                        ((uint32_t)0x00000000U)      /*!< data frame */
+#define CAN_FT_REMOTE                      ((uint32_t)0x00000002U)      /*!< remote frame */
+
+/* CAN timeout */
+#define CAN_TIMEOUT                        ((uint32_t)0x0000FFFFU)      /*!< timeout value */
+
+/* interrupt enable bits */
+#define CAN_INT_TME                        CAN_INTEN_TMEIE              /*!< transmit mailbox empty interrupt enable */
+#define CAN_INT_RFNE0                      CAN_INTEN_RFNEIE0            /*!< receive FIFO0 not empty interrupt enable */
+#define CAN_INT_RFF0                       CAN_INTEN_RFFIE0             /*!< receive FIFO0 full interrupt enable */
+#define CAN_INT_RFO0                       CAN_INTEN_RFOIE0             /*!< receive FIFO0 overfull interrupt enable */
+#define CAN_INT_RFNE1                      CAN_INTEN_RFNEIE1            /*!< receive FIFO1 not empty interrupt enable */
+#define CAN_INT_RFF1                       CAN_INTEN_RFFIE1             /*!< receive FIFO1 full interrupt enable */
+#define CAN_INT_RFO1                       CAN_INTEN_RFOIE1             /*!< receive FIFO1 overfull interrupt enable */
+#define CAN_INT_WERR                       CAN_INTEN_WERRIE             /*!< warning error interrupt enable */
+#define CAN_INT_PERR                       CAN_INTEN_PERRIE             /*!< passive error interrupt enable */
+#define CAN_INT_BO                         CAN_INTEN_BOIE               /*!< bus-off interrupt enable */
+#define CAN_INT_ERRN                       CAN_INTEN_ERRNIE             /*!< error number interrupt enable */
+#define CAN_INT_ERR                        CAN_INTEN_ERRIE              /*!< error interrupt enable */
+#define CAN_INT_WAKEUP                     CAN_INTEN_WIE                /*!< wakeup interrupt enable */
+#define CAN_INT_SLPW                       CAN_INTEN_SLPWIE             /*!< sleep working interrupt enable */
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize CAN */
+void can_deinit(uint32_t can_periph);
+/* initialize CAN structure */
+void can_struct_para_init(can_struct_type_enum type, void* p_struct);
+/* initialize CAN */
+ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
+/* CAN filter initialization */
+void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
+
+/* function configuration */
+/* set can1 filter start bank number */
+void can1_filter_start_bank(uint8_t start_bank);
+/* enable functions */
+/* CAN debug freeze enable */
+void can_debug_freeze_enable(uint32_t can_periph);
+/* CAN debug freeze disable */
+void can_debug_freeze_disable(uint32_t can_periph);
+/* CAN time trigger mode enable */
+void can_time_trigger_mode_enable(uint32_t can_periph);
+/* CAN time trigger mode disable */
+void can_time_trigger_mode_disable(uint32_t can_periph);
+
+/* transmit functions */
+/* transmit CAN message */
+uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
+/* get CAN transmit state */
+can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
+/* stop CAN transmission */
+void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
+/* CAN receive message */
+void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
+/* CAN release fifo */
+void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
+/* CAN receive message length */
+uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
+/* CAN working mode */
+ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
+/* CAN wakeup from sleep mode */
+ErrStatus can_wakeup(uint32_t can_periph);
+
+/* CAN get error */
+can_error_enum can_error_get(uint32_t can_periph);
+/* get CAN receive error number */
+uint8_t can_receive_error_number_get(uint32_t can_periph);
+/* get CAN transmit error number */
+uint8_t can_transmit_error_number_get(uint32_t can_periph);
+
+/* interrupt & flag functions */
+/* CAN interrupt enable */
+void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
+/* CAN interrupt disable */
+void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
+/* CAN get flag state */
+FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
+/* CAN clear flag state */
+void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
+/* CAN get interrupt flag state */
+FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
+/* CAN clear interrupt flag state */
+void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
+
+#endif /* GD32F20X_CAN_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_cau.h

@@ -0,0 +1,259 @@
+/*!
+    \file  gd32f20x_cau.h
+    \brief definitions for the CAU
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_CAU_H
+#define GD32F20X_CAU_H
+
+#include "gd32f20x.h"
+
+/* CAU definitions */
+#define CAU                        CAU_BASE
+
+/* registers definitions */
+#define CAU_CTL                    REG32(CAU + 0x00U)        /*!< control register  */
+#define CAU_STAT0                  REG32(CAU + 0x04U)        /*!< status register 0 */
+#define CAU_DI                     REG32(CAU + 0x08U)        /*!< data input register */ 
+#define CAU_DO                     REG32(CAU + 0x0CU)        /*!< data output register */
+#define CAU_DMAEN                  REG32(CAU + 0x10U)        /*!< DMA enable register */
+#define CAU_INTEN                  REG32(CAU + 0x14U)        /*!< interrupt enable register */
+#define CAU_STAT1                  REG32(CAU + 0x18U)        /*!< status register 1 */
+#define CAU_INTF                   REG32(CAU + 0x1CU)        /*!< interrupt flag register */
+#define CAU_KEY0H                  REG32(CAU + 0x20U)        /*!< key 0 high register */
+#define CAU_KEY0L                  REG32(CAU + 0x24U)        /*!< key 0 low register */
+#define CAU_KEY1H                  REG32(CAU + 0x28U)        /*!< key 1 high register */
+#define CAU_KEY1L                  REG32(CAU + 0x2CU)        /*!< key 1 low register */
+#define CAU_KEY2H                  REG32(CAU + 0x30U)        /*!< key 2 high register */
+#define CAU_KEY2L                  REG32(CAU + 0x34U)        /*!< key 2 low register */
+#define CAU_KEY3H                  REG32(CAU + 0x38U)        /*!< key 3 high register */
+#define CAU_KEY3L                  REG32(CAU + 0x3CU)        /*!< key 3 low register */
+#define CAU_IV0H                   REG32(CAU + 0x40U)        /*!< initial vector 0 high register */
+#define CAU_IV0L                   REG32(CAU + 0x44U)        /*!< initial vector 0 low register */
+#define CAU_IV1H                   REG32(CAU + 0x48U)        /*!< initial vector 1 high register */
+#define CAU_IV1L                   REG32(CAU + 0x4CU)        /*!< initial vector 1 low register */
+
+/* bits definitions */
+/* CAU_CTL */
+#define CAU_CTL_CAUDIR             BIT(2)                    /*!< algorithm direction */
+#define CAU_CTL_ALGM               BITS(3,5)                 /*!< algorithm mode selection */
+#define CAU_CTL_DATAM              BITS(6,7)                 /*!< data swapping selection */
+#define CAU_CTL_KEYM               BITS(8,9)                 /*!< key length selection when aes mode */
+#define CAU_CTL_FFLUSH             BIT(14)                   /*!< FIFO flush */
+#define CAU_CTL_CAUEN              BIT(15)                   /*!< cryptographic module enable */
+
+/* CAU_STAT0 */
+#define CAU_STAT0_IEM              BIT(0)                    /*!< IN FIFO empty flag */
+#define CAU_STAT0_INF              BIT(1)                    /*!< IN FIFO not full flag */
+#define CAU_STAT0_ONE              BIT(2)                    /*!< OUT FIFO not empty flag */
+#define CAU_STAT0_OFU              BIT(3)                    /*!< OUT FIFO full flag */
+#define CAU_STAT0_BUSY             BIT(4)                    /*!< busy flag */
+
+/* CAU_DI */
+#define CAU_DI_DI                  BITS(0,31)                /*!< data input */
+
+/* CAU_DO */
+#define CAU_DO_DO                  BITS(0,31)                /*!< data output */
+
+/* CAU_DMAEN */
+#define CAU_DMAEN_DMAIEN           BIT(0)                    /*!< IN FIFO DMA enable */
+#define CAU_DMAEN_DMAOEN           BIT(1)                    /*!< OUT FIFO DMA enable */
+
+/* CAU_INTEN */
+#define CAU_INTEN_IINTEN           BIT(0)                    /*!< IN FIFO interrupt enable */
+#define CAU_INTEN_OINTEN           BIT(1)                    /*!< OUT FIFO interrupt enable */
+
+/* CAU_STAT1 */
+#define CAU_STAT1_ISTA             BIT(0)                    /*!< flag set when there is less than 4 words in IN FIFO */
+#define CAU_STAT1_OSTA             BIT(1)                    /*!< flag set when there is one or more word in OUT FIFO */
+
+/* CAU_INTF */
+#define CAU_INTF_IINTF             BIT(0)                    /*!< IN FIFO interrupt flag */
+#define CAU_INTF_OINTF             BIT(1)                    /*!< OUT FIFO interrupt flag */
+
+/* CAU_KEYxH x=0..3 */
+#define CAU_KEYXH_KEYXH            BITS(0,31)                /*!< the key for des, tdes, aes */
+
+/* CAU_KEYxL x=0..3 */
+#define CAU_KEYXL_KEYXL            BITS(0,31)                /*!< the key for des, tdes, aes */
+
+/* CAU_IVxH x=0..1 */
+#define CAU_IVXH_IVXH              BITS(0,31)                /*!< the initialization vector for des, tdes, aes */
+
+/* CAU_IVxL x=0..1 */
+#define CAU_IVXL_IVXL              BITS(0,31)                /*!< the initialization vector for des, tdes, aes */
+
+/* constants definitions */
+/* structure for keys initialization of the cau */
+typedef struct
+{
+    uint32_t key_0_high;  /*!< key 0 high */
+    uint32_t key_0_low;   /*!< key 0 low  */
+    uint32_t key_1_high;  /*!< key 1 high */
+    uint32_t key_1_low;   /*!< key 1 low  */
+    uint32_t key_2_high;  /*!< key 2 high */
+    uint32_t key_2_low;   /*!< key 2 low  */
+    uint32_t key_3_high;  /*!< key 3 high */
+    uint32_t key_3_low;   /*!< key 3 low  */
+}cau_key_parameter_struct;
+
+/* structure for vectors initialization of the cau */
+typedef struct
+{
+    uint32_t iv_0_high;   /*!< init vector 0 high */
+    uint32_t iv_0_low;    /*!< init vector 0 low  */
+    uint32_t iv_1_high;   /*!< init vector 1 high */
+    uint32_t iv_1_low;    /*!< init vector 1 low  */
+}cau_iv_parameter_struct;
+
+/* structure for vectors initialization of the cau */
+typedef struct
+{
+    uint8_t *input;      /*!< pointer to the input buffer */
+    uint32_t in_length;  /*!< length of the input buffer, 
+                              must be a multiple of 8(DES and TDES) or 16(AES) */
+    uint8_t *output;     /*!< pointer to the returned buffer */
+}cau_text_struct;
+
+/* cau_ctl register value */
+#define CAU_ENCRYPT                 ((uint32_t)0x00000000)                     /*!< encrypt */
+#define CAU_DECRYPT                 CAU_CTL_CAUDIR                             /*!< decrypt */
+
+#define CTL_ALGM(regval)            (BITS(3,5) & ((uint32_t)(regval) << 3))    /*!< write value to CAU_CTL_ALGM bit field */
+#define CAU_MODE_TDES_ECB           CTL_ALGM(0)                                /*!< TDES-ECB (3DES Electronic codebook) */
+#define CAU_MODE_TDES_CBC           CTL_ALGM(1)                                /*!< TDES-CBC (3DES Cipher block chaining) */
+#define CAU_MODE_DES_ECB            CTL_ALGM(2)                                /*!< DES-ECB (simple DES Electronic codebook) */
+#define CAU_MODE_DES_CBC            CTL_ALGM(3)                                /*!< DES-CBC (simple DES Cipher block chaining) */
+#define CAU_MODE_AES_ECB            CTL_ALGM(4)                                /*!< AES-ECB (AES Electronic codebook) */
+#define CAU_MODE_AES_CBC            CTL_ALGM(5)                                /*!< AES-CBC (AES Cipher block chaining) */
+#define CAU_MODE_AES_CTR            CTL_ALGM(6)                                /*!< AES-CTR (AES counter mode) */
+#define CAU_MODE_AES_KEY            CTL_ALGM(7)                                /*!< AES decryption key preparation mode */
+
+#define CTL_DATAM(regval)           (BITS(6,7) & ((uint32_t)(regval) << 6))    /*!< write value to CAU_CTL_DATAM bit field */
+#define CAU_SWAPPING_32BIT          CTL_DATAM(0)                               /*!< no swapping */
+#define CAU_SWAPPING_16BIT          CTL_DATAM(1)                               /*!< half-word swapping */
+#define CAU_SWAPPING_8BIT           CTL_DATAM(2)                               /*!< bytes swapping */
+#define CAU_SWAPPING_1BIT           CTL_DATAM(3)                               /*!< bit swapping */
+
+#define CTL_KEYM(regval)            (BITS(8,9) & ((uint32_t)(regval) << 8))    /*!< write value to CAU_CTL_KEYM bit field */
+#define CAU_KEYSIZE_128BIT          CTL_KEYM(0)                                /*!< 128 bit key length */
+#define CAU_KEYSIZE_192BIT          CTL_KEYM(1)                                /*!< 192 bit key length */
+#define CAU_KEYSIZE_256BIT          CTL_KEYM(2)                                /*!< 256 bit key length */
+
+/* cau_stat0 register value */                                                        
+#define CAU_FLAG_INFIFO_EMPTY       CAU_STAT0_IEM                              /*!< IN FIFO empty */
+#define CAU_FLAG_INFIFO_NO_FULL     CAU_STAT0_INF                              /*!< IN FIFO is not full */
+#define CAU_FLAG_OUTFIFO_NO_EMPTY   CAU_STAT0_ONE                              /*!< OUT FIFO not empty */
+#define CAU_FLAG_OUTFIFO_FULL       CAU_STAT0_OFU                              /*!< OUT FIFO is full */
+#define CAU_FLAG_BUSY               CAU_STAT0_BUSY                             /*!< the CAU core is busy */
+
+/* cau_dmaen register value */
+#define CAU_DMA_INFIFO              CAU_DMAEN_DMAIEN                           /*!< DMA input enable */
+#define CAU_DMA_OUTFIFO             CAU_DMAEN_DMAOEN                           /*!< DMA output enable */
+
+/* cau_inten register value */
+#define CAU_INT_INFIFO              CAU_INTEN_IINTEN                           /*!< IN FIFO Interrupt */
+#define CAU_INT_OUTFIFO             CAU_INTEN_OINTEN                           /*!< OUT FIFO Interrupt */
+
+/* cau_stat1 register value */
+#define CAU_FLAG_INFIFO             (CAU_STAT1_ISTA | ((uint32_t)0x00000020U)) /*!< IN FIFO flag status */
+#define CAU_FLAG_OUTFIFO            (CAU_STAT1_OSTA | ((uint32_t)0x00000020U)) /*!< OUT FIFO flag status */
+
+/* cau_intf register value */
+#define CAU_INT_FLAG_INFIFO         CAU_INTF_IINTF                             /*!< IN FIFO interrupt status */
+#define CAU_INT_FLAG_OUTFIFO        CAU_INTF_OINTF                             /*!< OUT FIFO interrupt status */
+
+/* function declarations */
+/* initialization functions */
+/* reset the CAU peripheral */
+void cau_deinit(void);
+/* enable the CAU peripheral */
+void cau_enable(void);
+/* disable the CAU peripheral */
+void cau_disable(void);
+/* enable the CAU DMA interface */
+void cau_dma_enable(uint32_t dma_req);
+/* disable the CAU DMA interface */
+void cau_dma_disable(uint32_t dma_req);
+/* initialize the CAU peripheral */
+void cau_init(uint32_t algo_dir, uint32_t algo_mode, uint32_t swapping);
+/* configure key size if used AES algorithm */
+void cau_aes_keysize_config(uint32_t key_size);
+/* initialize the key parameters */
+void cau_key_init(cau_key_parameter_struct* key_initpara);
+/* initialize the structure cau_key_initpara */
+void cau_key_parameter_init(cau_key_parameter_struct* key_initpara);
+/* initialize the vectors parameters */
+void cau_iv_init(cau_iv_parameter_struct* iv_initpara);
+/* initialize the vectors parameters */
+void cau_iv_parameter_init(cau_iv_parameter_struct* iv_initpara);
+/* flush the IN and OUT FIFOs */
+void cau_fifo_flush(void);
+/* return whether CAU peripheral is enabled or disabled */
+ControlStatus cau_enable_state_get(void);
+/* write data to the IN FIFO */
+void cau_data_write(uint32_t data);
+/* return the last data entered into the output FIFO */
+uint32_t cau_data_read(void);
+
+/* function configuration */
+/* calculate digest in HASH mode */
+/* encrypt and decrypt using AES in ECB mode */
+ErrStatus cau_aes_ecb(uint32_t algo_dir, uint8_t *key, uint16_t keysize, cau_text_struct *text);
+/* encrypt and decrypt using AES in CBC mode */
+ErrStatus cau_aes_cbc(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t iv[16], cau_text_struct *text);
+/* encrypt and decrypt using AES in CTR mode */
+ErrStatus cau_aes_ctr(uint32_t algo_dir, uint8_t *key, uint16_t keysize, uint8_t iv[16], cau_text_struct *text);
+/* encrypt and decrypt using TDES in ECB mode */
+ErrStatus cau_tdes_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text);
+/* encrypt and decrypt using TDES in CBC mode */
+ErrStatus cau_tdes_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_text_struct *text);
+/* encrypt and decrypt using DES in ECB mode */
+ErrStatus cau_des_ecb(uint32_t algo_dir, uint8_t key[24], cau_text_struct *text);
+/* encrypt and decrypt using DES in CBC mode */
+ErrStatus cau_des_cbc(uint32_t algo_dir, uint8_t key[24], uint8_t iv[8], cau_text_struct *text);
+
+/* interrupt & flag functions */
+/* get the CAU flag status */
+FlagStatus cau_flag_get(uint32_t flag);
+/* enable the CAU interrupts */
+void cau_interrupt_enable(uint32_t interrupt);
+/* disable the CAU interrupts */
+void cau_interrupt_disable(uint32_t interrupt);
+/* get the interrupt flag */
+FlagStatus cau_interrupt_flag_get(uint32_t int_flag);
+
+#endif /* GD32F20X_CAU_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_crc.h

@@ -0,0 +1,81 @@
+/*!
+    \file  gd32f20x_crc.h
+    \brief definitions for the CRC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_CRC_H
+#define GD32F20X_CRC_H
+
+#include "gd32f20x.h"
+
+/* CRC definitions */
+#define CRC                            CRC_BASE
+
+/* registers definitions */
+#define CRC_DATA                       REG32(CRC + 0x00U)              /*!< CRC data register */
+#define CRC_FDATA                      REG32(CRC + 0x04U)              /*!< CRC free data register */
+#define CRC_CTL                        REG32(CRC + 0x08U)              /*!< CRC control register */
+
+/* bits definitions */
+/* CRC_DATA */
+#define CRC_DATA_DATA                  BITS(0,31)                      /*!< CRC calculation result bits */
+
+/* CRC_FDATA */
+#define CRC_FDATA_FDATA                BITS(0,7)                       /*!< CRC free data bits */
+
+/* CRC_CTL */
+#define CRC_CTL_RST                    BIT(0)                          /*!< CRC reset CRC_DATA register bit */
+
+/* function declarations */
+/* initialization functions */
+/* deinit CRC calculation unit */
+void crc_deinit(void);
+/* reset data register to the value of initialization data register */
+void crc_data_register_reset(void);
+/* read the value of the data register */
+uint32_t crc_data_register_read(void);
+
+/* function configuration */
+/* read the value of the free data register */
+uint8_t crc_free_data_register_read(void);
+/* write data to the free data register */
+void crc_free_data_register_write(uint8_t free_data);
+/* calculate the CRC value of a 32-bit data */
+uint32_t crc_single_data_calculate(uint32_t sdata);
+/* calculate the CRC value of an array of 32-bit values */
+uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
+
+#endif /* GD32F20X_CRC_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_dac.h

@@ -0,0 +1,248 @@
+/*!
+    \file  gd32f20x_dac.h
+    \brief definitions for the DAC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_DAC_H
+#define GD32F20X_DAC_H
+
+#include "gd32f20x.h"
+
+/* DACx(x=0,1) definitions */
+#define DAC                     DAC_BASE
+#define DAC0                    0U
+#define DAC1                    1U
+
+/* registers definitions */
+#define DAC_CTL                 REG32(DAC + 0x00U)   /*!< DAC control register */
+#define DAC_SWT                 REG32(DAC + 0x04U)   /*!< DAC software trigger register */
+#define DAC0_R12DH              REG32(DAC + 0x08U)   /*!< DAC0 12-bit right-aligned data holding register */
+#define DAC0_L12DH              REG32(DAC + 0x0CU)   /*!< DAC0 12-bit left-aligned data holding register */
+#define DAC0_R8DH               REG32(DAC + 0x10U)   /*!< DAC0 8-bit right-aligned data holding register */
+#define DAC1_R12DH              REG32(DAC + 0x14U)   /*!< DAC1 12-bit right-aligned data holding register */
+#define DAC1_L12DH              REG32(DAC + 0x18U)   /*!< DAC1 12-bit left-aligned data holding register */
+#define DAC1_R8DH               REG32(DAC + 0x1CU)   /*!< DAC1 8-bit right-aligned data holding register */
+#define DACC_R12DH              REG32(DAC + 0x20U)   /*!< DAC concurrent mode 12-bit right-aligned data holding register */
+#define DACC_L12DH              REG32(DAC + 0x24U)   /*!< DAC concurrent mode 12-bit left-aligned data holding register */
+#define DACC_R8DH               REG32(DAC + 0x28U)   /*!< DAC concurrent mode 8-bit right-aligned data holding register */
+#define DAC0_DO                 REG32(DAC + 0x2CU)   /*!< DAC0 data output register */
+#define DAC1_DO                 REG32(DAC + 0x30U)   /*!< DAC1 data output register */
+
+/* bits definitions */
+/* DAC_CTL */
+#define DAC_CTL_DEN0            BIT(0)               /*!< DAC0 enable/disable bit */
+#define DAC_CTL_DBOFF0          BIT(1)               /*!< DAC0 output buffer turn on/off bit */
+#define DAC_CTL_DTEN0           BIT(2)               /*!< DAC0 trigger enable/disable bit */
+#define DAC_CTL_DTSEL0          BITS(3,5)            /*!< DAC0 trigger source selection enable/disable bits */
+#define DAC_CTL_DWM0            BITS(6,7)            /*!< DAC0 noise wave mode */
+#define DAC_CTL_DWBW0           BITS(8,11)           /*!< DAC0 noise wave bit width */
+#define DAC_CTL_DDMAEN0         BIT(12)              /*!< DAC0 DMA enable/disable bit */
+#define DAC_CTL_DEN1            BIT(16)              /*!< DAC1 enable/disable bit */ 
+#define DAC_CTL_DBOFF1          BIT(17)              /*!< DAC1 output buffer turn on/turn off bit */
+#define DAC_CTL_DTEN1           BIT(18)              /*!< DAC1 trigger enable/disable bit */
+#define DAC_CTL_DTSEL1          BITS(19,21)          /*!< DAC1 trigger source selection enable/disable bits */
+#define DAC_CTL_DWM1            BITS(22,23)          /*!< DAC1 noise wave mode */
+#define DAC_CTL_DWBW1           BITS(24,27)          /*!< DAC1 noise wave bit width */
+#define DAC_CTL_DDMAEN1         BIT(28)              /*!< DAC1 DMA enable/disable bit */
+
+/* DAC_SWT */
+#define DAC_SWT_SWTR0           BIT(0)               /*!< DAC0 software trigger bit, cleared by hardware */
+#define DAC_SWT_SWTR1           BIT(1)               /*!< DAC1 software trigger bit, cleared by hardware */
+
+/* DAC0_R12DH */
+#define DAC0_R12DH_DAC0_DH      BITS(0,11)           /*!< DAC0 12-bit right-aligned data bits */
+
+/* DAC0_L12DH */
+#define DAC0_L12DH_DAC0_DH      BITS(4,15)           /*!< DAC0 12-bit left-aligned data bits */
+
+/* DAC0_R8DH */
+#define DAC0_R8DH_DAC0_DH       BITS(0,7)            /*!< DAC0 8-bit right-aligned data bits */
+
+/* DAC1_R12DH */
+#define DAC1_R12DH_DAC1_DH      BITS(0,11)           /*!< DAC1 12-bit right-aligned data bits */
+
+/* DAC1_L12DH */
+#define DAC1_L12DH_DAC1_DH      BITS(4,15)           /*!< DAC1 12-bit left-aligned data bits */
+
+/* DAC1_R8DH */
+#define DAC1_R8DH_DAC1_DH       BITS(0,7)            /*!< DAC1 8-bit right-aligned data bits */
+
+/* DACC_R12DH */
+#define DACC_R12DH_DAC0_DH      BITS(0,11)           /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
+#define DACC_R12DH_DAC1_DH      BITS(16,27)          /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
+
+/* DACC_L12DH */
+#define DACC_L12DH_DAC0_DH      BITS(4,15)           /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
+#define DACC_L12DH_DAC1_DH      BITS(20,31)          /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
+
+/* DACC_R8DH */
+#define DACC_R8DH_DAC0_DH       BITS(0,7)            /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
+#define DACC_R8DH_DAC1_DH       BITS(8,15)           /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
+
+/* DAC0_DO */
+#define DAC0_DO_DAC0_DO         BITS(0,11)           /*!< DAC0 12-bit output data bits */
+
+/* DAC1_DO */
+#define DAC1_DO_DAC1_DO         BITS(0,11)           /*!< DAC1 12-bit output data bits */
+
+/* constants definitions */
+/* DAC trigger source */
+#define CTL_DTSEL(regval)       (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define DAC_TRIGGER_T5_TRGO     CTL_DTSEL(0)         /*!< TIMER5 TRGO */
+#define DAC_TRIGGER_T2_TRGO     CTL_DTSEL(1)         /*!< TIMER2 TRGO */
+#define DAC_TRIGGER_T6_TRGO     CTL_DTSEL(2)         /*!< TIMER6 TRGO */
+#define DAC_TRIGGER_T4_TRGO     CTL_DTSEL(3)         /*!< TIMER4 TRGO */
+#define DAC_TRIGGER_T1_TRGO     CTL_DTSEL(4)         /*!< TIMER1 TRGO */
+#define DAC_TRIGGER_T3_TRGO     CTL_DTSEL(5)         /*!< TIMER3 TRGO */
+#define DAC_TRIGGER_EXTI_9      CTL_DTSEL(6)         /*!< EXTI interrupt line9 event */
+#define DAC_TRIGGER_SOFTWARE    CTL_DTSEL(7)         /*!< software trigger */
+
+/* DAC noise wave mode */
+#define CTL_DWM(regval)         (BITS(6,7) & ((uint32_t)(regval) << 6))
+#define DAC_WAVE_DISABLE        CTL_DWM(0)           /*!< wave disable */
+#define DAC_WAVE_MODE_LFSR      CTL_DWM(1)           /*!< LFSR noise mode */
+#define DAC_WAVE_MODE_TRIANGLE  CTL_DWM(2)           /*!< triangle noise mode */
+
+/* DAC noise wave bit width */
+#define DWBW(regval)            (BITS(8,11) & ((uint32_t)(regval) << 8))
+#define DAC_WAVE_BIT_WIDTH_1    DWBW(0)              /*!< bit width of the wave signal is 1 */
+#define DAC_WAVE_BIT_WIDTH_2    DWBW(1)              /*!< bit width of the wave signal is 2 */
+#define DAC_WAVE_BIT_WIDTH_3    DWBW(2)              /*!< bit width of the wave signal is 3 */
+#define DAC_WAVE_BIT_WIDTH_4    DWBW(3)              /*!< bit width of the wave signal is 4 */
+#define DAC_WAVE_BIT_WIDTH_5    DWBW(4)              /*!< bit width of the wave signal is 5 */
+#define DAC_WAVE_BIT_WIDTH_6    DWBW(5)              /*!< bit width of the wave signal is 6 */
+#define DAC_WAVE_BIT_WIDTH_7    DWBW(6)              /*!< bit width of the wave signal is 7 */
+#define DAC_WAVE_BIT_WIDTH_8    DWBW(7)              /*!< bit width of the wave signal is 8 */
+#define DAC_WAVE_BIT_WIDTH_9    DWBW(8)              /*!< bit width of the wave signal is 9 */
+#define DAC_WAVE_BIT_WIDTH_10   DWBW(9)              /*!< bit width of the wave signal is 10 */
+#define DAC_WAVE_BIT_WIDTH_11   DWBW(10)             /*!< bit width of the wave signal is 11 */
+#define DAC_WAVE_BIT_WIDTH_12   DWBW(11)             /*!< bit width of the wave signal is 12 */
+
+/* unmask LFSR bits in DAC LFSR noise mode */
+#define DAC_LFSR_BIT0           DAC_WAVE_BIT_WIDTH_1  /*!< unmask the LFSR bit0 */
+#define DAC_LFSR_BITS1_0        DAC_WAVE_BIT_WIDTH_2  /*!< unmask the LFSR bits[1:0] */
+#define DAC_LFSR_BITS2_0        DAC_WAVE_BIT_WIDTH_3  /*!< unmask the LFSR bits[2:0] */
+#define DAC_LFSR_BITS3_0        DAC_WAVE_BIT_WIDTH_4  /*!< unmask the LFSR bits[3:0] */
+#define DAC_LFSR_BITS4_0        DAC_WAVE_BIT_WIDTH_5  /*!< unmask the LFSR bits[4:0] */
+#define DAC_LFSR_BITS5_0        DAC_WAVE_BIT_WIDTH_6  /*!< unmask the LFSR bits[5:0] */
+#define DAC_LFSR_BITS6_0        DAC_WAVE_BIT_WIDTH_7  /*!< unmask the LFSR bits[6:0] */
+#define DAC_LFSR_BITS7_0        DAC_WAVE_BIT_WIDTH_8  /*!< unmask the LFSR bits[7:0] */
+#define DAC_LFSR_BITS8_0        DAC_WAVE_BIT_WIDTH_9  /*!< unmask the LFSR bits[8:0] */
+#define DAC_LFSR_BITS9_0        DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
+#define DAC_LFSR_BITS10_0       DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
+#define DAC_LFSR_BITS11_0       DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
+
+/* triangle amplitude in DAC triangle noise mode */
+#define DAC_TRIANGLE_AMPLITUDE_1    DAC_WAVE_BIT_WIDTH_1  /*!< triangle amplitude is 1 */
+#define DAC_TRIANGLE_AMPLITUDE_3    DAC_WAVE_BIT_WIDTH_2  /*!< triangle amplitude is 3 */
+#define DAC_TRIANGLE_AMPLITUDE_7    DAC_WAVE_BIT_WIDTH_3  /*!< triangle amplitude is 7 */
+#define DAC_TRIANGLE_AMPLITUDE_15   DAC_WAVE_BIT_WIDTH_4  /*!< triangle amplitude is 15 */
+#define DAC_TRIANGLE_AMPLITUDE_31   DAC_WAVE_BIT_WIDTH_5  /*!< triangle amplitude is 31 */
+#define DAC_TRIANGLE_AMPLITUDE_63   DAC_WAVE_BIT_WIDTH_6  /*!< triangle amplitude is 63 */
+#define DAC_TRIANGLE_AMPLITUDE_127  DAC_WAVE_BIT_WIDTH_7  /*!< triangle amplitude is 127 */
+#define DAC_TRIANGLE_AMPLITUDE_255  DAC_WAVE_BIT_WIDTH_8  /*!< triangle amplitude is 255 */
+#define DAC_TRIANGLE_AMPLITUDE_511  DAC_WAVE_BIT_WIDTH_9  /*!< triangle amplitude is 511 */
+#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
+#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
+#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
+
+/* DAC data alignment */
+#define DATA_ALIGN(regval)      (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define DAC_ALIGN_12B_R         DATA_ALIGN(0)        /*!< data right 12b alignment */
+#define DAC_ALIGN_12B_L         DATA_ALIGN(1)        /*!< data left  12b alignment */
+#define DAC_ALIGN_8B_R          DATA_ALIGN(2)        /*!< data right  8b alignment */
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize DAC */
+void dac_deinit(void);
+/* enable DAC */
+void dac_enable(uint32_t dac_periph);
+/* disable DAC */
+void dac_disable(uint32_t dac_periph);
+/* enable DAC DMA */
+void dac_dma_enable(uint32_t dac_periph);
+/* disable DAC DMA */
+void dac_dma_disable(uint32_t dac_periph); 
+/* enable DAC output buffer */
+void dac_output_buffer_enable(uint32_t dac_periph);
+/* disable DAC output buffer */
+void dac_output_buffer_disable(uint32_t dac_periph);
+/* get the last data output value */
+uint16_t dac_output_value_get(uint32_t dac_periph);
+/* set DAC data holding register value */
+void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
+
+/* function configuration */
+/* DAC trigger configuration */
+/* enable DAC trigger */
+void dac_trigger_enable(uint32_t dac_periph);
+/* disable DAC trigger */
+void dac_trigger_disable(uint32_t dac_periph);
+/* configure DAC trigger source */
+void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
+/* enable DAC software trigger */
+void dac_software_trigger_enable(uint32_t dac_periph);
+/* disable DAC software trigger */
+void dac_software_trigger_disable(uint32_t dac_periph);
+
+/* DAC wave mode configuration */
+/* configure DAC wave mode */
+void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
+/* configure DAC wave bit width */
+void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
+/* configure DAC LFSR noise mode */
+void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
+/* configure DAC triangle noise mode */
+void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
+
+/* DAC concurrent mode configuration */
+/* enable DAC concurrent mode */
+void dac_concurrent_enable(void);
+/* disable DAC concurrent mode */
+void dac_concurrent_disable(void);
+/* enable DAC concurrent software trigger */
+void dac_concurrent_software_trigger_enable(void);
+/* disable DAC concurrent software trigger */
+void dac_concurrent_software_trigger_disable(void);
+/* enable DAC concurrent buffer function */
+void dac_concurrent_output_buffer_enable(void);
+/* disable DAC concurrent buffer function */
+void dac_concurrent_output_buffer_disable(void);
+/* set DAC concurrent mode data holding register value */
+void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); 
+
+#endif /* GD32F20X_DAC_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_dbg.h

@@ -0,0 +1,146 @@
+/*!
+    \file  gd32f20x_dbg.h
+    \brief definitions for the DBG
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_DBG_H
+#define GD32F20X_DBG_H
+
+#include "gd32f20x.h"
+
+/* DBG definitions */
+#define DBG                      DBG_BASE
+
+/* registers definitions */
+#define DBG_ID                   REG32(DBG + 0x00U)         /*!< DBG_ID code register */
+#define DBG_CTL                  REG32(DBG + 0x04U)         /*!< DBG control register */
+
+/* bits definitions */
+/* DBG_ID */
+#define DBG_ID_ID_CODE           BITS(0,31)                 /*!< DBG ID code values */
+
+/* DBG_CTL */
+#define DBG_CTL_SLP_HOLD        BIT(0)                      /*!< keep debugger connection during sleep mode */
+#define DBG_CTL_DSLP_HOLD       BIT(1)                      /*!< keep debugger connection during deepsleep mode */
+#define DBG_CTL_STB_HOLD        BIT(2)                      /*!< keep debugger connection during standby mode */
+#define DBG_CTL_TRACE_IOEN      BIT(5)                      /*!< enable trace pin assignment */
+#define DBG_CTL_TRACE_MODE      BITS(6,7)                   /*!< trace pin mode selection */
+#define DBG_CTL_FWDGT_HOLD      BIT(8)                      /*!< debug FWDGT kept when core is halted */
+#define DBG_CTL_WWDGT_HOLD      BIT(9)                      /*!< debug WWDGT kept when core is halted */
+#define DBG_CTL_TIMER0_HOLD     BIT(10)                     /*!< hold TIMER0 counter when core is halted */
+#define DBG_CTL_TIMER1_HOLD     BIT(11)                     /*!< hold TIMER1 counter when core is halted */
+#define DBG_CTL_TIMER2_HOLD     BIT(12)                     /*!< hold TIMER2 counter when core is halted */
+#define DBG_CTL_TIMER3_HOLD     BIT(13)                     /*!< hold TIMER3 counter when core is halted */
+#define DBG_CTL_CAN0_HOLD       BIT(14)                     /*!< debug CAN0 kept when core is halted */
+#define DBG_CTL_I2C0_HOLD       BIT(15)                     /*!< hold I2C0 smbus when core is halted */
+#define DBG_CTL_I2C1_HOLD       BIT(16)                     /*!< hold I2C1 smbus when core is halted */
+#define DBG_CTL_TIMER4_HOLD     BIT(17)                     /*!< hold TIMER4 counter when core is halted */
+#define DBG_CTL_TIMER5_HOLD     BIT(18)                     /*!< hold TIMER5 counter when core is halted */
+#define DBG_CTL_TIMER6_HOLD     BIT(19)                     /*!< hold TIMER6 counter when core is halted */
+#define DBG_CTL_TIMER7_HOLD     BIT(20)                     /*!< hold TIMER7 counter when core is halted */
+#define DBG_CTL_CAN1_HOLD       BIT(21)                     /*!< debug CAN1 kept when core is halted */
+#define DBG_CTL_TIMER11_HOLD    BIT(25)                     /*!< hold TIMER11 counter when core is halted */
+#define DBG_CTL_TIMER12_HOLD    BIT(26)                     /*!< hold TIMER12 counter when core is halted */
+#define DBG_CTL_TIMER13_HOLD    BIT(27)                     /*!< hold TIMER13 counter when core is halted */
+#define DBG_CTL_TIMER8_HOLD     BIT(28)                     /*!< hold TIMER8 counter when core is halted */
+#define DBG_CTL_TIMER9_HOLD     BIT(29)                     /*!< hold TIMER9 counter when core is halted */
+#define DBG_CTL_TIMER10_HOLD    BIT(30)                     /*!< hold TIMER10 counter when core is halted */
+
+/* constants definitions */
+/* debug hold when core is halted */
+typedef enum
+{
+    DBG_FWDGT_HOLD             = BIT(8),                    /*!< debug FWDGT kept when core is halted */
+    DBG_WWDGT_HOLD             = BIT(9),                    /*!< debug WWDGT kept when core is halted */
+    DBG_TIMER0_HOLD            = BIT(10),                   /*!< hold TIMER0 counter when core is halted */
+    DBG_TIMER1_HOLD            = BIT(11),                   /*!< hold TIMER1 counter when core is halted */
+    DBG_TIMER2_HOLD            = BIT(12),                   /*!< hold TIMER2 counter when core is halted */
+    DBG_TIMER3_HOLD            = BIT(13),                   /*!< hold TIMER3 counter when core is halted */
+    DBG_CAN0_HOLD              = BIT(14),                   /*!< debug CAN0 kept when core is halted */
+    DBG_I2C0_HOLD              = BIT(15),                   /*!< hold I2C0 smbus when core is halted */
+    DBG_I2C1_HOLD              = BIT(16),                   /*!< hold I2C1 smbus when core is halted */
+    DBG_TIMER4_HOLD            = BIT(17),                   /*!< hold TIMER4 counter when core is halted */
+    DBG_TIMER5_HOLD            = BIT(18),                   /*!< hold TIMER5 counter when core is halted */
+    DBG_TIMER6_HOLD            = BIT(19),                   /*!< hold TIMER6 counter when core is halted */
+    DBG_TIMER7_HOLD            = BIT(20),                   /*!< hold TIMER7 counter when core is halted */
+    DBG_CAN1_HOLD              = BIT(21),                   /*!< debug CAN1 kept when core is halted */
+    DBG_TIMER11_HOLD           = BIT(25),                   /*!< hold TIMER11 counter when core is halted */
+    DBG_TIMER12_HOLD           = BIT(26),                   /*!< hold TIMER12 counter when core is halted */
+    DBG_TIMER13_HOLD           = BIT(27),                   /*!< hold TIMER13 counter when core is halted */
+    DBG_TIMER8_HOLD            = BIT(28),                   /*!< hold TIMER8 counter when core is halted */
+    DBG_TIMER9_HOLD            = BIT(29),                   /*!< hold TIMER9 counter when core is halted */
+    DBG_TIMER10_HOLD           = BIT(30),                   /*!< hold TIMER10 counter when core is halted */
+}dbg_periph_enum;
+
+/* DBG low power mode configurations */
+#define DBG_LOW_POWER_SLEEP      DBG_CTL_SLP_HOLD           /*!< keep debugger connection during sleep mode */
+#define DBG_LOW_POWER_DEEPSLEEP  DBG_CTL_DSLP_HOLD          /*!< keep debugger connection during deepsleep mode */
+#define DBG_LOW_POWER_STANDBY    DBG_CTL_STB_HOLD           /*!< keep debugger connection during standby mode */
+
+/* DBG_CTL0_TRACE_MODE configurations */
+#define CTL_TRACE_MODE(regval)       (BITS(6,7) & ((uint32_t)(regval) << 6U))
+#define TRACE_MODE_ASYNC              CTL_TRACE_MODE(0)     /*!< trace pin used for async mode */
+#define TRACE_MODE_SYNC_DATASIZE_1    CTL_TRACE_MODE(1)     /*!< trace pin used for sync mode and data size is 1 */
+#define TRACE_MODE_SYNC_DATASIZE_2    CTL_TRACE_MODE(2)     /*!< trace pin used for sync mode and data size is 2 */
+#define TRACE_MODE_SYNC_DATASIZE_4    CTL_TRACE_MODE(3)     /*!< trace pin used for sync mode and data size is 4 */
+
+/* function declarations */
+/* initialization functions */
+/* read DBG_ID code register */
+uint32_t dbg_id_get(void);
+
+/* function configuration */
+/* low power behavior configuration */
+/* enable low power behavior when the MCU is in debug mode */
+void dbg_low_power_enable(uint32_t dbg_low_power);
+/* disable low power behavior when the MCU is in debug mode */
+void dbg_low_power_disable(uint32_t dbg_low_power);
+
+/* peripheral behavior configuration */
+/* enable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_enable(dbg_periph_enum dbg_periph);
+/* disable peripheral behavior when the MCU is in debug mode */
+void dbg_periph_disable(dbg_periph_enum dbg_periph);
+
+/* trace pin assignment configuration */
+/* enable trace pin assignment */
+void dbg_trace_pin_enable(void);
+/* disable trace pin assignment */
+void dbg_trace_pin_disable(void);
+/* set trace pin mode */
+void dbg_trace_pin_mode_set(uint32_t trace_mode);
+
+#endif /* GD32F20X_DBG_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_dci.h

@@ -0,0 +1,237 @@
+/*!
+    \file  gd32f20x_dci.h
+    \brief definitions for the DCI
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_DCI_H
+#define GD32F20X_DCI_H
+
+#include "gd32f20x.h"
+
+/* DCI definitions */
+#define DCI                       DCI_BASE
+
+/* registers definitions */
+#define DCI_CTL                   REG32(DCI + 0x00U) /*!< DCI control register */
+#define DCI_STAT0                 REG32(DCI + 0x04U) /*!< DCI status register 0 */
+#define DCI_STAT1                 REG32(DCI + 0x08U) /*!< DCI status register 1 */
+#define DCI_INTEN                 REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
+#define DCI_INTF                  REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
+#define DCI_INTC                  REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
+#define DCI_SC                    REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
+#define DCI_SCUMSK                REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */
+#define DCI_CWSPOS                REG32(DCI + 0x20U) /*!< DCI cropping window start position register */
+#define DCI_CWSZ                  REG32(DCI + 0x24U) /*!< DCI cropping window size register */
+#define DCI_DATA                  REG32(DCI + 0x28U) /*!< DCI data register */
+
+/* bits definitions */
+/* DCI_CTL */
+#define DCI_CTL_CAP               BIT(0)             /*!< capture enable */
+#define DCI_CTL_SNAP              BIT(1)             /*!< snapshot mode */
+#define DCI_CTL_WDEN              BIT(2)             /*!< window enable */
+#define DCI_CTL_JM                BIT(3)             /*!< JPEG mode */
+#define DCI_CTL_ESM               BIT(4)             /*!< embedded synchronous mode */
+#define DCI_CTL_CKS               BIT(5)             /*!< clock polarity selection */
+#define DCI_CTL_HPS               BIT(6)             /*!< horizontal polarity selection */
+#define DCI_CTL_VPS               BIT(7)             /*!< vertical polarity selection */
+#define DCI_CTL_FR                BITS(8,9)          /*!< frame rate */
+#define DCI_CTL_DCIF              BITS(10,11)        /*!< digital camera interface format */
+#define DCI_CTL_DCIEN             BIT(14)            /*!< DCI enable */
+
+/* DCI_STAT0 */
+#define DCI_STAT0_HS              BIT(0)             /*!< HS line status */
+#define DCI_STAT0_VS              BIT(1)             /*!< VS line status */
+#define DCI_STAT0_FV              BIT(2)             /*!< FIFO valid */
+
+/* DCI_STAT1 */
+#define DCI_STAT1_EFF             BIT(0)             /*!< end of frame flag */
+#define DCI_STAT1_OVRF            BIT(1)             /*!< FIFO overrun flag */
+#define DCI_STAT1_ESEF            BIT(2)             /*!< embedded synchronous error flag */
+#define DCI_STAT1_VSF             BIT(3)             /*!< vsync flag */
+#define DCI_STAT1_ELF             BIT(4)             /*!< end of line flag */
+
+/* DCI_INTEN */
+#define DCI_INTEN_EFIE            BIT(0)             /*!< end of frame interrupt enable */
+#define DCI_INTEN_OVRIE           BIT(1)             /*!< FIFO overrun interrupt enable */
+#define DCI_INTEN_ESEIE           BIT(2)             /*!< embedded synchronous error interrupt enable */
+#define DCI_INTEN_VSIE            BIT(3)             /*!< vsync interrupt enable */
+#define DCI_INTEN_ELIE            BIT(4)             /*!< end of line interrupt enable */
+
+/* DCI_INTF */
+#define DCI_INTF_EFIF             BIT(0)             /*!< end of frame interrupt flag */
+#define DCI_INTF_OVRIF            BIT(1)             /*!< FIFO overrun interrupt flag */
+#define DCI_INTF_ESEIF            BIT(2)             /*!< embedded synchronous error interrupt flag */
+#define DCI_INTF_VSIF             BIT(3)             /*!< vsync interrupt flag  */
+#define DCI_INTF_ELIF             BIT(4)             /*!< end of line interrupt flag */
+
+/* DCI_INTC */
+#define DCI_INTC_EFFC             BIT(0)             /*!< clear end of frame flag */
+#define DCI_INTC_OVRFC            BIT(1)             /*!< clear FIFO overrun flag */
+#define DCI_INTC_ESEFC            BIT(2)             /*!< clear embedded synchronous error flag */
+#define DCI_INTC_VSFC             BIT(3)             /*!< vsync flag clear */
+#define DCI_INTC_ELFC             BIT(4)             /*!< end of line flag clear */
+
+/* DCI_SC */
+#define DCI_SC_FS                 BITS(0,7)          /*!< frame start code in embedded synchronous mode */
+#define DCI_SC_LS                 BITS(8,15)         /*!< line start code in embedded synchronous mode */
+#define DCI_SC_LE                 BITS(16,23)        /*!< line end code in embedded synchronous mode */
+#define DCI_SC_FE                 BITS(24,31)        /*!< frame end code in embedded synchronous mode */
+
+/* DCI_SCUNMSK */
+#define DCI_SCUMSK_FSM            BITS(0,7)          /*!< frame start code unmask bits in embedded synchronous mode */
+#define DCI_SCUMSK_LSM            BITS(8,15)         /*!< line start code unmask bits in embedded synchronous mode */
+#define DCI_SCUMSK_LEM            BITS(16,23)        /*!< line end code unmask bits in embedded synchronous mode */
+#define DCI_SCUMSK_FEM            BITS(24,31)        /*!< frame end code unmask bits in embedded synchronous mode */
+
+/* DCI_CWSPOS */
+#define DCI_CWSPOS_WHSP           BITS(0,13)         /*!< window horizontal start position */
+#define DCI_CWSPOS_WVSP           BITS(16,28)        /*!< window vertical start position */
+
+/* DCI_CWSZ */
+#define DCI_CWSZ_WHSZ             BITS(0,13)         /*!< window horizontal size */
+#define DCI_CWSZ_WVSZ             BITS(16,29)        /*!< window vertical size */
+
+/* constants definitions */
+/* DCI parameter structure definitions */
+typedef struct
+{   
+    uint32_t capture_mode;                                           /*!< DCI capture mode: continuous or snapshot */
+    uint32_t clock_polarity;                                         /*!< clock polarity selection */
+    uint32_t hsync_polarity;                                         /*!< horizontal polarity selection */
+    uint32_t vsync_polarity;                                         /*!< vertical polarity selection */
+    uint32_t frame_rate;                                             /*!< frame capture rate */
+    uint32_t interface_format;                                       /*!< digital camera interface format */
+}dci_parameter_struct;                                                         
+
+#define DCI_CAPTURE_MODE_CONTINUOUS   ((uint32_t)0x00000000U)        /*!< continuous capture mode */
+#define DCI_CAPTURE_MODE_SNAPSHOT     DCI_CTL_SNAP                   /*!< snapshot capture mode */
+
+#define DCI_CK_POLARITY_FALLING       ((uint32_t)0x00000000U)        /*!< capture at falling edge */
+#define DCI_CK_POLARITY_RISING        DCI_CTL_CKS                    /*!< capture at rising edge */
+
+#define DCI_HSYNC_POLARITY_LOW        ((uint32_t)0x00000000U)        /*!< low level during blanking period */
+#define DCI_HSYNC_POLARITY_HIGH       DCI_CTL_HPS                    /*!< high level during blanking period */
+
+#define DCI_VSYNC_POLARITY_LOW        ((uint32_t)0x00000000U)        /*!< low level during blanking period */
+#define DCI_VSYNC_POLARITY_HIGH       DCI_CTL_VPS                    /*!< high level during blanking period*/
+ 
+#define CTL_FR(regval)                (BITS(8,9)&((uint32_t)(regval) << 8U))    
+#define DCI_FRAME_RATE_ALL            CTL_FR(0)                      /*!< capture all frames */
+#define DCI_FRAME_RATE_1_2            CTL_FR(1)                      /*!< capture one in 2 frames */
+#define DCI_FRAME_RATE_1_4            CTL_FR(2)                      /*!< capture one in 4 frames */
+
+#define CTL_DCIF(regval)              (BITS(10,11)&((uint32_t)(regval) << 10U)) 
+#define DCI_INTERFACE_FORMAT_8BITS    CTL_DCIF(0)                    /*!< 8-bit data on every pixel clock */
+#define DCI_INTERFACE_FORMAT_10BITS   CTL_DCIF(1)                    /*!< 10-bit data on every pixel clock */
+#define DCI_INTERFACE_FORMAT_12BITS   CTL_DCIF(2)                    /*!< 12-bit data on every pixel clock */
+#define DCI_INTERFACE_FORMAT_14BITS   CTL_DCIF(3)                    /*!< 14-bit data on every pixel clock */
+
+/* DCI interrupt constants definitions */
+#define DCI_INT_EF                    BIT(0)                         /*!< end of frame interrupt */
+#define DCI_INT_OVR                   BIT(1)                         /*!< FIFO overrun interrupt */
+#define DCI_INT_ESE                   BIT(2)                         /*!< embedded synchronous error interrupt */
+#define DCI_INT_VSYNC                 BIT(3)                         /*!< vsync interrupt */
+#define DCI_INT_EL                    BIT(4)                         /*!< end of line interrupt */
+
+/* DCI interrupt flag definitions */
+#define DCI_INT_FLAG_EF               BIT(0)                         /*!< end of frame interrupt flag */
+#define DCI_INT_FLAG_OVR              BIT(1)                         /*!< FIFO overrun interrupt flag */
+#define DCI_INT_FLAG_ESE              BIT(2)                         /*!< embedded synchronous error interrupt flag */
+#define DCI_INT_FLAG_VSYNC            BIT(3)                         /*!< vsync interrupt flag */
+#define DCI_INT_FLAG_EL               BIT(4)                         /*!< end of line interrupt flag */
+
+/* DCI flag definitions */  
+#define DCI_FLAG_HS                   DCI_STAT0_HS                   /*!< HS line status */
+#define DCI_FLAG_VS                   DCI_STAT0_VS                   /*!< VS line status */
+#define DCI_FLAG_FV                   DCI_STAT0_FV                   /*!< FIFO valid */
+#define DCI_FLAG_EF                   (DCI_STAT1_EFF | BIT(31))      /*!< end of frame flag */
+#define DCI_FLAG_OVR                  (DCI_STAT1_OVRF | BIT(31))     /*!< FIFO overrun flag */
+#define DCI_FLAG_ESE                  (DCI_STAT1_ESEF | BIT(31))     /*!< embedded synchronous error flag */
+#define DCI_FLAG_VSYNC                (DCI_STAT1_VSF | BIT(31))      /*!< vsync flag */
+#define DCI_FLAG_EL                   (DCI_STAT1_ELF | BIT(31))      /*!< end of line flag */
+
+/* function declarations */
+/* initialization functions */
+/* DCI deinit */
+void dci_deinit(void);
+/* initialize DCI registers */
+void dci_init(dci_parameter_struct* dci_struct);
+
+/* enable DCI function */
+void dci_enable(void);
+/* disable DCI function */
+void dci_disable(void);
+/* enable DCI capture */
+void dci_capture_enable(void);
+/* disable DCI capture */
+void dci_capture_disable(void);
+/* enable DCI jpeg mode */
+void dci_jpeg_enable(void);
+/* disable DCI jpeg mode */
+void dci_jpeg_disable(void);
+
+/* function configuration */
+/* enable cropping window function */
+void dci_crop_window_enable(void);
+/* disable cropping window function */
+void dci_crop_window_disable(void);
+/* configure DCI cropping window */
+void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
+
+/* enable embedded synchronous mode */
+void dci_embedded_sync_enable(void);
+/* disable embedded synchronous mode */
+void dci_embedded_sync_disable(void);
+/* configure synchronous codes in embedded synchronous mode */
+void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
+/* configure synchronous codes unmask in embedded synchronous mode */
+void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
+/* read DCI data register */
+uint32_t dci_data_read(void);
+
+/* interrupt & flag functions */
+/* get specified flag */
+FlagStatus dci_flag_get(uint32_t flag);
+/* enable specified DCI interrupt */
+void dci_interrupt_enable(uint32_t interrupt);
+/* disable specified DCI interrupt */
+void dci_interrupt_disable(uint32_t interrupt);
+/* get specified interrupt flag */
+FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
+/* clear specified interrupt flag */
+void dci_interrupt_flag_clear(uint32_t int_flag);
+
+#endif /* GD32F20X_DCI_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_dma.h

@@ -0,0 +1,300 @@
+/*!
+    \file  gd32f20x_dma.h
+    \brief definitions for the DMA
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_DMA_H
+#define GD32F20X_DMA_H
+
+#include "gd32f20x.h"
+
+/* DMA definitions */
+#define DMA0                            (DMA_BASE)               /*!< DMA0 base address */
+#define DMA1                            (DMA_BASE + 0x0400U)     /*!< DMA1 base address */
+
+/* registers definitions */
+#define DMA_INTF(dmax)                  REG32((dmax) + 0x00U)    /*!< DMA interrupt flag register */
+#define DMA_INTC(dmax)                  REG32((dmax) + 0x04U)    /*!< DMA interrupt flag clear register */
+
+#define DMA_CH0CTL(dmax)                REG32((dmax) + 0x08U)    /*!< DMA channel 0 control register */
+#define DMA_CH0CNT(dmax)                REG32((dmax) + 0x0CU)    /*!< DMA channel 0 counter register */
+#define DMA_CH0PADDR(dmax)              REG32((dmax) + 0x10U)    /*!< DMA channel 0 peripheral base address register */
+#define DMA_CH0MADDR(dmax)              REG32((dmax) + 0x14U)    /*!< DMA channel 0 memory base address register */
+
+#define DMA_CH1CTL(dmax)                REG32((dmax) + 0x1CU)    /*!< DMA channel 1 control register */
+#define DMA_CH1CNT(dmax)                REG32((dmax) + 0x20U)    /*!< DMA channel 1 counter register */
+#define DMA_CH1PADDR(dmax)              REG32((dmax) + 0x24U)    /*!< DMA channel 1 peripheral base address register */
+#define DMA_CH1MADDR(dmax)              REG32((dmax) + 0x28U)    /*!< DMA channel 1 memory base address register */
+
+#define DMA_CH2CTL(dmax)                REG32((dmax) + 0x30U)    /*!< DMA channel 2 control register */
+#define DMA_CH2CNT(dmax)                REG32((dmax) + 0x34U)    /*!< DMA channel 2 counter register */
+#define DMA_CH2PADDR(dmax)              REG32((dmax) + 0x38U)    /*!< DMA channel 2 peripheral base address register */
+#define DMA_CH2MADDR(dmax)              REG32((dmax) + 0x3CU)    /*!< DMA channel 2 memory base address register */
+
+#define DMA_CH3CTL(dmax)                REG32((dmax) + 0x44U)    /*!< DMA channel 3 control register */
+#define DMA_CH3CNT(dmax)                REG32((dmax) + 0x48U)    /*!< DMA channel 3 counter register */
+#define DMA_CH3PADDR(dmax)              REG32((dmax) + 0x4CU)    /*!< DMA channel 3 peripheral base address register */
+#define DMA_CH3MADDR(dmax)              REG32((dmax) + 0x50U)    /*!< DMA channel 3 memory base address register */
+
+#define DMA_CH4CTL(dmax)                REG32((dmax) + 0x58U)    /*!< DMA channel 4 control register */
+#define DMA_CH4CNT(dmax)                REG32((dmax) + 0x5CU)    /*!< DMA channel 4 counter register */
+#define DMA_CH4PADDR(dmax)              REG32((dmax) + 0x60U)    /*!< DMA channel 4 peripheral base address register */
+#define DMA_CH4MADDR(dmax)              REG32((dmax) + 0x64U)    /*!< DMA channel 4 memory base address register */
+
+#define DMA_CH5CTL(dmax)                REG32((dmax) + 0x6CU)    /*!< DMA channel 5 control register */
+#define DMA_CH5CNT(dmax)                REG32((dmax) + 0x70U)    /*!< DMA channel 5 counter register */
+#define DMA_CH5PADDR(dmax)              REG32((dmax) + 0x74U)    /*!< DMA channel 5 peripheral base address register */
+#define DMA_CH5MADDR(dmax)              REG32((dmax) + 0x78U)    /*!< DMA channel 5 memory base address register */
+
+#define DMA_CH6CTL(dmax)                REG32((dmax) + 0x80U)    /*!< DMA channel 6 control register */
+#define DMA_CH6CNT(dmax)                REG32((dmax) + 0x84U)    /*!< DMA channel 6 counter register */
+#define DMA_CH6PADDR(dmax)              REG32((dmax) + 0x88U)    /*!< DMA channel 6 peripheral base address register */
+#define DMA_CH6MADDR(dmax)              REG32((dmax) + 0x8CU)    /*!< DMA channel 6 memory base address register */
+
+#define DMA_ACFG                        REG32((DMA1) + 0x300U)   /*!< DMA additional configuration register */
+
+/* bits definitions */
+/* DMA_INTF */
+#define DMA_INTF_GIF                    BIT(0)                  /*!< global interrupt flag of channel */
+#define DMA_INTF_FTFIF                  BIT(1)                  /*!< full transfer finish flag of channel */
+#define DMA_INTF_HTFIF                  BIT(2)                  /*!< half transfer finish flag of channel */
+#define DMA_INTF_ERRIF                  BIT(3)                  /*!< error flag of channel */
+
+/* DMA_INTC */
+#define DMA_INTC_GIFC                   BIT(0)                  /*!< clear global interrupt flag of channel */
+#define DMA_INTC_FTFIFC                 BIT(1)                  /*!< clear transfer finish flag of channel */
+#define DMA_INTC_HTFIFC                 BIT(2)                  /*!< clear half transfer finish flag of channel */
+#define DMA_INTC_ERRIFC                 BIT(3)                  /*!< clear error flag of channel */
+
+/* DMA_CHxCTL, x=0..6 */
+#define DMA_CHXCTL_CHEN                 BIT(0)                  /*!< channel enable */
+#define DMA_CHXCTL_FTFIE                BIT(1)                  /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_CHXCTL_HTFIE                BIT(2)                  /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_CHXCTL_ERRIE                BIT(3)                  /*!< enable bit for channel error interrupt */
+#define DMA_CHXCTL_DIR                  BIT(4)                  /*!< transfer direction */
+#define DMA_CHXCTL_CMEN                 BIT(5)                  /*!< circular mode enable */
+#define DMA_CHXCTL_PNAGA                BIT(6)                  /*!< next address generation algorithm of peripheral */
+#define DMA_CHXCTL_MNAGA                BIT(7)                  /*!< next address generation algorithm of memory */
+#define DMA_CHXCTL_PWIDTH               BITS(8,9)               /*!< transfer data width of peripheral */
+#define DMA_CHXCTL_MWIDTH               BITS(10,11)             /*!< transfer data width of memory */
+#define DMA_CHXCTL_PRIO                 BITS(12,13)             /*!< priority level */
+#define DMA_CHXCTL_M2M                  BIT(14)                 /*!< memory to memory mode */
+
+/* DMA_CHxCNT, x=0..6 */
+#define DMA_CHXCNT_CNT                  BITS(0,15)              /*!< transfer counter */
+
+/* DMA_CHxPADDR, x=0..6 */
+#define DMA_CHXPADDR_PADDR              BITS(0,31)              /*!< peripheral base address */
+
+/* DMA_CHxMADDR, x=0..6 */
+#define DMA_CHXMADDR_MADDR              BITS(0,31)              /*!< memory base address */
+
+/* DMA_ACFG */
+#define DMA_ACFG_FD_CH5EN               BIT(5)                  /*!< enable bit for DMA1 channel 5 Full_Data transfer mode */
+
+/* constants definitions */
+/* DMA channel select */
+typedef enum 
+{
+    DMA_CH0 = 0,                /*!< DMA channel 0 */
+    DMA_CH1,                    /*!< DMA channel 1 */ 
+    DMA_CH2,                    /*!< DMA channel 2 */ 
+    DMA_CH3,                    /*!< DMA channel 3 */ 
+    DMA_CH4,                    /*!< DMA channel 4 */ 
+    DMA_CH5,                    /*!< DMA channel 5 */ 
+    DMA_CH6                     /*!< DMA channel 6 */
+} dma_channel_enum;
+
+/* DMA initialize struct */
+typedef struct
+{
+    uint32_t periph_addr;       /*!< peripheral base address */
+    uint32_t periph_width;      /*!< transfer data size of peripheral */
+    uint32_t memory_addr;       /*!< memory base address */
+    uint32_t memory_width;      /*!< transfer data size of memory */
+    uint32_t number;            /*!< channel transfer number */
+    uint32_t priority;          /*!< channel priority level */
+    uint8_t periph_inc;         /*!< peripheral increasing mode */
+    uint8_t memory_inc;         /*!< memory increasing mode */
+    uint8_t direction;          /*!< channel data transfer direction */
+
+} dma_parameter_struct;
+
+#define DMA_FLAG_ADD(flag, shift)           ((flag) << ((shift) * 4U))                      /*!< DMA channel flag shift */
+
+/* DMA_register address */
+#define DMA_CHCTL(dma, channel)             REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXCTL register */
+#define DMA_CHCNT(dma, channel)             REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXCNT register */
+#define DMA_CHPADDR(dma, channel)           REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXPADDR register */
+#define DMA_CHMADDR(dma, channel)           REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel))      /*!< the address of DMA channel CHXMADDR register */
+
+/* DMA reset value */
+#define DMA_CHCTL_RESET_VALUE               ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCTL register */
+#define DMA_CHCNT_RESET_VALUE               ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXCNT register */
+#define DMA_CHPADDR_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXPADDR register */
+#define DMA_CHMADDR_RESET_VALUE             ((uint32_t)0x00000000U)                         /*!< the reset value of DMA channel CHXMADDR register */
+#define DMA_CHINTF_RESET_VALUE              (DMA_INTF_GIF | DMA_INTF_FTFIF | \
+                                             DMA_INTF_HTFIF | DMA_INTF_ERRIF)               /*!< clear DMA channel DMA_INTF register */
+#define DMA_ACFG_RESET_VALUE                ((uint32_t)0x00000000U)                         /*!< the reset value of DMA additional configuration register */
+
+/* DMA_INTF register */
+/* interrupt flag bits */
+#define DMA_INT_FLAG_G                      DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_INT_FLAG_FTF                    DMA_INTF_FTFIF                                  /*!< full transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_HTF                    DMA_INTF_HTFIF                                  /*!< half transfer finish interrupt flag of channel */
+#define DMA_INT_FLAG_ERR                    DMA_INTF_ERRIF                                  /*!< error interrupt flag of channel */
+
+/* flag bits */
+#define DMA_FLAG_G                          DMA_INTF_GIF                                    /*!< global interrupt flag of channel */
+#define DMA_FLAG_FTF                        DMA_INTF_FTFIF                                  /*!< full transfer finish flag of channel */
+#define DMA_FLAG_HTF                        DMA_INTF_HTFIF                                  /*!< half transfer finish flag of channel */
+#define DMA_FLAG_ERR                        DMA_INTF_ERRIF                                  /*!< error flag of channel */
+
+/* DMA_CHxCTL register */
+/* interrupt enable bits */
+#define DMA_INT_FTF                         DMA_CHXCTL_FTFIE                                /*!< enable bit for channel full transfer finish interrupt */
+#define DMA_INT_HTF                         DMA_CHXCTL_HTFIE                                /*!< enable bit for channel half transfer finish interrupt */
+#define DMA_INT_ERR                         DMA_CHXCTL_ERRIE                                /*!< enable bit for channel error interrupt */
+
+/* transfer direction */
+#define DMA_PERIPHERAL_TO_MEMORY            ((uint32_t)0x00000000U)                         /*!< read from peripheral and write to memory */
+#define DMA_MEMORY_TO_PERIPHERAL            ((uint32_t)0x00000001U)                         /*!< read from memory and write to peripheral */
+/* circular mode */
+#define DMA_CIRCULAR_MODE_DISABLE           ((uint32_t)0x00000000U)                         /*!< circular mode disable */
+#define DMA_CIRCULAR_MODE_ENABLE            ((uint32_t)0x00000001U)                         /*!< circular mode enable */
+
+/* peripheral increasing mode */
+#define DMA_PERIPH_INCREASE_DISABLE         ((uint32_t)0x00000000U)                         /*!< next address of peripheral is fixed address mode */
+#define DMA_PERIPH_INCREASE_ENABLE          ((uint32_t)0x00000001U)                         /*!< next address of peripheral is increasing address mode */
+
+/* memory increasing mode */
+#define DMA_MEMORY_INCREASE_DISABLE         ((uint32_t)0x00000000U)                         /*!< next address of memory is fixed address mode */
+#define DMA_MEMORY_INCREASE_ENABLE          ((uint32_t)0x00000001U)                         /*!< next address of memory is increasing address mode */
+
+/* transfer data size of peripheral */
+#define CHCTL_PWIDTH(regval)                (BITS(8,9) & ((regval) << 8))                   /*!< transfer data size of peripheral */
+#define DMA_PERIPHERAL_WIDTH_8BIT           CHCTL_PWIDTH(0U)                                /*!< transfer data size of peripheral is 8-bit */
+#define DMA_PERIPHERAL_WIDTH_16BIT          CHCTL_PWIDTH(1U)                                /*!< transfer data size of peripheral is 16-bit */
+#define DMA_PERIPHERAL_WIDTH_32BIT          CHCTL_PWIDTH(2U)                                /*!< transfer data size of peripheral is 32-bit */
+
+/* transfer data size of memory */
+#define CHCTL_MWIDTH(regval)                (BITS(10,11) & ((regval) << 10))                /*!< transfer data size of memory */
+#define DMA_MEMORY_WIDTH_8BIT               CHCTL_MWIDTH(0U)                                /*!< transfer data size of memory is 8-bit */
+#define DMA_MEMORY_WIDTH_16BIT              CHCTL_MWIDTH(1U)                                /*!< transfer data size of memory is 16-bit */
+#define DMA_MEMORY_WIDTH_32BIT              CHCTL_MWIDTH(2U)                                /*!< transfer data size of memory is 32-bit */
+
+/* channel priority level */
+#define CHCTL_PRIO(regval)                  (BITS(12,13) & ((regval) << 12))                /*!< DMA channel priority level */
+#define DMA_PRIORITY_LOW                    CHCTL_PRIO(0U)                                  /*!< low priority */
+#define DMA_PRIORITY_MEDIUM                 CHCTL_PRIO(1U)                                  /*!< medium priority */
+#define DMA_PRIORITY_HIGH                   CHCTL_PRIO(2U)                                  /*!< high priority */
+#define DMA_PRIORITY_ULTRA_HIGH             CHCTL_PRIO(3U)                                  /*!< ultra high priority */
+
+/* memory to memory mode */
+#define DMA_MEMORY_TO_MEMORY_DISABLE        ((uint32_t)0x00000000U)                         /*!< disable memory to memory mode */
+#define DMA_MEMORY_TO_MEMORY_ENABLE         ((uint32_t)0x00000001U)                         /*!< enable memory to memory mode */
+
+/* DMA_CHxCNT register */
+/* transfer counter */
+#define DMA_CHANNEL_CNT_MASK                DMA_CHXCNT_CNT                                  /*!< transfer counter mask */
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize DMA a channel registers */
+void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
+/* initialize the parameters of DMA structure with the default values */
+void dma_struct_para_init(dma_parameter_struct* init_struct);
+/* initialize DMA channel */
+void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct);
+/* enable DMA circulation mode */
+void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable DMA circulation mode */
+void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable memory to memory mode */
+void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable memory to memory mode */
+void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable DMA channel */
+void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable DMA channel */
+void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
+
+/* DMA configuration functions */
+/* set DMA peripheral base address */
+void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
+/* set DMA memory base address */
+void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
+/* set the number of remaining data to be transferred by the DMA */
+void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
+/* get the number of remaining data to be transferred by the DMA */
+uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
+/* configure priority level of DMA channel */
+void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
+/* configure transfer data size of memory */
+void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
+/* configure transfer data size of peripheral */
+void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
+/* enable next address increment algorithm of memory */
+void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable next address increment algorithm of memory */
+void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* enable next address increment algorithm of peripheral */
+void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
+/* disable next address increment algorithm of peripheral */
+void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
+/* configure the direction of data transfer on the channel */
+void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
+
+/* flag and interrupt functions */
+/* check DMA flag is set or not */
+FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* clear the flag of a DMA channel */
+void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* check DMA flag and interrupt enable bit is set or not */
+FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* clear the interrupt flag of a DMA channel */
+void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
+/* enable DMA interrupt */
+void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
+/* disable DMA interrupt */
+void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
+
+/* enable the DMA1 channel 5 Full_Data transfer mode */
+void dma_1_channel_5_fulldata_transfer_enable(void);
+/* disable the DMA1 channel 5 Full_Data transfer mode */
+void dma_1_channel_5_fulldata_transfer_disable(void);
+
+#endif /* GD32F20X_DMA_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_exmc.h

@@ -0,0 +1,921 @@
+/*!
+    \file  gd32f20x_exmc.h
+    \brief definitions for the EXMC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_EXMC_H
+#define GD32F20X_EXMC_H
+
+#include "gd32f20x.h"
+
+/* EXMC definitions */
+#define EXMC                              (EXMC_BASE)                   /*!< EXMC register base address */
+#define EXMC_NOR_PSRAM                    (EXMC_BASE - 0x40000000)      /*!< EXMC NOR/PSRAM base address */
+#define EXMC_NAND                         (EXMC_BASE - 0x30000000)      /*!< EXMC NAND base address */
+#define EXMC_PCCARD                       (EXMC_BASE - 0x10000000)      /*!< EXMC PC card base address */
+#define EXMC_SDRAM                        (EXMC_BASE + 0x20000000)      /*!< EXMC SDRAM base address */
+
+/* registers definitions */
+/* NOR/PSRAM */
+#define EXMC_SNCTL0                       REG32(EXMC + 0x00U)           /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG0                      REG32(EXMC + 0x04U)           /*!< EXMC SRAM/NOR flash timing configuration register */
+#define EXMC_SNWTCFG0                     REG32(EXMC + 0x104U)          /*!< EXMC SRAM/NOR flash write timing configuration register */
+
+#define EXMC_SNCTL1                       REG32(EXMC + 0x08U)           /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG1                      REG32(EXMC + 0x0CU)           /*!< EXMC SRAM/NOR flash timing configuration register */
+#define EXMC_SNWTCFG1                     REG32(EXMC + 0x10CU)          /*!< EXMC SRAM/NOR flash write timing configuration register */
+
+#define EXMC_SNCTL2                       REG32(EXMC + 0x10U)           /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG2                      REG32(EXMC + 0x14U)           /*!< EXMC SRAM/NOR flash timing configuration register */
+#define EXMC_SNWTCFG2                     REG32(EXMC + 0x114U)          /*!< EXMC SRAM/NOR flash write timing configuration register */
+
+#define EXMC_SNCTL3                       REG32(EXMC + 0x18U)           /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG3                      REG32(EXMC + 0x1CU)           /*!< EXMC SRAM/NOR flash timing configuration register */
+#define EXMC_SNWTCFG3                     REG32(EXMC + 0x11CU)          /*!< EXMC SRAM/NOR flash write timing configuration register */
+
+/* NAND/PC card */
+#define EXMC_NPCTL1                       REG32(EXMC + 0x60U)           /*!< EXMC NAND/PC card control register */
+#define EXMC_NPINTEN1                     REG32(EXMC + 0x64U)           /*!< EXMC NAND/PC card interrupt enable register */
+#define EXMC_NPCTCFG1                     REG32(EXMC + 0x68U)           /*!< EXMC NAND/PC card common space timing configuration register */
+#define EXMC_NPATCFG1                     REG32(EXMC + 0x6CU)           /*!< EXMC NAND/PC card attribute space timing configuration register */
+#define EXMC_NECC1                        REG32(EXMC + 0x74U)           /*!< EXMC NAND ECC register */
+
+#define EXMC_NPCTL2                       REG32(EXMC + 0x80U)           /*!< EXMC NAND/PC card control register */
+#define EXMC_NPINTEN2                     REG32(EXMC + 0x84U)           /*!< EXMC NAND/PC card interrupt enable register */
+#define EXMC_NPCTCFG2                     REG32(EXMC + 0x88U)           /*!< EXMC NAND/PC card common space timing configuration register */
+#define EXMC_NPATCFG2                     REG32(EXMC + 0x8CU)           /*!< EXMC NAND/PC card attribute space timing configuration register */
+#define EXMC_NECC2                        REG32(EXMC + 0x94U)           /*!< EXMC NAND ECC register */
+
+#define EXMC_NPCTL3                       REG32(EXMC + 0xA0U)           /*!< EXMC NAND/PC card control register */
+#define EXMC_NPINTEN3                     REG32(EXMC + 0xA4U)           /*!< EXMC NAND/PC card interrupt enable register */
+#define EXMC_NPCTCFG3                     REG32(EXMC + 0xA8U)           /*!< EXMC NAND/PC card common space timing configuration register */
+#define EXMC_NPATCFG3                     REG32(EXMC + 0xACU)           /*!< EXMC NAND/PC card attribute space timing configuration register */
+#define EXMC_PIOTCFG3                     REG32(EXMC + 0xB0U)           /*!< EXMC PC card I/O space timing configuration register */
+
+/* SDRAM */
+#define EXMC_SDCTL0                       REG32(EXMC + 0x140U)          /*!< EXMC SDRAM control register */
+#define EXMC_SDTCFG0                      REG32(EXMC + 0x148U)          /*!< EXMC SDRAM timing configuration register register */
+
+#define EXMC_SDCTL1                       REG32(EXMC + 0x144U)          /*!< EXMC SDRAM control register */
+#define EXMC_SDTCFG1                      REG32(EXMC + 0x14CU)          /*!< EXMC SDRAM timing configuration register register */
+
+#define EXMC_SDCMD                        REG32(EXMC + 0x150U)          /*!< EXMC SDRAM command register */
+#define EXMC_SDARI                        REG32(EXMC + 0x154U)          /*!< EXMC SDRAM auto-refresh interval register */
+#define EXMC_SDSTAT                       REG32(EXMC + 0x158U)          /*!< EXMC SDRAM status register */
+#define EXMC_SDRSCTL                      REG32(EXMC + 0x180U)          /*!< EXMC SDRAM read sample control register */
+
+/* SQPI PSRAM */
+#define EXMC_SINIT                        REG32(EXMC + 0x310U)          /*!< EXMC SPI initialization register */
+#define EXMC_SRCMD                        REG32(EXMC + 0x320U)          /*!< EXMC SPI read command register */
+#define EXMC_SWCMD                        REG32(EXMC + 0x330U)          /*!< EXMC SPI write command register */
+#define EXMC_SIDL                         REG32(EXMC + 0x340U)          /*!< EXMC SPI ID low register */
+#define EXMC_SIDH                         REG32(EXMC + 0x350U)          /*!< EXMC SPI ID high register */
+
+/* bits definitions */
+/* NOR/PSRAM */
+/* EXMC_SNCTLx,x=0..3 */
+#define EXMC_SNCTL_NRBKEN                 BIT(0)                        /*!< NOR bank enable */
+#define EXMC_SNCTL_NRMUX                  BIT(1)                        /*!< NOR bank memory address/data multiplexing */
+#define EXMC_SNCTL_NRTP                   BITS(2,3)                     /*!< NOR bank memory type */
+#define EXMC_SNCTL_NRW                    BITS(4,5)                     /*!< NOR bank memory data bus width */
+#define EXMC_SNCTL_NREN                   BIT(6)                        /*!< NOR flash access enable */
+#define EXMC_SNCTL_SBRSTEN                BIT(8)                        /*!< synchronous burst enable */
+#define EXMC_SNCTL_NRWTPOL                BIT(9)                        /*!< NWAIT signal polarity */
+#define EXMC_SNCTL_WRAPEN                 BIT(10)                       /*!< wrapped burst mode enable */
+#define EXMC_SNCTL_NRWTCFG                BIT(11)                       /*!< NWAIT signal configuration, only work in synchronous mode  */
+#define EXMC_SNCTL_WREN                   BIT(12)                       /*!< write enable */
+#define EXMC_SNCTL_NRWTEN                 BIT(13)                       /*!< NWAIT signal enable */
+#define EXMC_SNCTL_EXMODEN                BIT(14)                       /*!< extended mode enable */
+#define EXMC_SNCTL_ASYNCWAIT              BIT(15)                       /*!< asynchronous wait */
+#define EXMC_SNCTL_SYNCWR                 BIT(19)                       /*!< synchronous write */
+
+/* EXMC_SNTCFGx,x=0..3 */
+#define EXMC_SNTCFG_ASET                  BITS(0,3)                     /*!< address setup time */
+#define EXMC_SNTCFG_AHLD                  BITS(4,7)                     /*!< address hold time */
+#define EXMC_SNTCFG_DSET                  BITS(8,15)                    /*!< data setup time */
+#define EXMC_SNTCFG_BUSLAT                BITS(16,19)                   /*!< bus latency */
+#define EXMC_SNTCFG_CKDIV                 BITS(20,23)                   /*!< synchronous clock divide ratio */
+#define EXMC_SNTCFG_DLAT                  BITS(24,27)                   /*!< data latency for NOR flash */
+#define EXMC_SNTCFG_ASYNCMOD              BITS(28,29)                   /*!< asynchronous access mode */
+
+/* EXMC_SNWTCFGx,x=0..3 */
+#define EXMC_SNWTCFG_WASET                BITS(0,3)                     /*!< address setup time */
+#define EXMC_SNWTCFG_WAHLD                BITS(4,7)                     /*!< address hold time */
+#define EXMC_SNWTCFG_WDSET                BITS(8,15)                    /*!< data setup time */
+#define EXMC_SNWTCFG_CKDIV                BITS(20,23)                   /*!< synchronous clock divide ratio */
+#define EXMC_SNWTCFG_DLAT                 BITS(24,27)                   /*!< data latency for NOR flash */
+#define EXMC_SNWTCFG_WASYNCMOD            BITS(28,29)                   /*!< asynchronous access mode */
+
+/* NAND/PC card */
+/* EXMC_NPCTLx,x=1..3 */
+#define EXMC_NPCTL_NDWTEN                 BIT(1)                        /*!< wait feature enable */
+#define EXMC_NPCTL_NDBKEN                 BIT(2)                        /*!< NAND bank enable */
+#define EXMC_NPCTL_NDTP                   BIT(3)                        /*!< NAND bank memory type */
+#define EXMC_NPCTL_NDW                    BITS(4,5)                     /*!< NAND bank memory data bus width */
+#define EXMC_NPCTL_ECCEN                  BIT(6)                        /*!< ECC enable */
+#define EXMC_NPCTL_CTR                    BITS(9,12)                    /*!< CLE to RE delay */
+#define EXMC_NPCTL_ATR                    BITS(13,16)                   /*!< ALE to RE delay */
+#define EXMC_NPCTL_ECCSZ                  BITS(17,19)                   /*!< ECC size */
+
+/* EXMC_NPINTENx,x=1..3 */
+#define EXMC_NPINTEN_INTRS                BIT(0)                        /*!< interrupt rising edge status */
+#define EXMC_NPINTEN_INTHS                BIT(1)                        /*!< interrupt high-level status */
+#define EXMC_NPINTEN_INTFS                BIT(2)                        /*!< interrupt falling edge status */
+#define EXMC_NPINTEN_INTREN               BIT(3)                        /*!< interrupt rising edge detection enable */
+#define EXMC_NPINTEN_INTHEN               BIT(4)                        /*!< interrupt high-level detection enable */
+#define EXMC_NPINTEN_INTFEN               BIT(5)                        /*!< interrupt falling edge detection enable */
+#define EXMC_NPINTEN_FFEPT                BIT(6)                        /*!< FIFO empty flag */
+
+/* EXMC_NPCTCFGx,x=1..3 */
+#define EXMC_NPCTCFG_COMSET               BITS(0,7)                     /*!< common memory setup time */
+#define EXMC_NPCTCFG_COMWAIT              BITS(8,15)                    /*!< common memory wait time */
+#define EXMC_NPCTCFG_COMHLD               BITS(16,23)                   /*!< common memory hold time */
+#define EXMC_NPCTCFG_COMHIZ               BITS(24,31)                   /*!< common memory data bus HiZ time */
+
+/* EXMC_NPATCFGx,x=1..3 */
+#define EXMC_NPATCFG_ATTSET               BITS(0,7)                     /*!< attribute memory setup time */
+#define EXMC_NPATCFG_ATTWAIT              BITS(8,15)                    /*!< attribute memory wait time */
+#define EXMC_NPATCFG_ATTHLD               BITS(16,23)                   /*!< attribute memory hold time */
+#define EXMC_NPATCFG_ATTHIZ               BITS(24,31)                   /*!< attribute memory data bus HiZ time */
+
+/* EXMC_PIOTCFG3 */
+#define EXMC_PIOTCFG3_IOSET               BITS(0,7)                     /*!< IO space setup time */
+#define EXMC_PIOTCFG3_IOWAIT              BITS(8,15)                    /*!< IO space wait time */
+#define EXMC_PIOTCFG3_IOHLD               BITS(16,23)                   /*!< IO space hold time */
+#define EXMC_PIOTCFG3_IOHIZ               BITS(24,31)                   /*!< IO space data bus HiZ time */
+
+/* EXMC_NECCx,x=1..2 */
+#define EXMC_NECC_ECC                     BITS(0,31)                    /*!< ECC result */
+
+/* SDRAM */
+/* EXMC_SDCTLx,x=0..1 */
+#define EXMC_SDCTL_CAW                    BITS(0,1)                     /*!< column address bit width */
+#define EXMC_SDCTL_RAW                    BITS(2,3)                     /*!< row address bit width */
+#define EXMC_SDCTL_SDW                    BITS(4,5)                     /*!< SDRAM data bus width */
+#define EXMC_SDCTL_NBK                    BIT(6)                        /*!< number of banks */
+#define EXMC_SDCTL_CL                     BIT(7,8)                      /*!< CAS Latency */
+#define EXMC_SDCTL_WPEN                   BIT(9)                        /*!< write protection enable */
+#define EXMC_SDCTL_SDCLK                  BITS(10,11)                   /*!< SDRAM clock configuration */
+#define EXMC_SDCTL_BRSTRD                 BIT(12)                       /*!< burst read */
+#define EXMC_SDCTL_PIPED                  BITS(13,14)                   /*!< pipeline delay */
+
+/* EXMC_SDTCFGx,x=0..1 */
+#define EXMC_SDTCFG_LMRD                  BITS(0,3)                     /*!< load mode register delay */
+#define EXMC_SDTCFG_XSRD                  BITS(4,7)                     /*!< exit self-refresh delay */
+#define EXMC_SDTCFG_RASD                  BITS(8,11)                    /*!< row address select delay */
+#define EXMC_SDTCFG_ARFD                  BITS(12,15)                   /*!< auto refresh delay */
+#define EXMC_SDTCFG_WRD                   BITS(16,19)                   /*!< write recovery delay */
+#define EXMC_SDTCFG_RPD                   BITS(20,23)                   /*!< row precharge delay */
+#define EXMC_SDTCFG_RCD                   BITS(24,27)                   /*!< row to column delay */
+
+/* EXMC_SDCMD */
+#define EXMC_SDCMD_CMD                    BITS(0,2)                     /*!< command */
+#define EXMC_SDCMD_DS1                    BIT(3)                        /*!< device select 1 */
+#define EXMC_SDCMD_DS0                    BIT(4)                        /*!< device select 0 */
+#define EXMC_SDCMD_NARF                   BITS(5,8)                     /*!< number of successive auto-refresh */
+#define EXMC_SDCMD_MRC                    BITS(9,21)                    /*!< mode register content */
+
+/* EXMC_SDARI */
+#define EXMC_SDARI_REC                    BIT(0)                        /*!< refresh error flag clear */
+#define EXMC_SDARI_ARINTV                 BITS(1,13)                    /*!< auto-refresh interval */
+#define EXMC_SDARI_REIE                   BIT(14)                       /*!< interrupt refresh error enable */
+
+/* EXMC_SDSTAT */
+#define EXMC_SDSDAT_REIF                  BIT(0)                        /*!< refresh error interrupt flag */
+#define EXMC_SDSDAT_STA0                  BITS(1,2)                     /*!< device 0 status */
+#define EXMC_SDSDAT_STA1                  BITS(3,4)                     /*!< device 1 status */
+#define EXMC_SDSDAT_NRDY                  BIT(5)                        /*!< not ready status */
+
+/* EXMC_SDRSCTL */
+#define EXMC_SDRSCTL_RSEN                 BIT(0)                        /*!< read sample enable */
+#define EXMC_SDRSCTL_SSCR                 BIT(1)                        /*!< select sample cycle of read data */
+#define EXMC_SDRSCTL_SDSC                 BITS(4,7)                     /*!< select the delayed sample clock of read data */
+
+/* SQPI PSRAM */
+/* EXMC_SINIT */
+#define EXMC_SINIT_CMDBIT                 BITS(16,17)                   /*!< bit number of SPI PSRAM command phase */
+#define EXMC_SINIT_ARDBIT                 BITS(24,28)                   /*!< bit number of SPI PSRAM address phase */
+#define EXMC_SINIT_IDL                    BITS(29,30)                   /*!< SPI PSRAM ID length */
+#define EXMC_SINIT_POL                    BIT(31)                       /*!< read data sample polarity */
+
+/* EXMC_SRCMD */
+#define EXMC_SRCMD_RCMD                   BITS(0,15)                    /*!< SPI read command for AHB read transfer */
+#define EXMC_SRCMD_RWAITCYCLE             BITS(16,19)                   /*!< SPI read wait cycle number after address phase */
+#define EXMC_SRCMD_RMODE                  BITS(20,21)                   /*!< SPI PSRAM read command mode */
+#define EXMC_SRCMD_RDID                   BIT(31)                       /*!< send SPI read ID command */
+
+/* EXMC_SWCMD */
+#define EXMC_SWCMD_WCMD                   BITS(0,15)                    /*!< SPI write command for AHB write transfer */
+#define EXMC_SWCMD_WWAITCYCLE             BITS(16,19)                   /*!< SPI write wait cycle number after address phase */
+#define EXMC_SWCMD_WMODE                  BITS(20,21)                   /*!< SPI PSRAM write command mode */
+#define EXMC_SWCMD_SC                     BIT(31)                       /*!< send SPI special command */
+
+/* EXMC_SIDL */
+#define EXMC_SIDL_SIDL                    BITS(0,31)                    /*!< ID low data saved for SPI read ID command */
+
+/* EXMC_SIDH */
+#define EXMC_SIDL_SIDH                    BITS(0,31)                    /*!< ID high Data saved for SPI read ID command */
+
+/* constants definitions */
+/* EXMC NOR/SRAM timing initialize structure */
+typedef struct
+{
+    uint32_t asyn_access_mode;                                          /*!< asynchronous access mode */
+    
+    uint32_t syn_data_latency;                                          /*!< configure the data latency */
+                                                                        /*!< the range is EXMC_DATALAT_2_CLK to EXMC_DATALAT_17_CLK */
+                                                                        
+    uint32_t syn_clk_division;                                          /*!< configure the clock divide ratio */
+                                                                        /*!< the range is EXMC_SYN_CLOCK_RATIO_2_CLK to EXMC_SYN_CLOCK_RATIO_16_CLK */
+                                                                        
+    uint32_t bus_latency;                                               /*!< configure the bus latency */
+                                                                        /*!< the range is 1 to 16 HCLK */
+                                                                        
+    uint32_t asyn_data_setuptime;                                       /*!< configure the data setup time,asynchronous access mode valid */
+                                                                        /*!< the range is 2 to 256 HCLK */
+                                                                        
+    uint32_t asyn_address_holdtime;                                     /*!< configure the address hold time,asynchronous access mode valid */
+                                                                        /*!< the range is 2 to 16 HCLK */
+                                                                        
+    uint32_t asyn_address_setuptime;                                    /*!< configure the data setup time,asynchronous access mode valid */
+                                                                        /*!< the range is 1 to 16 HCLK */
+}exmc_norsram_timing_parameter_struct;
+
+/* EXMC NOR/SRAM initialize structure */
+typedef struct
+{
+    uint32_t norsram_region;                                            /*!< select the region of EXMC NOR/SRAM bank */
+                                                                        /*!< norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 */
+    
+    uint32_t write_mode;                                                /*!< the write mode, synchronous mode or asynchronous mode */
+                                                                        /*!< write_mode: EXMC_ASYN_WRITE or EXMC_SYN_WRITE */
+    
+    uint32_t extended_mode;                                             /*!< enable or disable the extended mode */
+                                                                        /*!< extended_mode: ENABLE or DISABLE */
+    
+    uint32_t asyn_wait;                                                 /*!< enable or disable the asynchronous wait function */
+                                                                        /*!< asyn_wait: ENABLE or DISABLE */
+    
+    uint32_t nwait_signal;                                              /*!< enable or disable the NWAIT signal while in synchronous bust mode */
+                                                                        /*!< nwait_signal: ENABLE or DISABLE */
+    
+    uint32_t memory_write;                                              /*!< enable or disable the write operation */
+                                                                        /*!< memory_write: ENABLE or DISABLE */
+    
+    uint32_t nwait_config;                                              /*!< NWAIT signal configuration */
+                                                                        /*!< nwait_config: EXMC_NWAIT_CONFIG_BEFORE or EXMC_NWAIT_CONFIG_DURING */
+    
+    uint32_t wrap_burst_mode;                                           /*!< enable or disable the wrap burst mode */
+                                                                        /*!< wrap_burst_mode: ENABLE or DISABLE */
+                                                                        
+    uint32_t nwait_polarity;                                            /*!< specifies the polarity of NWAIT signal from memory */
+                                                                        /*!< nwait_polarity: EXMC_NWAIT_POLARITY_LOW or EXMC_NWAIT_POLARITY_HIGH */
+                                                                        
+    uint32_t burst_mode;                                                /*!< enable or disable the burst mode */
+                                                                        /*!< burst_mode: ENABLE or DISABLE */
+                                                                        
+    uint32_t databus_width;                                             /*!< specifies the databus width of external memory */
+                                                                        /*!< databus_width: EXMC_NOR_DATABUS_WIDTH_8B or EXMC_NOR_DATABUS_WIDTH_16B */
+                                                                        
+    uint32_t memory_type;                                               /*!< specifies the type of external memory */
+                                                                        /*!< memory_type: EXMC_MEMORY_TYPE_SRAM / EXMC_MEMORY_TYPE_PSRAM / EXMC_MEMORY_TYPE_NOR */
+                                                                        
+    uint32_t address_data_mux;                                          /*!< specifies whether the data bus and address bus are multiplexed */
+                                                                        /*!< address_data_mux: ENABLE or DISABLE */
+                                                                        
+    exmc_norsram_timing_parameter_struct* read_write_timing;            /*!< timing parameters for read and write if the extendedmode is not used or the timing 
+                                                                             parameters for read if the extendedmode is used. */
+                                                                             
+    exmc_norsram_timing_parameter_struct* write_timing;                 /*!< timing parameters for write when the extendedmode is used. */
+}exmc_norsram_parameter_struct;
+
+/* EXMC NAND/PC card timing initialize struct */
+typedef struct
+{
+    uint32_t databus_hiztime;                                           /*!< configure the dadtabus HiZ time for write operation */
+                                                                        /*!< the range is 1 to 256 HCLK */
+    
+    uint32_t holdtime;                                                  /*!< configure the address hold time(or the data hold time for write operation) */
+                                                                        /*!< the range is 1 to 255 HCLK */
+    
+    uint32_t waittime;                                                  /*!< configure the minimum wait time */
+                                                                        /*!< the range is 2 to 256 HCLK (+NWAIT active cycles) */
+    
+    uint32_t setuptime;                                                 /*!< configure the address setup time */
+                                                                        /*!< the range is 1 to 256 HCLK */
+}exmc_nand_pccard_timing_parameter_struct;
+
+/* EXMC NAND initialize structure */
+typedef struct
+{
+    uint32_t nand_bank;                                                 /*!< select the bank of NAND */
+                                                                        /*!< nand_bank: EXMC_BANK1_NAND or EXMC_BANK2_NAND */
+    
+    uint32_t ecc_size;                                                  /*!< the page size for the ECC calculation */
+                                                                        /*!< ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 */
+    
+    uint32_t atr_latency;                                               /*!< configure the latency of ALE low to RB low */ 
+                                                                        /*!< atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 */
+    
+    uint32_t ctr_latency;                                               /*!< configure the latency of CLE low to RB low */
+                                                                        /*!< ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 */
+    
+    uint32_t ecc_logic;                                                 /*!< enable or disable the ECC calculation logic */
+                                                                        /*!< ecc_logic: ENABLE or DISABLE */
+    
+    uint32_t databus_width;                                             /*!< the NAND flash databus width */
+                                                                        /*!< databus_width: EXMC_NAND_DATABUS_WIDTH_8B or EXMC_NAND_DATABUS_WIDTH_16B */
+    
+    uint32_t wait_feature;                                              /*!< enables or disables the wait feature */
+                                                                        /*!< wait_feature: ENABLE or DISABLE */
+    
+    exmc_nand_pccard_timing_parameter_struct* common_space_timing;      /*!< the timing parameters for NAND flash Common Space */
+    
+    exmc_nand_pccard_timing_parameter_struct* attribute_space_timing;   /*!< the timing parameters for NAND flash Attribute Space */
+}exmc_nand_parameter_struct;
+
+/* EXMC PC card initialize structure */
+typedef struct
+{
+    uint32_t atr_latency;                                               /*!< configure the latency of ALE low to RB low */
+                                                                        /*!< atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 */
+                                                                        
+    uint32_t ctr_latency;                                               /*!< configure the latency of CLE low to RB low */
+                                                                        /*!< ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 */
+                                                                        
+    uint32_t wait_feature;                                              /*!< enables or disables the Wait feature */
+                                                                        /*!< wait_feature: ENABLE or DISABLE */
+                                                                        
+    exmc_nand_pccard_timing_parameter_struct*  common_space_timing;     /*!< the timing parameters for NAND flash Common Space */
+                                                                      
+    exmc_nand_pccard_timing_parameter_struct*  attribute_space_timing;  /*!< the timing parameters for NAND flash Attribute Space */  
+    
+    exmc_nand_pccard_timing_parameter_struct*  io_space_timing;         /*!< the timing parameters for NAND flash IO Space */
+}exmc_pccard_parameter_struct;;
+
+/* EXMC SDRAM timing initialize structure */
+typedef struct
+{
+    uint32_t row_to_column_delay;                                       /*!< configure the row to column delay */
+                                                                        /*!< the range is 1 to 16 cycles */
+                                                                        
+    uint32_t row_precharge_delay;                                       /*!< configure the row precharge delay */
+                                                                        /*!< the range is 1 to 16 cycles */
+                                                                        
+    uint32_t write_recovery_delay;                                      /*!< configure the write recovery delay */
+                                                                        /*!< the range is 1 to 16 cycles */
+                                                                        
+    uint32_t auto_refresh_delay;                                        /*!< configure the auto refresh delay */ 
+                                                                        /*!< the range is 1 to 16 cycles */
+                                                                        
+    uint32_t row_address_select_delay;                                  /*!< configure the row address select delay */
+                                                                        /*!< the range is 1 to 16 cycles */
+                                                                        
+    uint32_t exit_selfrefresh_delay;                                    /*!< configure the exit self-refresh delay */
+                                                                        /*!< the range is 1 to 16 cycles */
+                                                                        
+    uint32_t load_mode_register_delay;                                  /*!< configure the load mode register delay */
+                                                                        /*!< the range is 1 to 16 cycles */
+}exmc_sdram_timing_parameter_struct;
+
+/* EXMC SDRAM initialize structure */
+typedef struct
+{
+    uint32_t sdram_device;                                              /*!< device of SDRAM */
+                                                                        /*!< sdram_device: EXMC_SDRAM_DEVICE0 or EXMC_SDRAM_DEVICE1 */
+                                                                        
+    uint32_t pipeline_read_delay;                                       /*!< the delay for reading data after CAS latency in HCLK clock cycles */
+                                                                        /*!< pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK, x=0..2 */
+                                                                        
+    uint32_t brust_read_switch;                                         /*!< enable or disable the burst read */
+                                                                        /*!< brust_read_switch: ENABLE or DISABLE */
+                                                                        
+    uint32_t sdclock_config;                                            /*!< the SDCLK memory clock for both SDRAM banks */
+                                                                        /*!< sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK */
+                                                                        
+    uint32_t write_protection;                                          /*!< enable or disable SDRAM bank write protection function */
+                                                                        /*!< write_protection: ENABLE or DISABLE */
+                                                                        
+    uint32_t cas_latency;                                               /*!< configure the SDRAM CAS latency */
+                                                                        /*!< cas_latency: EXMC_CAS_LATENCY_x_SDCLK, x=1..3 */
+                                                                        
+    uint32_t internal_bank_number;                                      /*!< the number internal banks */
+                                                                        /*!< internal_bank_number: EXMC_SDRAM_2_INTER_BANK or EXMC_SDRAM_4_INTER_BANK */
+                                                                        
+    uint32_t data_width;                                                /*!< the databus width of SDRAM memory */
+                                                                        /*!< data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B */
+                                                                        
+    uint32_t row_address_width;                                         /*!< the bit width of a row address */
+                                                                        /*!< row_address_width: EXMC_SDRAM_ROW_ADDRESS_x, x=11..13 */
+                                                                        
+    uint32_t column_address_width;                                      /*!< the bit width of a column address */
+                                                                        /*!< column_address_width: EXMC_SDRAM_COW_ADDRESS_x, x=8..11 */
+                                                                        
+    exmc_sdram_timing_parameter_struct* timing;                         /*!< the timing parameters for write and read SDRAM */
+}exmc_sdram_parameter_struct;
+
+/* EXMC SDRAM command initialize structure */
+typedef struct
+{
+    uint32_t mode_register_content;                                     /*!< the SDRAM mode register content */
+                                                                        /*!< mode_register_content: */
+                                                                        
+    uint32_t auto_refresh_number;                                       /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */
+                                                                        /*!< auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 */
+                                                                        
+    uint32_t bank_select;                                               /*!< the bank which command will be sent to */
+                                                                        /*!< bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT */
+                                                                        
+    uint32_t command;                                                   /*!< the commands that will be sent to SDRAM */
+                                                                        /*!< command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, 
+                                                                                      EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, 
+                                                                                      EXMC_SDRAM_POWERDOWN_ENTRY */
+}exmc_sdram_command_parameter_struct;
+
+/* EXMC SQPISRAM initialize structure */
+typedef struct{
+    uint32_t sample_polarity;                                           /*!< read data sample polarity */
+                                                                        /*!< sample_polarity: EXMC_SDRAM_SAMPLE_RISING_EDGE,EXMC_SDRAM_SAMPLE_FALLING_EDGE */
+                                                                        
+    uint32_t id_length;                                                 /*!< SPI PSRAM ID length */
+                                                                        /*!< id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 */
+                                                                        
+    uint32_t address_bits;                                              /*!< bit number of SPI PSRAM address phase */
+                                                                        /*!< address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 */
+                                                                        
+    uint32_t command_bits;                                              /*!< bit number of SPI PSRAM command phase */
+                                                                        /*!< command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 */
+}exmc_sqpipsram_parameter_struct;
+
+/* EXMC NOR/SRAM bank region definition */
+#define EXMC_BANK0_NORSRAM_REGION0        ((uint32_t)0x00000000U)       /*!< bank0 NOR/SRAM region0 */
+#define EXMC_BANK0_NORSRAM_REGION1        ((uint32_t)0x00000001U)       /*!< bank0 NOR/SRAM region1 */
+#define EXMC_BANK0_NORSRAM_REGION2        ((uint32_t)0x00000002U)       /*!< bank0 NOR/SRAM region2 */
+#define EXMC_BANK0_NORSRAM_REGION3        ((uint32_t)0x00000003U)       /*!< bank0 NOR/SRAM region3 */
+
+/* EXMC NAND/PC card bank definition */
+#define EXMC_BANK1_NAND                   ((uint32_t)0x00000001U)       /*!< bank1 NAND flash */
+#define EXMC_BANK2_NAND                   ((uint32_t)0x00000002U)       /*!< bank2 NAND flash */
+#define EXMC_BANK3_PCCARD                 ((uint32_t)0x00000003U)       /*!< bank3 PC card */
+
+/* EXMC SDRAM bank definition */
+#define EXMC_SDRAM_DEVICE0                ((uint32_t)0x00000004U)       /*!< SDRAM device0 */
+#define EXMC_SDRAM_DEVICE1                ((uint32_t)0x00000005U)       /*!< SDRAM device1 */
+
+/* EXMC_register address */
+#define EXMC_SNCTL(bank)                  REG32(EXMC + 0x08U*((uint32_t)(bank)))        /*!< EXMC SRAM/NOR flash control register */
+#define EXMC_SNTCFG(bank)                 REG32(EXMC + 0x04U + 0x08U*(bank))            /*!< EXMC SRAM/NOR flash timing configuration register */
+#define EXMC_SNWTCFG(bank)                REG32(EXMC + 0x104U + 0x08U*(bank))           /*!< EXMC SRAM/NOR flash write timing configuration register */
+
+#define EXMC_NPCTL(bank)                  REG32(EXMC + 0x40U + 0x20U*(bank))            /*!< EXMC NAND/PC card control register */
+#define EXMC_NPINTEN(bank)                REG32(EXMC + 0x44U + 0x20U*(bank))            /*!< EXMC NAND/PC card interrupt enable register */
+#define EXMC_NPCTCFG(bank)                REG32(EXMC + 0x48U + 0x20U*(bank))            /*!< EXMC NAND/PC card common space timing configuration register */
+#define EXMC_NPATCFG(bank)                REG32(EXMC + 0x4CU + 0x20U*(bank))            /*!< EXMC NAND/PC card attribute space timing configuration register */
+#define EXMC_NECC(bank)                   REG32(EXMC + 0x54U + 0x20U*(bank))            /*!< EXMC NAND ECC register */
+
+#define EXMC_SDCTL(bank)                  REG32(EXMC + 0x140U + 0x4U*((bank) - 0x4U))   /*!< EXMC SDRAM control register */
+#define EXMC_SDTCFG(bank)                 REG32(EXMC + 0x148U + 0x4U*((bank) - 0x4U))   /*!< EXMC SDRAM timing configuration register */
+
+/* NOR/PSRAM */
+/* NOR bank memory data bus width */
+#define SNCTL_NRW(regval)                 (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define EXMC_NOR_DATABUS_WIDTH_8B         SNCTL_NRW(0)                  /*!< NOR data width 8 bits */
+#define EXMC_NOR_DATABUS_WIDTH_16B        SNCTL_NRW(1)                  /*!< NOR data width 16 bits */
+
+/* NOR bank memory type */
+#define SNCTL_NRTP(regval)                (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define EXMC_MEMORY_TYPE_SRAM             SNCTL_NRTP(0)                 /*!< SRAM,ROM */
+#define EXMC_MEMORY_TYPE_PSRAM            SNCTL_NRTP(1)                 /*!< PSRAM,CRAM */
+#define EXMC_MEMORY_TYPE_NOR              SNCTL_NRTP(2)                 /*!< NOR flash */
+
+/* asynchronous access mode */
+#define SNTCFG_ASYNCMOD(regval)           (BITS(28,29) & ((uint32_t)(regval) << 28))
+#define EXMC_ACCESS_MODE_A                SNTCFG_ASYNCMOD(0)            /*!< mode A access */
+#define EXMC_ACCESS_MODE_B                SNTCFG_ASYNCMOD(1)            /*!< mode B access */
+#define EXMC_ACCESS_MODE_C                SNTCFG_ASYNCMOD(2)            /*!< mode C access */
+#define EXMC_ACCESS_MODE_D                SNTCFG_ASYNCMOD(3)            /*!< mode D access */
+
+/* data latency for NOR flash */
+#define SNTCFG_DLAT(regval)               (BITS(24,27) & ((uint32_t)(regval) << 24))
+#define EXMC_DATALAT_2_CLK                SNTCFG_DLAT(0)                /*!< data latency 2 EXMC_CLK */
+#define EXMC_DATALAT_3_CLK                SNTCFG_DLAT(1)                /*!< data latency 3 EXMC_CLK */
+#define EXMC_DATALAT_4_CLK                SNTCFG_DLAT(2)                /*!< data latency 4 EXMC_CLK */
+#define EXMC_DATALAT_5_CLK                SNTCFG_DLAT(3)                /*!< data latency 5 EXMC_CLK */
+#define EXMC_DATALAT_6_CLK                SNTCFG_DLAT(4)                /*!< data latency 6 EXMC_CLK */
+#define EXMC_DATALAT_7_CLK                SNTCFG_DLAT(5)                /*!< data latency 7 EXMC_CLK */
+#define EXMC_DATALAT_8_CLK                SNTCFG_DLAT(6)                /*!< data latency 8 EXMC_CLK */
+#define EXMC_DATALAT_9_CLK                SNTCFG_DLAT(7)                /*!< data latency 9 EXMC_CLK */
+#define EXMC_DATALAT_10_CLK               SNTCFG_DLAT(8)                /*!< data latency 10 EXMC_CLK */
+#define EXMC_DATALAT_11_CLK               SNTCFG_DLAT(9)                /*!< data latency 11 EXMC_CLK */
+#define EXMC_DATALAT_12_CLK               SNTCFG_DLAT(10)               /*!< data latency 12 EXMC_CLK */
+#define EXMC_DATALAT_13_CLK               SNTCFG_DLAT(11)               /*!< data latency 13 EXMC_CLK */
+#define EXMC_DATALAT_14_CLK               SNTCFG_DLAT(12)               /*!< data latency 14 EXMC_CLK */
+#define EXMC_DATALAT_15_CLK               SNTCFG_DLAT(13)               /*!< data latency 15 EXMC_CLK */
+#define EXMC_DATALAT_16_CLK               SNTCFG_DLAT(14)               /*!< data latency 16 EXMC_CLK */
+#define EXMC_DATALAT_17_CLK               SNTCFG_DLAT(15)               /*!< data latency 17 EXMC_CLK */
+
+/* synchronous clock divide ratio */
+#define SNTCFG_CKDIV(regval)              (BITS(20,23) & ((uint32_t)(regval) << 20))
+#define EXMC_SYN_CLOCK_RATIO_2_CLK        SNTCFG_CKDIV(1)               /*!< EXMC_CLK = 2*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_3_CLK        SNTCFG_CKDIV(2)               /*!< EXMC_CLK = 3*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_4_CLK        SNTCFG_CKDIV(3)               /*!< EXMC_CLK = 4*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_5_CLK        SNTCFG_CKDIV(4)               /*!< EXMC_CLK = 5*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_6_CLK        SNTCFG_CKDIV(5)               /*!< EXMC_CLK = 6*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_7_CLK        SNTCFG_CKDIV(6)               /*!< EXMC_CLK = 7*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_8_CLK        SNTCFG_CKDIV(7)               /*!< EXMC_CLK = 8*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_9_CLK        SNTCFG_CKDIV(8)               /*!< EXMC_CLK = 9*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_10_CLK       SNTCFG_CKDIV(9)               /*!< EXMC_CLK = 10*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_11_CLK       SNTCFG_CKDIV(10)              /*!< EXMC_CLK = 11*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_12_CLK       SNTCFG_CKDIV(11)              /*!< EXMC_CLK = 12*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_13_CLK       SNTCFG_CKDIV(12)              /*!< EXMC_CLK = 13*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_14_CLK       SNTCFG_CKDIV(13)              /*!< EXMC_CLK = 14*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_15_CLK       SNTCFG_CKDIV(14)              /*!< EXMC_CLK = 15*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_16_CLK       SNTCFG_CKDIV(15)              /*!< EXMC_CLK = 16*HCLK */
+/* EXMC NOR/SRAM write mode */
+#define EXMC_ASYN_WRITE                   ((uint32_t)0x00000000U)       /*!< asynchronous write mode */
+#define EXMC_SYN_WRITE                    EXMC_SNCTL_SYNCWR             /*!< synchronous write mode */
+
+/* EXMC NWAIT signal configuration */
+#define EXMC_NWAIT_CONFIG_BEFORE          ((uint32_t)0x00000000U)       /*!< NWAIT signal is active one data cycle before wait state */
+#define EXMC_NWAIT_CONFIG_DURING          EXMC_SNCTL_NRWTCFG            /*!< NWAIT signal is active during wait state */
+
+/* EXMC NWAIT signal polarity configuration */
+#define EXMC_NWAIT_POLARITY_LOW           ((uint32_t)0x00000000U)       /*!< low level is active of NWAIT */
+#define EXMC_NWAIT_POLARITY_HIGH          EXMC_SNCTL_NRWTPOL            /*!< high level is active of NWAIT */
+
+/* NAND/PC card */
+/* ECC size */
+#define NPCTL_ECCSZ(regval)               (BITS(17,19) & ((uint32_t)(regval) << 17))
+#define EXMC_ECC_SIZE_256BYTES            NPCTL_ECCSZ(0)                /* 256 bytes */
+#define EXMC_ECC_SIZE_512BYTES            NPCTL_ECCSZ(1)                /* 512 bytes */
+#define EXMC_ECC_SIZE_1024BYTES           NPCTL_ECCSZ(2)                /* 1024 bytes */
+#define EXMC_ECC_SIZE_2048BYTES           NPCTL_ECCSZ(3)                /* 2048 bytes */
+#define EXMC_ECC_SIZE_4096BYTES           NPCTL_ECCSZ(4)                /* 4096 bytes */
+#define EXMC_ECC_SIZE_8192BYTES           NPCTL_ECCSZ(5)                /* 8192 bytes */
+
+/* ALE to RE delay */
+#define NPCTL_ATR(regval)                 (BITS(13,16) & ((uint32_t)(regval) << 13))
+#define EXMC_ALE_RE_DELAY_1_HCLK          NPCTL_ATR(0)                  /* ALE to RE delay = 1*HCLK */
+#define EXMC_ALE_RE_DELAY_2_HCLK          NPCTL_ATR(1)                  /* ALE to RE delay = 2*HCLK */
+#define EXMC_ALE_RE_DELAY_3_HCLK          NPCTL_ATR(2)                  /* ALE to RE delay = 3*HCLK */
+#define EXMC_ALE_RE_DELAY_4_HCLK          NPCTL_ATR(3)                  /* ALE to RE delay = 4*HCLK */
+#define EXMC_ALE_RE_DELAY_5_HCLK          NPCTL_ATR(4)                  /* ALE to RE delay = 5*HCLK */
+#define EXMC_ALE_RE_DELAY_6_HCLK          NPCTL_ATR(5)                  /* ALE to RE delay = 6*HCLK */
+#define EXMC_ALE_RE_DELAY_7_HCLK          NPCTL_ATR(6)                  /* ALE to RE delay = 7*HCLK */
+#define EXMC_ALE_RE_DELAY_8_HCLK          NPCTL_ATR(7)                  /* ALE to RE delay = 8*HCLK */
+#define EXMC_ALE_RE_DELAY_9_HCLK          NPCTL_ATR(8)                  /* ALE to RE delay = 9*HCLK */
+#define EXMC_ALE_RE_DELAY_10_HCLK         NPCTL_ATR(9)                  /* ALE to RE delay = 10*HCLK */
+#define EXMC_ALE_RE_DELAY_11_HCLK         NPCTL_ATR(10)                 /* ALE to RE delay = 11*HCLK */
+#define EXMC_ALE_RE_DELAY_12_HCLK         NPCTL_ATR(11)                 /* ALE to RE delay = 12*HCLK */
+#define EXMC_ALE_RE_DELAY_13_HCLK         NPCTL_ATR(12)                 /* ALE to RE delay = 13*HCLK */
+#define EXMC_ALE_RE_DELAY_14_HCLK         NPCTL_ATR(13)                 /* ALE to RE delay = 14*HCLK */
+#define EXMC_ALE_RE_DELAY_15_HCLK         NPCTL_ATR(14)                 /* ALE to RE delay = 15*HCLK */
+#define EXMC_ALE_RE_DELAY_16_HCLK         NPCTL_ATR(15)                 /* ALE to RE delay = 16*HCLK */
+
+/* CLE to RE delay */
+#define NPCTL_CTR(regval)                 (BITS(9,12) & ((uint32_t)(regval) << 9))
+#define EXMC_CLE_RE_DELAY_1_HCLK          NPCTL_CTR(0)                  /* CLE to RE delay = 1*HCLK */
+#define EXMC_CLE_RE_DELAY_2_HCLK          NPCTL_CTR(1)                  /* CLE to RE delay = 2*HCLK */
+#define EXMC_CLE_RE_DELAY_3_HCLK          NPCTL_CTR(2)                  /* CLE to RE delay = 3*HCLK */
+#define EXMC_CLE_RE_DELAY_4_HCLK          NPCTL_CTR(3)                  /* CLE to RE delay = 4*HCLK */
+#define EXMC_CLE_RE_DELAY_5_HCLK          NPCTL_CTR(4)                  /* CLE to RE delay = 5*HCLK */
+#define EXMC_CLE_RE_DELAY_6_HCLK          NPCTL_CTR(5)                  /* CLE to RE delay = 6*HCLK */
+#define EXMC_CLE_RE_DELAY_7_HCLK          NPCTL_CTR(6)                  /* CLE to RE delay = 7*HCLK */
+#define EXMC_CLE_RE_DELAY_8_HCLK          NPCTL_CTR(7)                  /* CLE to RE delay = 8*HCLK */
+#define EXMC_CLE_RE_DELAY_9_HCLK          NPCTL_CTR(8)                  /* CLE to RE delay = 9*HCLK */
+#define EXMC_CLE_RE_DELAY_10_HCLK         NPCTL_CTR(9)                  /* CLE to RE delay = 10*HCLK */
+#define EXMC_CLE_RE_DELAY_11_HCLK         NPCTL_CTR(10)                 /* CLE to RE delay = 11*HCLK */
+#define EXMC_CLE_RE_DELAY_12_HCLK         NPCTL_CTR(11)                 /* CLE to RE delay = 12*HCLK */
+#define EXMC_CLE_RE_DELAY_13_HCLK         NPCTL_CTR(12)                 /* CLE to RE delay = 13*HCLK */
+#define EXMC_CLE_RE_DELAY_14_HCLK         NPCTL_CTR(13)                 /* CLE to RE delay = 14*HCLK */
+#define EXMC_CLE_RE_DELAY_15_HCLK         NPCTL_CTR(14)                 /* CLE to RE delay = 15*HCLK */
+#define EXMC_CLE_RE_DELAY_16_HCLK         NPCTL_CTR(15)                 /* CLE to RE delay = 16*HCLK */
+
+/* NAND bank memory data bus width */
+#define NPCTL_NDW(regval)                 (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define EXMC_NAND_DATABUS_WIDTH_8B        NPCTL_NDW(0)                  /*!< NAND data width 8 bits */
+#define EXMC_NAND_DATABUS_WIDTH_16B       NPCTL_NDW(1)                  /*!< NAND data width 16 bits */
+
+/* SDRAM */
+/* SDRAM pipeline delay */
+#define SDCTL_PIPED(regval)               (BITS(13,14) & ((uint32_t)(regval) << 13))
+#define EXMC_PIPELINE_DELAY_0_HCLK        SDCTL_PIPED(0)                /*!< 0 HCLK clock cycle delay */
+#define EXMC_PIPELINE_DELAY_1_HCLK        SDCTL_PIPED(1)                /*!< 1 HCLK clock cycle delay */
+#define EXMC_PIPELINE_DELAY_2_HCLK        SDCTL_PIPED(2)                /*!< 2 HCLK clock cycle delay */
+
+/* SDRAM clock configuration */
+#define SDCTL_SDCLK(regval)               (BITS(10,11) & ((uint32_t)(regval) << 10))
+#define EXMC_SDCLK_DISABLE                SDCTL_SDCLK(0)                /*!< SDCLK memory clock disabled */
+#define EXMC_SDCLK_PERIODS_2_HCLK         SDCTL_SDCLK(2)                /*!< SDCLK memory period = 2*HCLK */
+#define EXMC_SDCLK_PERIODS_3_HCLK         SDCTL_SDCLK(3)                /*!< SDCLK memory period = 3*HCLK */
+
+/* CAS latency */
+#define SDCTL_CL(regval)                  (BITS(7,8) & ((uint32_t)(regval) << 7))
+#define EXMC_CAS_LATENCY_1_SDCLK          SDCTL_CL(1)                   /*!< CAS latency is 1 memory clock cycle */
+#define EXMC_CAS_LATENCY_2_SDCLK          SDCTL_CL(2)                   /*!< CAS latency is 2 memory clock cycle */
+#define EXMC_CAS_LATENCY_3_SDCLK          SDCTL_CL(3)                   /*!< CAS latency is 3 memory clock cycle */
+
+/* SDRAM data bus width */
+#define SDCTL_SDW(regval)                 (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define EXMC_SDRAM_DATABUS_WIDTH_8B       SDCTL_SDW(0)                  /*!< SDRAM data width 8 bits */
+#define EXMC_SDRAM_DATABUS_WIDTH_16B      SDCTL_SDW(1)                  /*!< SDRAM data width 16 bits */
+#define EXMC_SDRAM_DATABUS_WIDTH_32B      SDCTL_SDW(2)                  /*!< SDRAM data width 32 bits */
+
+/* SDRAM row address bit width */
+#define SDCTL_RAW(regval)                 (BITS(2,3) & ((uint32_t)(regval) << 2))
+#define EXMC_SDRAM_ROW_ADDRESS_11         SDCTL_RAW(0)                  /*!< row address bit width is 11 bits */
+#define EXMC_SDRAM_ROW_ADDRESS_12         SDCTL_RAW(1)                  /*!< row address bit width is 12 bits */
+#define EXMC_SDRAM_ROW_ADDRESS_13         SDCTL_RAW(2)                  /*!< row address bit width is 13 bits */
+
+/* SDRAM column address bit width */
+#define SDCTL_CAW(regval)                 (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define EXMC_SDRAM_COW_ADDRESS_8          SDCTL_CAW(0)                  /*!< column address bit width is 8 bits */
+#define EXMC_SDRAM_COW_ADDRESS_9          SDCTL_CAW(1)                  /*!< column address bit width is 9 bits */
+#define EXMC_SDRAM_COW_ADDRESS_10         SDCTL_CAW(2)                  /*!< column address bit width is 10 bits */
+#define EXMC_SDRAM_COW_ADDRESS_11         SDCTL_CAW(3)                  /*!< column address bit width is 11 bits */
+
+/* SDRAM number of successive auto-refresh */
+#define SDCMD_NARF(regval)                (BITS(5,8) & ((uint32_t)(regval) << 5))
+#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK   SDCMD_NARF(0)                 /*!< 1 auto-refresh cycle */
+#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK   SDCMD_NARF(1)                 /*!< 2 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK   SDCMD_NARF(2)                 /*!< 3 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK   SDCMD_NARF(3)                 /*!< 4 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK   SDCMD_NARF(4)                 /*!< 5 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK   SDCMD_NARF(5)                 /*!< 6 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK   SDCMD_NARF(6)                 /*!< 7 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK   SDCMD_NARF(7)                 /*!< 8 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK   SDCMD_NARF(8)                 /*!< 9 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK  SDCMD_NARF(9)                 /*!< 10 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK  SDCMD_NARF(10)                /*!< 11 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK  SDCMD_NARF(11)                /*!< 12 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK  SDCMD_NARF(12)                /*!< 13 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK  SDCMD_NARF(13)                /*!< 14 auto-refresh cycles */
+#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK  SDCMD_NARF(14)                /*!< 15 auto-refresh cycles */
+
+/* SDRAM command select */
+#define SDCMD_CMD(regval)                 (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define EXMC_SDRAM_NORMAL_OPERATION       SDCMD_CMD(0)                  /*!< normal operation command */
+#define EXMC_SDRAM_CLOCK_ENABLE           SDCMD_CMD(1)                  /*!< clock enable command */
+#define EXMC_SDRAM_PRECHARGE_ALL          SDCMD_CMD(2)                  /*!< precharge all command */
+#define EXMC_SDRAM_AUTO_REFRESH           SDCMD_CMD(3)                  /*!< auto-refresh command */
+#define EXMC_SDRAM_LOAD_MODE_REGISTER     SDCMD_CMD(4)                  /*!< load mode register command */
+#define EXMC_SDRAM_SELF_REFRESH           SDCMD_CMD(5)                  /*!< self-refresh command */
+#define EXMC_SDRAM_POWERDOWN_ENTRY        SDCMD_CMD(6)                  /*!< power-down entry command */
+
+/* SDRAM the delayed sample clock of read data */
+#define SDRSCTL_SDSC(regval)              (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define EXMC_SDRAM_0_DELAY_CELL           SDRSCTL_SDSC(0)               /*!< select the clock after 0 delay cell */
+#define EXMC_SDRAM_1_DELAY_CELL           SDRSCTL_SDSC(1)               /*!< select the clock after 1 delay cell */
+#define EXMC_SDRAM_2_DELAY_CELL           SDRSCTL_SDSC(2)               /*!< select the clock after 2 delay cell */
+#define EXMC_SDRAM_3_DELAY_CELL           SDRSCTL_SDSC(3)               /*!< select the clock after 3 delay cell */
+#define EXMC_SDRAM_4_DELAY_CELL           SDRSCTL_SDSC(4)               /*!< select the clock after 4 delay cell */
+#define EXMC_SDRAM_5_DELAY_CELL           SDRSCTL_SDSC(5)               /*!< select the clock after 5 delay cell */
+#define EXMC_SDRAM_6_DELAY_CELL           SDRSCTL_SDSC(6)               /*!< select the clock after 6 delay cell */
+#define EXMC_SDRAM_7_DELAY_CELL           SDRSCTL_SDSC(7)               /*!< select the clock after 7 delay cell */
+#define EXMC_SDRAM_8_DELAY_CELL           SDRSCTL_SDSC(8)               /*!< select the clock after 8 delay cell */
+#define EXMC_SDRAM_9_DELAY_CELL           SDRSCTL_SDSC(9)               /*!< select the clock after 9 delay cell */
+#define EXMC_SDRAM_10_DELAY_CELL          SDRSCTL_SDSC(10)              /*!< select the clock after 10 delay cell */
+#define EXMC_SDRAM_11_DELAY_CELL          SDRSCTL_SDSC(11)              /*!< select the clock after 11 delay cell */
+#define EXMC_SDRAM_12_DELAY_CELL          SDRSCTL_SDSC(12)              /*!< select the clock after 12 delay cell */
+#define EXMC_SDRAM_13_DELAY_CELL          SDRSCTL_SDSC(13)              /*!< select the clock after 13 delay cell */
+#define EXMC_SDRAM_14_DELAY_CELL          SDRSCTL_SDSC(14)              /*!< select the clock after 14 delay cell */
+#define EXMC_SDRAM_15_DELAY_CELL          SDRSCTL_SDSC(15)              /*!< select the clock after 15 delay cell */
+
+ /* EXMC SDRAM internal banks */
+#define EXMC_SDRAM_2_INTER_BANK           ((uint32_t)0x00000000U)       /*!< 2 internal banks */
+#define EXMC_SDRAM_4_INTER_BANK           EXMC_SDCTL_NBK                /*!< 4 internal banks */
+
+/* SDRAM device0 select */
+#define EXMC_SDRAM_DEVICE0_SELECT         EXMC_SDCMD_DS0                /*!< SDRAM Device0 is selected */
+
+/* SDRAM device1 select */
+#define EXMC_SDRAM_DEVICE1_SELECT         EXMC_SDCMD_DS1                /*!< SDRAM Device1 is selected */
+
+/* SDRAM device0 and device1 select */
+#define EXMC_SDRAM_DEVICE0_1_SELECT       (EXMC_SDCMD_DS0 | EXMC_SDCMD_DS1)  /*!< SDRAM Device1 is selected */
+
+/* SDRAM device status */
+#define EXMC_SDRAM_DEVICE_NORMAL            ((uint32_t)0x00000000U)     /*!< normal status */
+#define EXMC_SDRAM_DEVICE_SELF_REFRESH      ((uint32_t)0x00000001U)     /*!< self refresh status */
+#define EXMC_SDRAM_DEVICE_POWER_DOWN        ((uint32_t)0x00000002U)     /*!< power down status */
+
+/* sample cycle of read data */
+#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK   ((uint32_t)0x00000000U)     /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */
+#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK   EXMC_SDRSCTL_SSCR           /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */
+
+/* SQPI PSRAM */
+/* SPI PSRAM ID length */
+#define SINIT_IDL(regval)                 (BITS(29,30) & ((uint32_t)(regval) << 29))
+#define EXMC_SQPIPSRAM_ID_LENGTH_64B      SINIT_IDL(0)                  /*!< SPI PSRAM ID length is 64 bits */
+#define EXMC_SQPIPSRAM_ID_LENGTH_32B      SINIT_IDL(1)                  /*!< SPI PSRAM ID length is 32 bits */
+#define EXMC_SQPIPSRAM_ID_LENGTH_16B      SINIT_IDL(2)                  /*!< SPI PSRAM ID length is 16 bits */
+#define EXMC_SQPIPSRAM_ID_LENGTH_8B       SINIT_IDL(3)                  /*!< SPI PSRAM ID length is 8 bits */
+
+/* SPI PSRAM bit number of address phase */
+#define SINIT_ADRBIT(regval)              (BITS(24,28) & ((uint32_t)(regval) << 24))
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B     SINIT_ADRBIT(1)               /*!< SPI PSRAM address is 1 bit */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B     SINIT_ADRBIT(2)               /*!< SPI PSRAM address is 2 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B     SINIT_ADRBIT(3)               /*!< SPI PSRAM address is 3 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B     SINIT_ADRBIT(4)               /*!< SPI PSRAM address is 4 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B     SINIT_ADRBIT(5)               /*!< SPI PSRAM address is 5 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B     SINIT_ADRBIT(6)               /*!< SPI PSRAM address is 6 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B     SINIT_ADRBIT(7)               /*!< SPI PSRAM address is 7 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B     SINIT_ADRBIT(8)               /*!< SPI PSRAM address is 8 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B     SINIT_ADRBIT(9)               /*!< SPI PSRAM address is 9 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B    SINIT_ADRBIT(10)              /*!< SPI PSRAM address is 10 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B    SINIT_ADRBIT(11)              /*!< SPI PSRAM address is 11 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B    SINIT_ADRBIT(12)              /*!< SPI PSRAM address is 12 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B    SINIT_ADRBIT(13)              /*!< SPI PSRAM address is 13 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B    SINIT_ADRBIT(14)              /*!< SPI PSRAM address is 14 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B    SINIT_ADRBIT(15)              /*!< SPI PSRAM address is 15 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B    SINIT_ADRBIT(16)              /*!< SPI PSRAM address is 16 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B    SINIT_ADRBIT(17)              /*!< SPI PSRAM address is 17 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B    SINIT_ADRBIT(18)              /*!< SPI PSRAM address is 18 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B    SINIT_ADRBIT(19)              /*!< SPI PSRAM address is 19 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B    SINIT_ADRBIT(20)              /*!< SPI PSRAM address is 20 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B    SINIT_ADRBIT(21)              /*!< SPI PSRAM address is 21 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B    SINIT_ADRBIT(22)              /*!< SPI PSRAM address is 22 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B    SINIT_ADRBIT(23)              /*!< SPI PSRAM address is 23 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B    SINIT_ADRBIT(24)              /*!< SPI PSRAM address is 24 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B    SINIT_ADRBIT(25)              /*!< SPI PSRAM address is 25 bits */
+#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B    SINIT_ADRBIT(26)              /*!< SPI PSRAM address is 26 bits */
+
+/* SPI PSRAM bit number of command phase */
+#define SINIT_CMDBIT(regval)              (BITS(16,17) & ((uint32_t)(regval) << 16))
+#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B  SINIT_CMDBIT(0)               /*!< SPI PSRAM command is 4 bits */
+#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B  SINIT_CMDBIT(1)               /*!< SPI PSRAM command is 8 bits */
+#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2)               /*!< SPI PSRAM command is 16 bits */
+
+/* SPI PSRAM read command mode */
+#define SRCMD_RMODE(regval)               (BITS(20,21) & ((uint32_t)(regval) << 20))
+#define EXMC_SQPIPSRAM_READ_MODE_DISABLE  SRCMD_RMODE(0)                /*!< not SPI mode */
+#define EXMC_SQPIPSRAM_READ_MODE_SPI      SRCMD_RMODE(1)                /*!< SPI mode */
+#define EXMC_SQPIPSRAM_READ_MODE_SQPI     SRCMD_RMODE(2)                /*!< SQPI mode */
+#define EXMC_SQPIPSRAM_READ_MODE_QPI      SRCMD_RMODE(3)                /*!< QPI mode */
+
+/* SPI PSRAM write command mode */
+#define SRCMD_WMODE(regval)               (BITS(20,21) & ((uint32_t)(regval) << 20))
+#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0)                /*!< not SPI mode */
+#define EXMC_SQPIPSRAM_WRITE_MODE_SPI     SRCMD_WMODE(1)                /*!< SPI mode */
+#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI    SRCMD_WMODE(2)                /*!< SQPI mode */
+#define EXMC_SQPIPSRAM_WRITE_MODE_QPI     SRCMD_WMODE(3)                /*!< QPI mode */
+
+/* read data sample polarity */
+#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE   ((uint32_t)0x00000000U)     /*!< sample data at rising edge */
+#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE  EXMC_SINIT_POL              /*!< sample data at falling edge */
+
+/* SQPI SRAM command flag */
+#define EXMC_SEND_COMMAND_FLAG_RDID       EXMC_SRCMD_RDID               /*!< EXMC_SRCMD_RDID flag bit */
+#define EXMC_SEND_COMMAND_FLAG_SC         EXMC_SWCMD_SC                 /*!< EXMC_SWCMD_SC flag bit */
+
+/* EXMC flag bits */
+#define EXMC_NAND_PCCARD_FLAG_RISE        EXMC_NPINTEN_INTRS            /*!< interrupt rising edge status */
+#define EXMC_NAND_PCCARD_FLAG_LEVEL       EXMC_NPINTEN_INTHS            /*!< interrupt high-level status */
+#define EXMC_NAND_PCCARD_FLAG_FALL        EXMC_NPINTEN_INTFS            /*!< interrupt falling edge status */
+#define EXMC_NAND_PCCARD_FLAG_FIFOE       EXMC_NPINTEN_FFEPT            /*!< FIFO empty flag */
+#define EXMC_SDRAM_FLAG_REFRESH           EXMC_SDSDAT_REIF              /*!< refresh error interrupt flag */
+#define EXMC_SDRAM_FLAG_NREADY            EXMC_SDSDAT_NRDY              /*!< not ready status  */
+
+/* EXMC interrupt enable bits */
+#define EXMC_NAND_PCCARD_INT_RISE         EXMC_NPINTEN_INTREN           /*!< interrupt rising edge detection enable */
+#define EXMC_NAND_PCCARD_INT_LEVEL        EXMC_NPINTEN_INTHEN           /*!< interrupt high-level detection enable */
+#define EXMC_NAND_PCCARD_INT_FALL         EXMC_NPINTEN_INTFEN           /*!< interrupt falling edge detection enable */
+#define EXMC_SDRAM_INT_REFRESH            EXMC_SDARI_REIE               /*!< interrupt refresh error enable */
+
+/* EXMC interrupt flag bits */
+#define EXMC_NAND_PCCARD_INT_FLAG_RISE    EXMC_NPINTEN_INTREN           /*!< interrupt rising edge detection enable */
+#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL   EXMC_NPINTEN_INTHEN           /*!< interrupt high-level detection enable */
+#define EXMC_NAND_PCCARD_INT_FLAG_FALL    EXMC_NPINTEN_INTFEN           /*!< interrupt falling edge detection enable */
+#define EXMC_SDRAM_INT_FLAG_REFRESH       EXMC_SDARI_REIE               /*!< interrupt refresh error enable */
+
+/* function declarations */
+/* function configuration */
+/* deinitialize EXMC NOR/SRAM region */
+void exmc_norsram_deinit(uint32_t exmc_norsram_region);
+/* exmc_norsram_parameter_struct parameter initialize */
+void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
+/* initialize EXMC NOR/SRAM region */
+void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
+/* EXMC NOR/SRAM bank enable */
+void exmc_norsram_enable(uint32_t exmc_norsram_region);
+/* EXMC NOR/SRAM bank disable */
+void exmc_norsram_disable(uint32_t exmc_norsram_region);
+
+/* deinitialize EXMC NAND bank */
+void exmc_nand_deinit(uint32_t exmc_nand_bank);
+/* initialize EXMC NAND bank */
+void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
+/* exmc_nand_init_struct parameter initialize */
+void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
+/* EXMC NAND bank enable */
+void exmc_nand_enable(uint32_t exmc_nand_bank);
+/* EXMC NAND bank disable */
+void exmc_nand_disable(uint32_t exmc_nand_bank);
+/* enable or disable the EXMC NAND ECC function */
+void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue);
+/* get the EXMC ECC value */
+uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
+
+/* deinitialize EXMC PC card bank */
+void exmc_pccard_deinit(void);
+/* initialize EXMC PC card bank */
+void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
+/* exmc_pccard_parameter_struct parameter initialize */
+void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
+/* EXMC PC card bank enable */
+void exmc_pccard_enable(void);
+/* EXMC PC card bank disable */
+void exmc_pccard_disable(void);
+
+/* deinitialize EXMC SDRAM device */
+void exmc_sdram_deinit(uint32_t exmc_sdram_device);
+/* initialize EXMC SDRAM device */
+void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
+/* exmc_sdram_parameter_struct parameter initialize */
+void exmc_sdram_parameter_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
+/* configure the SDRAM memory command */
+void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct);
+/* set auto-refresh interval */
+void exmc_sdram_refresh_count_set(uint32_t exmc_count);
+/* set the number of successive auto-refresh command */
+void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
+/* config the write protection function */
+void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
+/* get the status of SDRAM device0 or device1 */
+uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
+/* configure the delayed sample clock of read data */
+void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk);
+/* enable read sample */
+void exmc_sdram_readsample_enable(void);
+/* disable read sample */
+void exmc_sdram_readsample_disable(void);
+
+/* deinitialize EXMC SQPIPSRAM */
+void exmc_sqpipsram_deinit(void);
+/* initialize EXMC SQPIPSRAM */
+void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
+/* exmc_sqpipsram_parameter_struct parameter initialize */
+void exmc_sqpipsram_parameter_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
+/* set the read command */
+void exmc_sqpipsram_read_command_set(uint32_t read_command_mode, uint32_t read_wait_cycle, uint32_t read_command_code);
+/* set the write command */
+void exmc_sqpipsram_write_command_set(uint32_t write_command_mode, uint32_t write_wait_cycle, uint32_t write_command_code);
+/* send SPI read ID command */
+void exmc_sqpipsram_read_id_command_send(void);
+/* send SPI special command which does not have address and data phase */
+void exmc_sqpipsram_write_cmd_send(void);
+/* get the EXMC SPI ID low data */
+uint32_t exmc_sqpipsram_low_id_get(void);
+/* get the EXMC SPI ID high data */
+uint32_t exmc_sqpipsram_high_id_get(void);
+/* get the bit value of EXMC send write command bit or read ID command */
+FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag);
+
+/* interrupt & flag functions */
+/* check EXMC flag is set or not */
+FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag);
+/* clear EXMC flag */
+void exmc_flag_clear(uint32_t bank, uint32_t flag);
+/* check EXMC flag is set or not */
+FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source);
+/* clear EXMC flag */
+void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source);
+/* enable EXMC interrupt */
+void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source);
+/* disable EXMC interrupt */
+void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source);
+
+#endif /* GD32F20X_EXMC_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_exti.h

@@ -0,0 +1,259 @@
+/*!
+    \file  gd32f20x_exti.h
+    \brief definitions for the EXTI
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_EXTI_H
+#define GD32F20X_EXTI_H
+
+#include "gd32f20x.h"
+
+/* EXTI definitions */
+#define EXTI                         EXTI_BASE
+
+/* registers definitions */
+#define EXTI_INTEN                   REG32(EXTI + 0x00U)      /*!< interrupt enable register */
+#define EXTI_EVEN                    REG32(EXTI + 0x04U)      /*!< event enable register */
+#define EXTI_RTEN                    REG32(EXTI + 0x08U)      /*!< rising edge trigger enable register */
+#define EXTI_FTEN                    REG32(EXTI + 0x0CU)      /*!< falling trigger enable register */
+#define EXTI_SWIEV                   REG32(EXTI + 0x10U)      /*!< software interrupt event register */
+#define EXTI_PD                      REG32(EXTI + 0x14U)      /*!< pending register */
+
+/* bits definitions */
+/* EXTI_INTEN */
+#define EXTI_INTEN_INTEN0            BIT(0)                   /*!< interrupt from line 0 */
+#define EXTI_INTEN_INTEN1            BIT(1)                   /*!< interrupt from line 1 */
+#define EXTI_INTEN_INTEN2            BIT(2)                   /*!< interrupt from line 2 */
+#define EXTI_INTEN_INTEN3            BIT(3)                   /*!< interrupt from line 3 */
+#define EXTI_INTEN_INTEN4            BIT(4)                   /*!< interrupt from line 4 */
+#define EXTI_INTEN_INTEN5            BIT(5)                   /*!< interrupt from line 5 */
+#define EXTI_INTEN_INTEN6            BIT(6)                   /*!< interrupt from line 6 */
+#define EXTI_INTEN_INTEN7            BIT(7)                   /*!< interrupt from line 7 */
+#define EXTI_INTEN_INTEN8            BIT(8)                   /*!< interrupt from line 8 */
+#define EXTI_INTEN_INTEN9            BIT(9)                   /*!< interrupt from line 9 */
+#define EXTI_INTEN_INTEN10           BIT(10)                  /*!< interrupt from line 10 */
+#define EXTI_INTEN_INTEN11           BIT(11)                  /*!< interrupt from line 11 */
+#define EXTI_INTEN_INTEN12           BIT(12)                  /*!< interrupt from line 12 */
+#define EXTI_INTEN_INTEN13           BIT(13)                  /*!< interrupt from line 13 */
+#define EXTI_INTEN_INTEN14           BIT(14)                  /*!< interrupt from line 14 */
+#define EXTI_INTEN_INTEN15           BIT(15)                  /*!< interrupt from line 15 */
+#define EXTI_INTEN_INTEN16           BIT(16)                  /*!< interrupt from line 16 */
+#define EXTI_INTEN_INTEN17           BIT(17)                  /*!< interrupt from line 17 */
+#define EXTI_INTEN_INTEN18           BIT(18)                  /*!< interrupt from line 18 */
+#define EXTI_INTEN_INTEN19           BIT(19)                  /*!< interrupt from line 19 */
+
+/* EXTI_EVEN */
+#define EXTI_EVEN_EVEN0              BIT(0)                   /*!< event from line 0 */
+#define EXTI_EVEN_EVEN1              BIT(1)                   /*!< event from line 1 */
+#define EXTI_EVEN_EVEN2              BIT(2)                   /*!< event from line 2 */
+#define EXTI_EVEN_EVEN3              BIT(3)                   /*!< event from line 3 */
+#define EXTI_EVEN_EVEN4              BIT(4)                   /*!< event from line 4 */
+#define EXTI_EVEN_EVEN5              BIT(5)                   /*!< event from line 5 */
+#define EXTI_EVEN_EVEN6              BIT(6)                   /*!< event from line 6 */
+#define EXTI_EVEN_EVEN7              BIT(7)                   /*!< event from line 7 */
+#define EXTI_EVEN_EVEN8              BIT(8)                   /*!< event from line 8 */
+#define EXTI_EVEN_EVEN9              BIT(9)                   /*!< event from line 9 */
+#define EXTI_EVEN_EVEN10             BIT(10)                  /*!< event from line 10 */
+#define EXTI_EVEN_EVEN11             BIT(11)                  /*!< event from line 11 */
+#define EXTI_EVEN_EVEN12             BIT(12)                  /*!< event from line 12 */
+#define EXTI_EVEN_EVEN13             BIT(13)                  /*!< event from line 13 */
+#define EXTI_EVEN_EVEN14             BIT(14)                  /*!< event from line 14 */
+#define EXTI_EVEN_EVEN15             BIT(15)                  /*!< event from line 15 */
+#define EXTI_EVEN_EVEN16             BIT(16)                  /*!< event from line 16 */
+#define EXTI_EVEN_EVEN17             BIT(17)                  /*!< event from line 17 */
+#define EXTI_EVEN_EVEN18             BIT(18)                  /*!< event from line 18 */
+#define EXTI_EVEN_EVEN19             BIT(19)                  /*!< event from line 19 */
+
+/* EXTI_RTEN */
+#define EXTI_RTEN_RTEN0              BIT(0)                   /*!< rising edge from line 0 */
+#define EXTI_RTEN_RTEN1              BIT(1)                   /*!< rising edge from line 1 */
+#define EXTI_RTEN_RTEN2              BIT(2)                   /*!< rising edge from line 2 */
+#define EXTI_RTEN_RTEN3              BIT(3)                   /*!< rising edge from line 3 */
+#define EXTI_RTEN_RTEN4              BIT(4)                   /*!< rising edge from line 4 */
+#define EXTI_RTEN_RTEN5              BIT(5)                   /*!< rising edge from line 5 */
+#define EXTI_RTEN_RTEN6              BIT(6)                   /*!< rising edge from line 6 */
+#define EXTI_RTEN_RTEN7              BIT(7)                   /*!< rising edge from line 7 */
+#define EXTI_RTEN_RTEN8              BIT(8)                   /*!< rising edge from line 8 */
+#define EXTI_RTEN_RTEN9              BIT(9)                   /*!< rising edge from line 9 */
+#define EXTI_RTEN_RTEN10             BIT(10)                  /*!< rising edge from line 10 */
+#define EXTI_RTEN_RTEN11             BIT(11)                  /*!< rising edge from line 11 */
+#define EXTI_RTEN_RTEN12             BIT(12)                  /*!< rising edge from line 12 */
+#define EXTI_RTEN_RTEN13             BIT(13)                  /*!< rising edge from line 13 */
+#define EXTI_RTEN_RTEN14             BIT(14)                  /*!< rising edge from line 14 */
+#define EXTI_RTEN_RTEN15             BIT(15)                  /*!< rising edge from line 15 */
+#define EXTI_RTEN_RTEN16             BIT(16)                  /*!< rising edge from line 16 */
+#define EXTI_RTEN_RTEN17             BIT(17)                  /*!< rising edge from line 17 */
+#define EXTI_RTEN_RTEN18             BIT(18)                  /*!< rising edge from line 18 */
+#define EXTI_RTEN_RTEN19             BIT(19)                  /*!< rising edge from line 19 */
+
+/* EXTI_FTEN */
+#define EXTI_FTEN_FTEN0              BIT(0)                   /*!< falling edge from line 0 */
+#define EXTI_FTEN_FTEN1              BIT(1)                   /*!< falling edge from line 1 */
+#define EXTI_FTEN_FTEN2              BIT(2)                   /*!< falling edge from line 2 */
+#define EXTI_FTEN_FTEN3              BIT(3)                   /*!< falling edge from line 3 */
+#define EXTI_FTEN_FTEN4              BIT(4)                   /*!< falling edge from line 4 */
+#define EXTI_FTEN_FTEN5              BIT(5)                   /*!< falling edge from line 5 */
+#define EXTI_FTEN_FTEN6              BIT(6)                   /*!< falling edge from line 6 */
+#define EXTI_FTEN_FTEN7              BIT(7)                   /*!< falling edge from line 7 */
+#define EXTI_FTEN_FTEN8              BIT(8)                   /*!< falling edge from line 8 */
+#define EXTI_FTEN_FTEN9              BIT(9)                   /*!< falling edge from line 9 */
+#define EXTI_FTEN_FTEN10             BIT(10)                  /*!< falling edge from line 10 */
+#define EXTI_FTEN_FTEN11             BIT(11)                  /*!< falling edge from line 11 */
+#define EXTI_FTEN_FTEN12             BIT(12)                  /*!< falling edge from line 12 */
+#define EXTI_FTEN_FTEN13             BIT(13)                  /*!< falling edge from line 13 */
+#define EXTI_FTEN_FTEN14             BIT(14)                  /*!< falling edge from line 14 */
+#define EXTI_FTEN_FTEN15             BIT(15)                  /*!< falling edge from line 15 */
+#define EXTI_FTEN_FTEN16             BIT(16)                  /*!< falling edge from line 16 */
+#define EXTI_FTEN_FTEN17             BIT(17)                  /*!< falling edge from line 17 */
+#define EXTI_FTEN_FTEN18             BIT(18)                  /*!< falling edge from line 18 */
+#define EXTI_FTEN_FTEN19             BIT(19)                  /*!< falling edge from line 19 */
+
+/* EXTI_SWIEV */
+#define EXTI_SWIEV_SWIEV0            BIT(0)                   /*!< software interrupt/event request from line 0 */
+#define EXTI_SWIEV_SWIEV1            BIT(1)                   /*!< software interrupt/event request from line 1 */
+#define EXTI_SWIEV_SWIEV2            BIT(2)                   /*!< software interrupt/event request from line 2 */
+#define EXTI_SWIEV_SWIEV3            BIT(3)                   /*!< software interrupt/event request from line 3 */
+#define EXTI_SWIEV_SWIEV4            BIT(4)                   /*!< software interrupt/event request from line 4 */
+#define EXTI_SWIEV_SWIEV5            BIT(5)                   /*!< software interrupt/event request from line 5 */
+#define EXTI_SWIEV_SWIEV6            BIT(6)                   /*!< software interrupt/event request from line 6 */
+#define EXTI_SWIEV_SWIEV7            BIT(7)                   /*!< software interrupt/event request from line 7 */
+#define EXTI_SWIEV_SWIEV8            BIT(8)                   /*!< software interrupt/event request from line 8 */
+#define EXTI_SWIEV_SWIEV9            BIT(9)                   /*!< software interrupt/event request from line 9 */
+#define EXTI_SWIEV_SWIEV10           BIT(10)                  /*!< software interrupt/event request from line 10 */
+#define EXTI_SWIEV_SWIEV11           BIT(11)                  /*!< software interrupt/event request from line 11 */
+#define EXTI_SWIEV_SWIEV12           BIT(12)                  /*!< software interrupt/event request from line 12 */
+#define EXTI_SWIEV_SWIEV13           BIT(13)                  /*!< software interrupt/event request from line 13 */
+#define EXTI_SWIEV_SWIEV14           BIT(14)                  /*!< software interrupt/event request from line 14 */
+#define EXTI_SWIEV_SWIEV15           BIT(15)                  /*!< software interrupt/event request from line 15 */
+#define EXTI_SWIEV_SWIEV16           BIT(16)                  /*!< software interrupt/event request from line 16 */
+#define EXTI_SWIEV_SWIEV17           BIT(17)                  /*!< software interrupt/event request from line 17 */
+#define EXTI_SWIEV_SWIEV18           BIT(18)                  /*!< software interrupt/event request from line 18 */
+#define EXTI_SWIEV_SWIEV19           BIT(19)                  /*!< software interrupt/event request from line 19 */
+
+/* EXTI_PD */
+#define EXTI_PD_PD0                  BIT(0)                   /*!< interrupt/event pending status from line 0 */
+#define EXTI_PD_PD1                  BIT(1)                   /*!< interrupt/event pending status from line 1 */
+#define EXTI_PD_PD2                  BIT(2)                   /*!< interrupt/event pending status from line 2 */
+#define EXTI_PD_PD3                  BIT(3)                   /*!< interrupt/event pending status from line 3 */
+#define EXTI_PD_PD4                  BIT(4)                   /*!< interrupt/event pending status from line 4 */
+#define EXTI_PD_PD5                  BIT(5)                   /*!< interrupt/event pending status from line 5 */
+#define EXTI_PD_PD6                  BIT(6)                   /*!< interrupt/event pending status from line 6 */
+#define EXTI_PD_PD7                  BIT(7)                   /*!< interrupt/event pending status from line 7 */
+#define EXTI_PD_PD8                  BIT(8)                   /*!< interrupt/event pending status from line 8 */
+#define EXTI_PD_PD9                  BIT(9)                   /*!< interrupt/event pending status from line 9 */
+#define EXTI_PD_PD10                 BIT(10)                  /*!< interrupt/event pending status from line 10 */
+#define EXTI_PD_PD11                 BIT(11)                  /*!< interrupt/event pending status from line 11 */
+#define EXTI_PD_PD12                 BIT(12)                  /*!< interrupt/event pending status from line 12 */
+#define EXTI_PD_PD13                 BIT(13)                  /*!< interrupt/event pending status from line 13 */
+#define EXTI_PD_PD14                 BIT(14)                  /*!< interrupt/event pending status from line 14 */
+#define EXTI_PD_PD15                 BIT(15)                  /*!< interrupt/event pending status from line 15 */
+#define EXTI_PD_PD16                 BIT(16)                  /*!< interrupt/event pending status from line 16 */
+#define EXTI_PD_PD17                 BIT(17)                  /*!< interrupt/event pending status from line 17 */
+#define EXTI_PD_PD18                 BIT(18)                  /*!< interrupt/event pending status from line 18 */
+#define EXTI_PD_PD19                 BIT(19)                  /*!< interrupt/event pending status from line 19 */
+
+/* constants definitions */
+/* EXTI line number */
+typedef enum
+{ 
+    EXTI_0      = BIT(0),                                     /*!< EXTI line 0 */
+    EXTI_1      = BIT(1),                                     /*!< EXTI line 1 */
+    EXTI_2      = BIT(2),                                     /*!< EXTI line 2 */
+    EXTI_3      = BIT(3),                                     /*!< EXTI line 3 */
+    EXTI_4      = BIT(4),                                     /*!< EXTI line 4 */
+    EXTI_5      = BIT(5),                                     /*!< EXTI line 5 */
+    EXTI_6      = BIT(6),                                     /*!< EXTI line 6 */
+    EXTI_7      = BIT(7),                                     /*!< EXTI line 7 */
+    EXTI_8      = BIT(8),                                     /*!< EXTI line 8 */
+    EXTI_9      = BIT(9),                                     /*!< EXTI line 9 */
+    EXTI_10     = BIT(10),                                    /*!< EXTI line 10 */
+    EXTI_11     = BIT(11),                                    /*!< EXTI line 11 */
+    EXTI_12     = BIT(12),                                    /*!< EXTI line 12 */
+    EXTI_13     = BIT(13),                                    /*!< EXTI line 13 */
+    EXTI_14     = BIT(14),                                    /*!< EXTI line 14 */
+    EXTI_15     = BIT(15),                                    /*!< EXTI line 15 */
+    EXTI_16     = BIT(16),                                    /*!< EXTI line 16 */
+    EXTI_17     = BIT(17),                                    /*!< EXTI line 17 */
+    EXTI_18     = BIT(18),                                    /*!< EXTI line 18 */
+    EXTI_19     = BIT(19),                                    /*!< EXTI line 19 */
+}exti_line_enum;
+
+/* external interrupt and event  */
+typedef enum
+{
+    EXTI_INTERRUPT   = 0,                                     /*!< EXTI interrupt mode */
+    EXTI_EVENT                                                /*!< EXTI event mode */
+}exti_mode_enum;
+
+/* interrupt trigger mode */
+typedef enum
+{ 
+    EXTI_TRIG_RISING = 0,                                     /*!< EXTI rising edge trigger */
+    EXTI_TRIG_FALLING,                                        /*!< EXTI falling edge trigger */
+    EXTI_TRIG_BOTH                                            /*!< EXTI rising and falling edge trigger */
+}exti_trig_type_enum;
+
+/* function declarations */
+/* initialization, EXTI lines configuration functions */
+/* deinitialize the EXTI */
+void exti_deinit(void);
+/* enable the configuration of EXTI initialize */
+void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
+/* enable the interrupts from EXTI line x */
+void exti_interrupt_enable(exti_line_enum linex);
+/* enable the events from EXTI line x */
+void exti_event_enable(exti_line_enum linex);
+/* disable the interrupts from EXTI line x */
+void exti_interrupt_disable(exti_line_enum linex);
+/* disable the events from EXTI line x */
+void exti_event_disable(exti_line_enum linex);
+
+/* interrupt & flag functions */
+/* get EXTI lines pending flag */
+FlagStatus exti_flag_get(exti_line_enum linex);
+/* clear EXTI lines pending flag */
+void exti_flag_clear(exti_line_enum linex);
+/* get EXTI lines flag when the interrupt flag is set */
+FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
+/* clear EXTI lines pending flag */
+void exti_interrupt_flag_clear(exti_line_enum linex);
+/* enable the EXTI software interrupt event  */
+void exti_software_interrupt_enable(exti_line_enum linex);
+/* disable the EXTI software interrupt event  */
+void exti_software_interrupt_disable(exti_line_enum linex);
+
+#endif /* GD32F20X_EXTI_H */
+

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_fmc.h

@@ -0,0 +1,370 @@
+/*!
+    \file  gd32f20x_fmc.h
+    \brief definitions for the FMC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_FMC_H
+#define GD32F20X_FMC_H
+
+#include "gd32f20x.h"
+
+/* FMC and option byte definition */
+#define FMC                        FMC_BASE                       /*!< FMC register base address */
+#define OB                         OB_BASE                        /*!< option bytes base address */
+
+/* registers definitions */
+#define FMC_WS                     REG32((FMC) + 0x00U)           /*!< FMC wait state register */
+#define FMC_KEY0                   REG32((FMC) + 0x04U)           /*!< FMC unlock key register 0 */
+#define FMC_OBKEY                  REG32((FMC) + 0x08U)           /*!< FMC option bytes unlock key register */
+#define FMC_STAT0                  REG32((FMC) + 0x0CU)           /*!< FMC status register 0 */
+#define FMC_CTL0                   REG32((FMC) + 0x10U)           /*!< FMC control register 0 */
+#define FMC_ADDR0                  REG32((FMC) + 0x14U)           /*!< FMC address register 0 */
+#define FMC_OBSTAT                 REG32((FMC) + 0x1CU)           /*!< FMC option bytes status register */
+#define FMC_WP                     REG32((FMC) + 0x20U)           /*!< FMC erase/program protection register */
+#define FMC_KEY1                   REG32((FMC) + 0x44U)           /*!< FMC unlock key register 1 */
+#define FMC_STAT1                  REG32((FMC) + 0x4CU)           /*!< FMC status register 1 */
+#define FMC_CTL1                   REG32((FMC) + 0x50U)           /*!< FMC control register 1 */
+#define FMC_ADDR1                  REG32((FMC) + 0x54U)           /*!< FMC address register 1 */
+#define FMC_WSEN                   REG32((FMC) + 0xFCU)           /*!< FMC wait state enable register */
+#define FMC_PID                    REG32((FMC) + 0x100U)          /*!< FMC product ID register */
+
+#define OB_SPC                     REG16((OB) + 0x00U)            /*!< option byte security protection value */
+#define OB_USER                    REG16((OB) + 0x02U)            /*!< option byte user value*/
+#define OB_WP0                     REG16((OB) + 0x08U)            /*!< option byte write protection 0 */
+#define OB_WP1                     REG16((OB) + 0x0AU)            /*!< option byte write protection 1 */
+#define OB_WP2                     REG16((OB) + 0x0CU)            /*!< option byte write protection 2 */
+#define OB_WP3                     REG16((OB) + 0x0EU)            /*!< option byte write protection 3 */
+
+/* bits definitions */
+/* FMC_WS */
+#define FMC_WS_WSCNT               BITS(0,2)                      /*!< wait state counter */
+
+/* FMC_KEY0 */
+#define FMC_KEY0_KEY               BITS(0,31)                     /*!< FMC_CTL0 unlock key bits */
+
+/* FMC_OBKEY */
+#define FMC_OBKEY_OBKEY            BITS(0,31)                     /*!< option bytes unlock key bits */
+
+/* FMC_STAT0 */
+#define FMC_STAT0_BUSY             BIT(0)                         /*!< flash busy flag bit */
+#define FMC_STAT0_PGERR            BIT(2)                         /*!< flash program error flag bit */
+#define FMC_STAT0_WPERR            BIT(4)                         /*!< erase/program protection error flag bit */
+#define FMC_STAT0_ENDF             BIT(5)                         /*!< end of operation flag bit */
+
+/* FMC_CTL0 */
+#define FMC_CTL0_PG                BIT(0)                         /*!< main flash program for bank0 command bit */
+#define FMC_CTL0_PER               BIT(1)                         /*!< main flash page erase for bank0 command bit */
+#define FMC_CTL0_MER               BIT(2)                         /*!< main flash mass erase for bank0 command bit */
+#define FMC_CTL0_OBPG              BIT(4)                         /*!< option bytes program command bit */
+#define FMC_CTL0_OBER              BIT(5)                         /*!< option bytes erase command bit */
+#define FMC_CTL0_START             BIT(6)                         /*!< send erase command to FMC bit */
+#define FMC_CTL0_LK                BIT(7)                         /*!< FMC_CTL0 lock bit */
+#define FMC_CTL0_OBWEN             BIT(9)                         /*!< option bytes erase/program enable bit */
+#define FMC_CTL0_ERRIE             BIT(10)                        /*!< error interrupt enable bit */
+#define FMC_CTL0_ENDIE             BIT(12)                        /*!< end of operation interrupt enable bit */
+
+/* FMC_ADDR0 */
+#define FMC_ADDR0_ADDR             BITS(0,31)                     /*!< Flash erase/program command address bits */
+
+/* FMC_OBSTAT */
+#define FMC_OBSTAT_OBERR           BIT(0)                         /*!< option bytes read error bit. */
+#define FMC_OBSTAT_SPC             BIT(1)                         /*!< option bytes security protection code */
+#define FMC_OBSTAT_USER            BITS(2,9)                      /*!< store USER of option bytes block after system reset */
+#define FMC_OBSTAT_DATA            BITS(10,25)                    /*!< store DATA of option bytes block after system reset. */
+
+/* FMC_WP */
+#define FMC_WP_WP                  BITS(0,31)                     /*!< store WP of option bytes block after system reset */
+
+/* FMC_KEY1 */
+#define FMC_KEY1_KEY               BITS(0,31)                     /*!< FMC_CTL1 unlock key bits */
+
+/* FMC_STAT1 */
+#define FMC_STAT1_BUSY             BIT(0)                         /*!< flash busy flag bit */
+#define FMC_STAT1_PGERR            BIT(2)                         /*!< flash program error flag bit */
+#define FMC_STAT1_WPERR            BIT(4)                         /*!< erase/program protection error flag bit */
+#define FMC_STAT1_ENDF             BIT(5)                         /*!< end of operation flag bit */
+
+/* FMC_CTL1 */
+#define FMC_CTL1_PG                BIT(0)                         /*!< main flash program for bank1 command bit */
+#define FMC_CTL1_PER               BIT(1)                         /*!< main flash page erase for bank1 command bit */
+#define FMC_CTL1_MER               BIT(2)                         /*!< main flash mass erase for bank1 command bit */
+#define FMC_CTL1_START             BIT(6)                         /*!< send erase command to FMC bit */
+#define FMC_CTL1_LK                BIT(7)                         /*!< FMC_CTL1 lock bit */
+#define FMC_CTL1_ERRIE             BIT(10)                        /*!< error interrupt enable bit */
+#define FMC_CTL1_ENDIE             BIT(12)                        /*!< end of operation interrupt enable bit */
+
+/* FMC_ADDR1 */
+#define FMC_ADDR1_ADDR             BITS(0,31)                     /*!< Flash erase/program command address bits */
+
+/* FMC_WSEN */
+#define FMC_WSEN_WSEN              BIT(0)                         /*!< FMC wait state enable bit */
+
+/* FMC_PID */
+#define FMC_PID_PID                BITS(0,31)                     /*!< product ID bits */
+
+/* constants definitions */
+/* define the FMC bit position and its register index offset */
+#define FMC_REGIDX_BIT(regidx, bitpos)              (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define FMC_REG_VAL(offset)                         (REG32(FMC + ((uint32_t)(offset) >> 6)))
+#define FMC_BIT_POS(val)                            ((uint32_t)(val) & 0x1FU)
+#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1)   (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
+#define FMC_REG_VALS(offset)                        (REG32(FMC + ((uint32_t)(offset) >> 12)))
+#define FMC_BIT_POS0(val)                           (((uint32_t)(val) >> 6) & 0x1FU)
+#define FMC_BIT_POS1(val)                           ((uint32_t)(val) & 0x1FU)
+#define FMC_REG_OFFSET_GET(flag)                    ((uint32_t)(flag) >> 12)
+
+/* configuration register */
+#define FMC_STAT0_REG_OFFSET             0x0CU                    /*!< status register 0 offset */
+#define FMC_CTL0_REG_OFFSET              0x10U                    /*!< control register 0 offset */
+#define FMC_STAT1_REG_OFFSET             0x4CU                    /*!< status register 1 offset */
+#define FMC_CTL1_REG_OFFSET              0x50U                    /*!< control register 1 offset */
+#define FMC_OBSTAT_REG_OFFSET            0x1CU                    /*!< option byte status register offset */
+
+/* fmc state */
+typedef enum
+{
+    FMC_READY,                                                    /*!< the operation has been completed */
+    FMC_BUSY,                                                     /*!< the operation is in progress */
+    FMC_PGERR,                                                    /*!< program error */
+    FMC_WPERR,                                                    /*!< erase/program protection error */
+    FMC_TOERR,                                                    /*!< timeout error */
+}fmc_state_enum;
+
+/* FMC interrupt enable */
+typedef enum
+{
+    FMC_INT_BANK0_END     = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U),            /*!< enable FMC end of program interrupt */
+    FMC_INT_BANK0_ERR     = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U),            /*!< enable FMC error interrupt */
+    FMC_INT_BANK1_END     = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U),            /*!< enable FMC bank1 end of program interrupt */
+    FMC_INT_BANK1_ERR     = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U),            /*!< enable FMC bank1 error interrupt */
+}fmc_int_enum;
+
+/* FMC flags */
+typedef enum
+{
+    FMC_FLAG_BANK0_BUSY   = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U),            /*!< FMC bank0 busy flag */
+    FMC_FLAG_BANK0_PGERR  = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U),            /*!< FMC bank0 operation error flag bit */
+    FMC_FLAG_BANK0_WPERR  = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U),            /*!< FMC bank0 erase/program protection error flag bit */
+    FMC_FLAG_BANK0_END    = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U),            /*!< FMC bank0 end of operation flag bit */
+    FMC_FLAG_OBERR        = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U),           /*!< FMC option bytes read error flag */
+    FMC_FLAG_BANK1_BUSY   = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U),            /*!< FMC bank1 busy flag */
+    FMC_FLAG_BANK1_PGERR  = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U),            /*!< FMC bank1 operation error flag bit */
+    FMC_FLAG_BANK1_WPERR  = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U),            /*!< FMC bank1 erase/program protection error flag bit */
+    FMC_FLAG_BANK1_END    = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U),            /*!< FMC bank1 end of operation flag bit */
+}fmc_flag_enum;
+
+/* FMC interrupt flags */
+typedef enum
+{
+    FMC_INT_FLAG_BANK0_PGERR  = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U),  /*!< FMC bank0 operation error interrupt flag bit */
+    FMC_INT_FLAG_BANK0_WPERR  = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U),  /*!< FMC bank0 erase/program protection error interrupt flag bit */
+    FMC_INT_FLAG_BANK0_END    = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U),  /*!< FMC bank0 end of operation interrupt flag bit */
+    FMC_INT_FLAG_BANK1_PGERR  = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U),  /*!< FMC bank1 operation error interrupt flag bit */
+    FMC_INT_FLAG_BANK1_WPERR  = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U),  /*!< FMC bank1 erase/program protection error interrupt flag bit */
+    FMC_INT_FLAG_BANK1_END    = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U),  /*!< FMC bank1 end of operation interrupt flag bit */
+}fmc_interrupt_flag_enum;
+
+/* unlock key */
+#define UNLOCK_KEY0                ((uint32_t)0x45670123U)        /*!< unlock key 0 */
+#define UNLOCK_KEY1                ((uint32_t)0xCDEF89ABU)        /*!< unlock key 1 */
+
+/* FMC wait state counter */
+#define WS_WSCNT(regval)           (BITS(0,2) & ((uint32_t)(regval)))
+#define WS_WSCNT_0                 WS_WSCNT(0)                    /*!< FMC 0 wait */
+#define WS_WSCNT_1                 WS_WSCNT(1)                    /*!< FMC 1 wait */
+#define WS_WSCNT_2                 WS_WSCNT(2)                    /*!< FMC 2 wait */
+
+/* option bytes software/hardware free watch dog timer */  
+#define OB_FWDGT_SW                ((uint8_t)0x01U)               /*!< software free watchdog */
+#define OB_FWDGT_HW                ((uint8_t)0x00U)               /*!< hardware free watchdog */
+
+/* option bytes reset or not entering deep sleep mode */
+#define OB_DEEPSLEEP_NRST          ((uint8_t)0x02U)               /*!< no reset when entering deepsleep mode */
+#define OB_DEEPSLEEP_RST           ((uint8_t)0x00U)               /*!< generate a reset instead of entering deepsleep mode */
+
+/* option bytes reset or not entering standby mode */
+#define OB_STDBY_NRST              ((uint8_t)0x04U)               /*!< no reset when entering deepsleep mode */
+#define OB_STDBY_RST               ((uint8_t)0x00U)               /*!< generate a reset instead of entering standby mode */
+
+/* option bytes boot bank value */
+#define OB_BOOT_B0                 ((uint8_t)0x08U)               /*!< boot from bank0 */
+#define OB_BOOT_B1                 ((uint8_t)0x00U)               /*!< boot from bank1 */
+
+#define OB_USER_MASK               ((uint8_t)0xF0U)               /*!< MASK value */
+
+/* read protect configure */
+#define FMC_NSPC                   ((uint8_t)0xA5U)               /*!< no security protection */
+#define FMC_USPC                   ((uint8_t)0xBBU)               /*!< under security protection */
+
+/* OB_SPC */
+#define OB_SPC_SPC                 ((uint32_t)0x000000FFU)        /*!< option byte security protection value */
+#define OB_SPC_SPC_N               ((uint32_t)0x0000FF00U)        /*!< option byte security protection complement value */
+
+/* OB_USER */
+#define OB_USER_USER               ((uint32_t)0x00FF0000U)        /*!< user option value */
+#define OB_USER_USER_N             ((uint32_t)0xFF000000U)        /*!< user option complement value */
+
+/* OB_WP0 */
+#define OB_WP0_WP0                 ((uint32_t)0x000000FFU)        /*!< FMC write protection option value */
+
+/* OB_WP1 */
+#define OB_WP1_WP1                 ((uint32_t)0x0000FF00U)        /*!< FMC write protection option complement value */
+
+/* OB_WP2 */
+#define OB_WP2_WP2                 ((uint32_t)0x00FF0000U)        /*!< FMC write protection option value */
+
+/* OB_WP3 */
+#define OB_WP3_WP3                 ((uint32_t)0xFF000000U)        /*!< FMC write protection option complement value */
+
+/* option bytes write protection */
+#define OB_WP_0                    ((uint32_t)0x00000001U)        /*!< erase/program protection of sector 0  */
+#define OB_WP_1                    ((uint32_t)0x00000002U)        /*!< erase/program protection of sector 1  */
+#define OB_WP_2                    ((uint32_t)0x00000004U)        /*!< erase/program protection of sector 2  */
+#define OB_WP_3                    ((uint32_t)0x00000008U)        /*!< erase/program protection of sector 3  */
+#define OB_WP_4                    ((uint32_t)0x00000010U)        /*!< erase/program protection of sector 4  */
+#define OB_WP_5                    ((uint32_t)0x00000020U)        /*!< erase/program protection of sector 5  */
+#define OB_WP_6                    ((uint32_t)0x00000040U)        /*!< erase/program protection of sector 6  */
+#define OB_WP_7                    ((uint32_t)0x00000080U)        /*!< erase/program protection of sector 7  */
+#define OB_WP_8                    ((uint32_t)0x00000100U)        /*!< erase/program protection of sector 8  */
+#define OB_WP_9                    ((uint32_t)0x00000200U)        /*!< erase/program protection of sector 9  */
+#define OB_WP_10                   ((uint32_t)0x00000400U)        /*!< erase/program protection of sector 10 */
+#define OB_WP_11                   ((uint32_t)0x00000800U)        /*!< erase/program protection of sector 11 */
+#define OB_WP_12                   ((uint32_t)0x00001000U)        /*!< erase/program protection of sector 12 */
+#define OB_WP_13                   ((uint32_t)0x00002000U)        /*!< erase/program protection of sector 13 */
+#define OB_WP_14                   ((uint32_t)0x00004000U)        /*!< erase/program protection of sector 14 */
+#define OB_WP_15                   ((uint32_t)0x00008000U)        /*!< erase/program protection of sector 15 */
+#define OB_WP_16                   ((uint32_t)0x00010000U)        /*!< erase/program protection of sector 16 */
+#define OB_WP_17                   ((uint32_t)0x00020000U)        /*!< erase/program protection of sector 17 */
+#define OB_WP_18                   ((uint32_t)0x00040000U)        /*!< erase/program protection of sector 18 */
+#define OB_WP_19                   ((uint32_t)0x00080000U)        /*!< erase/program protection of sector 19 */
+#define OB_WP_20                   ((uint32_t)0x00100000U)        /*!< erase/program protection of sector 20 */
+#define OB_WP_21                   ((uint32_t)0x00200000U)        /*!< erase/program protection of sector 21 */
+#define OB_WP_22                   ((uint32_t)0x00400000U)        /*!< erase/program protection of sector 22 */
+#define OB_WP_23                   ((uint32_t)0x00800000U)        /*!< erase/program protection of sector 23 */
+#define OB_WP_24                   ((uint32_t)0x01000000U)        /*!< erase/program protection of sector 24 */
+#define OB_WP_25                   ((uint32_t)0x02000000U)        /*!< erase/program protection of sector 25 */
+#define OB_WP_26                   ((uint32_t)0x04000000U)        /*!< erase/program protection of sector 26 */
+#define OB_WP_27                   ((uint32_t)0x08000000U)        /*!< erase/program protection of sector 27 */
+#define OB_WP_28                   ((uint32_t)0x10000000U)        /*!< erase/program protection of sector 28 */
+#define OB_WP_29                   ((uint32_t)0x20000000U)        /*!< erase/program protection of sector 29 */
+#define OB_WP_30                   ((uint32_t)0x40000000U)        /*!< erase/program protection of sector 30 */
+#define OB_WP_31                   ((uint32_t)0x80000000U)        /*!< erase/program protection of sector 31 */
+#define OB_WP_ALL                  ((uint32_t)0xFFFFFFFFU)        /*!< erase/program protection of all sectors */
+
+/* FMC timeout */
+#define FMC_TIMEOUT_COUNT          ((uint32_t)0x000F0000U)        /*!< FMC timeout count value */
+
+/* FMC BANK address */
+#define FMC_BANK0_END_ADDRESS      ((uint32_t)0x0807FFFFU)        /*!< FMC bank0 end address */
+#define FMC_BANK0_SIZE             ((uint32_t)0x00000200U)        /*!< FMC bank0 size */
+#define FMC_SIZE                   (*(uint16_t *)0x1FFFF7E0U)     /*!< FMC size */
+
+/* function declarations */
+/* FMC main memory programming functions */
+/* set the FMC wait state counter */
+void fmc_wscnt_set(uint32_t wscnt);
+/* unlock the main FMC operation */
+void fmc_unlock(void);
+/* unlock the FMC bank0 operation */
+void fmc_bank0_unlock(void);
+/* unlock the FMC bank1 operation */
+void fmc_bank1_unlock(void);
+/* lock the main FMC operation */
+void fmc_lock(void);
+/* lock the bank0 FMC operation */
+void fmc_bank0_lock(void);
+/* lock the bank1 FMC operation */
+void fmc_bank1_lock(void);
+/* FMC erase page */
+fmc_state_enum fmc_page_erase(uint32_t page_address);
+/* FMC erase whole chip */
+fmc_state_enum fmc_mass_erase(void);
+/* FMC erase whole bank0 */
+fmc_state_enum fmc_bank0_erase(void);
+/* FMC erase whole bank1 */
+fmc_state_enum fmc_bank1_erase(void);
+/* FMC program a word at the corresponding address */
+fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
+/* FMC program a half word at the corresponding address */
+fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
+
+/* FMC option bytes programming functions */
+/* unlock the option byte operation */
+void ob_unlock(void);
+/* lock the option byte operation */
+void ob_lock(void);
+/* erase the option byte */
+fmc_state_enum ob_erase(void);
+/* enable write protect */
+fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
+/* configure the option byte security protection */
+fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
+/* write the FMC option byte */
+fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
+/* program option bytes data */
+fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
+/* get the FMC option byte user */
+uint8_t ob_user_get(void);
+/* get OB_DATA in register FMC_OBSTAT */
+uint16_t ob_data_get(void);
+/* get the FMC option byte write protection */
+uint32_t ob_write_protection_get(void);
+/* get option byte security protection code value */
+FlagStatus ob_spc_get(void);
+
+/* FMC interrupts and flags management functions */
+/* enable FMC interrupt */
+void fmc_interrupt_enable(uint32_t interrupt);
+/* disable FMC interrupt */
+void fmc_interrupt_disable(uint32_t interrupt);
+/* check flag is set or not */
+FlagStatus fmc_flag_get(uint32_t flag);
+/* clear the FMC flag */
+void fmc_flag_clear(uint32_t flag);
+/* get FMC interrupt flag state */
+FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
+/* clear FMC interrupt flag state */
+void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
+/* return the  FMC bank0 state */
+fmc_state_enum fmc_bank0_state_get(void);
+/* return the  FMC bank1 state */
+fmc_state_enum fmc_bank1_state_get(void);
+/* check FMC bank0 ready or not */
+fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
+/* check FMC bank1 ready or not */
+fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
+
+#endif /* GD32F20X_FMC_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_fwdgt.h

@@ -0,0 +1,110 @@
+/*!
+    \file  gd32f20x_fwdgt.h
+    \brief definitions for the FWDGT
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_FWDGT_H
+#define GD32F20X_FWDGT_H
+
+#include "gd32f20x.h"
+
+/* FWDGT definitions */
+#define FWDGT                       FWDGT_BASE                                /*!< FWDGT base address */
+
+/* registers definitions */
+#define FWDGT_CTL                   REG32((FWDGT) + 0x00U)                    /*!< FWDGT control register */
+#define FWDGT_PSC                   REG32((FWDGT) + 0x04U)                    /*!< FWDGT prescaler register */
+#define FWDGT_RLD                   REG32((FWDGT) + 0x08U)                    /*!< FWDGT reload register */
+#define FWDGT_STAT                  REG32((FWDGT) + 0x0CU)                    /*!< FWDGT status register */
+
+/* bits definitions */
+/* FWDGT_CTL */
+#define FWDGT_CTL_CMD               BITS(0,15)                                /*!< FWDGT command value */
+
+/* FWDGT_PSC */
+#define FWDGT_PSC_PSC               BITS(0,2)                                 /*!< FWDGT prescaler divider value */
+
+/* FWDGT_RLD */
+#define FWDGT_RLD_RLD               BITS(0,11)                                /*!< FWDGT counter reload value */
+
+/* FWDGT_STAT */
+#define FWDGT_STAT_PUD              BIT(0)                                    /*!< FWDGT prescaler divider value update */
+#define FWDGT_STAT_RUD              BIT(1)                                    /*!< FWDGT counter reload value update */
+
+/* constants definitions */
+/* psc register value */
+#define PSC_PSC(regval)             (BITS(0,2) & ((uint32_t)(regval) << 0))
+#define FWDGT_PSC_DIV4              ((uint8_t)PSC_PSC(0))                     /*!< FWDGT prescaler set to 4 */
+#define FWDGT_PSC_DIV8              ((uint8_t)PSC_PSC(1))                     /*!< FWDGT prescaler set to 8 */
+#define FWDGT_PSC_DIV16             ((uint8_t)PSC_PSC(2))                     /*!< FWDGT prescaler set to 16 */
+#define FWDGT_PSC_DIV32             ((uint8_t)PSC_PSC(3))                     /*!< FWDGT prescaler set to 32 */
+#define FWDGT_PSC_DIV64             ((uint8_t)PSC_PSC(4))                     /*!< FWDGT prescaler set to 64 */
+#define FWDGT_PSC_DIV128            ((uint8_t)PSC_PSC(5))                     /*!< FWDGT prescaler set to 128 */
+#define FWDGT_PSC_DIV256            ((uint8_t)PSC_PSC(6))                     /*!< FWDGT prescaler set to 256 */
+
+/* control value */
+#define FWDGT_WRITEACCESS_ENABLE    ((uint16_t)0x5555U)                       /*!< FWDGT_CTL bits write access enable value */
+#define FWDGT_WRITEACCESS_DISABLE   ((uint16_t)0x0000U)                       /*!< FWDGT_CTL bits write access disable value */
+#define FWDGT_KEY_RELOAD            ((uint16_t)0xAAAAU)                       /*!< FWDGT_CTL bits fwdgt counter reload value */
+#define FWDGT_KEY_ENABLE            ((uint16_t)0xCCCCU)                       /*!< FWDGT_CTL bits fwdgt counter enable value */
+
+/* FWDGT timeout value */
+#define FWDGT_PSC_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_PSC register write operation state flag timeout */
+#define FWDGT_RLD_TIMEOUT           ((uint32_t)0x000FFFFFU)                   /*!< FWDGT_RLD register write operation state flag timeout */
+
+/* FWDGT flag definitions */
+#define FWDGT_FLAG_PUD              FWDGT_STAT_PUD                            /*!< FWDGT prescaler divider value update flag */
+#define FWDGT_FLAG_RUD              FWDGT_STAT_RUD                            /*!< FWDGT counter reload value update flag */
+
+/* function declarations */
+/* function configuration */
+/* enable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_enable(void);
+/* disable write access to FWDGT_PSC and FWDGT_RLD */
+void fwdgt_write_disable(void);
+/* start the free watchdog timer counter */
+void fwdgt_enable(void);
+
+/* reload the counter of FWDGT */
+void fwdgt_counter_reload(void);
+/* configure counter reload value, and prescaler divider value */
+ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
+
+/* interrupt & flag functions */
+/* get flag state of FWDGT */
+FlagStatus fwdgt_flag_get(uint16_t flag);
+
+#endif /* GD32F20X_FWDGT_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_gpio.h

@@ -0,0 +1,719 @@
+/*!
+    \file  gd32f20x_gpio.h
+    \brief definitions for the GPIO
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_GPIO_H
+#define GD32F20X_GPIO_H
+
+#include "gd32f20x.h"
+
+/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */
+#define GPIOA                      (GPIO_BASE + 0x00000000U)
+#define GPIOB                      (GPIO_BASE + 0x00000400U)
+#define GPIOC                      (GPIO_BASE + 0x00000800U)
+#define GPIOD                      (GPIO_BASE + 0x00000C00U)
+#define GPIOE                      (GPIO_BASE + 0x00001000U)
+#define GPIOF                      (GPIO_BASE + 0x00001400U)
+#define GPIOG                      (GPIO_BASE + 0x00001800U)
+#define GPIOH                      (GPIO_BASE + 0x00006C00U)
+#define GPIOI                      (GPIO_BASE + 0x00007000U)
+
+/* AFIO definitions */
+#define AFIO                       AFIO_BASE
+
+/* registers definitions */
+/* GPIO registers definitions */
+#define GPIO_CTL0(gpiox)           REG32((gpiox) + 0x00U)    /*!< GPIO port control register 0 */
+#define GPIO_CTL1(gpiox)           REG32((gpiox) + 0x04U)    /*!< GPIO port control register 1 */
+#define GPIO_ISTAT(gpiox)          REG32((gpiox) + 0x08U)    /*!< GPIO port input status register */
+#define GPIO_OCTL(gpiox)           REG32((gpiox) + 0x0CU)    /*!< GPIO port output control register */
+#define GPIO_BOP(gpiox)            REG32((gpiox) + 0x10U)    /*!< GPIO port bit operation register */
+#define GPIO_BC(gpiox)             REG32((gpiox) + 0x14U)    /*!< GPIO bit clear register */
+#define GPIO_LOCK(gpiox)           REG32((gpiox) + 0x18U)    /*!< GPIO port configuration lock register */
+
+/* AFIO registers definitions */
+#define AFIO_EC                    REG32(AFIO + 0x00U)       /*!< AFIO event control register */
+#define AFIO_PCF0                  REG32(AFIO + 0x04U)       /*!< AFIO port configuration register 0 */
+#define AFIO_EXTISS0               REG32(AFIO + 0x08U)       /*!< AFIO port EXTI sources selection register 0 */
+#define AFIO_EXTISS1               REG32(AFIO + 0x0CU)       /*!< AFIO port EXTI sources selection register 1 */
+#define AFIO_EXTISS2               REG32(AFIO + 0x10U)       /*!< AFIO port EXTI sources selection register 2 */
+#define AFIO_EXTISS3               REG32(AFIO + 0x14U)       /*!< AFIO port EXTI sources selection register 3 */
+#define AFIO_PCF1                  REG32(AFIO + 0x1CU)       /*!< AFIO port configuration register 1 */
+#define AFIO_PCF2                  REG32(AFIO + 0x3CU)       /*!< AFIO port configuration register 2 */
+#define AFIO_PCF3                  REG32(AFIO + 0x40U)       /*!< AFIO port configuration register 3 */
+#define AFIO_PCF4                  REG32(AFIO + 0x44U)       /*!< AFIO port configuration register 4 */
+#define AFIO_PCF5                  REG32(AFIO + 0x48U)       /*!< AFIO port configuration register 5 */
+
+/* bits definitions */
+/* GPIO_CTL0 */
+#define GPIO_CTL0_MD0              BITS(0,1)                 /*!< port 0 mode bits */ 
+#define GPIO_CTL0_CTL0             BITS(2,3)                 /*!< pin 0 configuration bits */
+#define GPIO_CTL0_MD1              BITS(4,5)                 /*!< port 1 mode bits */
+#define GPIO_CTL0_CTL1             BITS(6,7)                 /*!< pin 1 configuration bits */
+#define GPIO_CTL0_MD2              BITS(8,9)                 /*!< port 2 mode bits */
+#define GPIO_CTL0_CTL2             BITS(10,11)               /*!< pin 2 configuration bits */
+#define GPIO_CTL0_MD3              BITS(12,13)               /*!< port 3 mode bits */
+#define GPIO_CTL0_CTL3             BITS(14,15)               /*!< pin 3 configuration bits */
+#define GPIO_CTL0_MD4              BITS(16,17)               /*!< port 4 mode bits */
+#define GPIO_CTL0_CTL4             BITS(18,19)               /*!< pin 4 configuration bits */
+#define GPIO_CTL0_MD5              BITS(20,21)               /*!< port 5 mode bits */
+#define GPIO_CTL0_CTL5             BITS(22,23)               /*!< pin 5 configuration bits */
+#define GPIO_CTL0_MD6              BITS(24,25)               /*!< port 6 mode bits */
+#define GPIO_CTL0_CTL6             BITS(26,27)               /*!< pin 6 configuration bits */
+#define GPIO_CTL0_MD7              BITS(28,29)               /*!< port 7 mode bits */
+#define GPIO_CTL0_CTL7             BITS(30,31)               /*!< pin 7 configuration bits */
+
+/* GPIO_CTL1 */
+#define GPIO_CTL1_MD8              BITS(0,1)                 /*!< port 8 mode bits */ 
+#define GPIO_CTL1_CTL8             BITS(2,3)                 /*!< pin 8 configuration bits */
+#define GPIO_CTL1_MD9              BITS(4,5)                 /*!< port 9 mode bits */
+#define GPIO_CTL1_CTL9             BITS(6,7)                 /*!< pin 9 configuration bits */
+#define GPIO_CTL1_MD10             BITS(8,9)                 /*!< port 10 mode bits */
+#define GPIO_CTL1_CTL10            BITS(10,11)               /*!< pin 10 configuration bits */
+#define GPIO_CTL1_MD11             BITS(12,13)               /*!< port 11 mode bits */
+#define GPIO_CTL1_CTL11            BITS(14,15)               /*!< pin 11 configuration bits */
+#define GPIO_CTL1_MD12             BITS(16,17)               /*!< port 12 mode bits */
+#define GPIO_CTL1_CTL12            BITS(18,19)               /*!< pin 12 configuration bits */
+#define GPIO_CTL1_MD13             BITS(20,21)               /*!< port 13 mode bits */
+#define GPIO_CTL1_CTL13            BITS(22,23)               /*!< pin 13 configuration bits */
+#define GPIO_CTL1_MD14             BITS(24,25)               /*!< port 14 mode bits */
+#define GPIO_CTL1_CTL14            BITS(26,27)               /*!< pin 14 configuration bits */
+#define GPIO_CTL1_MD15             BITS(28,29)               /*!< port 15 mode bits */
+#define GPIO_CTL1_CTL15            BITS(30,31)               /*!< pin 15 configuration bits */
+
+/* GPIO_ISTAT */
+#define GPIO_ISTAT_ISTAT0          BIT(0)                    /*!< pin 0 input status */
+#define GPIO_ISTAT_ISTAT1          BIT(1)                    /*!< pin 1 input status */
+#define GPIO_ISTAT_ISTAT2          BIT(2)                    /*!< pin 2 input status */
+#define GPIO_ISTAT_ISTAT3          BIT(3)                    /*!< pin 3 input status */
+#define GPIO_ISTAT_ISTAT4          BIT(4)                    /*!< pin 4 input status */
+#define GPIO_ISTAT_ISTAT5          BIT(5)                    /*!< pin 5 input status */
+#define GPIO_ISTAT_ISTAT6          BIT(6)                    /*!< pin 6 input status */
+#define GPIO_ISTAT_ISTAT7          BIT(7)                    /*!< pin 7 input status */
+#define GPIO_ISTAT_ISTAT8          BIT(8)                    /*!< pin 8 input status */
+#define GPIO_ISTAT_ISTAT9          BIT(9)                    /*!< pin 9 input status */
+#define GPIO_ISTAT_ISTAT10         BIT(10)                   /*!< pin 10 input status */
+#define GPIO_ISTAT_ISTAT11         BIT(11)                   /*!< pin 11 input status */
+#define GPIO_ISTAT_ISTAT12         BIT(12)                   /*!< pin 12 input status */
+#define GPIO_ISTAT_ISTAT13         BIT(13)                   /*!< pin 13 input status */
+#define GPIO_ISTAT_ISTAT14         BIT(14)                   /*!< pin 14 input status */
+#define GPIO_ISTAT_ISTAT15         BIT(15)                   /*!< pin 15 input status */
+
+/* GPIO_OCTL */
+#define GPIO_OCTL_OCTL0            BIT(0)                    /*!< pin 0 output bit */
+#define GPIO_OCTL_OCTL1            BIT(1)                    /*!< pin 1 output bit */
+#define GPIO_OCTL_OCTL2            BIT(2)                    /*!< pin 2 output bit */
+#define GPIO_OCTL_OCTL3            BIT(3)                    /*!< pin 3 output bit */
+#define GPIO_OCTL_OCTL4            BIT(4)                    /*!< pin 4 output bit */
+#define GPIO_OCTL_OCTL5            BIT(5)                    /*!< pin 5 output bit */
+#define GPIO_OCTL_OCTL6            BIT(6)                    /*!< pin 6 output bit */
+#define GPIO_OCTL_OCTL7            BIT(7)                    /*!< pin 7 output bit */
+#define GPIO_OCTL_OCTL8            BIT(8)                    /*!< pin 8 output bit */
+#define GPIO_OCTL_OCTL9            BIT(9)                    /*!< pin 9 output bit */
+#define GPIO_OCTL_OCTL10           BIT(10)                   /*!< pin 10 output bit */
+#define GPIO_OCTL_OCTL11           BIT(11)                   /*!< pin 11 output bit */
+#define GPIO_OCTL_OCTL12           BIT(12)                   /*!< pin 12 output bit */
+#define GPIO_OCTL_OCTL13           BIT(13)                   /*!< pin 13 output bit */
+#define GPIO_OCTL_OCTL14           BIT(14)                   /*!< pin 14 output bit */
+#define GPIO_OCTL_OCTL15           BIT(15)                   /*!< pin 15 output bit */
+
+/* GPIO_BOP */
+#define GPIO_BOP_BOP0              BIT(0)                    /*!< pin 0 set bit */
+#define GPIO_BOP_BOP1              BIT(1)                    /*!< pin 1 set bit */
+#define GPIO_BOP_BOP2              BIT(2)                    /*!< pin 2 set bit */
+#define GPIO_BOP_BOP3              BIT(3)                    /*!< pin 3 set bit */
+#define GPIO_BOP_BOP4              BIT(4)                    /*!< pin 4 set bit */
+#define GPIO_BOP_BOP5              BIT(5)                    /*!< pin 5 set bit */
+#define GPIO_BOP_BOP6              BIT(6)                    /*!< pin 6 set bit */
+#define GPIO_BOP_BOP7              BIT(7)                    /*!< pin 7 set bit */
+#define GPIO_BOP_BOP8              BIT(8)                    /*!< pin 8 set bit */
+#define GPIO_BOP_BOP9              BIT(9)                    /*!< pin 9 set bit */
+#define GPIO_BOP_BOP10             BIT(10)                   /*!< pin 10 set bit */
+#define GPIO_BOP_BOP11             BIT(11)                   /*!< pin 11 set bit */
+#define GPIO_BOP_BOP12             BIT(12)                   /*!< pin 12 set bit */
+#define GPIO_BOP_BOP13             BIT(13)                   /*!< pin 13 set bit */
+#define GPIO_BOP_BOP14             BIT(14)                   /*!< pin 14 set bit */
+#define GPIO_BOP_BOP15             BIT(15)                   /*!< pin 15 set bit */
+#define GPIO_BOP_CR0               BIT(16)                   /*!< pin 0 clear bit */
+#define GPIO_BOP_CR1               BIT(17)                   /*!< pin 1 clear bit */
+#define GPIO_BOP_CR2               BIT(18)                   /*!< pin 2 clear bit */
+#define GPIO_BOP_CR3               BIT(19)                   /*!< pin 3 clear bit */
+#define GPIO_BOP_CR4               BIT(20)                   /*!< pin 4 clear bit */
+#define GPIO_BOP_CR5               BIT(21)                   /*!< pin 5 clear bit */
+#define GPIO_BOP_CR6               BIT(22)                   /*!< pin 6 clear bit */
+#define GPIO_BOP_CR7               BIT(23)                   /*!< pin 7 clear bit */
+#define GPIO_BOP_CR8               BIT(24)                   /*!< pin 8 clear bit */
+#define GPIO_BOP_CR9               BIT(25)                   /*!< pin 9 clear bit */
+#define GPIO_BOP_CR10              BIT(26)                   /*!< pin 10 clear bit */
+#define GPIO_BOP_CR11              BIT(27)                   /*!< pin 11 clear bit */
+#define GPIO_BOP_CR12              BIT(28)                   /*!< pin 12 clear bit */
+#define GPIO_BOP_CR13              BIT(29)                   /*!< pin 13 clear bit */
+#define GPIO_BOP_CR14              BIT(30)                   /*!< pin 14 clear bit */
+#define GPIO_BOP_CR15              BIT(31)                   /*!< pin 15 clear bit */
+
+/* GPIO_BC */
+#define GPIO_BC_CR0                BIT(0)                    /*!< pin 0 clear bit */
+#define GPIO_BC_CR1                BIT(1)                    /*!< pin 1 clear bit */
+#define GPIO_BC_CR2                BIT(2)                    /*!< pin 2 clear bit */
+#define GPIO_BC_CR3                BIT(3)                    /*!< pin 3 clear bit */
+#define GPIO_BC_CR4                BIT(4)                    /*!< pin 4 clear bit */
+#define GPIO_BC_CR5                BIT(5)                    /*!< pin 5 clear bit */
+#define GPIO_BC_CR6                BIT(6)                    /*!< pin 6 clear bit */
+#define GPIO_BC_CR7                BIT(7)                    /*!< pin 7 clear bit */
+#define GPIO_BC_CR8                BIT(8)                    /*!< pin 8 clear bit */
+#define GPIO_BC_CR9                BIT(9)                    /*!< pin 9 clear bit */
+#define GPIO_BC_CR10               BIT(10)                   /*!< pin 10 clear bit */
+#define GPIO_BC_CR11               BIT(11)                   /*!< pin 11 clear bit */
+#define GPIO_BC_CR12               BIT(12)                   /*!< pin 12 clear bit */
+#define GPIO_BC_CR13               BIT(13)                   /*!< pin 13 clear bit */
+#define GPIO_BC_CR14               BIT(14)                   /*!< pin 14 clear bit */
+#define GPIO_BC_CR15               BIT(15)                   /*!< pin 15 clear bit */
+
+/* GPIO_LOCK */
+#define GPIO_LOCK_LK0              BIT(0)                    /*!< pin 0 lock bit */
+#define GPIO_LOCK_LK1              BIT(1)                    /*!< pin 1 lock bit */
+#define GPIO_LOCK_LK2              BIT(2)                    /*!< pin 2 lock bit */
+#define GPIO_LOCK_LK3              BIT(3)                    /*!< pin 3 lock bit */
+#define GPIO_LOCK_LK4              BIT(4)                    /*!< pin 4 lock bit */
+#define GPIO_LOCK_LK5              BIT(5)                    /*!< pin 5 lock bit */
+#define GPIO_LOCK_LK6              BIT(6)                    /*!< pin 6 lock bit */
+#define GPIO_LOCK_LK7              BIT(7)                    /*!< pin 7 lock bit */
+#define GPIO_LOCK_LK8              BIT(8)                    /*!< pin 8 lock bit */
+#define GPIO_LOCK_LK9              BIT(9)                    /*!< pin 9 lock bit */
+#define GPIO_LOCK_LK10             BIT(10)                   /*!< pin 10 lock bit */
+#define GPIO_LOCK_LK11             BIT(11)                   /*!< pin 11 lock bit */
+#define GPIO_LOCK_LK12             BIT(12)                   /*!< pin 12 lock bit */
+#define GPIO_LOCK_LK13             BIT(13)                   /*!< pin 13 lock bit */
+#define GPIO_LOCK_LK14             BIT(14)                   /*!< pin 14 lock bit */
+#define GPIO_LOCK_LK15             BIT(15)                   /*!< pin 15 lock bit */
+#define GPIO_LOCK_LKK              BIT(16)                   /*!< pin sequence lock key */
+
+/* AFIO_EC */
+#define AFIO_EC_PIN                BITS(0,3)                 /*!< event output pin selection */
+#define AFIO_EC_PORT               BITS(4,6)                 /*!< event output port selection */
+#define AFIO_EC_EOE                BIT(7)                    /*!< event output enable */
+
+/* AFIO_PCF0 */
+#define AFIO_PCF0_SPI0_REMAP             BIT(0)              /*!< SPI0 remapping */
+#define AFIO_PCF0_I2C0_REMAP             BIT(1)              /*!< I2C0 remapping */
+#define AFIO_PCF0_USART0_REMAP           BIT(2)              /*!< USART0 remapping */
+#define AFIO_PCF0_USART1_REMAP           BIT(3)              /*!< USART1 remapping */
+#define AFIO_PCF0_USART2_REMAP           BITS(4,5)           /*!< USART2 remapping */
+#define AFIO_PCF0_TIMER0_REMAP           BITS(6,7)           /*!< TIMER0 remapping */
+#define AFIO_PCF0_TIMER1_REMAP           BITS(8,9)           /*!< TIMER1 remapping */
+#define AFIO_PCF0_TIMER2_REMAP           BITS(10,11)         /*!< TIMER2 remapping */
+#define AFIO_PCF0_TIMER3_REMAP           BIT(12)             /*!< TIMER3 remapping */
+#define AFIO_PCF0_CAN0_REMAP             BITS(13,14)         /*!< CAN0 remapping */
+#define AFIO_PCF0_PD01_REMAP             BIT(15)             /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCF0_TIMER4CH3_IREMAP       BIT(16)             /*!< TIMER4 channel3 internal remapping */
+#define AFIO_PCF0_ADC0_ETRGINS_REMAP     BIT(17)             /*!< ADC 0 external trigger inserted conversion remapping */
+#define AFIO_PCF0_ADC0_ETRGREG_REMAP     BIT(18)             /*!< ADC 0 external trigger regular conversion remapping */
+#define AFIO_PCF0_ADC1_ETRGINS_REMAP     BIT(19)             /*!< ADC 1 external trigger inserted conversion remapping */
+#define AFIO_PCF0_ADC1_ETRGREG_REMAP     BIT(20)             /*!< ADC 1 external trigger regular conversion remapping */
+#define AFIO_PCF0_ENET_REMAP             BIT(21)             /*!< ethernet MAC I/O remapping */
+#define AFIO_PCF0_CAN1_REMAP             BIT(22)             /*!< CAN1 remapping */
+#define AFIO_PCF0_ENET_PHY_SEL           BIT(23)             /*!< ethernet MII or RMII PHY selection */
+#define AFIO_PCF0_SWJ_CFG                BITS(24,26)         /*!< serial wire JTAG configuration */
+#define AFIO_PCF0_SPI2_REMAP             BIT(28)             /*!< SPI2/I2S2 remapping */
+#define AFIO_PCF0_TIMER1ITI1_REMAP       BIT(29)             /*!< TIMER1 internal trigger 1 remapping */
+#define AFIO_PCF0_PTP_PPS_REMAP          BIT(30)             /*!< ethernet PTP PPS remapping */
+
+/* AFIO_EXTISS0 */
+#define AFIO_EXTI0_SS                    BITS(0,3)           /*!< EXTI 0 sources selection */
+#define AFIO_EXTI1_SS                    BITS(4,7)           /*!< EXTI 1 sources selection */
+#define AFIO_EXTI2_SS                    BITS(8,11)          /*!< EXTI 2 sources selection */
+#define AFIO_EXTI3_SS                    BITS(12,15)         /*!< EXTI 3 sources selection */
+
+/* AFIO_EXTISS1 */
+#define AFIO_EXTI4_SS                    BITS(0,3)           /*!< EXTI 4 sources selection */
+#define AFIO_EXTI5_SS                    BITS(4,7)           /*!< EXTI 5 sources selection */
+#define AFIO_EXTI6_SS                    BITS(8,11)          /*!< EXTI 6 sources selection */
+#define AFIO_EXTI7_SS                    BITS(12,15)         /*!< EXTI 7 sources selection */
+
+/* AFIO_EXTISS2 */
+#define AFIO_EXTI8_SS                    BITS(0,3)           /*!< EXTI 8 sources selection */
+#define AFIO_EXTI9_SS                    BITS(4,7)           /*!< EXTI 9 sources selection */
+#define AFIO_EXTI10_SS                   BITS(8,11)          /*!< EXTI 10 sources selection */
+#define AFIO_EXTI11_SS                   BITS(12,15)         /*!< EXTI 11 sources selection */
+
+/* AFIO_EXTISS3 */
+#define AFIO_EXTI12_SS                   BITS(0,3)           /*!< EXTI 12 sources selection */
+#define AFIO_EXTI13_SS                   BITS(4,7)           /*!< EXTI 13 sources selection */
+#define AFIO_EXTI14_SS                   BITS(8,11)          /*!< EXTI 14 sources selection */
+#define AFIO_EXTI15_SS                   BITS(12,15)         /*!< EXTI 15 sources selection */
+
+/* AFIO_PCF1 */
+#define AFIO_PCF1_TIMER8_REMAP           BIT(5)              /*!< TIMER8 remapping */
+#define AFIO_PCF1_TIMER9_REMAP           BIT(6)              /*!< TIMER9 remapping */
+#define AFIO_PCF1_TIMER10_REMAP          BIT(7)              /*!< TIMER10 remapping */
+#define AFIO_PCF1_TIMER12_REMAP          BIT(8)              /*!< TIMER12 remapping */
+#define AFIO_PCF1_TIMER13_REMAP          BIT(9)              /*!< TIMER13 remapping */
+#define AFIO_PCF1_EXMC_NADV              BIT(10)             /*!< EXMC_NADV connect/disconnect */
+
+/* AFIO_PCF2 */
+#define AFIO_PCF2_DCI_VSYNC_REMAP        BITS(0,1)           /*!< DCI VSYNC remapping */
+#define AFIO_PCF2_DCI_D0_REMAP           BITS(2,3)           /*!< DCI D0 remapping */
+#define AFIO_PCF2_DCI_D1_REMAP           BITS(4,5)           /*!< DCI D1 remapping */
+#define AFIO_PCF2_DCI_D2_REMAP           BITS(6,7)           /*!< DCI D2 remapping */
+#define AFIO_PCF2_DCI_D3_REMAP           BITS(8,9)           /*!< DCI D3 remapping */
+#define AFIO_PCF2_DCI_D4_REMAP           BITS(10,11)         /*!< DCI D4 remapping */
+#define AFIO_PCF2_DCI_D5_REMAP           BITS(12,13)         /*!< DCI D5 remapping */
+#define AFIO_PCF2_DCI_D6_REMAP           BITS(14,15)         /*!< DCI D6 remapping */
+#define AFIO_PCF2_DCI_D7_REMAP           BITS(16,17)         /*!< DCI D7 remapping */
+#define AFIO_PCF2_DCI_D8_REMAP           BITS(18,19)         /*!< DCI D8 remapping */
+#define AFIO_PCF2_DCI_D9_REMAP           BITS(20,21)         /*!< DCI D9 remapping */
+#define AFIO_PCF2_DCI_D10_REMAP          BITS(22,23)         /*!< DCI D10 remapping */
+#define AFIO_PCF2_DCI_D11_REMAP          BITS(24,25)         /*!< DCI D11 remapping */
+#define AFIO_PCF2_DCI_D12_REMAP          BIT(26)             /*!< DCI D12 remapping */
+#define AFIO_PCF2_DCI_D13_REMAP          BITS(27,28)         /*!< DCI D13 remapping */
+#define AFIO_PCF2_DCI_HSYNC_REMAP        BIT(29)             /*!< DCI HSYNC remapping */
+#define AFIO_PCF2_PH01_REMAP             BIT(31)             /*!< PH0/PH1 remapping */
+
+/* AFIO_PCF3 */
+#define AFIO_PCF3_TLI_B5_PA3_REMAP       BIT(0)              /*!< TLI B5 PA3 remapping */
+#define AFIO_PCF3_TLI_VSYNC_PA4_REMAP    BIT(1)              /*!< TLI VSYNC PA4 remapping */
+#define AFIO_PCF3_TLI_G2_PA6_REMAP       BIT(2)              /*!< TLI G2 PA6 remapping */
+#define AFIO_PCF3_TLI_R6_PA8_REMAP       BIT(3)              /*!< TLI R6 PA8 remapping */
+#define AFIO_PCF3_TLI_R4_PA11_REMAP      BIT(4)              /*!< TLI R4 PA11 remapping */
+#define AFIO_PCF3_TLI_R5_PA12_REMAP      BIT(5)              /*!< TLI R5 PA12 remapping */
+#define AFIO_PCF3_TLI_R3_PB0_REMAP       BIT(6)              /*!< TLI R3 PB0 remapping */
+#define AFIO_PCF3_TLI_R6_PB1_REMAP       BIT(7)              /*!< TLI R6 PB1 remapping */
+#define AFIO_PCF3_TLI_B6_PB8_REMAP       BIT(8)              /*!< TLI B6 PB8 remapping */
+#define AFIO_PCF3_TLI_B7_PB9_REMAP       BIT(9)              /*!< TLI B7 PB9 remapping */
+#define AFIO_PCF3_TLI_G4_PB10_REMAP      BIT(10)             /*!< TLI G4 PB10 remapping */
+#define AFIO_PCF3_TLI_G5_PB11_REMAP      BIT(11)             /*!< TLI G5 PB11 remapping */
+#define AFIO_PCF3_TLI_HSYNC_PC6_REMAP    BIT(12)             /*!< TLI HSYNC PC6 remapping */
+#define AFIO_PCF3_TLI_G6_PC7_REMAP       BIT(13)             /*!< TLI G6 PC7 remapping */
+#define AFIO_PCF3_TLI_R2_PC10_REMAP      BIT(14)             /*!< TLI R2 PC10 remapping */
+#define AFIO_PCF3_TLI_G7_PD3_REMAP       BIT(15)             /*!< TLI G7 PD3 remapping */
+#define AFIO_PCF3_TLI_B2_PD6_REMAP       BIT(16)             /*!< TLI B2 PD6 remapping */
+#define AFIO_PCF3_TLI_B3_PD10_REMAP      BIT(17)             /*!< TLI B3 PD10 remapping */
+#define AFIO_PCF3_TLI_B0_PE4_REMAP       BIT(18)             /*!< TLI B0 PE4 remapping */
+#define AFIO_PCF3_TLI_G0_PE5_REMAP       BIT(19)             /*!< TLI G0 PE5 remapping */
+#define AFIO_PCF3_TLI_G1_PE6_REMAP       BIT(20)             /*!< TLI G1 PE6 remapping */
+#define AFIO_PCF3_TLI_G3_PE11_REMAP      BIT(21)             /*!< TLI G3 PE11 remapping */
+#define AFIO_PCF3_TLI_B4_PE12_REMAP      BIT(22)             /*!< TLI B4 PE12 remapping */
+#define AFIO_PCF3_TLI_DE_PE13_REMAP      BIT(23)             /*!< TLI DE PE13 remapping */
+#define AFIO_PCF3_TLI_CLK_PE14_REMAP     BIT(24)             /*!< TLI CLK PE14 remapping */
+#define AFIO_PCF3_TLI_R7_PE15_REMAP      BIT(25)             /*!< TLI R7 PE15 remapping */
+#define AFIO_PCF3_TLI_DE_PF10_REMAP      BIT(26)             /*!< TLI DE PF10 remapping */
+#define AFIO_PCF3_TLI_R7_PG6_REMAP       BIT(27)             /*!< TLI R7 PG6 remapping */
+#define AFIO_PCF3_TLI_CLK_PG7_REMAP      BIT(28)             /*!< TLI CLK PG7 remapping */
+#define AFIO_PCF3_TLI_G3_PG10_REMAP      BIT(29)             /*!< TLI G3 PG10 remapping */
+#define AFIO_PCF3_TLI_B2_PG10_REMAP      BIT(30)             /*!< TLI B2 PG10 remapping */
+#define AFIO_PCF3_TLI_B3_PG11_REMAP      BIT(31)             /*!< TLI B3 PG11 remapping */
+
+/* AFIO_PCF4 */
+#define AFIO_PCF4_TLI_B4_PG12_REMAP      BIT(0)              /*!< TLI B4 PG12 remapping  */
+#define AFIO_PCF4_TLI_B1_PG12_REMAP      BIT(1)              /*!< TLI B1 PG12 remapping  */
+#define AFIO_PCF4_TLI_R0_PH2_REMAP       BIT(2)              /*!< TLI R0 PH2 remapping  */
+#define AFIO_PCF4_TLI_R1_PH3_REMAP       BIT(3)              /*!< TLI R1 PH3 remapping  */
+#define AFIO_PCF4_TLI_R2_PH8_REMAP       BIT(4)              /*!< TLI R2 PH8 remapping  */
+#define AFIO_PCF4_TLI_R3_PH9_REMAP       BIT(5)              /*!< TLI R3 PH9 remapping  */
+#define AFIO_PCF4_TLI_R4_PH10_REMAP      BIT(6)              /*!< TLI R4 PH10 remapping  */
+#define AFIO_PCF4_TLI_R5_PH11_REMAP      BIT(7)              /*!< TLI R5 PH11 remapping  */
+#define AFIO_PCF4_TLI_R6_PH12_REMAP      BIT(8)              /*!< TLI R6 PH12 remapping  */
+#define AFIO_PCF4_TLI_G2_PH13_REMAP      BIT(9)              /*!< TLI G2 PH13 remapping  */
+#define AFIO_PCF4_TLI_G3_PH14_REMAP      BIT(10)             /*!< TLI G3 PH14 remapping  */
+#define AFIO_PCF4_TLI_G4_PH15_REMAP      BIT(11)             /*!< TLI G4 PH15 remapping  */
+#define AFIO_PCF4_TLI_G5_PI0_REMAP       BIT(12)             /*!< TLI G5 PI0 remapping  */
+#define AFIO_PCF4_TLI_G6_PI1_REMAP       BIT(13)             /*!< TLI G6 PI1 remapping  */
+#define AFIO_PCF4_TLI_G7_PI2_REMAP       BIT(14)             /*!< TLI G7 PI2 remapping  */
+#define AFIO_PCF4_TLI_B4_PI4_REMAP       BIT(15)             /*!< TLI B4 PI4 remapping  */
+#define AFIO_PCF4_TLI_B5_PI5_REMAP       BIT(16)             /*!< TLI B5 PI5 remapping  */
+#define AFIO_PCF4_TLI_B6_PI6_REMAP       BIT(17)             /*!< TLI B6 PI6 remapping  */
+#define AFIO_PCF4_TLI_B7_PI7_REMAP       BIT(18)             /*!< TLI B7 PI7 remapping  */
+#define AFIO_PCF4_TLI_VSYNC_PI9_REMAP    BIT(19)             /*!< TLI VSYNC PI9 remapping  */
+#define AFIO_PCF4_TLI_HSYNC_PI10_REMAP   BIT(20)             /*!< TLI HSYNC PI10 remapping  */
+#define AFIO_PCF4_TLI_R0_PH4_REMAP       BIT(21)             /*!< TLI R0 PH4 remapping  */
+#define AFIO_PCF4_TLI_R1_PI3_REMAP       BIT(22)             /*!< TLI R1 PI3 remapping  */
+#define AFIO_PCF4_SPI1_SCK_REMAP         BIT(23)             /*!< SPI1 SCK remapping  */
+#define AFIO_PCF4_SPI2_MOSI_REMAP        BIT(24)             /*!< SPI2 MOSI remapping  */
+
+/* AFIO_PCF5 */
+#define AFIO_PCF5_I2C2_REMAP0            BIT(0)              /*!< I2C2 remapping 0 */
+#define AFIO_PCF5_I2C2_REMAP1            BIT(1)              /*!< I2C2 remapping 1 */
+#define AFIO_PCF5_TIMER1_CH0_REMAP       BIT(2)              /*!< TIMER1 CH0 remapping */
+#define AFIO_PCF5_TIMER4_REMAP           BIT(3)              /*!< TIMER4 remapping */
+#define AFIO_PCF5_TIMER7_CHON_REMAP      BITS(4,5)           /*!< TIMER7 CHON remapping */
+#define AFIO_PCF5_TIMER7_CH_REMAP        BIT(6)              /*!< TIMER7 CH remapping */
+#define AFIO_PCF5_I2C1_REMAP             BITS(7,8)           /*!< I2C1 remapping */
+#define AFIO_PCF5_SPI1_NSCK_REMAP        BITS(9,10)          /*!< SPI1 NSCK remapping */
+#define AFIO_PCF5_SPI1_IO_REMAP          BITS(11,12)         /*!< SPI1 IO remapping */
+#define AFIO_PCF5_UART3_REMAP            BIT(13)             /*!< UART3 remapping */
+#define AFIO_PCF5_TIMER11_REMAP          BIT(14)             /*!< TIMER11 remapping */
+#define AFIO_PCF5_CAN0_ADD_REMAP         BIT(15)             /*!< CAN0 ADD remapping */
+#define AFIO_PCF5_ENET_TXD3_REMAP        BIT(16)             /*!< ENET TXD3 remapping */
+#define AFIO_PCF5_PPS_HI_REMAP           BIT(17)             /*!< ETH_PPS_OUT remapping */
+#define AFIO_PCF5_ENET_TXD01_REMAP       BIT(18)             /*!< ETH_TX_EN/ETH_TXD0/ETH_TXD1 remapping */
+#define AFIO_PCF5_ENET_CRSCOL_REMAP      BIT(19)             /*!< ETH_MII_CRS/ETH_MII_COL remapping */
+#define AFIO_PCF5_ENET_RX_HI_REMAP       BIT(20)             /*!< ETH_RXD2/ETH_RXD3/ETH_RX_ER remapping */
+#define AFIO_PCF5_UART6_REMAP            BIT(21)             /*!< UART6 remapping */
+#define AFIO_PCF5_USART5_CK_REMAP        BIT(22)             /*!< USART5 CK remapping */
+#define AFIO_PCF5_USART5_RTS_REMAP       BIT(23)             /*!< USART5 RTS remapping */
+#define AFIO_PCF5_USART5_CTS_REMAP       BIT(24)             /*!< USART5 CTS remapping */
+#define AFIO_PCF5_USART5_TX_REMAP        BIT(25)             /*!< USART5 TX remapping */
+#define AFIO_PCF5_USART5_RX_REMAP        BIT(26)             /*!< USART5 RX remapping */
+#define AFIO_PCF5_EXMC_SDNWE_REMAP       BIT(27)             /*!< EXMC SDNWE remapping */
+#define AFIO_PCF5_EXMC_SDCKE0_REMAP      BIT(28)             /*!< EXMC SDCKE0 remapping */
+#define AFIO_PCF5_EXMC_SDCKE1_REMAP      BIT(29)             /*!< EXMC SDCKE1 remapping */
+#define AFIO_PCF5_EXMC_SDNE0_REMAP       BIT(30)             /*!< EXMC SDNE0 remapping */
+#define AFIO_PCF5_EXMC_SDNE1_REMAP       BIT(30)             /*!< EXMC SDNE1 remapping */
+
+/* constants definitions */
+typedef FlagStatus bit_status;
+
+/* GPIO mode values set */
+#define GPIO_MODE_SET(n, mode)           ((uint32_t)((uint32_t)(mode) << (4U * (n))))
+#define GPIO_MODE_MASK(n)                (0xFU << (4U * (n)))
+
+/* GPIO mode definitions */
+#define GPIO_MODE_AIN                    ((uint8_t)0x00U)          /*!< analog input mode */
+#define GPIO_MODE_IN_FLOATING            ((uint8_t)0x04U)          /*!< floating input mode */
+#define GPIO_MODE_IPD                    ((uint8_t)0x28U)          /*!< pull-down input mode */
+#define GPIO_MODE_IPU                    ((uint8_t)0x48U)          /*!< pull-up input mode */
+#define GPIO_MODE_OUT_OD                 ((uint8_t)0x14U)          /*!< GPIO output with open-drain */
+#define GPIO_MODE_OUT_PP                 ((uint8_t)0x10U)          /*!< GPIO output with push-pull */
+#define GPIO_MODE_AF_OD                  ((uint8_t)0x1CU)          /*!< AFIO output with open-drain */
+#define GPIO_MODE_AF_PP                  ((uint8_t)0x18U)          /*!< AFIO output with push-pull */
+
+/* GPIO output max speed value */
+#define GPIO_OSPEED_10MHZ                ((uint8_t)0x01U)          /*!< output max speed 10MHz */
+#define GPIO_OSPEED_2MHZ                 ((uint8_t)0x02U)          /*!< output max speed 2MHz */
+#define GPIO_OSPEED_50MHZ                ((uint8_t)0x03U)          /*!< output max speed 50MHz */
+
+/* GPIO event output port definitions */
+#define GPIO_EVENT_PORT_GPIOA            ((uint8_t)0x00U)          /*!< event output port A */
+#define GPIO_EVENT_PORT_GPIOB            ((uint8_t)0x01U)          /*!< event output port B */
+#define GPIO_EVENT_PORT_GPIOC            ((uint8_t)0x02U)          /*!< event output port C */
+#define GPIO_EVENT_PORT_GPIOD            ((uint8_t)0x03U)          /*!< event output port D */
+#define GPIO_EVENT_PORT_GPIOE            ((uint8_t)0x04U)          /*!< event output port E */
+
+/* GPIO output port source definitions */
+#define GPIO_PORT_SOURCE_GPIOA           ((uint8_t)0x00U)          /*!< output port source A */
+#define GPIO_PORT_SOURCE_GPIOB           ((uint8_t)0x01U)          /*!< output port source B */
+#define GPIO_PORT_SOURCE_GPIOC           ((uint8_t)0x02U)          /*!< output port source C */
+#define GPIO_PORT_SOURCE_GPIOD           ((uint8_t)0x03U)          /*!< output port source D */
+#define GPIO_PORT_SOURCE_GPIOE           ((uint8_t)0x04U)          /*!< output port source E */
+#define GPIO_PORT_SOURCE_GPIOF           ((uint8_t)0x05U)          /*!< output port source F */
+#define GPIO_PORT_SOURCE_GPIOG           ((uint8_t)0x06U)          /*!< output port source G */
+#define GPIO_PORT_SOURCE_GPIOH           ((uint8_t)0x07U)          /*!< output port source H */
+#define GPIO_PORT_SOURCE_GPIOI           ((uint8_t)0x08U)          /*!< output port source I */
+
+/* GPIO event output pin definitions */
+#define GPIO_EVENT_PIN_0                 ((uint8_t)0x00U)          /*!< GPIO event pin 0 */
+#define GPIO_EVENT_PIN_1                 ((uint8_t)0x01U)          /*!< GPIO event pin 1 */
+#define GPIO_EVENT_PIN_2                 ((uint8_t)0x02U)          /*!< GPIO event pin 2 */
+#define GPIO_EVENT_PIN_3                 ((uint8_t)0x03U)          /*!< GPIO event pin 3 */
+#define GPIO_EVENT_PIN_4                 ((uint8_t)0x04U)          /*!< GPIO event pin 4 */
+#define GPIO_EVENT_PIN_5                 ((uint8_t)0x05U)          /*!< GPIO event pin 5 */
+#define GPIO_EVENT_PIN_6                 ((uint8_t)0x06U)          /*!< GPIO event pin 6 */
+#define GPIO_EVENT_PIN_7                 ((uint8_t)0x07U)          /*!< GPIO event pin 7 */
+#define GPIO_EVENT_PIN_8                 ((uint8_t)0x08U)          /*!< GPIO event pin 8 */
+#define GPIO_EVENT_PIN_9                 ((uint8_t)0x09U)          /*!< GPIO event pin 9 */
+#define GPIO_EVENT_PIN_10                ((uint8_t)0x0AU)          /*!< GPIO event pin 10 */
+#define GPIO_EVENT_PIN_11                ((uint8_t)0x0BU)          /*!< GPIO event pin 11 */
+#define GPIO_EVENT_PIN_12                ((uint8_t)0x0CU)          /*!< GPIO event pin 12 */
+#define GPIO_EVENT_PIN_13                ((uint8_t)0x0DU)          /*!< GPIO event pin 13 */
+#define GPIO_EVENT_PIN_14                ((uint8_t)0x0EU)          /*!< GPIO event pin 14 */
+#define GPIO_EVENT_PIN_15                ((uint8_t)0x0FU)          /*!< GPIO event pin 15 */
+
+/* GPIO output pin source definitions */
+#define GPIO_PIN_SOURCE_0                ((uint8_t)0x00U)          /*!< GPIO pin source 0 */
+#define GPIO_PIN_SOURCE_1                ((uint8_t)0x01U)          /*!< GPIO pin source 1 */
+#define GPIO_PIN_SOURCE_2                ((uint8_t)0x02U)          /*!< GPIO pin source 2 */
+#define GPIO_PIN_SOURCE_3                ((uint8_t)0x03U)          /*!< GPIO pin source 3 */
+#define GPIO_PIN_SOURCE_4                ((uint8_t)0x04U)          /*!< GPIO pin source 4 */
+#define GPIO_PIN_SOURCE_5                ((uint8_t)0x05U)          /*!< GPIO pin source 5 */
+#define GPIO_PIN_SOURCE_6                ((uint8_t)0x06U)          /*!< GPIO pin source 6 */
+#define GPIO_PIN_SOURCE_7                ((uint8_t)0x07U)          /*!< GPIO pin source 7 */
+#define GPIO_PIN_SOURCE_8                ((uint8_t)0x08U)          /*!< GPIO pin source 8 */
+#define GPIO_PIN_SOURCE_9                ((uint8_t)0x09U)          /*!< GPIO pin source 9 */
+#define GPIO_PIN_SOURCE_10               ((uint8_t)0x0AU)          /*!< GPIO pin source 10 */
+#define GPIO_PIN_SOURCE_11               ((uint8_t)0x0BU)          /*!< GPIO pin source 11 */
+#define GPIO_PIN_SOURCE_12               ((uint8_t)0x0CU)          /*!< GPIO pin source 12 */
+#define GPIO_PIN_SOURCE_13               ((uint8_t)0x0DU)          /*!< GPIO pin source 13 */
+#define GPIO_PIN_SOURCE_14               ((uint8_t)0x0EU)          /*!< GPIO pin source 14 */
+#define GPIO_PIN_SOURCE_15               ((uint8_t)0x0FU)          /*!< GPIO pin source 15 */
+
+/* GPIO pin definitions */
+#define GPIO_PIN_0                       BIT(0)                    /*!< GPIO pin 0 */
+#define GPIO_PIN_1                       BIT(1)                    /*!< GPIO pin 1 */
+#define GPIO_PIN_2                       BIT(2)                    /*!< GPIO pin 2 */
+#define GPIO_PIN_3                       BIT(3)                    /*!< GPIO pin 3 */
+#define GPIO_PIN_4                       BIT(4)                    /*!< GPIO pin 4 */
+#define GPIO_PIN_5                       BIT(5)                    /*!< GPIO pin 5 */
+#define GPIO_PIN_6                       BIT(6)                    /*!< GPIO pin 6 */
+#define GPIO_PIN_7                       BIT(7)                    /*!< GPIO pin 7 */
+#define GPIO_PIN_8                       BIT(8)                    /*!< GPIO pin 8 */
+#define GPIO_PIN_9                       BIT(9)                    /*!< GPIO pin 9 */
+#define GPIO_PIN_10                      BIT(10)                   /*!< GPIO pin 10 */
+#define GPIO_PIN_11                      BIT(11)                   /*!< GPIO pin 11 */
+#define GPIO_PIN_12                      BIT(12)                   /*!< GPIO pin 12 */
+#define GPIO_PIN_13                      BIT(13)                   /*!< GPIO pin 13 */
+#define GPIO_PIN_14                      BIT(14)                   /*!< GPIO pin 14 */
+#define GPIO_PIN_15                      BIT(15)                   /*!< GPIO pin 15 */
+#define GPIO_PIN_ALL                     BITS(0,15)                /*!< GPIO pin all */
+
+/* GPIO remap definitions */
+/* AFIO_PCF0 and AFIO_PCF1 remap definitions */
+#define GPIO_SPI0_REMAP                  ((uint32_t)0x00000001U)   /*!< SPI0 remapping */
+#define GPIO_I2C0_REMAP                  ((uint32_t)0x00000002U)   /*!< I2C0 remapping */
+#define GPIO_USART0_REMAP                ((uint32_t)0x00000004U)   /*!< USART0 remapping */
+#define GPIO_USART1_REMAP                ((uint32_t)0x00000008U)   /*!< USART1 remapping */
+#define GPIO_USART2_PARTIAL_REMAP        ((uint32_t)0x00140010U)   /*!< USART2 partial remapping */
+#define GPIO_USART2_FULL_REMAP           ((uint32_t)0x00140030U)   /*!< USART2 full remapping */
+#define GPIO_TIMER0_PARTIAL_REMAP        ((uint32_t)0x00160040U)   /*!< TIMER0 partial remapping */
+#define GPIO_TIMER0_FULL_REMAP           ((uint32_t)0x001600C0U)   /*!< TIMER0 full remapping */
+#define GPIO_TIMER1_PARTIAL_REMAP0       ((uint32_t)0x00180100U)   /*!< TIMER1 partial remapping */
+#define GPIO_TIMER1_PARTIAL_REMAP1       ((uint32_t)0x00180200U)   /*!< TIMER1 partial remapping */
+#define GPIO_TIMER1_FULL_REMAP           ((uint32_t)0x00180300U)   /*!< TIMER1 full remapping */
+#define GPIO_TIMER2_PARTIAL_REMAP        ((uint32_t)0x001A0800U)   /*!< TIMER2 partial remapping */
+#define GPIO_TIMER2_FULL_REMAP           ((uint32_t)0x001A0C00U)   /*!< TIMER2 full remapping */
+#define GPIO_TIMER3_REMAP                ((uint32_t)0x00001000U)   /*!< TIMER3 remapping */
+#define GPIO_CAN0_PARTIAL_REMAP          ((uint32_t)0x001D4000U)   /*!< CAN0 partial remapping */
+#define GPIO_CAN0_FULL_REMAP             ((uint32_t)0x001D6000U)   /*!< CAN0 full remapping */
+#define GPIO_PD01_REMAP                  ((uint32_t)0x00008000U)   /*!< PD01 remapping */
+#define GPIO_TIMER4CH3_IREMAP            ((uint32_t)0x00200001U)   /*!< TIMER4 channel3 internal remapping */
+#define GPIO_ADC0_ETRGINS_REMAP          ((uint32_t)0x00200002U)   /*!< ADC0 external trigger inserted conversion remapping */
+#define GPIO_ADC0_ETRGREG_REMAP          ((uint32_t)0x00200004U)   /*!< ADC0 external trigger regular conversion remapping */
+#define GPIO_ADC1_ETRGINS_REMAP          ((uint32_t)0x00200008U)   /*!< ADC1 external trigger inserted conversion remapping */
+#define GPIO_ADC1_ETRGREG_REMAP          ((uint32_t)0x00200010U)   /*!< ADC1 external trigger regular conversion remapping */
+#define GPIO_ENET_REMAP                  ((uint32_t)0x00200020U)   /*!< ENET remapping */
+#define GPIO_CAN1_REMAP                  ((uint32_t)0x00200040U)   /*!< CAN1 remapping */
+#define GPIO_SWJ_NONJTRST_REMAP          ((uint32_t)0x00300100U)   /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */
+#define GPIO_SWJ_SWDPENABLE_REMAP        ((uint32_t)0x00300200U)   /*!< JTAG-DP disabled and SW-DP enabled */
+#define GPIO_SWJ_DISABLE_REMAP           ((uint32_t)0x00300400U)   /*!< JTAG-DP disabled and SW-DP disabled */
+#define GPIO_SPI2_REMAP                  ((uint32_t)0x00201100U)   /*!< SPI2 remapping */
+#define GPIO_TIMER1ITI1_REMAP            ((uint32_t)0x00202000U)   /*!< TIMER1 internal trigger 1 remapping */
+#define GPIO_PTP_PPS_REMAP               ((uint32_t)0x00204000U)   /*!< ethernet PTP PPS remapping */
+#define GPIO_TIMER8_REMAP                ((uint32_t)0x80000020U)   /*!< TIMER8 remapping */
+#define GPIO_TIMER9_REMAP                ((uint32_t)0x80000040U)   /*!< TIMER9 remapping */
+#define GPIO_TIMER10_REMAP               ((uint32_t)0x80000080U)   /*!< TIMER10 remapping */
+#define GPIO_TIMER12_REMAP               ((uint32_t)0x80000100U)   /*!< TIMER12 remapping */
+#define GPIO_TIMER13_REMAP               ((uint32_t)0x80000200U)   /*!< TIMER13 remapping */
+#define GPIO_EXMC_NADV_REMAP             ((uint32_t)0x80000400U)   /*!< EXMC_NADV connect/disconnect */
+
+/* AFIO_PCF2 remap definitions */
+#define GPIO_PCF2_DCI_VSYNC_PG9_REMAP    ((uint32_t)0x00000001U)   /*!< DCI VSYNC remapped to PG9 */
+#define GPIO_PCF2_DCI_VSYNC_PI5_REMAP    ((uint32_t)0x00000003U)   /*!< DCI VSYNC remapped to PI5 */
+#define GPIO_PCF2_DCI_D0_PC6_REMAP       ((uint32_t)0x00000004U)   /*!< DCI D0 remapped to PC6 */
+#define GPIO_PCF2_DCI_D0_PH9_REMAP       ((uint32_t)0x0000000CU)   /*!< DCI D0 remapped to PH9 */
+#define GPIO_PCF2_DCI_D1_PC7_REMAP       ((uint32_t)0x00000010U)   /*!< DCI D1 remapped to PC7 */
+#define GPIO_PCF2_DCI_D1_PH10_REMAP      ((uint32_t)0x00000030U)   /*!< DCI D1 remapped to PH10 */
+#define GPIO_PCF2_DCI_D2_PE0_REMAP       ((uint32_t)0x00000040U)   /*!< DCI D2 remapped to PE0 */
+#define GPIO_PCF2_DCI_D2_PG10_REMAP      ((uint32_t)0x00000080U)   /*!< DCI D2 remapped to PG10 */
+#define GPIO_PCF2_DCI_D2_PH11_REMAP      ((uint32_t)0x000000C0U)   /*!< DCI D2 remapped to PH11 */
+#define GPIO_PCF2_DCI_D3_PE1_REMAP       ((uint32_t)0x00000100U)   /*!< DCI D3 remapped to PE1 */
+#define GPIO_PCF2_DCI_D3_PG11_REMAP      ((uint32_t)0x00000200U)   /*!< DCI D3 remapped to PG11 */
+#define GPIO_PCF2_DCI_D3_PH12_REMAP      ((uint32_t)0x00000300U)   /*!< DCI D3 remapped to PH12 */
+#define GPIO_PCF2_DCI_D4_PE4_REMAP       ((uint32_t)0x00000400U)   /*!< DCI D4 remapped to PE4 */
+#define GPIO_PCF2_DCI_D4_PH14_REMAP      ((uint32_t)0x00000C00U)   /*!< DCI D4 remapped to PH14 */
+#define GPIO_PCF2_DCI_D5_PD3_REMAP       ((uint32_t)0x00001000U)   /*!< DCI D5 remapped to PD3 */
+#define GPIO_PCF2_DCI_D5_PI4_REMAP       ((uint32_t)0x00003000U)   /*!< DCI D5 remapped to PI4 */
+#define GPIO_PCF2_DCI_D6_PE5_REMAP       ((uint32_t)0x00004000U)   /*!< DCI D6 remapped to PE5 */
+#define GPIO_PCF2_DCI_D6_PI6_REMAP       ((uint32_t)0x0000C000U)   /*!< DCI D6 remapped to PI6 */
+#define GPIO_PCF2_DCI_D7_PE6_REMAP       ((uint32_t)0x00010000U)   /*!< DCI D7 remapped to PE6 */
+#define GPIO_PCF2_DCI_D7_PI7_REMAP       ((uint32_t)0x00030000U)   /*!< DCI D7 remapped to PI7 */
+#define GPIO_PCF2_DCI_D8_PH6_REMAP       ((uint32_t)0x00040000U)   /*!< DCI D8 remapped to PH6 */
+#define GPIO_PCF2_DCI_D8_PI1_REMAP       ((uint32_t)0x000C0000U)   /*!< DCI D8 remapped to PI1 */
+#define GPIO_PCF2_DCI_D9_PH7_REMAP       ((uint32_t)0x00100000U)   /*!< DCI D9 remapped to PH7 */
+#define GPIO_PCF2_DCI_D9_PI2_REMAP       ((uint32_t)0x00300000U)   /*!< DCI D9 remapped to PI2 */
+#define GPIO_PCF2_DCI_D10_PD6_REMAP      ((uint32_t)0x00400000U)   /*!< DCI D10 remapped to PD6 */
+#define GPIO_PCF2_DCI_D10_PI3_REMAP      ((uint32_t)0x00C00000U)   /*!< DCI D10 remapped to PI3 */
+#define GPIO_PCF2_DCI_D11_PF10_REMAP     ((uint32_t)0x01000000U)   /*!< DCI D11 remapped to PF10 */
+#define GPIO_PCF2_DCI_D11_PH15_REMAP     ((uint32_t)0x03000000U)   /*!< DCI D11 remapped to PH15 */
+#define GPIO_PCF2_DCI_D12_PG6_REMAP      ((uint32_t)0x04000000U)   /*!< DCI D12 remapped to PG6 */
+#define GPIO_PCF2_DCI_D13_PG15_REMAP     ((uint32_t)0x08000000U)   /*!< DCI D12 remapped to PG15 */
+#define GPIO_PCF2_DCI_D13_PI0_REMAP      ((uint32_t)0x18000000U)   /*!< DCI D13 remapped to PI0 */
+#define GPIO_PCF2_DCI_HSYNC_PH8_REMAP    ((uint32_t)0x20000000U)   /*!< DCI HSYNC to PH8 */
+#define GPIO_PCF2_PH01_REMAP             ((uint32_t)0x80000000U)   /*!< PH0/PH1 remapping */
+
+/* AFIO_PCF3 remap definitions */
+#define GPIO_PCF3_TLI_B5_PA3_REMAP       ((uint32_t)0x00000001U)   /*!< TLI B5 remapped to PA3 */
+#define GPIO_PCF3_TLI_VSYNC_PA4_REMAP    ((uint32_t)0x00000002U)   /*!< TLI VSYNC remapped to PA4 */
+#define GPIO_PCF3_TLI_G2_PA6_REMAP       ((uint32_t)0x00000004U)   /*!< TLI G2 remapped to PA6 */
+#define GPIO_PCF3_TLI_R6_PA8_REMAP       ((uint32_t)0x00000008U)   /*!< TLI R6 remapped to PA8 */
+#define GPIO_PCF3_TLI_R4_PA11_REMAP      ((uint32_t)0x00000010U)   /*!< TLI R4 remapped to PA11 */
+#define GPIO_PCF3_TLI_R5_PA12_REMAP      ((uint32_t)0x00000020U)   /*!< TLI R5 remapped to PA12 */
+#define GPIO_PCF3_TLI_R3_PB0_REMAP       ((uint32_t)0x00000040U)   /*!< TLI R3 remapped to PB0 */
+#define GPIO_PCF3_TLI_R6_PB1_REMAP       ((uint32_t)0x00000080U)   /*!< TLI R6 remapped to PB1 */
+#define GPIO_PCF3_TLI_B6_PB8_REMAP       ((uint32_t)0x00000100U)   /*!< TLI B6 remapped to PB8 */
+#define GPIO_PCF3_TLI_B7_PB9_REMAP       ((uint32_t)0x00000200U)   /*!< TLI B7 remapped to PB9 */
+#define GPIO_PCF3_TLI_G4_PB10_REMAP      ((uint32_t)0x00000400U)   /*!< TLI G4 remapped to PB10 */
+#define GPIO_PCF3_TLI_G5_PB11_REMAP      ((uint32_t)0x00000800U)   /*!< TLI G5 remapped to PB11 */
+#define GPIO_PCF3_TLI_HSYNC_PC6_REMAP    ((uint32_t)0x00001000U)   /*!< TLI HSYNC remapped to PC6 */
+#define GPIO_PCF3_TLI_G6_PC7_REMAP       ((uint32_t)0x00002000U)   /*!< TLI G6 remapped to PC7 */
+#define GPIO_PCF3_TLI_R2_PC10_REMAP      ((uint32_t)0x00004000U)   /*!< TLI R2 remapped to PC10 */
+#define GPIO_PCF3_TLI_G7_PD3_REMAP       ((uint32_t)0x00008000U)   /*!< TLI G7 remapped to PD3 */
+#define GPIO_PCF3_TLI_B2_PD6_REMAP       ((uint32_t)0x00010000U)   /*!< TLI B2 remapped to PD6 */
+#define GPIO_PCF3_TLI_B3_PD10_REMAP      ((uint32_t)0x00020000U)   /*!< TLI B3 remapped to PD10 */
+#define GPIO_PCF3_TLI_B0_PE4_REMAP       ((uint32_t)0x00040000U)   /*!< TLI B0 remapped to PE4 */
+#define GPIO_PCF3_TLI_G0_PE5_REMAP       ((uint32_t)0x00080000U)   /*!< TLI G0 remapped to PE5 */
+#define GPIO_PCF3_TLI_G1_PE6_REMAP       ((uint32_t)0x00100000U)   /*!< TLI G1 remapped to PE6 */
+#define GPIO_PCF3_TLI_G3_PE11_REMAP      ((uint32_t)0x00200000U)   /*!< TLI G3 remapped to PE11 */
+#define GPIO_PCF3_TLI_B4_PE12_REMAP      ((uint32_t)0x00400000U)   /*!< TLI B4 remapped to PE12 */
+#define GPIO_PCF3_TLI_DE_PE13_REMAP      ((uint32_t)0x00800000U)   /*!< TLI DE remapped to PE13 */
+#define GPIO_PCF3_TLI_CLK_PE14_REMAP     ((uint32_t)0x01000000U)   /*!< TLI CLK remapped to PE14 */
+#define GPIO_PCF3_TLI_R7_PE15_REMAP      ((uint32_t)0x02000000U)   /*!< TLI R7 remapped to PE15 */
+#define GPIO_PCF3_TLI_DE_PF10_REMAP      ((uint32_t)0x04000000U)   /*!< TLI DE remapped to PF10 */
+#define GPIO_PCF3_TLI_R7_PG6_REMAP       ((uint32_t)0x08000000U)   /*!< TLI R7 remapped to PG6 */
+#define GPIO_PCF3_TLI_CLK_PG7_REMAP      ((uint32_t)0x10000000U)   /*!< TLI CLK remapped to PG7 */
+#define GPIO_PCF3_TLI_G3_PG10_REMAP      ((uint32_t)0x20000000U)   /*!< TLI G3 remapped to PG10 */
+#define GPIO_PCF3_TLI_B2_PG10_REMAP      ((uint32_t)0x40000000U)   /*!< TLI B2 remapped to PG10 */
+#define GPIO_PCF3_TLI_B3_PG11_REMAP      ((uint32_t)0x80000000U)   /*!< TLI B3 remapped to PG11 */
+
+/* AFIO_PCF4 remap definitions */
+#define GPIO_PCF4_TLI_B4_PG12_REMAP      ((uint32_t)0x00000001U)   /*!< TLI B4 remapped to PG12 */
+#define GPIO_PCF4_TLI_B1_PG12_REMAP      ((uint32_t)0x00000002U)   /*!< TLI B1 remapped to PG12 */
+#define GPIO_PCF4_TLI_R0_PH2_REMAP2      ((uint32_t)0x00000004U)   /*!< TLI R0 remapped to PH2 */
+#define GPIO_PCF4_TLI_R1_PH3_REMAP       ((uint32_t)0x00000008U)   /*!< TLI R1 remapped to PH3 */
+#define GPIO_PCF4_TLI_R2_PH8_REMAP       ((uint32_t)0x00000010U)   /*!< TLI R2 remapped to PH8 */
+#define GPIO_PCF4_TLI_R3_PH9_REMAP       ((uint32_t)0x00000020U)   /*!< TLI R3 remapped to PH9 */
+#define GPIO_PCF4_TLI_R4_PH10_REMAP      ((uint32_t)0x00000040U)   /*!< TLI R4 remapped to PH10 */
+#define GPIO_PCF4_TLI_R5_PH11_REMAP      ((uint32_t)0x00000080U)   /*!< TLI R5 remapped to PH11 */
+#define GPIO_PCF4_TLI_R6_PH12_REMAP      ((uint32_t)0x00000100U)   /*!< TLI R6 remapped to PH12 */
+#define GPIO_PCF4_TLI_G2_PH13_REMAP      ((uint32_t)0x00000200U)   /*!< TLI G2 remapped to PH13 */
+#define GPIO_PCF4_TLI_G3_PH14_REMAP      ((uint32_t)0x00000400U)   /*!< TLI G3 remapped to PH14 */
+#define GPIO_PCF4_TLI_G4_PH15_REMAP      ((uint32_t)0x00000800U)   /*!< TLI G4 remapped to PH15 */
+#define GPIO_PCF4_TLI_G5_PI0_REMAP       ((uint32_t)0x00001000U)   /*!< TLI G5 remapped to PI0 */
+#define GPIO_PCF4_TLI_G6_PI1_REMAP       ((uint32_t)0x00002000U)   /*!< TLI G6 remapped to PI1 */
+#define GPIO_PCF4_TLI_G7_PI2_REMAP       ((uint32_t)0x00004000U)   /*!< TLI G7 remapped to PI2 */
+#define GPIO_PCF4_TLI_B4_PI4_REMAP       ((uint32_t)0x00008000U)   /*!< TLI B4 remapped to PI4 */
+#define GPIO_PCF4_TLI_B5_PI5_REMAP       ((uint32_t)0x00010000U)   /*!< TLI B5 remapped to PI5 */
+#define GPIO_PCF4_TLI_B6_PI6_REMAP       ((uint32_t)0x00020000U)   /*!< TLI B6 remapped to PI6 */
+#define GPIO_PCF4_TLI_B7_PI7_REMAP       ((uint32_t)0x00040000U)   /*!< TLI B7 remapped to PI7 */
+#define GPIO_PCF4_TLI_VSYNC_PI9_REMAP    ((uint32_t)0x00080000U)   /*!< TLI VSYNC remapped to PI9 */
+#define GPIO_PCF4_TLI_HSYNC_PI10_REMAP   ((uint32_t)0x00100000U)   /*!< TLI HSYNC remapped to PI10 */
+#define GPIO_PCF4_TLI_R0_PH4_REMAP       ((uint32_t)0x00200000U)   /*!< TLI R0 remapped to PH4 */
+#define GPIO_PCF4_TLI_R1_PI3_REMAP       ((uint32_t)0x00400000U)   /*!< TLI R1 remapped to PI3 */
+#define GPIO_PCF4_SPI1_SCK_PD3_REMAP     ((uint32_t)0x00800000U)   /*!< SPI1 SCK remapped to PD3 */
+#define GPIO_PCF4_SPI2_MOSI_PD6_REMAP    ((uint32_t)0x01000000U)   /*!< SPI2 MOSI remapped to PD6 */
+
+/* AFIO_PCF5 remap definitions */
+#define GPIO_PCF5_I2C2_REMAP0            ((uint32_t)0x00000001U)   /*!< I2C2 remapping 0 */
+#define GPIO_PCF5_I2C2_REMAP1            ((uint32_t)0x00000002U)   /*!< I2C2 remapping 1 */
+#define GPIO_PCF5_TIMER1_CH0_REMAP       ((uint32_t)0x00000004U)   /*!< TIMER1 CH0 remapped to PA5 */
+#define GPIO_PCF5_TIMER4_REMAP           ((uint32_t)0x00000008U)   /*!< TIMER4 CH0 remapping */
+#define GPIO_PCF5_TIMER7_CHON_REMAP0     ((uint32_t)0x00000020U)   /*!< TIMER7 CHON remapping 0 */
+#define GPIO_PCF5_TIMER7_CHON_REMAP1     ((uint32_t)0x00000030U)   /*!< TIMER7 CHON remapping 1 */
+#define GPIO_PCF5_TIMER7_CH_REMAP        ((uint32_t)0x00000040U)   /*!< TIMER7 CH remapping */
+#define GPIO_PCF5_I2C1_REMAP0            ((uint32_t)0x00000100U)   /*!< I2C1 remapping 0 */
+#define GPIO_PCF5_I2C1_REMAP1            ((uint32_t)0x00000180U)   /*!< I2C1 remapping 1 */
+#define GPIO_PCF5_SPI1_NSCK_REMAP0       ((uint32_t)0x00000400U)   /*!< SPI1 NSS/SCK remapping 0 */
+#define GPIO_PCF5_SPI1_NSCK_REMAP1       ((uint32_t)0x00000600U)   /*!< SPI1 NSS/SCK remapping 1 */
+#define GPIO_PCF5_SPI1_IO_REMAP0         ((uint32_t)0x00000800U)   /*!< SPI1 MISO/MOSI remapping 0 */
+#define GPIO_PCF5_SPI1_IO_REMAP1         ((uint32_t)0x00001800U)   /*!< SPI1 MISO/MOSI remapping 1 */
+#define GPIO_PCF5_UART3_REMAP            ((uint32_t)0x00002000U)   /*!< UART3 remapping */
+#define GPIO_PCF5_TIMER11_REMAP          ((uint32_t)0x00004000U)   /*!< TIMER11 remapping */
+#define GPIO_PCF5_CAN0_ADD_REMAP         ((uint32_t)0x00008000U)   /*!< CAN0 addition remapping */
+#define GPIO_PCF5_ENET_TXD3_REMAP        ((uint32_t)0x00010000U)   /*!< ETH_TXD3 remapped to PE2 */
+#define GPIO_PCF5_PPS_HI_REMAP           ((uint32_t)0x00020000U)   /*!< ETH_PPS_OUT remapped to PG8 */
+#define GPIO_PCF5_ENET_TXD01_REMAP       ((uint32_t)0x00040000U)   /*!< ETH_TX_EN/ETH_TXD0/ETH_TXD1 remapping */
+#define GPIO_PCF5_ENET_CRSCOL_REMAP      ((uint32_t)0x00080000U)   /*!< ETH_MII_CRS/ETH_MII_COL remapping */
+#define GPIO_PCF5_ENET_RX_HI_REMAP       ((uint32_t)0x00100000U)   /*!< ETH_RXD2/ETH_RXD3/ETH_RX_ER remapping */
+#define GPIO_PCF5_UART6_REMAP            ((uint32_t)0x00200000U)   /*!< UART6 remapping */
+#define GPIO_PCF5_USART5_CK_PG7_REMAP    ((uint32_t)0x00400000U)   /*!< USART5 CK remapped to PG7 */
+#define GPIO_PCF5_USART5_RTS_PG12_REMAP  ((uint32_t)0x00800000U)   /*!< USART5 RTS remapped to PG12 */
+#define GPIO_PCF5_USART5_CTS_PG13_REMAP  ((uint32_t)0x01000000U)   /*!< USART5 CTS remapped to PG13 */
+#define GPIO_PCF5_USART5_TX_PG14_REMAP   ((uint32_t)0x02000000U)   /*!< USART5 TX remapped to PG14 */
+#define GPIO_PCF5_USART5_RX_PG9_REMAP    ((uint32_t)0x04000000U)   /*!< USART5 RX remapped to PG9 */
+#define GPIO_PCF5_EXMC_SDNWE_PC0_REMAP   ((uint32_t)0x08000000U)   /*!< EXMC SDNWE remapped to PC0 */
+#define GPIO_PCF5_EXMC_SDCKE0_PC3_REMAP  ((uint32_t)0x10000000U)   /*!< EXMC SDCKE0 remapped to PC3 */
+#define GPIO_PCF5_EXMC_SDCKE1_PB5_REMAP  ((uint32_t)0x20000000U)   /*!< EXMC SDCKE1 remapped to PB5 */
+#define GPIO_PCF5_EXMC_SDNE0_PC2_REMAP   ((uint32_t)0x40000000U)   /*!< EXMC SDNE0 remapped to PC2 */
+#define GPIO_PCF5_EXMC_SDNE1_PB6_REMAP   ((uint32_t)0x80000000U)   /*!< EXMC SDNE1 remapped to PB6 */
+
+/* AFIO port configuration register selection */
+#define GPIO_PCF2                        ((uint8_t)0x02U)          /*!< AFIO port configuration register 2 */
+#define GPIO_PCF3                        ((uint8_t)0x03U)          /*!< AFIO port configuration register 3 */
+#define GPIO_PCF4                        ((uint8_t)0x04U)          /*!< AFIO port configuration register 4 */
+#define GPIO_PCF5                        ((uint8_t)0x05U)          /*!< AFIO port configuration register 5*/
+
+/* ethernet MII or RMII PHY selection */
+#define GPIO_ENET_PHY_MII                ((uint32_t)0x00000000U)   /*!< configure ethernet MAC for connection with an MII PHY */
+#define GPIO_ENET_PHY_RMII               AFIO_PCF0_ENET_PHY_SEL    /*!< configure ethernet MAC for connection with an RMII PHY */
+
+/* function declarations */
+/* initialization functions */
+/* reset GPIO port */
+void gpio_deinit(uint32_t gpio_periph);
+/* reset alternate function I/O(AFIO) */
+void gpio_afio_deinit(void);
+/* GPIO parameter initialization */
+void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin);
+
+/* function configuration */
+/* set GPIO pin bit */
+void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
+/* reset GPIO pin bit */
+void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
+/* write data to the specified GPIO pin */
+void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
+/* write data to the specified GPIO port */
+void gpio_port_write(uint32_t gpio_periph, uint16_t data);
+
+/* get GPIO pin input status */
+FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
+/* get GPIO port input status */
+uint16_t gpio_input_port_get(uint32_t gpio_periph);
+/* get GPIO pin output status */
+FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
+/* get GPIO port output status */
+uint16_t gpio_output_port_get(uint32_t gpio_periph);
+
+/* configure GPIO pin remap */
+void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue);
+/* configure GPIO pin remap1 */
+void gpio_pin_remap1_config(uint8_t remap_reg, uint32_t remap, ControlStatus newvalue);
+
+/* select GPIO pin exti sources */
+void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin);
+/* configure GPIO pin event output */
+void gpio_event_output_config(uint8_t output_port, uint8_t output_pin);
+/* enable GPIO pin event output */
+void gpio_event_output_enable(void);
+/* disable GPIO pin event output */
+void gpio_event_output_disable(void);
+
+/* lock GPIO pin bit */
+void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
+
+/* select ethernet MII or RMII PHY */
+void gpio_ethernet_phy_select(uint32_t enet_sel);
+
+#endif /* GD32F20X_GPIO_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_hau.h

@@ -0,0 +1,209 @@
+/*!
+    \file  gd32f20x_hau.h
+    \brief definitions for the HAU
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_HAU_H
+#define GD32F20X_HAU_H
+
+#include "gd32f20x.h"
+
+/* HAU definitions */
+#define HAU                        HAU_BASE
+
+/* registers definitions */
+#define HAU_CTL                    REG32(HAU + 0x00U)        /*!< control register  */
+#define HAU_DI                     REG32(HAU + 0x04U)        /*!< data input register */ 
+#define HAU_CFG                    REG32(HAU + 0x08U)        /*!< configuration register */
+#define HAU_DO0                    REG32(HAU + 0x0CU)        /*!< data output register 0 */
+#define HAU_DO1                    REG32(HAU + 0x10U)        /*!< data output register 1 */
+#define HAU_DO2                    REG32(HAU + 0x14U)        /*!< data output register 2 */
+#define HAU_DO3                    REG32(HAU + 0x18U)        /*!< data output register 3 */
+#define HAU_DO4                    REG32(HAU + 0x1CU)        /*!< data output register 4 */
+#define HAU_DO5                    REG32(HAU + 0x324U)       /*!< data output register 5 */
+#define HAU_DO6                    REG32(HAU + 0x328U)       /*!< data output register 6 */
+#define HAU_DO7                    REG32(HAU + 0x32CU)       /*!< data output register 7 */
+#define HAU_INTEN                  REG32(HAU + 0x20U)        /*!< interrupt enable register */
+#define HAU_STAT                   REG32(HAU + 0x24U)        /*!< status and interrupt flag register */
+
+/* bits definitions */
+/* HAU_CTL */
+#define HAU_CTL_START              BIT(2)                    /*!< set to 1 to reset the HAU processor core, so that it is ready to start the digest calculation */
+#define HAU_CTL_DMAE               BIT(3)                    /*!< DMA enable */
+#define HAU_CTL_DATAM              BITS(4,5)                 /*!< data type mode */
+#define HAU_CTL_HMS                BIT(6)                    /*!< HAU mode selection */
+#define HAU_CTL_ALGM_0             BIT(7)                    /*!< algorithm selection bit 0 */
+#define HAU_CTL_NWIF               BITS(8,11)                /*!< number of words in the input FIFO */
+#define HAU_CTL_DINE               BIT(12)                   /*!< DI register not empty */
+#define HAU_CTL_MDS                BIT(13)                   /*!< multiple DMA selection */
+#define HAU_CTL_KLM                BIT(16)                   /*!< key length mode */
+#define HAU_CTL_ALGM_1             BIT(18)                   /*!< algorithm selection bit 1 */
+
+/* HAU_DI */
+#define HAU_DI_DI                  BITS(0,31)                /*!< message data input */
+
+/* HAU_CFG */
+#define HAU_CFG_VBL                BITS(0,4)                 /*!< valid bits length in the last word */
+#define HAU_CFG_CALEN              BIT(8)                    /*!< digest calculation enable */
+
+/* HAU_DOx x=0..7 */
+#define HAU_DOX_DOX                BITS(0,31)                /*!< message digest result of hash algorithm */
+
+/* HAU_INTEN */
+#define HAU_INTEN_DIIE             BIT(0)                    /*!< data input interrupt enable */
+#define HAU_INTEN_CCIE             BIT(1)                    /*!< calculation completion interrupt enable */
+
+/* HAU_STAT */
+#define HAU_STAT_DINT              BIT(0)                    /*!< data input interrupt flag */
+#define HAU_STAT_CINT              BIT(1)                    /*!< digest calculation completion interrupt flag */
+#define HAU_STAT_DMAS              BIT(2)                    /*!< DMA status */
+#define HAU_STAT_BUSY              BIT(3)                    /*!< busy bit */
+
+/* constants definitions */
+/* structure for initialization of the hau */ 
+typedef struct
+{
+    uint32_t algo;      /*!< algorithm selection */
+    uint32_t mode;      /*!< HAU mode selection */
+    uint32_t datatype;  /*!< data type mode */
+    uint32_t keytype;   /*!< key length mode */
+}hau_init_parameter_struct;
+
+/* structure for message digest result of the hau */
+typedef struct
+{
+    uint32_t out[8];     /* message digest result 0-7 */
+}hau_digest_parameter_struct; 
+
+/* hau_ctl register value */ 
+#define HAU_ALGO_SHA1                     ((uint32_t)0x00000000U)                        /*!< HAU function is SHA1 */
+#define HAU_ALGO_SHA224                   HAU_CTL_ALGM_1                                 /*!< HAU function is SHA224 */
+#define HAU_ALGO_SHA256                   (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0)              /*!< HAU function is SHA256 */
+#define HAU_ALGO_MD5                      HAU_CTL_ALGM_0                                 /*!< HAU function is MD5 */
+
+#define HAU_MODE_HASH                     ((uint32_t)0x00000000U)                        /*!< HAU mode is HASH */ 
+#define HAU_MODE_HMAC                     HAU_CTL_HMS                                    /*!< HAU mode is HMAC */
+
+#define CTL_DATAM_1(regval)               (BITS(4,5) & ((uint32_t)(regval) << 4))        /*!< write value to HAU_CTL_DATAM bit field */
+#define HAU_SWAPPING_32BIT                CTL_DATAM_1(0)                                 /*!< no swapping */
+#define HAU_SWAPPING_16BIT                CTL_DATAM_1(1)                                 /*!< half-word swapping */
+#define HAU_SWAPPING_8BIT                 CTL_DATAM_1(2)                                 /*!< bytes swapping */
+#define HAU_SWAPPING_1BIT                 CTL_DATAM_1(3)                                 /*!< bit swapping */
+
+#define HAU_KEY_SHORTER_64                ((uint32_t)0x00000000U)                        /*!< HMAC key is <= 64 bytes */
+#define HAU_KEY_LONGGER_64                HAU_CTL_KLM                                    /*!< HMAC key is > 64 bytes  */
+
+#define GET_CTL_NWIF(regval)              GET_BITS((regval),8,11)                        /*!< get value of HAU_CTL_NWIF bit field */
+
+#define SINGLE_DMA_AUTO_DIGEST            ((uint32_t)0x00000000U)                        /*!< message padding and message digest calculation at the end of a DMA transfer */
+#define MULTIPLE_DMA_NO_DIGEST            HAU_CTL_MDS                                    /*!< multiple DMA transfers needed and CALEN bit is not automatically set at the end of a DMA transfer */
+
+/* hau_cfg register value */
+#define CFG_VBL(regval)                   (BITS(0,4) & ((regval) << 0))                  /*!< write value to HAU_CFG_VBL bit field */
+
+/* hau_inten register value */
+#define HAU_INT_DATA_INPUT                HAU_INTEN_DIIE                                 /*!< a new block can be entered into the IN buffer */
+#define HAU_INT_CALCULATION_COMPLETE      HAU_INTEN_CCIE                                 /*!< calculation complete */
+
+#define HAU_FLAG_DATA_INPUT               HAU_STAT_DINT                                  /*!< there is enough space (16 bytes) in the input FIFO */
+#define HAU_FLAG_CALCULATION_COMPLETE     HAU_STAT_CINT                                  /*!< digest calculation is completed */
+#define HAU_FLAG_DMA                      HAU_STAT_DMAS                                  /*!< DMA is enabled (DMAE =1) or a transfer is processing */
+#define HAU_FLAG_BUSY                     HAU_STAT_BUSY                                  /*!< data block is in process */
+#define HAU_FLAG_INFIFO_NO_EMPTY          HAU_CTL_DINE                                   /*!< the input FIFO is not empty */                         
+
+#define HAU_INT_FLAG_DATA_INPUT           HAU_STAT_DINT                                  /*!< there is enough space (16 bytes) in the input FIFO */
+#define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CINT                                  /*!< digest calculation is completed */
+
+/* function declarations */
+/* initialization functions */
+/* reset the HAU peripheral */
+void hau_deinit(void);
+/* initialize the HAU peripheral parameters */
+void hau_init(hau_init_parameter_struct* initpara);
+/* initialize the structure hau_initpara */
+void hau_init_parameter_init(hau_init_parameter_struct* initpara);
+/* reset the HAU processor core */
+void hau_reset(void);
+/* configure the number of valid bits in last word of the message */
+void hau_last_word_validbits_num_config(uint32_t valid_num);
+/* write data to the IN FIFO */
+void hau_data_write(uint32_t data);
+/* return the number of words already written into the IN FIFO */
+uint32_t hau_infifo_words_num_get(void);
+/* read the message digest result */
+void hau_digest_read(hau_digest_parameter_struct* digestpara);
+/* enable digest calculation */
+void hau_digest_calculation_enable(void);
+/* configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not */
+void hau_multiple_single_dma_config(uint32_t multi_single);
+/* enable the HAU DMA interface */
+void hau_dma_enable(void);
+/* disable the HAU DMA interface */
+void hau_dma_disable(void);
+
+/* calculate digest in HASH mode */
+/* calculate digest using SHA1 in HASH mode */
+ErrStatus hau_hash_sha_1(uint8_t *input, uint32_t in_length, uint8_t output[20]);
+/* calculate digest using SHA1 in HMAC mode */
+ErrStatus hau_hmac_sha_1(uint8_t *key, uint32_t keysize, uint8_t *input, uint32_t in_length, uint8_t output[20]);
+/* calculate digest using SHA224 in HASH mode */
+ErrStatus hau_hash_sha_224(uint8_t *input, uint32_t in_length, uint8_t output[28]);
+/* calculate digest using SHA224 in HMAC mode */
+ErrStatus hau_hmac_sha_224(uint8_t *key, uint32_t keysize, uint8_t *input, uint32_t in_length, uint8_t output[28]);
+/* calculate digest using SHA256 in HASH mode */
+ErrStatus hau_hash_sha_256(uint8_t *input, uint32_t in_length, uint8_t output[32]);
+/* calculate digest using SHA256 in HMAC mode */
+ErrStatus hau_hmac_sha_256(uint8_t *key, uint32_t keysize, uint8_t *input, uint32_t in_length, uint8_t output[32]);
+/* calculate digest using MD5 in HASH mode */
+ErrStatus hau_hash_md5(uint8_t *input, uint32_t in_length, uint8_t output[16]);
+/* calculate digest using MD5 in HMAC mode */
+ErrStatus hau_hmac_md5(uint8_t *key, uint32_t keysize, uint8_t *input, uint32_t in_length, uint8_t output[16]);
+
+/* interrupt & flag functions */
+/* get the HAU flag status */
+FlagStatus hau_flag_get(uint32_t flag);
+/* clear the HAU flag status */
+void hau_flag_clear(uint32_t flag);
+/* enable the HAU interrupts */
+void hau_interrupt_enable(uint32_t interrupt);
+/* disable the HAU interrupts */
+void hau_interrupt_disable(uint32_t interrupt);
+/* get the HAU interrupt flag status */
+FlagStatus hau_interrupt_flag_get(uint32_t int_flag);
+/* clear the HAU interrupt flag status */
+void hau_interrupt_flag_clear(uint32_t int_flag);
+
+#endif /*GD32F20X_HAU_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_i2c.h

@@ -0,0 +1,350 @@
+/*!
+    \file  gd32f20x_i2c.h
+    \brief definitions for the I2C
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_I2C_H
+#define GD32F20X_I2C_H
+
+#include "gd32f20x.h"
+
+/* I2Cx(x=0,1,2) definitions */
+#define I2C0                          I2C_BASE                   /*!< I2C0 base address */
+#define I2C1                          (I2C_BASE + 0x00000400U)   /*!< I2C1 base address */
+#define I2C2                          (I2C_BASE + 0x00006C00U)   /*!< I2C2 base address */
+
+/* registers definitions */
+#define I2C_CTL0(i2cx)                REG32((i2cx) + 0x00U)      /*!< I2C control register 0 */
+#define I2C_CTL1(i2cx)                REG32((i2cx) + 0x04U)      /*!< I2C control register 1 */
+#define I2C_SADDR0(i2cx)              REG32((i2cx) + 0x08U)      /*!< I2C slave address register 0*/
+#define I2C_SADDR1(i2cx)              REG32((i2cx) + 0x0CU)      /*!< I2C slave address register */
+#define I2C_DATA(i2cx)                REG32((i2cx) + 0x10U)      /*!< I2C transfer buffer register */
+#define I2C_STAT0(i2cx)               REG32((i2cx) + 0x14U)      /*!< I2C transfer status register 0 */
+#define I2C_STAT1(i2cx)               REG32((i2cx) + 0x18U)      /*!< I2C transfer status register */
+#define I2C_CKCFG(i2cx)               REG32((i2cx) + 0x1CU)      /*!< I2C clock configure register */
+#define I2C_RT(i2cx)                  REG32((i2cx) + 0x20U)      /*!< I2C rise time register */
+
+/* bits definitions */
+/* I2Cx_CTL0 */
+#define I2C_CTL0_I2CEN                BIT(0)        /*!< peripheral enable */
+#define I2C_CTL0_SMBEN                BIT(1)        /*!< SMBus mode */
+#define I2C_CTL0_SMBSEL               BIT(3)        /*!< SMBus type */
+#define I2C_CTL0_ARPEN                BIT(4)        /*!< ARP enable */
+#define I2C_CTL0_PECEN                BIT(5)        /*!< PEC enable */
+#define I2C_CTL0_GCEN                 BIT(6)        /*!< general call enable */
+#define I2C_CTL0_DISSTRC              BIT(7)        /*!< clock stretching disable (slave mode) */
+#define I2C_CTL0_START                BIT(8)        /*!< start generation */
+#define I2C_CTL0_STOP                 BIT(9)        /*!< stop generation */
+#define I2C_CTL0_ACKEN                BIT(10)       /*!< acknowledge enable */
+#define I2C_CTL0_POAP                 BIT(11)       /*!< acknowledge/PEC position (for data reception) */
+#define I2C_CTL0_PECTRANS             BIT(12)       /*!< packet error checking */
+#define I2C_CTL0_SALT                 BIT(13)       /*!< SMBus alert */
+#define I2C_CTL0_SRESET               BIT(15)       /*!< software reset */
+
+/* I2Cx_CTL1 */
+#define I2C_CTL1_I2CCLK               BITS(0,5)     /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
+#define I2C_CTL1_ERRIE                BIT(8)        /*!< error interrupt enable */
+#define I2C_CTL1_EVIE                 BIT(9)        /*!< event interrupt enable */
+#define I2C_CTL1_BUFIE                BIT(10)       /*!< buffer interrupt enable */
+#define I2C_CTL1_DMAON                BIT(11)       /*!< DMA requests enable */
+#define I2C_CTL1_DMALST               BIT(12)       /*!< DMA last transfer */
+
+/* I2Cx_SADDR0 */
+#define I2C_SADDR0_ADDRESS0           BIT(0)        /*!< bit 0 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS            BITS(1,7)     /*!< 7-bit address or bits 7:1 of a 10-bit address */
+#define I2C_SADDR0_ADDRESS_H          BITS(8,9)     /*!< highest two bits of a 10-bit address */
+#define I2C_SADDR0_ADDFORMAT          BIT(15)       /*!< address mode for the I2C slave */
+
+/* I2Cx_SADDR1 */
+#define I2C_SADDR1_DUADEN             BIT(0)        /*!< aual-address mode switch */
+#define I2C_SADDR1_ADDRESS2           BITS(1,7)     /*!< second I2C address for the slave in dual-address mode */
+
+/* I2Cx_DATA */
+#define I2C_DATA_TRB                  BITS(0,7)     /*!< 8-bit data register */
+
+/* I2Cx_STAT0 */
+#define I2C_STAT0_SBSEND              BIT(0)        /*!< start bit (master mode) */
+#define I2C_STAT0_ADDSEND             BIT(1)        /*!< address sent (master mode)/matched (slave mode) */
+#define I2C_STAT0_BTC                 BIT(2)        /*!< byte transfer finished */
+#define I2C_STAT0_ADD10SEND           BIT(3)        /*!< 10-bit header sent (master mode) */
+#define I2C_STAT0_STPDET              BIT(4)        /*!< stop detection (slave mode) */
+#define I2C_STAT0_RBNE                BIT(6)        /*!< data register not empty (receivers) */
+#define I2C_STAT0_TBE                 BIT(7)        /*!< data register empty (transmitters) */
+#define I2C_STAT0_BERR                BIT(8)        /*!< bus error */
+#define I2C_STAT0_LOSTARB             BIT(9)        /*!< arbitration lost (master mode) */
+#define I2C_STAT0_AERR                BIT(10)       /*!< acknowledge failure */
+#define I2C_STAT0_OUERR               BIT(11)       /*!< overrun/underrun */
+#define I2C_STAT0_PECERR              BIT(12)       /*!< PEC error in reception */
+#define I2C_STAT0_SMBTO               BIT(14)       /*!< timeout signal in SMBus mode */
+#define I2C_STAT0_SMBALT              BIT(15)       /*!< SMBus alert status */
+
+/* I2Cx_STAT1 */
+#define I2C_STAT1_MASTER              BIT(0)        /*!< master/slave */
+#define I2C_STAT1_I2CBSY              BIT(1)        /*!< bus busy */
+#define I2C_STAT1_TRS                 BIT(2)        /*!< transmitter/receiver */
+#define I2C_STAT1_RXGC                BIT(4)        /*!< general call address (slave mode) */
+#define I2C_STAT1_DEFSMB              BIT(5)        /*!< SMBus device default address (slave mode) */
+#define I2C_STAT1_HSTSMB              BIT(6)        /*!< SMBus host header (slave mode) */
+#define I2C_STAT1_DUMODF              BIT(7)        /*!< dual flag (slave mode) */
+#define I2C_STAT1_ECV                 BITS(8,15)    /*!< packet error checking register */
+
+/* I2Cx_CKCFG */
+#define I2C_CKCFG_CLKC                BITS(0,11)    /*!< clock control register in fast/standard mode (master mode) */
+#define I2C_CKCFG_DTCY                BIT(14)       /*!< fast mode duty cycle */
+#define I2C_CKCFG_FAST                BIT(15)       /*!< I2C speed selection in master mode */
+
+/* I2Cx_RT */
+#define I2C_RT_RISETIME               BITS(0,5)     /*!< maximum rise time in fast/standard mode (Master mode) */
+
+/* constants definitions */
+/* define the I2C bit position and its register index offset */
+#define I2C_REGIDX_BIT(regidx, bitpos)  (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define I2C_REG_VAL(i2cx, offset)       (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
+#define I2C_BIT_POS(val)                ((uint32_t)(val) & 0x1FU)
+#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+                                                              | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define I2C_REG_VAL2(i2cx, offset)      (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
+#define I2C_BIT_POS2(val)               (((uint32_t)(val) & 0x1F0000U) >> 16)
+
+/* register offset */
+#define I2C_CTL1_REG_OFFSET           0x04U         /*!< CTL1 register offset */
+#define I2C_STAT0_REG_OFFSET          0x14U         /*!< STAT0 register offset */
+#define I2C_STAT1_REG_OFFSET          0x18U         /*!< STAT1 register offset */
+#define I2C_SAMCS_REG_OFFSET          0x80U         /*!< SAMCS register offset */
+
+/* I2C flags */
+typedef enum
+{
+    /* flags in STAT0 register */
+    I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U),                /*!< start condition sent out in master mode */
+    I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U),               /*!< address is sent in master mode or received and matches in slave mode */
+    I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U),                   /*!< byte transmission finishes */
+    I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U),             /*!< header of 10-bit address is sent in master mode */
+    I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U),                /*!< stop condition detected in slave mode */
+    I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U),                  /*!< I2C_DATA is not Empty during receiving */
+    I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U),                   /*!< I2C_DATA is empty during transmitting */
+    I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U),                  /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
+    I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U),               /*!< arbitration lost in master mode */
+    I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U),                 /*!< acknowledge error */
+    I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U),                /*!< over-run or under-run situation occurs in slave mode */
+    I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U),               /*!< PEC error when receiving data */
+    I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U),                /*!< timeout signal in SMBus mode */
+    I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U),               /*!< SMBus alert status */
+    /* flags in STAT1 register */
+    I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U),                /*!< a flag indicating whether I2C block is in master or slave mode */
+    I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U),                /*!< busy flag */
+    I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U),                   /*!< whether the I2C is a transmitter or a receiver */
+    I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U),                  /*!< general call address (00h) received */
+    I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U),                /*!< default address of SMBus device */
+    I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U),                /*!< SMBus host header detected in slave mode */
+    I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U),                 /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
+}i2c_flag_enum;
+
+/* I2C interrupt flags */
+typedef enum
+{
+    /* interrupt flags in CTL1 register */
+    I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U),        /*!< start condition sent out in master mode interrupt flag */
+    I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U),       /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
+    I2C_INT_FLAG_BTC =  I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U),          /*!< byte transmission finishes */
+    I2C_INT_FLAG_ADD10SEND =  I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U),    /*!< header of 10-bit address is sent in master mode interrupt flag */
+    I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U),        /*!< stop condition detected in slave mode interrupt flag */
+    I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U),          /*!< I2C_DATA is not Empty during receiving interrupt flag */
+    I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U),           /*!< I2C_DATA is empty during transmitting interrupt flag */    
+    I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U),          /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
+    I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U),       /*!< arbitration lost in master mode interrupt flag */
+    I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U),         /*!< acknowledge error interrupt flag */
+    I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U),        /*!< over-run or under-run situation occurs in slave mode interrupt flag */
+    I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U),       /*!< PEC error when receiving data interrupt flag */
+    I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U),        /*!< timeout signal in SMBus mode interrupt flag */
+    I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U),       /*!< SMBus Alert status interrupt flag */
+}i2c_interrupt_flag_enum;
+
+/* I2C interrupt enable or disable */
+typedef enum
+{
+    /* interrupt in CTL1 register */
+    I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U),                     /*!< error interrupt enable */
+    I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U),                      /*!< event interrupt enable */
+    I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U),                    /*!< buffer interrupt enable */
+}i2c_interrupt_enum;
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_I2CMODE_ENABLE            ((uint32_t)0x00000000U)                  /*!< I2C mode */
+#define I2C_SMBUSMODE_ENABLE          I2C_CTL0_SMBEN                           /*!< SMBus mode */
+
+/* SMBus/I2C mode switch and SMBus type selection */
+#define I2C_SMBUS_DEVICE              ((uint32_t)0x00000000U)                  /*!< SMBus mode device type */
+#define I2C_SMBUS_HOST                I2C_CTL0_SMBSEL                          /*!< SMBus mode host type */
+
+/* I2C transfer direction */
+#define I2C_RECEIVER                  ((uint32_t)0x00000001U)                  /*!< receiver */
+#define I2C_TRANSMITTER               ((uint32_t)0xFFFFFFFEU)                  /*!< transmitter */
+
+/* whether or not to send an ACK */
+#define I2C_ACK_DISABLE               ((uint32_t)0x00000000U)                  /*!< ACK will be not sent */
+#define I2C_ACK_ENABLE                ((uint32_t)0x00000001U)                  /*!< ACK will be sent */
+
+/* I2C POAP position*/
+#define I2C_ACKPOS_NEXT               ((uint32_t)0x00000000U)                  /*!< ACKEN bit decides whether or not to send ACK for the next byte */
+#define I2C_ACKPOS_CURRENT            ((uint32_t)0x00000001U)                  /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
+
+/* I2C dual-address mode switch */
+#define I2C_DUADEN_DISABLE            ((uint32_t)0x00000000U)                  /*!< dual-address mode disabled */
+#define I2C_DUADEN_ENABLE             ((uint32_t)0x00000001U)                  /*!< dual-address mode enabled */
+
+/* whether or not to stretch SCL low */
+#define I2C_SCLSTRETCH_ENABLE         ((uint32_t)0x00000000U)                  /*!< SCL stretching is enabled */
+#define I2C_SCLSTRETCH_DISABLE        I2C_CTL0_DISSTRC                         /*!< SCL stretching is disabled */
+
+/* whether or not to response to a general call */
+#define I2C_GCEN_ENABLE               I2C_CTL0_GCEN                            /*!< slave will response to a general call */
+#define I2C_GCEN_DISABLE              ((uint32_t)0x00000000U)                  /*!< slave will not response to a general call */
+
+/* software reset I2C */
+#define I2C_SRESET_SET                I2C_CTL0_SRESET                          /*!< I2C is under reset */
+#define I2C_SRESET_RESET              ((uint32_t)0x00000000U)                  /*!< I2C is not under reset */
+
+/* I2C DMA mode configure */
+/* DMA mode switch */
+#define I2C_DMA_ON                    I2C_CTL1_DMAON                           /*!< DMA mode enabled */
+#define I2C_DMA_OFF                   ((uint32_t)0x00000000U)                  /*!< DMA mode disabled */
+
+/* flag indicating DMA last transfer */
+#define I2C_DMALST_ON                 I2C_CTL1_DMALST                          /*!< next DMA EOT is the last transfer */
+#define I2C_DMALST_OFF                ((uint32_t)0x00000000U)                  /*!< next DMA EOT is not the last transfer */
+
+/* I2C PEC configure */
+/* PEC enable */
+#define I2C_PEC_ENABLE                I2C_CTL0_PECEN                           /*!< PEC calculation on */
+#define I2C_PEC_DISABLE              ((uint32_t)0x00000000U)                   /*!< PEC calculation off */
+
+/* PEC transfer */
+#define I2C_PECTRANS_ENABLE           I2C_CTL0_PECTRANS                        /*!< transfer PEC */
+#define I2C_PECTRANS_DISABLE          ((uint32_t)0x00000000U)                  /*!< not transfer PEC value */
+
+/* I2C SMBus configure */
+/* issue or not alert through SMBA pin */
+#define I2C_SALTSEND_ENABLE           I2C_CTL0_SALT                            /*!< issue alert through SMBA pin */
+#define I2C_SALTSEND_DISABLE          ((uint32_t)0x00000000U)                  /*!< not issue alert through SMBA */
+
+/* ARP protocol in SMBus switch */
+#define I2C_ARP_ENABLE                I2C_CTL0_ARPEN                           /*!< ARP is enabled */
+#define I2C_ARP_DISABLE               ((uint32_t)0x00000000U)                  /*!< ARP is disabled */
+
+/* transmit I2C data */
+#define DATA_TRANS(regval)            (BITS(0,7) & ((uint32_t)(regval) << 0))
+
+/* receive I2C data */
+#define DATA_RECV(regval)             GET_BITS((uint32_t)(regval), 0, 7)
+
+/* I2C duty cycle in fast mode */
+#define I2C_DTCY_2                    ((uint32_t)0x00000000U)                  /*!< I2C fast mode Tlow/Thigh = 2 */
+#define I2C_DTCY_16_9                 I2C_CKCFG_DTCY                           /*!< I2C fast mode Tlow/Thigh = 16/9 */
+
+/* address mode for the I2C slave */
+#define I2C_ADDFORMAT_7BITS           ((uint32_t)0x00000000U)                  /*!< address:7 bits */
+#define I2C_ADDFORMAT_10BITS          I2C_SADDR0_ADDFORMAT                     /*!< address:10 bits */
+
+/* function declarations */
+/* initialization functions */
+/* reset I2C */
+void i2c_deinit(uint32_t i2c_periph);
+/* configure I2C clock */
+void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
+/* configure I2C address */
+void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
+/* SMBus type selection */
+void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
+/* whether or not to send an ACK */
+void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
+/* configure I2C POAP position */
+void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
+/* master sends slave address */
+void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
+/* dual-address mode switch */
+void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr);
+
+/* function configuration */
+/* enable I2C */
+void i2c_enable(uint32_t i2c_periph);
+/* disable I2C */
+void i2c_disable(uint32_t i2c_periph);
+/* generate a START condition on I2C bus */
+void i2c_start_on_bus(uint32_t i2c_periph);
+/* generate a STOP condition on I2C bus */
+void i2c_stop_on_bus(uint32_t i2c_periph);
+/* I2C transmit data function */
+void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
+/* I2C receive data function */
+uint8_t i2c_data_receive(uint32_t i2c_periph);
+/* enable I2C DMA mode */
+void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
+/* configure whether next DMA EOT is DMA last transfer or not */
+void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
+/* whether to stretch SCL low when data is not ready in slave mode */
+void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
+/* whether or not to response to a general call */
+void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
+/* software reset I2C */
+void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
+
+/* I2C PEC calculation on or off */
+void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
+/* I2C whether to transfer PEC value */
+void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
+/* packet error checking value */
+uint8_t i2c_pec_value_get(uint32_t i2c_periph);
+/* I2C issue alert through SMBA pin */
+void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
+/* I2C ARP protocol in SMBus switch */
+void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
+
+/* interrupt & flag functions */
+/* check I2C flag is set or not */
+FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
+/* clear I2C flag */
+void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
+/* enable I2C interrupt */
+void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* disable I2C interrupt */
+void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
+/* check I2C interrupt flag */
+FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
+/* clear I2C interrupt flag */
+void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
+
+#endif /* GD32F20X_I2C_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_misc.h

@@ -0,0 +1,97 @@
+/*!
+    \file  gd32f20x_misc.h
+    \brief definitions for the MISC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_MISC_H
+#define GD32F20X_MISC_H
+
+#include "gd32f20x.h"
+
+/* constants definitions */
+/* set the RAM and FLASH base address */
+#define NVIC_VECTTAB_RAM            ((uint32_t)0x20000000)  /*!< RAM base address */
+#define NVIC_VECTTAB_FLASH          ((uint32_t)0x08000000)  /*!< Flash base address */
+
+/* set the NVIC vector table offset mask */
+#define NVIC_VECTTAB_OFFSET_MASK    ((uint32_t)0x1FFFFF80)  /*!< NVIC vector table offset mask */
+
+/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
+#define NVIC_AIRCR_VECTKEY_MASK     ((uint32_t)0x05FA0000)  /*!< NVIC VECTKEY mask */
+
+/* priority group - define the pre-emption priority and the subpriority */
+#define NVIC_PRIGROUP_PRE0_SUB4     ((uint32_t)0x700)       /*!< 0 bits for pre-emption priority 4 bits for subpriority */
+#define NVIC_PRIGROUP_PRE1_SUB3     ((uint32_t)0x600)       /*!< 1 bits for pre-emption priority 3 bits for subpriority */
+#define NVIC_PRIGROUP_PRE2_SUB2     ((uint32_t)0x500)       /*!< 2 bits for pre-emption priority 2 bits for subpriority */
+#define NVIC_PRIGROUP_PRE3_SUB1     ((uint32_t)0x400)       /*!< 3 bits for pre-emption priority 1 bits for subpriority */
+#define NVIC_PRIGROUP_PRE4_SUB0     ((uint32_t)0x300)       /*!< 4 bits for pre-emption priority 0 bits for subpriority */
+
+/* choose the method to enter or exit the lowpower mode */
+#define SCB_SCR_SLEEPONEXIT         ((uint8_t)0x02)         /*!< choose the the system whether enter low power mode by exiting from ISR */
+#define SCB_SCR_SLEEPDEEP           ((uint8_t)0x04)         /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
+#define SCB_SCR_SEVONPEND           ((uint8_t)0x10)         /*!< choose the interrupt source that can wake up the lowpower mode */
+
+#define SCB_LPM_SLEEP_EXIT_ISR      SCB_SCR_SLEEPONEXIT     /*!< low power mode by exiting from ISR */
+#define SCB_LPM_DEEPSLEEP           SCB_SCR_SLEEPDEEP       /*!< DEEPSLEEP mode or SLEEP mode */
+#define SCB_LPM_WAKE_BY_ALL_INT     SCB_SCR_SEVONPEND       /*!< wakeup by all interrupt */
+
+/* choose the systick clock source */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
+#define SYSTICK_CLKSOURCE_HCLK      ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
+
+/* function declarations */
+/* function configuration */
+/* set the priority group */
+void nvic_priority_group_set(uint32_t nvic_prigroup);
+
+/* enable NVIC request */
+void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
+/* disable NVIC request */
+void nvic_irq_disable(uint8_t nvic_irq);
+
+/* set the NVIC vector table base address */
+void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
+
+/* set the state of the low power mode */
+void system_lowpower_set(uint8_t lowpower_mode);
+/* reset the state of the low power mode */
+void system_lowpower_reset(uint8_t lowpower_mode);
+
+/* set the systick clock source */
+void systick_clksource_set(uint32_t systick_clksource);
+
+#endif /* GD32F20X_MISC_H */
+

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_pmu.h

@@ -0,0 +1,130 @@
+/*!
+    \file  gd32f20x_pmu.h
+    \brief definitions for the PMU
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_PMU_H
+#define GD32F20X_PMU_H
+
+#include "gd32f20x.h"
+
+/* PMU definitions */
+#define PMU                           PMU_BASE                 /*!< PMU base address */
+
+/* registers definitions */
+#define PMU_CTL                       REG32((PMU) + 0x00U)     /*!< PMU control register */
+#define PMU_CS                        REG32((PMU) + 0x04U)     /*!< PMU control and status register */
+
+/* bits definitions */
+/* PMU_CTL */
+#define PMU_CTL_LDOLP                 BIT(0)                   /*!< LDO low power mode */
+#define PMU_CTL_STBMOD                BIT(1)                   /*!< standby mode */
+#define PMU_CTL_WURST                 BIT(2)                   /*!< wakeup flag reset */
+#define PMU_CTL_STBRST                BIT(3)                   /*!< standby flag reset */
+#define PMU_CTL_LVDEN                 BIT(4)                   /*!< low voltage detector enable */
+#define PMU_CTL_LVDT                  BITS(5,7)                /*!< low voltage detector threshold */
+#define PMU_CTL_BKPWEN                BIT(8)                   /*!< backup domain write enable */
+
+/* PMU_CS */
+#define PMU_CS_WUF                    BIT(0)                   /*!< wakeup flag */
+#define PMU_CS_STBF                   BIT(1)                   /*!< standby flag */
+#define PMU_CS_LVDF                   BIT(2)                   /*!< low voltage detector status flag */
+#define PMU_CS_WUPEN                  BIT(8)                   /*!< wakeup pin enable */
+
+/* constants definitions */
+/* PMU low voltage detector threshold definitions */
+#define CTL_LVDT(regval)              (BITS(5,7)&((uint32_t)(regval) << 5))
+#define PMU_LVDT_0                    CTL_LVDT(0)              /*!< voltage threshold is 2.2V */
+#define PMU_LVDT_1                    CTL_LVDT(1)              /*!< voltage threshold is 2.3V */
+#define PMU_LVDT_2                    CTL_LVDT(2)              /*!< voltage threshold is 2.4V */
+#define PMU_LVDT_3                    CTL_LVDT(3)              /*!< voltage threshold is 2.5V */
+#define PMU_LVDT_4                    CTL_LVDT(4)              /*!< voltage threshold is 2.6V */
+#define PMU_LVDT_5                    CTL_LVDT(5)              /*!< voltage threshold is 2.7V */
+#define PMU_LVDT_6                    CTL_LVDT(6)              /*!< voltage threshold is 2.8V */
+#define PMU_LVDT_7                    CTL_LVDT(7)              /*!< voltage threshold is 2.9V */
+
+/* PMU flag definitions */
+#define PMU_FLAG_WAKEUP               PMU_CS_WUF               /*!< wakeup flag status */
+#define PMU_FLAG_STANDBY              PMU_CS_STBF              /*!< standby flag status */
+#define PMU_FLAG_LVD                  PMU_CS_LVDF              /*!< lvd flag status */
+
+/* PMU ldo definitions */
+#define PMU_LDO_NORMAL                ((uint32_t)0x00000000U)  /*!< LDO normal work when PMU enter deepsleep mode */
+#define PMU_LDO_LOWPOWER              PMU_CTL_LDOLP            /*!< LDO work at low power status when PMU enter deepsleep mode */
+
+/* PMU flag reset definitions */
+#define PMU_FLAG_RESET_WAKEUP         ((uint8_t)0x00U)         /*!< wakeup flag reset */
+#define PMU_FLAG_RESET_STANDBY        ((uint8_t)0x01U)         /*!< standby flag reset */
+
+/* PMU command constants definitions */
+#define WFI_CMD                       ((uint8_t)0x00U)         /*!< use WFI command */
+#define WFE_CMD                       ((uint8_t)0x01U)         /*!< use WFE command */
+
+/* function declarations */
+/* initialization functions */
+/* reset PMU registers */
+void pmu_deinit(void);
+
+/* select low voltage detector threshold */
+void pmu_lvd_select(uint32_t lvdt_n);
+/* disable PMU lvd */
+void pmu_lvd_disable(void);
+
+/* set PMU mode */
+/* PMU work at sleep mode */
+void pmu_to_sleepmode(uint8_t sleepmodecmd);
+/* PMU work at deepsleep mode */
+void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
+/* PMU work at standby mode */
+void pmu_to_standbymode(uint8_t standbymodecmd);
+/* enable PMU wakeup pin */
+void pmu_wakeup_pin_enable(void);
+/* disable PMU wakeup pin */
+void pmu_wakeup_pin_disable(void);
+
+/* backup related functions */
+/* enable write access to the registers in backup domain */
+void pmu_backup_write_enable(void);
+/* disable write access to the registers in backup domain */
+void pmu_backup_write_disable(void);
+
+/* flag functions */
+/* get flag state */
+FlagStatus pmu_flag_get(uint32_t flag);
+/* clear flag bit */
+void pmu_flag_clear(uint32_t flag_reset);
+
+#endif /* GD32F20X_PMU_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_rtc.h

@@ -0,0 +1,152 @@
+/*!
+    \file  gd32f20x_rtc.h
+    \brief definitions for the RTC
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_RTC_H
+#define GD32F20X_RTC_H
+
+#include "gd32f20x.h"
+
+/* RTC definitions */
+#define RTC                          RTC_BASE
+
+/* registers definitions */
+#define RTC_INTEN                    REG32(RTC + 0x00U)      /*!< interrupt enable register */
+#define RTC_CTL                      REG32(RTC + 0x04U)      /*!< control register */
+#define RTC_PSCH                     REG32(RTC + 0x08U)      /*!< prescaler high register */
+#define RTC_PSCL                     REG32(RTC + 0x0CU)      /*!< prescaler low register */
+#define RTC_DIVH                     REG32(RTC + 0x10U)      /*!< divider high register */
+#define RTC_DIVL                     REG32(RTC + 0x14U)      /*!< divider low register */
+#define RTC_CNTH                     REG32(RTC + 0x18U)      /*!< counter high register */
+#define RTC_CNTL                     REG32(RTC + 0x1CU)      /*!< counter low register */
+#define RTC_ALRMH                    REG32(RTC + 0x20U)      /*!< alarm high register */
+#define RTC_ALRML                    REG32(RTC + 0x24U)      /*!< alarm low register */
+
+/* bits definitions */
+/* RTC_INTEN */
+#define RTC_INTEN_SCIE               BIT(0)                   /*!< second interrupt enable */
+#define RTC_INTEN_ALRMIE             BIT(1)                   /*!< alarm interrupt enable */
+#define RTC_INTEN_OVIE               BIT(2)                   /*!< overflow interrupt enable */
+
+/* RTC_CTL */
+#define RTC_CTL_SCIF                 BIT(0)                   /*!< second interrupt flag */
+#define RTC_CTL_ALRMIF               BIT(1)                   /*!< alarm interrupt flag */
+#define RTC_CTL_OVIF                 BIT(2)                   /*!< overflow interrupt flag */
+#define RTC_CTL_RSYNF                BIT(3)                   /*!< registers synchronized flag */
+#define RTC_CTL_CMF                  BIT(4)                   /*!< configuration mode flag */
+#define RTC_CTL_LWOFF                BIT(5)                   /*!< last write operation finished flag */
+
+/* RTC_PSCH */
+#define RTC_PSCH_PSC                 BITS(0,3)                /*!< prescaler high value */
+
+/* RTC_PSCL */
+#define RTC_PSCL_PSC                 BITS(0,15)               /*!< prescaler low value */
+
+/* RTC_DIVH */
+#define RTC_DIVH_DIV                 BITS(0,3)                /*!< divider high value */
+
+/* RTC_DIVL */
+#define RTC_DIVL_DIV                 BITS(0,15)               /*!< divider low value */
+
+/* RTC_CNTH */
+#define RTC_CNTH_CNT                 BITS(0,15)               /*!< counter high value */
+
+/* RTC_CNTL */
+#define RTC_CNTL_CNT                 BITS(0,15)               /*!< counter low value */
+
+/* RTC_ALRMH */
+#define RTC_ALRMH_ALRM               BITS(0,15)               /*!< alarm high value */
+
+/* RTC_ALRML */
+#define RTC_ALRML_ALRM               BITS(0,15)               /*!< alarm low value */
+
+/* constants definitions */
+/* RTC interrupt enable or disable definitions */
+#define RTC_INT_SECOND               RTC_INTEN_SCIE           /*!< second interrupt enable */
+#define RTC_INT_ALARM                RTC_INTEN_ALRMIE         /*!< alarm interrupt enable */
+#define RTC_INT_OVERFLOW             RTC_INTEN_OVIE           /*!< overflow interrupt enable */
+
+/* RTC interrupt flag definitions */
+#define RTC_INT_FLAG_SECOND          RTC_CTL_SCIF             /*!< second interrupt flag */
+#define RTC_INT_FLAG_ALARM           RTC_CTL_ALRMIF           /*!< alarm interrupt flag */
+#define RTC_INT_FLAG_OVERFLOW        RTC_CTL_OVIF             /*!< overflow interrupt flag */
+
+/* RTC flag definitions */
+#define RTC_FLAG_SECOND              RTC_CTL_SCIF             /*!< second interrupt flag */
+#define RTC_FLAG_ALARM               RTC_CTL_ALRMIF           /*!< alarm interrupt flag */
+#define RTC_FLAG_OVERFLOW            RTC_CTL_OVIF             /*!< overflow interrupt flag */
+#define RTC_FLAG_RSYN                RTC_CTL_RSYNF            /*!< registers synchronized flag */
+#define RTC_FLAG_LWOF                RTC_CTL_LWOFF            /*!< last write operation finished flag */
+
+/* function declarations */
+/* initialization functions */
+/* enter RTC configuration mode */
+void rtc_configuration_mode_enter(void);
+/* exit RTC configuration mode */
+void rtc_configuration_mode_exit(void);
+/* set RTC counter value */
+void rtc_counter_set(uint32_t cnt);
+/* set RTC prescaler value */
+void rtc_prescaler_set(uint32_t psc);
+
+/* operation functions */
+/* wait RTC last write operation finished flag set */
+void rtc_lwoff_wait(void);
+/* wait RTC registers synchronized flag set */
+void rtc_register_sync_wait(void);
+/* set RTC alarm value */
+void rtc_alarm_config(uint32_t alarm);
+/* get RTC counter value */
+uint32_t rtc_counter_get(void);
+/* get RTC divider value */
+uint32_t rtc_divider_get(void);
+
+/* flag & interrupt functions */
+/* get RTC flag status */
+FlagStatus rtc_flag_get(uint32_t flag);
+/* clear RTC flag status */
+void rtc_flag_clear(uint32_t flag);
+/* get RTC interrupt flag status */
+FlagStatus rtc_interrupt_flag_get(uint32_t flag);
+/* clear RTC interrupt flag status */
+void rtc_interrupt_flag_clear(uint32_t flag);
+/* enable RTC interrupt */
+void rtc_interrupt_enable(uint32_t interrupt);
+/* disable RTC interrupt */
+void rtc_interrupt_disable(uint32_t interrupt);
+
+#endif /* GD32F20X_RTC_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_sdio.h

@@ -0,0 +1,434 @@
+/*!
+    \file  gd32f20x_sdio.h
+    \brief definitions for the SDIO
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_SDIO_H
+#define GD32F20X_SDIO_H
+
+#include "gd32f20x.h"
+
+/* SDIO definitions */
+#define SDIO                            SDIO_BASE
+
+/* registers definitions */
+#define SDIO_PWRCTL                     REG32(SDIO + 0x00U)    /*!< SDIO power control register */
+#define SDIO_CLKCTL                     REG32(SDIO + 0x04U)    /*!< SDIO clock control register */
+#define SDIO_CMDAGMT                    REG32(SDIO + 0x08U)    /*!< SDIO command argument register */
+#define SDIO_CMDCTL                     REG32(SDIO + 0x0CU)    /*!< SDIO command control register */
+#define SDIO_RSPCMDIDX                  REG32(SDIO + 0x10U)    /*!< SDIO command index response register */
+#define SDIO_RESP0                      REG32(SDIO + 0x14U)    /*!< SDIO response register 0 */
+#define SDIO_RESP1                      REG32(SDIO + 0x18U)    /*!< SDIO response register 1 */
+#define SDIO_RESP2                      REG32(SDIO + 0x1CU)    /*!< SDIO response register 2 */
+#define SDIO_RESP3                      REG32(SDIO + 0x20U)    /*!< SDIO response register 3 */
+#define SDIO_DATATO                     REG32(SDIO + 0x24U)    /*!< SDIO data timeout register */
+#define SDIO_DATALEN                    REG32(SDIO + 0x28U)    /*!< SDIO data length register */
+#define SDIO_DATACTL                    REG32(SDIO + 0x2CU)    /*!< SDIO data control register */
+#define SDIO_DATACNT                    REG32(SDIO + 0x30U)    /*!< SDIO data counter register */
+#define SDIO_STAT                       REG32(SDIO + 0x34U)    /*!< SDIO status register */
+#define SDIO_INTC                       REG32(SDIO + 0x38U)    /*!< SDIO interrupt clear register */
+#define SDIO_INTEN                      REG32(SDIO + 0x3CU)    /*!< SDIO interrupt enable register */
+#define SDIO_FIFOCNT                    REG32(SDIO + 0x48U)    /*!< SDIO FIFO counter register */
+#define SDIO_FIFO                       REG32(SDIO + 0x80U)    /*!< SDIO FIFO data register */
+
+/* bits definitions */
+/* SDIO_PWRCTL */
+#define SDIO_PWRCTL_PWRCTL              BITS(0,1)              /*!< SDIO power control bits */
+
+/* SDIO_CLKCTL */
+#define SDIO_CLKCTL_DIV                 BITS(0,7)              /*!< clock division */
+#define SDIO_CLKCTL_CLKEN               BIT(8)                 /*!< SDIO_CLK clock output enable bit */
+#define SDIO_CLKCTL_CLKPWRSAV           BIT(9)                 /*!< SDIO_CLK clock dynamic switch on/off for power saving */
+#define SDIO_CLKCTL_CLKBYP              BIT(10)                /*!< clock bypass enable bit */
+#define SDIO_CLKCTL_BUSMODE             BITS(11,12)            /*!< SDIO card bus mode control bit */
+#define SDIO_CLKCTL_CLKEDGE             BIT(13)                /*!< SDIO_CLK clock edge selection bit */
+#define SDIO_CLKCTL_HWCLKEN             BIT(14)                /*!< hardware clock control enable bit */
+#define SDIO_CLKCTL_DIV8                BIT(31)                /*!< MSB of clock division */
+
+/* SDIO_CMDAGMT */
+#define SDIO_CMDAGMT_CMDAGMT            BITS(0,31)             /*!< SDIO card command argument */
+
+/* SDIO_CMDCTL */
+#define SDIO_CMDCTL_CMDIDX              BITS(0,5)              /*!< command index */
+#define SDIO_CMDCTL_CMDRESP             BITS(6,7)              /*!< command response type bits */
+#define SDIO_CMDCTL_INTWAIT             BIT(8)                 /*!< interrupt wait instead of timeout */
+#define SDIO_CMDCTL_WAITDEND            BIT(9)                 /*!< wait for ends of data transfer */
+#define SDIO_CMDCTL_CSMEN               BIT(10)                /*!< command state machine(CSM) enable bit */
+#define SDIO_CMDCTL_SUSPEND             BIT(11)                /*!< SD I/O suspend command(SD I/O only) */
+#define SDIO_CMDCTL_ENCMDC              BIT(12)                /*!< CMD completion signal enabled (CE-ATA only) */
+#define SDIO_CMDCTL_NINTEN              BIT(13)                /*!< no CE-ATA interrupt (CE-ATA only) */
+#define SDIO_CMDCTL_ATAEN               BIT(14)                /*!< CE-ATA command enable(CE-ATA only) */
+
+/* SDIO_DATATO */
+#define SDIO_DATATO_DATATO              BITS(0,31)             /*!< data timeout period */
+
+/* SDIO_DATALEN */
+#define SDIO_DATALEN_DATALEN            BITS(0,24)             /*!< data transfer length */
+
+/* SDIO_DATACTL */
+#define SDIO_DATACTL_DATAEN             BIT(0)                 /*!< data transfer enabled bit */
+#define SDIO_DATACTL_DATADIR            BIT(1)                 /*!< data transfer direction */
+#define SDIO_DATACTL_TRANSMOD           BIT(2)                 /*!< data transfer mode */
+#define SDIO_DATACTL_DMAEN              BIT(3)                 /*!< DMA enable bit */
+#define SDIO_DATACTL_BLKSZ              BITS(4,7)              /*!< data block size */
+#define SDIO_DATACTL_RWEN               BIT(8)                 /*!< read wait mode enabled(SD I/O only) */
+#define SDIO_DATACTL_RWSTOP             BIT(9)                 /*!< read wait stop(SD I/O only) */
+#define SDIO_DATACTL_RWTYPE             BIT(10)                /*!< read wait type(SD I/O only) */
+#define SDIO_DATACTL_IOEN               BIT(11)                /*!< SD I/O specific function enable(SD I/O only) */
+
+/* SDIO_STAT */
+#define SDIO_STAT_CCRCERR               BIT(0)                 /*!< command response received (CRC check failed) */
+#define SDIO_STAT_DTCRCERR              BIT(1)                 /*!< data block sent/received (CRC check failed) */
+#define SDIO_STAT_CMDTMOUT              BIT(2)                 /*!< command response timeout */
+#define SDIO_STAT_DTTMOUT               BIT(3)                 /*!< data timeout */
+#define SDIO_STAT_TXURE                 BIT(4)                 /*!< transmit FIFO underrun error occurs */
+#define SDIO_STAT_RXORE                 BIT(5)                 /*!< received FIFO overrun error occurs */
+#define SDIO_STAT_CMDRECV               BIT(6)                 /*!< command response received (CRC check passed) */
+#define SDIO_STAT_CMDSEND               BIT(7)                 /*!< command sent (no response required) */
+#define SDIO_STAT_DTEND                 BIT(8)                 /*!< data end (data counter, SDIO_DATACNT, is zero) */
+#define SDIO_STAT_STBITE                BIT(9)                 /*!< start bit error in the bus */
+#define SDIO_STAT_DTBLKEND              BIT(10)                /*!< data block sent/received (CRC check passed) */
+#define SDIO_STAT_CMDRUN                BIT(11)                /*!< command transmission in progress */
+#define SDIO_STAT_TXRUN                 BIT(12)                /*!< data transmission in progress */
+#define SDIO_STAT_RXRUN                 BIT(13)                /*!< data reception in progress */
+#define SDIO_STAT_TFH                   BIT(14)                /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
+#define SDIO_STAT_RFH                   BIT(15)                /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
+#define SDIO_STAT_TFF                   BIT(16)                /*!< transmit FIFO is full */
+#define SDIO_STAT_RFF                   BIT(17)                /*!< receive FIFO is full */
+#define SDIO_STAT_TFE                   BIT(18)                /*!< transmit FIFO is empty */
+#define SDIO_STAT_RFE                   BIT(19)                /*!< receive FIFO is empty */
+#define SDIO_STAT_TXDTVAL               BIT(20)                /*!< data is valid in transmit FIFO */
+#define SDIO_STAT_RXDTVAL               BIT(21)                /*!< data is valid in receive FIFO */
+#define SDIO_STAT_SDIOINT               BIT(22)                /*!< SD I/O interrupt received */
+#define SDIO_STAT_ATAEND                BIT(23)                /*!< CE-ATA command completion signal received (only for CMD61) */
+
+/* SDIO_INTC */
+#define SDIO_INTC_CCRCERRC              BIT(0)                 /*!< CCRCERR flag clear bit */
+#define SDIO_INTC_DTCRCERRC             BIT(1)                 /*!< DTCRCERR flag clear bit */
+#define SDIO_INTC_CMDTMOUTC             BIT(2)                 /*!< CMDTMOUT flag clear bit */
+#define SDIO_INTC_DTTMOUTC              BIT(3)                 /*!< DTTMOUT flag clear bit */
+#define SDIO_INTC_TXUREC                BIT(4)                 /*!< TXURE flag clear bit */
+#define SDIO_INTC_RXOREC                BIT(5)                 /*!< RXORE flag clear bit */
+#define SDIO_INTC_CMDRECVC              BIT(6)                 /*!< CMDRECV flag clear bit */
+#define SDIO_INTC_CMDSENDC              BIT(7)                 /*!< CMDSEND flag clear bit */
+#define SDIO_INTC_DTENDC                BIT(8)                 /*!< DTEND flag clear bit */
+#define SDIO_INTC_STBITEC               BIT(9)                 /*!< STBITE flag clear bit */
+#define SDIO_INTC_DTBLKENDC             BIT(10)                /*!< DTBLKEND flag clear bit */
+#define SDIO_INTC_SDIOINTC              BIT(22)                /*!< SDIOINT flag clear bit */
+#define SDIO_INTC_ATAENDC               BIT(23)                /*!< ATAEND flag clear bit */
+
+/* SDIO_INTEN */
+#define SDIO_INTEN_CCRCERRIE            BIT(0)                 /*!< command response CRC fail interrupt enable */
+#define SDIO_INTEN_DTCRCERRIE           BIT(1)                 /*!< data CRC fail interrupt enable */
+#define SDIO_INTEN_CMDTMOUTIE           BIT(2)                 /*!< command response timeout interrupt enable */
+#define SDIO_INTEN_DTTMOUTIE            BIT(3)                 /*!< data timeout interrupt enable */
+#define SDIO_INTEN_TXUREIE              BIT(4)                 /*!< transmit FIFO underrun error interrupt enable */
+#define SDIO_INTEN_RXOREIE              BIT(5)                 /*!< received FIFO overrun error interrupt enable */
+#define SDIO_INTEN_CMDRECVIE            BIT(6)                 /*!< command response received interrupt enable */
+#define SDIO_INTEN_CMDSENDIE            BIT(7)                 /*!< command sent interrupt enable */
+#define SDIO_INTEN_DTENDIE              BIT(8)                 /*!< data end interrupt enable */
+#define SDIO_INTEN_STBITEIE             BIT(9)                 /*!< start bit error interrupt enable */
+#define SDIO_INTEN_DTBLKENDIE           BIT(10)                /*!< data block end interrupt enable */
+#define SDIO_INTEN_CMDRUNIE             BIT(11)                /*!< command transmission interrupt enable */
+#define SDIO_INTEN_TXRUNIE              BIT(12)                /*!< data transmission interrupt enable */
+#define SDIO_INTEN_RXRUNIE              BIT(13)                /*!< data reception interrupt enable */
+#define SDIO_INTEN_TFHIE                BIT(14)                /*!< transmit FIFO half empty interrupt enable */
+#define SDIO_INTEN_RFHIE                BIT(15)                /*!< receive FIFO half full interrupt enable */
+#define SDIO_INTEN_TFFIE                BIT(16)                /*!< transmit FIFO full interrupt enable */
+#define SDIO_INTEN_RFFIE                BIT(17)                /*!< receive FIFO full interrupt enable */
+#define SDIO_INTEN_TFEIE                BIT(18)                /*!< transmit FIFO empty interrupt enable */
+#define SDIO_INTEN_RFEIE                BIT(19)                /*!< receive FIFO empty interrupt enable */
+#define SDIO_INTEN_TXDTVALIE            BIT(20)                /*!< data valid in transmit FIFO interrupt enable */
+#define SDIO_INTEN_RXDTVALIE            BIT(21)                /*!< data valid in receive FIFO interrupt enable */
+#define SDIO_INTEN_SDIOINTIE            BIT(22)                /*!< SD I/O interrupt received interrupt enable */
+#define SDIO_INTEN_ATAENDIE             BIT(23)                /*!< CE-ATA command completion signal received interrupt enable */
+
+/* SDIO_FIFO */
+#define SDIO_FIFO_FIFODT                BITS(0,31)             /*!< receive FIFO data or transmit FIFO data */
+
+/* constants definitions */
+/* SDIO flags */
+#define SDIO_FLAG_CCRCERR               BIT(0)                 /*!< command response received (CRC check failed) flag */
+#define SDIO_FLAG_DTCRCERR              BIT(1)                 /*!< data block sent/received (CRC check failed) flag */
+#define SDIO_FLAG_CMDTMOUT              BIT(2)                 /*!< command response timeout flag */
+#define SDIO_FLAG_DTTMOUT               BIT(3)                 /*!< data timeout flag */
+#define SDIO_FLAG_TXURE                 BIT(4)                 /*!< transmit FIFO underrun error occurs flag */
+#define SDIO_FLAG_RXORE                 BIT(5)                 /*!< received FIFO overrun error occurs flag */
+#define SDIO_FLAG_CMDRECV               BIT(6)                 /*!< command response received (CRC check passed) flag */
+#define SDIO_FLAG_CMDSEND               BIT(7)                 /*!< command sent (no response required) flag */
+#define SDIO_FLAG_DTEND                 BIT(8)                 /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
+#define SDIO_FLAG_STBITE                BIT(9)                 /*!< start bit error in the bus flag */
+#define SDIO_FLAG_DTBLKEND              BIT(10)                /*!< data block sent/received (CRC check passed) flag */
+#define SDIO_FLAG_CMDRUN                BIT(11)                /*!< command transmission in progress flag */
+#define SDIO_FLAG_TXRUN                 BIT(12)                /*!< data transmission in progress flag */
+#define SDIO_FLAG_RXRUN                 BIT(13)                /*!< data reception in progress flag */
+#define SDIO_FLAG_TFH                   BIT(14)                /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
+#define SDIO_FLAG_RFH                   BIT(15)                /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
+#define SDIO_FLAG_TFF                   BIT(16)                /*!< transmit FIFO is full flag */
+#define SDIO_FLAG_RFF                   BIT(17)                /*!< receive FIFO is full flag */
+#define SDIO_FLAG_TFE                   BIT(18)                /*!< transmit FIFO is empty flag */
+#define SDIO_FLAG_RFE                   BIT(19)                /*!< receive FIFO is empty flag */
+#define SDIO_FLAG_TXDTVAL               BIT(20)                /*!< data is valid in transmit FIFO flag */
+#define SDIO_FLAG_RXDTVAL               BIT(21)                /*!< data is valid in receive FIFO flag */
+#define SDIO_FLAG_SDIOINT               BIT(22)                /*!< SD I/O interrupt received flag */
+#define SDIO_FLAG_ATAEND                BIT(23)                /*!< CE-ATA command completion signal received (only for CMD61) flag */
+
+/* SDIO interrupt enable or disable */
+#define SDIO_INT_CCRCERR                BIT(0)                 /*!< SDIO CCRCERR interrupt */
+#define SDIO_INT_DTCRCERR               BIT(1)                 /*!< SDIO DTCRCERR interrupt */
+#define SDIO_INT_CMDTMOUT               BIT(2)                 /*!< SDIO CMDTMOUT interrupt */
+#define SDIO_INT_DTTMOUT                BIT(3)                 /*!< SDIO DTTMOUT interrupt */
+#define SDIO_INT_TXURE                  BIT(4)                 /*!< SDIO TXURE interrupt */
+#define SDIO_INT_RXORE                  BIT(5)                 /*!< SDIO RXORE interrupt */
+#define SDIO_INT_CMDRECV                BIT(6)                 /*!< SDIO CMDRECV interrupt */
+#define SDIO_INT_CMDSEND                BIT(7)                 /*!< SDIO CMDSEND interrupt */
+#define SDIO_INT_DTEND                  BIT(8)                 /*!< SDIO DTEND interrupt */
+#define SDIO_INT_STBITE                 BIT(9)                 /*!< SDIO STBITE interrupt */
+#define SDIO_INT_DTBLKEND               BIT(10)                /*!< SDIO DTBLKEND interrupt */
+#define SDIO_INT_CMDRUN                 BIT(11)                /*!< SDIO CMDRUN interrupt */
+#define SDIO_INT_TXRUN                  BIT(12)                /*!< SDIO TXRUN interrupt */
+#define SDIO_INT_RXRUN                  BIT(13)                /*!< SDIO RXRUN interrupt */
+#define SDIO_INT_TFH                    BIT(14)                /*!< SDIO TFH interrupt */
+#define SDIO_INT_RFH                    BIT(15)                /*!< SDIO RFH interrupt */
+#define SDIO_INT_TFF                    BIT(16)                /*!< SDIO TFF interrupt */
+#define SDIO_INT_RFF                    BIT(17)                /*!< SDIO RFF interrupt */
+#define SDIO_INT_TFE                    BIT(18)                /*!< SDIO TFE interrupt */
+#define SDIO_INT_RFE                    BIT(19)                /*!< SDIO RFE interrupt */
+#define SDIO_INT_TXDTVAL                BIT(20)                /*!< SDIO TXDTVAL interrupt */
+#define SDIO_INT_RXDTVAL                BIT(21)                /*!< SDIO RXDTVAL interrupt */
+#define SDIO_INT_SDIOINT                BIT(22)                /*!< SDIO SDIOINT interrupt */
+#define SDIO_INT_ATAEND                 BIT(23)                /*!< SDIO ATAEND interrupt */
+
+/* SDIO interrupt flags */
+#define SDIO_INT_FLAG_CCRCERR           BIT(0)                 /*!< SDIO CCRCERR interrupt */
+#define SDIO_INT_FLAG_DTCRCERR          BIT(1)                 /*!< SDIO DTCRCERR interrupt */
+#define SDIO_INT_FLAG_CMDTMOUT          BIT(2)                 /*!< SDIO CMDTMOUT interrupt */
+#define SDIO_INT_FLAG_DTTMOUT           BIT(3)                 /*!< SDIO DTTMOUT interrupt */
+#define SDIO_INT_FLAG_TXURE             BIT(4)                 /*!< SDIO TXURE interrupt */
+#define SDIO_INT_FLAG_RXORE             BIT(5)                 /*!< SDIO RXORE interrupt */
+#define SDIO_INT_FLAG_CMDRECV           BIT(6)                 /*!< SDIO CMDRECV interrupt */
+#define SDIO_INT_FLAG_CMDSEND           BIT(7)                 /*!< SDIO CMDSEND interrupt */
+#define SDIO_INT_FLAG_DTEND             BIT(8)                 /*!< SDIO DTEND interrupt */
+#define SDIO_INT_FLAG_STBITE            BIT(9)                 /*!< SDIO STBITE interrupt */
+#define SDIO_INT_FLAG_DTBLKEND          BIT(10)                /*!< SDIO DTBLKEND interrupt */
+#define SDIO_INT_FLAG_CMDRUN            BIT(11)                /*!< SDIO CMDRUN interrupt */
+#define SDIO_INT_FLAG_TXRUN             BIT(12)                /*!< SDIO TXRUN interrupt */
+#define SDIO_INT_FLAG_RXRUN             BIT(13)                /*!< SDIO RXRUN interrupt */
+#define SDIO_INT_FLAG_TFH               BIT(14)                /*!< SDIO TFH interrupt */
+#define SDIO_INT_FLAG_RFH               BIT(15)                /*!< SDIO RFH interrupt */
+#define SDIO_INT_FLAG_TFF               BIT(16)                /*!< SDIO TFF interrupt */
+#define SDIO_INT_FLAG_RFF               BIT(17)                /*!< SDIO RFF interrupt */
+#define SDIO_INT_FLAG_TFE               BIT(18)                /*!< SDIO TFE interrupt */
+#define SDIO_INT_FLAG_RFE               BIT(19)                /*!< SDIO RFE interrupt */
+#define SDIO_INT_FLAG_TXDTVAL           BIT(20)                /*!< SDIO TXDTVAL interrupt */
+#define SDIO_INT_FLAG_RXDTVAL           BIT(21)                /*!< SDIO RXDTVAL interrupt */
+#define SDIO_INT_FLAG_SDIOINT           BIT(22)                /*!< SDIO SDIOINT interrupt */
+#define SDIO_INT_FLAG_ATAEND            BIT(23)                /*!< SDIO ATAEND interrupt */
+
+/* SDIO power control */
+#define PWRCTL_PWRCTL(regval)           (BITS(0,1) & ((uint32_t)(regval) << 0))
+#define SDIO_POWER_OFF                  PWRCTL_PWRCTL(0)       /*!< SDIO power off */
+#define SDIO_POWER_ON                   PWRCTL_PWRCTL(3)       /*!< SDIO power on */
+
+/* SDIO card bus mode control */
+#define CLKCTL_BUSMODE(regval)          (BITS(11,12) & ((uint32_t)(regval) << 11))
+#define SDIO_BUSMODE_1BIT               CLKCTL_BUSMODE(0)      /*!< 1-bit SDIO card bus mode */
+#define SDIO_BUSMODE_4BIT               CLKCTL_BUSMODE(1)      /*!< 4-bit SDIO card bus mode */
+#define SDIO_BUSMODE_8BIT               CLKCTL_BUSMODE(2)      /*!< 8-bit SDIO card bus mode */
+
+/* SDIO_CLK clock edge selection */
+#define SDIO_SDIOCLKEDGE_RISING         ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
+#define SDIO_SDIOCLKEDGE_FALLING        SDIO_CLKCTL_CLKEDGE    /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
+
+/* clock bypass enable or disable */
+#define SDIO_CLOCKBYPASS_DISABLE        ((uint32_t)0x00000000U)/*!< no bypass */
+#define SDIO_CLOCKBYPASS_ENABLE         SDIO_CLKCTL_CLKBYP     /*!< clock bypass */
+
+/* SDIO_CLK clock dynamic switch on/off for power saving */
+#define SDIO_CLOCKPWRSAVE_DISABLE       ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */
+#define SDIO_CLOCKPWRSAVE_ENABLE        SDIO_CLKCTL_CLKPWRSAV  /*!< SDIO_CLK closed when bus is idle */
+
+/* SDIO command response type */
+#define CMDCTL_CMDRESP(regval)          (BITS(6,7) & ((uint32_t)(regval) << 6))
+#define SDIO_RESPONSETYPE_NO            CMDCTL_CMDRESP(0)      /*!< no response */
+#define SDIO_RESPONSETYPE_SHORT         CMDCTL_CMDRESP(1)      /*!< short response */
+#define SDIO_RESPONSETYPE_LONG          CMDCTL_CMDRESP(3)      /*!< long response */
+
+/* command state machine wait type */
+#define SDIO_WAITTYPE_NO                ((uint32_t)0x00000000U)/*!< not wait interrupt */
+#define SDIO_WAITTYPE_INTERRUPT         SDIO_CMDCTL_INTWAIT    /*!< wait interrupt */
+#define SDIO_WAITTYPE_DATAEND           SDIO_CMDCTL_WAITDEND   /*!< wait the end of data transfer */
+
+#define SDIO_RESPONSE0                  ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */
+#define SDIO_RESPONSE1                  ((uint32_t)0x00000001U)/*!< card response[95:64] */
+#define SDIO_RESPONSE2                  ((uint32_t)0x00000002U)/*!< card response[63:32] */
+#define SDIO_RESPONSE3                  ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */
+
+/* SDIO data block size */
+#define DATACTL_BLKSZ(regval)           (BITS(4,7) & ((uint32_t)(regval) << 4))
+#define SDIO_DATABLOCKSIZE_1BYTE        DATACTL_BLKSZ(0)       /*!< block size = 1 byte */
+#define SDIO_DATABLOCKSIZE_2BYTES       DATACTL_BLKSZ(1)       /*!< block size = 2 bytes */
+#define SDIO_DATABLOCKSIZE_4BYTES       DATACTL_BLKSZ(2)       /*!< block size = 4 bytes */
+#define SDIO_DATABLOCKSIZE_8BYTES       DATACTL_BLKSZ(3)       /*!< block size = 8 bytes */
+#define SDIO_DATABLOCKSIZE_16BYTES      DATACTL_BLKSZ(4)       /*!< block size = 16 bytes */
+#define SDIO_DATABLOCKSIZE_32BYTES      DATACTL_BLKSZ(5)       /*!< block size = 32 bytes */
+#define SDIO_DATABLOCKSIZE_64BYTES      DATACTL_BLKSZ(6)       /*!< block size = 64 bytes */
+#define SDIO_DATABLOCKSIZE_128BYTES     DATACTL_BLKSZ(7)       /*!< block size = 128 bytes */
+#define SDIO_DATABLOCKSIZE_256BYTES     DATACTL_BLKSZ(8)       /*!< block size = 256 bytes */
+#define SDIO_DATABLOCKSIZE_512BYTES     DATACTL_BLKSZ(9)       /*!< block size = 512 bytes */
+#define SDIO_DATABLOCKSIZE_1024BYTES    DATACTL_BLKSZ(10)      /*!< block size = 1024 bytes */
+#define SDIO_DATABLOCKSIZE_2048BYTES    DATACTL_BLKSZ(11)      /*!< block size = 2048 bytes */
+#define SDIO_DATABLOCKSIZE_4096BYTES    DATACTL_BLKSZ(12)      /*!< block size = 4096 bytes */
+#define SDIO_DATABLOCKSIZE_8192BYTES    DATACTL_BLKSZ(13)      /*!< block size = 8192 bytes */
+#define SDIO_DATABLOCKSIZE_16384BYTES   DATACTL_BLKSZ(14)      /*!< block size = 16384 bytes */
+
+/* SDIO data transfer mode */
+#define SDIO_TRANSMODE_BLOCK            ((uint32_t)0x00000000U)/*!< block transfer */
+#define SDIO_TRANSMODE_STREAM           SDIO_DATACTL_TRANSMOD  /*!< stream transfer or SDIO multibyte transfer */
+
+/* SDIO data transfer direction */
+#define SDIO_TRANSDIRECTION_TOCARD      ((uint32_t)0x00000000U)/*!< write data to card */
+#define SDIO_TRANSDIRECTION_TOSDIO      SDIO_DATACTL_DATADIR   /*!< read data from card */
+
+/* SDIO read wait type */
+#define SDIO_READWAITTYPE_DAT2          ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */
+#define SDIO_READWAITTYPE_CLK           SDIO_DATACTL_RWTYPE    /*!< read wait control by stopping SDIO_CLK */
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize the SDIO */
+void sdio_deinit(void);
+/* configure the SDIO clock */
+void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
+/* enable hardware clock control */
+void sdio_hardware_clock_enable(void);
+/* disable hardware clock control */
+void sdio_hardware_clock_disable(void);
+/* set different SDIO card bus mode */
+void sdio_bus_mode_set(uint32_t bus_mode);
+/* set the SDIO power state */
+void sdio_power_state_set(uint32_t power_state);
+/* get the SDIO power state */
+uint32_t sdio_power_state_get(void);
+/* enable SDIO_CLK clock output */
+void sdio_clock_enable(void);
+/* disable SDIO_CLK clock output */
+void sdio_clock_disable(void);
+
+/* function configuration */
+/* configure the command index, argument, response type, wait type and CSM to send command */
+/* configure the command and response */
+void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
+/* set the command state machine wait type */
+void sdio_wait_type_set(uint32_t wait_type);
+/* enable the CSM(command state machine) */
+void sdio_csm_enable(void);
+/* disable the CSM(command state machine) */
+void sdio_csm_disable(void);
+/* get the last response command index */
+uint8_t sdio_command_index_get(void);
+/* get the response for the last received command */
+uint32_t sdio_response_get(uint32_t responsex);
+
+/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */
+/* configure the data timeout, data length and data block size */
+void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
+/* configure the data transfer mode and direction */
+void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
+/* enable the DSM(data state machine) for data transfer */
+void sdio_dsm_enable(void);
+/* disable the DSM(data state machine) */
+void sdio_dsm_disable(void);
+/* write data(one word) to the transmit FIFO */
+void sdio_data_write(uint32_t data);
+/* read data(one word) from the receive FIFO */
+uint32_t sdio_data_read(void);
+/* get the number of remaining data bytes to be transferred to card */
+uint32_t sdio_data_counter_get(void);
+/* get the number of words remaining to be written or read from FIFO */
+uint32_t sdio_fifo_counter_get(void);
+/* enable the DMA request for SDIO */
+void sdio_dma_enable(void);
+/* disable the DMA request for SDIO */
+void sdio_dma_disable(void);
+
+/* enable the read wait mode(SD I/O only) */
+void sdio_readwait_enable(void);
+/* disable the read wait mode(SD I/O only) */
+void sdio_readwait_disable(void);
+/* enable the function that stop the read wait process(SD I/O only) */
+void sdio_stop_readwait_enable(void);
+/* disable the function that stop the read wait process(SD I/O only) */
+void sdio_stop_readwait_disable(void);
+/* set the read wait type(SD I/O only) */
+void sdio_readwait_type_set(uint32_t readwait_type);
+/* enable the SD I/O mode specific operation(SD I/O only) */
+void sdio_operation_enable(void);
+/* disable the SD I/O mode specific operation(SD I/O only) */
+void sdio_operation_disable(void);
+/* enable the SD I/O suspend operation(SD I/O only) */
+void sdio_suspend_enable(void);
+/* disable the SD I/O suspend operation(SD I/O only) */
+void sdio_suspend_disable(void);
+
+/* enable the CE-ATA command(CE-ATA only) */
+void sdio_ceata_command_enable(void);
+/* disable the CE-ATA command(CE-ATA only) */
+void sdio_ceata_command_disable(void);
+/* enable the CE-ATA interrupt(CE-ATA only) */
+void sdio_ceata_interrupt_enable(void);
+/* disable the CE-ATA interrupt(CE-ATA only) */
+void sdio_ceata_interrupt_disable(void);
+/* enable the CE-ATA command completion signal(CE-ATA only) */
+void sdio_ceata_command_completion_enable(void);
+/* disable the CE-ATA command completion signal(CE-ATA only) */
+void sdio_ceata_command_completion_disable(void);
+
+/* interrupt & flag functions */
+/* get the flags state of SDIO */
+FlagStatus sdio_flag_get(uint32_t flag);
+/* clear the pending flags of SDIO */
+void sdio_flag_clear(uint32_t flag);
+/* enable the SDIO interrupt */
+void sdio_interrupt_enable(uint32_t int_flag);
+/* disable the SDIO interrupt */
+void sdio_interrupt_disable(uint32_t int_flag);
+/* get the interrupt flags state of SDIO */
+FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
+/* clear the interrupt pending flags of SDIO */
+void sdio_interrupt_flag_clear(uint32_t int_flag);
+
+#endif /* GD32F20X_SDIO_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_spi.h

@@ -0,0 +1,347 @@
+/*!
+    \file  gd32f20x_spi.h
+    \brief definitions for the SPI
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_SPI_H
+#define GD32F20X_SPI_H
+
+#include "gd32f20x.h"
+
+/* SPIx(x=0,1,2) definitions */
+#define SPI0                            (SPI_BASE + 0x0000F800U)
+#define SPI1                            SPI_BASE
+#define SPI2                            (SPI_BASE + 0x00000400U)
+
+/* SPI registers definitions */
+#define SPI_CTL0(spix)                  REG32((spix) + 0x00U)                   /*!< SPI control register 0 */
+#define SPI_CTL1(spix)                  REG32((spix) + 0x04U)                   /*!< SPI control register 1*/
+#define SPI_STAT(spix)                  REG32((spix) + 0x08U)                   /*!< SPI status register */
+#define SPI_DATA(spix)                  REG32((spix) + 0x0CU)                   /*!< SPI data register */
+#define SPI_CRCPOLY(spix)               REG32((spix) + 0x10U)                   /*!< SPI CRC polynomial register */
+#define SPI_RCRC(spix)                  REG32((spix) + 0x14U)                   /*!< SPI receive CRC register */
+#define SPI_TCRC(spix)                  REG32((spix) + 0x18U)                   /*!< SPI transmit CRC register */
+#define SPI_I2SCTL(spix)                REG32((spix) + 0x1CU)                   /*!< SPI I2S control register */
+#define SPI_I2SPSC(spix)                REG32((spix) + 0x20U)                   /*!< SPI I2S clock prescaler register */
+#define SPI_QCTL(spix)                  REG32((spix) + 0x80U)                   /*!< SPI quad mode control register(only SPI0) */
+
+/* bits definitions */
+/* SPI_CTL0 */
+#define SPI_CTL0_CKPH                   BIT(0)                                  /*!< clock phase selection*/
+#define SPI_CTL0_CKPL                   BIT(1)                                  /*!< clock polarity selection */
+#define SPI_CTL0_MSTMOD                 BIT(2)                                  /*!< master mode enable */
+#define SPI_CTL0_PSC                    BITS(3,5)                               /*!< master clock prescaler selection */
+#define SPI_CTL0_SPIEN                  BIT(6)                                  /*!< SPI enable*/
+#define SPI_CTL0_LF                     BIT(7)                                  /*!< LSB first mode */
+#define SPI_CTL0_SWNSS                  BIT(8)                                  /*!< NSS pin selection in NSS software mode */
+#define SPI_CTL0_SWNSSEN                BIT(9)                                  /*!< NSS software mode selection */
+#define SPI_CTL0_RO                     BIT(10)                                 /*!< receive only */
+#define SPI_CTL0_FF16                   BIT(11)                                 /*!< data frame size */
+#define SPI_CTL0_CRCNT                  BIT(12)                                 /*!< CRC next transfer */
+#define SPI_CTL0_CRCEN                  BIT(13)                                 /*!< CRC calculation enable */
+#define SPI_CTL0_BDOEN                  BIT(14)                                 /*!< bidirectional transmit output enable*/
+#define SPI_CTL0_BDEN                   BIT(15)                                 /*!< bidirectional enable */
+
+/* SPI_CTL1 */
+#define SPI_CTL1_DMAREN                 BIT(0)                                  /*!< receive buffer dma enable */
+#define SPI_CTL1_DMATEN                 BIT(1)                                  /*!< transmit buffer dma enable */
+#define SPI_CTL1_NSSDRV                 BIT(2)                                  /*!< drive NSS output */
+#define SPI_CTL1_ERRIE                  BIT(5)                                  /*!< errors interrupt enable */
+#define SPI_CTL1_RBNEIE                 BIT(6)                                  /*!< receive buffer not empty interrupt enable */
+#define SPI_CTL1_TBEIE                  BIT(7)                                  /*!< transmit buffer empty interrupt enable */
+
+/* SPI_STAT */
+#define SPI_STAT_RBNE                   BIT(0)                                  /*!< receive buffer not empty */
+#define SPI_STAT_TBE                    BIT(1)                                  /*!< transmit buffer empty */
+#define SPI_STAT_I2SCH                  BIT(2)                                  /*!< I2S channel side */
+#define SPI_STAT_TXURERR                BIT(3)                                  /*!< I2S transmission underrun error bit */
+#define SPI_STAT_CRCERR                 BIT(4)                                  /*!< SPI CRC error bit */
+#define SPI_STAT_CONFERR                BIT(5)                                  /*!< SPI configuration error bit */
+#define SPI_STAT_RXORERR                BIT(6)                                  /*!< SPI reception overrun error bit */
+#define SPI_STAT_TRANS                  BIT(7)                                  /*!< transmitting on-going bit */
+
+/* SPI_DATA */
+#define SPI_DATA_DATA                   BITS(0,15)                              /*!< data transfer register */
+
+/* SPI_CRCPOLY */
+#define SPI_CRCPOLY_CPR                 BITS(0,15)                              /*!< CRC polynomial register */
+
+/* SPI_RCRC */
+#define SPI_RCRC_RCR                    BITS(0,15)                              /*!< RX CRC register */
+
+/* SPI_TCRC */
+#define SPI_TCRC_TCR                    BITS(0,15)                              /*!< RX CRC register */
+
+/* SPI_I2SCTL */
+#define SPI_I2SCTL_CHLEN                BIT(0)                                  /*!< channel length */
+#define SPI_I2SCTL_DTLEN                BITS(1,2)                               /*!< data length */
+#define SPI_I2SCTL_CKPL                 BIT(3)                                  /*!< idle state clock polarity */
+#define SPI_I2SCTL_I2SSTD               BITS(4,5)                               /*!< I2S standard selection */
+#define SPI_I2SCTL_PCMSMOD              BIT(7)                                  /*!< PCM frame synchronization mode */
+#define SPI_I2SCTL_I2SOPMOD             BITS(8,9)                               /*!< I2S operation mode */
+#define SPI_I2SCTL_I2SEN                BIT(10)                                 /*!< I2S enable */
+#define SPI_I2SCTL_I2SSEL               BIT(11)                                 /*!< I2S mode selection */
+
+/* SPI_I2SPSC */
+#define SPI_I2SPSC_DIV                  BITS(0,7)                               /*!< dividing factor for the prescaler */
+#define SPI_I2SPSC_OF                   BIT(8)                                  /*!< odd factor for the prescaler */
+#define SPI_I2SPSC_MCKOEN               BIT(9)                                  /*!< I2S MCK output enable */
+
+/* SPI_QCTL(only for SPI0) */
+#define SPI_QCTL_QMOD                   BIT(0)                                  /*!< quad-SPI mode enable */
+#define SPI_QCTL_QRD                    BIT(1)                                  /*!< quad-SPI mode read select */
+#define SPI_QCTL_IO23_DRV               BIT(2)                                  /*!< drive SPI_IO2 and SPI_IO3 enable */
+
+/* constants definitions */
+/* SPI and I2S parameter struct definitions */
+typedef struct
+{   
+    uint32_t device_mode;                                                       /*!< SPI master or slave */
+    uint32_t trans_mode;                                                        /*!< SPI transfer type */
+    uint32_t frame_size;                                                        /*!< SPI frame size */
+    uint32_t nss;                                                               /*!< SPI NSS control by hardware or software */
+    uint32_t endian;                                                            /*!< SPI big endian or little endian */
+    uint32_t clock_polarity_phase;                                              /*!< SPI clock phase and polarity */
+    uint32_t prescale;                                                          /*!< SPI prescaler factor */
+}spi_parameter_struct;
+
+/* SPI mode definitions */
+#define SPI_MASTER                      (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS)      /*!< SPI as master */
+#define SPI_SLAVE                       ((uint32_t)0x00000000U)                 /*!< SPI as slave */
+
+/* SPI bidirectional transfer direction */
+#define SPI_BIDIRECTIONAL_TRANSMIT      SPI_CTL0_BDOEN                          /*!< SPI work in transmit-only mode */
+#define SPI_BIDIRECTIONAL_RECEIVE       ~SPI_CTL0_BDOEN                         /*!< SPI work in receive-only mode */
+
+/* SPI transmit type */
+#define SPI_TRANSMODE_FULLDUPLEX        ((uint32_t)0x00000000U)                 /*!< SPI receive and send data at fullduplex communication */
+#define SPI_TRANSMODE_RECEIVEONLY       SPI_CTL0_RO                             /*!< SPI only receive data */
+#define SPI_TRANSMODE_BDRECEIVE         SPI_CTL0_BDEN                           /*!< bidirectional receive data */
+#define SPI_TRANSMODE_BDTRANSMIT        (SPI_CTL0_BDEN | SPI_CTL0_BDOEN)        /*!< bidirectional transmit data*/
+
+/* SPI frame size */
+#define SPI_FRAMESIZE_16BIT             SPI_CTL0_FF16                           /*!< SPI frame size is 16 bits */
+#define SPI_FRAMESIZE_8BIT              ((uint32_t)0x00000000U)                 /*!< SPI frame size is 8 bits */
+
+/* SPI NSS control mode */
+#define SPI_NSS_SOFT                    SPI_CTL0_SWNSSEN                        /*!< SPI NSS control by sofrware */
+#define SPI_NSS_HARD                    ((uint32_t)0x00000000U)                 /*!< SPI NSS control by hardware */
+
+/* SPI transmit way */
+#define SPI_ENDIAN_MSB                  ((uint32_t)0x00000000U)                 /*!< SPI transmit way is big endian: transmit MSB first */
+#define SPI_ENDIAN_LSB                  SPI_CTL0_LF                             /*!< SPI transmit way is little endian: transmit LSB first */
+
+/* SPI clock phase and polarity */
+#define SPI_CK_PL_LOW_PH_1EDGE          ((uint32_t)0x00000000U)                 /*!< SPI clock polarity is low level and phase is first edge */
+#define SPI_CK_PL_HIGH_PH_1EDGE         SPI_CTL0_CKPL                           /*!< SPI clock polarity is high level and phase is first edge */
+#define SPI_CK_PL_LOW_PH_2EDGE          SPI_CTL0_CKPH                           /*!< SPI clock polarity is low level and phase is second edge */
+#define SPI_CK_PL_HIGH_PH_2EDGE         (SPI_CTL0_CKPL | SPI_CTL0_CKPH)         /*!< SPI clock polarity is high level and phase is second edge */
+
+/* SPI clock prescale factor */
+#define CTL0_PSC(regval)                (BITS(3,5) & ((uint32_t)(regval) << 3))
+#define SPI_PSC_2                       CTL0_PSC(0)                             /*!< SPI clock prescale factor is 2 */
+#define SPI_PSC_4                       CTL0_PSC(1)                             /*!< SPI clock prescale factor is 4 */
+#define SPI_PSC_8                       CTL0_PSC(2)                             /*!< SPI clock prescale factor is 8 */
+#define SPI_PSC_16                      CTL0_PSC(3)                             /*!< SPI clock prescale factor is 16 */
+#define SPI_PSC_32                      CTL0_PSC(4)                             /*!< SPI clock prescale factor is 32 */
+#define SPI_PSC_64                      CTL0_PSC(5)                             /*!< SPI clock prescale factor is 64 */
+#define SPI_PSC_128                     CTL0_PSC(6)                             /*!< SPI clock prescale factor is 128 */
+#define SPI_PSC_256                     CTL0_PSC(7)                             /*!< SPI clock prescale factor is 256 */
+
+/* I2S audio sample rate */
+#define I2S_AUDIOSAMPLE_8K              ((uint32_t)8000U)                       /*!< I2S audio sample rate is 8KHz */
+#define I2S_AUDIOSAMPLE_11K             ((uint32_t)11025U)                      /*!< I2S audio sample rate is 11KHz */
+#define I2S_AUDIOSAMPLE_16K             ((uint32_t)16000U)                      /*!< I2S audio sample rate is 16KHz */
+#define I2S_AUDIOSAMPLE_22K             ((uint32_t)22050U)                      /*!< I2S audio sample rate is 22KHz */
+#define I2S_AUDIOSAMPLE_32K             ((uint32_t)32000U)                      /*!< I2S audio sample rate is 32KHz */
+#define I2S_AUDIOSAMPLE_44K             ((uint32_t)44100U)                      /*!< I2S audio sample rate is 44KHz */
+#define I2S_AUDIOSAMPLE_48K             ((uint32_t)48000U)                      /*!< I2S audio sample rate is 48KHz */
+#define I2S_AUDIOSAMPLE_96K             ((uint32_t)96000U)                      /*!< I2S audio sample rate is 96KHz */
+#define I2S_AUDIOSAMPLE_192K            ((uint32_t)192000U)                     /*!< I2S audio sample rate is 192KHz */
+
+/* I2S frame format */
+#define I2SCTL_DTLEN(regval)            (BITS(1,2) & ((uint32_t)(regval) << 1))
+#define I2S_FRAMEFORMAT_DT16B_CH16B     I2SCTL_DTLEN(0)                         /*!< I2S data length is 16 bit and channel length is 16 bit */
+#define I2S_FRAMEFORMAT_DT16B_CH32B     (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 16 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT24B_CH32B     (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 24 bit and channel length is 32 bit */
+#define I2S_FRAMEFORMAT_DT32B_CH32B     (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN)    /*!< I2S data length is 32 bit and channel length is 32 bit */
+
+/* I2S master clock output */
+#define I2S_MCKOUT_DISABLE              ((uint32_t)0x00000000U)                 /*!< I2S master clock output disable */
+#define I2S_MCKOUT_ENABLE               SPI_I2SPSC_MCKOEN                       /*!< I2S master clock output enable */
+
+/* I2S operation mode */
+#define I2SCTL_I2SOPMOD(regval)         (BITS(8,9) & ((uint32_t)(regval) << 8))
+#define I2S_MODE_SLAVETX                I2SCTL_I2SOPMOD(0)                      /*!< I2S slave transmit mode */
+#define I2S_MODE_SLAVERX                I2SCTL_I2SOPMOD(1)                      /*!< I2S slave receive mode */
+#define I2S_MODE_MASTERTX               I2SCTL_I2SOPMOD(2)                      /*!< I2S master transmit mode */
+#define I2S_MODE_MASTERRX               I2SCTL_I2SOPMOD(3)                      /*!< I2S master receive mode */
+
+/* I2S standard */
+#define I2SCTL_I2SSTD(regval)           (BITS(4,5) & ((uint32_t)(regval) << 4))
+#define I2S_STD_PHILLIPS                I2SCTL_I2SSTD(0)                        /*!< I2S phillips standard */
+#define I2S_STD_MSB                     I2SCTL_I2SSTD(1)                        /*!< I2S MSB standard */
+#define I2S_STD_LSB                     I2SCTL_I2SSTD(2)                        /*!< I2S LSB standard */
+#define I2S_STD_PCMSHORT                I2SCTL_I2SSTD(3)                        /*!< I2S PCM short standard */
+#define I2S_STD_PCMLONG                 (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
+
+/* I2S clock polarity */
+#define I2S_CKPL_LOW                    ((uint32_t)0x00000000U)                 /*!< I2S clock polarity low level */
+#define I2S_CKPL_HIGH                   SPI_I2SCTL_CKPL                         /*!< I2S clock polarity high level */
+
+/* SPI DMA constants definitions */                                    
+#define SPI_DMA_TRANSMIT                ((uint8_t)0x00U)                        /*!< SPI transmit data use DMA */
+#define SPI_DMA_RECEIVE                 ((uint8_t)0x01U)                        /*!< SPI receive data use DMA */
+
+/* SPI CRC constants definitions */
+#define SPI_CRC_TX                      ((uint8_t)0x00U)                        /*!< SPI transmit CRC value */
+#define SPI_CRC_RX                      ((uint8_t)0x01U)                        /*!< SPI receive CRC value */
+
+/* SPI/I2S interrupt enable/disable constants definitions */
+#define SPI_I2S_INT_TBE                 ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt */
+#define SPI_I2S_INT_RBNE                ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt */
+#define SPI_I2S_INT_ERR                 ((uint8_t)0x02U)                        /*!< error interrupt */
+
+/* SPI/I2S interrupt flag constants definitions */
+#define SPI_I2S_INT_FLAG_TBE            ((uint8_t)0x00U)                        /*!< transmit buffer empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RBNE           ((uint8_t)0x01U)                        /*!< receive buffer not empty interrupt flag */
+#define SPI_I2S_INT_FLAG_RXORERR        ((uint8_t)0x02U)                        /*!< overrun interrupt flag */
+#define SPI_INT_FLAG_CONFERR            ((uint8_t)0x03U)                        /*!< config error interrupt flag */
+#define SPI_INT_FLAG_CRCERR             ((uint8_t)0x04U)                        /*!< CRC error interrupt flag */
+#define I2S_INT_FLAG_TXURERR            ((uint8_t)0x05U)                        /*!< underrun error interrupt flag */
+
+/* SPI/I2S flag definitions */                                                  
+#define SPI_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
+#define SPI_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
+#define SPI_FLAG_CRCERR                 SPI_STAT_CRCERR                         /*!< CRC error flag */
+#define SPI_FLAG_CONFERR                SPI_STAT_CONFERR                        /*!< mode config error flag */
+#define SPI_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< receive overrun error flag */
+#define SPI_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+#define I2S_FLAG_RBNE                   SPI_STAT_RBNE                           /*!< receive buffer not empty flag */
+#define I2S_FLAG_TBE                    SPI_STAT_TBE                            /*!< transmit buffer empty flag */
+#define I2S_FLAG_CH                     SPI_STAT_I2SCH                          /*!< channel side flag */
+#define I2S_FLAG_TXURERR                SPI_STAT_TXURERR                        /*!< underrun error flag */
+#define I2S_FLAG_RXORERR                SPI_STAT_RXORERR                        /*!< overrun error flag */
+#define I2S_FLAG_TRANS                  SPI_STAT_TRANS                          /*!< transmit on-going flag */
+
+/* function declarations */
+/* SPI/I2S deinitialization and initialization functions */
+/* reset SPI and I2S */
+void spi_i2s_deinit(uint32_t spi_periph);
+/* initialize the parameters of SPI structure with the default values */
+void spi_struct_para_init(spi_parameter_struct* spi_struct);
+/* initialize SPI parameter */
+void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
+/* enable SPI */
+void spi_enable(uint32_t spi_periph);
+/* disable SPI */
+void spi_disable(uint32_t spi_periph);
+
+/* initialize I2S parameter */
+void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
+/* configure I2S prescaler */
+void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
+/* enable I2S */
+void i2s_enable(uint32_t spi_periph);
+/* disable I2S */
+void i2s_disable(uint32_t spi_periph);
+
+/* NSS functions */
+/* enable SPI NSS output */
+void spi_nss_output_enable(uint32_t spi_periph);
+/* disable SPI NSS output */
+void spi_nss_output_disable(uint32_t spi_periph);
+/* SPI NSS pin high level in software mode */
+void spi_nss_internal_high(uint32_t spi_periph);
+/* SPI NSS pin low level in software mode */
+void spi_nss_internal_low(uint32_t spi_periph);
+
+/* DMA communication */
+/* enable SPI DMA */
+void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
+/* disable SPI DMA */
+void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
+
+/* normal mode communication */
+/* configure SPI/I2S data frame format */
+void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
+/* SPI transmit data */
+void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
+/* SPI receive data */
+uint16_t spi_i2s_data_receive(uint32_t spi_periph);
+/* configure SPI bidirectional transfer direction */
+void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
+
+/* SPI CRC functions */
+/* set SPI CRC polynomial */
+void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
+/* get SPI CRC polynomial */
+uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
+/* turn on SPI CRC function */
+void spi_crc_on(uint32_t spi_periph);
+/* turn off SPI CRC function */
+void spi_crc_off(uint32_t spi_periph);
+/* SPI next data is CRC value */
+void spi_crc_next(uint32_t spi_periph);
+/* get SPI CRC send value or receive value */
+uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
+
+/* flag and interrupt functions */
+/* enable SPI and I2S interrupt */
+void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
+/* disable SPI and I2S interrupt */
+void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S interrupt status */
+FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
+/* get SPI and I2S flag status */
+FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
+/* clear SPI CRC error flag status */
+void spi_crc_error_clear(uint32_t spi_periph);
+
+/* enable quad wire SPI */
+void qspi_enable(uint32_t spi_periph);
+/* disable quad wire SPI */
+void qspi_disable(uint32_t spi_periph);
+/* enable quad wire SPI write */
+void qspi_write_enable(uint32_t spi_periph);
+/* enable quad wire SPI read */
+void qspi_read_enable(uint32_t spi_periph);
+/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
+void qspi_io23_output_enable(uint32_t spi_periph);
+/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
+void qspi_io23_output_disable(uint32_t spi_periph);
+
+#endif /* GD32F20X_SPI_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_timer.h

@@ -0,0 +1,732 @@
+/*!
+    \file  gd32f20x_timer.h
+    \brief definitions for the TIMER
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_TIMER_H
+#define GD32F20X_TIMER_H
+
+#include "gd32f20x.h"
+
+/* TIMERx(x=0..13) definitions */
+#define TIMER0                           (TIMER_BASE + 0x00012C00U)
+#define TIMER1                           (TIMER_BASE + 0x00000000U)
+#define TIMER2                           (TIMER_BASE + 0x00000400U)
+#define TIMER3                           (TIMER_BASE + 0x00000800U)
+#define TIMER4                           (TIMER_BASE + 0x00000C00U)
+#define TIMER5                           (TIMER_BASE + 0x00001000U)
+#define TIMER6                           (TIMER_BASE + 0x00001400U)
+#define TIMER7                           (TIMER_BASE + 0x00013400U)
+#define TIMER8                           (TIMER_BASE + 0x00014C00U)
+#define TIMER9                           (TIMER_BASE + 0x00015000U)
+#define TIMER10                          (TIMER_BASE + 0x00015400U)
+#define TIMER11                          (TIMER_BASE + 0x00001800U)
+#define TIMER12                          (TIMER_BASE + 0x00001C00U)
+#define TIMER13                          (TIMER_BASE + 0x00002000U)
+
+/* registers definitions */
+#define TIMER_CTL0(timerx)               REG32((timerx) + 0x00U)           /*!< TIMER control register 0 */
+#define TIMER_CTL1(timerx)               REG32((timerx) + 0x04U)           /*!< TIMER control register 1 */
+#define TIMER_SMCFG(timerx)              REG32((timerx) + 0x08U)           /*!< TIMER slave mode configuration register */
+#define TIMER_DMAINTEN(timerx)           REG32((timerx) + 0x0CU)           /*!< TIMER DMA and interrupt enable register */
+#define TIMER_INTF(timerx)               REG32((timerx) + 0x10U)           /*!< TIMER interrupt flag register */
+#define TIMER_SWEVG(timerx)              REG32((timerx) + 0x14U)           /*!< TIMER software event generation register */
+#define TIMER_CHCTL0(timerx)             REG32((timerx) + 0x18U)           /*!< TIMER channel control register 0 */
+#define TIMER_CHCTL1(timerx)             REG32((timerx) + 0x1CU)           /*!< TIMER channel control register 1 */
+#define TIMER_CHCTL2(timerx)             REG32((timerx) + 0x20U)           /*!< TIMER channel control register 2 */
+#define TIMER_CNT(timerx)                REG32((timerx) + 0x24U)           /*!< TIMER counter register */
+#define TIMER_PSC(timerx)                REG32((timerx) + 0x28U)           /*!< TIMER prescaler register */
+#define TIMER_CAR(timerx)                REG32((timerx) + 0x2CU)           /*!< TIMER counter auto reload register */
+#define TIMER_CREP(timerx)               REG32((timerx) + 0x30U)           /*!< TIMER counter repetition register */
+#define TIMER_CH0CV(timerx)              REG32((timerx) + 0x34U)           /*!< TIMER channel 0 capture/compare value register */
+#define TIMER_CH1CV(timerx)              REG32((timerx) + 0x38U)           /*!< TIMER channel 1 capture/compare value register */
+#define TIMER_CH2CV(timerx)              REG32((timerx) + 0x3CU)           /*!< TIMER channel 2 capture/compare value register */
+#define TIMER_CH3CV(timerx)              REG32((timerx) + 0x40U)           /*!< TIMER channel 3 capture/compare value register */
+#define TIMER_CCHP(timerx)               REG32((timerx) + 0x44U)           /*!< TIMER channel complementary protection register */
+#define TIMER_DMACFG(timerx)             REG32((timerx) + 0x48U)           /*!< TIMER DMA configuration register */
+#define TIMER_DMATB(timerx)              REG32((timerx) + 0x4CU)           /*!< TIMER DMA transfer buffer register */
+
+/* bits definitions */
+/* TIMER_CTL0 */
+#define TIMER_CTL0_CEN                   BIT(0)              /*!< TIMER counter enable */
+#define TIMER_CTL0_UPDIS                 BIT(1)              /*!< update disable */
+#define TIMER_CTL0_UPS                   BIT(2)              /*!< update source */
+#define TIMER_CTL0_SPM                   BIT(3)              /*!< single pulse mode */
+#define TIMER_CTL0_DIR                   BIT(4)              /*!< timer counter direction */
+#define TIMER_CTL0_CAM                   BITS(5,6)           /*!< center-aligned mode selection */
+#define TIMER_CTL0_ARSE                  BIT(7)              /*!< auto-reload shadow enable */
+#define TIMER_CTL0_CKDIV                 BITS(8,9)           /*!< clock division */
+
+/* TIMER_CTL1 */
+#define TIMER_CTL1_CCSE                  BIT(0)              /*!< commutation control shadow enable */
+#define TIMER_CTL1_CCUC                  BIT(2)              /*!< commutation control shadow register update control */
+#define TIMER_CTL1_DMAS                  BIT(3)              /*!< DMA request source selection */
+#define TIMER_CTL1_MMC                   BITS(4,6)           /*!< master mode control */
+#define TIMER_CTL1_TI0S                  BIT(7)              /*!< channel 0 trigger input selection(hall mode selection) */
+#define TIMER_CTL1_ISO0                  BIT(8)              /*!< idle state of channel 0 output */
+#define TIMER_CTL1_ISO0N                 BIT(9)              /*!< idle state of channel 0 complementary output */
+#define TIMER_CTL1_ISO1                  BIT(10)             /*!< idle state of channel 1 output */
+#define TIMER_CTL1_ISO1N                 BIT(11)             /*!< idle state of channel 1 complementary output */
+#define TIMER_CTL1_ISO2                  BIT(12)             /*!< idle state of channel 2 output */
+#define TIMER_CTL1_ISO2N                 BIT(13)             /*!< idle state of channel 2 complementary output */
+#define TIMER_CTL1_ISO3                  BIT(14)             /*!< idle state of channel 3 output */
+
+/* TIMER_SMCFG */
+#define TIMER_SMCFG_SMC                  BITS(0,2)           /*!< slave mode control */
+#define TIMER_SMCFG_TRGS                 BITS(4,6)           /*!< trigger selection */
+#define TIMER_SMCFG_MSM                  BIT(7)              /*!< master-slave mode */
+#define TIMER_SMCFG_ETFC                 BITS(8,11)          /*!< external trigger filter control */
+#define TIMER_SMCFG_ETPSC                BITS(12,13)         /*!< external trigger prescaler */
+#define TIMER_SMCFG_SMC1                 BIT(14)             /*!< part of SMC for enable external clock mode 1 */
+#define TIMER_SMCFG_ETP                  BIT(15)             /*!< external trigger polarity */
+ 
+/* TIMER_DMAINTEN */
+#define TIMER_DMAINTEN_UPIE              BIT(0)              /*!< update interrupt enable */
+#define TIMER_DMAINTEN_CH0IE             BIT(1)              /*!< channel 0 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH1IE             BIT(2)              /*!< channel 1 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH2IE             BIT(3)              /*!< channel 2 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CH3IE             BIT(4)              /*!< channel 3 capture/compare interrupt enable */
+#define TIMER_DMAINTEN_CMTIE             BIT(5)              /*!< commutation interrupt request enable */
+#define TIMER_DMAINTEN_TRGIE             BIT(6)              /*!< trigger interrupt enable */
+#define TIMER_DMAINTEN_BRKIE             BIT(7)              /*!< break interrupt enable */
+#define TIMER_DMAINTEN_UPDEN             BIT(8)              /*!< update DMA request enable */
+#define TIMER_DMAINTEN_CH0DEN            BIT(9)              /*!< channel 0 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH1DEN            BIT(10)             /*!< channel 1 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH2DEN            BIT(11)             /*!< channel 2 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CH3DEN            BIT(12)             /*!< channel 3 capture/compare DMA request enable */
+#define TIMER_DMAINTEN_CMTDEN            BIT(13)             /*!< commutation DMA request enable */
+#define TIMER_DMAINTEN_TRGDEN            BIT(14)             /*!< trigger DMA request enable */
+
+/* TIMER_INTF */
+#define TIMER_INTF_UPIF                  BIT(0)              /*!< update interrupt flag */
+#define TIMER_INTF_CH0IF                 BIT(1)              /*!< channel 0 capture/compare interrupt flag */
+#define TIMER_INTF_CH1IF                 BIT(2)              /*!< channel 1 capture/compare interrupt flag */
+#define TIMER_INTF_CH2IF                 BIT(3)              /*!< channel 2 capture/compare interrupt flag */
+#define TIMER_INTF_CH3IF                 BIT(4)              /*!< channel 3 capture/compare interrupt flag */
+#define TIMER_INTF_CMTIF                 BIT(5)              /*!< channel commutation interrupt flag */
+#define TIMER_INTF_TRGIF                 BIT(6)              /*!< trigger interrupt flag */
+#define TIMER_INTF_BRKIF                 BIT(7)              /*!< break interrupt flag */
+#define TIMER_INTF_CH0OF                 BIT(9)              /*!< channel 0 over capture flag */
+#define TIMER_INTF_CH1OF                 BIT(10)             /*!< channel 1 over capture flag */
+#define TIMER_INTF_CH2OF                 BIT(11)             /*!< channel 2 over capture flag */
+#define TIMER_INTF_CH3OF                 BIT(12)             /*!< channel 3 over capture flag */
+
+/* TIMER_SWEVG */
+#define TIMER_SWEVG_UPG                  BIT(0)              /*!< update event generate */
+#define TIMER_SWEVG_CH0G                 BIT(1)              /*!< channel 0 capture or compare event generation */
+#define TIMER_SWEVG_CH1G                 BIT(2)              /*!< channel 1 capture or compare event generation */
+#define TIMER_SWEVG_CH2G                 BIT(3)              /*!< channel 2 capture or compare event generation */
+#define TIMER_SWEVG_CH3G                 BIT(4)              /*!< channel 3 capture or compare event generation */
+#define TIMER_SWEVG_CMTG                 BIT(5)              /*!< channel commutation event generation */
+#define TIMER_SWEVG_TRGG                 BIT(6)              /*!< trigger event generation */
+#define TIMER_SWEVG_BRKG                 BIT(7)              /*!< break event generation */
+
+/* TIMER_CHCTL0 */
+/* output compare mode */
+#define TIMER_CHCTL0_CH0MS               BITS(0,1)           /*!< channel 0 mode selection */
+#define TIMER_CHCTL0_CH0COMFEN           BIT(2)              /*!< channel 0 output compare fast enable */
+#define TIMER_CHCTL0_CH0COMSEN           BIT(3)              /*!< channel 0 output compare shadow enable */
+#define TIMER_CHCTL0_CH0COMCTL           BITS(4,6)           /*!< channel 0 output compare control  */
+#define TIMER_CHCTL0_CH0COMCEN           BIT(7)              /*!< channel 0 output compare clear enable */
+#define TIMER_CHCTL0_CH1MS               BITS(8,9)           /*!< channel 1 mode selection */
+#define TIMER_CHCTL0_CH1COMFEN           BIT(10)             /*!< channel 1 output compare fast enable */
+#define TIMER_CHCTL0_CH1COMSEN           BIT(11)             /*!< channel 1 output compare shadow enable */
+#define TIMER_CHCTL0_CH1COMCTL           BITS(12,14)         /*!< channel 1 output compare control  */
+#define TIMER_CHCTL0_CH1COMCEN           BIT(15)             /*!< channel 1 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL0_CH0CAPPSC           BITS(2,3)           /*!< channel 0 input capture prescaler */
+#define TIMER_CHCTL0_CH0CAPFLT           BITS(4,7)           /*!< channel 0 input capture filter control */
+#define TIMER_CHCTL0_CH1CAPPSC           BITS(10,11)         /*!< channel 1 input capture prescaler */
+#define TIMER_CHCTL0_CH1CAPFLT           BITS(12,15)         /*!< channel 1 input capture filter control */
+
+/* TIMER_CHCTL1 */
+/* output compare mode */
+#define TIMER_CHCTL1_CH2MS               BITS(0,1)           /*!< channel 2 mode selection */
+#define TIMER_CHCTL1_CH2COMFEN           BIT(2)              /*!< channel 2 output compare fast enable */
+#define TIMER_CHCTL1_CH2COMSEN           BIT(3)              /*!< channel 2 output compare shadow enable */
+#define TIMER_CHCTL1_CH2COMCTL           BITS(4,6)           /*!< channel 2 output compare control */
+#define TIMER_CHCTL1_CH2COMCEN           BIT(7)              /*!< channel 2 output compare clear enable */
+#define TIMER_CHCTL1_CH3MS               BITS(8,9)           /*!< channel 3 mode selection */
+#define TIMER_CHCTL1_CH3COMFEN           BIT(10)             /*!< channel 3 output compare fast enable */
+#define TIMER_CHCTL1_CH3COMSEN           BIT(11)             /*!< channel 3 output compare shadow enable */
+#define TIMER_CHCTL1_CH3COMCTL           BITS(12,14)         /*!< channel 3 output compare control */
+#define TIMER_CHCTL1_CH3COMCEN           BIT(15)             /*!< channel 3 output compare clear enable */
+/* input capture mode */
+#define TIMER_CHCTL1_CH2CAPPSC           BITS(2,3)           /*!< channel 2 input capture prescaler */
+#define TIMER_CHCTL1_CH2CAPFLT           BITS(4,7)           /*!< channel 2 input capture filter control */
+#define TIMER_CHCTL1_CH3CAPPSC           BITS(10,11)         /*!< channel 3 input capture prescaler */
+#define TIMER_CHCTL1_CH3CAPFLT           BITS(12,15)         /*!< channel 3 input capture filter control */
+
+/* TIMER_CHCTL2 */
+#define TIMER_CHCTL2_CH0EN               BIT(0)              /*!< channel 0 capture/compare function enable */
+#define TIMER_CHCTL2_CH0P                BIT(1)              /*!< channel 0 capture/compare function polarity */
+#define TIMER_CHCTL2_CH0NEN              BIT(2)              /*!< channel 0 complementary output enable */
+#define TIMER_CHCTL2_CH0NP               BIT(3)              /*!< channel 0 complementary output polarity */
+#define TIMER_CHCTL2_CH1EN               BIT(4)              /*!< channel 1 capture/compare function enable  */
+#define TIMER_CHCTL2_CH1P                BIT(5)              /*!< channel 1 capture/compare function polarity */
+#define TIMER_CHCTL2_CH1NEN              BIT(6)              /*!< channel 1 complementary output enable */
+#define TIMER_CHCTL2_CH1NP               BIT(7)              /*!< channel 1 complementary output polarity */
+#define TIMER_CHCTL2_CH2EN               BIT(8)              /*!< channel 2 capture/compare function enable  */
+#define TIMER_CHCTL2_CH2P                BIT(9)              /*!< channel 2 capture/compare function polarity */
+#define TIMER_CHCTL2_CH2NEN              BIT(10)             /*!< channel 2 complementary output enable */
+#define TIMER_CHCTL2_CH2NP               BIT(11)             /*!< channel 2 complementary output polarity */
+#define TIMER_CHCTL2_CH3EN               BIT(12)             /*!< channel 3 capture/compare function enable  */
+#define TIMER_CHCTL2_CH3P                BIT(13)             /*!< channel 3 capture/compare function polarity */
+
+/* TIMER_CNT */
+#define TIMER_CNT_CNT                    BITS(0,15)          /*!< 16 bit timer counter */
+
+/* TIMER_PSC */
+#define TIMER_PSC_PSC                    BITS(0,15)          /*!< prescaler value of the counter clock */
+
+/* TIMER_CAR */
+#define TIMER_CAR_CARL                   BITS(0,15)          /*!< 16 bit counter auto reload value */
+
+/* TIMER_CREP */
+#define TIMER_CREP_CREP                  BITS(0,7)           /*!< counter repetition value */
+
+/* TIMER_CH0CV */
+#define TIMER_CH0CV_CH0VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 0 */
+
+/* TIMER_CH1CV */
+#define TIMER_CH1CV_CH1VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 1 */
+
+/* TIMER_CH2CV */
+#define TIMER_CH2CV_CH2VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 2 */
+
+/* TIMER_CH3CV */
+#define TIMER_CH3CV_CH3VAL               BITS(0,15)          /*!< 16 bit capture/compare value of channel 3 */
+
+/* TIMER_CCHP */
+#define TIMER_CCHP_DTCFG                 BITS(0,7)           /*!< dead time configure */
+#define TIMER_CCHP_PROT                  BITS(8,9)           /*!< complementary register protect control */
+#define TIMER_CCHP_IOS                   BIT(10)             /*!< idle mode off-state configure */
+#define TIMER_CCHP_ROS                   BIT(11)             /*!< run mode off-state configure */
+#define TIMER_CCHP_BRKEN                 BIT(12)             /*!< break enable */
+#define TIMER_CCHP_BRKP                  BIT(13)             /*!< break polarity */
+#define TIMER_CCHP_OAEN                  BIT(14)             /*!< output automatic enable */
+#define TIMER_CCHP_POEN                  BIT(15)             /*!< primary output enable */
+
+/* TIMER_DMACFG */
+#define TIMER_DMACFG_DMATA               BITS(0,4)           /*!< DMA transfer access start address */
+#define TIMER_DMACFG_DMATC               BITS(8,12)          /*!< DMA transfer count */
+
+/* TIMER_DMATB */
+#define TIMER_DMATB_DMATB                BITS(0,15)          /*!< DMA transfer buffer address */
+
+/* constants definitions */
+/* TIMER init parameter structure definitions */
+typedef struct
+{ 
+    uint16_t prescaler;                         /*!< prescaler value */
+    uint16_t alignedmode;                       /*!< aligned mode */
+    uint16_t counterdirection;                  /*!< counter direction */
+    uint32_t period;                            /*!< period value */
+    uint16_t clockdivision;                     /*!< clock division value */
+    uint8_t  repetitioncounter;                 /*!< the counter repetition value */
+}timer_parameter_struct;
+
+/* break parameter structure definitions*/
+typedef struct
+{ 
+    uint16_t runoffstate;                       /*!< run mode off-state */
+    uint16_t ideloffstate;                      /*!< idle mode off-state */
+    uint16_t deadtime;                          /*!< dead time */
+    uint16_t breakpolarity;                     /*!< break polarity */
+    uint16_t outputautostate;                   /*!< output automatic enable */
+    uint16_t protectmode;                       /*!< complementary register protect control */
+    uint16_t breakstate;                        /*!< break enable */
+}timer_break_parameter_struct;
+
+/* channel output parameter structure definitions */
+typedef struct
+{ 
+    uint16_t outputstate;                       /*!< channel output state */
+    uint16_t outputnstate;                      /*!< channel complementary output state */
+    uint16_t ocpolarity;                        /*!< channel output polarity */
+    uint16_t ocnpolarity;                       /*!< channel complementary output polarity */
+    uint16_t ocidlestate;                       /*!< idle state of channel output */
+    uint16_t ocnidlestate;                      /*!< idle state of channel complementary output */
+}timer_oc_parameter_struct;
+
+/* channel input parameter structure definitions */
+typedef struct
+{ 
+    uint16_t icpolarity;                        /*!< channel input polarity */
+    uint16_t icselection;                       /*!< channel input mode selection */
+    uint16_t icprescaler;                       /*!< channel input capture prescaler */
+    uint16_t icfilter;                          /*!< channel input capture filter control */
+}timer_ic_parameter_struct;
+
+/* TIMER interrupt enable or disable */
+#define TIMER_INT_UP                        TIMER_DMAINTEN_UPIE                     /*!< update interrupt */
+#define TIMER_INT_CH0                       TIMER_DMAINTEN_CH0IE                    /*!< channel 0 interrupt */
+#define TIMER_INT_CH1                       TIMER_DMAINTEN_CH1IE                    /*!< channel 1 interrupt */
+#define TIMER_INT_CH2                       TIMER_DMAINTEN_CH2IE                    /*!< channel 2 interrupt */
+#define TIMER_INT_CH3                       TIMER_DMAINTEN_CH3IE                    /*!< channel 3 interrupt */
+#define TIMER_INT_CMT                       TIMER_DMAINTEN_CMTIE                    /*!< channel commutation interrupt flag */
+#define TIMER_INT_TRG                       TIMER_DMAINTEN_TRGIE                    /*!< trigger interrupt */
+#define TIMER_INT_BRK                       TIMER_DMAINTEN_BRKIE                    /*!< break interrupt */
+
+/* TIMER interrupt flag */
+#define TIMER_INT_FLAG_UP                   TIMER_INT_UP                            /*!< update interrupt */
+#define TIMER_INT_FLAG_CH0                  TIMER_INT_CH0                           /*!< channel 0 interrupt */
+#define TIMER_INT_FLAG_CH1                  TIMER_INT_CH1                           /*!< channel 1 interrupt */
+#define TIMER_INT_FLAG_CH2                  TIMER_INT_CH2                           /*!< channel 2 interrupt */
+#define TIMER_INT_FLAG_CH3                  TIMER_INT_CH3                           /*!< channel 3 interrupt */
+#define TIMER_INT_FLAG_CMT                  TIMER_INT_CMT                           /*!< channel commutation interrupt flag */
+#define TIMER_INT_FLAG_TRG                  TIMER_INT_TRG                           /*!< trigger interrupt */
+#define TIMER_INT_FLAG_BRK                  TIMER_INT_BRK  
+
+/* TIMER flag */
+#define TIMER_FLAG_UP                       TIMER_INTF_UPIF                         /*!< update flag */
+#define TIMER_FLAG_CH0                      TIMER_INTF_CH0IF                        /*!< channel 0 flag */
+#define TIMER_FLAG_CH1                      TIMER_INTF_CH1IF                        /*!< channel 1 flag */
+#define TIMER_FLAG_CH2                      TIMER_INTF_CH2IF                        /*!< channel 2 flag */
+#define TIMER_FLAG_CH3                      TIMER_INTF_CH3IF                        /*!< channel 3 flag */
+#define TIMER_FLAG_CMT                      TIMER_INTF_CMTIF                        /*!< channel commutation flag */
+#define TIMER_FLAG_TRG                      TIMER_INTF_TRGIF                        /*!< trigger flag */
+#define TIMER_FLAG_BRK                      TIMER_INTF_BRKIF                        /*!< break flag */
+#define TIMER_FLAG_CH0O                     TIMER_INTF_CH0OF                        /*!< channel 0 overcapture flag */
+#define TIMER_FLAG_CH1O                     TIMER_INTF_CH1OF                        /*!< channel 1 overcapture flag */
+#define TIMER_FLAG_CH2O                     TIMER_INTF_CH2OF                        /*!< channel 2 overcapture flag */
+#define TIMER_FLAG_CH3O                     TIMER_INTF_CH3OF                        /*!< channel 3 overcapture flag */
+
+/* TIMER DMA source enable */
+#define TIMER_DMA_UPD                       ((uint16_t)TIMER_DMAINTEN_UPDEN)        /*!< update DMA enable */
+#define TIMER_DMA_CH0D                      ((uint16_t)TIMER_DMAINTEN_CH0DEN)       /*!< channel 0 DMA enable */
+#define TIMER_DMA_CH1D                      ((uint16_t)TIMER_DMAINTEN_CH1DEN)       /*!< channel 1 DMA enable */
+#define TIMER_DMA_CH2D                      ((uint16_t)TIMER_DMAINTEN_CH2DEN)       /*!< channel 2 DMA enable */
+#define TIMER_DMA_CH3D                      ((uint16_t)TIMER_DMAINTEN_CH3DEN)       /*!< channel 3 DMA enable */
+#define TIMER_DMA_CMTD                      ((uint16_t)TIMER_DMAINTEN_CMTDEN)       /*!< commutation DMA request enable */
+#define TIMER_DMA_TRGD                      ((uint16_t)TIMER_DMAINTEN_TRGDEN)       /*!< trigger DMA enable */
+
+/* channel DMA request source selection */ 
+#define TIMER_DMAREQUEST_UPDATEEVENT        TIMER_CTL1_DMAS                         /*!< DMA request of channel n is sent when update event occurs */
+#define TIMER_DMAREQUEST_CHANNELEVENT       ((uint32_t)0x00000000U)                 /*!< DMA request of channel n is sent when channel n event occurs */
+
+/* DMA access base address */
+#define DMACFG_DMATA(regval)                (BITS(0, 4) & ((uint32_t)(regval) << 0U))
+#define TIMER_DMACFG_DMATA_CTL0             DMACFG_DMATA(0)                         /*!< DMA transfer address is TIMER_CTL0 */
+#define TIMER_DMACFG_DMATA_CTL1             DMACFG_DMATA(1)                         /*!< DMA transfer address is TIMER_CTL1 */
+#define TIMER_DMACFG_DMATA_SMCFG            DMACFG_DMATA(2)                         /*!< DMA transfer address is TIMER_SMCFG */
+#define TIMER_DMACFG_DMATA_DMAINTEN         DMACFG_DMATA(3)                         /*!< DMA transfer address is TIMER_DMAINTEN */
+#define TIMER_DMACFG_DMATA_INTF             DMACFG_DMATA(4)                         /*!< DMA transfer address is TIMER_INTF */
+#define TIMER_DMACFG_DMATA_SWEVG            DMACFG_DMATA(5)                         /*!< DMA transfer address is TIMER_SWEVG */
+#define TIMER_DMACFG_DMATA_CHCTL0           DMACFG_DMATA(6)                         /*!< DMA transfer address is TIMER_CHCTL0 */
+#define TIMER_DMACFG_DMATA_CHCTL1           DMACFG_DMATA(7)                         /*!< DMA transfer address is TIMER_CHCTL1 */
+#define TIMER_DMACFG_DMATA_CHCTL2           DMACFG_DMATA(8)                         /*!< DMA transfer address is TIMER_CHCTL2 */
+#define TIMER_DMACFG_DMATA_CNT              DMACFG_DMATA(9)                         /*!< DMA transfer address is TIMER_CNT */
+#define TIMER_DMACFG_DMATA_PSC              DMACFG_DMATA(10)                        /*!< DMA transfer address is TIMER_PSC */
+#define TIMER_DMACFG_DMATA_CAR              DMACFG_DMATA(11)                        /*!< DMA transfer address is TIMER_CAR */
+#define TIMER_DMACFG_DMATA_CREP             DMACFG_DMATA(12)                        /*!< DMA transfer address is TIMER_CREP */
+#define TIMER_DMACFG_DMATA_CH0CV            DMACFG_DMATA(13)                        /*!< DMA transfer address is TIMER_CH0CV */
+#define TIMER_DMACFG_DMATA_CH1CV            DMACFG_DMATA(14)                        /*!< DMA transfer address is TIMER_CH1CV */
+#define TIMER_DMACFG_DMATA_CH2CV            DMACFG_DMATA(15)                        /*!< DMA transfer address is TIMER_CH2CV */
+#define TIMER_DMACFG_DMATA_CH3CV            DMACFG_DMATA(16)                        /*!< DMA transfer address is TIMER_CH3CV */
+#define TIMER_DMACFG_DMATA_CCHP             DMACFG_DMATA(17)                        /*!< DMA transfer address is TIMER_CCHP */
+#define TIMER_DMACFG_DMATA_DMACFG           DMACFG_DMATA(18)                        /*!< DMA transfer address is TIMER_DMACFG */
+#define TIMER_DMACFG_DMATA_DMATB            DMACFG_DMATA(19)                        /*!< DMA transfer address is TIMER_DMATB */
+
+/* DMA access burst length */
+#define DMACFG_DMATC(regval)                (BITS(8, 12) & ((uint32_t)(regval) << 8U))
+#define TIMER_DMACFG_DMATC_1TRANSFER        DMACFG_DMATC(0)                         /*!< DMA transfer 1 time */
+#define TIMER_DMACFG_DMATC_2TRANSFER        DMACFG_DMATC(1)                         /*!< DMA transfer 2 times */
+#define TIMER_DMACFG_DMATC_3TRANSFER        DMACFG_DMATC(2)                         /*!< DMA transfer 3 times */
+#define TIMER_DMACFG_DMATC_4TRANSFER        DMACFG_DMATC(3)                         /*!< DMA transfer 4 times */
+#define TIMER_DMACFG_DMATC_5TRANSFER        DMACFG_DMATC(4)                         /*!< DMA transfer 5 times */
+#define TIMER_DMACFG_DMATC_6TRANSFER        DMACFG_DMATC(5)                         /*!< DMA transfer 6 times */
+#define TIMER_DMACFG_DMATC_7TRANSFER        DMACFG_DMATC(6)                         /*!< DMA transfer 7 times */
+#define TIMER_DMACFG_DMATC_8TRANSFER        DMACFG_DMATC(7)                         /*!< DMA transfer 8 times */
+#define TIMER_DMACFG_DMATC_9TRANSFER        DMACFG_DMATC(8)                         /*!< DMA transfer 9 times */
+#define TIMER_DMACFG_DMATC_10TRANSFER       DMACFG_DMATC(9)                         /*!< DMA transfer 10 times */
+#define TIMER_DMACFG_DMATC_11TRANSFER       DMACFG_DMATC(10)                        /*!< DMA transfer 11 times */
+#define TIMER_DMACFG_DMATC_12TRANSFER       DMACFG_DMATC(11)                        /*!< DMA transfer 12 times */
+#define TIMER_DMACFG_DMATC_13TRANSFER       DMACFG_DMATC(12)                        /*!< DMA transfer 13 times */
+#define TIMER_DMACFG_DMATC_14TRANSFER       DMACFG_DMATC(13)                        /*!< DMA transfer 14 times */
+#define TIMER_DMACFG_DMATC_15TRANSFER       DMACFG_DMATC(14)                        /*!< DMA transfer 15 times */
+#define TIMER_DMACFG_DMATC_16TRANSFER       DMACFG_DMATC(15)                        /*!< DMA transfer 16 times */
+#define TIMER_DMACFG_DMATC_17TRANSFER       DMACFG_DMATC(16)                        /*!< DMA transfer 17 times */
+#define TIMER_DMACFG_DMATC_18TRANSFER       DMACFG_DMATC(17)                        /*!< DMA transfer 18 times */
+
+/* TIMER software event generation source */
+#define TIMER_EVENT_SRC_UPG                 ((uint16_t)0x0001U)                     /*!< update event generation */
+#define TIMER_EVENT_SRC_CH0G                ((uint16_t)0x0002U)                     /*!< channel 0 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH1G                ((uint16_t)0x0004U)                     /*!< channel 1 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH2G                ((uint16_t)0x0008U)                     /*!< channel 2 capture or compare event generation */
+#define TIMER_EVENT_SRC_CH3G                ((uint16_t)0x0010U)                     /*!< channel 3 capture or compare event generation */
+#define TIMER_EVENT_SRC_CMTG                ((uint16_t)0x0020U)                     /*!< channel commutation event generation */
+#define TIMER_EVENT_SRC_TRGG                ((uint16_t)0x0040U)                     /*!< trigger event generation */
+#define TIMER_EVENT_SRC_BRKG                ((uint16_t)0x0080U)                     /*!< break event generation */
+
+/* center-aligned mode selection */
+#define CTL0_CAM(regval)                    ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
+#define TIMER_COUNTER_EDGE                  CTL0_CAM(0)                             /*!< edge-aligned mode */
+#define TIMER_COUNTER_CENTER_DOWN           CTL0_CAM(1)                             /*!< center-aligned and counting down assert mode */
+#define TIMER_COUNTER_CENTER_UP             CTL0_CAM(2)                             /*!< center-aligned and counting up assert mode */
+#define TIMER_COUNTER_CENTER_BOTH           CTL0_CAM(3)                             /*!< center-aligned and counting up/down assert mode */
+
+/* TIMER prescaler reload mode */
+#define TIMER_PSC_RELOAD_NOW                TIMER_SWEVG_UPG                         /*!< the prescaler is loaded right now */
+#define TIMER_PSC_RELOAD_UPDATE             ((uint32_t)0x00000000U)                 /*!< the prescaler is loaded at the next update event */
+
+/* count direction */
+#define TIMER_COUNTER_UP                    ((uint16_t)0x0000U)                     /*!< counter up direction */
+#define TIMER_COUNTER_DOWN                  ((uint16_t)TIMER_CTL0_DIR)              /*!< counter down direction */
+
+/* specify division ratio between TIMER clock and dead-time and sampling clock */
+#define CTL0_CKDIV(regval)                  ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CKDIV_DIV1                    CTL0_CKDIV(0)                           /*!< clock division value is 1,fDTS=fTIMER_CK */
+#define TIMER_CKDIV_DIV2                    CTL0_CKDIV(1)                           /*!< clock division value is 2,fDTS= fTIMER_CK/2 */
+#define TIMER_CKDIV_DIV4                    CTL0_CKDIV(2)                           /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
+
+/* single pulse mode */
+#define TIMER_SP_MODE_SINGLE                TIMER_CTL0_SPM                          /*!< single pulse mode */
+#define TIMER_SP_MODE_REPETITIVE            ((uint32_t)0x00000000U)                 /*!< repetitive pulse mode */
+
+/* update source */
+#define TIMER_UPDATE_SRC_REGULAR            TIMER_CTL0_UPS                          /*!< update generate only by counter overflow/underflow */
+#define TIMER_UPDATE_SRC_GLOBAL             ((uint32_t)0x00000000U)                 /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
+
+/* run mode off-state configure */
+#define TIMER_ROS_STATE_ENABLE              ((uint16_t)TIMER_CCHP_ROS)              /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_ROS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */
+
+/* idle mode off-state configure */                                                 
+#define TIMER_IOS_STATE_ENABLE              ((uint16_t)TIMER_CCHP_IOS)              /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
+#define TIMER_IOS_STATE_DISABLE             ((uint16_t)0x0000U)                     /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */
+
+/* break input polarity */
+#define TIMER_BREAK_POLARITY_LOW            ((uint16_t)0x0000U)                     /*!< break input polarity is low */
+#define TIMER_BREAK_POLARITY_HIGH           ((uint16_t)TIMER_CCHP_BRKP)             /*!< break input polarity is high */
+
+/* output automatic enable */
+#define TIMER_OUTAUTO_ENABLE                ((uint16_t)TIMER_CCHP_OAEN)             /*!< output automatic enable */
+#define TIMER_OUTAUTO_DISABLE               ((uint16_t)0x0000U)                     /*!< output automatic disable */
+
+/* complementary register protect control */
+#define CCHP_PROT(regval)                   ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
+#define TIMER_CCHP_PROT_OFF                 CCHP_PROT(0)                            /*!< protect disable */
+#define TIMER_CCHP_PROT_0                   CCHP_PROT(1)                            /*!< PROT mode 0 */
+#define TIMER_CCHP_PROT_1                   CCHP_PROT(2)                            /*!< PROT mode 1 */
+#define TIMER_CCHP_PROT_2                   CCHP_PROT(3)                            /*!< PROT mode 2 */
+
+/* break input enable */
+#define TIMER_BREAK_ENABLE                  ((uint16_t)TIMER_CCHP_BRKEN)            /*!< break input enable */
+#define TIMER_BREAK_DISABLE                 ((uint16_t)0x0000U)                     /*!< break input disable */
+
+/* TIMER channel n(n=0,1,2,3) */
+#define TIMER_CH_0                          ((uint16_t)0x0000U)                     /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */
+#define TIMER_CH_1                          ((uint16_t)0x0001U)                     /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */
+#define TIMER_CH_2                          ((uint16_t)0x0002U)                     /*!< TIMER channel 2(TIMERx(x=0..4,7)) */
+#define TIMER_CH_3                          ((uint16_t)0x0003U)                     /*!< TIMER channel 3(TIMERx(x=0..4,7)) */
+
+/* channel enable state */
+#define TIMER_CCX_ENABLE                    ((uint16_t)0x0001U)                     /*!< channel enable */
+#define TIMER_CCX_DISABLE                   ((uint16_t)0x0000U)                     /*!< channel disable */
+
+/* channel complementary output enable state */
+#define TIMER_CCXN_ENABLE                   ((uint16_t)0x0004U)                     /*!< channel complementary enable */
+#define TIMER_CCXN_DISABLE                  ((uint16_t)0x0000U)                     /*!< channel complementary disable */
+
+/* channel output polarity */
+#define TIMER_OC_POLARITY_HIGH              ((uint16_t)0x0000U)                     /*!< channel output polarity is high */
+#define TIMER_OC_POLARITY_LOW               ((uint16_t)0x0002U)                     /*!< channel output polarity is low */
+
+/* channel complementary output polarity */
+#define TIMER_OCN_POLARITY_HIGH             ((uint16_t)0x0000U)                     /*!< channel complementary output polarity is high */
+#define TIMER_OCN_POLARITY_LOW              ((uint16_t)0x0008U)                     /*!< channel complementary output polarity is low */
+
+/* idle state of channel output */ 
+#define TIMER_OC_IDLE_STATE_HIGH            ((uint16_t)0x0100)                      /*!< idle state of channel output is high */
+#define TIMER_OC_IDLE_STATE_LOW             ((uint16_t)0x0000)                      /*!< idle state of channel output is low */
+
+/* idle state of channel complementary output */ 
+#define TIMER_OCN_IDLE_STATE_HIGH           ((uint16_t)0x0200U)                     /*!< idle state of channel complementary output is high */
+#define TIMER_OCN_IDLE_STATE_LOW            ((uint16_t)0x0000U)                     /*!< idle state of channel complementary output is low */
+
+/* channel output compare mode */
+#define TIMER_OC_MODE_TIMING                ((uint16_t)0x0000U)                     /*!< frozen mode */
+#define TIMER_OC_MODE_ACTIVE                ((uint16_t)0x0010U)                     /*!< set the channel output */
+#define TIMER_OC_MODE_INACTIVE              ((uint16_t)0x0020U)                     /*!< clear the channel output */
+#define TIMER_OC_MODE_TOGGLE                ((uint16_t)0x0030U)                     /*!< toggle on match */
+#define TIMER_OC_MODE_LOW                   ((uint16_t)0x0040U)                     /*!< force low mode */
+#define TIMER_OC_MODE_HIGH                  ((uint16_t)0x0050U)                     /*!< force high mode */
+#define TIMER_OC_MODE_PWM0                  ((uint16_t)0x0060U)                     /*!< PWM0 mode */
+#define TIMER_OC_MODE_PWM1                  ((uint16_t)0x0070U)                     /*!< PWM1 mode*/
+
+/* channel output compare shadow enable */
+#define TIMER_OC_SHADOW_ENABLE              ((uint16_t)0x0008U)                     /*!< channel output shadow state enable */
+#define TIMER_OC_SHADOW_DISABLE             ((uint16_t)0x0000U)                     /*!< channel output shadow state disable */
+
+/* channel output compare fast enable */
+#define TIMER_OC_FAST_ENABLE                ((uint16_t)0x0004)                      /*!< channel output fast function enable */
+#define TIMER_OC_FAST_DISABLE               ((uint16_t)0x0000)                      /*!< channel output fast function disable */
+
+/* channel output compare clear enable */
+#define TIMER_OC_CLEAR_ENABLE               ((uint16_t)0x0080U)                     /*!< channel output clear function enable */
+#define TIMER_OC_CLEAR_DISABLE              ((uint16_t)0x0000U)                     /*!< channel output clear function disable */
+
+/* channel control shadow register update control */ 
+#define TIMER_UPDATECTL_CCU                 ((uint32_t)0x00000000U)                 /*!< the shadow registers update by when CMTG bit is set */
+#define TIMER_UPDATECTL_CCUTRI              TIMER_CTL1_CCUC                         /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
+
+/* channel input capture polarity */
+#define TIMER_IC_POLARITY_RISING            ((uint16_t)0x0000U)                     /*!< input capture rising edge */
+#define TIMER_IC_POLARITY_FALLING           ((uint16_t)0x0002U)                     /*!< input capture falling edge */
+#define TIMER_IC_POLARITY_BOTH_EDGE         ((uint16_t)0x000AU)                     /*!< input capture both edge */
+
+/* timer input capture selection */
+#define TIMER_IC_SELECTION_DIRECTTI         ((uint16_t)0x0001U)                     /*!< channel y is configured as input and icy is mapped on CIy */
+#define TIMER_IC_SELECTION_INDIRECTTI       ((uint16_t)0x0002U)                     /*!< channel y is configured as input and icy is mapped on opposite input */
+#define TIMER_IC_SELECTION_ITS              ((uint16_t)0x0003U)                     /*!< channel y is configured as input and icy is mapped on ITS */
+
+/* channel input capture prescaler */
+#define TIMER_IC_PSC_DIV1                   ((uint16_t)0x0000U)                     /*!< no prescaler */
+#define TIMER_IC_PSC_DIV2                   ((uint16_t)0x0004U)                     /*!< divided by 2 */
+#define TIMER_IC_PSC_DIV4                   ((uint16_t)0x0008U)                     /*!< divided by 4 */
+#define TIMER_IC_PSC_DIV8                   ((uint16_t)0x000CU)                     /*!< divided by 8 */
+
+/* trigger selection */
+#define SMCFG_TRGSEL(regval)                (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_SMCFG_TRGSEL_ITI0             SMCFG_TRGSEL(0)                         /*!< internal trigger 0 */
+#define TIMER_SMCFG_TRGSEL_ITI1             SMCFG_TRGSEL(1)                         /*!< internal trigger 1 */
+#define TIMER_SMCFG_TRGSEL_ITI2             SMCFG_TRGSEL(2)                         /*!< internal trigger 2 */
+#define TIMER_SMCFG_TRGSEL_ITI3             SMCFG_TRGSEL(3)                         /*!< internal trigger 3 */
+#define TIMER_SMCFG_TRGSEL_CI0F_ED          SMCFG_TRGSEL(4)                         /*!< TI0 Edge Detector */
+#define TIMER_SMCFG_TRGSEL_CI0FE0           SMCFG_TRGSEL(5)                         /*!< filtered TIMER input 0 */
+#define TIMER_SMCFG_TRGSEL_CI1FE1           SMCFG_TRGSEL(6)                         /*!< filtered TIMER input 1 */
+#define TIMER_SMCFG_TRGSEL_ETIFP            SMCFG_TRGSEL(7)                         /*!< external trigger */
+
+/* master mode control */
+#define CTL1_MMC(regval)                    (BITS(4, 6) & ((uint32_t)(regval) << 4U))
+#define TIMER_TRI_OUT_SRC_RESET             CTL1_MMC(0)                             /*!< the UPG bit as trigger output */
+#define TIMER_TRI_OUT_SRC_ENABLE            CTL1_MMC(1)                             /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
+#define TIMER_TRI_OUT_SRC_UPDATE            CTL1_MMC(2)                             /*!< update event as trigger output */
+#define TIMER_TRI_OUT_SRC_CH0               CTL1_MMC(3)                             /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */
+#define TIMER_TRI_OUT_SRC_O0CPRE            CTL1_MMC(4)                             /*!< O0CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O1CPRE            CTL1_MMC(5)                             /*!< O1CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O2CPRE            CTL1_MMC(6)                             /*!< O2CPRE as trigger output */
+#define TIMER_TRI_OUT_SRC_O3CPRE            CTL1_MMC(7)                             /*!< O3CPRE as trigger output */
+
+/* slave mode control */
+#define SMCFG_SMC(regval)                   (BITS(0, 2) & ((uint32_t)(regval) << 0U)) 
+#define TIMER_SLAVE_MODE_DISABLE            SMCFG_SMC(0)                            /*!< slave mode disable */
+#define TIMER_ENCODER_MODE0                 SMCFG_SMC(1)                            /*!< encoder mode 0 */
+#define TIMER_ENCODER_MODE1                 SMCFG_SMC(2)                            /*!< encoder mode 1 */
+#define TIMER_ENCODER_MODE2                 SMCFG_SMC(3)                            /*!< encoder mode 2 */
+#define TIMER_SLAVE_MODE_RESTART            SMCFG_SMC(4)                            /*!< restart mode */
+#define TIMER_SLAVE_MODE_PAUSE              SMCFG_SMC(5)                            /*!< pause mode */
+#define TIMER_SLAVE_MODE_EVENT              SMCFG_SMC(6)                            /*!< event mode */
+#define TIMER_SLAVE_MODE_EXTERNAL0          SMCFG_SMC(7)                            /*!< external clock mode 0 */
+
+/* master slave mode selection */ 
+#define TIMER_MASTER_SLAVE_MODE_ENABLE      TIMER_SMCFG_MSM                         /*!< master slave mode enable */
+#define TIMER_MASTER_SLAVE_MODE_DISABLE     ((uint32_t)0x00000000U)                 /*!< master slave mode disable */
+
+/* external trigger prescaler */
+#define SMCFG_ETPSC(regval)                 (BITS(12, 13) & ((uint32_t)(regval) << 12U))
+#define TIMER_EXT_TRI_PSC_OFF               SMCFG_ETPSC(0)                          /*!< no divided */
+#define TIMER_EXT_TRI_PSC_DIV2              SMCFG_ETPSC(1)                          /*!< divided by 2 */
+#define TIMER_EXT_TRI_PSC_DIV4              SMCFG_ETPSC(2)                          /*!< divided by 4 */
+#define TIMER_EXT_TRI_PSC_DIV8              SMCFG_ETPSC(3)                          /*!< divided by 8 */
+
+/* external trigger polarity */
+#define TIMER_ETP_FALLING                   TIMER_SMCFG_ETP                         /*!< active low or falling edge active */
+#define TIMER_ETP_RISING                    ((uint32_t)0x00000000U)                 /*!< active high or rising edge active */
+
+/* channel 0 trigger input selection */ 
+#define TIMER_HALLINTERFACE_ENABLE          TIMER_CTL1_TI0S                         /*!< TIMER hall sensor mode enable */
+#define TIMER_HALLINTERFACE_DISABLE         ((uint32_t)0x00000000U)                 /*!< TIMER hall sensor mode disable */
+
+/* TIMERx(x=0..4,7..13) write CHxVAL register selection */
+#define TIMER_CHVSEL_ENABLE                 ((uint16_t)TIMER_CFG_OUTSEL)            /*!< write CHxVAL register selection enable */
+#define TIMER_CHVSEL_DISABLE                ((uint16_t)0x0000U)                     /*!< write CHxVAL register selection disable */
+
+/* function declarations */
+/* TIMER timebase */
+/* deinit a TIMER */
+void timer_deinit(uint32_t timer_periph);
+/* initialize TIMER init parameter structure */
+void timer_struct_para_init(timer_parameter_struct* initpara);
+/* initialize TIMER counter */
+void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
+/* enable a TIMER */
+void timer_enable(uint32_t timer_periph);
+/* disable a TIMER */
+void timer_disable(uint32_t timer_periph);
+/* enable the auto reload shadow function */
+void timer_auto_reload_shadow_enable(uint32_t timer_periph);
+/* disable the auto reload shadow function */
+void timer_auto_reload_shadow_disable(uint32_t timer_periph);
+/* enable the update event */
+void timer_update_event_enable(uint32_t timer_periph);
+/* disable the update event */
+void timer_update_event_disable(uint32_t timer_periph);
+/* set TIMER counter alignment mode */
+void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
+/* set TIMER counter up direction */
+void timer_counter_up_direction(uint32_t timer_periph);
+/* set TIMER counter down direction */
+void timer_counter_down_direction(uint32_t timer_periph);
+/* configure TIMER prescaler */
+void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload);
+/* configure TIMER repetition register value */
+void timer_repetition_value_config(uint32_t timer_periph, uint8_t repetition);
+/* configure TIMER autoreload register value */
+void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload);
+/* configure TIMER counter register value */
+void timer_counter_value_config(uint32_t timer_periph, uint32_t counter);
+/* read TIMER counter value */
+uint32_t timer_counter_read(uint32_t timer_periph);
+/* read TIMER prescaler value */
+uint16_t timer_prescaler_read(uint32_t timer_periph);
+/* configure TIMER single pulse mode */
+void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
+/* configure TIMER update source */
+void timer_update_source_config(uint32_t timer_periph, uint32_t update);
+
+/* timer DMA and event */
+/* enable the TIMER DMA */
+void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
+/* disable the TIMER DMA */
+void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
+/* channel DMA request source selection */
+void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request);
+/* configure the TIMER DMA transfer */
+void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth);
+/* software generate events */
+void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
+
+/* TIMER channel complementary protection */
+/* initialize TIMER break parameter struct */
+void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
+/* configure TIMER break function */
+void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
+/* enable TIMER break function */
+void timer_break_enable(uint32_t timer_periph);
+/* disable TIMER break function */
+void timer_break_disable(uint32_t timer_periph);
+/* enable TIMER output automatic function */
+void timer_automatic_output_enable(uint32_t timer_periph);
+/* disable TIMER output automatic function */
+void timer_automatic_output_disable(uint32_t timer_periph);
+/* enable or disable TIMER primary output function */
+void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
+/* enable or disable channel capture/compare control shadow register */
+void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
+/* configure TIMER channel control shadow register update control */
+void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl);
+
+/* TIMER channel output */
+/* initialize TIMER channel output parameter struct */
+void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output function */
+void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara);
+/* configure TIMER channel output compare mode */
+void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode);
+/* configure TIMER channel output pulse value */
+void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint16_t pulse);
+/* configure TIMER channel output shadow function */
+void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
+/* configure TIMER channel output fast function */
+void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
+/* configure TIMER channel output clear function */
+void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear);
+/* configure TIMER channel output polarity */
+void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
+/* configure TIMER channel complementary output polarity */
+void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
+/* configure TIMER channel enable state */
+void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
+/* configure TIMER channel complementary output enable state */
+void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
+
+/* TIMER channel input */
+/* initialize TIMER channel input parameter structure */
+void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
+/* configure TIMER input capture parameter */
+void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
+/* configure TIMER channel input capture prescaler value */
+void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
+/* read TIMER channel capture compare register value */
+uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
+/* configure TIMER input pwm capture function */
+void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
+/* configure TIMER hall sensor mode */
+void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
+
+/* TIMER master and slave */
+/* select TIMER input trigger source */
+void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
+/* select TIMER master mode output trigger source */
+void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
+/* select TIMER slave mode */
+void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode);
+/* configure TIMER master slave mode */
+void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
+/* configure TIMER external trigger input */
+void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
+/* configure TIMER quadrature decoder mode */
+void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
+/* configure TIMER internal clock mode */
+void timer_internal_clock_config(uint32_t timer_periph);
+/* configure TIMER the internal trigger as external clock input */
+void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
+/* configure TIMER the external trigger as external clock input */
+void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint8_t extfilter);
+/* configure TIMER the external clock mode 0 */
+void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
+/* configure TIMER the external clock mode 1 */
+void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint8_t extfilter);
+/* disable TIMER the external clock mode 1 */
+void timer_external_clock_mode1_disable(uint32_t timer_periph);
+
+/* TIMER interrupt and flag */
+/* enable the TIMER interrupt */
+void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
+/* disable the TIMER interrupt */
+void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER interrupt flag */
+FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
+/* clear TIMER interrupt flag */
+void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
+/* get TIMER flag */
+FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
+/* clear TIMER flag */
+void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
+
+#endif /* GD32F20X_TIMER_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_tli.h

@@ -0,0 +1,369 @@
+/*!
+    \file  gd32f20x_tli.h
+    \brief definitions for the TLI
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_TLI_H
+#define GD32F20X_TLI_H
+
+#include "gd32f20x.h"
+
+/* TLI definitions */
+#define TLI                               TLI_BASE                    /*!< TLI base address */
+/* TLI layer definitions */
+#define LAYER0                            TLI_BASE                    /*!< Layer0 base address */
+#define LAYER1                            (TLI_BASE + 0x80)           /*!< Layer1 base address */
+
+/* registers definitions */
+#define TLI_SPSZ                          REG32(TLI + 0x08U)          /*!< TLI synchronous pulse size register */
+#define TLI_BPSZ                          REG32(TLI + 0x0CU)          /*!< TLI back-porch size register */
+#define TLI_ASZ                           REG32(TLI + 0x10U)          /*!< TLI active size register */
+#define TLI_TSZ                           REG32(TLI + 0x14U)          /*!< TLI total size register */
+#define TLI_CTL                           REG32(TLI + 0x18U)          /*!< TLI control register */
+#define TLI_RL                            REG32(TLI + 0x24U)          /*!< TLI reload layer register */
+#define TLI_BGC                           REG32(TLI + 0x2CU)          /*!< TLI background color register */
+#define TLI_INTEN                         REG32(TLI + 0x34U)          /*!< TLI interrupt enable register */
+#define TLI_INTF                          REG32(TLI + 0x38U)          /*!< TLI interrupt flag register */
+#define TLI_INTC                          REG32(TLI + 0x3CU)          /*!< TLI interrupt flag clear register */
+#define TLI_LM                            REG32(TLI + 0x40U)          /*!< TLI line mark register */
+#define TLI_CPPOS                         REG32(TLI + 0x44U)          /*!< TLI current pixel position register */
+#define TLI_STAT                          REG32(TLI + 0x48U)          /*!< TLI status register */
+#define TLI_LxCTL(layerx)                 REG32((layerx) + 0x84U)     /*!< TLI layer x control register */
+#define TLI_LxHPOS(layerx)                REG32((layerx) + 0x88U)     /*!< TLI layer x horizontal position parameters register */
+#define TLI_LxVPOS(layerx)                REG32((layerx) + 0x8CU)     /*!< TLI layer x vertical position parameters register */
+#define TLI_LxCKEY(layerx)                REG32((layerx) + 0x90U)     /*!< TLI layer x color key register */
+#define TLI_LxPPF(layerx)                 REG32((layerx) + 0x94U)     /*!< TLI layer x packeted pixel format register */
+#define TLI_LxSA(layerx)                  REG32((layerx) + 0x98U)     /*!< TLI layer x specified alpha register */
+#define TLI_LxDC(layerx)                  REG32((layerx) + 0x9CU)     /*!< TLI layer x default color register */
+#define TLI_LxBLEND(layerx)               REG32((layerx) + 0xA0U)     /*!< TLI layer x blending register */
+#define TLI_LxFBADDR(layerx)              REG32((layerx) + 0xACU)     /*!< TLI layer x frame base address register */
+#define TLI_LxFLLEN(layerx)               REG32((layerx) + 0xB0U)     /*!< TLI layer x frame line length register */
+#define TLI_LxFTLN(layerx)                REG32((layerx) + 0xB4U)     /*!< TLI layer x frame total line number register */
+#define TLI_LxLUT(layerx)                 REG32((layerx) + 0xC4U)     /*!< TLI layer x look up table register */
+
+/* bits definitions */
+/* TLI_SPSZ */
+#define TLI_SPSZ_VPSZ                     BITS(0,11)       /*!< size of the vertical synchronous pulse */
+#define TLI_SPSZ_HPSZ                     BITS(16,27)      /*!< size of the horizontal synchronous pulse */
+
+/* TLI_BPSZ */
+#define TLI_BPSZ_VBPSZ                    BITS(0,11)       /*!< size of the vertical back porch plus synchronous pulse */
+#define TLI_BPSZ_HBPSZ                    BITS(16,27)      /*!< size of the horizontal back porch plus synchronous pulse */
+
+/* TLI_ASZ */
+#define TLI_ASZ_VASZ                      BITS(0,11)       /*!< size of the vertical active area width plus back porch and synchronous pulse */
+#define TLI_ASZ_HASZ                      BITS(16,27)      /*!< size of the horizontal active area width plus back porch and synchronous pulse */
+
+/* TLI_TSZ */
+#define TLI_TSZ_VTSZ                      BITS(0,11)       /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */
+#define TLI_TSZ_HTSZ                      BITS(16,27)      /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */
+
+/* TLI_CTL */
+#define TLI_CTL_TLIEN                     BIT(0)           /*!< TLI enable bit */
+#define TLI_CTL_BDB                       BITS(4,6)        /*!< blue channel dither bits number */
+#define TLI_CTL_GDB                       BITS(8,10)       /*!< green channel dither bits number */
+#define TLI_CTL_RDB                       BITS(12,14)      /*!< red channel dither bits number */
+#define TLI_CTL_DFEN                      BIT(16)          /*!< dither function enable */
+#define TLI_CTL_CLKPS                     BIT(28)          /*!< pixel clock polarity selection */
+#define TLI_CTL_DEPS                      BIT(29)          /*!< data enable polarity selection */
+#define TLI_CTL_VPPS                      BIT(30)          /*!< vertical pulse polarity selection */
+#define TLI_CTL_HPPS                      BIT(31)          /*!< horizontal pulse polarity selection */
+
+/* TLI_RL */
+#define TLI_RL_RQR                        BIT(0)           /*!< request reload */
+#define TLI_RL_FBR                        BIT(1)           /*!< frame blank reload */
+
+/* TLI_BGC */
+#define TLI_BGC_BVB                       BITS(0,7)        /*!< background value blue */
+#define TLI_BGC_BVG                       BITS(8,15)       /*!< background value green */
+#define TLI_BGC_BVR                       BITS(16,23)      /*!< background value red */
+
+/* TLI_INTEN */
+#define TLI_INTEN_LMIE                    BIT(0)           /*!< line mark interrupt enable */
+#define TLI_INTEN_FEIE                    BIT(1)           /*!< FIFO error interrupt enable */
+#define TLI_INTEN_TEIE                    BIT(2)           /*!< transaction error interrupt enable */
+#define TLI_INTEN_LCRIE                   BIT(3)           /*!< layer configuration reloaded interrupt enable */
+
+/* TLI_INTF */
+#define TLI_INTF_LMF                      BIT(0)           /*!< line mark flag */
+#define TLI_INTF_FEF                      BIT(1)           /*!< FIFO error flag */
+#define TLI_INTF_TEF                      BIT(2)           /*!< transaction error flag */
+#define TLI_INTF_LCRF                     BIT(3)           /*!< layer configuration reloaded flag */
+
+/* TLI_INTC */
+#define TLI_INTC_LMC                      BIT(0)           /*!< line mark flag clear */
+#define TLI_INTC_FEC                      BIT(1)           /*!< FIFO error flag clear */
+#define TLI_INTC_TEC                      BIT(2)           /*!< transaction error flag clear */
+#define TLI_INTC_LCRC                     BIT(3)           /*!< layer configuration reloaded flag clear */
+
+/* TLI_LM */
+#define TLI_LM_LM                         BITS(0,10)       /*!< line mark value */
+
+/* TLI_CPPOS */
+#define TLI_CPPOS_VPOS                    BITS(0,15)       /*!< vertical position */
+#define TLI_CPPOS_HPOS                    BITS(16,31)      /*!< horizontal position */
+
+/* TLI_STAT */
+#define TLI_STAT_VDE                      BIT(0)           /*!< current VDE status */
+#define TLI_STAT_HDE                      BIT(1)           /*!< current HDE status */
+#define TLI_STAT_VS                       BIT(2)           /*!< current VS status of the TLI */
+#define TLI_STAT_HS                       BIT(3)           /*!< current HS status of the TLI */
+
+/* TLI_LxCTL */
+#define TLI_LxCTL_LEN                     BIT(0)           /*!< layer enable */
+#define TLI_LxCTL_CKEYEN                  BIT(1)           /*!< color keying enable */
+#define TLI_LxCTL_LUTEN                   BIT(4)           /*!< LUT enable */
+
+/* TLI_LxHPOS */
+#define TLI_LxHPOS_WLP                    BITS(0,11)       /*!< window left position */
+#define TLI_LxHPOS_WRP                    BITS(16,27)      /*!< window right position */
+
+/* TLI_LxVPOS */
+#define TLI_LxVPOS_WTP                    BITS(0,11)       /*!< window top position */
+#define TLI_LxVPOS_WBP                    BITS(16,27)      /*!< window bottom position */
+
+/* TLI_LxCKEY */
+#define TLI_LxCKEY_CKEYB                  BITS(0,7)        /*!< color key blue */
+#define TLI_LxCKEY_CKEYG                  BITS(8,15)       /*!< color key green */
+#define TLI_LxCKEY_CKEYR                  BITS(16,23)      /*!< color key red */
+
+/* TLI_LxPPF */
+#define TLI_LxPPF_PPF                     BITS(0,2)        /*!< packeted pixel format */
+
+/* TLI_LxSA */
+#define TLI_LxSA_SA                       BITS(0,7)        /*!< specified alpha */
+
+/* TLI_LxDC */
+#define TLI_LxDC_DCB                      BITS(0,7)        /*!< the default color blue */
+#define TLI_LxDC_DCG                      BITS(8,15)       /*!< the default color green */
+#define TLI_LxDC_DCR                      BITS(16,23)      /*!< the default color red */
+#define TLI_LxDC_DCA                      BITS(24,31)      /*!< the default color alpha */
+
+/* TLI_LxBLEND */
+#define TLI_LxBLEND_ACF2                  BITS(0,2)        /*!< alpha calculation factor 2 of blending method */
+#define TLI_LxBLEND_ACF1                  BITS(8,10)       /*!< alpha calculation factor 1 of blending method */
+
+/* TLI_LxFBADDR */
+#define TLI_LxFBADDR_FBADD                BITS(0,31)       /*!< frame buffer base address */
+
+/* TLI_LxFLLEN */
+#define TLI_LxFLLEN_FLL                   BITS(0,13)       /*!< frame line length */
+#define TLI_LxFLLEN_STDOFF                BITS(16,29)      /*!< frame buffer stride offset */
+
+/* TLI_LxFTLN */
+#define TLI_LxFTLN_FTLN                   BITS(0,10)       /*!< frame total line number */
+
+/* TLI_LxLUT */
+#define TLI_LxLUT_TB                      BITS(0,7)        /*!< blue channel of a LUT entry */
+#define TLI_LxLUT_TG                      BITS(8,15)       /*!< green channel of a LUT entry */
+#define TLI_LxLUT_TR                      BITS(16,23)      /*!< red channel of a LUT entry */
+#define TLI_LxLUT_TADD                    BITS(24,31)      /*!< look up table write address */
+
+/* constants definitions */
+/* TLI parameter structure definitions */
+typedef struct
+{   
+    uint32_t synpsz_vpsz;                     /*!< size of the vertical synchronous pulse */
+    uint32_t synpsz_hpsz;                     /*!< size of the horizontal synchronous pulse */
+    uint32_t backpsz_vbpsz;                   /*!< size of the vertical back porch plus synchronous pulse */
+    uint32_t backpsz_hbpsz;                   /*!< size of the horizontal back porch plus synchronous pulse */
+    uint32_t activesz_vasz;                   /*!< size of the vertical active area width plus back porch and synchronous pulse */
+    uint32_t activesz_hasz;                   /*!< size of the horizontal active area width plus back porch and synchronous pulse */
+    uint32_t totalsz_vtsz;                    /*!< vertical total size of the display */
+    uint32_t totalsz_htsz;                    /*!< horizontal total size of the display */
+    uint32_t backcolor_red;                   /*!< background value red */
+    uint32_t backcolor_green;                 /*!< background value green */
+    uint32_t backcolor_blue;                  /*!< background value blue */
+    uint32_t signalpolarity_hs;               /*!< horizontal pulse polarity selection */
+    uint32_t signalpolarity_vs;               /*!< vertical pulse polarity selection */
+    uint32_t signalpolarity_de;               /*!< data enable polarity selection */
+    uint32_t signalpolarity_pixelck;          /*!< pixel clock polarity selection */
+}tli_parameter_struct; 
+
+/* TLI layer parameter structure definitions */
+typedef struct
+{   
+    uint32_t layer_window_rightpos;           /*!< window right position */
+    uint32_t layer_window_leftpos;            /*!< window left position */
+    uint32_t layer_window_bottompos;          /*!< window bottom position */
+    uint32_t layer_window_toppos;             /*!< window top position */
+    uint32_t layer_ppf;                       /*!< packeted pixel format */
+    uint32_t layer_sa;                        /*!< specified alpha */
+    uint32_t layer_default_alpha;             /*!< the default color alpha */
+    uint32_t layer_default_red;               /*!< the default color red */
+    uint32_t layer_default_green;             /*!< the default color green */
+    uint32_t layer_default_blue;              /*!< the default color blue */
+    uint32_t layer_acf1;                      /*!< alpha calculation factor 1 of blending method */
+    uint32_t layer_acf2;                      /*!< alpha calculation factor 2 of blending method */
+    uint32_t layer_frame_bufaddr;             /*!< frame buffer base address */
+    uint32_t layer_frame_buf_stride_offset;   /*!< frame buffer stride offset */
+    uint32_t layer_frame_line_length;         /*!< frame line length */
+    uint32_t layer_frame_total_line_number;   /*!< frame total line number */
+}tli_layer_parameter_struct; 
+
+/* TLI layer LUT parameter structure definitions */
+typedef struct
+{
+    uint32_t layer_table_addr;                /*!< look up table write address */
+    uint32_t layer_lut_channel_red;           /*!< red channel of a LUT entry */
+    uint32_t layer_lut_channel_green;         /*!< green channel of a LUT entry */
+    uint32_t layer_lut_channel_blue;          /*!< blue channel of a LUT entry */                                                       
+}tli_layer_lut_parameter_struct; 
+
+/* packeted pixel format */
+typedef enum 
+{
+     LAYER_PPF_ARGB8888,                      /*!< layerx packeted pixel format ARGB8888 */
+     LAYER_PPF_RGB888,                        /*!< layerx packeted pixel format RGB888 */
+     LAYER_PPF_RGB565,                        /*!< layerx packeted pixel format RGB565 */
+     LAYER_PPF_ARGB1555,                      /*!< layerx packeted pixel format ARGB1555 */
+     LAYER_PPF_ARGB4444,                      /*!< layerx packeted pixel format ARGB4444 */
+     LAYER_PPF_L8,                            /*!< layerx packeted pixel format L8 */
+     LAYER_PPF_AL44,                          /*!< layerx packeted pixel format AL44 */
+     LAYER_PPF_AL88                           /*!< layerx packeted pixel format AL88 */
+} tli_layer_ppf_enum;
+
+/* TLI flags and states */
+#define TLI_FLAG_VDE                   TLI_STAT_VDE                /*!< current VDE status */
+#define TLI_FLAG_HDE                   TLI_STAT_HDE                /*!< current HDE status */
+#define TLI_FLAG_VS                    TLI_STAT_VS                 /*!< current VS status of the TLI */
+#define TLI_FLAG_HS                    TLI_STAT_HS                 /*!< current HS status of the TLI */
+#define TLI_FLAG_LM                    (BIT(0) | BIT(31))          /*!< line mark interrupt flag */
+#define TLI_FLAG_FE                    (BIT(1) | BIT(31))          /*!< FIFO error interrupt flag */
+#define TLI_FLAG_TE                    (BIT(2) | BIT(31))          /*!< transaction error interrupt flag */
+#define TLI_FLAG_LCR                   (BIT(3) | BIT(31))          /*!< layer configuration reloaded interrupt flag */
+
+/* TLI interrupt enable or disable */
+#define TLI_INT_LM                     BIT(0)                      /*!< line mark interrupt */
+#define TLI_INT_FE                     BIT(1)                      /*!< FIFO error interrupt */
+#define TLI_INT_TE                     BIT(2)                      /*!< transaction error interrupt */
+#define TLI_INT_LCR                    BIT(3)                      /*!< layer configuration reloaded interrupt */
+
+/* TLI interrupt flag */
+#define TLI_INT_FLAG_LM                BIT(0)                      /*!< line mark interrupt flag */
+#define TLI_INT_FLAG_FE                BIT(1)                      /*!< FIFO error interrupt flag */
+#define TLI_INT_FLAG_TE                BIT(2)                      /*!< transaction error interrupt flag */
+#define TLI_INT_FLAG_LCR               BIT(3)                      /*!< layer configuration reloaded interrupt flag */
+
+/* layer reload configure */
+#define TLI_FRAME_BLANK_RELOAD_EN     ((uint8_t)0x00U)             /*!< the layer configuration will be reloaded at frame blank */
+#define TLI_REQUEST_RELOAD_EN         ((uint8_t)0x01U)             /*!< the layer configuration will be reloaded after this bit sets */
+
+/* dither function */
+#define TLI_DITHER_DISABLE            ((uint8_t)0x00U)             /*!< dither function disable */
+#define TLI_DITHER_ENABLE             ((uint8_t)0x01U)             /*!< dither function enable */
+
+/* horizontal pulse polarity selection */
+#define TLI_HSYN_ACTLIVE_LOW          ((uint32_t)0x00000000U)      /*!< horizontal synchronous pulse active low */
+#define TLI_HSYN_ACTLIVE_HIGHT        TLI_CTL_HPPS                 /*!< horizontal synchronous pulse active high */
+
+/* vertical pulse polarity selection */
+#define TLI_VSYN_ACTLIVE_LOW          ((uint32_t)0x00000000U)      /*!< vertical synchronous pulse active low */
+#define TLI_VSYN_ACTLIVE_HIGHT        TLI_CTL_VPPS                 /*!< vertical synchronous pulse active high */
+
+/* pixel clock polarity selection */
+#define TLI_PIXEL_CLOCK_TLI           ((uint32_t)0x00000000U)      /*!< pixel clock is TLI clock */
+#define TLI_PIXEL_CLOCK_INVERTEDTLI   TLI_CTL_CLKPS                /*!< pixel clock is inverted TLI clock */
+
+/* data enable polarity selection */
+#define TLI_DE_ACTLIVE_LOW            ((uint32_t)0x00000000U)      /*!< data enable active low */
+#define TLI_DE_ACTLIVE_HIGHT          TLI_CTL_DEPS                 /*!< data enable active high */
+
+/* alpha calculation factor 1 of blending method */
+#define LxBLEND_ACF1(regval)          (BITS(8,10) & ((regval)<<8))
+#define LAYER_ACF1_SA                 LxBLEND_ACF1(4)              /*!< normalization specified alpha */
+#define LAYER_ACF1_PASA               LxBLEND_ACF1(6)              /*!< normalization pixel alpha * normalization specified alpha */
+
+/* alpha calculation factor 2 of blending method */
+#define LxBLEND_ACF2(regval)          (BITS(0,2) & ((regval)))
+#define LAYER_ACF2_SA                 LxBLEND_ACF2(5)              /*!< normalization specified alpha */
+#define LAYER_ACF2_PASA               LxBLEND_ACF2(7)              /*!< normalization pixel alpha * normalization specified alpha */
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize TLI */
+void tli_deinit(void);
+/* initialize TLI */
+void tli_init(tli_parameter_struct *tli_struct);
+/* configure TLI dither function */
+void tli_dither_config(uint8_t ditherstat);
+/* enable TLI */
+void tli_enable(void);
+/* disable TLI */
+void tli_disable(void);
+/* configure TLI reload mode */
+void tli_reload_config(uint8_t reloadmode);
+
+/* set line mark value */
+void tli_line_mark_set(uint32_t linenum);
+/* get current displayed position */
+uint32_t tli_current_pos_get(void);
+
+/* function configuration */
+/* TLI layer enable */
+void tli_layer_enable(uint32_t layerx);
+/* TLI layer disable */
+void tli_layer_disable(uint32_t layerx);
+/* TLI layer color keying enable */
+void tli_color_key_enable(uint32_t layerx);
+/* TLI layer color keying disable */
+void tli_color_key_disable(uint32_t layerx);
+/* TLI layer LUT enable */
+void tli_lut_enable(uint32_t layerx);
+/* TLI layer LUT disable */
+void tli_lut_disable(uint32_t layerx);
+/* TLI layer initialize */
+void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct);
+/* TLI layer initialize */
+void tli_layer_window_offset_modify(uint32_t layerx,uint32_t offset_x,uint32_t offset_y);
+/* TLI layer LUT initialize */
+void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct);
+/* TLI layer key initialize */
+void tli_ckey_init(uint32_t layerx,uint32_t redkey,uint32_t greenkey,uint32_t bluekey);
+
+/* interrupt & flag functions */
+/* get TLI flag or state */
+FlagStatus tli_flag_get(uint32_t flag);
+/* enable TLI interrupt */
+void tli_interrupt_enable(uint32_t interrupt);
+/* disable TLI interrupt */
+void tli_interrupt_disable(uint32_t interrupt);
+/* get TLI interrupt flag */
+FlagStatus tli_interrupt_flag_get(uint32_t int_flag);
+/* clear TLI interrupt flag */
+void tli_interrupt_flag_clear(uint32_t int_flag);
+
+#endif /* GD32F20X_TLI_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_trng.h

@@ -0,0 +1,106 @@
+/*!
+    \file  gd32f20x_trng.h
+    \brief definitions for the TRNG
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_TRNG_H
+#define GD32F20X_TRNG_H
+
+#include "gd32f20x.h"
+
+/* TRNG definitions */
+#define TRNG                        TRNG_BASE
+
+/* registers definitions */
+#define TRNG_CTL                    REG32(TRNG + 0x00U)        /*!< control register */
+#define TRNG_STAT                   REG32(TRNG + 0x04U)        /*!< status register */
+#define TRNG_DATA                   REG32(TRNG + 0x08U)        /*!< data register */
+
+/* bits definitions */
+/* TRNG_CTL */
+#define TRNG_CTL_TRNGEN             BIT(2)                     /*!< TRNG enable bit */
+#define TRNG_CTL_IE                 BIT(3)                     /*!< interrupt enable bit */
+
+/* TRNG_STAT */
+#define TRNG_STAT_DRDY              BIT(0)                     /*!< random data ready status bit */
+#define TRNG_STAT_CECS              BIT(1)                     /*!< clock error current status */
+#define TRNG_STAT_SECS              BIT(2)                     /*!< seed error current status */
+#define TRNG_STAT_CEIF              BIT(5)                     /*!< clock error interrupt flag */
+#define TRNG_STAT_SEIF              BIT(6)                     /*!< seed error interrupt flag */
+
+/* TRNG_DATA */
+#define TRNG_DATA_TRNDATA           BITS(0,31)                 /*!< 32-Bit Random data */
+
+/* constants definitions */
+/* trng status flag */
+typedef enum
+{ 
+    TRNG_FLAG_DRDY = TRNG_STAT_DRDY,                           /*!< random Data ready status */
+    TRNG_FLAG_CECS = TRNG_STAT_CECS,                           /*!< clock error current status */
+    TRNG_FLAG_SECS = TRNG_STAT_SECS                            /*!< seed error current status */
+}trng_flag_enum;
+
+/* trng inerrupt flag */
+typedef enum
+{
+    TRNG_INT_FLAG_CE = TRNG_STAT_CEIF,                       /*!< clock error interrupt flag */
+    TRNG_INT_FLAG_SE = TRNG_STAT_SEIF                        /*!< seed error interrupt flag */
+}trng_int_flag_enum;
+
+/* function declarations */
+/* initialization functions */
+/* deinitialize the TRNG */
+void trng_deinit(void);
+/* enable the TRNG interface */
+void trng_enable(void);
+/* disable the TRNG interface */
+void trng_disable(void);
+/* get the true random data */
+uint32_t trng_get_true_random_data(void);
+
+/* interrupt & flag functions */
+/* get the trng status flags */
+FlagStatus trng_flag_get(trng_flag_enum flag);
+/* the trng interrupt enable */
+void trng_interrupt_enable(void);
+/* the trng interrupt disable */
+void trng_interrupt_disable(void);
+/* get the trng interrupt flags */
+FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag);
+/* clear the trng interrupt flags */
+void trng_interrupt_flag_clear(trng_int_flag_enum int_flag);
+
+#endif /* GD32F20X_TRNG_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_usart.h

@@ -0,0 +1,450 @@
+/*!
+    \file  gd32f20x_usart.h
+    \brief definitions for the USART
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_USART_H
+#define GD32F20X_USART_H
+
+#include "gd32f20x.h"
+
+/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */
+#define USART1                        USART_BASE                     /*!< USART1 base address */
+#define USART2                        (USART_BASE+0x00000400U)       /*!< USART2 base address */
+#define UART3                         (USART_BASE+0x00000800U)       /*!< UART3 base address */
+#define UART4                         (USART_BASE+0x00000C00U)       /*!< UART4 base address */
+#define UART6                         (USART_BASE+0x00003400U)       /*!< UART6 base address */
+#define UART7                         (USART_BASE+0x00003800U)       /*!< UART7 base address */
+#define USART0                        (USART_BASE+0x0000F400U)       /*!< USART0 base address */
+#define USART5                        (USART_BASE+0x00012C00U)       /*!< USART5 base address */
+
+/* registers definitions */
+#define USART_STAT0(usartx)           REG32((usartx) + 0x00U)        /*!< USART status register 0 */
+#define USART_DATA(usartx)            REG32((usartx) + 0x04U)        /*!< USART data register */
+#define USART_BAUD(usartx)            REG32((usartx) + 0x08U)        /*!< USART baud rate register */
+#define USART_CTL0(usartx)            REG32((usartx) + 0x0CU)        /*!< USART control register 0 */
+#define USART_CTL1(usartx)            REG32((usartx) + 0x10U)        /*!< USART control register 1 */
+#define USART_CTL2(usartx)            REG32((usartx) + 0x14U)        /*!< USART control register 2 */
+#define USART_GP(usartx)              REG32((usartx) + 0x18U)        /*!< USART guard time and prescaler register */
+#define USART_CTL3(usartx)            REG32((usartx) + 0x80U)        /*!< USART control register 3 */
+#define USART_RT(usartx)              REG32((usartx) + 0x84U)        /*!< USART receiver timeout register */
+#define USART_STAT1(usartx)           REG32((usartx) + 0x88U)        /*!< USART status register 1 */
+
+/* bits definitions */
+/* USARTx_STAT0 */
+#define USART_STAT0_PERR              BIT(0)       /*!< parity error flag */
+#define USART_STAT0_FERR              BIT(1)       /*!< frame error flag */
+#define USART_STAT0_NERR              BIT(2)       /*!< noise error flag */
+#define USART_STAT0_ORERR             BIT(3)       /*!< overrun error */
+#define USART_STAT0_IDLEF             BIT(4)       /*!< IDLE frame detected flag */
+#define USART_STAT0_RBNE              BIT(5)       /*!< read data buffer not empty */
+#define USART_STAT0_TC                BIT(6)       /*!< transmission complete */
+#define USART_STAT0_TBE               BIT(7)       /*!< transmit data buffer empty */
+#define USART_STAT0_LBDF              BIT(8)       /*!< LIN break detected flag */
+#define USART_STAT0_CTSF              BIT(9)       /*!< CTS change flag */
+
+/* USARTx_DATA */
+#define USART_DATA_DATA               BITS(0,8)    /*!< transmit or read data value */
+
+/* USARTx_BAUD */
+#define USART_BAUD_FRADIV             BITS(0,3)    /*!< fraction part of baud-rate divider */
+#define USART_BAUD_INTDIV             BITS(4,15)   /*!< integer part of baud-rate divider */
+
+/* USARTx_CTL0 */
+#define USART_CTL0_SBKCMD             BIT(0)       /*!< send break command */
+#define USART_CTL0_RWU                BIT(1)       /*!< receiver wakeup from mute mode */
+#define USART_CTL0_REN                BIT(2)       /*!< receiver enable */
+#define USART_CTL0_TEN                BIT(3)       /*!< transmitter enable */
+#define USART_CTL0_IDLEIE             BIT(4)       /*!< idle line detected interrupt enable */
+#define USART_CTL0_RBNEIE             BIT(5)       /*!< read data buffer not empty interrupt and overrun error interrupt enable */
+#define USART_CTL0_TCIE               BIT(6)       /*!< transmission complete interrupt enable */
+#define USART_CTL0_TBEIE              BIT(7)       /*!< transmitter buffer empty interrupt enable */
+#define USART_CTL0_PERRIE             BIT(8)       /*!< parity error interrupt enable */
+#define USART_CTL0_PM                 BIT(9)       /*!< parity mode */
+#define USART_CTL0_PCEN               BIT(10)      /*!< parity check function enable */
+#define USART_CTL0_WM                 BIT(11)      /*!< wakeup method in mute mode */
+#define USART_CTL0_WL                 BIT(12)      /*!< word length */
+#define USART_CTL0_UEN                BIT(13)      /*!< USART enable */
+
+/* USARTx_CTL1 */
+#define USART_CTL1_ADDR               BITS(0,3)    /*!< address of USART */
+#define USART_CTL1_LBLEN              BIT(5)       /*!< LIN break frame length */
+#define USART_CTL1_LBDIE              BIT(6)       /*!< LIN break detected interrupt eanble */
+#define USART_CTL1_CLEN               BIT(8)       /*!< CK length */
+#define USART_CTL1_CPH                BIT(9)       /*!< CK phase */
+#define USART_CTL1_CPL                BIT(10)      /*!< CK polarity */
+#define USART_CTL1_CKEN               BIT(11)      /*!< CK pin enable */
+#define USART_CTL1_STB                BITS(12,13)  /*!< STOP bits length */
+#define USART_CTL1_LMEN               BIT(14)      /*!< LIN mode enable */
+
+/* USARTx_CTL2 */
+#define USART_CTL2_ERRIE              BIT(0)       /*!< error interrupt enable */
+#define USART_CTL2_IREN               BIT(1)       /*!< IrDA mode enable */
+#define USART_CTL2_IRLP               BIT(2)       /*!< IrDA low-power */
+#define USART_CTL2_HDEN               BIT(3)       /*!< half-duplex enable */
+#define USART_CTL2_NKEN               BIT(4)       /*!< NACK enable in smartcard mode */
+#define USART_CTL2_SCEN               BIT(5)       /*!< smartcard mode enable */
+#define USART_CTL2_DENR               BIT(6)       /*!< DMA request enable for reception */
+#define USART_CTL2_DENT               BIT(7)       /*!< DMA request enable for transmission */
+#define USART_CTL2_RTSEN              BIT(8)       /*!< RTS enable */
+#define USART_CTL2_CTSEN              BIT(9)       /*!< CTS enable */
+#define USART_CTL2_CTSIE              BIT(10)      /*!< CTS interrupt enable */
+
+/* USARTx_GP */
+#define USART_GP_PSC                  BITS(0,7)    /*!< prescaler value for dividing the system clock */
+#define USART_GP_GUAT                 BITS(8,15)   /*!< guard time value in smartcard mode */
+ 
+/* USARTx_CTL3 */
+#define USART_CTL3_RTEN               BIT(0)       /*!< receiver timeout enable */
+#define USART_CTL3_SCRTNUM            BITS(1,3)    /*!< smartcard auto-retry number */
+#define USART_CTL3_RTIE               BIT(4)       /*!< interrupt enable bit of receive timeout event */
+#define USART_CTL3_EBIE               BIT(5)       /*!< interrupt enable bit of end of block event */
+#define USART_CTL3_RINV               BIT(8)       /*!< RX pin level inversion */
+#define USART_CTL3_TINV               BIT(9)       /*!< TX pin level inversion */
+#define USART_CTL3_DINV               BIT(10)      /*!< data bit level inversion */
+#define USART_CTL3_MSBF               BIT(11)      /*!< most significant bit first */
+
+/* USARTx_RT */
+#define USART_RT_RT                   BITS(0,23)   /*!< receiver timeout threshold */
+#define USART_RT_BL                   BITS(24,31)  /*!< block length */
+
+/* USARTx_STAT1 */
+#define USART_STAT1_RTF               BIT(11)      /*!< receiver timeout flag */
+#define USART_STAT1_EBF               BIT(12)      /*!< end of block flag */
+#define USART_STAT1_BSY               BIT(16)      /*!< busy flag */
+
+/* constants definitions */
+/* define the USART bit position and its register index offset */
+#define USART_REGIDX_BIT(regidx, bitpos)    (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
+#define USART_REG_VAL(usartx, offset)       (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
+#define USART_BIT_POS(val)                  ((uint32_t)(val) & 0x1FU)
+#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2)   (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
+                                                              | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
+#define USART_REG_VAL2(usartx, offset)       (REG32((usartx) + ((uint32_t)(offset) >> 22)))
+#define USART_BIT_POS2(val)                  (((uint32_t)(val) & 0x1F0000U) >> 16)
+
+/* register offset */
+#define USART_STAT0_REG_OFFSET              0x00U        /*!< STAT0 register offset */
+#define USART_STAT1_REG_OFFSET              0x88U        /*!< STAT1 register offset */
+#define USART_CTL0_REG_OFFSET               0x0CU        /*!< CTL0 register offset */
+#define USART_CTL1_REG_OFFSET               0x10U        /*!< CTL1 register offset */
+#define USART_CTL2_REG_OFFSET               0x14U        /*!< CTL2 register offset */
+#define USART_CTL3_REG_OFFSET               0x80U        /*!< CTL3 register offset */
+
+/* USART flags */
+typedef enum
+{
+    /* flags in STAT0 register */
+    USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U),       /*!< CTS change flag */
+    USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U),       /*!< LIN break detected flag */
+    USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U),       /*!< transmit data buffer empty */
+    USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U),        /*!< transmission complete */
+    USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U),      /*!< read data buffer not empty */
+    USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U),      /*!< IDLE frame detected flag */
+    USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U),     /*!< overrun error */
+    USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U),      /*!< noise error flag */
+    USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U),      /*!< frame error flag */
+    USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U),      /*!< parity error flag */
+    /* flags in STAT1 register */
+    USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U),      /*!< busy flag */
+    USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U),       /*!< end of block flag */
+    USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U),       /*!< receiver timeout flag */
+}usart_flag_enum;
+
+/* USART interrupt flags */
+typedef enum
+{
+    /* interrupt flags in CTL0 register */
+    USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U),       /*!< parity error interrupt and flag */
+    USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U),        /*!< transmitter buffer empty interrupt and flag */
+    USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U),         /*!< transmission complete interrupt and flag */
+    USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U),       /*!< read data buffer not empty interrupt and flag */
+    USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
+    USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U),       /*!< IDLE line detected interrupt and flag */
+    /* interrupt flags in CTL1 register */
+    USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U),        /*!< LIN break detected interrupt and flag */
+    /* interrupt flags in CTL2 register */
+    USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U),       /*!< CTS interrupt and flag */
+    USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U),  /*!< error interrupt and overrun error */
+    USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U),   /*!< error interrupt and noise error flag */
+    USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U),   /*!< error interrupt and frame error flag */
+    /* interrupt flags in CTL3 register */
+    USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U),        /*!< interrupt enable bit of end of block event and flag */
+    USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U),        /*!< interrupt enable bit of receive timeout event and flag */
+}usart_interrupt_flag_enum;
+
+/* USART interrupt enable or disable */
+typedef enum
+{
+    /* interrupt in CTL0 register */
+    USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U),        /*!< parity error interrupt */
+    USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U),         /*!< transmitter buffer empty interrupt */
+    USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U),          /*!< transmission complete interrupt */
+    USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U),        /*!< read data buffer not empty interrupt and overrun error interrupt */
+    USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U),        /*!< IDLE line detected interrupt */
+    /* interrupt in CTL1 register */
+    USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U),         /*!< LIN break detected interrupt */
+    /* interrupt in CTL2 register */
+    USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U),        /*!< CTS interrupt */
+    USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U),         /*!< error interrupt */
+    /* interrupt in CTL3 register */
+    USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U),          /*!< end of block interrupt */
+    USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U),          /*!< receive timeout interrupt */
+}usart_interrupt_enum;
+
+/* USART invert configure */
+typedef enum
+{
+    /* data bit level inversion */
+    USART_DINV_ENABLE,                             /*!< data bit level inversion */
+    USART_DINV_DISABLE,                            /*!< data bit level not inversion */
+    /* TX pin level inversion */
+    USART_TXPIN_ENABLE,                            /*!< TX pin level inversion */
+    USART_TXPIN_DISABLE,                           /*!< TX pin level not inversion */
+    /* RX pin level inversion */
+    USART_RXPIN_ENABLE,                            /*!< RX pin level inversion */
+    USART_RXPIN_DISABLE,                           /*!< RX pin level not inversion */
+}usart_invert_enum;
+
+/* USART receiver configure */
+#define CTL0_REN(regval)              (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_RECEIVE_ENABLE          CTL0_REN(1)                      /*!< enable receiver */
+#define USART_RECEIVE_DISABLE         CTL0_REN(0)                      /*!< disable receiver */
+
+/* USART transmitter configure */
+#define CTL0_TEN(regval)              (BIT(3) & ((uint32_t)(regval) << 3))
+#define USART_TRANSMIT_ENABLE         CTL0_TEN(1)                      /*!< enable transmitter */
+#define USART_TRANSMIT_DISABLE        CTL0_TEN(0)                      /*!< disable transmitter */
+
+/* USART parity bits definitions */
+#define CTL0_PM(regval)               (BITS(9,10) & ((uint32_t)(regval) << 9))
+#define USART_PM_NONE                 CTL0_PM(0)                       /*!< no parity */
+#define USART_PM_EVEN                 CTL0_PM(2)                       /*!< even parity */
+#define USART_PM_ODD                  CTL0_PM(3)                       /*!< odd parity */
+
+/* USART wakeup method in mute mode */
+#define CTL0_WM(regval)               (BIT(11) & ((uint32_t)(regval) << 11))
+#define USART_WM_IDLE                 CTL0_WM(0)                       /*!< idle line */
+#define USART_WM_ADDR                 CTL0_WM(1)                       /*!< address match */
+
+/* USART word length definitions */
+#define CTL0_WL(regval)               (BIT(12) & ((uint32_t)(regval) << 12))
+#define USART_WL_8BIT                 CTL0_WL(0)                       /*!< 8 bits */
+#define USART_WL_9BIT                 CTL0_WL(1)                       /*!< 9 bits */
+
+/* USART stop bits definitions */
+#define CTL1_STB(regval)              (BITS(12,13) & ((uint32_t)(regval) << 12))
+#define USART_STB_1BIT                CTL1_STB(0)                      /*!< 1 bit */
+#define USART_STB_0_5BIT              CTL1_STB(1)                      /*!< 0.5 bit */
+#define USART_STB_2BIT                CTL1_STB(2)                      /*!< 2 bits */
+#define USART_STB_1_5BIT              CTL1_STB(3)                      /*!< 1.5 bits */
+
+/* USART LIN break frame length */
+#define CTL1_LBLEN(regval)            (BIT(5) & ((uint32_t)(regval) << 5))
+#define USART_LBLEN_10B               CTL1_LBLEN(0)                    /*!< 10 bits */
+#define USART_LBLEN_11B               CTL1_LBLEN(1)                    /*!< 11 bits */
+
+/* USART CK length */
+#define CTL1_CLEN(regval)             (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_CLEN_NONE               CTL1_CLEN(0)                     /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
+#define USART_CLEN_EN                 CTL1_CLEN(1)                     /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
+
+/* USART clock phase */
+#define CTL1_CPH(regval)              (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CPH_1CK                 CTL1_CPH(0)                      /*!< first clock transition is the first data capture edge */
+#define USART_CPH_2CK                 CTL1_CPH(1)                      /*!< second clock transition is the first data capture edge */
+
+/* USART clock polarity */
+#define CTL1_CPL(regval)              (BIT(10) & ((uint32_t)(regval) << 10))
+#define USART_CPL_LOW                 CTL1_CPL(0)                      /*!< steady low value on CK pin */
+#define USART_CPL_HIGH                CTL1_CPL(1)                      /*!< steady high value on CK pin */
+
+/* USART DMA request for receive configure */
+#define CLT2_DENR(regval)             (BIT(6) & ((uint32_t)(regval) << 6))
+#define USART_DENR_ENABLE             CLT2_DENR(1)                     /*!< DMA request enable for reception */
+#define USART_DENR_DISABLE            CLT2_DENR(0)                     /*!< DMA request disable for reception */
+
+/* USART DMA request for transmission configure */
+#define CLT2_DENT(regval)             (BIT(7) & ((uint32_t)(regval) << 7))
+#define USART_DENT_ENABLE             CLT2_DENT(1)                     /*!< DMA request enable for transmission */
+#define USART_DENT_DISABLE            CLT2_DENT(0)                     /*!< DMA request disable for transmission */
+
+/* USART RTS configure */
+#define CLT2_RTSEN(regval)            (BIT(8) & ((uint32_t)(regval) << 8))
+#define USART_RTS_ENABLE              CLT2_RTSEN(1)                    /*!< RTS enable */
+#define USART_RTS_DISABLE             CLT2_RTSEN(0)                    /*!< RTS disable */
+
+/* USART CTS configure */
+#define CLT2_CTSEN(regval)            (BIT(9) & ((uint32_t)(regval) << 9))
+#define USART_CTS_ENABLE              CLT2_CTSEN(1)                    /*!< CTS enable */
+#define USART_CTS_DISABLE             CLT2_CTSEN(0)                    /*!< CTS disable */
+
+/* USART IrDA low-power enable */
+#define CTL2_IRLP(regval)             (BIT(2) & ((uint32_t)(regval) << 2))
+#define USART_IRLP_LOW                CTL2_IRLP(1)                     /*!< low-power */
+#define USART_IRLP_NORMAL             CTL2_IRLP(0)                     /*!< normal */
+
+/* USART data is transmitted/received with the LSB/MSB first */
+#define CTL3_MSBF(regval)             (BIT(11) & ((uint32_t)(regval) << 11))
+#define USART_MSBF_LSB                CTL3_MSBF(0)                     /*!< LSB first */
+#define USART_MSBF_MSB                CTL3_MSBF(1)                     /*!< MSB first */
+
+
+
+/* function declarations */
+/* initialization functions */
+/* reset USART */
+void usart_deinit(uint32_t usart_periph);
+/* configure USART baud rate value */
+void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
+/* configure USART parity function */
+void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
+/* configure USART word length */
+void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
+/* configure USART stop bit length */
+void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
+
+/* function configuration */
+/* USART normal mode communication */
+/* enable USART */
+void usart_enable(uint32_t usart_periph);
+/* disable USART */
+void usart_disable(uint32_t usart_periph);
+/* configure USART transmitter */
+void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
+/* configure USART receiver */
+void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
+/* data is transmitted/received with the LSB/MSB first */
+void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
+/* configure USART inverted */
+void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
+/* enable receiver timeout */
+void usart_receiver_timeout_enable(uint32_t usart_periph);
+/* disable receiver timeout */
+void usart_receiver_timeout_disable(uint32_t usart_periph);
+/* configure receiver timeout threshold */
+void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
+/* USART transmit data function */
+void usart_data_transmit(uint32_t usart_periph, uint16_t data);
+/* USART receive data function */
+uint16_t usart_data_receive(uint32_t usart_periph);
+
+/* multi-processor communication */
+/* configure address of the USART */
+void usart_address_config(uint32_t usart_periph, uint8_t addr);
+/* enable mute mode */
+void usart_mute_mode_enable(uint32_t usart_periph);
+/* disable mute mode */
+void usart_mute_mode_disable(uint32_t usart_periph);
+/* configure wakeup method in mute mode */
+void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
+
+/* LIN mode communication */
+/* LIN mode enable */
+void usart_lin_mode_enable(uint32_t usart_periph);
+/* LIN mode disable */
+void usart_lin_mode_disable(uint32_t usart_periph);
+/* LIN break detection length */
+void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
+/* send break frame */
+void usart_send_break(uint32_t usart_periph);
+
+/* half-duplex communication */
+/* half-duplex enable */
+void usart_halfduplex_enable(uint32_t usart_periph);
+/* half-duplex disable */
+void usart_halfduplex_disable(uint32_t usart_periph);
+
+/* synchronous communication */
+/* clock enable */
+void usart_synchronous_clock_enable(uint32_t usart_periph);
+/* clock disable */
+void usart_synchronous_clock_disable(uint32_t usart_periph);
+/* configure usart synchronous mode parameters */
+void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
+
+/* smartcard communication */
+/* guard time value configure in smartcard mode */
+void usart_guard_time_config(uint32_t usart_periph,uint32_t guat);
+/* smartcard mode enable */
+void usart_smartcard_mode_enable(uint32_t usart_periph);
+/* smartcard mode disable */
+void usart_smartcard_mode_disable(uint32_t usart_periph);
+/* NACK enable in smartcard mode */
+void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
+/* NACK disable in smartcard mode */
+void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
+/* smartcard auto-retry number configure */
+void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
+/* block length configure */
+void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
+
+/* IrDA communication */
+/* enable IrDA mode */
+void usart_irda_mode_enable(uint32_t usart_periph);
+/* disable IrDA mode */
+void usart_irda_mode_disable(uint32_t usart_periph);
+/* configure the peripheral clock prescaler */
+void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
+/* configure IrDA low-power */
+void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
+
+/* hardware flow communication */
+/* configure hardware flow control RTS */
+void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
+/* configure hardware flow control CTS */
+void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
+
+/* configure USART DMA for reception */
+void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
+/* configure USART DMA for transmission */
+void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
+
+/* interrupt & flag functions */
+/* get flag in STAT0/STAT1 register */
+FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
+/* clear flag in STAT0/STAT1 register */
+void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
+/* enable USART interrupt */
+void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag);
+/* disable USART interrupt */
+void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag);
+/* get USART interrupt and flag status */
+FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag);
+/* clear interrupt flag in STAT0/STAT1 register */
+void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag);
+
+#endif /* GD32F20X_USART_H */ 

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Include/gd32f20x_wwdgt.h

@@ -0,0 +1,92 @@
+/*!
+    \file  gd32f20x_wwdgt.h
+    \brief definitions for the WWDGT 
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F20X_WWDGT_H
+#define GD32F20X_WWDGT_H
+
+#include "gd32f20x.h"
+
+/* WWDGT definitions */
+#define WWDGT                       WWDGT_BASE                                /*!< WWDGT base address */
+
+/* registers definitions */
+#define WWDGT_CTL                   REG32((WWDGT) + 0x00U)                    /*!< WWDGT control register */
+#define WWDGT_CFG                   REG32((WWDGT) + 0x04U)                    /*!< WWDGT configuration register */
+#define WWDGT_STAT                  REG32((WWDGT) + 0x08U)                    /*!< WWDGT status register */
+
+/* bits definitions */
+/* WWDGT_CTL */
+#define WWDGT_CTL_CNT               BITS(0,6)                                 /*!< WWDGT counter value */
+#define WWDGT_CTL_WDGTEN            BIT(7)                                    /*!< WWDGT counter enable */
+
+/* WWDGT_CFG */
+#define WWDGT_CFG_WIN               BITS(0,6)                                 /*!< WWDGT counter window value */
+#define WWDGT_CFG_PSC               BITS(7,8)                                 /*!< WWDGT prescaler divider value */
+#define WWDGT_CFG_EWIE              BIT(9)                                    /*!< early wakeup interrupt enable */
+
+/* WWDGT_STAT */
+#define WWDGT_STAT_EWIF             BIT(0)                                    /*!< early wakeup interrupt flag */
+
+/* constants definitions */
+#define CFG_PSC(regval)             (BITS(7,8) & ((uint32_t)(regval) << 7))   /*!< write value to WWDGT_CFG_PSC bit field */
+#define WWDGT_CFG_PSC_DIV1          CFG_PSC(0)                                /*!< the time base of WWDGT = (PCLK1/4096)/1 */
+#define WWDGT_CFG_PSC_DIV2          CFG_PSC(1)                                /*!< the time base of WWDGT = (PCLK1/4096)/2 */
+#define WWDGT_CFG_PSC_DIV4          CFG_PSC(2)                                /*!< the time base of WWDGT = (PCLK1/4096)/4 */
+#define WWDGT_CFG_PSC_DIV8          CFG_PSC(3)                                /*!< the time base of WWDGT = (PCLK1/4096)/8 */
+
+/* function declarations */
+/* initialization functions */
+/* reset the window watchdog timer configuration */
+void wwdgt_deinit(void);
+/* start the window watchdog timer counter */
+void wwdgt_enable(void);
+
+/* configure the window watchdog timer counter value */
+void wwdgt_counter_update(uint16_t counter_value);
+/* configure counter value, window value, and prescaler divider value */
+void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
+
+/* interrupt & flag functions */
+/* enable early wakeup interrupt of WWDGT */
+void wwdgt_interrupt_enable(void);
+/* check early wakeup interrupt state of WWDGT */
+FlagStatus wwdgt_flag_get(void);
+/* clear early wakeup interrupt state of WWDGT */
+void wwdgt_flag_clear(void);
+
+#endif /* GD32F20X_WWDGT_H */

platform/vendor_bsp/gd/GD32F20x_Firmware_Library_V2.1.0/GD32F20x_standard_peripheral/Source/gd32f20x_bkp.c

@@ -0,0 +1,422 @@
+/*!
+    \file  gd32f20x_bkp.c
+    \brief BKP driver
+
+    \version 2015-07-15, V1.0.0, firmware for GD32F20x
+    \version 2017-06-05, V2.0.0, firmware for GD32F20x
+    \version 2018-10-31, V2.1.0, firmware for GD32F20x
+*/
+
+/*
+    Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without modification, 
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this 
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice, 
+       this list of conditions and the following disclaimer in the documentation 
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors 
+       may be used to endorse or promote products derived from this software without 
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+OF SUCH DAMAGE.
+*/
+
+#include "gd32f20x_bkp.h"
+
+#define TAMPER0_FLAG_SHIFT          ((uint8_t)8U)
+#define TAMPER1_FLAG_SHIFT          ((uint8_t)9U)
+
+/*!
+    \brief      reset BKP registers
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_deinit(void)
+{
+    /* reset BKP domain register*/
+    rcu_bkp_reset_enable();
+    rcu_bkp_reset_disable();
+}
+
+/*!
+    \brief      write BKP data register
+    \param[in]  register_number: refer to bkp_data_register_enum
+                only one parameter can be selected which is shown as below:
+      \arg        BKP_DATA_x(x = 0..41): bkp data register number x
+    \param[in]  data: the data to be write in BKP data register
+    \param[out] none
+    \retval     none
+*/
+void bkp_data_write(bkp_data_register_enum register_number, uint16_t data)
+{
+    if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
+        BKP_DATA10_41(register_number - 1U) = data;
+    }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
+        BKP_DATA0_9(register_number - 1U) = data;
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      read BKP data register
+    \param[in]  register_number: refer to bkp_data_register_enum
+                only one parameter can be selected which is shown as below:
+      \arg        BKP_DATA_x(x = 0..41): bkp data register number x
+    \param[out] none
+    \retval     data of BKP data register
+*/
+uint16_t bkp_data_read(bkp_data_register_enum register_number)
+{
+    uint16_t data = 0U;
+    
+    /* get the data from the BKP data register */
+    if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){
+        data = BKP_DATA10_41(register_number - 1U);
+    }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){
+        data = BKP_DATA0_9(register_number - 1U);
+    }else{
+        /* illegal parameters */
+    }
+    return data;
+}
+
+/*!
+    \brief      enable RTC clock calibration output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_calibration_output_enable(void)
+{
+    BKP_OCTL |= (uint16_t)BKP_OCTL_COEN;
+}
+
+/*!
+    \brief      disable RTC clock calibration output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_calibration_output_disable(void)
+{
+    BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN;
+}
+
+/*!
+    \brief      enable RTC alarm or second signal output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_signal_output_enable(void)
+{
+    BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN;
+}
+
+/*!
+    \brief      disable RTC alarm or second signal output
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_signal_output_disable(void)
+{
+    BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN;
+}
+
+/*!
+    \brief      select RTC output
+    \param[in]  outputsel: RTC output selection
+                only one parameter can be selected which is shown as below:
+      \arg        RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output
+      \arg        RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_output_select(uint16_t outputsel)
+{
+    uint16_t ctl = 0U;
+    
+    ctl = BKP_OCTL;
+    ctl &= (uint16_t)~BKP_OCTL_ROSEL;
+    ctl |= outputsel;
+    BKP_OCTL = ctl;
+}
+
+/*!
+    \brief      select RTC clock output
+    \param[in]  clocksel: RTC clock output selection
+      \arg        RTC_CLOCK_DIV64: RTC clock div 64
+      \arg        RTC_CLOCK_DIV1: RTC clock
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_clock_output_select(uint16_t clocksel)
+{
+    uint16_t ctl = 0U;
+    
+    ctl = BKP_OCTL;
+    ctl &= (uint16_t)~BKP_OCTL_CCOSEL;
+    ctl |= clocksel;
+    BKP_OCTL = ctl;
+}
+
+/*!
+    \brief      RTC clock calibration direction
+    \param[in]  direction: RTC clock calibration direction
+      \arg        RTC_CLOCK_SLOWED_DOWN: RTC clock slow down
+      \arg        RTC_CLOCK_SPEED_UP: RTC clock speed up
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_clock_calibration_direction(uint16_t direction)
+{
+    uint16_t ctl = 0U;
+    
+    ctl = BKP_OCTL;
+    ctl &= (uint16_t)~BKP_OCTL_CALDIR;
+    ctl |= direction;
+    BKP_OCTL = ctl;
+}
+
+/*!
+    \brief      set RTC clock calibration value 
+    \param[in]  value: RTC clock calibration value
+      \arg        0x00 - 0x7F
+    \param[out] none
+    \retval     none
+*/
+void bkp_rtc_calibration_value_set(uint8_t value)
+{
+    uint16_t ctl;
+    
+    /* configure BKP_OCTL_RCCV with value */
+    ctl = BKP_OCTL;
+    ctl &= (uint16_t)OCTL_RCCV(0);
+    ctl |= (uint16_t)OCTL_RCCV(value);
+    BKP_OCTL = ctl;
+}
+
+/*!
+    \brief      enable tamper detection
+    \param[in]  tamperx
+      \arg        TAMPER_0: BKP tamper0
+      \arg        TAMPER_1: BKP tamper1
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_detection_enable(bkp_tamper_enum tamperx)
+{
+    if(TAMPER_0 == tamperx){
+        BKP_TPCTL0 |= (uint16_t)BKP_TPCTL0_TPEN0;
+    }else{
+        BKP_TPCTL1 |= (uint16_t)BKP_TPCTL1_TPEN1;
+    }
+}
+
+/*!
+    \brief      disable tamper detection
+    \param[in]  tamperx
+      \arg        TAMPER_0: BKP tamper0
+      \arg        TAMPER_1: BKP tamper1
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_detection_disable(bkp_tamper_enum tamperx)
+{
+    if(TAMPER_0 == tamperx){
+        BKP_TPCTL0 &= (uint16_t)~BKP_TPCTL0_TPEN0;
+    }else{
+        BKP_TPCTL1 &= (uint16_t)~BKP_TPCTL1_TPEN1;
+    }
+}
+
+/*!
+    \brief      set tamper pin active level
+    \param[in]  tamperx
+      \arg        TAMPER_0: BKP tamper0
+      \arg        TAMPER_1: BKP tamper1
+    \param[in]  level: tamper active level
+      \arg        TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high
+      \arg        TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_active_level_set(bkp_tamper_enum tamperx, uint16_t level)
+{
+    uint16_t ctl = 0U;
+
+    if(TAMPER_0 == tamperx){
+        ctl = BKP_TPCTL0;
+        ctl &= (uint16_t)~BKP_TPCTL0_TPAL0;
+        ctl |= level;
+        BKP_TPCTL0 = ctl;
+    }else{
+        ctl = BKP_TPCTL1;
+        ctl &= (uint16_t)~BKP_TPCTL1_TPAL1;
+        ctl |= level;
+        BKP_TPCTL1 = ctl;
+    }
+}
+
+/*!
+    \brief      enable tamper interrupt
+    \param[in]  tamperx
+      \arg        TAMPER_0: BKP tamper0
+      \arg        TAMPER_1: BKP tamper1
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_interrupt_enable(bkp_tamper_enum tamperx)
+{
+    if(TAMPER_0 == tamperx){
+        BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE0;
+    }else{
+        BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE1;
+    }
+}
+
+/*!
+    \brief      disable tamper interrupt
+    \param[in]  tamperx
+      \arg        TAMPER_0: BKP tamper0
+      \arg        TAMPER_1: BKP tamper1
+    \param[out] none
+    \retval     none
+*/
+void bkp_tamper_interrupt_disable(bkp_tamper_enum tamperx)
+{
+    if(TAMPER_0 == tamperx){
+        BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE0;
+    }else{
+        BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE1;
+    }
+}
+
+/*!
+    \brief      waveform detect configure
+    \param[in]  waveform_detect_mode
+      \arg        BKP_WAVEFORM_DETECT_1: the first waveform detection
+      \arg        BKP_WAVEFORM_DETECT_2: the second waveform detection
+    \param[in]  newvalue: ENABLE or DISABLE
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+void bkp_waveform_detect_enable(uint16_t waveform_detect_mode, ControlStatus newvalue)
+{
+    uint16_t tpctl0 = 0U, tpctl1 = 0U, octl = 0U;
+    
+    tpctl0 = BKP_TPCTL0;
+    tpctl1 = BKP_TPCTL1;
+  
+    /* disable tamper0 and tamper1 */
+    tpctl0 &= (uint16_t)~BKP_TPCTL0_TPEN0;
+    tpctl1 &= (uint16_t)~BKP_TPCTL1_TPEN1;
+
+    octl = BKP_OCTL;
+
+    /* RTC clock output divided 64 */
+    octl &= (uint16_t)~BKP_OCTL_CCOSEL;
+
+    /* set the value to the register */
+    BKP_TPCTL0 = tpctl0;
+    BKP_TPCTL1 = tpctl1;
+    BKP_OCTL = octl;
+
+    if(DISABLE != newvalue){
+        /* enable the waveform detection function */
+        BKP_TPCTL1 |= waveform_detect_mode;
+    }else{
+        /* disable the waveform detection function */
+        BKP_TPCTL1 &= (uint16_t)(~waveform_detect_mode);
+    }
+}
+
+/*!
+    \brief      get bkp flag state
+    \param[in]  flag
+      \arg        BKP_FLAG_TAMPER0: tamper0 event flag
+      \arg        BKP_FLAG_TAMPER1_WAVEDETECT: tamper1/wavedetect event flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus bkp_flag_get(uint16_t flag)
+{
+    if(RESET != (BKP_TPCS & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear bkp flag state
+    \param[in]  flag
+      \arg        BKP_FLAG_TAMPER0: tamper0 event flag
+      \arg        BKP_FLAG_TAMPER1_WAVEDETECT: tamper1/wavedetect event flag
+    \param[out] none
+    \retval     none
+*/
+void bkp_flag_clear(uint16_t flag)
+{
+    if(BKP_FLAG_TAMPER0 == flag){
+        BKP_TPCS |= (uint16_t)(flag >> TAMPER0_FLAG_SHIFT);
+    }else if(BKP_FLAG_TAMPER1_WAVEDETECT == flag){
+        BKP_TPCS |= (uint16_t)(flag >> TAMPER1_FLAG_SHIFT);
+    }else{
+        /* illegal parameters */
+    }
+}
+
+/*!
+    \brief      get bkp interrupt flag state
+    \param[in]  flag
+      \arg        BKP_INT_FLAG_TAMPER0: tamper0 interrupt flag
+      \arg        BKP_INT_FLAG_TAMPER1_WAVEDETECT: tamper1/waveform detect interrupt flag
+    \param[out] none
+    \retval     FlagStatus: SET or RESET
+*/
+FlagStatus bkp_interrupt_flag_get(uint16_t flag)
+{
+    if(RESET != (BKP_TPCS & flag)){
+        return SET;
+    }else{
+        return RESET;
+    }
+}
+
+/*!
+    \brief      clear bkp interrupt flag state
+    \param[in]  flag
+      \arg        BKP_INT_FLAG_TAMPER0: tamper0 interrupt flag
+      \arg        BKP_INT_FLAG_TAMPER1_WAVEDETECT: tamper1/waveform detect interrupt flag
+    \param[out] none
+    \retval     none
+*/
+void bkp_interrupt_flag_clear(uint16_t flag)
+{
+    if(BKP_INT_FLAG_TAMPER0 == flag){
+        BKP_TPCS |= (uint16_t)(flag >> TAMPER0_FLAG_SHIFT);
+    }else if(BKP_INT_FLAG_TAMPER1_WAVEDETECT == flag){
+        BKP_TPCS |= (uint16_t)(flag >> TAMPER1_FLAG_SHIFT);
+    }else{
+        /* illegal parameters */
+    }
+}